2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/ptrace.h>
29 #include <linux/errno.h>
30 #include <linux/ioport.h>
31 #include <linux/slab.h>
32 #include <linux/interrupt.h>
33 #include <linux/delay.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/icmp.h>
44 #include <linux/spinlock.h>
45 #include <linux/workqueue.h>
46 #include <linux/bitops.h>
48 #include <linux/irq.h>
49 #include <linux/clk.h>
50 #include <linux/platform_device.h>
51 #include <linux/mdio.h>
52 #include <linux/phy.h>
53 #include <linux/fec.h>
55 #include <linux/of_device.h>
56 #include <linux/of_gpio.h>
57 #include <linux/of_mdio.h>
58 #include <linux/of_net.h>
59 #include <linux/regulator/consumer.h>
60 #include <linux/if_vlan.h>
61 #include <linux/pinctrl/consumer.h>
62 #include <linux/prefetch.h>
64 #include <asm/cacheflush.h>
68 static void set_multicast_list(struct net_device *ndev);
69 static void fec_enet_itr_coal_init(struct net_device *ndev);
71 #define DRIVER_NAME "fec"
73 #define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0))
75 /* Pause frame feild and FIFO threshold */
76 #define FEC_ENET_FCE (1 << 5)
77 #define FEC_ENET_RSEM_V 0x84
78 #define FEC_ENET_RSFL_V 16
79 #define FEC_ENET_RAEM_V 0x8
80 #define FEC_ENET_RAFL_V 0x8
81 #define FEC_ENET_OPD_V 0xFFF0
82 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */
84 static struct platform_device_id fec_devtype[] = {
86 /* keep it for coldfire */
91 .driver_data = FEC_QUIRK_USE_GASKET | FEC_QUIRK_HAS_RACC,
94 .driver_data = FEC_QUIRK_HAS_RACC,
97 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME |
98 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC,
101 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
102 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
103 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 |
106 .name = "mvf600-fec",
107 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC,
109 .name = "imx6sx-fec",
110 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
111 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
112 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
113 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
119 MODULE_DEVICE_TABLE(platform, fec_devtype);
122 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
123 IMX27_FEC, /* runs on i.mx27/35/51 */
130 static const struct of_device_id fec_dt_ids[] = {
131 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
132 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
133 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
134 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
135 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
136 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
139 MODULE_DEVICE_TABLE(of, fec_dt_ids);
141 static unsigned char macaddr[ETH_ALEN];
142 module_param_array(macaddr, byte, NULL, 0);
143 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
145 #if defined(CONFIG_M5272)
147 * Some hardware gets it MAC address out of local flash memory.
148 * if this is non-zero then assume it is the address to get MAC from.
150 #if defined(CONFIG_NETtel)
151 #define FEC_FLASHMAC 0xf0006006
152 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
153 #define FEC_FLASHMAC 0xf0006000
154 #elif defined(CONFIG_CANCam)
155 #define FEC_FLASHMAC 0xf0020000
156 #elif defined (CONFIG_M5272C3)
157 #define FEC_FLASHMAC (0xffe04000 + 4)
158 #elif defined(CONFIG_MOD5272)
159 #define FEC_FLASHMAC 0xffc0406b
161 #define FEC_FLASHMAC 0
163 #endif /* CONFIG_M5272 */
165 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
167 #define PKT_MAXBUF_SIZE 1522
168 #define PKT_MINBUF_SIZE 64
169 #define PKT_MAXBLR_SIZE 1536
171 /* FEC receive acceleration */
172 #define FEC_RACC_IPDIS (1 << 1)
173 #define FEC_RACC_PRODIS (1 << 2)
174 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
177 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
178 * size bits. Other FEC hardware does not, so we need to take that into
179 * account when setting it.
181 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
182 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
183 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
185 #define OPT_FRAME_SIZE 0
188 /* FEC MII MMFR bits definition */
189 #define FEC_MMFR_ST (1 << 30)
190 #define FEC_MMFR_OP_READ (2 << 28)
191 #define FEC_MMFR_OP_WRITE (1 << 28)
192 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
193 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
194 #define FEC_MMFR_TA (2 << 16)
195 #define FEC_MMFR_DATA(v) (v & 0xffff)
196 /* FEC ECR bits definition */
197 #define FEC_ECR_MAGICEN (1 << 2)
198 #define FEC_ECR_SLEEP (1 << 3)
200 #define FEC_MII_TIMEOUT 30000 /* us */
202 /* Transmitter timeout */
203 #define TX_TIMEOUT (2 * HZ)
205 #define FEC_PAUSE_FLAG_AUTONEG 0x1
206 #define FEC_PAUSE_FLAG_ENABLE 0x2
207 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0)
208 #define FEC_WOL_FLAG_ENABLE (0x1 << 1)
209 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2)
211 #define COPYBREAK_DEFAULT 256
213 #define TSO_HEADER_SIZE 128
214 /* Max number of allowed TCP segments for software TSO */
215 #define FEC_MAX_TSO_SEGS 100
216 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
218 #define IS_TSO_HEADER(txq, addr) \
219 ((addr >= txq->tso_hdrs_dma) && \
220 (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE))
225 struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp,
226 struct fec_enet_private *fep,
229 struct bufdesc *new_bd = bdp + 1;
230 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp + 1;
231 struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id];
232 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id];
233 struct bufdesc_ex *ex_base;
234 struct bufdesc *base;
237 if (bdp >= txq->tx_bd_base) {
238 base = txq->tx_bd_base;
239 ring_size = txq->tx_ring_size;
240 ex_base = (struct bufdesc_ex *)txq->tx_bd_base;
242 base = rxq->rx_bd_base;
243 ring_size = rxq->rx_ring_size;
244 ex_base = (struct bufdesc_ex *)rxq->rx_bd_base;
248 return (struct bufdesc *)((ex_new_bd >= (ex_base + ring_size)) ?
249 ex_base : ex_new_bd);
251 return (new_bd >= (base + ring_size)) ?
256 struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp,
257 struct fec_enet_private *fep,
260 struct bufdesc *new_bd = bdp - 1;
261 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp - 1;
262 struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id];
263 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id];
264 struct bufdesc_ex *ex_base;
265 struct bufdesc *base;
268 if (bdp >= txq->tx_bd_base) {
269 base = txq->tx_bd_base;
270 ring_size = txq->tx_ring_size;
271 ex_base = (struct bufdesc_ex *)txq->tx_bd_base;
273 base = rxq->rx_bd_base;
274 ring_size = rxq->rx_ring_size;
275 ex_base = (struct bufdesc_ex *)rxq->rx_bd_base;
279 return (struct bufdesc *)((ex_new_bd < ex_base) ?
280 (ex_new_bd + ring_size) : ex_new_bd);
282 return (new_bd < base) ? (new_bd + ring_size) : new_bd;
285 static int fec_enet_get_bd_index(struct bufdesc *base, struct bufdesc *bdp,
286 struct fec_enet_private *fep)
288 return ((const char *)bdp - (const char *)base) / fep->bufdesc_size;
291 static int fec_enet_get_free_txdesc_num(struct fec_enet_private *fep,
292 struct fec_enet_priv_tx_q *txq)
296 entries = ((const char *)txq->dirty_tx -
297 (const char *)txq->cur_tx) / fep->bufdesc_size - 1;
299 return entries > 0 ? entries : entries + txq->tx_ring_size;
302 static void swap_buffer(void *bufaddr, int len)
305 unsigned int *buf = bufaddr;
307 for (i = 0; i < len; i += 4, buf++)
311 static void swap_buffer2(void *dst_buf, void *src_buf, int len)
314 unsigned int *src = src_buf;
315 unsigned int *dst = dst_buf;
317 for (i = 0; i < len; i += 4, src++, dst++)
321 static void fec_dump(struct net_device *ndev)
323 struct fec_enet_private *fep = netdev_priv(ndev);
325 struct fec_enet_priv_tx_q *txq;
328 netdev_info(ndev, "TX ring dump\n");
329 pr_info("Nr SC addr len SKB\n");
331 txq = fep->tx_queue[0];
332 bdp = txq->tx_bd_base;
335 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n",
337 bdp == txq->cur_tx ? 'S' : ' ',
338 bdp == txq->dirty_tx ? 'H' : ' ',
339 fec16_to_cpu(bdp->cbd_sc),
340 fec32_to_cpu(bdp->cbd_bufaddr),
341 fec16_to_cpu(bdp->cbd_datlen),
342 txq->tx_skbuff[index]);
343 bdp = fec_enet_get_nextdesc(bdp, fep, 0);
345 } while (bdp != txq->tx_bd_base);
348 static inline bool is_ipv4_pkt(struct sk_buff *skb)
350 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
354 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
356 /* Only run for packets requiring a checksum. */
357 if (skb->ip_summed != CHECKSUM_PARTIAL)
360 if (unlikely(skb_cow_head(skb, 0)))
363 if (is_ipv4_pkt(skb))
364 ip_hdr(skb)->check = 0;
365 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
370 static struct bufdesc *
371 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq,
373 struct net_device *ndev)
375 struct fec_enet_private *fep = netdev_priv(ndev);
376 struct bufdesc *bdp = txq->cur_tx;
377 struct bufdesc_ex *ebdp;
378 int nr_frags = skb_shinfo(skb)->nr_frags;
379 unsigned short queue = skb_get_queue_mapping(skb);
381 unsigned short status;
382 unsigned int estatus = 0;
383 skb_frag_t *this_frag;
389 for (frag = 0; frag < nr_frags; frag++) {
390 this_frag = &skb_shinfo(skb)->frags[frag];
391 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
392 ebdp = (struct bufdesc_ex *)bdp;
394 status = fec16_to_cpu(bdp->cbd_sc);
395 status &= ~BD_ENET_TX_STATS;
396 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
397 frag_len = skb_shinfo(skb)->frags[frag].size;
399 /* Handle the last BD specially */
400 if (frag == nr_frags - 1) {
401 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
402 if (fep->bufdesc_ex) {
403 estatus |= BD_ENET_TX_INT;
404 if (unlikely(skb_shinfo(skb)->tx_flags &
405 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
406 estatus |= BD_ENET_TX_TS;
410 if (fep->bufdesc_ex) {
411 if (fep->quirks & FEC_QUIRK_HAS_AVB)
412 estatus |= FEC_TX_BD_FTYPE(queue);
413 if (skb->ip_summed == CHECKSUM_PARTIAL)
414 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
416 ebdp->cbd_esc = cpu_to_fec32(estatus);
419 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset;
421 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
422 if (((unsigned long) bufaddr) & fep->tx_align ||
423 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
424 memcpy(txq->tx_bounce[index], bufaddr, frag_len);
425 bufaddr = txq->tx_bounce[index];
427 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
428 swap_buffer(bufaddr, frag_len);
431 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
433 if (dma_mapping_error(&fep->pdev->dev, addr)) {
434 dev_kfree_skb_any(skb);
436 netdev_err(ndev, "Tx DMA memory map failed\n");
437 goto dma_mapping_error;
440 bdp->cbd_bufaddr = cpu_to_fec32(addr);
441 bdp->cbd_datlen = cpu_to_fec16(frag_len);
442 bdp->cbd_sc = cpu_to_fec16(status);
448 for (i = 0; i < frag; i++) {
449 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
450 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr),
451 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE);
453 return ERR_PTR(-ENOMEM);
456 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq,
457 struct sk_buff *skb, struct net_device *ndev)
459 struct fec_enet_private *fep = netdev_priv(ndev);
460 int nr_frags = skb_shinfo(skb)->nr_frags;
461 struct bufdesc *bdp, *last_bdp;
464 unsigned short status;
465 unsigned short buflen;
466 unsigned short queue;
467 unsigned int estatus = 0;
471 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
472 if (entries_free < MAX_SKB_FRAGS + 1) {
473 dev_kfree_skb_any(skb);
475 netdev_err(ndev, "NOT enough BD for SG!\n");
479 /* Protocol checksum off-load for TCP and UDP. */
480 if (fec_enet_clear_csum(skb, ndev)) {
481 dev_kfree_skb_any(skb);
485 /* Fill in a Tx ring entry */
488 status = fec16_to_cpu(bdp->cbd_sc);
489 status &= ~BD_ENET_TX_STATS;
491 /* Set buffer length and buffer pointer */
493 buflen = skb_headlen(skb);
495 queue = skb_get_queue_mapping(skb);
496 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
497 if (((unsigned long) bufaddr) & fep->tx_align ||
498 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
499 memcpy(txq->tx_bounce[index], skb->data, buflen);
500 bufaddr = txq->tx_bounce[index];
502 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
503 swap_buffer(bufaddr, buflen);
506 /* Push the data cache so the CPM does not get stale memory data. */
507 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
508 if (dma_mapping_error(&fep->pdev->dev, addr)) {
509 dev_kfree_skb_any(skb);
511 netdev_err(ndev, "Tx DMA memory map failed\n");
516 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev);
517 if (IS_ERR(last_bdp))
520 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
521 if (fep->bufdesc_ex) {
522 estatus = BD_ENET_TX_INT;
523 if (unlikely(skb_shinfo(skb)->tx_flags &
524 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
525 estatus |= BD_ENET_TX_TS;
529 if (fep->bufdesc_ex) {
531 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
533 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
535 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
537 if (fep->quirks & FEC_QUIRK_HAS_AVB)
538 estatus |= FEC_TX_BD_FTYPE(queue);
540 if (skb->ip_summed == CHECKSUM_PARTIAL)
541 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
544 ebdp->cbd_esc = cpu_to_fec32(estatus);
547 index = fec_enet_get_bd_index(txq->tx_bd_base, last_bdp, fep);
548 /* Save skb pointer */
549 txq->tx_skbuff[index] = skb;
551 bdp->cbd_datlen = cpu_to_fec16(buflen);
552 bdp->cbd_bufaddr = cpu_to_fec32(addr);
554 /* Send it on its way. Tell FEC it's ready, interrupt when done,
555 * it's the last BD of the frame, and to put the CRC on the end.
557 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
558 bdp->cbd_sc = cpu_to_fec16(status);
560 /* If this was the last BD in the ring, start at the beginning again. */
561 bdp = fec_enet_get_nextdesc(last_bdp, fep, queue);
563 skb_tx_timestamp(skb);
565 /* Make sure the update to bdp and tx_skbuff are performed before
571 /* Trigger transmission start */
572 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue));
578 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb,
579 struct net_device *ndev,
580 struct bufdesc *bdp, int index, char *data,
581 int size, bool last_tcp, bool is_last)
583 struct fec_enet_private *fep = netdev_priv(ndev);
584 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
585 unsigned short queue = skb_get_queue_mapping(skb);
586 unsigned short status;
587 unsigned int estatus = 0;
590 status = fec16_to_cpu(bdp->cbd_sc);
591 status &= ~BD_ENET_TX_STATS;
593 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
595 if (((unsigned long) data) & fep->tx_align ||
596 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
597 memcpy(txq->tx_bounce[index], data, size);
598 data = txq->tx_bounce[index];
600 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
601 swap_buffer(data, size);
604 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
605 if (dma_mapping_error(&fep->pdev->dev, addr)) {
606 dev_kfree_skb_any(skb);
608 netdev_err(ndev, "Tx DMA memory map failed\n");
609 return NETDEV_TX_BUSY;
612 bdp->cbd_datlen = cpu_to_fec16(size);
613 bdp->cbd_bufaddr = cpu_to_fec32(addr);
615 if (fep->bufdesc_ex) {
616 if (fep->quirks & FEC_QUIRK_HAS_AVB)
617 estatus |= FEC_TX_BD_FTYPE(queue);
618 if (skb->ip_summed == CHECKSUM_PARTIAL)
619 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
621 ebdp->cbd_esc = cpu_to_fec32(estatus);
624 /* Handle the last BD specially */
626 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
628 status |= BD_ENET_TX_INTR;
630 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT);
633 bdp->cbd_sc = cpu_to_fec16(status);
639 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq,
640 struct sk_buff *skb, struct net_device *ndev,
641 struct bufdesc *bdp, int index)
643 struct fec_enet_private *fep = netdev_priv(ndev);
644 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
645 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
646 unsigned short queue = skb_get_queue_mapping(skb);
648 unsigned long dmabuf;
649 unsigned short status;
650 unsigned int estatus = 0;
652 status = fec16_to_cpu(bdp->cbd_sc);
653 status &= ~BD_ENET_TX_STATS;
654 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
656 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
657 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE;
658 if (((unsigned long)bufaddr) & fep->tx_align ||
659 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
660 memcpy(txq->tx_bounce[index], skb->data, hdr_len);
661 bufaddr = txq->tx_bounce[index];
663 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
664 swap_buffer(bufaddr, hdr_len);
666 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
667 hdr_len, DMA_TO_DEVICE);
668 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
669 dev_kfree_skb_any(skb);
671 netdev_err(ndev, "Tx DMA memory map failed\n");
672 return NETDEV_TX_BUSY;
676 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf);
677 bdp->cbd_datlen = cpu_to_fec16(hdr_len);
679 if (fep->bufdesc_ex) {
680 if (fep->quirks & FEC_QUIRK_HAS_AVB)
681 estatus |= FEC_TX_BD_FTYPE(queue);
682 if (skb->ip_summed == CHECKSUM_PARTIAL)
683 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
685 ebdp->cbd_esc = cpu_to_fec32(estatus);
688 bdp->cbd_sc = cpu_to_fec16(status);
693 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq,
695 struct net_device *ndev)
697 struct fec_enet_private *fep = netdev_priv(ndev);
698 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
699 int total_len, data_left;
700 struct bufdesc *bdp = txq->cur_tx;
701 unsigned short queue = skb_get_queue_mapping(skb);
703 unsigned int index = 0;
706 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(fep, txq)) {
707 dev_kfree_skb_any(skb);
709 netdev_err(ndev, "NOT enough BD for TSO!\n");
713 /* Protocol checksum off-load for TCP and UDP. */
714 if (fec_enet_clear_csum(skb, ndev)) {
715 dev_kfree_skb_any(skb);
719 /* Initialize the TSO handler, and prepare the first payload */
720 tso_start(skb, &tso);
722 total_len = skb->len - hdr_len;
723 while (total_len > 0) {
726 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
727 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
728 total_len -= data_left;
730 /* prepare packet headers: MAC + IP + TCP */
731 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
732 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
733 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index);
737 while (data_left > 0) {
740 size = min_t(int, tso.size, data_left);
741 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
742 index = fec_enet_get_bd_index(txq->tx_bd_base,
744 ret = fec_enet_txq_put_data_tso(txq, skb, ndev,
753 tso_build_data(skb, &tso, size);
756 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
759 /* Save skb pointer */
760 txq->tx_skbuff[index] = skb;
762 skb_tx_timestamp(skb);
765 /* Trigger transmission start */
766 if (!(fep->quirks & FEC_QUIRK_ERR007885) ||
767 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
768 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
769 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
770 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)))
771 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue));
776 /* TODO: Release all used data descriptors for TSO */
781 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
783 struct fec_enet_private *fep = netdev_priv(ndev);
785 unsigned short queue;
786 struct fec_enet_priv_tx_q *txq;
787 struct netdev_queue *nq;
790 queue = skb_get_queue_mapping(skb);
791 txq = fep->tx_queue[queue];
792 nq = netdev_get_tx_queue(ndev, queue);
795 ret = fec_enet_txq_submit_tso(txq, skb, ndev);
797 ret = fec_enet_txq_submit_skb(txq, skb, ndev);
801 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
802 if (entries_free <= txq->tx_stop_threshold)
803 netif_tx_stop_queue(nq);
808 /* Init RX & TX buffer descriptors
810 static void fec_enet_bd_init(struct net_device *dev)
812 struct fec_enet_private *fep = netdev_priv(dev);
813 struct fec_enet_priv_tx_q *txq;
814 struct fec_enet_priv_rx_q *rxq;
819 for (q = 0; q < fep->num_rx_queues; q++) {
820 /* Initialize the receive buffer descriptors. */
821 rxq = fep->rx_queue[q];
822 bdp = rxq->rx_bd_base;
824 for (i = 0; i < rxq->rx_ring_size; i++) {
826 /* Initialize the BD for every fragment in the page. */
827 if (bdp->cbd_bufaddr)
828 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
830 bdp->cbd_sc = cpu_to_fec16(0);
831 bdp = fec_enet_get_nextdesc(bdp, fep, q);
834 /* Set the last buffer to wrap */
835 bdp = fec_enet_get_prevdesc(bdp, fep, q);
836 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
838 rxq->cur_rx = rxq->rx_bd_base;
841 for (q = 0; q < fep->num_tx_queues; q++) {
842 /* ...and the same for transmit */
843 txq = fep->tx_queue[q];
844 bdp = txq->tx_bd_base;
847 for (i = 0; i < txq->tx_ring_size; i++) {
848 /* Initialize the BD for every fragment in the page. */
849 bdp->cbd_sc = cpu_to_fec16(0);
850 if (txq->tx_skbuff[i]) {
851 dev_kfree_skb_any(txq->tx_skbuff[i]);
852 txq->tx_skbuff[i] = NULL;
854 bdp->cbd_bufaddr = cpu_to_fec32(0);
855 bdp = fec_enet_get_nextdesc(bdp, fep, q);
858 /* Set the last buffer to wrap */
859 bdp = fec_enet_get_prevdesc(bdp, fep, q);
860 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
865 static void fec_enet_active_rxring(struct net_device *ndev)
867 struct fec_enet_private *fep = netdev_priv(ndev);
870 for (i = 0; i < fep->num_rx_queues; i++)
871 writel(0, fep->hwp + FEC_R_DES_ACTIVE(i));
874 static void fec_enet_enable_ring(struct net_device *ndev)
876 struct fec_enet_private *fep = netdev_priv(ndev);
877 struct fec_enet_priv_tx_q *txq;
878 struct fec_enet_priv_rx_q *rxq;
881 for (i = 0; i < fep->num_rx_queues; i++) {
882 rxq = fep->rx_queue[i];
883 writel(rxq->bd_dma, fep->hwp + FEC_R_DES_START(i));
884 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i));
888 writel(RCMR_MATCHEN | RCMR_CMP(i),
889 fep->hwp + FEC_RCMR(i));
892 for (i = 0; i < fep->num_tx_queues; i++) {
893 txq = fep->tx_queue[i];
894 writel(txq->bd_dma, fep->hwp + FEC_X_DES_START(i));
898 writel(DMA_CLASS_EN | IDLE_SLOPE(i),
899 fep->hwp + FEC_DMA_CFG(i));
903 static void fec_enet_reset_skb(struct net_device *ndev)
905 struct fec_enet_private *fep = netdev_priv(ndev);
906 struct fec_enet_priv_tx_q *txq;
909 for (i = 0; i < fep->num_tx_queues; i++) {
910 txq = fep->tx_queue[i];
912 for (j = 0; j < txq->tx_ring_size; j++) {
913 if (txq->tx_skbuff[j]) {
914 dev_kfree_skb_any(txq->tx_skbuff[j]);
915 txq->tx_skbuff[j] = NULL;
922 * This function is called to start or restart the FEC during a link
923 * change, transmit timeout, or to reconfigure the FEC. The network
924 * packet processing for this device must be stopped before this call.
927 fec_restart(struct net_device *ndev)
929 struct fec_enet_private *fep = netdev_priv(ndev);
932 u32 rcntl = OPT_FRAME_SIZE | 0x04;
933 u32 ecntl = 0x2; /* ETHEREN */
935 /* Whack a reset. We should wait for this.
936 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
937 * instead of reset MAC itself.
939 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
940 writel(0, fep->hwp + FEC_ECNTRL);
942 writel(1, fep->hwp + FEC_ECNTRL);
947 * enet-mac reset will reset mac address registers too,
948 * so need to reconfigure it.
950 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
951 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
952 writel((__force u32)cpu_to_be32(temp_mac[0]),
953 fep->hwp + FEC_ADDR_LOW);
954 writel((__force u32)cpu_to_be32(temp_mac[1]),
955 fep->hwp + FEC_ADDR_HIGH);
958 /* Clear any outstanding interrupt. */
959 writel(0xffffffff, fep->hwp + FEC_IEVENT);
961 fec_enet_bd_init(ndev);
963 fec_enet_enable_ring(ndev);
965 /* Reset tx SKB buffers. */
966 fec_enet_reset_skb(ndev);
968 /* Enable MII mode */
969 if (fep->full_duplex == DUPLEX_FULL) {
971 writel(0x04, fep->hwp + FEC_X_CNTRL);
975 writel(0x0, fep->hwp + FEC_X_CNTRL);
979 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
981 #if !defined(CONFIG_M5272)
982 if (fep->quirks & FEC_QUIRK_HAS_RACC) {
983 /* set RX checksum */
984 val = readl(fep->hwp + FEC_RACC);
985 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
986 val |= FEC_RACC_OPTIONS;
988 val &= ~FEC_RACC_OPTIONS;
989 writel(val, fep->hwp + FEC_RACC);
994 * The phy interface and speed need to get configured
995 * differently on enet-mac.
997 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
998 /* Enable flow control and length check */
999 rcntl |= 0x40000000 | 0x00000020;
1001 /* RGMII, RMII or MII */
1002 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII ||
1003 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
1004 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
1005 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
1007 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1012 /* 1G, 100M or 10M */
1014 if (fep->phy_dev->speed == SPEED_1000)
1016 else if (fep->phy_dev->speed == SPEED_100)
1022 #ifdef FEC_MIIGSK_ENR
1023 if (fep->quirks & FEC_QUIRK_USE_GASKET) {
1025 /* disable the gasket and wait */
1026 writel(0, fep->hwp + FEC_MIIGSK_ENR);
1027 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
1031 * configure the gasket:
1032 * RMII, 50 MHz, no loopback, no echo
1033 * MII, 25 MHz, no loopback, no echo
1035 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1036 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
1037 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
1038 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
1039 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
1041 /* re-enable the gasket */
1042 writel(2, fep->hwp + FEC_MIIGSK_ENR);
1047 #if !defined(CONFIG_M5272)
1048 /* enable pause frame*/
1049 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
1050 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
1051 fep->phy_dev && fep->phy_dev->pause)) {
1052 rcntl |= FEC_ENET_FCE;
1054 /* set FIFO threshold parameter to reduce overrun */
1055 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
1056 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
1057 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
1058 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
1061 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
1063 rcntl &= ~FEC_ENET_FCE;
1065 #endif /* !defined(CONFIG_M5272) */
1067 writel(rcntl, fep->hwp + FEC_R_CNTRL);
1069 /* Setup multicast filter. */
1070 set_multicast_list(ndev);
1071 #ifndef CONFIG_M5272
1072 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1073 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1076 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
1077 /* enable ENET endian swap */
1079 /* enable ENET store and forward mode */
1080 writel(1 << 8, fep->hwp + FEC_X_WMRK);
1083 if (fep->bufdesc_ex)
1086 #ifndef CONFIG_M5272
1087 /* Enable the MIB statistic event counters */
1088 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
1091 /* And last, enable the transmit and receive processing */
1092 writel(ecntl, fep->hwp + FEC_ECNTRL);
1093 fec_enet_active_rxring(ndev);
1095 if (fep->bufdesc_ex)
1096 fec_ptp_start_cyclecounter(ndev);
1098 /* Enable interrupts we wish to service */
1100 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1102 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
1104 /* Init the interrupt coalescing */
1105 fec_enet_itr_coal_init(ndev);
1110 fec_stop(struct net_device *ndev)
1112 struct fec_enet_private *fep = netdev_priv(ndev);
1113 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
1114 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
1117 /* We cannot expect a graceful transmit stop without link !!! */
1119 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1121 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
1122 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
1125 /* Whack a reset. We should wait for this.
1126 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1127 * instead of reset MAC itself.
1129 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1130 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
1131 writel(0, fep->hwp + FEC_ECNTRL);
1133 writel(1, fep->hwp + FEC_ECNTRL);
1136 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1138 writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK);
1139 val = readl(fep->hwp + FEC_ECNTRL);
1140 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
1141 writel(val, fep->hwp + FEC_ECNTRL);
1143 if (pdata && pdata->sleep_mode_enable)
1144 pdata->sleep_mode_enable(true);
1146 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1148 /* We have to keep ENET enabled to have MII interrupt stay working */
1149 if (fep->quirks & FEC_QUIRK_ENET_MAC &&
1150 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1151 writel(2, fep->hwp + FEC_ECNTRL);
1152 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1158 fec_timeout(struct net_device *ndev)
1160 struct fec_enet_private *fep = netdev_priv(ndev);
1164 ndev->stats.tx_errors++;
1166 schedule_work(&fep->tx_timeout_work);
1169 static void fec_enet_timeout_work(struct work_struct *work)
1171 struct fec_enet_private *fep =
1172 container_of(work, struct fec_enet_private, tx_timeout_work);
1173 struct net_device *ndev = fep->netdev;
1176 if (netif_device_present(ndev) || netif_running(ndev)) {
1177 napi_disable(&fep->napi);
1178 netif_tx_lock_bh(ndev);
1180 netif_wake_queue(ndev);
1181 netif_tx_unlock_bh(ndev);
1182 napi_enable(&fep->napi);
1188 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts,
1189 struct skb_shared_hwtstamps *hwtstamps)
1191 unsigned long flags;
1194 spin_lock_irqsave(&fep->tmreg_lock, flags);
1195 ns = timecounter_cyc2time(&fep->tc, ts);
1196 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1198 memset(hwtstamps, 0, sizeof(*hwtstamps));
1199 hwtstamps->hwtstamp = ns_to_ktime(ns);
1203 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id)
1205 struct fec_enet_private *fep;
1206 struct bufdesc *bdp;
1207 unsigned short status;
1208 struct sk_buff *skb;
1209 struct fec_enet_priv_tx_q *txq;
1210 struct netdev_queue *nq;
1214 fep = netdev_priv(ndev);
1216 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1218 txq = fep->tx_queue[queue_id];
1219 /* get next bdp of dirty_tx */
1220 nq = netdev_get_tx_queue(ndev, queue_id);
1221 bdp = txq->dirty_tx;
1223 /* get next bdp of dirty_tx */
1224 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1226 while (bdp != READ_ONCE(txq->cur_tx)) {
1227 /* Order the load of cur_tx and cbd_sc */
1229 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc));
1230 if (status & BD_ENET_TX_READY)
1233 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
1235 skb = txq->tx_skbuff[index];
1236 txq->tx_skbuff[index] = NULL;
1237 if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
1238 dma_unmap_single(&fep->pdev->dev,
1239 fec32_to_cpu(bdp->cbd_bufaddr),
1240 fec16_to_cpu(bdp->cbd_datlen),
1242 bdp->cbd_bufaddr = cpu_to_fec32(0);
1244 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1248 /* Check for errors. */
1249 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1250 BD_ENET_TX_RL | BD_ENET_TX_UN |
1252 ndev->stats.tx_errors++;
1253 if (status & BD_ENET_TX_HB) /* No heartbeat */
1254 ndev->stats.tx_heartbeat_errors++;
1255 if (status & BD_ENET_TX_LC) /* Late collision */
1256 ndev->stats.tx_window_errors++;
1257 if (status & BD_ENET_TX_RL) /* Retrans limit */
1258 ndev->stats.tx_aborted_errors++;
1259 if (status & BD_ENET_TX_UN) /* Underrun */
1260 ndev->stats.tx_fifo_errors++;
1261 if (status & BD_ENET_TX_CSL) /* Carrier lost */
1262 ndev->stats.tx_carrier_errors++;
1264 ndev->stats.tx_packets++;
1265 ndev->stats.tx_bytes += skb->len;
1268 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
1270 struct skb_shared_hwtstamps shhwtstamps;
1271 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1273 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps);
1274 skb_tstamp_tx(skb, &shhwtstamps);
1277 /* Deferred means some collisions occurred during transmit,
1278 * but we eventually sent the packet OK.
1280 if (status & BD_ENET_TX_DEF)
1281 ndev->stats.collisions++;
1283 /* Free the sk buffer associated with this last transmit */
1284 dev_kfree_skb_any(skb);
1286 /* Make sure the update to bdp and tx_skbuff are performed
1290 txq->dirty_tx = bdp;
1292 /* Update pointer to next buffer descriptor to be transmitted */
1293 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1295 /* Since we have freed up a buffer, the ring is no longer full
1297 if (netif_queue_stopped(ndev)) {
1298 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
1299 if (entries_free >= txq->tx_wake_threshold)
1300 netif_tx_wake_queue(nq);
1304 /* ERR006538: Keep the transmitter going */
1305 if (bdp != txq->cur_tx &&
1306 readl(fep->hwp + FEC_X_DES_ACTIVE(queue_id)) == 0)
1307 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue_id));
1311 fec_enet_tx(struct net_device *ndev)
1313 struct fec_enet_private *fep = netdev_priv(ndev);
1315 /* First process class A queue, then Class B and Best Effort queue */
1316 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) {
1317 clear_bit(queue_id, &fep->work_tx);
1318 fec_enet_tx_queue(ndev, queue_id);
1324 fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb)
1326 struct fec_enet_private *fep = netdev_priv(ndev);
1329 off = ((unsigned long)skb->data) & fep->rx_align;
1331 skb_reserve(skb, fep->rx_align + 1 - off);
1333 bdp->cbd_bufaddr = cpu_to_fec32(dma_map_single(&fep->pdev->dev, skb->data, FEC_ENET_RX_FRSIZE - fep->rx_align, DMA_FROM_DEVICE));
1334 if (dma_mapping_error(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr))) {
1335 if (net_ratelimit())
1336 netdev_err(ndev, "Rx DMA memory map failed\n");
1343 static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb,
1344 struct bufdesc *bdp, u32 length, bool swap)
1346 struct fec_enet_private *fep = netdev_priv(ndev);
1347 struct sk_buff *new_skb;
1349 if (length > fep->rx_copybreak)
1352 new_skb = netdev_alloc_skb(ndev, length);
1356 dma_sync_single_for_cpu(&fep->pdev->dev,
1357 fec32_to_cpu(bdp->cbd_bufaddr),
1358 FEC_ENET_RX_FRSIZE - fep->rx_align,
1361 memcpy(new_skb->data, (*skb)->data, length);
1363 swap_buffer2(new_skb->data, (*skb)->data, length);
1369 /* During a receive, the cur_rx points to the current incoming buffer.
1370 * When we update through the ring, if the next incoming buffer has
1371 * not been given to the system, we just set the empty indicator,
1372 * effectively tossing the packet.
1375 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id)
1377 struct fec_enet_private *fep = netdev_priv(ndev);
1378 struct fec_enet_priv_rx_q *rxq;
1379 struct bufdesc *bdp;
1380 unsigned short status;
1381 struct sk_buff *skb_new = NULL;
1382 struct sk_buff *skb;
1385 int pkt_received = 0;
1386 struct bufdesc_ex *ebdp = NULL;
1387 bool vlan_packet_rcvd = false;
1391 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME;
1396 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1397 rxq = fep->rx_queue[queue_id];
1399 /* First, grab all of the stats for the incoming packet.
1400 * These get messed up if we get called due to a busy condition.
1404 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) {
1406 if (pkt_received >= budget)
1410 /* Since we have allocated space to hold a complete frame,
1411 * the last indicator should be set.
1413 if ((status & BD_ENET_RX_LAST) == 0)
1414 netdev_err(ndev, "rcv is not +last\n");
1416 writel(FEC_ENET_RXF, fep->hwp + FEC_IEVENT);
1418 /* Check for errors. */
1419 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1420 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
1421 ndev->stats.rx_errors++;
1422 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
1423 /* Frame too long or too short. */
1424 ndev->stats.rx_length_errors++;
1426 if (status & BD_ENET_RX_NO) /* Frame alignment */
1427 ndev->stats.rx_frame_errors++;
1428 if (status & BD_ENET_RX_CR) /* CRC Error */
1429 ndev->stats.rx_crc_errors++;
1430 if (status & BD_ENET_RX_OV) /* FIFO overrun */
1431 ndev->stats.rx_fifo_errors++;
1434 /* Report late collisions as a frame error.
1435 * On this error, the BD is closed, but we don't know what we
1436 * have in the buffer. So, just drop this frame on the floor.
1438 if (status & BD_ENET_RX_CL) {
1439 ndev->stats.rx_errors++;
1440 ndev->stats.rx_frame_errors++;
1441 goto rx_processing_done;
1444 /* Process the incoming frame. */
1445 ndev->stats.rx_packets++;
1446 pkt_len = fec16_to_cpu(bdp->cbd_datlen);
1447 ndev->stats.rx_bytes += pkt_len;
1449 index = fec_enet_get_bd_index(rxq->rx_bd_base, bdp, fep);
1450 skb = rxq->rx_skbuff[index];
1452 /* The packet length includes FCS, but we don't want to
1453 * include that when passing upstream as it messes up
1454 * bridging applications.
1456 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4,
1458 if (!is_copybreak) {
1459 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1460 if (unlikely(!skb_new)) {
1461 ndev->stats.rx_dropped++;
1462 goto rx_processing_done;
1464 dma_unmap_single(&fep->pdev->dev,
1465 fec32_to_cpu(bdp->cbd_bufaddr),
1466 FEC_ENET_RX_FRSIZE - fep->rx_align,
1470 prefetch(skb->data - NET_IP_ALIGN);
1471 skb_put(skb, pkt_len - 4);
1473 if (!is_copybreak && need_swap)
1474 swap_buffer(data, pkt_len);
1476 /* Extract the enhanced buffer descriptor */
1478 if (fep->bufdesc_ex)
1479 ebdp = (struct bufdesc_ex *)bdp;
1481 /* If this is a VLAN packet remove the VLAN Tag */
1482 vlan_packet_rcvd = false;
1483 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1485 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) {
1486 /* Push and remove the vlan tag */
1487 struct vlan_hdr *vlan_header =
1488 (struct vlan_hdr *) (data + ETH_HLEN);
1489 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
1491 vlan_packet_rcvd = true;
1493 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2);
1494 skb_pull(skb, VLAN_HLEN);
1497 skb->protocol = eth_type_trans(skb, ndev);
1499 /* Get receive timestamp from the skb */
1500 if (fep->hwts_rx_en && fep->bufdesc_ex)
1501 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts),
1502 skb_hwtstamps(skb));
1504 if (fep->bufdesc_ex &&
1505 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
1506 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) {
1507 /* don't check it */
1508 skb->ip_summed = CHECKSUM_UNNECESSARY;
1510 skb_checksum_none_assert(skb);
1514 /* Handle received VLAN packets */
1515 if (vlan_packet_rcvd)
1516 __vlan_hwaccel_put_tag(skb,
1520 napi_gro_receive(&fep->napi, skb);
1523 dma_sync_single_for_device(&fep->pdev->dev,
1524 fec32_to_cpu(bdp->cbd_bufaddr),
1525 FEC_ENET_RX_FRSIZE - fep->rx_align,
1528 rxq->rx_skbuff[index] = skb_new;
1529 fec_enet_new_rxbdp(ndev, bdp, skb_new);
1533 /* Clear the status flags for this buffer */
1534 status &= ~BD_ENET_RX_STATS;
1536 /* Mark the buffer empty */
1537 status |= BD_ENET_RX_EMPTY;
1538 bdp->cbd_sc = cpu_to_fec16(status);
1540 if (fep->bufdesc_ex) {
1541 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1543 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
1548 /* Update BD pointer to next entry */
1549 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1551 /* Doing this here will keep the FEC running while we process
1552 * incoming frames. On a heavily loaded network, we should be
1553 * able to keep up at the expense of system resources.
1555 writel(0, fep->hwp + FEC_R_DES_ACTIVE(queue_id));
1558 return pkt_received;
1562 fec_enet_rx(struct net_device *ndev, int budget)
1564 int pkt_received = 0;
1566 struct fec_enet_private *fep = netdev_priv(ndev);
1568 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) {
1569 clear_bit(queue_id, &fep->work_rx);
1570 pkt_received += fec_enet_rx_queue(ndev,
1571 budget - pkt_received, queue_id);
1573 return pkt_received;
1577 fec_enet_collect_events(struct fec_enet_private *fep, uint int_events)
1579 if (int_events == 0)
1582 if (int_events & FEC_ENET_RXF)
1583 fep->work_rx |= (1 << 2);
1584 if (int_events & FEC_ENET_RXF_1)
1585 fep->work_rx |= (1 << 0);
1586 if (int_events & FEC_ENET_RXF_2)
1587 fep->work_rx |= (1 << 1);
1589 if (int_events & FEC_ENET_TXF)
1590 fep->work_tx |= (1 << 2);
1591 if (int_events & FEC_ENET_TXF_1)
1592 fep->work_tx |= (1 << 0);
1593 if (int_events & FEC_ENET_TXF_2)
1594 fep->work_tx |= (1 << 1);
1600 fec_enet_interrupt(int irq, void *dev_id)
1602 struct net_device *ndev = dev_id;
1603 struct fec_enet_private *fep = netdev_priv(ndev);
1605 irqreturn_t ret = IRQ_NONE;
1607 int_events = readl(fep->hwp + FEC_IEVENT);
1608 writel(int_events, fep->hwp + FEC_IEVENT);
1609 fec_enet_collect_events(fep, int_events);
1611 if ((fep->work_tx || fep->work_rx) && fep->link) {
1614 if (napi_schedule_prep(&fep->napi)) {
1615 /* Disable the NAPI interrupts */
1616 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
1617 __napi_schedule(&fep->napi);
1621 if (int_events & FEC_ENET_MII) {
1623 complete(&fep->mdio_done);
1627 fec_ptp_check_pps_event(fep);
1632 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1634 struct net_device *ndev = napi->dev;
1635 struct fec_enet_private *fep = netdev_priv(ndev);
1638 pkts = fec_enet_rx(ndev, budget);
1642 if (pkts < budget) {
1643 napi_complete(napi);
1644 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1649 /* ------------------------------------------------------------------------- */
1650 static void fec_get_mac(struct net_device *ndev)
1652 struct fec_enet_private *fep = netdev_priv(ndev);
1653 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
1654 unsigned char *iap, tmpaddr[ETH_ALEN];
1657 * try to get mac address in following order:
1659 * 1) module parameter via kernel command line in form
1660 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1665 * 2) from device tree data
1667 if (!is_valid_ether_addr(iap)) {
1668 struct device_node *np = fep->pdev->dev.of_node;
1670 const char *mac = of_get_mac_address(np);
1672 iap = (unsigned char *) mac;
1677 * 3) from flash or fuse (via platform data)
1679 if (!is_valid_ether_addr(iap)) {
1682 iap = (unsigned char *)FEC_FLASHMAC;
1685 iap = (unsigned char *)&pdata->mac;
1690 * 4) FEC mac registers set by bootloader
1692 if (!is_valid_ether_addr(iap)) {
1693 *((__be32 *) &tmpaddr[0]) =
1694 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1695 *((__be16 *) &tmpaddr[4]) =
1696 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1701 * 5) random mac address
1703 if (!is_valid_ether_addr(iap)) {
1704 /* Report it and use a random ethernet address instead */
1705 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1706 eth_hw_addr_random(ndev);
1707 netdev_info(ndev, "Using random MAC address: %pM\n",
1712 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1714 /* Adjust MAC if using macaddr */
1716 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1719 /* ------------------------------------------------------------------------- */
1724 static void fec_enet_adjust_link(struct net_device *ndev)
1726 struct fec_enet_private *fep = netdev_priv(ndev);
1727 struct phy_device *phy_dev = fep->phy_dev;
1728 int status_change = 0;
1730 /* Prevent a state halted on mii error */
1731 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1732 phy_dev->state = PHY_RESUMING;
1737 * If the netdev is down, or is going down, we're not interested
1738 * in link state events, so just mark our idea of the link as down
1739 * and ignore the event.
1741 if (!netif_running(ndev) || !netif_device_present(ndev)) {
1743 } else if (phy_dev->link) {
1745 fep->link = phy_dev->link;
1749 if (fep->full_duplex != phy_dev->duplex) {
1750 fep->full_duplex = phy_dev->duplex;
1754 if (phy_dev->speed != fep->speed) {
1755 fep->speed = phy_dev->speed;
1759 /* if any of the above changed restart the FEC */
1760 if (status_change) {
1761 napi_disable(&fep->napi);
1762 netif_tx_lock_bh(ndev);
1764 netif_wake_queue(ndev);
1765 netif_tx_unlock_bh(ndev);
1766 napi_enable(&fep->napi);
1770 napi_disable(&fep->napi);
1771 netif_tx_lock_bh(ndev);
1773 netif_tx_unlock_bh(ndev);
1774 napi_enable(&fep->napi);
1775 fep->link = phy_dev->link;
1781 phy_print_status(phy_dev);
1784 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1786 struct fec_enet_private *fep = bus->priv;
1787 struct device *dev = &fep->pdev->dev;
1788 unsigned long time_left;
1791 ret = pm_runtime_get_sync(dev);
1795 fep->mii_timeout = 0;
1796 reinit_completion(&fep->mdio_done);
1798 /* start a read op */
1799 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1800 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1801 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1803 /* wait for end of transfer */
1804 time_left = wait_for_completion_timeout(&fep->mdio_done,
1805 usecs_to_jiffies(FEC_MII_TIMEOUT));
1806 if (time_left == 0) {
1807 fep->mii_timeout = 1;
1808 netdev_err(fep->netdev, "MDIO read timeout\n");
1813 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1816 pm_runtime_mark_last_busy(dev);
1817 pm_runtime_put_autosuspend(dev);
1822 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1825 struct fec_enet_private *fep = bus->priv;
1826 struct device *dev = &fep->pdev->dev;
1827 unsigned long time_left;
1830 ret = pm_runtime_get_sync(dev);
1836 fep->mii_timeout = 0;
1837 reinit_completion(&fep->mdio_done);
1839 /* start a write op */
1840 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1841 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1842 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1843 fep->hwp + FEC_MII_DATA);
1845 /* wait for end of transfer */
1846 time_left = wait_for_completion_timeout(&fep->mdio_done,
1847 usecs_to_jiffies(FEC_MII_TIMEOUT));
1848 if (time_left == 0) {
1849 fep->mii_timeout = 1;
1850 netdev_err(fep->netdev, "MDIO write timeout\n");
1854 pm_runtime_mark_last_busy(dev);
1855 pm_runtime_put_autosuspend(dev);
1860 static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
1862 struct fec_enet_private *fep = netdev_priv(ndev);
1866 ret = clk_prepare_enable(fep->clk_ahb);
1869 if (fep->clk_enet_out) {
1870 ret = clk_prepare_enable(fep->clk_enet_out);
1872 goto failed_clk_enet_out;
1875 mutex_lock(&fep->ptp_clk_mutex);
1876 ret = clk_prepare_enable(fep->clk_ptp);
1878 mutex_unlock(&fep->ptp_clk_mutex);
1879 goto failed_clk_ptp;
1881 fep->ptp_clk_on = true;
1883 mutex_unlock(&fep->ptp_clk_mutex);
1886 ret = clk_prepare_enable(fep->clk_ref);
1888 goto failed_clk_ref;
1891 clk_disable_unprepare(fep->clk_ahb);
1892 if (fep->clk_enet_out)
1893 clk_disable_unprepare(fep->clk_enet_out);
1895 mutex_lock(&fep->ptp_clk_mutex);
1896 clk_disable_unprepare(fep->clk_ptp);
1897 fep->ptp_clk_on = false;
1898 mutex_unlock(&fep->ptp_clk_mutex);
1901 clk_disable_unprepare(fep->clk_ref);
1908 clk_disable_unprepare(fep->clk_ref);
1910 if (fep->clk_enet_out)
1911 clk_disable_unprepare(fep->clk_enet_out);
1912 failed_clk_enet_out:
1913 clk_disable_unprepare(fep->clk_ahb);
1918 static int fec_enet_mii_probe(struct net_device *ndev)
1920 struct fec_enet_private *fep = netdev_priv(ndev);
1921 struct phy_device *phy_dev = NULL;
1922 char mdio_bus_id[MII_BUS_ID_SIZE];
1923 char phy_name[MII_BUS_ID_SIZE + 3];
1925 int dev_id = fep->dev_id;
1927 fep->phy_dev = NULL;
1929 if (fep->phy_node) {
1930 phy_dev = of_phy_connect(ndev, fep->phy_node,
1931 &fec_enet_adjust_link, 0,
1932 fep->phy_interface);
1936 /* check for attached phy */
1937 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1938 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id))
1942 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1946 if (phy_id >= PHY_MAX_ADDR) {
1947 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
1948 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1952 snprintf(phy_name, sizeof(phy_name),
1953 PHY_ID_FMT, mdio_bus_id, phy_id);
1954 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1955 fep->phy_interface);
1958 if (IS_ERR(phy_dev)) {
1959 netdev_err(ndev, "could not attach to PHY\n");
1960 return PTR_ERR(phy_dev);
1963 /* mask with MAC supported features */
1964 if (fep->quirks & FEC_QUIRK_HAS_GBIT) {
1965 phy_dev->supported &= PHY_GBIT_FEATURES;
1966 phy_dev->supported &= ~SUPPORTED_1000baseT_Half;
1967 #if !defined(CONFIG_M5272)
1968 phy_dev->supported |= SUPPORTED_Pause;
1972 phy_dev->supported &= PHY_BASIC_FEATURES;
1974 phy_dev->advertising = phy_dev->supported;
1976 fep->phy_dev = phy_dev;
1978 fep->full_duplex = 0;
1980 phy_attached_info(phy_dev);
1985 static int fec_enet_mii_init(struct platform_device *pdev)
1987 static struct mii_bus *fec0_mii_bus;
1988 struct net_device *ndev = platform_get_drvdata(pdev);
1989 struct fec_enet_private *fep = netdev_priv(ndev);
1990 struct device_node *node;
1992 u32 mii_speed, holdtime;
1995 * The i.MX28 dual fec interfaces are not equal.
1996 * Here are the differences:
1998 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1999 * - fec0 acts as the 1588 time master while fec1 is slave
2000 * - external phys can only be configured by fec0
2002 * That is to say fec1 can not work independently. It only works
2003 * when fec0 is working. The reason behind this design is that the
2004 * second interface is added primarily for Switch mode.
2006 * Because of the last point above, both phys are attached on fec0
2007 * mdio interface in board design, and need to be configured by
2010 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) {
2011 /* fec1 uses fec0 mii_bus */
2012 if (mii_cnt && fec0_mii_bus) {
2013 fep->mii_bus = fec0_mii_bus;
2020 fep->mii_timeout = 0;
2023 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
2025 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
2026 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
2027 * Reference Manual has an error on this, and gets fixed on i.MX6Q
2030 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000);
2031 if (fep->quirks & FEC_QUIRK_ENET_MAC)
2033 if (mii_speed > 63) {
2035 "fec clock (%lu) to fast to get right mii speed\n",
2036 clk_get_rate(fep->clk_ipg));
2042 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka
2043 * MII_SPEED) register that defines the MDIO output hold time. Earlier
2044 * versions are RAZ there, so just ignore the difference and write the
2046 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
2047 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
2049 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
2050 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
2051 * holdtime cannot result in a value greater than 3.
2053 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1;
2055 fep->phy_speed = mii_speed << 1 | holdtime << 8;
2057 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
2059 fep->mii_bus = mdiobus_alloc();
2060 if (fep->mii_bus == NULL) {
2065 fep->mii_bus->name = "fec_enet_mii_bus";
2066 fep->mii_bus->read = fec_enet_mdio_read;
2067 fep->mii_bus->write = fec_enet_mdio_write;
2068 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2069 pdev->name, fep->dev_id + 1);
2070 fep->mii_bus->priv = fep;
2071 fep->mii_bus->parent = &pdev->dev;
2073 node = of_get_child_by_name(pdev->dev.of_node, "mdio");
2075 err = of_mdiobus_register(fep->mii_bus, node);
2078 err = mdiobus_register(fep->mii_bus);
2082 goto err_out_free_mdiobus;
2086 /* save fec0 mii_bus */
2087 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO)
2088 fec0_mii_bus = fep->mii_bus;
2092 err_out_free_mdiobus:
2093 mdiobus_free(fep->mii_bus);
2098 static void fec_enet_mii_remove(struct fec_enet_private *fep)
2100 if (--mii_cnt == 0) {
2101 mdiobus_unregister(fep->mii_bus);
2102 mdiobus_free(fep->mii_bus);
2106 static int fec_enet_get_settings(struct net_device *ndev,
2107 struct ethtool_cmd *cmd)
2109 struct fec_enet_private *fep = netdev_priv(ndev);
2110 struct phy_device *phydev = fep->phy_dev;
2115 return phy_ethtool_gset(phydev, cmd);
2118 static int fec_enet_set_settings(struct net_device *ndev,
2119 struct ethtool_cmd *cmd)
2121 struct fec_enet_private *fep = netdev_priv(ndev);
2122 struct phy_device *phydev = fep->phy_dev;
2127 return phy_ethtool_sset(phydev, cmd);
2130 static void fec_enet_get_drvinfo(struct net_device *ndev,
2131 struct ethtool_drvinfo *info)
2133 struct fec_enet_private *fep = netdev_priv(ndev);
2135 strlcpy(info->driver, fep->pdev->dev.driver->name,
2136 sizeof(info->driver));
2137 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
2138 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
2141 static int fec_enet_get_regs_len(struct net_device *ndev)
2143 struct fec_enet_private *fep = netdev_priv(ndev);
2147 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0);
2149 s = resource_size(r);
2154 /* List of registers that can be safety be read to dump them with ethtool */
2155 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
2156 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
2157 static u32 fec_enet_register_offset[] = {
2158 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0,
2159 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL,
2160 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1,
2161 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH,
2162 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW,
2163 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1,
2164 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2,
2165 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0,
2166 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM,
2167 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2,
2168 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1,
2169 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME,
2170 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT,
2171 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG,
2172 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255,
2173 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047,
2174 RMON_T_P_GTE2048, RMON_T_OCTETS,
2175 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF,
2176 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE,
2177 IEEE_T_FDXFC, IEEE_T_OCTETS_OK,
2178 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN,
2179 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB,
2180 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255,
2181 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047,
2182 RMON_R_P_GTE2048, RMON_R_OCTETS,
2183 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR,
2184 IEEE_R_FDXFC, IEEE_R_OCTETS_OK
2187 static u32 fec_enet_register_offset[] = {
2188 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0,
2189 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0,
2190 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED,
2191 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL,
2192 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH,
2193 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0,
2194 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0,
2195 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0,
2196 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2
2200 static void fec_enet_get_regs(struct net_device *ndev,
2201 struct ethtool_regs *regs, void *regbuf)
2203 struct fec_enet_private *fep = netdev_priv(ndev);
2204 u32 __iomem *theregs = (u32 __iomem *)fep->hwp;
2205 u32 *buf = (u32 *)regbuf;
2208 memset(buf, 0, regs->len);
2210 for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) {
2211 off = fec_enet_register_offset[i] / 4;
2212 buf[off] = readl(&theregs[off]);
2216 static int fec_enet_get_ts_info(struct net_device *ndev,
2217 struct ethtool_ts_info *info)
2219 struct fec_enet_private *fep = netdev_priv(ndev);
2221 if (fep->bufdesc_ex) {
2223 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2224 SOF_TIMESTAMPING_RX_SOFTWARE |
2225 SOF_TIMESTAMPING_SOFTWARE |
2226 SOF_TIMESTAMPING_TX_HARDWARE |
2227 SOF_TIMESTAMPING_RX_HARDWARE |
2228 SOF_TIMESTAMPING_RAW_HARDWARE;
2230 info->phc_index = ptp_clock_index(fep->ptp_clock);
2232 info->phc_index = -1;
2234 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
2235 (1 << HWTSTAMP_TX_ON);
2237 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
2238 (1 << HWTSTAMP_FILTER_ALL);
2241 return ethtool_op_get_ts_info(ndev, info);
2245 #if !defined(CONFIG_M5272)
2247 static void fec_enet_get_pauseparam(struct net_device *ndev,
2248 struct ethtool_pauseparam *pause)
2250 struct fec_enet_private *fep = netdev_priv(ndev);
2252 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
2253 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
2254 pause->rx_pause = pause->tx_pause;
2257 static int fec_enet_set_pauseparam(struct net_device *ndev,
2258 struct ethtool_pauseparam *pause)
2260 struct fec_enet_private *fep = netdev_priv(ndev);
2265 if (pause->tx_pause != pause->rx_pause) {
2267 "hardware only support enable/disable both tx and rx");
2271 fep->pause_flag = 0;
2273 /* tx pause must be same as rx pause */
2274 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
2275 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
2277 if (pause->rx_pause || pause->autoneg) {
2278 fep->phy_dev->supported |= ADVERTISED_Pause;
2279 fep->phy_dev->advertising |= ADVERTISED_Pause;
2281 fep->phy_dev->supported &= ~ADVERTISED_Pause;
2282 fep->phy_dev->advertising &= ~ADVERTISED_Pause;
2285 if (pause->autoneg) {
2286 if (netif_running(ndev))
2288 phy_start_aneg(fep->phy_dev);
2290 if (netif_running(ndev)) {
2291 napi_disable(&fep->napi);
2292 netif_tx_lock_bh(ndev);
2294 netif_wake_queue(ndev);
2295 netif_tx_unlock_bh(ndev);
2296 napi_enable(&fep->napi);
2302 static const struct fec_stat {
2303 char name[ETH_GSTRING_LEN];
2307 { "tx_dropped", RMON_T_DROP },
2308 { "tx_packets", RMON_T_PACKETS },
2309 { "tx_broadcast", RMON_T_BC_PKT },
2310 { "tx_multicast", RMON_T_MC_PKT },
2311 { "tx_crc_errors", RMON_T_CRC_ALIGN },
2312 { "tx_undersize", RMON_T_UNDERSIZE },
2313 { "tx_oversize", RMON_T_OVERSIZE },
2314 { "tx_fragment", RMON_T_FRAG },
2315 { "tx_jabber", RMON_T_JAB },
2316 { "tx_collision", RMON_T_COL },
2317 { "tx_64byte", RMON_T_P64 },
2318 { "tx_65to127byte", RMON_T_P65TO127 },
2319 { "tx_128to255byte", RMON_T_P128TO255 },
2320 { "tx_256to511byte", RMON_T_P256TO511 },
2321 { "tx_512to1023byte", RMON_T_P512TO1023 },
2322 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
2323 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
2324 { "tx_octets", RMON_T_OCTETS },
2327 { "IEEE_tx_drop", IEEE_T_DROP },
2328 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
2329 { "IEEE_tx_1col", IEEE_T_1COL },
2330 { "IEEE_tx_mcol", IEEE_T_MCOL },
2331 { "IEEE_tx_def", IEEE_T_DEF },
2332 { "IEEE_tx_lcol", IEEE_T_LCOL },
2333 { "IEEE_tx_excol", IEEE_T_EXCOL },
2334 { "IEEE_tx_macerr", IEEE_T_MACERR },
2335 { "IEEE_tx_cserr", IEEE_T_CSERR },
2336 { "IEEE_tx_sqe", IEEE_T_SQE },
2337 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
2338 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
2341 { "rx_packets", RMON_R_PACKETS },
2342 { "rx_broadcast", RMON_R_BC_PKT },
2343 { "rx_multicast", RMON_R_MC_PKT },
2344 { "rx_crc_errors", RMON_R_CRC_ALIGN },
2345 { "rx_undersize", RMON_R_UNDERSIZE },
2346 { "rx_oversize", RMON_R_OVERSIZE },
2347 { "rx_fragment", RMON_R_FRAG },
2348 { "rx_jabber", RMON_R_JAB },
2349 { "rx_64byte", RMON_R_P64 },
2350 { "rx_65to127byte", RMON_R_P65TO127 },
2351 { "rx_128to255byte", RMON_R_P128TO255 },
2352 { "rx_256to511byte", RMON_R_P256TO511 },
2353 { "rx_512to1023byte", RMON_R_P512TO1023 },
2354 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
2355 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
2356 { "rx_octets", RMON_R_OCTETS },
2359 { "IEEE_rx_drop", IEEE_R_DROP },
2360 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
2361 { "IEEE_rx_crc", IEEE_R_CRC },
2362 { "IEEE_rx_align", IEEE_R_ALIGN },
2363 { "IEEE_rx_macerr", IEEE_R_MACERR },
2364 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
2365 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
2368 static void fec_enet_get_ethtool_stats(struct net_device *dev,
2369 struct ethtool_stats *stats, u64 *data)
2371 struct fec_enet_private *fep = netdev_priv(dev);
2374 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2375 data[i] = readl(fep->hwp + fec_stats[i].offset);
2378 static void fec_enet_get_strings(struct net_device *netdev,
2379 u32 stringset, u8 *data)
2382 switch (stringset) {
2384 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2385 memcpy(data + i * ETH_GSTRING_LEN,
2386 fec_stats[i].name, ETH_GSTRING_LEN);
2391 static int fec_enet_get_sset_count(struct net_device *dev, int sset)
2395 return ARRAY_SIZE(fec_stats);
2400 #endif /* !defined(CONFIG_M5272) */
2402 static int fec_enet_nway_reset(struct net_device *dev)
2404 struct fec_enet_private *fep = netdev_priv(dev);
2405 struct phy_device *phydev = fep->phy_dev;
2410 return genphy_restart_aneg(phydev);
2413 /* ITR clock source is enet system clock (clk_ahb).
2414 * TCTT unit is cycle_ns * 64 cycle
2415 * So, the ICTT value = X us / (cycle_ns * 64)
2417 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us)
2419 struct fec_enet_private *fep = netdev_priv(ndev);
2421 return us * (fep->itr_clk_rate / 64000) / 1000;
2424 /* Set threshold for interrupt coalescing */
2425 static void fec_enet_itr_coal_set(struct net_device *ndev)
2427 struct fec_enet_private *fep = netdev_priv(ndev);
2430 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
2433 /* Must be greater than zero to avoid unpredictable behavior */
2434 if (!fep->rx_time_itr || !fep->rx_pkts_itr ||
2435 !fep->tx_time_itr || !fep->tx_pkts_itr)
2438 /* Select enet system clock as Interrupt Coalescing
2439 * timer Clock Source
2441 rx_itr = FEC_ITR_CLK_SEL;
2442 tx_itr = FEC_ITR_CLK_SEL;
2444 /* set ICFT and ICTT */
2445 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr);
2446 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr));
2447 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr);
2448 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr));
2450 rx_itr |= FEC_ITR_EN;
2451 tx_itr |= FEC_ITR_EN;
2453 writel(tx_itr, fep->hwp + FEC_TXIC0);
2454 writel(rx_itr, fep->hwp + FEC_RXIC0);
2455 writel(tx_itr, fep->hwp + FEC_TXIC1);
2456 writel(rx_itr, fep->hwp + FEC_RXIC1);
2457 writel(tx_itr, fep->hwp + FEC_TXIC2);
2458 writel(rx_itr, fep->hwp + FEC_RXIC2);
2462 fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2464 struct fec_enet_private *fep = netdev_priv(ndev);
2466 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
2469 ec->rx_coalesce_usecs = fep->rx_time_itr;
2470 ec->rx_max_coalesced_frames = fep->rx_pkts_itr;
2472 ec->tx_coalesce_usecs = fep->tx_time_itr;
2473 ec->tx_max_coalesced_frames = fep->tx_pkts_itr;
2479 fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2481 struct fec_enet_private *fep = netdev_priv(ndev);
2484 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
2487 if (ec->rx_max_coalesced_frames > 255) {
2488 pr_err("Rx coalesced frames exceed hardware limiation");
2492 if (ec->tx_max_coalesced_frames > 255) {
2493 pr_err("Tx coalesced frame exceed hardware limiation");
2497 cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr);
2498 if (cycle > 0xFFFF) {
2499 pr_err("Rx coalesed usec exceeed hardware limiation");
2503 cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr);
2504 if (cycle > 0xFFFF) {
2505 pr_err("Rx coalesed usec exceeed hardware limiation");
2509 fep->rx_time_itr = ec->rx_coalesce_usecs;
2510 fep->rx_pkts_itr = ec->rx_max_coalesced_frames;
2512 fep->tx_time_itr = ec->tx_coalesce_usecs;
2513 fep->tx_pkts_itr = ec->tx_max_coalesced_frames;
2515 fec_enet_itr_coal_set(ndev);
2520 static void fec_enet_itr_coal_init(struct net_device *ndev)
2522 struct ethtool_coalesce ec;
2524 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2525 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2527 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2528 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2530 fec_enet_set_coalesce(ndev, &ec);
2533 static int fec_enet_get_tunable(struct net_device *netdev,
2534 const struct ethtool_tunable *tuna,
2537 struct fec_enet_private *fep = netdev_priv(netdev);
2541 case ETHTOOL_RX_COPYBREAK:
2542 *(u32 *)data = fep->rx_copybreak;
2552 static int fec_enet_set_tunable(struct net_device *netdev,
2553 const struct ethtool_tunable *tuna,
2556 struct fec_enet_private *fep = netdev_priv(netdev);
2560 case ETHTOOL_RX_COPYBREAK:
2561 fep->rx_copybreak = *(u32 *)data;
2572 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2574 struct fec_enet_private *fep = netdev_priv(ndev);
2576 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) {
2577 wol->supported = WAKE_MAGIC;
2578 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0;
2580 wol->supported = wol->wolopts = 0;
2585 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2587 struct fec_enet_private *fep = netdev_priv(ndev);
2589 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET))
2592 if (wol->wolopts & ~WAKE_MAGIC)
2595 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC);
2596 if (device_may_wakeup(&ndev->dev)) {
2597 fep->wol_flag |= FEC_WOL_FLAG_ENABLE;
2598 if (fep->irq[0] > 0)
2599 enable_irq_wake(fep->irq[0]);
2601 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE);
2602 if (fep->irq[0] > 0)
2603 disable_irq_wake(fep->irq[0]);
2609 static const struct ethtool_ops fec_enet_ethtool_ops = {
2610 .get_settings = fec_enet_get_settings,
2611 .set_settings = fec_enet_set_settings,
2612 .get_drvinfo = fec_enet_get_drvinfo,
2613 .get_regs_len = fec_enet_get_regs_len,
2614 .get_regs = fec_enet_get_regs,
2615 .nway_reset = fec_enet_nway_reset,
2616 .get_link = ethtool_op_get_link,
2617 .get_coalesce = fec_enet_get_coalesce,
2618 .set_coalesce = fec_enet_set_coalesce,
2619 #ifndef CONFIG_M5272
2620 .get_pauseparam = fec_enet_get_pauseparam,
2621 .set_pauseparam = fec_enet_set_pauseparam,
2622 .get_strings = fec_enet_get_strings,
2623 .get_ethtool_stats = fec_enet_get_ethtool_stats,
2624 .get_sset_count = fec_enet_get_sset_count,
2626 .get_ts_info = fec_enet_get_ts_info,
2627 .get_tunable = fec_enet_get_tunable,
2628 .set_tunable = fec_enet_set_tunable,
2629 .get_wol = fec_enet_get_wol,
2630 .set_wol = fec_enet_set_wol,
2633 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2635 struct fec_enet_private *fep = netdev_priv(ndev);
2636 struct phy_device *phydev = fep->phy_dev;
2638 if (!netif_running(ndev))
2644 if (fep->bufdesc_ex) {
2645 if (cmd == SIOCSHWTSTAMP)
2646 return fec_ptp_set(ndev, rq);
2647 if (cmd == SIOCGHWTSTAMP)
2648 return fec_ptp_get(ndev, rq);
2651 return phy_mii_ioctl(phydev, rq, cmd);
2654 static void fec_enet_free_buffers(struct net_device *ndev)
2656 struct fec_enet_private *fep = netdev_priv(ndev);
2658 struct sk_buff *skb;
2659 struct bufdesc *bdp;
2660 struct fec_enet_priv_tx_q *txq;
2661 struct fec_enet_priv_rx_q *rxq;
2664 for (q = 0; q < fep->num_rx_queues; q++) {
2665 rxq = fep->rx_queue[q];
2666 bdp = rxq->rx_bd_base;
2667 for (i = 0; i < rxq->rx_ring_size; i++) {
2668 skb = rxq->rx_skbuff[i];
2669 rxq->rx_skbuff[i] = NULL;
2671 dma_unmap_single(&fep->pdev->dev,
2672 fec32_to_cpu(bdp->cbd_bufaddr),
2673 FEC_ENET_RX_FRSIZE - fep->rx_align,
2677 bdp = fec_enet_get_nextdesc(bdp, fep, q);
2681 for (q = 0; q < fep->num_tx_queues; q++) {
2682 txq = fep->tx_queue[q];
2683 bdp = txq->tx_bd_base;
2684 for (i = 0; i < txq->tx_ring_size; i++) {
2685 kfree(txq->tx_bounce[i]);
2686 txq->tx_bounce[i] = NULL;
2687 skb = txq->tx_skbuff[i];
2688 txq->tx_skbuff[i] = NULL;
2694 static void fec_enet_free_queue(struct net_device *ndev)
2696 struct fec_enet_private *fep = netdev_priv(ndev);
2698 struct fec_enet_priv_tx_q *txq;
2700 for (i = 0; i < fep->num_tx_queues; i++)
2701 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) {
2702 txq = fep->tx_queue[i];
2703 dma_free_coherent(NULL,
2704 txq->tx_ring_size * TSO_HEADER_SIZE,
2709 for (i = 0; i < fep->num_rx_queues; i++)
2710 kfree(fep->rx_queue[i]);
2711 for (i = 0; i < fep->num_tx_queues; i++)
2712 kfree(fep->tx_queue[i]);
2715 static int fec_enet_alloc_queue(struct net_device *ndev)
2717 struct fec_enet_private *fep = netdev_priv(ndev);
2720 struct fec_enet_priv_tx_q *txq;
2722 for (i = 0; i < fep->num_tx_queues; i++) {
2723 txq = kzalloc(sizeof(*txq), GFP_KERNEL);
2729 fep->tx_queue[i] = txq;
2730 txq->tx_ring_size = TX_RING_SIZE;
2731 fep->total_tx_ring_size += fep->tx_queue[i]->tx_ring_size;
2733 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS;
2734 txq->tx_wake_threshold =
2735 (txq->tx_ring_size - txq->tx_stop_threshold) / 2;
2737 txq->tso_hdrs = dma_alloc_coherent(NULL,
2738 txq->tx_ring_size * TSO_HEADER_SIZE,
2741 if (!txq->tso_hdrs) {
2747 for (i = 0; i < fep->num_rx_queues; i++) {
2748 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]),
2750 if (!fep->rx_queue[i]) {
2755 fep->rx_queue[i]->rx_ring_size = RX_RING_SIZE;
2756 fep->total_rx_ring_size += fep->rx_queue[i]->rx_ring_size;
2761 fec_enet_free_queue(ndev);
2766 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue)
2768 struct fec_enet_private *fep = netdev_priv(ndev);
2770 struct sk_buff *skb;
2771 struct bufdesc *bdp;
2772 struct fec_enet_priv_rx_q *rxq;
2774 rxq = fep->rx_queue[queue];
2775 bdp = rxq->rx_bd_base;
2776 for (i = 0; i < rxq->rx_ring_size; i++) {
2777 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
2781 if (fec_enet_new_rxbdp(ndev, bdp, skb)) {
2786 rxq->rx_skbuff[i] = skb;
2787 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
2789 if (fep->bufdesc_ex) {
2790 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2791 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
2794 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
2797 /* Set the last buffer to wrap. */
2798 bdp = fec_enet_get_prevdesc(bdp, fep, queue);
2799 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
2803 fec_enet_free_buffers(ndev);
2808 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue)
2810 struct fec_enet_private *fep = netdev_priv(ndev);
2812 struct bufdesc *bdp;
2813 struct fec_enet_priv_tx_q *txq;
2815 txq = fep->tx_queue[queue];
2816 bdp = txq->tx_bd_base;
2817 for (i = 0; i < txq->tx_ring_size; i++) {
2818 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
2819 if (!txq->tx_bounce[i])
2822 bdp->cbd_sc = cpu_to_fec16(0);
2823 bdp->cbd_bufaddr = cpu_to_fec32(0);
2825 if (fep->bufdesc_ex) {
2826 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2827 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT);
2830 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
2833 /* Set the last buffer to wrap. */
2834 bdp = fec_enet_get_prevdesc(bdp, fep, queue);
2835 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
2840 fec_enet_free_buffers(ndev);
2844 static int fec_enet_alloc_buffers(struct net_device *ndev)
2846 struct fec_enet_private *fep = netdev_priv(ndev);
2849 for (i = 0; i < fep->num_rx_queues; i++)
2850 if (fec_enet_alloc_rxq_buffers(ndev, i))
2853 for (i = 0; i < fep->num_tx_queues; i++)
2854 if (fec_enet_alloc_txq_buffers(ndev, i))
2860 fec_enet_open(struct net_device *ndev)
2862 struct fec_enet_private *fep = netdev_priv(ndev);
2865 ret = pm_runtime_get_sync(&fep->pdev->dev);
2869 pinctrl_pm_select_default_state(&fep->pdev->dev);
2870 ret = fec_enet_clk_enable(ndev, true);
2874 /* I should reset the ring buffers here, but I don't yet know
2875 * a simple way to do that.
2878 ret = fec_enet_alloc_buffers(ndev);
2880 goto err_enet_alloc;
2882 /* Init MAC prior to mii bus probe */
2885 /* Probe and connect to PHY when open the interface */
2886 ret = fec_enet_mii_probe(ndev);
2888 goto err_enet_mii_probe;
2890 napi_enable(&fep->napi);
2891 phy_start(fep->phy_dev);
2892 netif_tx_start_all_queues(ndev);
2894 device_set_wakeup_enable(&ndev->dev, fep->wol_flag &
2895 FEC_WOL_FLAG_ENABLE);
2900 fec_enet_free_buffers(ndev);
2902 fec_enet_clk_enable(ndev, false);
2904 pm_runtime_mark_last_busy(&fep->pdev->dev);
2905 pm_runtime_put_autosuspend(&fep->pdev->dev);
2906 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2911 fec_enet_close(struct net_device *ndev)
2913 struct fec_enet_private *fep = netdev_priv(ndev);
2915 phy_stop(fep->phy_dev);
2917 if (netif_device_present(ndev)) {
2918 napi_disable(&fep->napi);
2919 netif_tx_disable(ndev);
2923 phy_disconnect(fep->phy_dev);
2924 fep->phy_dev = NULL;
2926 fec_enet_clk_enable(ndev, false);
2927 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2928 pm_runtime_mark_last_busy(&fep->pdev->dev);
2929 pm_runtime_put_autosuspend(&fep->pdev->dev);
2931 fec_enet_free_buffers(ndev);
2936 /* Set or clear the multicast filter for this adaptor.
2937 * Skeleton taken from sunlance driver.
2938 * The CPM Ethernet implementation allows Multicast as well as individual
2939 * MAC address filtering. Some of the drivers check to make sure it is
2940 * a group multicast address, and discard those that are not. I guess I
2941 * will do the same for now, but just remove the test if you want
2942 * individual filtering as well (do the upper net layers want or support
2943 * this kind of feature?).
2946 #define HASH_BITS 6 /* #bits in hash */
2947 #define CRC32_POLY 0xEDB88320
2949 static void set_multicast_list(struct net_device *ndev)
2951 struct fec_enet_private *fep = netdev_priv(ndev);
2952 struct netdev_hw_addr *ha;
2953 unsigned int i, bit, data, crc, tmp;
2956 if (ndev->flags & IFF_PROMISC) {
2957 tmp = readl(fep->hwp + FEC_R_CNTRL);
2959 writel(tmp, fep->hwp + FEC_R_CNTRL);
2963 tmp = readl(fep->hwp + FEC_R_CNTRL);
2965 writel(tmp, fep->hwp + FEC_R_CNTRL);
2967 if (ndev->flags & IFF_ALLMULTI) {
2968 /* Catch all multicast addresses, so set the
2971 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2972 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2977 /* Clear filter and add the addresses in hash register
2979 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2980 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2982 netdev_for_each_mc_addr(ha, ndev) {
2983 /* calculate crc32 value of mac address */
2986 for (i = 0; i < ndev->addr_len; i++) {
2988 for (bit = 0; bit < 8; bit++, data >>= 1) {
2990 (((crc ^ data) & 1) ? CRC32_POLY : 0);
2994 /* only upper 6 bits (HASH_BITS) are used
2995 * which point to specific bit in he hash registers
2997 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
3000 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
3001 tmp |= 1 << (hash - 32);
3002 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
3004 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
3006 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
3011 /* Set a MAC change in hardware. */
3013 fec_set_mac_address(struct net_device *ndev, void *p)
3015 struct fec_enet_private *fep = netdev_priv(ndev);
3016 struct sockaddr *addr = p;
3019 if (!is_valid_ether_addr(addr->sa_data))
3020 return -EADDRNOTAVAIL;
3021 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3024 /* Add netif status check here to avoid system hang in below case:
3025 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx;
3026 * After ethx down, fec all clocks are gated off and then register
3027 * access causes system hang.
3029 if (!netif_running(ndev))
3032 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
3033 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
3034 fep->hwp + FEC_ADDR_LOW);
3035 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
3036 fep->hwp + FEC_ADDR_HIGH);
3040 #ifdef CONFIG_NET_POLL_CONTROLLER
3042 * fec_poll_controller - FEC Poll controller function
3043 * @dev: The FEC network adapter
3045 * Polled functionality used by netconsole and others in non interrupt mode
3048 static void fec_poll_controller(struct net_device *dev)
3051 struct fec_enet_private *fep = netdev_priv(dev);
3053 for (i = 0; i < FEC_IRQ_NUM; i++) {
3054 if (fep->irq[i] > 0) {
3055 disable_irq(fep->irq[i]);
3056 fec_enet_interrupt(fep->irq[i], dev);
3057 enable_irq(fep->irq[i]);
3063 static inline void fec_enet_set_netdev_features(struct net_device *netdev,
3064 netdev_features_t features)
3066 struct fec_enet_private *fep = netdev_priv(netdev);
3067 netdev_features_t changed = features ^ netdev->features;
3069 netdev->features = features;
3071 /* Receive checksum has been changed */
3072 if (changed & NETIF_F_RXCSUM) {
3073 if (features & NETIF_F_RXCSUM)
3074 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3076 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
3080 static int fec_set_features(struct net_device *netdev,
3081 netdev_features_t features)
3083 struct fec_enet_private *fep = netdev_priv(netdev);
3084 netdev_features_t changed = features ^ netdev->features;
3086 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) {
3087 napi_disable(&fep->napi);
3088 netif_tx_lock_bh(netdev);
3090 fec_enet_set_netdev_features(netdev, features);
3091 fec_restart(netdev);
3092 netif_tx_wake_all_queues(netdev);
3093 netif_tx_unlock_bh(netdev);
3094 napi_enable(&fep->napi);
3096 fec_enet_set_netdev_features(netdev, features);
3102 static const struct net_device_ops fec_netdev_ops = {
3103 .ndo_open = fec_enet_open,
3104 .ndo_stop = fec_enet_close,
3105 .ndo_start_xmit = fec_enet_start_xmit,
3106 .ndo_set_rx_mode = set_multicast_list,
3107 .ndo_change_mtu = eth_change_mtu,
3108 .ndo_validate_addr = eth_validate_addr,
3109 .ndo_tx_timeout = fec_timeout,
3110 .ndo_set_mac_address = fec_set_mac_address,
3111 .ndo_do_ioctl = fec_enet_ioctl,
3112 #ifdef CONFIG_NET_POLL_CONTROLLER
3113 .ndo_poll_controller = fec_poll_controller,
3115 .ndo_set_features = fec_set_features,
3119 * XXX: We need to clean up on failure exits here.
3122 static int fec_enet_init(struct net_device *ndev)
3124 struct fec_enet_private *fep = netdev_priv(ndev);
3125 struct fec_enet_priv_tx_q *txq;
3126 struct fec_enet_priv_rx_q *rxq;
3127 struct bufdesc *cbd_base;
3132 #if defined(CONFIG_ARM)
3133 fep->rx_align = 0xf;
3134 fep->tx_align = 0xf;
3136 fep->rx_align = 0x3;
3137 fep->tx_align = 0x3;
3140 fec_enet_alloc_queue(ndev);
3142 if (fep->bufdesc_ex)
3143 fep->bufdesc_size = sizeof(struct bufdesc_ex);
3145 fep->bufdesc_size = sizeof(struct bufdesc);
3146 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) *
3149 /* Allocate memory for buffer descriptors. */
3150 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma,
3156 memset(cbd_base, 0, bd_size);
3158 /* Get the Ethernet address */
3160 /* make sure MAC we just acquired is programmed into the hw */
3161 fec_set_mac_address(ndev, NULL);
3163 /* Set receive and transmit descriptor base. */
3164 for (i = 0; i < fep->num_rx_queues; i++) {
3165 rxq = fep->rx_queue[i];
3167 rxq->rx_bd_base = (struct bufdesc *)cbd_base;
3168 rxq->bd_dma = bd_dma;
3169 if (fep->bufdesc_ex) {
3170 bd_dma += sizeof(struct bufdesc_ex) * rxq->rx_ring_size;
3171 cbd_base = (struct bufdesc *)
3172 (((struct bufdesc_ex *)cbd_base) + rxq->rx_ring_size);
3174 bd_dma += sizeof(struct bufdesc) * rxq->rx_ring_size;
3175 cbd_base += rxq->rx_ring_size;
3179 for (i = 0; i < fep->num_tx_queues; i++) {
3180 txq = fep->tx_queue[i];
3182 txq->tx_bd_base = (struct bufdesc *)cbd_base;
3183 txq->bd_dma = bd_dma;
3184 if (fep->bufdesc_ex) {
3185 bd_dma += sizeof(struct bufdesc_ex) * txq->tx_ring_size;
3186 cbd_base = (struct bufdesc *)
3187 (((struct bufdesc_ex *)cbd_base) + txq->tx_ring_size);
3189 bd_dma += sizeof(struct bufdesc) * txq->tx_ring_size;
3190 cbd_base += txq->tx_ring_size;
3195 /* The FEC Ethernet specific entries in the device structure */
3196 ndev->watchdog_timeo = TX_TIMEOUT;
3197 ndev->netdev_ops = &fec_netdev_ops;
3198 ndev->ethtool_ops = &fec_enet_ethtool_ops;
3200 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
3201 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
3203 if (fep->quirks & FEC_QUIRK_HAS_VLAN)
3204 /* enable hw VLAN support */
3205 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3207 if (fep->quirks & FEC_QUIRK_HAS_CSUM) {
3208 ndev->gso_max_segs = FEC_MAX_TSO_SEGS;
3210 /* enable hw accelerator */
3211 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
3212 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
3213 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3216 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
3218 fep->rx_align = 0x3f;
3221 ndev->hw_features = ndev->features;
3229 static void fec_reset_phy(struct platform_device *pdev)
3233 struct device_node *np = pdev->dev.of_node;
3238 of_property_read_u32(np, "phy-reset-duration", &msec);
3239 /* A sane reset duration should not be longer than 1s */
3243 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
3244 if (!gpio_is_valid(phy_reset))
3247 err = devm_gpio_request_one(&pdev->dev, phy_reset,
3248 GPIOF_OUT_INIT_LOW, "phy-reset");
3250 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
3254 gpio_set_value_cansleep(phy_reset, 1);
3256 #else /* CONFIG_OF */
3257 static void fec_reset_phy(struct platform_device *pdev)
3260 * In case of platform probe, the reset has been done
3264 #endif /* CONFIG_OF */
3267 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx)
3269 struct device_node *np = pdev->dev.of_node;
3271 *num_tx = *num_rx = 1;
3273 if (!np || !of_device_is_available(np))
3276 /* parse the num of tx and rx queues */
3277 of_property_read_u32(np, "fsl,num-tx-queues", num_tx);
3279 of_property_read_u32(np, "fsl,num-rx-queues", num_rx);
3281 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) {
3282 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n",
3288 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) {
3289 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n",
3298 fec_probe(struct platform_device *pdev)
3300 struct fec_enet_private *fep;
3301 struct fec_platform_data *pdata;
3302 struct net_device *ndev;
3303 int i, irq, ret = 0;
3305 const struct of_device_id *of_id;
3307 struct device_node *np = pdev->dev.of_node, *phy_node;
3311 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs);
3313 /* Init network device */
3314 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private),
3315 num_tx_qs, num_rx_qs);
3319 SET_NETDEV_DEV(ndev, &pdev->dev);
3321 /* setup board info structure */
3322 fep = netdev_priv(ndev);
3324 of_id = of_match_device(fec_dt_ids, &pdev->dev);
3326 pdev->id_entry = of_id->data;
3327 fep->quirks = pdev->id_entry->driver_data;
3330 fep->num_rx_queues = num_rx_qs;
3331 fep->num_tx_queues = num_tx_qs;
3333 #if !defined(CONFIG_M5272)
3334 /* default enable pause frame auto negotiation */
3335 if (fep->quirks & FEC_QUIRK_HAS_GBIT)
3336 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
3339 /* Select default pin state */
3340 pinctrl_pm_select_default_state(&pdev->dev);
3342 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3343 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
3344 if (IS_ERR(fep->hwp)) {
3345 ret = PTR_ERR(fep->hwp);
3346 goto failed_ioremap;
3350 fep->dev_id = dev_id++;
3352 platform_set_drvdata(pdev, ndev);
3354 if (of_get_property(np, "fsl,magic-packet", NULL))
3355 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET;
3357 phy_node = of_parse_phandle(np, "phy-handle", 0);
3358 if (!phy_node && of_phy_is_fixed_link(np)) {
3359 ret = of_phy_register_fixed_link(np);
3362 "broken fixed-link specification\n");
3365 phy_node = of_node_get(np);
3367 fep->phy_node = phy_node;
3369 ret = of_get_phy_mode(pdev->dev.of_node);
3371 pdata = dev_get_platdata(&pdev->dev);
3373 fep->phy_interface = pdata->phy;
3375 fep->phy_interface = PHY_INTERFACE_MODE_MII;
3377 fep->phy_interface = ret;
3380 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
3381 if (IS_ERR(fep->clk_ipg)) {
3382 ret = PTR_ERR(fep->clk_ipg);
3386 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
3387 if (IS_ERR(fep->clk_ahb)) {
3388 ret = PTR_ERR(fep->clk_ahb);
3392 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb);
3394 /* enet_out is optional, depends on board */
3395 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
3396 if (IS_ERR(fep->clk_enet_out))
3397 fep->clk_enet_out = NULL;
3399 fep->ptp_clk_on = false;
3400 mutex_init(&fep->ptp_clk_mutex);
3402 /* clk_ref is optional, depends on board */
3403 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref");
3404 if (IS_ERR(fep->clk_ref))
3405 fep->clk_ref = NULL;
3407 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX;
3408 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
3409 if (IS_ERR(fep->clk_ptp)) {
3410 fep->clk_ptp = NULL;
3411 fep->bufdesc_ex = false;
3414 ret = fec_enet_clk_enable(ndev, true);
3418 ret = clk_prepare_enable(fep->clk_ipg);
3420 goto failed_clk_ipg;
3422 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
3423 if (!IS_ERR(fep->reg_phy)) {
3424 ret = regulator_enable(fep->reg_phy);
3427 "Failed to enable phy regulator: %d\n", ret);
3428 goto failed_regulator;
3431 fep->reg_phy = NULL;
3434 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT);
3435 pm_runtime_use_autosuspend(&pdev->dev);
3436 pm_runtime_get_noresume(&pdev->dev);
3437 pm_runtime_set_active(&pdev->dev);
3438 pm_runtime_enable(&pdev->dev);
3440 fec_reset_phy(pdev);
3442 if (fep->bufdesc_ex)
3445 ret = fec_enet_init(ndev);
3449 for (i = 0; i < FEC_IRQ_NUM; i++) {
3450 irq = platform_get_irq(pdev, i);
3457 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
3458 0, pdev->name, ndev);
3465 init_completion(&fep->mdio_done);
3466 ret = fec_enet_mii_init(pdev);
3468 goto failed_mii_init;
3470 /* Carrier starts down, phylib will bring it up */
3471 netif_carrier_off(ndev);
3472 fec_enet_clk_enable(ndev, false);
3473 pinctrl_pm_select_sleep_state(&pdev->dev);
3475 ret = register_netdev(ndev);
3477 goto failed_register;
3479 device_init_wakeup(&ndev->dev, fep->wol_flag &
3480 FEC_WOL_HAS_MAGIC_PACKET);
3482 if (fep->bufdesc_ex && fep->ptp_clock)
3483 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
3485 fep->rx_copybreak = COPYBREAK_DEFAULT;
3486 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
3488 pm_runtime_mark_last_busy(&pdev->dev);
3489 pm_runtime_put_autosuspend(&pdev->dev);
3494 fec_enet_mii_remove(fep);
3500 regulator_disable(fep->reg_phy);
3502 clk_disable_unprepare(fep->clk_ipg);
3504 fec_enet_clk_enable(ndev, false);
3507 of_node_put(phy_node);
3515 fec_drv_remove(struct platform_device *pdev)
3517 struct net_device *ndev = platform_get_drvdata(pdev);
3518 struct fec_enet_private *fep = netdev_priv(ndev);
3520 cancel_work_sync(&fep->tx_timeout_work);
3522 unregister_netdev(ndev);
3523 fec_enet_mii_remove(fep);
3525 regulator_disable(fep->reg_phy);
3526 of_node_put(fep->phy_node);
3532 static int __maybe_unused fec_suspend(struct device *dev)
3534 struct net_device *ndev = dev_get_drvdata(dev);
3535 struct fec_enet_private *fep = netdev_priv(ndev);
3538 if (netif_running(ndev)) {
3539 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE)
3540 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON;
3541 phy_stop(fep->phy_dev);
3542 napi_disable(&fep->napi);
3543 netif_tx_lock_bh(ndev);
3544 netif_device_detach(ndev);
3545 netif_tx_unlock_bh(ndev);
3547 fec_enet_clk_enable(ndev, false);
3548 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3549 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3553 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3554 regulator_disable(fep->reg_phy);
3556 /* SOC supply clock to phy, when clock is disabled, phy link down
3557 * SOC control phy regulator, when regulator is disabled, phy link down
3559 if (fep->clk_enet_out || fep->reg_phy)
3565 static int __maybe_unused fec_resume(struct device *dev)
3567 struct net_device *ndev = dev_get_drvdata(dev);
3568 struct fec_enet_private *fep = netdev_priv(ndev);
3569 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
3573 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) {
3574 ret = regulator_enable(fep->reg_phy);
3580 if (netif_running(ndev)) {
3581 ret = fec_enet_clk_enable(ndev, true);
3586 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) {
3587 if (pdata && pdata->sleep_mode_enable)
3588 pdata->sleep_mode_enable(false);
3589 val = readl(fep->hwp + FEC_ECNTRL);
3590 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
3591 writel(val, fep->hwp + FEC_ECNTRL);
3592 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON;
3594 pinctrl_pm_select_default_state(&fep->pdev->dev);
3597 netif_tx_lock_bh(ndev);
3598 netif_device_attach(ndev);
3599 netif_tx_unlock_bh(ndev);
3600 napi_enable(&fep->napi);
3601 phy_start(fep->phy_dev);
3609 regulator_disable(fep->reg_phy);
3613 static int __maybe_unused fec_runtime_suspend(struct device *dev)
3615 struct net_device *ndev = dev_get_drvdata(dev);
3616 struct fec_enet_private *fep = netdev_priv(ndev);
3618 clk_disable_unprepare(fep->clk_ipg);
3623 static int __maybe_unused fec_runtime_resume(struct device *dev)
3625 struct net_device *ndev = dev_get_drvdata(dev);
3626 struct fec_enet_private *fep = netdev_priv(ndev);
3628 return clk_prepare_enable(fep->clk_ipg);
3631 static const struct dev_pm_ops fec_pm_ops = {
3632 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume)
3633 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL)
3636 static struct platform_driver fec_driver = {
3638 .name = DRIVER_NAME,
3640 .of_match_table = fec_dt_ids,
3642 .id_table = fec_devtype,
3644 .remove = fec_drv_remove,
3647 module_platform_driver(fec_driver);
3649 MODULE_ALIAS("platform:"DRIVER_NAME);
3650 MODULE_LICENSE("GPL");