2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/ptrace.h>
29 #include <linux/errno.h>
30 #include <linux/ioport.h>
31 #include <linux/slab.h>
32 #include <linux/interrupt.h>
33 #include <linux/delay.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/icmp.h>
44 #include <linux/spinlock.h>
45 #include <linux/workqueue.h>
46 #include <linux/bitops.h>
48 #include <linux/irq.h>
49 #include <linux/clk.h>
50 #include <linux/platform_device.h>
51 #include <linux/mdio.h>
52 #include <linux/phy.h>
53 #include <linux/fec.h>
55 #include <linux/of_device.h>
56 #include <linux/of_gpio.h>
57 #include <linux/of_mdio.h>
58 #include <linux/of_net.h>
59 #include <linux/regulator/consumer.h>
60 #include <linux/if_vlan.h>
61 #include <linux/pinctrl/consumer.h>
62 #include <linux/prefetch.h>
63 #include <soc/imx/cpuidle.h>
65 #include <asm/cacheflush.h>
69 static void set_multicast_list(struct net_device *ndev);
70 static void fec_enet_itr_coal_init(struct net_device *ndev);
72 #define DRIVER_NAME "fec"
74 #define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0))
76 /* Pause frame feild and FIFO threshold */
77 #define FEC_ENET_FCE (1 << 5)
78 #define FEC_ENET_RSEM_V 0x84
79 #define FEC_ENET_RSFL_V 16
80 #define FEC_ENET_RAEM_V 0x8
81 #define FEC_ENET_RAFL_V 0x8
82 #define FEC_ENET_OPD_V 0xFFF0
83 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */
85 static struct platform_device_id fec_devtype[] = {
87 /* keep it for coldfire */
92 .driver_data = FEC_QUIRK_USE_GASKET | FEC_QUIRK_HAS_RACC,
95 .driver_data = FEC_QUIRK_HAS_RACC,
98 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME |
99 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC,
102 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
103 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
104 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 |
107 .name = "mvf600-fec",
108 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC,
110 .name = "imx6sx-fec",
111 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
112 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
113 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
114 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
120 MODULE_DEVICE_TABLE(platform, fec_devtype);
123 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
124 IMX27_FEC, /* runs on i.mx27/35/51 */
131 static const struct of_device_id fec_dt_ids[] = {
132 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
133 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
134 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
135 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
136 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
137 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
140 MODULE_DEVICE_TABLE(of, fec_dt_ids);
142 static unsigned char macaddr[ETH_ALEN];
143 module_param_array(macaddr, byte, NULL, 0);
144 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
146 #if defined(CONFIG_M5272)
148 * Some hardware gets it MAC address out of local flash memory.
149 * if this is non-zero then assume it is the address to get MAC from.
151 #if defined(CONFIG_NETtel)
152 #define FEC_FLASHMAC 0xf0006006
153 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
154 #define FEC_FLASHMAC 0xf0006000
155 #elif defined(CONFIG_CANCam)
156 #define FEC_FLASHMAC 0xf0020000
157 #elif defined (CONFIG_M5272C3)
158 #define FEC_FLASHMAC (0xffe04000 + 4)
159 #elif defined(CONFIG_MOD5272)
160 #define FEC_FLASHMAC 0xffc0406b
162 #define FEC_FLASHMAC 0
164 #endif /* CONFIG_M5272 */
166 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
168 #define PKT_MAXBUF_SIZE 1522
169 #define PKT_MINBUF_SIZE 64
170 #define PKT_MAXBLR_SIZE 1536
172 /* FEC receive acceleration */
173 #define FEC_RACC_IPDIS (1 << 1)
174 #define FEC_RACC_PRODIS (1 << 2)
175 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
178 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
179 * size bits. Other FEC hardware does not, so we need to take that into
180 * account when setting it.
182 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
183 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
184 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
186 #define OPT_FRAME_SIZE 0
189 /* FEC MII MMFR bits definition */
190 #define FEC_MMFR_ST (1 << 30)
191 #define FEC_MMFR_OP_READ (2 << 28)
192 #define FEC_MMFR_OP_WRITE (1 << 28)
193 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
194 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
195 #define FEC_MMFR_TA (2 << 16)
196 #define FEC_MMFR_DATA(v) (v & 0xffff)
197 /* FEC ECR bits definition */
198 #define FEC_ECR_MAGICEN (1 << 2)
199 #define FEC_ECR_SLEEP (1 << 3)
201 #define FEC_MII_TIMEOUT 30000 /* us */
203 /* Transmitter timeout */
204 #define TX_TIMEOUT (2 * HZ)
206 #define FEC_PAUSE_FLAG_AUTONEG 0x1
207 #define FEC_PAUSE_FLAG_ENABLE 0x2
208 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0)
209 #define FEC_WOL_FLAG_ENABLE (0x1 << 1)
210 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2)
212 #define COPYBREAK_DEFAULT 256
214 #define TSO_HEADER_SIZE 128
215 /* Max number of allowed TCP segments for software TSO */
216 #define FEC_MAX_TSO_SEGS 100
217 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
219 #define IS_TSO_HEADER(txq, addr) \
220 ((addr >= txq->tso_hdrs_dma) && \
221 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE))
225 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp,
226 struct bufdesc_prop *bd)
228 return (bdp >= bd->last) ? bd->base
229 : (struct bufdesc *)(((unsigned)bdp) + bd->dsize);
232 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp,
233 struct bufdesc_prop *bd)
235 return (bdp <= bd->base) ? bd->last
236 : (struct bufdesc *)(((unsigned)bdp) - bd->dsize);
239 static int fec_enet_get_bd_index(struct bufdesc *bdp,
240 struct bufdesc_prop *bd)
242 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2;
245 static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq)
249 entries = (((const char *)txq->dirty_tx -
250 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1;
252 return entries >= 0 ? entries : entries + txq->bd.ring_size;
255 static void swap_buffer(void *bufaddr, int len)
258 unsigned int *buf = bufaddr;
260 for (i = 0; i < len; i += 4, buf++)
264 static void swap_buffer2(void *dst_buf, void *src_buf, int len)
267 unsigned int *src = src_buf;
268 unsigned int *dst = dst_buf;
270 for (i = 0; i < len; i += 4, src++, dst++)
274 static void fec_dump(struct net_device *ndev)
276 struct fec_enet_private *fep = netdev_priv(ndev);
278 struct fec_enet_priv_tx_q *txq;
281 netdev_info(ndev, "TX ring dump\n");
282 pr_info("Nr SC addr len SKB\n");
284 txq = fep->tx_queue[0];
288 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n",
290 bdp == txq->bd.cur ? 'S' : ' ',
291 bdp == txq->dirty_tx ? 'H' : ' ',
292 fec16_to_cpu(bdp->cbd_sc),
293 fec32_to_cpu(bdp->cbd_bufaddr),
294 fec16_to_cpu(bdp->cbd_datlen),
295 txq->tx_skbuff[index]);
296 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
298 } while (bdp != txq->bd.base);
301 static inline bool is_ipv4_pkt(struct sk_buff *skb)
303 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
307 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
309 /* Only run for packets requiring a checksum. */
310 if (skb->ip_summed != CHECKSUM_PARTIAL)
313 if (unlikely(skb_cow_head(skb, 0)))
316 if (is_ipv4_pkt(skb))
317 ip_hdr(skb)->check = 0;
318 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
323 static struct bufdesc *
324 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq,
326 struct net_device *ndev)
328 struct fec_enet_private *fep = netdev_priv(ndev);
329 struct bufdesc *bdp = txq->bd.cur;
330 struct bufdesc_ex *ebdp;
331 int nr_frags = skb_shinfo(skb)->nr_frags;
333 unsigned short status;
334 unsigned int estatus = 0;
335 skb_frag_t *this_frag;
341 for (frag = 0; frag < nr_frags; frag++) {
342 this_frag = &skb_shinfo(skb)->frags[frag];
343 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
344 ebdp = (struct bufdesc_ex *)bdp;
346 status = fec16_to_cpu(bdp->cbd_sc);
347 status &= ~BD_ENET_TX_STATS;
348 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
349 frag_len = skb_shinfo(skb)->frags[frag].size;
351 /* Handle the last BD specially */
352 if (frag == nr_frags - 1) {
353 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
354 if (fep->bufdesc_ex) {
355 estatus |= BD_ENET_TX_INT;
356 if (unlikely(skb_shinfo(skb)->tx_flags &
357 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
358 estatus |= BD_ENET_TX_TS;
362 if (fep->bufdesc_ex) {
363 if (fep->quirks & FEC_QUIRK_HAS_AVB)
364 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
365 if (skb->ip_summed == CHECKSUM_PARTIAL)
366 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
368 ebdp->cbd_esc = cpu_to_fec32(estatus);
371 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset;
373 index = fec_enet_get_bd_index(bdp, &txq->bd);
374 if (((unsigned long) bufaddr) & fep->tx_align ||
375 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
376 memcpy(txq->tx_bounce[index], bufaddr, frag_len);
377 bufaddr = txq->tx_bounce[index];
379 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
380 swap_buffer(bufaddr, frag_len);
383 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
385 if (dma_mapping_error(&fep->pdev->dev, addr)) {
387 netdev_err(ndev, "Tx DMA memory map failed\n");
388 goto dma_mapping_error;
391 bdp->cbd_bufaddr = cpu_to_fec32(addr);
392 bdp->cbd_datlen = cpu_to_fec16(frag_len);
393 /* Make sure the updates to rest of the descriptor are
394 * performed before transferring ownership.
397 bdp->cbd_sc = cpu_to_fec16(status);
403 for (i = 0; i < frag; i++) {
404 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
405 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr),
406 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE);
408 return ERR_PTR(-ENOMEM);
411 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq,
412 struct sk_buff *skb, struct net_device *ndev)
414 struct fec_enet_private *fep = netdev_priv(ndev);
415 int nr_frags = skb_shinfo(skb)->nr_frags;
416 struct bufdesc *bdp, *last_bdp;
419 unsigned short status;
420 unsigned short buflen;
421 unsigned int estatus = 0;
425 entries_free = fec_enet_get_free_txdesc_num(txq);
426 if (entries_free < MAX_SKB_FRAGS + 1) {
427 dev_kfree_skb_any(skb);
429 netdev_err(ndev, "NOT enough BD for SG!\n");
433 /* Protocol checksum off-load for TCP and UDP. */
434 if (fec_enet_clear_csum(skb, ndev)) {
435 dev_kfree_skb_any(skb);
439 /* Fill in a Tx ring entry */
442 status = fec16_to_cpu(bdp->cbd_sc);
443 status &= ~BD_ENET_TX_STATS;
445 /* Set buffer length and buffer pointer */
447 buflen = skb_headlen(skb);
449 index = fec_enet_get_bd_index(bdp, &txq->bd);
450 if (((unsigned long) bufaddr) & fep->tx_align ||
451 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
452 memcpy(txq->tx_bounce[index], skb->data, buflen);
453 bufaddr = txq->tx_bounce[index];
455 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
456 swap_buffer(bufaddr, buflen);
459 /* Push the data cache so the CPM does not get stale memory data. */
460 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
461 if (dma_mapping_error(&fep->pdev->dev, addr)) {
462 dev_kfree_skb_any(skb);
464 netdev_err(ndev, "Tx DMA memory map failed\n");
469 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev);
470 if (IS_ERR(last_bdp)) {
471 dma_unmap_single(&fep->pdev->dev, addr,
472 buflen, DMA_TO_DEVICE);
473 dev_kfree_skb_any(skb);
477 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
478 if (fep->bufdesc_ex) {
479 estatus = BD_ENET_TX_INT;
480 if (unlikely(skb_shinfo(skb)->tx_flags &
481 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
482 estatus |= BD_ENET_TX_TS;
485 bdp->cbd_bufaddr = cpu_to_fec32(addr);
486 bdp->cbd_datlen = cpu_to_fec16(buflen);
488 if (fep->bufdesc_ex) {
490 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
492 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
494 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
496 if (fep->quirks & FEC_QUIRK_HAS_AVB)
497 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
499 if (skb->ip_summed == CHECKSUM_PARTIAL)
500 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
503 ebdp->cbd_esc = cpu_to_fec32(estatus);
506 index = fec_enet_get_bd_index(last_bdp, &txq->bd);
507 /* Save skb pointer */
508 txq->tx_skbuff[index] = skb;
510 /* Make sure the updates to rest of the descriptor are performed before
511 * transferring ownership.
515 /* Send it on its way. Tell FEC it's ready, interrupt when done,
516 * it's the last BD of the frame, and to put the CRC on the end.
518 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
519 bdp->cbd_sc = cpu_to_fec16(status);
521 /* If this was the last BD in the ring, start at the beginning again. */
522 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd);
524 skb_tx_timestamp(skb);
526 /* Make sure the update to bdp and tx_skbuff are performed before
532 /* Trigger transmission start */
533 writel(0, txq->bd.reg_desc_active);
539 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb,
540 struct net_device *ndev,
541 struct bufdesc *bdp, int index, char *data,
542 int size, bool last_tcp, bool is_last)
544 struct fec_enet_private *fep = netdev_priv(ndev);
545 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
546 unsigned short status;
547 unsigned int estatus = 0;
550 status = fec16_to_cpu(bdp->cbd_sc);
551 status &= ~BD_ENET_TX_STATS;
553 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
555 if (((unsigned long) data) & fep->tx_align ||
556 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
557 memcpy(txq->tx_bounce[index], data, size);
558 data = txq->tx_bounce[index];
560 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
561 swap_buffer(data, size);
564 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
565 if (dma_mapping_error(&fep->pdev->dev, addr)) {
566 dev_kfree_skb_any(skb);
568 netdev_err(ndev, "Tx DMA memory map failed\n");
569 return NETDEV_TX_BUSY;
572 bdp->cbd_datlen = cpu_to_fec16(size);
573 bdp->cbd_bufaddr = cpu_to_fec32(addr);
575 if (fep->bufdesc_ex) {
576 if (fep->quirks & FEC_QUIRK_HAS_AVB)
577 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
578 if (skb->ip_summed == CHECKSUM_PARTIAL)
579 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
581 ebdp->cbd_esc = cpu_to_fec32(estatus);
584 /* Handle the last BD specially */
586 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
588 status |= BD_ENET_TX_INTR;
590 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT);
593 bdp->cbd_sc = cpu_to_fec16(status);
599 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq,
600 struct sk_buff *skb, struct net_device *ndev,
601 struct bufdesc *bdp, int index)
603 struct fec_enet_private *fep = netdev_priv(ndev);
604 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
605 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
607 unsigned long dmabuf;
608 unsigned short status;
609 unsigned int estatus = 0;
611 status = fec16_to_cpu(bdp->cbd_sc);
612 status &= ~BD_ENET_TX_STATS;
613 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
615 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
616 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE;
617 if (((unsigned long)bufaddr) & fep->tx_align ||
618 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
619 memcpy(txq->tx_bounce[index], skb->data, hdr_len);
620 bufaddr = txq->tx_bounce[index];
622 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
623 swap_buffer(bufaddr, hdr_len);
625 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
626 hdr_len, DMA_TO_DEVICE);
627 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
628 dev_kfree_skb_any(skb);
630 netdev_err(ndev, "Tx DMA memory map failed\n");
631 return NETDEV_TX_BUSY;
635 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf);
636 bdp->cbd_datlen = cpu_to_fec16(hdr_len);
638 if (fep->bufdesc_ex) {
639 if (fep->quirks & FEC_QUIRK_HAS_AVB)
640 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
641 if (skb->ip_summed == CHECKSUM_PARTIAL)
642 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
644 ebdp->cbd_esc = cpu_to_fec32(estatus);
647 bdp->cbd_sc = cpu_to_fec16(status);
652 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq,
654 struct net_device *ndev)
656 struct fec_enet_private *fep = netdev_priv(ndev);
657 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
658 int total_len, data_left;
659 struct bufdesc *bdp = txq->bd.cur;
661 unsigned int index = 0;
664 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) {
665 dev_kfree_skb_any(skb);
667 netdev_err(ndev, "NOT enough BD for TSO!\n");
671 /* Protocol checksum off-load for TCP and UDP. */
672 if (fec_enet_clear_csum(skb, ndev)) {
673 dev_kfree_skb_any(skb);
677 /* Initialize the TSO handler, and prepare the first payload */
678 tso_start(skb, &tso);
680 total_len = skb->len - hdr_len;
681 while (total_len > 0) {
684 index = fec_enet_get_bd_index(bdp, &txq->bd);
685 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
686 total_len -= data_left;
688 /* prepare packet headers: MAC + IP + TCP */
689 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
690 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
691 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index);
695 while (data_left > 0) {
698 size = min_t(int, tso.size, data_left);
699 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
700 index = fec_enet_get_bd_index(bdp, &txq->bd);
701 ret = fec_enet_txq_put_data_tso(txq, skb, ndev,
710 tso_build_data(skb, &tso, size);
713 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
716 /* Save skb pointer */
717 txq->tx_skbuff[index] = skb;
719 skb_tx_timestamp(skb);
722 /* Trigger transmission start */
723 if (!(fep->quirks & FEC_QUIRK_ERR007885) ||
724 !readl(txq->bd.reg_desc_active) ||
725 !readl(txq->bd.reg_desc_active) ||
726 !readl(txq->bd.reg_desc_active) ||
727 !readl(txq->bd.reg_desc_active))
728 writel(0, txq->bd.reg_desc_active);
733 /* TODO: Release all used data descriptors for TSO */
738 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
740 struct fec_enet_private *fep = netdev_priv(ndev);
742 unsigned short queue;
743 struct fec_enet_priv_tx_q *txq;
744 struct netdev_queue *nq;
747 queue = skb_get_queue_mapping(skb);
748 txq = fep->tx_queue[queue];
749 nq = netdev_get_tx_queue(ndev, queue);
752 ret = fec_enet_txq_submit_tso(txq, skb, ndev);
754 ret = fec_enet_txq_submit_skb(txq, skb, ndev);
758 entries_free = fec_enet_get_free_txdesc_num(txq);
759 if (entries_free <= txq->tx_stop_threshold)
760 netif_tx_stop_queue(nq);
765 /* Init RX & TX buffer descriptors
767 static void fec_enet_bd_init(struct net_device *dev)
769 struct fec_enet_private *fep = netdev_priv(dev);
770 struct fec_enet_priv_tx_q *txq;
771 struct fec_enet_priv_rx_q *rxq;
776 for (q = 0; q < fep->num_rx_queues; q++) {
777 /* Initialize the receive buffer descriptors. */
778 rxq = fep->rx_queue[q];
781 for (i = 0; i < rxq->bd.ring_size; i++) {
783 /* Initialize the BD for every fragment in the page. */
784 if (bdp->cbd_bufaddr)
785 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
787 bdp->cbd_sc = cpu_to_fec16(0);
788 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
791 /* Set the last buffer to wrap */
792 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
793 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
795 rxq->bd.cur = rxq->bd.base;
798 for (q = 0; q < fep->num_tx_queues; q++) {
799 /* ...and the same for transmit */
800 txq = fep->tx_queue[q];
804 for (i = 0; i < txq->bd.ring_size; i++) {
805 /* Initialize the BD for every fragment in the page. */
806 bdp->cbd_sc = cpu_to_fec16(0);
807 if (txq->tx_skbuff[i]) {
808 dev_kfree_skb_any(txq->tx_skbuff[i]);
809 txq->tx_skbuff[i] = NULL;
811 bdp->cbd_bufaddr = cpu_to_fec32(0);
812 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
815 /* Set the last buffer to wrap */
816 bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
817 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
822 static void fec_enet_active_rxring(struct net_device *ndev)
824 struct fec_enet_private *fep = netdev_priv(ndev);
827 for (i = 0; i < fep->num_rx_queues; i++)
828 writel(0, fep->rx_queue[i]->bd.reg_desc_active);
831 static void fec_enet_enable_ring(struct net_device *ndev)
833 struct fec_enet_private *fep = netdev_priv(ndev);
834 struct fec_enet_priv_tx_q *txq;
835 struct fec_enet_priv_rx_q *rxq;
838 for (i = 0; i < fep->num_rx_queues; i++) {
839 rxq = fep->rx_queue[i];
840 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i));
841 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i));
845 writel(RCMR_MATCHEN | RCMR_CMP(i),
846 fep->hwp + FEC_RCMR(i));
849 for (i = 0; i < fep->num_tx_queues; i++) {
850 txq = fep->tx_queue[i];
851 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i));
855 writel(DMA_CLASS_EN | IDLE_SLOPE(i),
856 fep->hwp + FEC_DMA_CFG(i));
860 static void fec_enet_reset_skb(struct net_device *ndev)
862 struct fec_enet_private *fep = netdev_priv(ndev);
863 struct fec_enet_priv_tx_q *txq;
866 for (i = 0; i < fep->num_tx_queues; i++) {
867 txq = fep->tx_queue[i];
869 for (j = 0; j < txq->bd.ring_size; j++) {
870 if (txq->tx_skbuff[j]) {
871 dev_kfree_skb_any(txq->tx_skbuff[j]);
872 txq->tx_skbuff[j] = NULL;
879 * This function is called to start or restart the FEC during a link
880 * change, transmit timeout, or to reconfigure the FEC. The network
881 * packet processing for this device must be stopped before this call.
884 fec_restart(struct net_device *ndev)
886 struct fec_enet_private *fep = netdev_priv(ndev);
889 u32 rcntl = OPT_FRAME_SIZE | 0x04;
890 u32 ecntl = 0x2; /* ETHEREN */
892 /* Whack a reset. We should wait for this.
893 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
894 * instead of reset MAC itself.
896 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
897 writel(0, fep->hwp + FEC_ECNTRL);
899 writel(1, fep->hwp + FEC_ECNTRL);
904 * enet-mac reset will reset mac address registers too,
905 * so need to reconfigure it.
907 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
908 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
909 writel((__force u32)cpu_to_be32(temp_mac[0]),
910 fep->hwp + FEC_ADDR_LOW);
911 writel((__force u32)cpu_to_be32(temp_mac[1]),
912 fep->hwp + FEC_ADDR_HIGH);
915 /* Clear any outstanding interrupt. */
916 writel(0xffffffff, fep->hwp + FEC_IEVENT);
918 fec_enet_bd_init(ndev);
920 fec_enet_enable_ring(ndev);
922 /* Reset tx SKB buffers. */
923 fec_enet_reset_skb(ndev);
925 /* Enable MII mode */
926 if (fep->full_duplex == DUPLEX_FULL) {
928 writel(0x04, fep->hwp + FEC_X_CNTRL);
932 writel(0x0, fep->hwp + FEC_X_CNTRL);
936 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
938 #if !defined(CONFIG_M5272)
939 if (fep->quirks & FEC_QUIRK_HAS_RACC) {
940 /* set RX checksum */
941 val = readl(fep->hwp + FEC_RACC);
942 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
943 val |= FEC_RACC_OPTIONS;
945 val &= ~FEC_RACC_OPTIONS;
946 writel(val, fep->hwp + FEC_RACC);
947 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL);
952 * The phy interface and speed need to get configured
953 * differently on enet-mac.
955 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
956 /* Enable flow control and length check */
957 rcntl |= 0x40000000 | 0x00000020;
959 /* RGMII, RMII or MII */
960 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII ||
961 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
962 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
963 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
965 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
970 /* 1G, 100M or 10M */
972 if (ndev->phydev->speed == SPEED_1000)
974 else if (ndev->phydev->speed == SPEED_100)
980 #ifdef FEC_MIIGSK_ENR
981 if (fep->quirks & FEC_QUIRK_USE_GASKET) {
983 /* disable the gasket and wait */
984 writel(0, fep->hwp + FEC_MIIGSK_ENR);
985 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
989 * configure the gasket:
990 * RMII, 50 MHz, no loopback, no echo
991 * MII, 25 MHz, no loopback, no echo
993 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
994 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
995 if (ndev->phydev && ndev->phydev->speed == SPEED_10)
996 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
997 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
999 /* re-enable the gasket */
1000 writel(2, fep->hwp + FEC_MIIGSK_ENR);
1005 #if !defined(CONFIG_M5272)
1006 /* enable pause frame*/
1007 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
1008 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
1009 ndev->phydev && ndev->phydev->pause)) {
1010 rcntl |= FEC_ENET_FCE;
1012 /* set FIFO threshold parameter to reduce overrun */
1013 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
1014 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
1015 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
1016 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
1019 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
1021 rcntl &= ~FEC_ENET_FCE;
1023 #endif /* !defined(CONFIG_M5272) */
1025 writel(rcntl, fep->hwp + FEC_R_CNTRL);
1027 /* Setup multicast filter. */
1028 set_multicast_list(ndev);
1029 #ifndef CONFIG_M5272
1030 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1031 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1034 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
1035 /* enable ENET endian swap */
1037 /* enable ENET store and forward mode */
1038 writel(1 << 8, fep->hwp + FEC_X_WMRK);
1041 if (fep->bufdesc_ex)
1044 #ifndef CONFIG_M5272
1045 /* Enable the MIB statistic event counters */
1046 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
1049 /* And last, enable the transmit and receive processing */
1050 writel(ecntl, fep->hwp + FEC_ECNTRL);
1051 fec_enet_active_rxring(ndev);
1053 if (fep->bufdesc_ex)
1054 fec_ptp_start_cyclecounter(ndev);
1056 /* Enable interrupts we wish to service */
1058 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1060 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
1062 /* Init the interrupt coalescing */
1063 fec_enet_itr_coal_init(ndev);
1068 fec_stop(struct net_device *ndev)
1070 struct fec_enet_private *fep = netdev_priv(ndev);
1071 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
1072 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
1075 /* We cannot expect a graceful transmit stop without link !!! */
1077 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1079 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
1080 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
1083 /* Whack a reset. We should wait for this.
1084 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1085 * instead of reset MAC itself.
1087 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1088 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
1089 writel(0, fep->hwp + FEC_ECNTRL);
1091 writel(1, fep->hwp + FEC_ECNTRL);
1094 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1096 writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK);
1097 val = readl(fep->hwp + FEC_ECNTRL);
1098 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
1099 writel(val, fep->hwp + FEC_ECNTRL);
1101 if (pdata && pdata->sleep_mode_enable)
1102 pdata->sleep_mode_enable(true);
1104 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1106 /* We have to keep ENET enabled to have MII interrupt stay working */
1107 if (fep->quirks & FEC_QUIRK_ENET_MAC &&
1108 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1109 writel(2, fep->hwp + FEC_ECNTRL);
1110 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1116 fec_timeout(struct net_device *ndev)
1118 struct fec_enet_private *fep = netdev_priv(ndev);
1122 ndev->stats.tx_errors++;
1124 schedule_work(&fep->tx_timeout_work);
1127 static void fec_enet_timeout_work(struct work_struct *work)
1129 struct fec_enet_private *fep =
1130 container_of(work, struct fec_enet_private, tx_timeout_work);
1131 struct net_device *ndev = fep->netdev;
1134 if (netif_device_present(ndev) || netif_running(ndev)) {
1135 napi_disable(&fep->napi);
1136 netif_tx_lock_bh(ndev);
1138 netif_wake_queue(ndev);
1139 netif_tx_unlock_bh(ndev);
1140 napi_enable(&fep->napi);
1146 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts,
1147 struct skb_shared_hwtstamps *hwtstamps)
1149 unsigned long flags;
1152 spin_lock_irqsave(&fep->tmreg_lock, flags);
1153 ns = timecounter_cyc2time(&fep->tc, ts);
1154 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1156 memset(hwtstamps, 0, sizeof(*hwtstamps));
1157 hwtstamps->hwtstamp = ns_to_ktime(ns);
1161 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id)
1163 struct fec_enet_private *fep;
1164 struct bufdesc *bdp;
1165 unsigned short status;
1166 struct sk_buff *skb;
1167 struct fec_enet_priv_tx_q *txq;
1168 struct netdev_queue *nq;
1172 fep = netdev_priv(ndev);
1174 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1176 txq = fep->tx_queue[queue_id];
1177 /* get next bdp of dirty_tx */
1178 nq = netdev_get_tx_queue(ndev, queue_id);
1179 bdp = txq->dirty_tx;
1181 /* get next bdp of dirty_tx */
1182 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1184 while (bdp != READ_ONCE(txq->bd.cur)) {
1185 /* Order the load of bd.cur and cbd_sc */
1187 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc));
1188 if (status & BD_ENET_TX_READY)
1191 index = fec_enet_get_bd_index(bdp, &txq->bd);
1193 skb = txq->tx_skbuff[index];
1194 txq->tx_skbuff[index] = NULL;
1195 if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
1196 dma_unmap_single(&fep->pdev->dev,
1197 fec32_to_cpu(bdp->cbd_bufaddr),
1198 fec16_to_cpu(bdp->cbd_datlen),
1200 bdp->cbd_bufaddr = cpu_to_fec32(0);
1204 /* Check for errors. */
1205 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1206 BD_ENET_TX_RL | BD_ENET_TX_UN |
1208 ndev->stats.tx_errors++;
1209 if (status & BD_ENET_TX_HB) /* No heartbeat */
1210 ndev->stats.tx_heartbeat_errors++;
1211 if (status & BD_ENET_TX_LC) /* Late collision */
1212 ndev->stats.tx_window_errors++;
1213 if (status & BD_ENET_TX_RL) /* Retrans limit */
1214 ndev->stats.tx_aborted_errors++;
1215 if (status & BD_ENET_TX_UN) /* Underrun */
1216 ndev->stats.tx_fifo_errors++;
1217 if (status & BD_ENET_TX_CSL) /* Carrier lost */
1218 ndev->stats.tx_carrier_errors++;
1220 ndev->stats.tx_packets++;
1221 ndev->stats.tx_bytes += skb->len;
1224 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
1226 struct skb_shared_hwtstamps shhwtstamps;
1227 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1229 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps);
1230 skb_tstamp_tx(skb, &shhwtstamps);
1233 /* Deferred means some collisions occurred during transmit,
1234 * but we eventually sent the packet OK.
1236 if (status & BD_ENET_TX_DEF)
1237 ndev->stats.collisions++;
1239 /* Free the sk buffer associated with this last transmit */
1240 dev_kfree_skb_any(skb);
1242 /* Make sure the update to bdp and tx_skbuff are performed
1246 txq->dirty_tx = bdp;
1248 /* Update pointer to next buffer descriptor to be transmitted */
1249 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1251 /* Since we have freed up a buffer, the ring is no longer full
1253 if (netif_queue_stopped(ndev)) {
1254 entries_free = fec_enet_get_free_txdesc_num(txq);
1255 if (entries_free >= txq->tx_wake_threshold)
1256 netif_tx_wake_queue(nq);
1260 /* ERR006538: Keep the transmitter going */
1261 if (bdp != txq->bd.cur &&
1262 readl(txq->bd.reg_desc_active) == 0)
1263 writel(0, txq->bd.reg_desc_active);
1267 fec_enet_tx(struct net_device *ndev)
1269 struct fec_enet_private *fep = netdev_priv(ndev);
1271 /* First process class A queue, then Class B and Best Effort queue */
1272 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) {
1273 clear_bit(queue_id, &fep->work_tx);
1274 fec_enet_tx_queue(ndev, queue_id);
1280 fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb)
1282 struct fec_enet_private *fep = netdev_priv(ndev);
1285 off = ((unsigned long)skb->data) & fep->rx_align;
1287 skb_reserve(skb, fep->rx_align + 1 - off);
1289 bdp->cbd_bufaddr = cpu_to_fec32(dma_map_single(&fep->pdev->dev, skb->data, FEC_ENET_RX_FRSIZE - fep->rx_align, DMA_FROM_DEVICE));
1290 if (dma_mapping_error(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr))) {
1291 if (net_ratelimit())
1292 netdev_err(ndev, "Rx DMA memory map failed\n");
1299 static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb,
1300 struct bufdesc *bdp, u32 length, bool swap)
1302 struct fec_enet_private *fep = netdev_priv(ndev);
1303 struct sk_buff *new_skb;
1305 if (length > fep->rx_copybreak)
1308 new_skb = netdev_alloc_skb(ndev, length);
1312 dma_sync_single_for_cpu(&fep->pdev->dev,
1313 fec32_to_cpu(bdp->cbd_bufaddr),
1314 FEC_ENET_RX_FRSIZE - fep->rx_align,
1317 memcpy(new_skb->data, (*skb)->data, length);
1319 swap_buffer2(new_skb->data, (*skb)->data, length);
1325 /* During a receive, the bd_rx.cur points to the current incoming buffer.
1326 * When we update through the ring, if the next incoming buffer has
1327 * not been given to the system, we just set the empty indicator,
1328 * effectively tossing the packet.
1331 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id)
1333 struct fec_enet_private *fep = netdev_priv(ndev);
1334 struct fec_enet_priv_rx_q *rxq;
1335 struct bufdesc *bdp;
1336 unsigned short status;
1337 struct sk_buff *skb_new = NULL;
1338 struct sk_buff *skb;
1341 int pkt_received = 0;
1342 struct bufdesc_ex *ebdp = NULL;
1343 bool vlan_packet_rcvd = false;
1347 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME;
1352 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1353 rxq = fep->rx_queue[queue_id];
1355 /* First, grab all of the stats for the incoming packet.
1356 * These get messed up if we get called due to a busy condition.
1360 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) {
1362 if (pkt_received >= budget)
1366 writel(FEC_ENET_RXF, fep->hwp + FEC_IEVENT);
1368 /* Check for errors. */
1369 status ^= BD_ENET_RX_LAST;
1370 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1371 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST |
1373 ndev->stats.rx_errors++;
1374 if (status & BD_ENET_RX_OV) {
1376 ndev->stats.rx_fifo_errors++;
1377 goto rx_processing_done;
1379 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH
1380 | BD_ENET_RX_LAST)) {
1381 /* Frame too long or too short. */
1382 ndev->stats.rx_length_errors++;
1383 if (status & BD_ENET_RX_LAST)
1384 netdev_err(ndev, "rcv is not +last\n");
1386 if (status & BD_ENET_RX_CR) /* CRC Error */
1387 ndev->stats.rx_crc_errors++;
1388 /* Report late collisions as a frame error. */
1389 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL))
1390 ndev->stats.rx_frame_errors++;
1391 goto rx_processing_done;
1394 /* Process the incoming frame. */
1395 ndev->stats.rx_packets++;
1396 pkt_len = fec16_to_cpu(bdp->cbd_datlen);
1397 ndev->stats.rx_bytes += pkt_len;
1399 index = fec_enet_get_bd_index(bdp, &rxq->bd);
1400 skb = rxq->rx_skbuff[index];
1402 /* The packet length includes FCS, but we don't want to
1403 * include that when passing upstream as it messes up
1404 * bridging applications.
1406 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4,
1408 if (!is_copybreak) {
1409 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1410 if (unlikely(!skb_new)) {
1411 ndev->stats.rx_dropped++;
1412 goto rx_processing_done;
1414 dma_unmap_single(&fep->pdev->dev,
1415 fec32_to_cpu(bdp->cbd_bufaddr),
1416 FEC_ENET_RX_FRSIZE - fep->rx_align,
1420 prefetch(skb->data - NET_IP_ALIGN);
1421 skb_put(skb, pkt_len - 4);
1423 if (!is_copybreak && need_swap)
1424 swap_buffer(data, pkt_len);
1426 /* Extract the enhanced buffer descriptor */
1428 if (fep->bufdesc_ex)
1429 ebdp = (struct bufdesc_ex *)bdp;
1431 /* If this is a VLAN packet remove the VLAN Tag */
1432 vlan_packet_rcvd = false;
1433 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1435 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) {
1436 /* Push and remove the vlan tag */
1437 struct vlan_hdr *vlan_header =
1438 (struct vlan_hdr *) (data + ETH_HLEN);
1439 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
1441 vlan_packet_rcvd = true;
1443 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2);
1444 skb_pull(skb, VLAN_HLEN);
1447 skb->protocol = eth_type_trans(skb, ndev);
1449 /* Get receive timestamp from the skb */
1450 if (fep->hwts_rx_en && fep->bufdesc_ex)
1451 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts),
1452 skb_hwtstamps(skb));
1454 if (fep->bufdesc_ex &&
1455 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
1456 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) {
1457 /* don't check it */
1458 skb->ip_summed = CHECKSUM_UNNECESSARY;
1460 skb_checksum_none_assert(skb);
1464 /* Handle received VLAN packets */
1465 if (vlan_packet_rcvd)
1466 __vlan_hwaccel_put_tag(skb,
1470 napi_gro_receive(&fep->napi, skb);
1473 dma_sync_single_for_device(&fep->pdev->dev,
1474 fec32_to_cpu(bdp->cbd_bufaddr),
1475 FEC_ENET_RX_FRSIZE - fep->rx_align,
1478 rxq->rx_skbuff[index] = skb_new;
1479 fec_enet_new_rxbdp(ndev, bdp, skb_new);
1483 /* Clear the status flags for this buffer */
1484 status &= ~BD_ENET_RX_STATS;
1486 /* Mark the buffer empty */
1487 status |= BD_ENET_RX_EMPTY;
1489 if (fep->bufdesc_ex) {
1490 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1492 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
1496 /* Make sure the updates to rest of the descriptor are
1497 * performed before transferring ownership.
1500 bdp->cbd_sc = cpu_to_fec16(status);
1502 /* Update BD pointer to next entry */
1503 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
1505 /* Doing this here will keep the FEC running while we process
1506 * incoming frames. On a heavily loaded network, we should be
1507 * able to keep up at the expense of system resources.
1509 writel(0, rxq->bd.reg_desc_active);
1512 return pkt_received;
1516 fec_enet_rx(struct net_device *ndev, int budget)
1518 int pkt_received = 0;
1520 struct fec_enet_private *fep = netdev_priv(ndev);
1522 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) {
1525 ret = fec_enet_rx_queue(ndev,
1526 budget - pkt_received, queue_id);
1528 if (ret < budget - pkt_received)
1529 clear_bit(queue_id, &fep->work_rx);
1531 pkt_received += ret;
1533 return pkt_received;
1537 fec_enet_collect_events(struct fec_enet_private *fep, uint int_events)
1539 if (int_events == 0)
1542 if (int_events & FEC_ENET_RXF)
1543 fep->work_rx |= (1 << 2);
1544 if (int_events & FEC_ENET_RXF_1)
1545 fep->work_rx |= (1 << 0);
1546 if (int_events & FEC_ENET_RXF_2)
1547 fep->work_rx |= (1 << 1);
1549 if (int_events & FEC_ENET_TXF)
1550 fep->work_tx |= (1 << 2);
1551 if (int_events & FEC_ENET_TXF_1)
1552 fep->work_tx |= (1 << 0);
1553 if (int_events & FEC_ENET_TXF_2)
1554 fep->work_tx |= (1 << 1);
1560 fec_enet_interrupt(int irq, void *dev_id)
1562 struct net_device *ndev = dev_id;
1563 struct fec_enet_private *fep = netdev_priv(ndev);
1565 irqreturn_t ret = IRQ_NONE;
1567 int_events = readl(fep->hwp + FEC_IEVENT);
1568 writel(int_events, fep->hwp + FEC_IEVENT);
1569 fec_enet_collect_events(fep, int_events);
1571 if ((fep->work_tx || fep->work_rx) && fep->link) {
1574 if (napi_schedule_prep(&fep->napi)) {
1575 /* Disable the NAPI interrupts */
1576 writel(FEC_NAPI_IMASK, fep->hwp + FEC_IMASK);
1577 __napi_schedule(&fep->napi);
1581 if (int_events & FEC_ENET_MII) {
1583 complete(&fep->mdio_done);
1587 fec_ptp_check_pps_event(fep);
1592 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1594 struct net_device *ndev = napi->dev;
1595 struct fec_enet_private *fep = netdev_priv(ndev);
1598 pkts = fec_enet_rx(ndev, budget);
1602 if (pkts < budget) {
1603 napi_complete(napi);
1604 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1609 /* ------------------------------------------------------------------------- */
1610 static void fec_get_mac(struct net_device *ndev)
1612 struct fec_enet_private *fep = netdev_priv(ndev);
1613 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
1614 unsigned char *iap, tmpaddr[ETH_ALEN];
1617 * try to get mac address in following order:
1619 * 1) module parameter via kernel command line in form
1620 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1625 * 2) from device tree data
1627 if (!is_valid_ether_addr(iap)) {
1628 struct device_node *np = fep->pdev->dev.of_node;
1630 const char *mac = of_get_mac_address(np);
1632 iap = (unsigned char *) mac;
1637 * 3) from flash or fuse (via platform data)
1639 if (!is_valid_ether_addr(iap)) {
1642 iap = (unsigned char *)FEC_FLASHMAC;
1645 iap = (unsigned char *)&pdata->mac;
1650 * 4) FEC mac registers set by bootloader
1652 if (!is_valid_ether_addr(iap)) {
1653 *((__be32 *) &tmpaddr[0]) =
1654 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1655 *((__be16 *) &tmpaddr[4]) =
1656 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1661 * 5) random mac address
1663 if (!is_valid_ether_addr(iap)) {
1664 /* Report it and use a random ethernet address instead */
1665 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1666 eth_hw_addr_random(ndev);
1667 netdev_info(ndev, "Using random MAC address: %pM\n",
1672 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1674 /* Adjust MAC if using macaddr */
1676 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1679 /* ------------------------------------------------------------------------- */
1684 static void fec_enet_adjust_link(struct net_device *ndev)
1686 struct fec_enet_private *fep = netdev_priv(ndev);
1687 struct phy_device *phy_dev = ndev->phydev;
1688 int status_change = 0;
1690 /* Prevent a state halted on mii error */
1691 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1692 phy_dev->state = PHY_RESUMING;
1697 * If the netdev is down, or is going down, we're not interested
1698 * in link state events, so just mark our idea of the link as down
1699 * and ignore the event.
1701 if (!netif_running(ndev) || !netif_device_present(ndev)) {
1703 } else if (phy_dev->link) {
1705 fep->link = phy_dev->link;
1709 if (fep->full_duplex != phy_dev->duplex) {
1710 fep->full_duplex = phy_dev->duplex;
1714 if (phy_dev->speed != fep->speed) {
1715 fep->speed = phy_dev->speed;
1719 /* if any of the above changed restart the FEC */
1720 if (status_change) {
1721 napi_disable(&fep->napi);
1722 netif_tx_lock_bh(ndev);
1724 netif_wake_queue(ndev);
1725 netif_tx_unlock_bh(ndev);
1726 napi_enable(&fep->napi);
1730 napi_disable(&fep->napi);
1731 netif_tx_lock_bh(ndev);
1733 netif_tx_unlock_bh(ndev);
1734 napi_enable(&fep->napi);
1735 fep->link = phy_dev->link;
1741 phy_print_status(phy_dev);
1744 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1746 struct fec_enet_private *fep = bus->priv;
1747 struct device *dev = &fep->pdev->dev;
1748 unsigned long time_left;
1751 ret = pm_runtime_get_sync(dev);
1755 fep->mii_timeout = 0;
1756 reinit_completion(&fep->mdio_done);
1758 /* start a read op */
1759 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1760 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1761 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1763 /* wait for end of transfer */
1764 time_left = wait_for_completion_timeout(&fep->mdio_done,
1765 usecs_to_jiffies(FEC_MII_TIMEOUT));
1766 if (time_left == 0) {
1767 fep->mii_timeout = 1;
1768 netdev_err(fep->netdev, "MDIO read timeout\n");
1773 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1776 pm_runtime_mark_last_busy(dev);
1777 pm_runtime_put_autosuspend(dev);
1782 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1785 struct fec_enet_private *fep = bus->priv;
1786 struct device *dev = &fep->pdev->dev;
1787 unsigned long time_left;
1790 ret = pm_runtime_get_sync(dev);
1796 fep->mii_timeout = 0;
1797 reinit_completion(&fep->mdio_done);
1799 /* start a write op */
1800 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1801 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1802 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1803 fep->hwp + FEC_MII_DATA);
1805 /* wait for end of transfer */
1806 time_left = wait_for_completion_timeout(&fep->mdio_done,
1807 usecs_to_jiffies(FEC_MII_TIMEOUT));
1808 if (time_left == 0) {
1809 fep->mii_timeout = 1;
1810 netdev_err(fep->netdev, "MDIO write timeout\n");
1814 pm_runtime_mark_last_busy(dev);
1815 pm_runtime_put_autosuspend(dev);
1820 static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
1822 struct fec_enet_private *fep = netdev_priv(ndev);
1826 ret = clk_prepare_enable(fep->clk_ahb);
1829 if (fep->clk_enet_out) {
1830 ret = clk_prepare_enable(fep->clk_enet_out);
1832 goto failed_clk_enet_out;
1835 mutex_lock(&fep->ptp_clk_mutex);
1836 ret = clk_prepare_enable(fep->clk_ptp);
1838 mutex_unlock(&fep->ptp_clk_mutex);
1839 goto failed_clk_ptp;
1841 fep->ptp_clk_on = true;
1843 mutex_unlock(&fep->ptp_clk_mutex);
1846 ret = clk_prepare_enable(fep->clk_ref);
1848 goto failed_clk_ref;
1851 clk_disable_unprepare(fep->clk_ahb);
1852 if (fep->clk_enet_out)
1853 clk_disable_unprepare(fep->clk_enet_out);
1855 mutex_lock(&fep->ptp_clk_mutex);
1856 clk_disable_unprepare(fep->clk_ptp);
1857 fep->ptp_clk_on = false;
1858 mutex_unlock(&fep->ptp_clk_mutex);
1861 clk_disable_unprepare(fep->clk_ref);
1868 clk_disable_unprepare(fep->clk_ref);
1870 if (fep->clk_enet_out)
1871 clk_disable_unprepare(fep->clk_enet_out);
1872 failed_clk_enet_out:
1873 clk_disable_unprepare(fep->clk_ahb);
1878 static int fec_enet_mii_probe(struct net_device *ndev)
1880 struct fec_enet_private *fep = netdev_priv(ndev);
1881 struct phy_device *phy_dev = NULL;
1882 char mdio_bus_id[MII_BUS_ID_SIZE];
1883 char phy_name[MII_BUS_ID_SIZE + 3];
1885 int dev_id = fep->dev_id;
1887 if (fep->phy_node) {
1888 phy_dev = of_phy_connect(ndev, fep->phy_node,
1889 &fec_enet_adjust_link, 0,
1890 fep->phy_interface);
1894 /* check for attached phy */
1895 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1896 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id))
1900 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1904 if (phy_id >= PHY_MAX_ADDR) {
1905 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
1906 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1910 snprintf(phy_name, sizeof(phy_name),
1911 PHY_ID_FMT, mdio_bus_id, phy_id);
1912 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1913 fep->phy_interface);
1916 if (IS_ERR(phy_dev)) {
1917 netdev_err(ndev, "could not attach to PHY\n");
1918 return PTR_ERR(phy_dev);
1921 /* mask with MAC supported features */
1922 if (fep->quirks & FEC_QUIRK_HAS_GBIT) {
1923 phy_dev->supported &= PHY_GBIT_FEATURES;
1924 phy_dev->supported &= ~SUPPORTED_1000baseT_Half;
1925 #if !defined(CONFIG_M5272)
1926 phy_dev->supported |= SUPPORTED_Pause;
1930 phy_dev->supported &= PHY_BASIC_FEATURES;
1932 phy_dev->advertising = phy_dev->supported;
1935 fep->full_duplex = 0;
1937 phy_attached_info(phy_dev);
1942 static int fec_enet_mii_init(struct platform_device *pdev)
1944 static struct mii_bus *fec0_mii_bus;
1945 struct net_device *ndev = platform_get_drvdata(pdev);
1946 struct fec_enet_private *fep = netdev_priv(ndev);
1947 struct device_node *node;
1949 u32 mii_speed, holdtime;
1952 * The i.MX28 dual fec interfaces are not equal.
1953 * Here are the differences:
1955 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1956 * - fec0 acts as the 1588 time master while fec1 is slave
1957 * - external phys can only be configured by fec0
1959 * That is to say fec1 can not work independently. It only works
1960 * when fec0 is working. The reason behind this design is that the
1961 * second interface is added primarily for Switch mode.
1963 * Because of the last point above, both phys are attached on fec0
1964 * mdio interface in board design, and need to be configured by
1967 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) {
1968 /* fec1 uses fec0 mii_bus */
1969 if (mii_cnt && fec0_mii_bus) {
1970 fep->mii_bus = fec0_mii_bus;
1977 fep->mii_timeout = 0;
1980 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
1982 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1983 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1984 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1987 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000);
1988 if (fep->quirks & FEC_QUIRK_ENET_MAC)
1990 if (mii_speed > 63) {
1992 "fec clock (%lu) to fast to get right mii speed\n",
1993 clk_get_rate(fep->clk_ipg));
1999 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka
2000 * MII_SPEED) register that defines the MDIO output hold time. Earlier
2001 * versions are RAZ there, so just ignore the difference and write the
2003 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
2004 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
2006 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
2007 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
2008 * holdtime cannot result in a value greater than 3.
2010 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1;
2012 fep->phy_speed = mii_speed << 1 | holdtime << 8;
2014 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
2016 fep->mii_bus = mdiobus_alloc();
2017 if (fep->mii_bus == NULL) {
2022 fep->mii_bus->name = "fec_enet_mii_bus";
2023 fep->mii_bus->read = fec_enet_mdio_read;
2024 fep->mii_bus->write = fec_enet_mdio_write;
2025 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2026 pdev->name, fep->dev_id + 1);
2027 fep->mii_bus->priv = fep;
2028 fep->mii_bus->parent = &pdev->dev;
2030 node = of_get_child_by_name(pdev->dev.of_node, "mdio");
2032 err = of_mdiobus_register(fep->mii_bus, node);
2035 err = mdiobus_register(fep->mii_bus);
2039 goto err_out_free_mdiobus;
2043 /* save fec0 mii_bus */
2044 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO)
2045 fec0_mii_bus = fep->mii_bus;
2049 err_out_free_mdiobus:
2050 mdiobus_free(fep->mii_bus);
2055 static void fec_enet_mii_remove(struct fec_enet_private *fep)
2057 if (--mii_cnt == 0) {
2058 mdiobus_unregister(fep->mii_bus);
2059 mdiobus_free(fep->mii_bus);
2063 static void fec_enet_get_drvinfo(struct net_device *ndev,
2064 struct ethtool_drvinfo *info)
2066 struct fec_enet_private *fep = netdev_priv(ndev);
2068 strlcpy(info->driver, fep->pdev->dev.driver->name,
2069 sizeof(info->driver));
2070 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
2071 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
2074 static int fec_enet_get_regs_len(struct net_device *ndev)
2076 struct fec_enet_private *fep = netdev_priv(ndev);
2080 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0);
2082 s = resource_size(r);
2087 /* List of registers that can be safety be read to dump them with ethtool */
2088 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
2089 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
2090 static u32 fec_enet_register_offset[] = {
2091 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0,
2092 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL,
2093 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1,
2094 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH,
2095 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW,
2096 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1,
2097 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2,
2098 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0,
2099 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM,
2100 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2,
2101 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1,
2102 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME,
2103 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT,
2104 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG,
2105 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255,
2106 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047,
2107 RMON_T_P_GTE2048, RMON_T_OCTETS,
2108 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF,
2109 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE,
2110 IEEE_T_FDXFC, IEEE_T_OCTETS_OK,
2111 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN,
2112 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB,
2113 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255,
2114 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047,
2115 RMON_R_P_GTE2048, RMON_R_OCTETS,
2116 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR,
2117 IEEE_R_FDXFC, IEEE_R_OCTETS_OK
2120 static u32 fec_enet_register_offset[] = {
2121 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0,
2122 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0,
2123 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED,
2124 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL,
2125 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH,
2126 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0,
2127 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0,
2128 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0,
2129 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2
2133 static void fec_enet_get_regs(struct net_device *ndev,
2134 struct ethtool_regs *regs, void *regbuf)
2136 struct fec_enet_private *fep = netdev_priv(ndev);
2137 u32 __iomem *theregs = (u32 __iomem *)fep->hwp;
2138 u32 *buf = (u32 *)regbuf;
2141 memset(buf, 0, regs->len);
2143 for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) {
2144 off = fec_enet_register_offset[i] / 4;
2145 buf[off] = readl(&theregs[off]);
2149 static int fec_enet_get_ts_info(struct net_device *ndev,
2150 struct ethtool_ts_info *info)
2152 struct fec_enet_private *fep = netdev_priv(ndev);
2154 if (fep->bufdesc_ex) {
2156 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2157 SOF_TIMESTAMPING_RX_SOFTWARE |
2158 SOF_TIMESTAMPING_SOFTWARE |
2159 SOF_TIMESTAMPING_TX_HARDWARE |
2160 SOF_TIMESTAMPING_RX_HARDWARE |
2161 SOF_TIMESTAMPING_RAW_HARDWARE;
2163 info->phc_index = ptp_clock_index(fep->ptp_clock);
2165 info->phc_index = -1;
2167 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
2168 (1 << HWTSTAMP_TX_ON);
2170 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
2171 (1 << HWTSTAMP_FILTER_ALL);
2174 return ethtool_op_get_ts_info(ndev, info);
2178 #if !defined(CONFIG_M5272)
2180 static void fec_enet_get_pauseparam(struct net_device *ndev,
2181 struct ethtool_pauseparam *pause)
2183 struct fec_enet_private *fep = netdev_priv(ndev);
2185 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
2186 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
2187 pause->rx_pause = pause->tx_pause;
2190 static int fec_enet_set_pauseparam(struct net_device *ndev,
2191 struct ethtool_pauseparam *pause)
2193 struct fec_enet_private *fep = netdev_priv(ndev);
2198 if (pause->tx_pause != pause->rx_pause) {
2200 "hardware only support enable/disable both tx and rx");
2204 fep->pause_flag = 0;
2206 /* tx pause must be same as rx pause */
2207 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
2208 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
2210 if (pause->rx_pause || pause->autoneg) {
2211 ndev->phydev->supported |= ADVERTISED_Pause;
2212 ndev->phydev->advertising |= ADVERTISED_Pause;
2214 ndev->phydev->supported &= ~ADVERTISED_Pause;
2215 ndev->phydev->advertising &= ~ADVERTISED_Pause;
2218 if (pause->autoneg) {
2219 if (netif_running(ndev))
2221 phy_start_aneg(ndev->phydev);
2223 if (netif_running(ndev)) {
2224 napi_disable(&fep->napi);
2225 netif_tx_lock_bh(ndev);
2227 netif_wake_queue(ndev);
2228 netif_tx_unlock_bh(ndev);
2229 napi_enable(&fep->napi);
2235 static const struct fec_stat {
2236 char name[ETH_GSTRING_LEN];
2240 { "tx_dropped", RMON_T_DROP },
2241 { "tx_packets", RMON_T_PACKETS },
2242 { "tx_broadcast", RMON_T_BC_PKT },
2243 { "tx_multicast", RMON_T_MC_PKT },
2244 { "tx_crc_errors", RMON_T_CRC_ALIGN },
2245 { "tx_undersize", RMON_T_UNDERSIZE },
2246 { "tx_oversize", RMON_T_OVERSIZE },
2247 { "tx_fragment", RMON_T_FRAG },
2248 { "tx_jabber", RMON_T_JAB },
2249 { "tx_collision", RMON_T_COL },
2250 { "tx_64byte", RMON_T_P64 },
2251 { "tx_65to127byte", RMON_T_P65TO127 },
2252 { "tx_128to255byte", RMON_T_P128TO255 },
2253 { "tx_256to511byte", RMON_T_P256TO511 },
2254 { "tx_512to1023byte", RMON_T_P512TO1023 },
2255 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
2256 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
2257 { "tx_octets", RMON_T_OCTETS },
2260 { "IEEE_tx_drop", IEEE_T_DROP },
2261 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
2262 { "IEEE_tx_1col", IEEE_T_1COL },
2263 { "IEEE_tx_mcol", IEEE_T_MCOL },
2264 { "IEEE_tx_def", IEEE_T_DEF },
2265 { "IEEE_tx_lcol", IEEE_T_LCOL },
2266 { "IEEE_tx_excol", IEEE_T_EXCOL },
2267 { "IEEE_tx_macerr", IEEE_T_MACERR },
2268 { "IEEE_tx_cserr", IEEE_T_CSERR },
2269 { "IEEE_tx_sqe", IEEE_T_SQE },
2270 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
2271 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
2274 { "rx_packets", RMON_R_PACKETS },
2275 { "rx_broadcast", RMON_R_BC_PKT },
2276 { "rx_multicast", RMON_R_MC_PKT },
2277 { "rx_crc_errors", RMON_R_CRC_ALIGN },
2278 { "rx_undersize", RMON_R_UNDERSIZE },
2279 { "rx_oversize", RMON_R_OVERSIZE },
2280 { "rx_fragment", RMON_R_FRAG },
2281 { "rx_jabber", RMON_R_JAB },
2282 { "rx_64byte", RMON_R_P64 },
2283 { "rx_65to127byte", RMON_R_P65TO127 },
2284 { "rx_128to255byte", RMON_R_P128TO255 },
2285 { "rx_256to511byte", RMON_R_P256TO511 },
2286 { "rx_512to1023byte", RMON_R_P512TO1023 },
2287 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
2288 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
2289 { "rx_octets", RMON_R_OCTETS },
2292 { "IEEE_rx_drop", IEEE_R_DROP },
2293 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
2294 { "IEEE_rx_crc", IEEE_R_CRC },
2295 { "IEEE_rx_align", IEEE_R_ALIGN },
2296 { "IEEE_rx_macerr", IEEE_R_MACERR },
2297 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
2298 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
2301 static void fec_enet_get_ethtool_stats(struct net_device *dev,
2302 struct ethtool_stats *stats, u64 *data)
2304 struct fec_enet_private *fep = netdev_priv(dev);
2307 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2308 data[i] = readl(fep->hwp + fec_stats[i].offset);
2311 static void fec_enet_get_strings(struct net_device *netdev,
2312 u32 stringset, u8 *data)
2315 switch (stringset) {
2317 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2318 memcpy(data + i * ETH_GSTRING_LEN,
2319 fec_stats[i].name, ETH_GSTRING_LEN);
2324 static int fec_enet_get_sset_count(struct net_device *dev, int sset)
2328 return ARRAY_SIZE(fec_stats);
2333 #endif /* !defined(CONFIG_M5272) */
2335 static int fec_enet_nway_reset(struct net_device *dev)
2337 struct phy_device *phydev = dev->phydev;
2342 return genphy_restart_aneg(phydev);
2345 /* ITR clock source is enet system clock (clk_ahb).
2346 * TCTT unit is cycle_ns * 64 cycle
2347 * So, the ICTT value = X us / (cycle_ns * 64)
2349 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us)
2351 struct fec_enet_private *fep = netdev_priv(ndev);
2353 return us * (fep->itr_clk_rate / 64000) / 1000;
2356 /* Set threshold for interrupt coalescing */
2357 static void fec_enet_itr_coal_set(struct net_device *ndev)
2359 struct fec_enet_private *fep = netdev_priv(ndev);
2362 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
2365 /* Must be greater than zero to avoid unpredictable behavior */
2366 if (!fep->rx_time_itr || !fep->rx_pkts_itr ||
2367 !fep->tx_time_itr || !fep->tx_pkts_itr)
2370 /* Select enet system clock as Interrupt Coalescing
2371 * timer Clock Source
2373 rx_itr = FEC_ITR_CLK_SEL;
2374 tx_itr = FEC_ITR_CLK_SEL;
2376 /* set ICFT and ICTT */
2377 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr);
2378 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr));
2379 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr);
2380 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr));
2382 rx_itr |= FEC_ITR_EN;
2383 tx_itr |= FEC_ITR_EN;
2385 writel(tx_itr, fep->hwp + FEC_TXIC0);
2386 writel(rx_itr, fep->hwp + FEC_RXIC0);
2387 writel(tx_itr, fep->hwp + FEC_TXIC1);
2388 writel(rx_itr, fep->hwp + FEC_RXIC1);
2389 writel(tx_itr, fep->hwp + FEC_TXIC2);
2390 writel(rx_itr, fep->hwp + FEC_RXIC2);
2394 fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2396 struct fec_enet_private *fep = netdev_priv(ndev);
2398 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
2401 ec->rx_coalesce_usecs = fep->rx_time_itr;
2402 ec->rx_max_coalesced_frames = fep->rx_pkts_itr;
2404 ec->tx_coalesce_usecs = fep->tx_time_itr;
2405 ec->tx_max_coalesced_frames = fep->tx_pkts_itr;
2411 fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2413 struct fec_enet_private *fep = netdev_priv(ndev);
2416 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
2419 if (ec->rx_max_coalesced_frames > 255) {
2420 pr_err("Rx coalesced frames exceed hardware limitation\n");
2424 if (ec->tx_max_coalesced_frames > 255) {
2425 pr_err("Tx coalesced frame exceed hardware limitation\n");
2429 cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr);
2430 if (cycle > 0xFFFF) {
2431 pr_err("Rx coalesced usec exceed hardware limitation\n");
2435 cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr);
2436 if (cycle > 0xFFFF) {
2437 pr_err("Rx coalesced usec exceed hardware limitation\n");
2441 fep->rx_time_itr = ec->rx_coalesce_usecs;
2442 fep->rx_pkts_itr = ec->rx_max_coalesced_frames;
2444 fep->tx_time_itr = ec->tx_coalesce_usecs;
2445 fep->tx_pkts_itr = ec->tx_max_coalesced_frames;
2447 fec_enet_itr_coal_set(ndev);
2452 static void fec_enet_itr_coal_init(struct net_device *ndev)
2454 struct ethtool_coalesce ec;
2456 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2457 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2459 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2460 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2462 fec_enet_set_coalesce(ndev, &ec);
2465 static int fec_enet_get_tunable(struct net_device *netdev,
2466 const struct ethtool_tunable *tuna,
2469 struct fec_enet_private *fep = netdev_priv(netdev);
2473 case ETHTOOL_RX_COPYBREAK:
2474 *(u32 *)data = fep->rx_copybreak;
2484 static int fec_enet_set_tunable(struct net_device *netdev,
2485 const struct ethtool_tunable *tuna,
2488 struct fec_enet_private *fep = netdev_priv(netdev);
2492 case ETHTOOL_RX_COPYBREAK:
2493 fep->rx_copybreak = *(u32 *)data;
2504 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2506 struct fec_enet_private *fep = netdev_priv(ndev);
2508 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) {
2509 wol->supported = WAKE_MAGIC;
2510 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0;
2512 wol->supported = wol->wolopts = 0;
2517 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2519 struct fec_enet_private *fep = netdev_priv(ndev);
2521 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET))
2524 if (wol->wolopts & ~WAKE_MAGIC)
2527 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC);
2528 if (device_may_wakeup(&ndev->dev)) {
2529 fep->wol_flag |= FEC_WOL_FLAG_ENABLE;
2530 if (fep->irq[0] > 0)
2531 enable_irq_wake(fep->irq[0]);
2533 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE);
2534 if (fep->irq[0] > 0)
2535 disable_irq_wake(fep->irq[0]);
2541 static const struct ethtool_ops fec_enet_ethtool_ops = {
2542 .get_drvinfo = fec_enet_get_drvinfo,
2543 .get_regs_len = fec_enet_get_regs_len,
2544 .get_regs = fec_enet_get_regs,
2545 .nway_reset = fec_enet_nway_reset,
2546 .get_link = ethtool_op_get_link,
2547 .get_coalesce = fec_enet_get_coalesce,
2548 .set_coalesce = fec_enet_set_coalesce,
2549 #ifndef CONFIG_M5272
2550 .get_pauseparam = fec_enet_get_pauseparam,
2551 .set_pauseparam = fec_enet_set_pauseparam,
2552 .get_strings = fec_enet_get_strings,
2553 .get_ethtool_stats = fec_enet_get_ethtool_stats,
2554 .get_sset_count = fec_enet_get_sset_count,
2556 .get_ts_info = fec_enet_get_ts_info,
2557 .get_tunable = fec_enet_get_tunable,
2558 .set_tunable = fec_enet_set_tunable,
2559 .get_wol = fec_enet_get_wol,
2560 .set_wol = fec_enet_set_wol,
2561 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2562 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2565 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2567 struct fec_enet_private *fep = netdev_priv(ndev);
2568 struct phy_device *phydev = ndev->phydev;
2570 if (!netif_running(ndev))
2576 if (fep->bufdesc_ex) {
2577 if (cmd == SIOCSHWTSTAMP)
2578 return fec_ptp_set(ndev, rq);
2579 if (cmd == SIOCGHWTSTAMP)
2580 return fec_ptp_get(ndev, rq);
2583 return phy_mii_ioctl(phydev, rq, cmd);
2586 static void fec_enet_free_buffers(struct net_device *ndev)
2588 struct fec_enet_private *fep = netdev_priv(ndev);
2590 struct sk_buff *skb;
2591 struct bufdesc *bdp;
2592 struct fec_enet_priv_tx_q *txq;
2593 struct fec_enet_priv_rx_q *rxq;
2596 for (q = 0; q < fep->num_rx_queues; q++) {
2597 rxq = fep->rx_queue[q];
2599 for (i = 0; i < rxq->bd.ring_size; i++) {
2600 skb = rxq->rx_skbuff[i];
2601 rxq->rx_skbuff[i] = NULL;
2603 dma_unmap_single(&fep->pdev->dev,
2604 fec32_to_cpu(bdp->cbd_bufaddr),
2605 FEC_ENET_RX_FRSIZE - fep->rx_align,
2609 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
2613 for (q = 0; q < fep->num_tx_queues; q++) {
2614 txq = fep->tx_queue[q];
2616 for (i = 0; i < txq->bd.ring_size; i++) {
2617 kfree(txq->tx_bounce[i]);
2618 txq->tx_bounce[i] = NULL;
2619 skb = txq->tx_skbuff[i];
2620 txq->tx_skbuff[i] = NULL;
2626 static void fec_enet_free_queue(struct net_device *ndev)
2628 struct fec_enet_private *fep = netdev_priv(ndev);
2630 struct fec_enet_priv_tx_q *txq;
2632 for (i = 0; i < fep->num_tx_queues; i++)
2633 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) {
2634 txq = fep->tx_queue[i];
2635 dma_free_coherent(NULL,
2636 txq->bd.ring_size * TSO_HEADER_SIZE,
2641 for (i = 0; i < fep->num_rx_queues; i++)
2642 kfree(fep->rx_queue[i]);
2643 for (i = 0; i < fep->num_tx_queues; i++)
2644 kfree(fep->tx_queue[i]);
2647 static int fec_enet_alloc_queue(struct net_device *ndev)
2649 struct fec_enet_private *fep = netdev_priv(ndev);
2652 struct fec_enet_priv_tx_q *txq;
2654 for (i = 0; i < fep->num_tx_queues; i++) {
2655 txq = kzalloc(sizeof(*txq), GFP_KERNEL);
2661 fep->tx_queue[i] = txq;
2662 txq->bd.ring_size = TX_RING_SIZE;
2663 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size;
2665 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS;
2666 txq->tx_wake_threshold =
2667 (txq->bd.ring_size - txq->tx_stop_threshold) / 2;
2669 txq->tso_hdrs = dma_alloc_coherent(NULL,
2670 txq->bd.ring_size * TSO_HEADER_SIZE,
2673 if (!txq->tso_hdrs) {
2679 for (i = 0; i < fep->num_rx_queues; i++) {
2680 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]),
2682 if (!fep->rx_queue[i]) {
2687 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE;
2688 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size;
2693 fec_enet_free_queue(ndev);
2698 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue)
2700 struct fec_enet_private *fep = netdev_priv(ndev);
2702 struct sk_buff *skb;
2703 struct bufdesc *bdp;
2704 struct fec_enet_priv_rx_q *rxq;
2706 rxq = fep->rx_queue[queue];
2708 for (i = 0; i < rxq->bd.ring_size; i++) {
2709 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
2713 if (fec_enet_new_rxbdp(ndev, bdp, skb)) {
2718 rxq->rx_skbuff[i] = skb;
2719 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
2721 if (fep->bufdesc_ex) {
2722 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2723 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
2726 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
2729 /* Set the last buffer to wrap. */
2730 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
2731 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
2735 fec_enet_free_buffers(ndev);
2740 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue)
2742 struct fec_enet_private *fep = netdev_priv(ndev);
2744 struct bufdesc *bdp;
2745 struct fec_enet_priv_tx_q *txq;
2747 txq = fep->tx_queue[queue];
2749 for (i = 0; i < txq->bd.ring_size; i++) {
2750 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
2751 if (!txq->tx_bounce[i])
2754 bdp->cbd_sc = cpu_to_fec16(0);
2755 bdp->cbd_bufaddr = cpu_to_fec32(0);
2757 if (fep->bufdesc_ex) {
2758 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2759 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT);
2762 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
2765 /* Set the last buffer to wrap. */
2766 bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
2767 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
2772 fec_enet_free_buffers(ndev);
2776 static int fec_enet_alloc_buffers(struct net_device *ndev)
2778 struct fec_enet_private *fep = netdev_priv(ndev);
2781 for (i = 0; i < fep->num_rx_queues; i++)
2782 if (fec_enet_alloc_rxq_buffers(ndev, i))
2785 for (i = 0; i < fep->num_tx_queues; i++)
2786 if (fec_enet_alloc_txq_buffers(ndev, i))
2792 fec_enet_open(struct net_device *ndev)
2794 struct fec_enet_private *fep = netdev_priv(ndev);
2797 ret = pm_runtime_get_sync(&fep->pdev->dev);
2801 pinctrl_pm_select_default_state(&fep->pdev->dev);
2802 ret = fec_enet_clk_enable(ndev, true);
2806 /* I should reset the ring buffers here, but I don't yet know
2807 * a simple way to do that.
2810 ret = fec_enet_alloc_buffers(ndev);
2812 goto err_enet_alloc;
2814 /* Init MAC prior to mii bus probe */
2817 /* Probe and connect to PHY when open the interface */
2818 ret = fec_enet_mii_probe(ndev);
2820 goto err_enet_mii_probe;
2822 if (fep->quirks & FEC_QUIRK_ERR006687)
2823 imx6q_cpuidle_fec_irqs_used();
2825 napi_enable(&fep->napi);
2826 phy_start(ndev->phydev);
2827 netif_tx_start_all_queues(ndev);
2829 device_set_wakeup_enable(&ndev->dev, fep->wol_flag &
2830 FEC_WOL_FLAG_ENABLE);
2835 fec_enet_free_buffers(ndev);
2837 fec_enet_clk_enable(ndev, false);
2839 pm_runtime_mark_last_busy(&fep->pdev->dev);
2840 pm_runtime_put_autosuspend(&fep->pdev->dev);
2841 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2846 fec_enet_close(struct net_device *ndev)
2848 struct fec_enet_private *fep = netdev_priv(ndev);
2850 phy_stop(ndev->phydev);
2852 if (netif_device_present(ndev)) {
2853 napi_disable(&fep->napi);
2854 netif_tx_disable(ndev);
2858 phy_disconnect(ndev->phydev);
2860 if (fep->quirks & FEC_QUIRK_ERR006687)
2861 imx6q_cpuidle_fec_irqs_unused();
2863 fec_enet_clk_enable(ndev, false);
2864 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2865 pm_runtime_mark_last_busy(&fep->pdev->dev);
2866 pm_runtime_put_autosuspend(&fep->pdev->dev);
2868 fec_enet_free_buffers(ndev);
2873 /* Set or clear the multicast filter for this adaptor.
2874 * Skeleton taken from sunlance driver.
2875 * The CPM Ethernet implementation allows Multicast as well as individual
2876 * MAC address filtering. Some of the drivers check to make sure it is
2877 * a group multicast address, and discard those that are not. I guess I
2878 * will do the same for now, but just remove the test if you want
2879 * individual filtering as well (do the upper net layers want or support
2880 * this kind of feature?).
2883 #define HASH_BITS 6 /* #bits in hash */
2884 #define CRC32_POLY 0xEDB88320
2886 static void set_multicast_list(struct net_device *ndev)
2888 struct fec_enet_private *fep = netdev_priv(ndev);
2889 struct netdev_hw_addr *ha;
2890 unsigned int i, bit, data, crc, tmp;
2893 if (ndev->flags & IFF_PROMISC) {
2894 tmp = readl(fep->hwp + FEC_R_CNTRL);
2896 writel(tmp, fep->hwp + FEC_R_CNTRL);
2900 tmp = readl(fep->hwp + FEC_R_CNTRL);
2902 writel(tmp, fep->hwp + FEC_R_CNTRL);
2904 if (ndev->flags & IFF_ALLMULTI) {
2905 /* Catch all multicast addresses, so set the
2908 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2909 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2914 /* Clear filter and add the addresses in hash register
2916 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2917 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2919 netdev_for_each_mc_addr(ha, ndev) {
2920 /* calculate crc32 value of mac address */
2923 for (i = 0; i < ndev->addr_len; i++) {
2925 for (bit = 0; bit < 8; bit++, data >>= 1) {
2927 (((crc ^ data) & 1) ? CRC32_POLY : 0);
2931 /* only upper 6 bits (HASH_BITS) are used
2932 * which point to specific bit in he hash registers
2934 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
2937 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2938 tmp |= 1 << (hash - 32);
2939 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2941 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2943 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2948 /* Set a MAC change in hardware. */
2950 fec_set_mac_address(struct net_device *ndev, void *p)
2952 struct fec_enet_private *fep = netdev_priv(ndev);
2953 struct sockaddr *addr = p;
2956 if (!is_valid_ether_addr(addr->sa_data))
2957 return -EADDRNOTAVAIL;
2958 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
2961 /* Add netif status check here to avoid system hang in below case:
2962 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx;
2963 * After ethx down, fec all clocks are gated off and then register
2964 * access causes system hang.
2966 if (!netif_running(ndev))
2969 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
2970 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
2971 fep->hwp + FEC_ADDR_LOW);
2972 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
2973 fep->hwp + FEC_ADDR_HIGH);
2977 #ifdef CONFIG_NET_POLL_CONTROLLER
2979 * fec_poll_controller - FEC Poll controller function
2980 * @dev: The FEC network adapter
2982 * Polled functionality used by netconsole and others in non interrupt mode
2985 static void fec_poll_controller(struct net_device *dev)
2988 struct fec_enet_private *fep = netdev_priv(dev);
2990 for (i = 0; i < FEC_IRQ_NUM; i++) {
2991 if (fep->irq[i] > 0) {
2992 disable_irq(fep->irq[i]);
2993 fec_enet_interrupt(fep->irq[i], dev);
2994 enable_irq(fep->irq[i]);
3000 static inline void fec_enet_set_netdev_features(struct net_device *netdev,
3001 netdev_features_t features)
3003 struct fec_enet_private *fep = netdev_priv(netdev);
3004 netdev_features_t changed = features ^ netdev->features;
3006 netdev->features = features;
3008 /* Receive checksum has been changed */
3009 if (changed & NETIF_F_RXCSUM) {
3010 if (features & NETIF_F_RXCSUM)
3011 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3013 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
3017 static int fec_set_features(struct net_device *netdev,
3018 netdev_features_t features)
3020 struct fec_enet_private *fep = netdev_priv(netdev);
3021 netdev_features_t changed = features ^ netdev->features;
3023 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) {
3024 napi_disable(&fep->napi);
3025 netif_tx_lock_bh(netdev);
3027 fec_enet_set_netdev_features(netdev, features);
3028 fec_restart(netdev);
3029 netif_tx_wake_all_queues(netdev);
3030 netif_tx_unlock_bh(netdev);
3031 napi_enable(&fep->napi);
3033 fec_enet_set_netdev_features(netdev, features);
3039 static const struct net_device_ops fec_netdev_ops = {
3040 .ndo_open = fec_enet_open,
3041 .ndo_stop = fec_enet_close,
3042 .ndo_start_xmit = fec_enet_start_xmit,
3043 .ndo_set_rx_mode = set_multicast_list,
3044 .ndo_change_mtu = eth_change_mtu,
3045 .ndo_validate_addr = eth_validate_addr,
3046 .ndo_tx_timeout = fec_timeout,
3047 .ndo_set_mac_address = fec_set_mac_address,
3048 .ndo_do_ioctl = fec_enet_ioctl,
3049 #ifdef CONFIG_NET_POLL_CONTROLLER
3050 .ndo_poll_controller = fec_poll_controller,
3052 .ndo_set_features = fec_set_features,
3055 static const unsigned short offset_des_active_rxq[] = {
3056 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2
3059 static const unsigned short offset_des_active_txq[] = {
3060 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2
3064 * XXX: We need to clean up on failure exits here.
3067 static int fec_enet_init(struct net_device *ndev)
3069 struct fec_enet_private *fep = netdev_priv(ndev);
3070 struct bufdesc *cbd_base;
3074 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) :
3075 sizeof(struct bufdesc);
3076 unsigned dsize_log2 = __fls(dsize);
3078 WARN_ON(dsize != (1 << dsize_log2));
3079 #if defined(CONFIG_ARM)
3080 fep->rx_align = 0xf;
3081 fep->tx_align = 0xf;
3083 fep->rx_align = 0x3;
3084 fep->tx_align = 0x3;
3087 fec_enet_alloc_queue(ndev);
3089 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize;
3091 /* Allocate memory for buffer descriptors. */
3092 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma,
3098 memset(cbd_base, 0, bd_size);
3100 /* Get the Ethernet address */
3102 /* make sure MAC we just acquired is programmed into the hw */
3103 fec_set_mac_address(ndev, NULL);
3105 /* Set receive and transmit descriptor base. */
3106 for (i = 0; i < fep->num_rx_queues; i++) {
3107 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i];
3108 unsigned size = dsize * rxq->bd.ring_size;
3111 rxq->bd.base = cbd_base;
3112 rxq->bd.cur = cbd_base;
3113 rxq->bd.dma = bd_dma;
3114 rxq->bd.dsize = dsize;
3115 rxq->bd.dsize_log2 = dsize_log2;
3116 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i];
3118 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
3119 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
3122 for (i = 0; i < fep->num_tx_queues; i++) {
3123 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i];
3124 unsigned size = dsize * txq->bd.ring_size;
3127 txq->bd.base = cbd_base;
3128 txq->bd.cur = cbd_base;
3129 txq->bd.dma = bd_dma;
3130 txq->bd.dsize = dsize;
3131 txq->bd.dsize_log2 = dsize_log2;
3132 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i];
3134 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
3135 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
3139 /* The FEC Ethernet specific entries in the device structure */
3140 ndev->watchdog_timeo = TX_TIMEOUT;
3141 ndev->netdev_ops = &fec_netdev_ops;
3142 ndev->ethtool_ops = &fec_enet_ethtool_ops;
3144 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
3145 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
3147 if (fep->quirks & FEC_QUIRK_HAS_VLAN)
3148 /* enable hw VLAN support */
3149 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3151 if (fep->quirks & FEC_QUIRK_HAS_CSUM) {
3152 ndev->gso_max_segs = FEC_MAX_TSO_SEGS;
3154 /* enable hw accelerator */
3155 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
3156 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
3157 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3160 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
3162 fep->rx_align = 0x3f;
3165 ndev->hw_features = ndev->features;
3173 static void fec_reset_phy(struct platform_device *pdev)
3176 bool active_high = false;
3178 struct device_node *np = pdev->dev.of_node;
3183 of_property_read_u32(np, "phy-reset-duration", &msec);
3184 /* A sane reset duration should not be longer than 1s */
3188 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
3189 if (!gpio_is_valid(phy_reset))
3192 active_high = of_property_read_bool(np, "phy-reset-active-high");
3194 err = devm_gpio_request_one(&pdev->dev, phy_reset,
3195 active_high ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW,
3198 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
3202 gpio_set_value_cansleep(phy_reset, !active_high);
3204 #else /* CONFIG_OF */
3205 static void fec_reset_phy(struct platform_device *pdev)
3208 * In case of platform probe, the reset has been done
3212 #endif /* CONFIG_OF */
3215 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx)
3217 struct device_node *np = pdev->dev.of_node;
3219 *num_tx = *num_rx = 1;
3221 if (!np || !of_device_is_available(np))
3224 /* parse the num of tx and rx queues */
3225 of_property_read_u32(np, "fsl,num-tx-queues", num_tx);
3227 of_property_read_u32(np, "fsl,num-rx-queues", num_rx);
3229 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) {
3230 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n",
3236 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) {
3237 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n",
3246 fec_probe(struct platform_device *pdev)
3248 struct fec_enet_private *fep;
3249 struct fec_platform_data *pdata;
3250 struct net_device *ndev;
3251 int i, irq, ret = 0;
3253 const struct of_device_id *of_id;
3255 struct device_node *np = pdev->dev.of_node, *phy_node;
3259 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs);
3261 /* Init network device */
3262 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private),
3263 num_tx_qs, num_rx_qs);
3267 SET_NETDEV_DEV(ndev, &pdev->dev);
3269 /* setup board info structure */
3270 fep = netdev_priv(ndev);
3272 of_id = of_match_device(fec_dt_ids, &pdev->dev);
3274 pdev->id_entry = of_id->data;
3275 fep->quirks = pdev->id_entry->driver_data;
3278 fep->num_rx_queues = num_rx_qs;
3279 fep->num_tx_queues = num_tx_qs;
3281 #if !defined(CONFIG_M5272)
3282 /* default enable pause frame auto negotiation */
3283 if (fep->quirks & FEC_QUIRK_HAS_GBIT)
3284 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
3287 /* Select default pin state */
3288 pinctrl_pm_select_default_state(&pdev->dev);
3290 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3291 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
3292 if (IS_ERR(fep->hwp)) {
3293 ret = PTR_ERR(fep->hwp);
3294 goto failed_ioremap;
3298 fep->dev_id = dev_id++;
3300 platform_set_drvdata(pdev, ndev);
3302 if ((of_machine_is_compatible("fsl,imx6q") ||
3303 of_machine_is_compatible("fsl,imx6dl")) &&
3304 !of_property_read_bool(np, "fsl,err006687-workaround-present"))
3305 fep->quirks |= FEC_QUIRK_ERR006687;
3307 if (of_get_property(np, "fsl,magic-packet", NULL))
3308 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET;
3310 phy_node = of_parse_phandle(np, "phy-handle", 0);
3311 if (!phy_node && of_phy_is_fixed_link(np)) {
3312 ret = of_phy_register_fixed_link(np);
3315 "broken fixed-link specification\n");
3318 phy_node = of_node_get(np);
3320 fep->phy_node = phy_node;
3322 ret = of_get_phy_mode(pdev->dev.of_node);
3324 pdata = dev_get_platdata(&pdev->dev);
3326 fep->phy_interface = pdata->phy;
3328 fep->phy_interface = PHY_INTERFACE_MODE_MII;
3330 fep->phy_interface = ret;
3333 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
3334 if (IS_ERR(fep->clk_ipg)) {
3335 ret = PTR_ERR(fep->clk_ipg);
3339 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
3340 if (IS_ERR(fep->clk_ahb)) {
3341 ret = PTR_ERR(fep->clk_ahb);
3345 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb);
3347 /* enet_out is optional, depends on board */
3348 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
3349 if (IS_ERR(fep->clk_enet_out))
3350 fep->clk_enet_out = NULL;
3352 fep->ptp_clk_on = false;
3353 mutex_init(&fep->ptp_clk_mutex);
3355 /* clk_ref is optional, depends on board */
3356 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref");
3357 if (IS_ERR(fep->clk_ref))
3358 fep->clk_ref = NULL;
3360 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX;
3361 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
3362 if (IS_ERR(fep->clk_ptp)) {
3363 fep->clk_ptp = NULL;
3364 fep->bufdesc_ex = false;
3367 ret = fec_enet_clk_enable(ndev, true);
3371 ret = clk_prepare_enable(fep->clk_ipg);
3373 goto failed_clk_ipg;
3375 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
3376 if (!IS_ERR(fep->reg_phy)) {
3377 ret = regulator_enable(fep->reg_phy);
3380 "Failed to enable phy regulator: %d\n", ret);
3381 goto failed_regulator;
3384 fep->reg_phy = NULL;
3387 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT);
3388 pm_runtime_use_autosuspend(&pdev->dev);
3389 pm_runtime_get_noresume(&pdev->dev);
3390 pm_runtime_set_active(&pdev->dev);
3391 pm_runtime_enable(&pdev->dev);
3393 fec_reset_phy(pdev);
3395 if (fep->bufdesc_ex)
3398 ret = fec_enet_init(ndev);
3402 for (i = 0; i < FEC_IRQ_NUM; i++) {
3403 irq = platform_get_irq(pdev, i);
3410 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
3411 0, pdev->name, ndev);
3418 init_completion(&fep->mdio_done);
3419 ret = fec_enet_mii_init(pdev);
3421 goto failed_mii_init;
3423 /* Carrier starts down, phylib will bring it up */
3424 netif_carrier_off(ndev);
3425 fec_enet_clk_enable(ndev, false);
3426 pinctrl_pm_select_sleep_state(&pdev->dev);
3428 ret = register_netdev(ndev);
3430 goto failed_register;
3432 device_init_wakeup(&ndev->dev, fep->wol_flag &
3433 FEC_WOL_HAS_MAGIC_PACKET);
3435 if (fep->bufdesc_ex && fep->ptp_clock)
3436 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
3438 fep->rx_copybreak = COPYBREAK_DEFAULT;
3439 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
3441 pm_runtime_mark_last_busy(&pdev->dev);
3442 pm_runtime_put_autosuspend(&pdev->dev);
3447 fec_enet_mii_remove(fep);
3453 regulator_disable(fep->reg_phy);
3455 clk_disable_unprepare(fep->clk_ipg);
3457 fec_enet_clk_enable(ndev, false);
3460 of_node_put(phy_node);
3468 fec_drv_remove(struct platform_device *pdev)
3470 struct net_device *ndev = platform_get_drvdata(pdev);
3471 struct fec_enet_private *fep = netdev_priv(ndev);
3473 cancel_work_sync(&fep->tx_timeout_work);
3475 unregister_netdev(ndev);
3476 fec_enet_mii_remove(fep);
3478 regulator_disable(fep->reg_phy);
3479 of_node_put(fep->phy_node);
3485 static int __maybe_unused fec_suspend(struct device *dev)
3487 struct net_device *ndev = dev_get_drvdata(dev);
3488 struct fec_enet_private *fep = netdev_priv(ndev);
3491 if (netif_running(ndev)) {
3492 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE)
3493 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON;
3494 phy_stop(ndev->phydev);
3495 napi_disable(&fep->napi);
3496 netif_tx_lock_bh(ndev);
3497 netif_device_detach(ndev);
3498 netif_tx_unlock_bh(ndev);
3500 fec_enet_clk_enable(ndev, false);
3501 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3502 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3506 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3507 regulator_disable(fep->reg_phy);
3509 /* SOC supply clock to phy, when clock is disabled, phy link down
3510 * SOC control phy regulator, when regulator is disabled, phy link down
3512 if (fep->clk_enet_out || fep->reg_phy)
3518 static int __maybe_unused fec_resume(struct device *dev)
3520 struct net_device *ndev = dev_get_drvdata(dev);
3521 struct fec_enet_private *fep = netdev_priv(ndev);
3522 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
3526 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) {
3527 ret = regulator_enable(fep->reg_phy);
3533 if (netif_running(ndev)) {
3534 ret = fec_enet_clk_enable(ndev, true);
3539 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) {
3540 if (pdata && pdata->sleep_mode_enable)
3541 pdata->sleep_mode_enable(false);
3542 val = readl(fep->hwp + FEC_ECNTRL);
3543 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
3544 writel(val, fep->hwp + FEC_ECNTRL);
3545 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON;
3547 pinctrl_pm_select_default_state(&fep->pdev->dev);
3550 netif_tx_lock_bh(ndev);
3551 netif_device_attach(ndev);
3552 netif_tx_unlock_bh(ndev);
3553 napi_enable(&fep->napi);
3554 phy_start(ndev->phydev);
3562 regulator_disable(fep->reg_phy);
3566 static int __maybe_unused fec_runtime_suspend(struct device *dev)
3568 struct net_device *ndev = dev_get_drvdata(dev);
3569 struct fec_enet_private *fep = netdev_priv(ndev);
3571 clk_disable_unprepare(fep->clk_ipg);
3576 static int __maybe_unused fec_runtime_resume(struct device *dev)
3578 struct net_device *ndev = dev_get_drvdata(dev);
3579 struct fec_enet_private *fep = netdev_priv(ndev);
3581 return clk_prepare_enable(fep->clk_ipg);
3584 static const struct dev_pm_ops fec_pm_ops = {
3585 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume)
3586 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL)
3589 static struct platform_driver fec_driver = {
3591 .name = DRIVER_NAME,
3593 .of_match_table = fec_dt_ids,
3595 .id_table = fec_devtype,
3597 .remove = fec_drv_remove,
3600 module_platform_driver(fec_driver);
3602 MODULE_ALIAS("platform:"DRIVER_NAME);
3603 MODULE_LICENSE("GPL");