drivers/net/ethernet/freescale/gianfar.c

   1 /* drivers/net/ethernet/freescale/gianfar.c
   2  *
   3  * Gianfar Ethernet Driver
   4  * This driver is designed for the non-CPM ethernet controllers
   5  * on the 85xx and 83xx family of integrated processors
   6  * Based on 8260_io/fcc_enet.c
   7  *
   8  * Author: Andy Fleming
   9  * Maintainer: Kumar Gala
  10  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
  11  *
  12  * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
  13  * Copyright 2007 MontaVista Software, Inc.
  14  *
  15  * This program is free software; you can redistribute  it and/or modify it
  16  * under  the terms of  the GNU General  Public License as published by the
  17  * Free Software Foundation;  either version 2 of the  License, or (at your
  18  * option) any later version.
  19  *
  20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  21  *  RA 11 31 24.2
  22  *  Dec +69 19 52
  23  *  V 3.84
  24  *  B-V +1.62
  25  *
  26  *  Theory of operation
  27  *
  28  *  The driver is initialized through of_device. Configuration information
  29  *  is therefore conveyed through an OF-style device tree.
  30  *
  31  *  The Gianfar Ethernet Controller uses a ring of buffer
  32  *  descriptors.  The beginning is indicated by a register
  33  *  pointing to the physical address of the start of the ring.
  34  *  The end is determined by a "wrap" bit being set in the
  35  *  last descriptor of the ring.
  36  *
  37  *  When a packet is received, the RXF bit in the
  38  *  IEVENT register is set, triggering an interrupt when the
  39  *  corresponding bit in the IMASK register is also set (if
  40  *  interrupt coalescing is active, then the interrupt may not
  41  *  happen immediately, but will wait until either a set number
  42  *  of frames or amount of time have passed).  In NAPI, the
  43  *  interrupt handler will signal there is work to be done, and
  44  *  exit. This method will start at the last known empty
  45  *  descriptor, and process every subsequent descriptor until there
  46  *  are none left with data (NAPI will stop after a set number of
  47  *  packets to give time to other tasks, but will eventually
  48  *  process all the packets).  The data arrives inside a
  49  *  pre-allocated skb, and so after the skb is passed up to the
  50  *  stack, a new skb must be allocated, and the address field in
  51  *  the buffer descriptor must be updated to indicate this new
  52  *  skb.
  53  *
  54  *  When the kernel requests that a packet be transmitted, the
  55  *  driver starts where it left off last time, and points the
  56  *  descriptor at the buffer which was passed in.  The driver
  57  *  then informs the DMA engine that there are packets ready to
  58  *  be transmitted.  Once the controller is finished transmitting
  59  *  the packet, an interrupt may be triggered (under the same
  60  *  conditions as for reception, but depending on the TXF bit).
  61  *  The driver then cleans up the buffer.
  62  */
  63
  64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  65 #define DEBUG
  66
  67 #include <linux/kernel.h>
  68 #include <linux/string.h>
  69 #include <linux/errno.h>
  70 #include <linux/unistd.h>
  71 #include <linux/slab.h>
  72 #include <linux/interrupt.h>
  73 #include <linux/delay.h>
  74 #include <linux/netdevice.h>
  75 #include <linux/etherdevice.h>
  76 #include <linux/skbuff.h>
  77 #include <linux/if_vlan.h>
  78 #include <linux/spinlock.h>
  79 #include <linux/mm.h>
  80 #include <linux/of_address.h>
  81 #include <linux/of_irq.h>
  82 #include <linux/of_mdio.h>
  83 #include <linux/of_platform.h>
  84 #include <linux/ip.h>
  85 #include <linux/tcp.h>
  86 #include <linux/udp.h>
  87 #include <linux/in.h>
  88 #include <linux/net_tstamp.h>
  89
  90 #include <asm/io.h>
  91 #ifdef CONFIG_PPC
  92 #include <asm/reg.h>
  93 #include <asm/mpc85xx.h>
  94 #endif
  95 #include <asm/irq.h>
  96 #include <asm/uaccess.h>
  97 #include <linux/module.h>
  98 #include <linux/dma-mapping.h>
  99 #include <linux/crc32.h>
 100 #include <linux/mii.h>
 101 #include <linux/phy.h>
 102 #include <linux/phy_fixed.h>
 103 #include <linux/of.h>
 104 #include <linux/of_net.h>
 105 #include <linux/of_address.h>
 106 #include <linux/of_irq.h>
 107
 108 #include "gianfar.h"
 109
 110 #define TX_TIMEOUT      (1*HZ)
 111
 112 const char gfar_driver_version[] = "1.3";
 113
 114 static int gfar_enet_open(struct net_device *dev);
 115 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
 116 static void gfar_reset_task(struct work_struct *work);
 117 static void gfar_timeout(struct net_device *dev);
 118 static int gfar_close(struct net_device *dev);
 119 static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue,
 120                                 int alloc_cnt);
 121 static int gfar_set_mac_address(struct net_device *dev);
 122 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
 123 static irqreturn_t gfar_error(int irq, void *dev_id);
 124 static irqreturn_t gfar_transmit(int irq, void *dev_id);
 125 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
 126 static void adjust_link(struct net_device *dev);
 127 static noinline void gfar_update_link_state(struct gfar_private *priv);
 128 static int init_phy(struct net_device *dev);
 129 static int gfar_probe(struct platform_device *ofdev);
 130 static int gfar_remove(struct platform_device *ofdev);
 131 static void free_skb_resources(struct gfar_private *priv);
 132 static void gfar_set_multi(struct net_device *dev);
 133 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
 134 static void gfar_configure_serdes(struct net_device *dev);
 135 static int gfar_poll_rx(struct napi_struct *napi, int budget);
 136 static int gfar_poll_tx(struct napi_struct *napi, int budget);
 137 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget);
 138 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget);
 139 #ifdef CONFIG_NET_POLL_CONTROLLER
 140 static void gfar_netpoll(struct net_device *dev);
 141 #endif
 142 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
 143 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
 144 static void gfar_process_frame(struct net_device *ndev, struct sk_buff *skb);
 145 static void gfar_halt_nodisable(struct gfar_private *priv);
 146 static void gfar_clear_exact_match(struct net_device *dev);
 147 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
 148                                   const u8 *addr);
 149 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 150
 151 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 152 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 153 MODULE_LICENSE("GPL");
 154
 155 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 156                             dma_addr_t buf)
 157 {
 158         u32 lstatus;
 159
 160         bdp->bufPtr = cpu_to_be32(buf);
 161
 162         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
 163         if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
 164                 lstatus |= BD_LFLAG(RXBD_WRAP);
 165
 166         gfar_wmb();
 167
 168         bdp->lstatus = cpu_to_be32(lstatus);
 169 }
 170
 171 static void gfar_init_bds(struct net_device *ndev)
 172 {
 173         struct gfar_private *priv = netdev_priv(ndev);
 174         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 175         struct gfar_priv_tx_q *tx_queue = NULL;
 176         struct gfar_priv_rx_q *rx_queue = NULL;
 177         struct txbd8 *txbdp;
 178         u32 __iomem *rfbptr;
 179         int i, j;
 180
 181         for (i = 0; i < priv->num_tx_queues; i++) {
 182                 tx_queue = priv->tx_queue[i];
 183                 /* Initialize some variables in our dev structure */
 184                 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
 185                 tx_queue->dirty_tx = tx_queue->tx_bd_base;
 186                 tx_queue->cur_tx = tx_queue->tx_bd_base;
 187                 tx_queue->skb_curtx = 0;
 188                 tx_queue->skb_dirtytx = 0;
 189
 190                 /* Initialize Transmit Descriptor Ring */
 191                 txbdp = tx_queue->tx_bd_base;
 192                 for (j = 0; j < tx_queue->tx_ring_size; j++) {
 193                         txbdp->lstatus = 0;
 194                         txbdp->bufPtr = 0;
 195                         txbdp++;
 196                 }
 197
 198                 /* Set the last descriptor in the ring to indicate wrap */
 199                 txbdp--;
 200                 txbdp->status = cpu_to_be16(be16_to_cpu(txbdp->status) |
 201                                             TXBD_WRAP);
 202         }
 203
 204         rfbptr = &regs->rfbptr0;
 205         for (i = 0; i < priv->num_rx_queues; i++) {
 206                 rx_queue = priv->rx_queue[i];
 207
 208                 rx_queue->next_to_clean = 0;
 209                 rx_queue->next_to_use = 0;
 210
 211                 /* make sure next_to_clean != next_to_use after this
 212                  * by leaving at least 1 unused descriptor
 213                  */
 214                 gfar_alloc_rx_buffs(rx_queue, gfar_rxbd_unused(rx_queue));
 215
 216                 rx_queue->rfbptr = rfbptr;
 217                 rfbptr += 2;
 218         }
 219 }
 220
 221 static int gfar_alloc_skb_resources(struct net_device *ndev)
 222 {
 223         void *vaddr;
 224         dma_addr_t addr;
 225         int i, j, k;
 226         struct gfar_private *priv = netdev_priv(ndev);
 227         struct device *dev = priv->dev;
 228         struct gfar_priv_tx_q *tx_queue = NULL;
 229         struct gfar_priv_rx_q *rx_queue = NULL;
 230
 231         priv->total_tx_ring_size = 0;
 232         for (i = 0; i < priv->num_tx_queues; i++)
 233                 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
 234
 235         priv->total_rx_ring_size = 0;
 236         for (i = 0; i < priv->num_rx_queues; i++)
 237                 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
 238
 239         /* Allocate memory for the buffer descriptors */
 240         vaddr = dma_alloc_coherent(dev,
 241                                    (priv->total_tx_ring_size *
 242                                     sizeof(struct txbd8)) +
 243                                    (priv->total_rx_ring_size *
 244                                     sizeof(struct rxbd8)),
 245                                    &addr, GFP_KERNEL);
 246         if (!vaddr)
 247                 return -ENOMEM;
 248
 249         for (i = 0; i < priv->num_tx_queues; i++) {
 250                 tx_queue = priv->tx_queue[i];
 251                 tx_queue->tx_bd_base = vaddr;
 252                 tx_queue->tx_bd_dma_base = addr;
 253                 tx_queue->dev = ndev;
 254                 /* enet DMA only understands physical addresses */
 255                 addr  += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 256                 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 257         }
 258
 259         /* Start the rx descriptor ring where the tx ring leaves off */
 260         for (i = 0; i < priv->num_rx_queues; i++) {
 261                 rx_queue = priv->rx_queue[i];
 262                 rx_queue->rx_bd_base = vaddr;
 263                 rx_queue->rx_bd_dma_base = addr;
 264                 rx_queue->ndev = ndev;
 265                 addr  += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 266                 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 267         }
 268
 269         /* Setup the skbuff rings */
 270         for (i = 0; i < priv->num_tx_queues; i++) {
 271                 tx_queue = priv->tx_queue[i];
 272                 tx_queue->tx_skbuff =
 273                         kmalloc_array(tx_queue->tx_ring_size,
 274                                       sizeof(*tx_queue->tx_skbuff),
 275                                       GFP_KERNEL);
 276                 if (!tx_queue->tx_skbuff)
 277                         goto cleanup;
 278
 279                 for (k = 0; k < tx_queue->tx_ring_size; k++)
 280                         tx_queue->tx_skbuff[k] = NULL;
 281         }
 282
 283         for (i = 0; i < priv->num_rx_queues; i++) {
 284                 rx_queue = priv->rx_queue[i];
 285                 rx_queue->rx_skbuff =
 286                         kmalloc_array(rx_queue->rx_ring_size,
 287                                       sizeof(*rx_queue->rx_skbuff),
 288                                       GFP_KERNEL);
 289                 if (!rx_queue->rx_skbuff)
 290                         goto cleanup;
 291
 292                 for (j = 0; j < rx_queue->rx_ring_size; j++)
 293                         rx_queue->rx_skbuff[j] = NULL;
 294         }
 295
 296         gfar_init_bds(ndev);
 297
 298         return 0;
 299
 300 cleanup:
 301         free_skb_resources(priv);
 302         return -ENOMEM;
 303 }
 304
 305 static void gfar_init_tx_rx_base(struct gfar_private *priv)
 306 {
 307         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 308         u32 __iomem *baddr;
 309         int i;
 310
 311         baddr = &regs->tbase0;
 312         for (i = 0; i < priv->num_tx_queues; i++) {
 313                 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
 314                 baddr += 2;
 315         }
 316
 317         baddr = &regs->rbase0;
 318         for (i = 0; i < priv->num_rx_queues; i++) {
 319                 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
 320                 baddr += 2;
 321         }
 322 }
 323
 324 static void gfar_init_rqprm(struct gfar_private *priv)
 325 {
 326         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 327         u32 __iomem *baddr;
 328         int i;
 329
 330         baddr = &regs->rqprm0;
 331         for (i = 0; i < priv->num_rx_queues; i++) {
 332                 gfar_write(baddr, priv->rx_queue[i]->rx_ring_size |
 333                            (DEFAULT_RX_LFC_THR << FBTHR_SHIFT));
 334                 baddr++;
 335         }
 336 }
 337
 338 static void gfar_rx_buff_size_config(struct gfar_private *priv)
 339 {
 340         int frame_size = priv->ndev->mtu + ETH_HLEN + ETH_FCS_LEN;
 341
 342         /* set this when rx hw offload (TOE) functions are being used */
 343         priv->uses_rxfcb = 0;
 344
 345         if (priv->ndev->features & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX))
 346                 priv->uses_rxfcb = 1;
 347
 348         if (priv->hwts_rx_en)
 349                 priv->uses_rxfcb = 1;
 350
 351         if (priv->uses_rxfcb)
 352                 frame_size += GMAC_FCB_LEN;
 353
 354         frame_size += priv->padding;
 355
 356         frame_size = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
 357                      INCREMENTAL_BUFFER_SIZE;
 358
 359         priv->rx_buffer_size = frame_size;
 360 }
 361
 362 static void gfar_mac_rx_config(struct gfar_private *priv)
 363 {
 364         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 365         u32 rctrl = 0;
 366
 367         if (priv->rx_filer_enable) {
 368                 rctrl |= RCTRL_FILREN;
 369                 /* Program the RIR0 reg with the required distribution */
 370                 if (priv->poll_mode == GFAR_SQ_POLLING)
 371                         gfar_write(&regs->rir0, DEFAULT_2RXQ_RIR0);
 372                 else /* GFAR_MQ_POLLING */
 373                         gfar_write(&regs->rir0, DEFAULT_8RXQ_RIR0);
 374         }
 375
 376         /* Restore PROMISC mode */
 377         if (priv->ndev->flags & IFF_PROMISC)
 378                 rctrl |= RCTRL_PROM;
 379
 380         if (priv->ndev->features & NETIF_F_RXCSUM)
 381                 rctrl |= RCTRL_CHECKSUMMING;
 382
 383         if (priv->extended_hash)
 384                 rctrl |= RCTRL_EXTHASH | RCTRL_EMEN;
 385
 386         if (priv->padding) {
 387                 rctrl &= ~RCTRL_PAL_MASK;
 388                 rctrl |= RCTRL_PADDING(priv->padding);
 389         }
 390
 391         /* Enable HW time stamping if requested from user space */
 392         if (priv->hwts_rx_en)
 393                 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
 394
 395         if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)
 396                 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
 397
 398         /* Clear the LFC bit */
 399         gfar_write(&regs->rctrl, rctrl);
 400         /* Init flow control threshold values */
 401         gfar_init_rqprm(priv);
 402         gfar_write(&regs->ptv, DEFAULT_LFC_PTVVAL);
 403         rctrl |= RCTRL_LFC;
 404
 405         /* Init rctrl based on our settings */
 406         gfar_write(&regs->rctrl, rctrl);
 407 }
 408
 409 static void gfar_mac_tx_config(struct gfar_private *priv)
 410 {
 411         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 412         u32 tctrl = 0;
 413
 414         if (priv->ndev->features & NETIF_F_IP_CSUM)
 415                 tctrl |= TCTRL_INIT_CSUM;
 416
 417         if (priv->prio_sched_en)
 418                 tctrl |= TCTRL_TXSCHED_PRIO;
 419         else {
 420                 tctrl |= TCTRL_TXSCHED_WRRS;
 421                 gfar_write(&regs->tr03wt, DEFAULT_WRRS_WEIGHT);
 422                 gfar_write(&regs->tr47wt, DEFAULT_WRRS_WEIGHT);
 423         }
 424
 425         if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_TX)
 426                 tctrl |= TCTRL_VLINS;
 427
 428         gfar_write(&regs->tctrl, tctrl);
 429 }
 430
 431 static void gfar_configure_coalescing(struct gfar_private *priv,
 432                                unsigned long tx_mask, unsigned long rx_mask)
 433 {
 434         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 435         u32 __iomem *baddr;
 436
 437         if (priv->mode == MQ_MG_MODE) {
 438                 int i = 0;
 439
 440                 baddr = &regs->txic0;
 441                 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
 442                         gfar_write(baddr + i, 0);
 443                         if (likely(priv->tx_queue[i]->txcoalescing))
 444                                 gfar_write(baddr + i, priv->tx_queue[i]->txic);
 445                 }
 446
 447                 baddr = &regs->rxic0;
 448                 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
 449                         gfar_write(baddr + i, 0);
 450                         if (likely(priv->rx_queue[i]->rxcoalescing))
 451                                 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
 452                 }
 453         } else {
 454                 /* Backward compatible case -- even if we enable
 455                  * multiple queues, there's only single reg to program
 456                  */
 457                 gfar_write(&regs->txic, 0);
 458                 if (likely(priv->tx_queue[0]->txcoalescing))
 459                         gfar_write(&regs->txic, priv->tx_queue[0]->txic);
 460
 461                 gfar_write(&regs->rxic, 0);
 462                 if (unlikely(priv->rx_queue[0]->rxcoalescing))
 463                         gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
 464         }
 465 }
 466
 467 void gfar_configure_coalescing_all(struct gfar_private *priv)
 468 {
 469         gfar_configure_coalescing(priv, 0xFF, 0xFF);
 470 }
 471
 472 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
 473 {
 474         struct gfar_private *priv = netdev_priv(dev);
 475         unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
 476         unsigned long tx_packets = 0, tx_bytes = 0;
 477         int i;
 478
 479         for (i = 0; i < priv->num_rx_queues; i++) {
 480                 rx_packets += priv->rx_queue[i]->stats.rx_packets;
 481                 rx_bytes   += priv->rx_queue[i]->stats.rx_bytes;
 482                 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
 483         }
 484
 485         dev->stats.rx_packets = rx_packets;
 486         dev->stats.rx_bytes   = rx_bytes;
 487         dev->stats.rx_dropped = rx_dropped;
 488
 489         for (i = 0; i < priv->num_tx_queues; i++) {
 490                 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
 491                 tx_packets += priv->tx_queue[i]->stats.tx_packets;
 492         }
 493
 494         dev->stats.tx_bytes   = tx_bytes;
 495         dev->stats.tx_packets = tx_packets;
 496
 497         return &dev->stats;
 498 }
 499
 500 static int gfar_set_mac_addr(struct net_device *dev, void *p)
 501 {
 502         eth_mac_addr(dev, p);
 503
 504         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
 505
 506         return 0;
 507 }
 508
 509 static const struct net_device_ops gfar_netdev_ops = {
 510         .ndo_open = gfar_enet_open,
 511         .ndo_start_xmit = gfar_start_xmit,
 512         .ndo_stop = gfar_close,
 513         .ndo_change_mtu = gfar_change_mtu,
 514         .ndo_set_features = gfar_set_features,
 515         .ndo_set_rx_mode = gfar_set_multi,
 516         .ndo_tx_timeout = gfar_timeout,
 517         .ndo_do_ioctl = gfar_ioctl,
 518         .ndo_get_stats = gfar_get_stats,
 519         .ndo_set_mac_address = gfar_set_mac_addr,
 520         .ndo_validate_addr = eth_validate_addr,
 521 #ifdef CONFIG_NET_POLL_CONTROLLER
 522         .ndo_poll_controller = gfar_netpoll,
 523 #endif
 524 };
 525
 526 static void gfar_ints_disable(struct gfar_private *priv)
 527 {
 528         int i;
 529         for (i = 0; i < priv->num_grps; i++) {
 530                 struct gfar __iomem *regs = priv->gfargrp[i].regs;
 531                 /* Clear IEVENT */
 532                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
 533
 534                 /* Initialize IMASK */
 535                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
 536         }
 537 }
 538
 539 static void gfar_ints_enable(struct gfar_private *priv)
 540 {
 541         int i;
 542         for (i = 0; i < priv->num_grps; i++) {
 543                 struct gfar __iomem *regs = priv->gfargrp[i].regs;
 544                 /* Unmask the interrupts we look for */
 545                 gfar_write(&regs->imask, IMASK_DEFAULT);
 546         }
 547 }
 548
 549 static void lock_tx_qs(struct gfar_private *priv)
 550 {
 551         int i;
 552
 553         for (i = 0; i < priv->num_tx_queues; i++)
 554                 spin_lock(&priv->tx_queue[i]->txlock);
 555 }
 556
 557 static void unlock_tx_qs(struct gfar_private *priv)
 558 {
 559         int i;
 560
 561         for (i = 0; i < priv->num_tx_queues; i++)
 562                 spin_unlock(&priv->tx_queue[i]->txlock);
 563 }
 564
 565 static int gfar_alloc_tx_queues(struct gfar_private *priv)
 566 {
 567         int i;
 568
 569         for (i = 0; i < priv->num_tx_queues; i++) {
 570                 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
 571                                             GFP_KERNEL);
 572                 if (!priv->tx_queue[i])
 573                         return -ENOMEM;
 574
 575                 priv->tx_queue[i]->tx_skbuff = NULL;
 576                 priv->tx_queue[i]->qindex = i;
 577                 priv->tx_queue[i]->dev = priv->ndev;
 578                 spin_lock_init(&(priv->tx_queue[i]->txlock));
 579         }
 580         return 0;
 581 }
 582
 583 static int gfar_alloc_rx_queues(struct gfar_private *priv)
 584 {
 585         int i;
 586
 587         for (i = 0; i < priv->num_rx_queues; i++) {
 588                 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
 589                                             GFP_KERNEL);
 590                 if (!priv->rx_queue[i])
 591                         return -ENOMEM;
 592
 593                 priv->rx_queue[i]->rx_skbuff = NULL;
 594                 priv->rx_queue[i]->qindex = i;
 595                 priv->rx_queue[i]->ndev = priv->ndev;
 596         }
 597         return 0;
 598 }
 599
 600 static void gfar_free_tx_queues(struct gfar_private *priv)
 601 {
 602         int i;
 603
 604         for (i = 0; i < priv->num_tx_queues; i++)
 605                 kfree(priv->tx_queue[i]);
 606 }
 607
 608 static void gfar_free_rx_queues(struct gfar_private *priv)
 609 {
 610         int i;
 611
 612         for (i = 0; i < priv->num_rx_queues; i++)
 613                 kfree(priv->rx_queue[i]);
 614 }
 615
 616 static void unmap_group_regs(struct gfar_private *priv)
 617 {
 618         int i;
 619
 620         for (i = 0; i < MAXGROUPS; i++)
 621                 if (priv->gfargrp[i].regs)
 622                         iounmap(priv->gfargrp[i].regs);
 623 }
 624
 625 static void free_gfar_dev(struct gfar_private *priv)
 626 {
 627         int i, j;
 628
 629         for (i = 0; i < priv->num_grps; i++)
 630                 for (j = 0; j < GFAR_NUM_IRQS; j++) {
 631                         kfree(priv->gfargrp[i].irqinfo[j]);
 632                         priv->gfargrp[i].irqinfo[j] = NULL;
 633                 }
 634
 635         free_netdev(priv->ndev);
 636 }
 637
 638 static void disable_napi(struct gfar_private *priv)
 639 {
 640         int i;
 641
 642         for (i = 0; i < priv->num_grps; i++) {
 643                 napi_disable(&priv->gfargrp[i].napi_rx);
 644                 napi_disable(&priv->gfargrp[i].napi_tx);
 645         }
 646 }
 647
 648 static void enable_napi(struct gfar_private *priv)
 649 {
 650         int i;
 651
 652         for (i = 0; i < priv->num_grps; i++) {
 653                 napi_enable(&priv->gfargrp[i].napi_rx);
 654                 napi_enable(&priv->gfargrp[i].napi_tx);
 655         }
 656 }
 657
 658 static int gfar_parse_group(struct device_node *np,
 659                             struct gfar_private *priv, const char *model)
 660 {
 661         struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
 662         int i;
 663
 664         for (i = 0; i < GFAR_NUM_IRQS; i++) {
 665                 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
 666                                           GFP_KERNEL);
 667                 if (!grp->irqinfo[i])
 668                         return -ENOMEM;
 669         }
 670
 671         grp->regs = of_iomap(np, 0);
 672         if (!grp->regs)
 673                 return -ENOMEM;
 674
 675         gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
 676
 677         /* If we aren't the FEC we have multiple interrupts */
 678         if (model && strcasecmp(model, "FEC")) {
 679                 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
 680                 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
 681                 if (gfar_irq(grp, TX)->irq == NO_IRQ ||
 682                     gfar_irq(grp, RX)->irq == NO_IRQ ||
 683                     gfar_irq(grp, ER)->irq == NO_IRQ)
 684                         return -EINVAL;
 685         }
 686
 687         grp->priv = priv;
 688         spin_lock_init(&grp->grplock);
 689         if (priv->mode == MQ_MG_MODE) {
 690                 u32 rxq_mask, txq_mask;
 691                 int ret;
 692
 693                 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 694                 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 695
 696                 ret = of_property_read_u32(np, "fsl,rx-bit-map", &rxq_mask);
 697                 if (!ret) {
 698                         grp->rx_bit_map = rxq_mask ?
 699                         rxq_mask : (DEFAULT_MAPPING >> priv->num_grps);
 700                 }
 701
 702                 ret = of_property_read_u32(np, "fsl,tx-bit-map", &txq_mask);
 703                 if (!ret) {
 704                         grp->tx_bit_map = txq_mask ?
 705                         txq_mask : (DEFAULT_MAPPING >> priv->num_grps);
 706                 }
 707
 708                 if (priv->poll_mode == GFAR_SQ_POLLING) {
 709                         /* One Q per interrupt group: Q0 to G0, Q1 to G1 */
 710                         grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 711                         grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 712                 }
 713         } else {
 714                 grp->rx_bit_map = 0xFF;
 715                 grp->tx_bit_map = 0xFF;
 716         }
 717
 718         /* bit_map's MSB is q0 (from q0 to q7) but, for_each_set_bit parses
 719          * right to left, so we need to revert the 8 bits to get the q index
 720          */
 721         grp->rx_bit_map = bitrev8(grp->rx_bit_map);
 722         grp->tx_bit_map = bitrev8(grp->tx_bit_map);
 723
 724         /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
 725          * also assign queues to groups
 726          */
 727         for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
 728                 if (!grp->rx_queue)
 729                         grp->rx_queue = priv->rx_queue[i];
 730                 grp->num_rx_queues++;
 731                 grp->rstat |= (RSTAT_CLEAR_RHALT >> i);
 732                 priv->rqueue |= ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
 733                 priv->rx_queue[i]->grp = grp;
 734         }
 735
 736         for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
 737                 if (!grp->tx_queue)
 738                         grp->tx_queue = priv->tx_queue[i];
 739                 grp->num_tx_queues++;
 740                 grp->tstat |= (TSTAT_CLEAR_THALT >> i);
 741                 priv->tqueue |= (TQUEUE_EN0 >> i);
 742                 priv->tx_queue[i]->grp = grp;
 743         }
 744
 745         priv->num_grps++;
 746
 747         return 0;
 748 }
 749
 750 static int gfar_of_group_count(struct device_node *np)
 751 {
 752         struct device_node *child;
 753         int num = 0;
 754
 755         for_each_available_child_of_node(np, child)
 756                 if (!of_node_cmp(child->name, "queue-group"))
 757                         num++;
 758
 759         return num;
 760 }
 761
 762 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
 763 {
 764         const char *model;
 765         const char *ctype;
 766         const void *mac_addr;
 767         int err = 0, i;
 768         struct net_device *dev = NULL;
 769         struct gfar_private *priv = NULL;
 770         struct device_node *np = ofdev->dev.of_node;
 771         struct device_node *child = NULL;
 772         struct property *stash;
 773         u32 stash_len = 0;
 774         u32 stash_idx = 0;
 775         unsigned int num_tx_qs, num_rx_qs;
 776         unsigned short mode, poll_mode;
 777
 778         if (!np)
 779                 return -ENODEV;
 780
 781         if (of_device_is_compatible(np, "fsl,etsec2")) {
 782                 mode = MQ_MG_MODE;
 783                 poll_mode = GFAR_SQ_POLLING;
 784         } else {
 785                 mode = SQ_SG_MODE;
 786                 poll_mode = GFAR_SQ_POLLING;
 787         }
 788
 789         if (mode == SQ_SG_MODE) {
 790                 num_tx_qs = 1;
 791                 num_rx_qs = 1;
 792         } else { /* MQ_MG_MODE */
 793                 /* get the actual number of supported groups */
 794                 unsigned int num_grps = gfar_of_group_count(np);
 795
 796                 if (num_grps == 0 || num_grps > MAXGROUPS) {
 797                         dev_err(&ofdev->dev, "Invalid # of int groups(%d)\n",
 798                                 num_grps);
 799                         pr_err("Cannot do alloc_etherdev, aborting\n");
 800                         return -EINVAL;
 801                 }
 802
 803                 if (poll_mode == GFAR_SQ_POLLING) {
 804                         num_tx_qs = num_grps; /* one txq per int group */
 805                         num_rx_qs = num_grps; /* one rxq per int group */
 806                 } else { /* GFAR_MQ_POLLING */
 807                         u32 tx_queues, rx_queues;
 808                         int ret;
 809
 810                         /* parse the num of HW tx and rx queues */
 811                         ret = of_property_read_u32(np, "fsl,num_tx_queues",
 812                                                    &tx_queues);
 813                         num_tx_qs = ret ? 1 : tx_queues;
 814
 815                         ret = of_property_read_u32(np, "fsl,num_rx_queues",
 816                                                    &rx_queues);
 817                         num_rx_qs = ret ? 1 : rx_queues;
 818                 }
 819         }
 820
 821         if (num_tx_qs > MAX_TX_QS) {
 822                 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
 823                        num_tx_qs, MAX_TX_QS);
 824                 pr_err("Cannot do alloc_etherdev, aborting\n");
 825                 return -EINVAL;
 826         }
 827
 828         if (num_rx_qs > MAX_RX_QS) {
 829                 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
 830                        num_rx_qs, MAX_RX_QS);
 831                 pr_err("Cannot do alloc_etherdev, aborting\n");
 832                 return -EINVAL;
 833         }
 834
 835         *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
 836         dev = *pdev;
 837         if (NULL == dev)
 838                 return -ENOMEM;
 839
 840         priv = netdev_priv(dev);
 841         priv->ndev = dev;
 842
 843         priv->mode = mode;
 844         priv->poll_mode = poll_mode;
 845
 846         priv->num_tx_queues = num_tx_qs;
 847         netif_set_real_num_rx_queues(dev, num_rx_qs);
 848         priv->num_rx_queues = num_rx_qs;
 849
 850         err = gfar_alloc_tx_queues(priv);
 851         if (err)
 852                 goto tx_alloc_failed;
 853
 854         err = gfar_alloc_rx_queues(priv);
 855         if (err)
 856                 goto rx_alloc_failed;
 857
 858         err = of_property_read_string(np, "model", &model);
 859         if (err) {
 860                 pr_err("Device model property missing, aborting\n");
 861                 goto rx_alloc_failed;
 862         }
 863
 864         /* Init Rx queue filer rule set linked list */
 865         INIT_LIST_HEAD(&priv->rx_list.list);
 866         priv->rx_list.count = 0;
 867         mutex_init(&priv->rx_queue_access);
 868
 869         for (i = 0; i < MAXGROUPS; i++)
 870                 priv->gfargrp[i].regs = NULL;
 871
 872         /* Parse and initialize group specific information */
 873         if (priv->mode == MQ_MG_MODE) {
 874                 for_each_available_child_of_node(np, child) {
 875                         if (of_node_cmp(child->name, "queue-group"))
 876                                 continue;
 877
 878                         err = gfar_parse_group(child, priv, model);
 879                         if (err)
 880                                 goto err_grp_init;
 881                 }
 882         } else { /* SQ_SG_MODE */
 883                 err = gfar_parse_group(np, priv, model);
 884                 if (err)
 885                         goto err_grp_init;
 886         }
 887
 888         stash = of_find_property(np, "bd-stash", NULL);
 889
 890         if (stash) {
 891                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
 892                 priv->bd_stash_en = 1;
 893         }
 894
 895         err = of_property_read_u32(np, "rx-stash-len", &stash_len);
 896
 897         if (err == 0)
 898                 priv->rx_stash_size = stash_len;
 899
 900         err = of_property_read_u32(np, "rx-stash-idx", &stash_idx);
 901
 902         if (err == 0)
 903                 priv->rx_stash_index = stash_idx;
 904
 905         if (stash_len || stash_idx)
 906                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
 907
 908         mac_addr = of_get_mac_address(np);
 909
 910         if (mac_addr)
 911                 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
 912
 913         if (model && !strcasecmp(model, "TSEC"))
 914                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
 915                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 916                                      FSL_GIANFAR_DEV_HAS_RMON |
 917                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR;
 918
 919         if (model && !strcasecmp(model, "eTSEC"))
 920                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
 921                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 922                                      FSL_GIANFAR_DEV_HAS_RMON |
 923                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR |
 924                                      FSL_GIANFAR_DEV_HAS_CSUM |
 925                                      FSL_GIANFAR_DEV_HAS_VLAN |
 926                                      FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
 927                                      FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
 928                                      FSL_GIANFAR_DEV_HAS_TIMER;
 929
 930         err = of_property_read_string(np, "phy-connection-type", &ctype);
 931
 932         /* We only care about rgmii-id.  The rest are autodetected */
 933         if (err == 0 && !strcmp(ctype, "rgmii-id"))
 934                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
 935         else
 936                 priv->interface = PHY_INTERFACE_MODE_MII;
 937
 938         if (of_find_property(np, "fsl,magic-packet", NULL))
 939                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
 940
 941         priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
 942
 943         /* In the case of a fixed PHY, the DT node associated
 944          * to the PHY is the Ethernet MAC DT node.
 945          */
 946         if (!priv->phy_node && of_phy_is_fixed_link(np)) {
 947                 err = of_phy_register_fixed_link(np);
 948                 if (err)
 949                         goto err_grp_init;
 950
 951                 priv->phy_node = of_node_get(np);
 952         }
 953
 954         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
 955         priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
 956
 957         return 0;
 958
 959 err_grp_init:
 960         unmap_group_regs(priv);
 961 rx_alloc_failed:
 962         gfar_free_rx_queues(priv);
 963 tx_alloc_failed:
 964         gfar_free_tx_queues(priv);
 965         free_gfar_dev(priv);
 966         return err;
 967 }
 968
 969 static int gfar_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
 970 {
 971         struct hwtstamp_config config;
 972         struct gfar_private *priv = netdev_priv(netdev);
 973
 974         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
 975                 return -EFAULT;
 976
 977         /* reserved for future extensions */
 978         if (config.flags)
 979                 return -EINVAL;
 980
 981         switch (config.tx_type) {
 982         case HWTSTAMP_TX_OFF:
 983                 priv->hwts_tx_en = 0;
 984                 break;
 985         case HWTSTAMP_TX_ON:
 986                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 987                         return -ERANGE;
 988                 priv->hwts_tx_en = 1;
 989                 break;
 990         default:
 991                 return -ERANGE;
 992         }
 993
 994         switch (config.rx_filter) {
 995         case HWTSTAMP_FILTER_NONE:
 996                 if (priv->hwts_rx_en) {
 997                         priv->hwts_rx_en = 0;
 998                         reset_gfar(netdev);
 999                 }
1000                 break;
1001         default:
1002                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
1003                         return -ERANGE;
1004                 if (!priv->hwts_rx_en) {
1005                         priv->hwts_rx_en = 1;
1006                         reset_gfar(netdev);
1007                 }
1008                 config.rx_filter = HWTSTAMP_FILTER_ALL;
1009                 break;
1010         }
1011
1012         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1013                 -EFAULT : 0;
1014 }
1015
1016 static int gfar_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
1017 {
1018         struct hwtstamp_config config;
1019         struct gfar_private *priv = netdev_priv(netdev);
1020
1021         config.flags = 0;
1022         config.tx_type = priv->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1023         config.rx_filter = (priv->hwts_rx_en ?
1024                             HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE);
1025
1026         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1027                 -EFAULT : 0;
1028 }
1029
1030 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1031 {
1032         struct gfar_private *priv = netdev_priv(dev);
1033
1034         if (!netif_running(dev))
1035                 return -EINVAL;
1036
1037         if (cmd == SIOCSHWTSTAMP)
1038                 return gfar_hwtstamp_set(dev, rq);
1039         if (cmd == SIOCGHWTSTAMP)
1040                 return gfar_hwtstamp_get(dev, rq);
1041
1042         if (!priv->phydev)
1043                 return -ENODEV;
1044
1045         return phy_mii_ioctl(priv->phydev, rq, cmd);
1046 }
1047
1048 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
1049                                    u32 class)
1050 {
1051         u32 rqfpr = FPR_FILER_MASK;
1052         u32 rqfcr = 0x0;
1053
1054         rqfar--;
1055         rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
1056         priv->ftp_rqfpr[rqfar] = rqfpr;
1057         priv->ftp_rqfcr[rqfar] = rqfcr;
1058         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1059
1060         rqfar--;
1061         rqfcr = RQFCR_CMP_NOMATCH;
1062         priv->ftp_rqfpr[rqfar] = rqfpr;
1063         priv->ftp_rqfcr[rqfar] = rqfcr;
1064         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1065
1066         rqfar--;
1067         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
1068         rqfpr = class;
1069         priv->ftp_rqfcr[rqfar] = rqfcr;
1070         priv->ftp_rqfpr[rqfar] = rqfpr;
1071         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1072
1073         rqfar--;
1074         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
1075         rqfpr = class;
1076         priv->ftp_rqfcr[rqfar] = rqfcr;
1077         priv->ftp_rqfpr[rqfar] = rqfpr;
1078         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1079
1080         return rqfar;
1081 }
1082
1083 static void gfar_init_filer_table(struct gfar_private *priv)
1084 {
1085         int i = 0x0;
1086         u32 rqfar = MAX_FILER_IDX;
1087         u32 rqfcr = 0x0;
1088         u32 rqfpr = FPR_FILER_MASK;
1089
1090         /* Default rule */
1091         rqfcr = RQFCR_CMP_MATCH;
1092         priv->ftp_rqfcr[rqfar] = rqfcr;
1093         priv->ftp_rqfpr[rqfar] = rqfpr;
1094         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1095
1096         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
1097         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
1098         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
1099         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
1100         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
1101         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
1102
1103         /* cur_filer_idx indicated the first non-masked rule */
1104         priv->cur_filer_idx = rqfar;
1105
1106         /* Rest are masked rules */
1107         rqfcr = RQFCR_CMP_NOMATCH;
1108         for (i = 0; i < rqfar; i++) {
1109                 priv->ftp_rqfcr[i] = rqfcr;
1110                 priv->ftp_rqfpr[i] = rqfpr;
1111                 gfar_write_filer(priv, i, rqfcr, rqfpr);
1112         }
1113 }
1114
1115 #ifdef CONFIG_PPC
1116 static void __gfar_detect_errata_83xx(struct gfar_private *priv)
1117 {
1118         unsigned int pvr = mfspr(SPRN_PVR);
1119         unsigned int svr = mfspr(SPRN_SVR);
1120         unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
1121         unsigned int rev = svr & 0xffff;
1122
1123         /* MPC8313 Rev 2.0 and higher; All MPC837x */
1124         if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
1125             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
1126                 priv->errata |= GFAR_ERRATA_74;
1127
1128         /* MPC8313 and MPC837x all rev */
1129         if ((pvr == 0x80850010 && mod == 0x80b0) ||
1130             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
1131                 priv->errata |= GFAR_ERRATA_76;
1132
1133         /* MPC8313 Rev < 2.0 */
1134         if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020)
1135                 priv->errata |= GFAR_ERRATA_12;
1136 }
1137
1138 static void __gfar_detect_errata_85xx(struct gfar_private *priv)
1139 {
1140         unsigned int svr = mfspr(SPRN_SVR);
1141
1142         if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20))
1143                 priv->errata |= GFAR_ERRATA_12;
1144         if (((SVR_SOC_VER(svr) == SVR_P2020) && (SVR_REV(svr) < 0x20)) ||
1145             ((SVR_SOC_VER(svr) == SVR_P2010) && (SVR_REV(svr) < 0x20)))
1146                 priv->errata |= GFAR_ERRATA_76; /* aka eTSEC 20 */
1147 }
1148 #endif
1149
1150 static void gfar_detect_errata(struct gfar_private *priv)
1151 {
1152         struct device *dev = &priv->ofdev->dev;
1153
1154         /* no plans to fix */
1155         priv->errata |= GFAR_ERRATA_A002;
1156
1157 #ifdef CONFIG_PPC
1158         if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2))
1159                 __gfar_detect_errata_85xx(priv);
1160         else /* non-mpc85xx parts, i.e. e300 core based */
1161                 __gfar_detect_errata_83xx(priv);
1162 #endif
1163
1164         if (priv->errata)
1165                 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
1166                          priv->errata);
1167 }
1168
1169 void gfar_mac_reset(struct gfar_private *priv)
1170 {
1171         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1172         u32 tempval;
1173
1174         /* Reset MAC layer */
1175         gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1176
1177         /* We need to delay at least 3 TX clocks */
1178         udelay(3);
1179
1180         /* the soft reset bit is not self-resetting, so we need to
1181          * clear it before resuming normal operation
1182          */
1183         gfar_write(&regs->maccfg1, 0);
1184
1185         udelay(3);
1186
1187         /* Compute rx_buff_size based on config flags */
1188         gfar_rx_buff_size_config(priv);
1189
1190         /* Initialize the max receive frame/buffer lengths */
1191         gfar_write(&regs->maxfrm, priv->rx_buffer_size);
1192         gfar_write(&regs->mrblr, priv->rx_buffer_size);
1193
1194         /* Initialize the Minimum Frame Length Register */
1195         gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1196
1197         /* Initialize MACCFG2. */
1198         tempval = MACCFG2_INIT_SETTINGS;
1199
1200         /* If the mtu is larger than the max size for standard
1201          * ethernet frames (ie, a jumbo frame), then set maccfg2
1202          * to allow huge frames, and to check the length
1203          */
1204         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
1205             gfar_has_errata(priv, GFAR_ERRATA_74))
1206                 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1207
1208         gfar_write(&regs->maccfg2, tempval);
1209
1210         /* Clear mac addr hash registers */
1211         gfar_write(&regs->igaddr0, 0);
1212         gfar_write(&regs->igaddr1, 0);
1213         gfar_write(&regs->igaddr2, 0);
1214         gfar_write(&regs->igaddr3, 0);
1215         gfar_write(&regs->igaddr4, 0);
1216         gfar_write(&regs->igaddr5, 0);
1217         gfar_write(&regs->igaddr6, 0);
1218         gfar_write(&regs->igaddr7, 0);
1219
1220         gfar_write(&regs->gaddr0, 0);
1221         gfar_write(&regs->gaddr1, 0);
1222         gfar_write(&regs->gaddr2, 0);
1223         gfar_write(&regs->gaddr3, 0);
1224         gfar_write(&regs->gaddr4, 0);
1225         gfar_write(&regs->gaddr5, 0);
1226         gfar_write(&regs->gaddr6, 0);
1227         gfar_write(&regs->gaddr7, 0);
1228
1229         if (priv->extended_hash)
1230                 gfar_clear_exact_match(priv->ndev);
1231
1232         gfar_mac_rx_config(priv);
1233
1234         gfar_mac_tx_config(priv);
1235
1236         gfar_set_mac_address(priv->ndev);
1237
1238         gfar_set_multi(priv->ndev);
1239
1240         /* clear ievent and imask before configuring coalescing */
1241         gfar_ints_disable(priv);
1242
1243         /* Configure the coalescing support */
1244         gfar_configure_coalescing_all(priv);
1245 }
1246
1247 static void gfar_hw_init(struct gfar_private *priv)
1248 {
1249         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1250         u32 attrs;
1251
1252         /* Stop the DMA engine now, in case it was running before
1253          * (The firmware could have used it, and left it running).
1254          */
1255         gfar_halt(priv);
1256
1257         gfar_mac_reset(priv);
1258
1259         /* Zero out the rmon mib registers if it has them */
1260         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1261                 memset_io(&(regs->rmon), 0, sizeof(struct rmon_mib));
1262
1263                 /* Mask off the CAM interrupts */
1264                 gfar_write(&regs->rmon.cam1, 0xffffffff);
1265                 gfar_write(&regs->rmon.cam2, 0xffffffff);
1266         }
1267
1268         /* Initialize ECNTRL */
1269         gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1270
1271         /* Set the extraction length and index */
1272         attrs = ATTRELI_EL(priv->rx_stash_size) |
1273                 ATTRELI_EI(priv->rx_stash_index);
1274
1275         gfar_write(&regs->attreli, attrs);
1276
1277         /* Start with defaults, and add stashing
1278          * depending on driver parameters
1279          */
1280         attrs = ATTR_INIT_SETTINGS;
1281
1282         if (priv->bd_stash_en)
1283                 attrs |= ATTR_BDSTASH;
1284
1285         if (priv->rx_stash_size != 0)
1286                 attrs |= ATTR_BUFSTASH;
1287
1288         gfar_write(&regs->attr, attrs);
1289
1290         /* FIFO configs */
1291         gfar_write(&regs->fifo_tx_thr, DEFAULT_FIFO_TX_THR);
1292         gfar_write(&regs->fifo_tx_starve, DEFAULT_FIFO_TX_STARVE);
1293         gfar_write(&regs->fifo_tx_starve_shutoff, DEFAULT_FIFO_TX_STARVE_OFF);
1294
1295         /* Program the interrupt steering regs, only for MG devices */
1296         if (priv->num_grps > 1)
1297                 gfar_write_isrg(priv);
1298 }
1299
1300 static void gfar_init_addr_hash_table(struct gfar_private *priv)
1301 {
1302         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1303
1304         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1305                 priv->extended_hash = 1;
1306                 priv->hash_width = 9;
1307
1308                 priv->hash_regs[0] = &regs->igaddr0;
1309                 priv->hash_regs[1] = &regs->igaddr1;
1310                 priv->hash_regs[2] = &regs->igaddr2;
1311                 priv->hash_regs[3] = &regs->igaddr3;
1312                 priv->hash_regs[4] = &regs->igaddr4;
1313                 priv->hash_regs[5] = &regs->igaddr5;
1314                 priv->hash_regs[6] = &regs->igaddr6;
1315                 priv->hash_regs[7] = &regs->igaddr7;
1316                 priv->hash_regs[8] = &regs->gaddr0;
1317                 priv->hash_regs[9] = &regs->gaddr1;
1318                 priv->hash_regs[10] = &regs->gaddr2;
1319                 priv->hash_regs[11] = &regs->gaddr3;
1320                 priv->hash_regs[12] = &regs->gaddr4;
1321                 priv->hash_regs[13] = &regs->gaddr5;
1322                 priv->hash_regs[14] = &regs->gaddr6;
1323                 priv->hash_regs[15] = &regs->gaddr7;
1324
1325         } else {
1326                 priv->extended_hash = 0;
1327                 priv->hash_width = 8;
1328
1329                 priv->hash_regs[0] = &regs->gaddr0;
1330                 priv->hash_regs[1] = &regs->gaddr1;
1331                 priv->hash_regs[2] = &regs->gaddr2;
1332                 priv->hash_regs[3] = &regs->gaddr3;
1333                 priv->hash_regs[4] = &regs->gaddr4;
1334                 priv->hash_regs[5] = &regs->gaddr5;
1335                 priv->hash_regs[6] = &regs->gaddr6;
1336                 priv->hash_regs[7] = &regs->gaddr7;
1337         }
1338 }
1339
1340 /* Set up the ethernet device structure, private data,
1341  * and anything else we need before we start
1342  */
1343 static int gfar_probe(struct platform_device *ofdev)
1344 {
1345         struct net_device *dev = NULL;
1346         struct gfar_private *priv = NULL;
1347         int err = 0, i;
1348
1349         err = gfar_of_init(ofdev, &dev);
1350
1351         if (err)
1352                 return err;
1353
1354         priv = netdev_priv(dev);
1355         priv->ndev = dev;
1356         priv->ofdev = ofdev;
1357         priv->dev = &ofdev->dev;
1358         SET_NETDEV_DEV(dev, &ofdev->dev);
1359
1360         spin_lock_init(&priv->bflock);
1361         INIT_WORK(&priv->reset_task, gfar_reset_task);
1362
1363         platform_set_drvdata(ofdev, priv);
1364
1365         gfar_detect_errata(priv);
1366
1367         /* Set the dev->base_addr to the gfar reg region */
1368         dev->base_addr = (unsigned long) priv->gfargrp[0].regs;
1369
1370         /* Fill in the dev structure */
1371         dev->watchdog_timeo = TX_TIMEOUT;
1372         dev->mtu = 1500;
1373         dev->netdev_ops = &gfar_netdev_ops;
1374         dev->ethtool_ops = &gfar_ethtool_ops;
1375
1376         /* Register for napi ...We are registering NAPI for each grp */
1377         for (i = 0; i < priv->num_grps; i++) {
1378                 if (priv->poll_mode == GFAR_SQ_POLLING) {
1379                         netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1380                                        gfar_poll_rx_sq, GFAR_DEV_WEIGHT);
1381                         netif_napi_add(dev, &priv->gfargrp[i].napi_tx,
1382                                        gfar_poll_tx_sq, 2);
1383                 } else {
1384                         netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1385                                        gfar_poll_rx, GFAR_DEV_WEIGHT);
1386                         netif_napi_add(dev, &priv->gfargrp[i].napi_tx,
1387                                        gfar_poll_tx, 2);
1388                 }
1389         }
1390
1391         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1392                 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1393                                    NETIF_F_RXCSUM;
1394                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1395                                  NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1396         }
1397
1398         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
1399                 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
1400                                     NETIF_F_HW_VLAN_CTAG_RX;
1401                 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
1402         }
1403
1404         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
1405
1406         gfar_init_addr_hash_table(priv);
1407
1408         /* Insert receive time stamps into padding alignment bytes */
1409         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1410                 priv->padding = 8;
1411
1412         if (dev->features & NETIF_F_IP_CSUM ||
1413             priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1414                 dev->needed_headroom = GMAC_FCB_LEN;
1415
1416         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1417
1418         /* Initializing some of the rx/tx queue level parameters */
1419         for (i = 0; i < priv->num_tx_queues; i++) {
1420                 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1421                 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1422                 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1423                 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1424         }
1425
1426         for (i = 0; i < priv->num_rx_queues; i++) {
1427                 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1428                 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1429                 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1430         }
1431
1432         /* always enable rx filer */
1433         priv->rx_filer_enable = 1;
1434         /* Enable most messages by default */
1435         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1436         /* use pritority h/w tx queue scheduling for single queue devices */
1437         if (priv->num_tx_queues == 1)
1438                 priv->prio_sched_en = 1;
1439
1440         set_bit(GFAR_DOWN, &priv->state);
1441
1442         gfar_hw_init(priv);
1443
1444         /* Carrier starts down, phylib will bring it up */
1445         netif_carrier_off(dev);
1446
1447         err = register_netdev(dev);
1448
1449         if (err) {
1450                 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1451                 goto register_fail;
1452         }
1453
1454         device_init_wakeup(&dev->dev,
1455                            priv->device_flags &
1456                            FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1457
1458         /* fill out IRQ number and name fields */
1459         for (i = 0; i < priv->num_grps; i++) {
1460                 struct gfar_priv_grp *grp = &priv->gfargrp[i];
1461                 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1462                         sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
1463                                 dev->name, "_g", '0' + i, "_tx");
1464                         sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
1465                                 dev->name, "_g", '0' + i, "_rx");
1466                         sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
1467                                 dev->name, "_g", '0' + i, "_er");
1468                 } else
1469                         strcpy(gfar_irq(grp, TX)->name, dev->name);
1470         }
1471
1472         /* Initialize the filer table */
1473         gfar_init_filer_table(priv);
1474
1475         /* Print out the device info */
1476         netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1477
1478         /* Even more device info helps when determining which kernel
1479          * provided which set of benchmarks.
1480          */
1481         netdev_info(dev, "Running with NAPI enabled\n");
1482         for (i = 0; i < priv->num_rx_queues; i++)
1483                 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1484                             i, priv->rx_queue[i]->rx_ring_size);
1485         for (i = 0; i < priv->num_tx_queues; i++)
1486                 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1487                             i, priv->tx_queue[i]->tx_ring_size);
1488
1489         return 0;
1490
1491 register_fail:
1492         unmap_group_regs(priv);
1493         gfar_free_rx_queues(priv);
1494         gfar_free_tx_queues(priv);
1495         of_node_put(priv->phy_node);
1496         of_node_put(priv->tbi_node);
1497         free_gfar_dev(priv);
1498         return err;
1499 }
1500
1501 static int gfar_remove(struct platform_device *ofdev)
1502 {
1503         struct gfar_private *priv = platform_get_drvdata(ofdev);
1504
1505         of_node_put(priv->phy_node);
1506         of_node_put(priv->tbi_node);
1507
1508         unregister_netdev(priv->ndev);
1509         unmap_group_regs(priv);
1510         gfar_free_rx_queues(priv);
1511         gfar_free_tx_queues(priv);
1512         free_gfar_dev(priv);
1513
1514         return 0;
1515 }
1516
1517 #ifdef CONFIG_PM
1518
1519 static int gfar_suspend(struct device *dev)
1520 {
1521         struct gfar_private *priv = dev_get_drvdata(dev);
1522         struct net_device *ndev = priv->ndev;
1523         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1524         unsigned long flags;
1525         u32 tempval;
1526
1527         int magic_packet = priv->wol_en &&
1528                            (priv->device_flags &
1529                             FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1530
1531         netif_device_detach(ndev);
1532
1533         if (netif_running(ndev)) {
1534
1535                 local_irq_save(flags);
1536                 lock_tx_qs(priv);
1537
1538                 gfar_halt_nodisable(priv);
1539
1540                 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1541                 tempval = gfar_read(&regs->maccfg1);
1542
1543                 tempval &= ~MACCFG1_TX_EN;
1544
1545                 if (!magic_packet)
1546                         tempval &= ~MACCFG1_RX_EN;
1547
1548                 gfar_write(&regs->maccfg1, tempval);
1549
1550                 unlock_tx_qs(priv);
1551                 local_irq_restore(flags);
1552
1553                 disable_napi(priv);
1554
1555                 if (magic_packet) {
1556                         /* Enable interrupt on Magic Packet */
1557                         gfar_write(&regs->imask, IMASK_MAG);
1558
1559                         /* Enable Magic Packet mode */
1560                         tempval = gfar_read(&regs->maccfg2);
1561                         tempval |= MACCFG2_MPEN;
1562                         gfar_write(&regs->maccfg2, tempval);
1563                 } else {
1564                         phy_stop(priv->phydev);
1565                 }
1566         }
1567
1568         return 0;
1569 }
1570
1571 static int gfar_resume(struct device *dev)
1572 {
1573         struct gfar_private *priv = dev_get_drvdata(dev);
1574         struct net_device *ndev = priv->ndev;
1575         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1576         unsigned long flags;
1577         u32 tempval;
1578         int magic_packet = priv->wol_en &&
1579                            (priv->device_flags &
1580                             FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1581
1582         if (!netif_running(ndev)) {
1583                 netif_device_attach(ndev);
1584                 return 0;
1585         }
1586
1587         if (!magic_packet && priv->phydev)
1588                 phy_start(priv->phydev);
1589
1590         /* Disable Magic Packet mode, in case something
1591          * else woke us up.
1592          */
1593         local_irq_save(flags);
1594         lock_tx_qs(priv);
1595
1596         tempval = gfar_read(&regs->maccfg2);
1597         tempval &= ~MACCFG2_MPEN;
1598         gfar_write(&regs->maccfg2, tempval);
1599
1600         gfar_start(priv);
1601
1602         unlock_tx_qs(priv);
1603         local_irq_restore(flags);
1604
1605         netif_device_attach(ndev);
1606
1607         enable_napi(priv);
1608
1609         return 0;
1610 }
1611
1612 static int gfar_restore(struct device *dev)
1613 {
1614         struct gfar_private *priv = dev_get_drvdata(dev);
1615         struct net_device *ndev = priv->ndev;
1616
1617         if (!netif_running(ndev)) {
1618                 netif_device_attach(ndev);
1619
1620                 return 0;
1621         }
1622
1623         gfar_init_bds(ndev);
1624
1625         gfar_mac_reset(priv);
1626
1627         gfar_init_tx_rx_base(priv);
1628
1629         gfar_start(priv);
1630
1631         priv->oldlink = 0;
1632         priv->oldspeed = 0;
1633         priv->oldduplex = -1;
1634
1635         if (priv->phydev)
1636                 phy_start(priv->phydev);
1637
1638         netif_device_attach(ndev);
1639         enable_napi(priv);
1640
1641         return 0;
1642 }
1643
1644 static struct dev_pm_ops gfar_pm_ops = {
1645         .suspend = gfar_suspend,
1646         .resume = gfar_resume,
1647         .freeze = gfar_suspend,
1648         .thaw = gfar_resume,
1649         .restore = gfar_restore,
1650 };
1651
1652 #define GFAR_PM_OPS (&gfar_pm_ops)
1653
1654 #else
1655
1656 #define GFAR_PM_OPS NULL
1657
1658 #endif
1659
1660 /* Reads the controller's registers to determine what interface
1661  * connects it to the PHY.
1662  */
1663 static phy_interface_t gfar_get_interface(struct net_device *dev)
1664 {
1665         struct gfar_private *priv = netdev_priv(dev);
1666         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1667         u32 ecntrl;
1668
1669         ecntrl = gfar_read(&regs->ecntrl);
1670
1671         if (ecntrl & ECNTRL_SGMII_MODE)
1672                 return PHY_INTERFACE_MODE_SGMII;
1673
1674         if (ecntrl & ECNTRL_TBI_MODE) {
1675                 if (ecntrl & ECNTRL_REDUCED_MODE)
1676                         return PHY_INTERFACE_MODE_RTBI;
1677                 else
1678                         return PHY_INTERFACE_MODE_TBI;
1679         }
1680
1681         if (ecntrl & ECNTRL_REDUCED_MODE) {
1682                 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
1683                         return PHY_INTERFACE_MODE_RMII;
1684                 }
1685                 else {
1686                         phy_interface_t interface = priv->interface;
1687
1688                         /* This isn't autodetected right now, so it must
1689                          * be set by the device tree or platform code.
1690                          */
1691                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1692                                 return PHY_INTERFACE_MODE_RGMII_ID;
1693
1694                         return PHY_INTERFACE_MODE_RGMII;
1695                 }
1696         }
1697
1698         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1699                 return PHY_INTERFACE_MODE_GMII;
1700
1701         return PHY_INTERFACE_MODE_MII;
1702 }
1703
1704
1705 /* Initializes driver's PHY state, and attaches to the PHY.
1706  * Returns 0 on success.
1707  */
1708 static int init_phy(struct net_device *dev)
1709 {
1710         struct gfar_private *priv = netdev_priv(dev);
1711         uint gigabit_support =
1712                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1713                 GFAR_SUPPORTED_GBIT : 0;
1714         phy_interface_t interface;
1715
1716         priv->oldlink = 0;
1717         priv->oldspeed = 0;
1718         priv->oldduplex = -1;
1719
1720         interface = gfar_get_interface(dev);
1721
1722         priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1723                                       interface);
1724         if (!priv->phydev) {
1725                 dev_err(&dev->dev, "could not attach to PHY\n");
1726                 return -ENODEV;
1727         }
1728
1729         if (interface == PHY_INTERFACE_MODE_SGMII)
1730                 gfar_configure_serdes(dev);
1731
1732         /* Remove any features not supported by the controller */
1733         priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1734         priv->phydev->advertising = priv->phydev->supported;
1735
1736         /* Add support for flow control, but don't advertise it by default */
1737         priv->phydev->supported |= (SUPPORTED_Pause | SUPPORTED_Asym_Pause);
1738
1739         return 0;
1740 }
1741
1742 /* Initialize TBI PHY interface for communicating with the
1743  * SERDES lynx PHY on the chip.  We communicate with this PHY
1744  * through the MDIO bus on each controller, treating it as a
1745  * "normal" PHY at the address found in the TBIPA register.  We assume
1746  * that the TBIPA register is valid.  Either the MDIO bus code will set
1747  * it to a value that doesn't conflict with other PHYs on the bus, or the
1748  * value doesn't matter, as there are no other PHYs on the bus.
1749  */
1750 static void gfar_configure_serdes(struct net_device *dev)
1751 {
1752         struct gfar_private *priv = netdev_priv(dev);
1753         struct phy_device *tbiphy;
1754
1755         if (!priv->tbi_node) {
1756                 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1757                                     "device tree specify a tbi-handle\n");
1758                 return;
1759         }
1760
1761         tbiphy = of_phy_find_device(priv->tbi_node);
1762         if (!tbiphy) {
1763                 dev_err(&dev->dev, "error: Could not get TBI device\n");
1764                 return;
1765         }
1766
1767         /* If the link is already up, we must already be ok, and don't need to
1768          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
1769          * everything for us?  Resetting it takes the link down and requires
1770          * several seconds for it to come back.
1771          */
1772         if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
1773                 return;
1774
1775         /* Single clk mode, mii mode off(for serdes communication) */
1776         phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1777
1778         phy_write(tbiphy, MII_ADVERTISE,
1779                   ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1780                   ADVERTISE_1000XPSE_ASYM);
1781
1782         phy_write(tbiphy, MII_BMCR,
1783                   BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1784                   BMCR_SPEED1000);
1785 }
1786
1787 static int __gfar_is_rx_idle(struct gfar_private *priv)
1788 {
1789         u32 res;
1790
1791         /* Normaly TSEC should not hang on GRS commands, so we should
1792          * actually wait for IEVENT_GRSC flag.
1793          */
1794         if (!gfar_has_errata(priv, GFAR_ERRATA_A002))
1795                 return 0;
1796
1797         /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1798          * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1799          * and the Rx can be safely reset.
1800          */
1801         res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1802         res &= 0x7f807f80;
1803         if ((res & 0xffff) == (res >> 16))
1804                 return 1;
1805
1806         return 0;
1807 }
1808
1809 /* Halt the receive and transmit queues */
1810 static void gfar_halt_nodisable(struct gfar_private *priv)
1811 {
1812         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1813         u32 tempval;
1814         unsigned int timeout;
1815         int stopped;
1816
1817         gfar_ints_disable(priv);
1818
1819         if (gfar_is_dma_stopped(priv))
1820                 return;
1821
1822         /* Stop the DMA, and wait for it to stop */
1823         tempval = gfar_read(&regs->dmactrl);
1824         tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1825         gfar_write(&regs->dmactrl, tempval);
1826
1827 retry:
1828         timeout = 1000;
1829         while (!(stopped = gfar_is_dma_stopped(priv)) && timeout) {
1830                 cpu_relax();
1831                 timeout--;
1832         }
1833
1834         if (!timeout)
1835                 stopped = gfar_is_dma_stopped(priv);
1836
1837         if (!stopped && !gfar_is_rx_dma_stopped(priv) &&
1838             !__gfar_is_rx_idle(priv))
1839                 goto retry;
1840 }
1841
1842 /* Halt the receive and transmit queues */
1843 void gfar_halt(struct gfar_private *priv)
1844 {
1845         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1846         u32 tempval;
1847
1848         /* Dissable the Rx/Tx hw queues */
1849         gfar_write(&regs->rqueue, 0);
1850         gfar_write(&regs->tqueue, 0);
1851
1852         mdelay(10);
1853
1854         gfar_halt_nodisable(priv);
1855
1856         /* Disable Rx/Tx DMA */
1857         tempval = gfar_read(&regs->maccfg1);
1858         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1859         gfar_write(&regs->maccfg1, tempval);
1860 }
1861
1862 void stop_gfar(struct net_device *dev)
1863 {
1864         struct gfar_private *priv = netdev_priv(dev);
1865
1866         netif_tx_stop_all_queues(dev);
1867
1868         smp_mb__before_atomic();
1869         set_bit(GFAR_DOWN, &priv->state);
1870         smp_mb__after_atomic();
1871
1872         disable_napi(priv);
1873
1874         /* disable ints and gracefully shut down Rx/Tx DMA */
1875         gfar_halt(priv);
1876
1877         phy_stop(priv->phydev);
1878
1879         free_skb_resources(priv);
1880 }
1881
1882 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1883 {
1884         struct txbd8 *txbdp;
1885         struct gfar_private *priv = netdev_priv(tx_queue->dev);
1886         int i, j;
1887
1888         txbdp = tx_queue->tx_bd_base;
1889
1890         for (i = 0; i < tx_queue->tx_ring_size; i++) {
1891                 if (!tx_queue->tx_skbuff[i])
1892                         continue;
1893
1894                 dma_unmap_single(priv->dev, be32_to_cpu(txbdp->bufPtr),
1895                                  be16_to_cpu(txbdp->length), DMA_TO_DEVICE);
1896                 txbdp->lstatus = 0;
1897                 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1898                      j++) {
1899                         txbdp++;
1900                         dma_unmap_page(priv->dev, be32_to_cpu(txbdp->bufPtr),
1901                                        be16_to_cpu(txbdp->length),
1902                                        DMA_TO_DEVICE);
1903                 }
1904                 txbdp++;
1905                 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1906                 tx_queue->tx_skbuff[i] = NULL;
1907         }
1908         kfree(tx_queue->tx_skbuff);
1909         tx_queue->tx_skbuff = NULL;
1910 }
1911
1912 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1913 {
1914         struct rxbd8 *rxbdp;
1915         struct gfar_private *priv = netdev_priv(rx_queue->ndev);
1916         int i;
1917
1918         rxbdp = rx_queue->rx_bd_base;
1919
1920         for (i = 0; i < rx_queue->rx_ring_size; i++) {
1921                 if (rx_queue->rx_skbuff[i]) {
1922                         dma_unmap_single(priv->dev, be32_to_cpu(rxbdp->bufPtr),
1923                                          priv->rx_buffer_size,
1924                                          DMA_FROM_DEVICE);
1925                         dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1926                         rx_queue->rx_skbuff[i] = NULL;
1927                 }
1928                 rxbdp->lstatus = 0;
1929                 rxbdp->bufPtr = 0;
1930                 rxbdp++;
1931         }
1932         kfree(rx_queue->rx_skbuff);
1933         rx_queue->rx_skbuff = NULL;
1934 }
1935
1936 /* If there are any tx skbs or rx skbs still around, free them.
1937  * Then free tx_skbuff and rx_skbuff
1938  */
1939 static void free_skb_resources(struct gfar_private *priv)
1940 {
1941         struct gfar_priv_tx_q *tx_queue = NULL;
1942         struct gfar_priv_rx_q *rx_queue = NULL;
1943         int i;
1944
1945         /* Go through all the buffer descriptors and free their data buffers */
1946         for (i = 0; i < priv->num_tx_queues; i++) {
1947                 struct netdev_queue *txq;
1948
1949                 tx_queue = priv->tx_queue[i];
1950                 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
1951                 if (tx_queue->tx_skbuff)
1952                         free_skb_tx_queue(tx_queue);
1953                 netdev_tx_reset_queue(txq);
1954         }
1955
1956         for (i = 0; i < priv->num_rx_queues; i++) {
1957                 rx_queue = priv->rx_queue[i];
1958                 if (rx_queue->rx_skbuff)
1959                         free_skb_rx_queue(rx_queue);
1960         }
1961
1962         dma_free_coherent(priv->dev,
1963                           sizeof(struct txbd8) * priv->total_tx_ring_size +
1964                           sizeof(struct rxbd8) * priv->total_rx_ring_size,
1965                           priv->tx_queue[0]->tx_bd_base,
1966                           priv->tx_queue[0]->tx_bd_dma_base);
1967 }
1968
1969 void gfar_start(struct gfar_private *priv)
1970 {
1971         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1972         u32 tempval;
1973         int i = 0;
1974
1975         /* Enable Rx/Tx hw queues */
1976         gfar_write(&regs->rqueue, priv->rqueue);
1977         gfar_write(&regs->tqueue, priv->tqueue);
1978
1979         /* Initialize DMACTRL to have WWR and WOP */
1980         tempval = gfar_read(&regs->dmactrl);
1981         tempval |= DMACTRL_INIT_SETTINGS;
1982         gfar_write(&regs->dmactrl, tempval);
1983
1984         /* Make sure we aren't stopped */
1985         tempval = gfar_read(&regs->dmactrl);
1986         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1987         gfar_write(&regs->dmactrl, tempval);
1988
1989         for (i = 0; i < priv->num_grps; i++) {
1990                 regs = priv->gfargrp[i].regs;
1991                 /* Clear THLT/RHLT, so that the DMA starts polling now */
1992                 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1993                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1994         }
1995
1996         /* Enable Rx/Tx DMA */
1997         tempval = gfar_read(&regs->maccfg1);
1998         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1999         gfar_write(&regs->maccfg1, tempval);
2000
2001         gfar_ints_enable(priv);
2002
2003         priv->ndev->trans_start = jiffies; /* prevent tx timeout */
2004 }
2005
2006 static void free_grp_irqs(struct gfar_priv_grp *grp)
2007 {
2008         free_irq(gfar_irq(grp, TX)->irq, grp);
2009         free_irq(gfar_irq(grp, RX)->irq, grp);
2010         free_irq(gfar_irq(grp, ER)->irq, grp);
2011 }
2012
2013 static int register_grp_irqs(struct gfar_priv_grp *grp)
2014 {
2015         struct gfar_private *priv = grp->priv;
2016         struct net_device *dev = priv->ndev;
2017         int err;
2018
2019         /* If the device has multiple interrupts, register for
2020          * them.  Otherwise, only register for the one
2021          */
2022         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2023                 /* Install our interrupt handlers for Error,
2024                  * Transmit, and Receive
2025                  */
2026                 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
2027                                   gfar_irq(grp, ER)->name, grp);
2028                 if (err < 0) {
2029                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2030                                   gfar_irq(grp, ER)->irq);
2031
2032                         goto err_irq_fail;
2033                 }
2034                 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
2035                                   gfar_irq(grp, TX)->name, grp);
2036                 if (err < 0) {
2037                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2038                                   gfar_irq(grp, TX)->irq);
2039                         goto tx_irq_fail;
2040                 }
2041                 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
2042                                   gfar_irq(grp, RX)->name, grp);
2043                 if (err < 0) {
2044                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2045                                   gfar_irq(grp, RX)->irq);
2046                         goto rx_irq_fail;
2047                 }
2048         } else {
2049                 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
2050                                   gfar_irq(grp, TX)->name, grp);
2051                 if (err < 0) {
2052                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2053                                   gfar_irq(grp, TX)->irq);
2054                         goto err_irq_fail;
2055                 }
2056         }
2057
2058         return 0;
2059
2060 rx_irq_fail:
2061         free_irq(gfar_irq(grp, TX)->irq, grp);
2062 tx_irq_fail:
2063         free_irq(gfar_irq(grp, ER)->irq, grp);
2064 err_irq_fail:
2065         return err;
2066
2067 }
2068
2069 static void gfar_free_irq(struct gfar_private *priv)
2070 {
2071         int i;
2072
2073         /* Free the IRQs */
2074         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2075                 for (i = 0; i < priv->num_grps; i++)
2076                         free_grp_irqs(&priv->gfargrp[i]);
2077         } else {
2078                 for (i = 0; i < priv->num_grps; i++)
2079                         free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
2080                                  &priv->gfargrp[i]);
2081         }
2082 }
2083
2084 static int gfar_request_irq(struct gfar_private *priv)
2085 {
2086         int err, i, j;
2087
2088         for (i = 0; i < priv->num_grps; i++) {
2089                 err = register_grp_irqs(&priv->gfargrp[i]);
2090                 if (err) {
2091                         for (j = 0; j < i; j++)
2092                                 free_grp_irqs(&priv->gfargrp[j]);
2093                         return err;
2094                 }
2095         }
2096
2097         return 0;
2098 }
2099
2100 /* Bring the controller up and running */
2101 int startup_gfar(struct net_device *ndev)
2102 {
2103         struct gfar_private *priv = netdev_priv(ndev);
2104         int err;
2105
2106         gfar_mac_reset(priv);
2107
2108         err = gfar_alloc_skb_resources(ndev);
2109         if (err)
2110                 return err;
2111
2112         gfar_init_tx_rx_base(priv);
2113
2114         smp_mb__before_atomic();
2115         clear_bit(GFAR_DOWN, &priv->state);
2116         smp_mb__after_atomic();
2117
2118         /* Start Rx/Tx DMA and enable the interrupts */
2119         gfar_start(priv);
2120
2121         phy_start(priv->phydev);
2122
2123         enable_napi(priv);
2124
2125         netif_tx_wake_all_queues(ndev);
2126
2127         return 0;
2128 }
2129
2130 /* Called when something needs to use the ethernet device
2131  * Returns 0 for success.
2132  */
2133 static int gfar_enet_open(struct net_device *dev)
2134 {
2135         struct gfar_private *priv = netdev_priv(dev);
2136         int err;
2137
2138         err = init_phy(dev);
2139         if (err)
2140                 return err;
2141
2142         err = gfar_request_irq(priv);
2143         if (err)
2144                 return err;
2145
2146         err = startup_gfar(dev);
2147         if (err)
2148                 return err;
2149
2150         device_set_wakeup_enable(&dev->dev, priv->wol_en);
2151
2152         return err;
2153 }
2154
2155 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
2156 {
2157         struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
2158
2159         memset(fcb, 0, GMAC_FCB_LEN);
2160
2161         return fcb;
2162 }
2163
2164 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
2165                                     int fcb_length)
2166 {
2167         /* If we're here, it's a IP packet with a TCP or UDP
2168          * payload.  We set it to checksum, using a pseudo-header
2169          * we provide
2170          */
2171         u8 flags = TXFCB_DEFAULT;
2172
2173         /* Tell the controller what the protocol is
2174          * And provide the already calculated phcs
2175          */
2176         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
2177                 flags |= TXFCB_UDP;
2178                 fcb->phcs = (__force __be16)(udp_hdr(skb)->check);
2179         } else
2180                 fcb->phcs = (__force __be16)(tcp_hdr(skb)->check);
2181
2182         /* l3os is the distance between the start of the
2183          * frame (skb->data) and the start of the IP hdr.
2184          * l4os is the distance between the start of the
2185          * l3 hdr and the l4 hdr
2186          */
2187         fcb->l3os = (u8)(skb_network_offset(skb) - fcb_length);
2188         fcb->l4os = skb_network_header_len(skb);
2189
2190         fcb->flags = flags;
2191 }
2192
2193 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2194 {
2195         fcb->flags |= TXFCB_VLN;
2196         fcb->vlctl = cpu_to_be16(skb_vlan_tag_get(skb));
2197 }
2198
2199 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2200                                       struct txbd8 *base, int ring_size)
2201 {
2202         struct txbd8 *new_bd = bdp + stride;
2203
2204         return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2205 }
2206
2207 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2208                                       int ring_size)
2209 {
2210         return skip_txbd(bdp, 1, base, ring_size);
2211 }
2212
2213 /* eTSEC12: csum generation not supported for some fcb offsets */
2214 static inline bool gfar_csum_errata_12(struct gfar_private *priv,
2215                                        unsigned long fcb_addr)
2216 {
2217         return (gfar_has_errata(priv, GFAR_ERRATA_12) &&
2218                (fcb_addr % 0x20) > 0x18);
2219 }
2220
2221 /* eTSEC76: csum generation for frames larger than 2500 may
2222  * cause excess delays before start of transmission
2223  */
2224 static inline bool gfar_csum_errata_76(struct gfar_private *priv,
2225                                        unsigned int len)
2226 {
2227         return (gfar_has_errata(priv, GFAR_ERRATA_76) &&
2228                (len > 2500));
2229 }
2230
2231 /* This is called by the kernel when a frame is ready for transmission.
2232  * It is pointed to by the dev->hard_start_xmit function pointer
2233  */
2234 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2235 {
2236         struct gfar_private *priv = netdev_priv(dev);
2237         struct gfar_priv_tx_q *tx_queue = NULL;
2238         struct netdev_queue *txq;
2239         struct gfar __iomem *regs = NULL;
2240         struct txfcb *fcb = NULL;
2241         struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2242         u32 lstatus;
2243         int i, rq = 0;
2244         int do_tstamp, do_csum, do_vlan;
2245         u32 bufaddr;
2246         unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0;
2247
2248         rq = skb->queue_mapping;
2249         tx_queue = priv->tx_queue[rq];
2250         txq = netdev_get_tx_queue(dev, rq);
2251         base = tx_queue->tx_bd_base;
2252         regs = tx_queue->grp->regs;
2253
2254         do_csum = (CHECKSUM_PARTIAL == skb->ip_summed);
2255         do_vlan = skb_vlan_tag_present(skb);
2256         do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2257                     priv->hwts_tx_en;
2258
2259         if (do_csum || do_vlan)
2260                 fcb_len = GMAC_FCB_LEN;
2261
2262         /* check if time stamp should be generated */
2263         if (unlikely(do_tstamp))
2264                 fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2265
2266         /* make space for additional header when fcb is needed */
2267         if (fcb_len && unlikely(skb_headroom(skb) < fcb_len)) {
2268                 struct sk_buff *skb_new;
2269
2270                 skb_new = skb_realloc_headroom(skb, fcb_len);
2271                 if (!skb_new) {
2272                         dev->stats.tx_errors++;
2273                         dev_kfree_skb_any(skb);
2274                         return NETDEV_TX_OK;
2275                 }
2276
2277                 if (skb->sk)
2278                         skb_set_owner_w(skb_new, skb->sk);
2279                 dev_consume_skb_any(skb);
2280                 skb = skb_new;
2281         }
2282
2283         /* total number of fragments in the SKB */
2284         nr_frags = skb_shinfo(skb)->nr_frags;
2285
2286         /* calculate the required number of TxBDs for this skb */
2287         if (unlikely(do_tstamp))
2288                 nr_txbds = nr_frags + 2;
2289         else
2290                 nr_txbds = nr_frags + 1;
2291
2292         /* check if there is space to queue this packet */
2293         if (nr_txbds > tx_queue->num_txbdfree) {
2294                 /* no space, stop the queue */
2295                 netif_tx_stop_queue(txq);
2296                 dev->stats.tx_fifo_errors++;
2297                 return NETDEV_TX_BUSY;
2298         }
2299
2300         /* Update transmit stats */
2301         bytes_sent = skb->len;
2302         tx_queue->stats.tx_bytes += bytes_sent;
2303         /* keep Tx bytes on wire for BQL accounting */
2304         GFAR_CB(skb)->bytes_sent = bytes_sent;
2305         tx_queue->stats.tx_packets++;
2306
2307         txbdp = txbdp_start = tx_queue->cur_tx;
2308         lstatus = be32_to_cpu(txbdp->lstatus);
2309
2310         /* Time stamp insertion requires one additional TxBD */
2311         if (unlikely(do_tstamp))
2312                 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2313                                                  tx_queue->tx_ring_size);
2314
2315         if (nr_frags == 0) {
2316                 if (unlikely(do_tstamp)) {
2317                         u32 lstatus_ts = be32_to_cpu(txbdp_tstamp->lstatus);
2318
2319                         lstatus_ts |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2320                         txbdp_tstamp->lstatus = cpu_to_be32(lstatus_ts);
2321                 } else {
2322                         lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2323                 }
2324         } else {
2325                 /* Place the fragment addresses and lengths into the TxBDs */
2326                 for (i = 0; i < nr_frags; i++) {
2327                         unsigned int frag_len;
2328                         /* Point at the next BD, wrapping as needed */
2329                         txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2330
2331                         frag_len = skb_shinfo(skb)->frags[i].size;
2332
2333                         lstatus = be32_to_cpu(txbdp->lstatus) | frag_len |
2334                                   BD_LFLAG(TXBD_READY);
2335
2336                         /* Handle the last BD specially */
2337                         if (i == nr_frags - 1)
2338                                 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2339
2340                         bufaddr = skb_frag_dma_map(priv->dev,
2341                                                    &skb_shinfo(skb)->frags[i],
2342                                                    0,
2343                                                    frag_len,
2344                                                    DMA_TO_DEVICE);
2345                         if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
2346                                 goto dma_map_err;
2347
2348                         /* set the TxBD length and buffer pointer */
2349                         txbdp->bufPtr = cpu_to_be32(bufaddr);
2350                         txbdp->lstatus = cpu_to_be32(lstatus);
2351                 }
2352
2353                 lstatus = be32_to_cpu(txbdp_start->lstatus);
2354         }
2355
2356         /* Add TxPAL between FCB and frame if required */
2357         if (unlikely(do_tstamp)) {
2358                 skb_push(skb, GMAC_TXPAL_LEN);
2359                 memset(skb->data, 0, GMAC_TXPAL_LEN);
2360         }
2361
2362         /* Add TxFCB if required */
2363         if (fcb_len) {
2364                 fcb = gfar_add_fcb(skb);
2365                 lstatus |= BD_LFLAG(TXBD_TOE);
2366         }
2367
2368         /* Set up checksumming */
2369         if (do_csum) {
2370                 gfar_tx_checksum(skb, fcb, fcb_len);
2371
2372                 if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) ||
2373                     unlikely(gfar_csum_errata_76(priv, skb->len))) {
2374                         __skb_pull(skb, GMAC_FCB_LEN);
2375                         skb_checksum_help(skb);
2376                         if (do_vlan || do_tstamp) {
2377                                 /* put back a new fcb for vlan/tstamp TOE */
2378                                 fcb = gfar_add_fcb(skb);
2379                         } else {
2380                                 /* Tx TOE not used */
2381                                 lstatus &= ~(BD_LFLAG(TXBD_TOE));
2382                                 fcb = NULL;
2383                         }
2384                 }
2385         }
2386
2387         if (do_vlan)
2388                 gfar_tx_vlan(skb, fcb);
2389
2390         /* Setup tx hardware time stamping if requested */
2391         if (unlikely(do_tstamp)) {
2392                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2393                 fcb->ptp = 1;
2394         }
2395
2396         bufaddr = dma_map_single(priv->dev, skb->data, skb_headlen(skb),
2397                                  DMA_TO_DEVICE);
2398         if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
2399                 goto dma_map_err;
2400
2401         txbdp_start->bufPtr = cpu_to_be32(bufaddr);
2402
2403         /* If time stamping is requested one additional TxBD must be set up. The
2404          * first TxBD points to the FCB and must have a data length of
2405          * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2406          * the full frame length.
2407          */
2408         if (unlikely(do_tstamp)) {
2409                 u32 lstatus_ts = be32_to_cpu(txbdp_tstamp->lstatus);
2410
2411                 bufaddr = be32_to_cpu(txbdp_start->bufPtr);
2412                 bufaddr += fcb_len;
2413                 lstatus_ts |= BD_LFLAG(TXBD_READY) |
2414                               (skb_headlen(skb) - fcb_len);
2415
2416                 txbdp_tstamp->bufPtr = cpu_to_be32(bufaddr);
2417                 txbdp_tstamp->lstatus = cpu_to_be32(lstatus_ts);
2418                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2419         } else {
2420                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2421         }
2422
2423         netdev_tx_sent_queue(txq, bytes_sent);
2424
2425         gfar_wmb();
2426
2427         txbdp_start->lstatus = cpu_to_be32(lstatus);
2428
2429         gfar_wmb(); /* force lstatus write before tx_skbuff */
2430
2431         tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2432
2433         /* Update the current skb pointer to the next entry we will use
2434          * (wrapping if necessary)
2435          */
2436         tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2437                               TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2438
2439         tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2440
2441         /* We can work in parallel with gfar_clean_tx_ring(), except
2442          * when modifying num_txbdfree. Note that we didn't grab the lock
2443          * when we were reading the num_txbdfree and checking for available
2444          * space, that's because outside of this function it can only grow.
2445          */
2446         spin_lock_bh(&tx_queue->txlock);
2447         /* reduce TxBD free count */
2448         tx_queue->num_txbdfree -= (nr_txbds);
2449         spin_unlock_bh(&tx_queue->txlock);
2450
2451         /* If the next BD still needs to be cleaned up, then the bds
2452          * are full.  We need to tell the kernel to stop sending us stuff.
2453          */
2454         if (!tx_queue->num_txbdfree) {
2455                 netif_tx_stop_queue(txq);
2456
2457                 dev->stats.tx_fifo_errors++;
2458         }
2459
2460         /* Tell the DMA to go go go */
2461         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2462
2463         return NETDEV_TX_OK;
2464
2465 dma_map_err:
2466         txbdp = next_txbd(txbdp_start, base, tx_queue->tx_ring_size);
2467         if (do_tstamp)
2468                 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2469         for (i = 0; i < nr_frags; i++) {
2470                 lstatus = be32_to_cpu(txbdp->lstatus);
2471                 if (!(lstatus & BD_LFLAG(TXBD_READY)))
2472                         break;
2473
2474                 lstatus &= ~BD_LFLAG(TXBD_READY);
2475                 txbdp->lstatus = cpu_to_be32(lstatus);
2476                 bufaddr = be32_to_cpu(txbdp->bufPtr);
2477                 dma_unmap_page(priv->dev, bufaddr, be16_to_cpu(txbdp->length),
2478                                DMA_TO_DEVICE);
2479                 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2480         }
2481         gfar_wmb();
2482         dev_kfree_skb_any(skb);
2483         return NETDEV_TX_OK;
2484 }
2485
2486 /* Stops the kernel queue, and halts the controller */
2487 static int gfar_close(struct net_device *dev)
2488 {
2489         struct gfar_private *priv = netdev_priv(dev);
2490
2491         cancel_work_sync(&priv->reset_task);
2492         stop_gfar(dev);
2493
2494         /* Disconnect from the PHY */
2495         phy_disconnect(priv->phydev);
2496         priv->phydev = NULL;
2497
2498         gfar_free_irq(priv);
2499
2500         return 0;
2501 }
2502
2503 /* Changes the mac address if the controller is not running. */
2504 static int gfar_set_mac_address(struct net_device *dev)
2505 {
2506         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2507
2508         return 0;
2509 }
2510
2511 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2512 {
2513         struct gfar_private *priv = netdev_priv(dev);
2514         int frame_size = new_mtu + ETH_HLEN;
2515
2516         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
2517                 netif_err(priv, drv, dev, "Invalid MTU setting\n");
2518                 return -EINVAL;
2519         }
2520
2521         while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2522                 cpu_relax();
2523
2524         if (dev->flags & IFF_UP)
2525                 stop_gfar(dev);
2526
2527         dev->mtu = new_mtu;
2528
2529         if (dev->flags & IFF_UP)
2530                 startup_gfar(dev);
2531
2532         clear_bit_unlock(GFAR_RESETTING, &priv->state);
2533
2534         return 0;
2535 }
2536
2537 void reset_gfar(struct net_device *ndev)
2538 {
2539         struct gfar_private *priv = netdev_priv(ndev);
2540
2541         while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2542                 cpu_relax();
2543
2544         stop_gfar(ndev);
2545         startup_gfar(ndev);
2546
2547         clear_bit_unlock(GFAR_RESETTING, &priv->state);
2548 }
2549
2550 /* gfar_reset_task gets scheduled when a packet has not been
2551  * transmitted after a set amount of time.
2552  * For now, assume that clearing out all the structures, and
2553  * starting over will fix the problem.
2554  */
2555 static void gfar_reset_task(struct work_struct *work)
2556 {
2557         struct gfar_private *priv = container_of(work, struct gfar_private,
2558                                                  reset_task);
2559         reset_gfar(priv->ndev);
2560 }
2561
2562 static void gfar_timeout(struct net_device *dev)
2563 {
2564         struct gfar_private *priv = netdev_priv(dev);
2565
2566         dev->stats.tx_errors++;
2567         schedule_work(&priv->reset_task);
2568 }
2569
2570 static void gfar_align_skb(struct sk_buff *skb)
2571 {
2572         /* We need the data buffer to be aligned properly.  We will reserve
2573          * as many bytes as needed to align the data properly
2574          */
2575         skb_reserve(skb, RXBUF_ALIGNMENT -
2576                     (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
2577 }
2578
2579 /* Interrupt Handler for Transmit complete */
2580 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2581 {
2582         struct net_device *dev = tx_queue->dev;
2583         struct netdev_queue *txq;
2584         struct gfar_private *priv = netdev_priv(dev);
2585         struct txbd8 *bdp, *next = NULL;
2586         struct txbd8 *lbdp = NULL;
2587         struct txbd8 *base = tx_queue->tx_bd_base;
2588         struct sk_buff *skb;
2589         int skb_dirtytx;
2590         int tx_ring_size = tx_queue->tx_ring_size;
2591         int frags = 0, nr_txbds = 0;
2592         int i;
2593         int howmany = 0;
2594         int tqi = tx_queue->qindex;
2595         unsigned int bytes_sent = 0;
2596         u32 lstatus;
2597         size_t buflen;
2598
2599         txq = netdev_get_tx_queue(dev, tqi);
2600         bdp = tx_queue->dirty_tx;
2601         skb_dirtytx = tx_queue->skb_dirtytx;
2602
2603         while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2604
2605                 frags = skb_shinfo(skb)->nr_frags;
2606
2607                 /* When time stamping, one additional TxBD must be freed.
2608                  * Also, we need to dma_unmap_single() the TxPAL.
2609                  */
2610                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2611                         nr_txbds = frags + 2;
2612                 else
2613                         nr_txbds = frags + 1;
2614
2615                 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2616
2617                 lstatus = be32_to_cpu(lbdp->lstatus);
2618
2619                 /* Only clean completed frames */
2620                 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2621                     (lstatus & BD_LENGTH_MASK))
2622                         break;
2623
2624                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2625                         next = next_txbd(bdp, base, tx_ring_size);
2626                         buflen = be16_to_cpu(next->length) +
2627                                  GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2628                 } else
2629                         buflen = be16_to_cpu(bdp->length);
2630
2631                 dma_unmap_single(priv->dev, be32_to_cpu(bdp->bufPtr),
2632                                  buflen, DMA_TO_DEVICE);
2633
2634                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2635                         struct skb_shared_hwtstamps shhwtstamps;
2636                         u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
2637
2638                         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2639                         shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2640                         skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2641                         skb_tstamp_tx(skb, &shhwtstamps);
2642                         gfar_clear_txbd_status(bdp);
2643                         bdp = next;
2644                 }
2645
2646                 gfar_clear_txbd_status(bdp);
2647                 bdp = next_txbd(bdp, base, tx_ring_size);
2648
2649                 for (i = 0; i < frags; i++) {
2650                         dma_unmap_page(priv->dev, be32_to_cpu(bdp->bufPtr),
2651                                        be16_to_cpu(bdp->length),
2652                                        DMA_TO_DEVICE);
2653                         gfar_clear_txbd_status(bdp);
2654                         bdp = next_txbd(bdp, base, tx_ring_size);
2655                 }
2656
2657                 bytes_sent += GFAR_CB(skb)->bytes_sent;
2658
2659                 dev_kfree_skb_any(skb);
2660
2661                 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2662
2663                 skb_dirtytx = (skb_dirtytx + 1) &
2664                               TX_RING_MOD_MASK(tx_ring_size);
2665
2666                 howmany++;
2667                 spin_lock(&tx_queue->txlock);
2668                 tx_queue->num_txbdfree += nr_txbds;
2669                 spin_unlock(&tx_queue->txlock);
2670         }
2671
2672         /* If we freed a buffer, we can restart transmission, if necessary */
2673         if (tx_queue->num_txbdfree &&
2674             netif_tx_queue_stopped(txq) &&
2675             !(test_bit(GFAR_DOWN, &priv->state)))
2676                 netif_wake_subqueue(priv->ndev, tqi);
2677
2678         /* Update dirty indicators */
2679         tx_queue->skb_dirtytx = skb_dirtytx;
2680         tx_queue->dirty_tx = bdp;
2681
2682         netdev_tx_completed_queue(txq, howmany, bytes_sent);
2683 }
2684
2685 static struct sk_buff *gfar_new_skb(struct net_device *ndev,
2686                                     dma_addr_t *bufaddr)
2687 {
2688         struct gfar_private *priv = netdev_priv(ndev);
2689         struct sk_buff *skb;
2690         dma_addr_t addr;
2691
2692         skb = netdev_alloc_skb(ndev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
2693         if (!skb)
2694                 return NULL;
2695
2696         gfar_align_skb(skb);
2697
2698         addr = dma_map_single(priv->dev, skb->data,
2699                               priv->rx_buffer_size, DMA_FROM_DEVICE);
2700         if (unlikely(dma_mapping_error(priv->dev, addr))) {
2701                 dev_kfree_skb_any(skb);
2702                 return NULL;
2703         }
2704
2705         *bufaddr = addr;
2706         return skb;
2707 }
2708
2709 static void gfar_rx_alloc_err(struct gfar_priv_rx_q *rx_queue)
2710 {
2711         struct gfar_private *priv = netdev_priv(rx_queue->ndev);
2712         struct gfar_extra_stats *estats = &priv->extra_stats;
2713
2714         netdev_err(rx_queue->ndev, "Can't alloc RX buffers\n");
2715         atomic64_inc(&estats->rx_alloc_err);
2716 }
2717
2718 static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue,
2719                                 int alloc_cnt)
2720 {
2721         struct net_device *ndev = rx_queue->ndev;
2722         struct rxbd8 *bdp, *base;
2723         dma_addr_t bufaddr;
2724         int i;
2725
2726         i = rx_queue->next_to_use;
2727         base = rx_queue->rx_bd_base;
2728         bdp = &rx_queue->rx_bd_base[i];
2729
2730         while (alloc_cnt--) {
2731                 struct sk_buff *skb = rx_queue->rx_skbuff[i];
2732
2733                 if (likely(!skb)) {
2734                         skb = gfar_new_skb(ndev, &bufaddr);
2735                         if (unlikely(!skb)) {
2736                                 gfar_rx_alloc_err(rx_queue);
2737                                 break;
2738                         }
2739                 } else { /* restore from sleep state */
2740                         bufaddr = be32_to_cpu(bdp->bufPtr);
2741                 }
2742
2743                 rx_queue->rx_skbuff[i] = skb;
2744
2745                 /* Setup the new RxBD */
2746                 gfar_init_rxbdp(rx_queue, bdp, bufaddr);
2747
2748                 /* Update to the next pointer */
2749                 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
2750
2751                 if (unlikely(++i == rx_queue->rx_ring_size))
2752                         i = 0;
2753         }
2754
2755         rx_queue->next_to_use = i;
2756 }
2757
2758 static void count_errors(u32 lstatus, struct net_device *ndev)
2759 {
2760         struct gfar_private *priv = netdev_priv(ndev);
2761         struct net_device_stats *stats = &ndev->stats;
2762         struct gfar_extra_stats *estats = &priv->extra_stats;
2763
2764         /* If the packet was truncated, none of the other errors matter */
2765         if (lstatus & BD_LFLAG(RXBD_TRUNCATED)) {
2766                 stats->rx_length_errors++;
2767
2768                 atomic64_inc(&estats->rx_trunc);
2769
2770                 return;
2771         }
2772         /* Count the errors, if there were any */
2773         if (lstatus & BD_LFLAG(RXBD_LARGE | RXBD_SHORT)) {
2774                 stats->rx_length_errors++;
2775
2776                 if (lstatus & BD_LFLAG(RXBD_LARGE))
2777                         atomic64_inc(&estats->rx_large);
2778                 else
2779                         atomic64_inc(&estats->rx_short);
2780         }
2781         if (lstatus & BD_LFLAG(RXBD_NONOCTET)) {
2782                 stats->rx_frame_errors++;
2783                 atomic64_inc(&estats->rx_nonoctet);
2784         }
2785         if (lstatus & BD_LFLAG(RXBD_CRCERR)) {
2786                 atomic64_inc(&estats->rx_crcerr);
2787                 stats->rx_crc_errors++;
2788         }
2789         if (lstatus & BD_LFLAG(RXBD_OVERRUN)) {
2790                 atomic64_inc(&estats->rx_overrun);
2791                 stats->rx_over_errors++;
2792         }
2793 }
2794
2795 irqreturn_t gfar_receive(int irq, void *grp_id)
2796 {
2797         struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2798         unsigned long flags;
2799         u32 imask;
2800
2801         if (likely(napi_schedule_prep(&grp->napi_rx))) {
2802                 spin_lock_irqsave(&grp->grplock, flags);
2803                 imask = gfar_read(&grp->regs->imask);
2804                 imask &= IMASK_RX_DISABLED;
2805                 gfar_write(&grp->regs->imask, imask);
2806                 spin_unlock_irqrestore(&grp->grplock, flags);
2807                 __napi_schedule(&grp->napi_rx);
2808         } else {
2809                 /* Clear IEVENT, so interrupts aren't called again
2810                  * because of the packets that have already arrived.
2811                  */
2812                 gfar_write(&grp->regs->ievent, IEVENT_RX_MASK);
2813         }
2814
2815         return IRQ_HANDLED;
2816 }
2817
2818 /* Interrupt Handler for Transmit complete */
2819 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2820 {
2821         struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2822         unsigned long flags;
2823         u32 imask;
2824
2825         if (likely(napi_schedule_prep(&grp->napi_tx))) {
2826                 spin_lock_irqsave(&grp->grplock, flags);
2827                 imask = gfar_read(&grp->regs->imask);
2828                 imask &= IMASK_TX_DISABLED;
2829                 gfar_write(&grp->regs->imask, imask);
2830                 spin_unlock_irqrestore(&grp->grplock, flags);
2831                 __napi_schedule(&grp->napi_tx);
2832         } else {
2833                 /* Clear IEVENT, so interrupts aren't called again
2834                  * because of the packets that have already arrived.
2835                  */
2836                 gfar_write(&grp->regs->ievent, IEVENT_TX_MASK);
2837         }
2838
2839         return IRQ_HANDLED;
2840 }
2841
2842 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2843 {
2844         /* If valid headers were found, and valid sums
2845          * were verified, then we tell the kernel that no
2846          * checksumming is necessary.  Otherwise, it is [FIXME]
2847          */
2848         if ((be16_to_cpu(fcb->flags) & RXFCB_CSUM_MASK) ==
2849             (RXFCB_CIP | RXFCB_CTU))
2850                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2851         else
2852                 skb_checksum_none_assert(skb);
2853 }
2854
2855 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
2856 static void gfar_process_frame(struct net_device *ndev, struct sk_buff *skb)
2857 {
2858         struct gfar_private *priv = netdev_priv(ndev);
2859         struct rxfcb *fcb = NULL;
2860
2861         /* fcb is at the beginning if exists */
2862         fcb = (struct rxfcb *)skb->data;
2863
2864         /* Remove the FCB from the skb
2865          * Remove the padded bytes, if there are any
2866          */
2867         if (priv->uses_rxfcb)
2868                 skb_pull(skb, GMAC_FCB_LEN);
2869
2870         /* Get receive timestamp from the skb */
2871         if (priv->hwts_rx_en) {
2872                 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2873                 u64 *ns = (u64 *) skb->data;
2874
2875                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2876                 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2877         }
2878
2879         if (priv->padding)
2880                 skb_pull(skb, priv->padding);
2881
2882         if (ndev->features & NETIF_F_RXCSUM)
2883                 gfar_rx_checksum(skb, fcb);
2884
2885         /* Tell the skb what kind of packet this is */
2886         skb->protocol = eth_type_trans(skb, ndev);
2887
2888         /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here.
2889          * Even if vlan rx accel is disabled, on some chips
2890          * RXFCB_VLN is pseudo randomly set.
2891          */
2892         if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX &&
2893             be16_to_cpu(fcb->flags) & RXFCB_VLN)
2894                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2895                                        be16_to_cpu(fcb->vlctl));
2896 }
2897
2898 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2899  * until the budget/quota has been reached. Returns the number
2900  * of frames handled
2901  */
2902 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
2903 {
2904         struct net_device *ndev = rx_queue->ndev;
2905         struct rxbd8 *bdp, *base;
2906         struct sk_buff *skb;
2907         int i, howmany = 0;
2908         int cleaned_cnt = gfar_rxbd_unused(rx_queue);
2909         struct gfar_private *priv = netdev_priv(ndev);
2910
2911         /* Get the first full descriptor */
2912         base = rx_queue->rx_bd_base;
2913         i = rx_queue->next_to_clean;
2914
2915         while (rx_work_limit--) {
2916                 u32 lstatus;
2917
2918                 if (cleaned_cnt >= GFAR_RX_BUFF_ALLOC) {
2919                         gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
2920                         cleaned_cnt = 0;
2921                 }
2922
2923                 bdp = &rx_queue->rx_bd_base[i];
2924                 lstatus = be32_to_cpu(bdp->lstatus);
2925                 if (lstatus & BD_LFLAG(RXBD_EMPTY))
2926                         break;
2927
2928                 /* order rx buffer descriptor reads */
2929                 rmb();
2930
2931                 /* fetch next to clean buffer from the ring */
2932                 skb = rx_queue->rx_skbuff[i];
2933
2934                 dma_unmap_single(priv->dev, be32_to_cpu(bdp->bufPtr),
2935                                  priv->rx_buffer_size, DMA_FROM_DEVICE);
2936
2937                 if (unlikely(!(lstatus & BD_LFLAG(RXBD_ERR)) &&
2938                              (lstatus & BD_LENGTH_MASK) > priv->rx_buffer_size))
2939                         lstatus |= BD_LFLAG(RXBD_LARGE);
2940
2941                 if (unlikely(!(lstatus & BD_LFLAG(RXBD_LAST)) ||
2942                              (lstatus & BD_LFLAG(RXBD_ERR)))) {
2943                         count_errors(lstatus, ndev);
2944
2945                         /* discard faulty buffer */
2946                         dev_kfree_skb(skb);
2947
2948                 } else {
2949                         /* Increment the number of packets */
2950                         rx_queue->stats.rx_packets++;
2951                         howmany++;
2952
2953                         if (likely(skb)) {
2954                                 int pkt_len = (lstatus & BD_LENGTH_MASK) -
2955                                           ETH_FCS_LEN;
2956                                 /* Remove the FCS from the packet length */
2957                                 skb_put(skb, pkt_len);
2958                                 rx_queue->stats.rx_bytes += pkt_len;
2959                                 skb_record_rx_queue(skb, rx_queue->qindex);
2960                                 gfar_process_frame(ndev, skb);
2961
2962                                 /* Send the packet up the stack */
2963                                 napi_gro_receive(&rx_queue->grp->napi_rx, skb);
2964
2965                         } else {
2966                                 netif_warn(priv, rx_err, ndev, "Missing skb!\n");
2967                                 rx_queue->stats.rx_dropped++;
2968                                 atomic64_inc(&priv->extra_stats.rx_skbmissing);
2969                         }
2970
2971                 }
2972
2973                 rx_queue->rx_skbuff[i] = NULL;
2974                 cleaned_cnt++;
2975                 if (unlikely(++i == rx_queue->rx_ring_size))
2976                         i = 0;
2977         }
2978
2979         rx_queue->next_to_clean = i;
2980
2981         if (cleaned_cnt)
2982                 gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
2983
2984         /* Update Last Free RxBD pointer for LFC */
2985         if (unlikely(priv->tx_actual_en)) {
2986                 bdp = gfar_rxbd_lastfree(rx_queue);
2987                 gfar_write(rx_queue->rfbptr, (u32)bdp);
2988         }
2989
2990         return howmany;
2991 }
2992
2993 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget)
2994 {
2995         struct gfar_priv_grp *gfargrp =
2996                 container_of(napi, struct gfar_priv_grp, napi_rx);
2997         struct gfar __iomem *regs = gfargrp->regs;
2998         struct gfar_priv_rx_q *rx_queue = gfargrp->rx_queue;
2999         int work_done = 0;
3000
3001         /* Clear IEVENT, so interrupts aren't called again
3002          * because of the packets that have already arrived
3003          */
3004         gfar_write(&regs->ievent, IEVENT_RX_MASK);
3005
3006         work_done = gfar_clean_rx_ring(rx_queue, budget);
3007
3008         if (work_done < budget) {
3009                 u32 imask;
3010                 napi_complete(napi);
3011                 /* Clear the halt bit in RSTAT */
3012                 gfar_write(&regs->rstat, gfargrp->rstat);
3013
3014                 spin_lock_irq(&gfargrp->grplock);
3015                 imask = gfar_read(&regs->imask);
3016                 imask |= IMASK_RX_DEFAULT;
3017                 gfar_write(&regs->imask, imask);
3018                 spin_unlock_irq(&gfargrp->grplock);
3019         }
3020
3021         return work_done;
3022 }
3023
3024 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget)
3025 {
3026         struct gfar_priv_grp *gfargrp =
3027                 container_of(napi, struct gfar_priv_grp, napi_tx);
3028         struct gfar __iomem *regs = gfargrp->regs;
3029         struct gfar_priv_tx_q *tx_queue = gfargrp->tx_queue;
3030         u32 imask;
3031
3032         /* Clear IEVENT, so interrupts aren't called again
3033          * because of the packets that have already arrived
3034          */
3035         gfar_write(&regs->ievent, IEVENT_TX_MASK);
3036
3037         /* run Tx cleanup to completion */
3038         if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx])
3039                 gfar_clean_tx_ring(tx_queue);
3040
3041         napi_complete(napi);
3042
3043         spin_lock_irq(&gfargrp->grplock);
3044         imask = gfar_read(&regs->imask);
3045         imask |= IMASK_TX_DEFAULT;
3046         gfar_write(&regs->imask, imask);
3047         spin_unlock_irq(&gfargrp->grplock);
3048
3049         return 0;
3050 }
3051
3052 static int gfar_poll_rx(struct napi_struct *napi, int budget)
3053 {
3054         struct gfar_priv_grp *gfargrp =
3055                 container_of(napi, struct gfar_priv_grp, napi_rx);
3056         struct gfar_private *priv = gfargrp->priv;
3057         struct gfar __iomem *regs = gfargrp->regs;
3058         struct gfar_priv_rx_q *rx_queue = NULL;
3059         int work_done = 0, work_done_per_q = 0;
3060         int i, budget_per_q = 0;
3061         unsigned long rstat_rxf;
3062         int num_act_queues;
3063
3064         /* Clear IEVENT, so interrupts aren't called again
3065          * because of the packets that have already arrived
3066          */
3067         gfar_write(&regs->ievent, IEVENT_RX_MASK);
3068
3069         rstat_rxf = gfar_read(&regs->rstat) & RSTAT_RXF_MASK;
3070
3071         num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS);
3072         if (num_act_queues)
3073                 budget_per_q = budget/num_act_queues;
3074
3075         for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
3076                 /* skip queue if not active */
3077                 if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i)))
3078                         continue;
3079
3080                 rx_queue = priv->rx_queue[i];
3081                 work_done_per_q =
3082                         gfar_clean_rx_ring(rx_queue, budget_per_q);
3083                 work_done += work_done_per_q;
3084
3085                 /* finished processing this queue */
3086                 if (work_done_per_q < budget_per_q) {
3087                         /* clear active queue hw indication */
3088                         gfar_write(&regs->rstat,
3089                                    RSTAT_CLEAR_RXF0 >> i);
3090                         num_act_queues--;
3091
3092                         if (!num_act_queues)
3093                                 break;
3094                 }
3095         }
3096
3097         if (!num_act_queues) {
3098                 u32 imask;
3099                 napi_complete(napi);
3100
3101                 /* Clear the halt bit in RSTAT */
3102                 gfar_write(&regs->rstat, gfargrp->rstat);
3103
3104                 spin_lock_irq(&gfargrp->grplock);
3105                 imask = gfar_read(&regs->imask);
3106                 imask |= IMASK_RX_DEFAULT;
3107                 gfar_write(&regs->imask, imask);
3108                 spin_unlock_irq(&gfargrp->grplock);
3109         }
3110
3111         return work_done;
3112 }
3113
3114 static int gfar_poll_tx(struct napi_struct *napi, int budget)
3115 {
3116         struct gfar_priv_grp *gfargrp =
3117                 container_of(napi, struct gfar_priv_grp, napi_tx);
3118         struct gfar_private *priv = gfargrp->priv;
3119         struct gfar __iomem *regs = gfargrp->regs;
3120         struct gfar_priv_tx_q *tx_queue = NULL;
3121         int has_tx_work = 0;
3122         int i;
3123
3124         /* Clear IEVENT, so interrupts aren't called again
3125          * because of the packets that have already arrived
3126          */
3127         gfar_write(&regs->ievent, IEVENT_TX_MASK);
3128
3129         for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) {
3130                 tx_queue = priv->tx_queue[i];
3131                 /* run Tx cleanup to completion */
3132                 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) {
3133                         gfar_clean_tx_ring(tx_queue);
3134                         has_tx_work = 1;
3135                 }
3136         }
3137
3138         if (!has_tx_work) {
3139                 u32 imask;
3140                 napi_complete(napi);
3141
3142                 spin_lock_irq(&gfargrp->grplock);
3143                 imask = gfar_read(&regs->imask);
3144                 imask |= IMASK_TX_DEFAULT;
3145                 gfar_write(&regs->imask, imask);
3146                 spin_unlock_irq(&gfargrp->grplock);
3147         }
3148
3149         return 0;
3150 }
3151
3152
3153 #ifdef CONFIG_NET_POLL_CONTROLLER
3154 /* Polling 'interrupt' - used by things like netconsole to send skbs
3155  * without having to re-enable interrupts. It's not called while
3156  * the interrupt routine is executing.
3157  */
3158 static void gfar_netpoll(struct net_device *dev)
3159 {
3160         struct gfar_private *priv = netdev_priv(dev);
3161         int i;
3162
3163         /* If the device has multiple interrupts, run tx/rx */
3164         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
3165                 for (i = 0; i < priv->num_grps; i++) {
3166                         struct gfar_priv_grp *grp = &priv->gfargrp[i];
3167
3168                         disable_irq(gfar_irq(grp, TX)->irq);
3169                         disable_irq(gfar_irq(grp, RX)->irq);
3170                         disable_irq(gfar_irq(grp, ER)->irq);
3171                         gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3172                         enable_irq(gfar_irq(grp, ER)->irq);
3173                         enable_irq(gfar_irq(grp, RX)->irq);
3174                         enable_irq(gfar_irq(grp, TX)->irq);
3175                 }
3176         } else {
3177                 for (i = 0; i < priv->num_grps; i++) {
3178                         struct gfar_priv_grp *grp = &priv->gfargrp[i];
3179
3180                         disable_irq(gfar_irq(grp, TX)->irq);
3181                         gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3182                         enable_irq(gfar_irq(grp, TX)->irq);
3183                 }
3184         }
3185 }
3186 #endif
3187
3188 /* The interrupt handler for devices with one interrupt */
3189 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
3190 {
3191         struct gfar_priv_grp *gfargrp = grp_id;
3192
3193         /* Save ievent for future reference */
3194         u32 events = gfar_read(&gfargrp->regs->ievent);
3195
3196         /* Check for reception */
3197         if (events & IEVENT_RX_MASK)
3198                 gfar_receive(irq, grp_id);
3199
3200         /* Check for transmit completion */
3201         if (events & IEVENT_TX_MASK)
3202                 gfar_transmit(irq, grp_id);
3203
3204         /* Check for errors */
3205         if (events & IEVENT_ERR_MASK)
3206                 gfar_error(irq, grp_id);
3207
3208         return IRQ_HANDLED;
3209 }
3210
3211 /* Called every time the controller might need to be made
3212  * aware of new link state.  The PHY code conveys this
3213  * information through variables in the phydev structure, and this
3214  * function converts those variables into the appropriate
3215  * register values, and can bring down the device if needed.
3216  */
3217 static void adjust_link(struct net_device *dev)
3218 {
3219         struct gfar_private *priv = netdev_priv(dev);
3220         struct phy_device *phydev = priv->phydev;
3221
3222         if (unlikely(phydev->link != priv->oldlink ||
3223                      (phydev->link && (phydev->duplex != priv->oldduplex ||
3224                                        phydev->speed != priv->oldspeed))))
3225                 gfar_update_link_state(priv);
3226 }
3227
3228 /* Update the hash table based on the current list of multicast
3229  * addresses we subscribe to.  Also, change the promiscuity of
3230  * the device based on the flags (this function is called
3231  * whenever dev->flags is changed
3232  */
3233 static void gfar_set_multi(struct net_device *dev)
3234 {
3235         struct netdev_hw_addr *ha;
3236         struct gfar_private *priv = netdev_priv(dev);
3237         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3238         u32 tempval;
3239
3240         if (dev->flags & IFF_PROMISC) {
3241                 /* Set RCTRL to PROM */
3242                 tempval = gfar_read(&regs->rctrl);
3243                 tempval |= RCTRL_PROM;
3244                 gfar_write(&regs->rctrl, tempval);
3245         } else {
3246                 /* Set RCTRL to not PROM */
3247                 tempval = gfar_read(&regs->rctrl);
3248                 tempval &= ~(RCTRL_PROM);
3249                 gfar_write(&regs->rctrl, tempval);
3250         }
3251
3252         if (dev->flags & IFF_ALLMULTI) {
3253                 /* Set the hash to rx all multicast frames */
3254                 gfar_write(&regs->igaddr0, 0xffffffff);
3255                 gfar_write(&regs->igaddr1, 0xffffffff);
3256                 gfar_write(&regs->igaddr2, 0xffffffff);
3257                 gfar_write(&regs->igaddr3, 0xffffffff);
3258                 gfar_write(&regs->igaddr4, 0xffffffff);
3259                 gfar_write(&regs->igaddr5, 0xffffffff);
3260                 gfar_write(&regs->igaddr6, 0xffffffff);
3261                 gfar_write(&regs->igaddr7, 0xffffffff);
3262                 gfar_write(&regs->gaddr0, 0xffffffff);
3263                 gfar_write(&regs->gaddr1, 0xffffffff);
3264                 gfar_write(&regs->gaddr2, 0xffffffff);
3265                 gfar_write(&regs->gaddr3, 0xffffffff);
3266                 gfar_write(&regs->gaddr4, 0xffffffff);
3267                 gfar_write(&regs->gaddr5, 0xffffffff);
3268                 gfar_write(&regs->gaddr6, 0xffffffff);
3269                 gfar_write(&regs->gaddr7, 0xffffffff);
3270         } else {
3271                 int em_num;
3272                 int idx;
3273
3274                 /* zero out the hash */
3275                 gfar_write(&regs->igaddr0, 0x0);
3276                 gfar_write(&regs->igaddr1, 0x0);
3277                 gfar_write(&regs->igaddr2, 0x0);
3278                 gfar_write(&regs->igaddr3, 0x0);
3279                 gfar_write(&regs->igaddr4, 0x0);
3280                 gfar_write(&regs->igaddr5, 0x0);
3281                 gfar_write(&regs->igaddr6, 0x0);
3282                 gfar_write(&regs->igaddr7, 0x0);
3283                 gfar_write(&regs->gaddr0, 0x0);
3284                 gfar_write(&regs->gaddr1, 0x0);
3285                 gfar_write(&regs->gaddr2, 0x0);
3286                 gfar_write(&regs->gaddr3, 0x0);
3287                 gfar_write(&regs->gaddr4, 0x0);
3288                 gfar_write(&regs->gaddr5, 0x0);
3289                 gfar_write(&regs->gaddr6, 0x0);
3290                 gfar_write(&regs->gaddr7, 0x0);
3291
3292                 /* If we have extended hash tables, we need to
3293                  * clear the exact match registers to prepare for
3294                  * setting them
3295                  */
3296                 if (priv->extended_hash) {
3297                         em_num = GFAR_EM_NUM + 1;
3298                         gfar_clear_exact_match(dev);
3299                         idx = 1;
3300                 } else {
3301                         idx = 0;
3302                         em_num = 0;
3303                 }
3304
3305                 if (netdev_mc_empty(dev))
3306                         return;
3307
3308                 /* Parse the list, and set the appropriate bits */
3309                 netdev_for_each_mc_addr(ha, dev) {
3310                         if (idx < em_num) {
3311                                 gfar_set_mac_for_addr(dev, idx, ha->addr);
3312                                 idx++;
3313                         } else
3314                                 gfar_set_hash_for_addr(dev, ha->addr);
3315                 }
3316         }
3317 }
3318
3319
3320 /* Clears each of the exact match registers to zero, so they
3321  * don't interfere with normal reception
3322  */
3323 static void gfar_clear_exact_match(struct net_device *dev)
3324 {
3325         int idx;
3326         static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3327
3328         for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3329                 gfar_set_mac_for_addr(dev, idx, zero_arr);
3330 }
3331
3332 /* Set the appropriate hash bit for the given addr */
3333 /* The algorithm works like so:
3334  * 1) Take the Destination Address (ie the multicast address), and
3335  * do a CRC on it (little endian), and reverse the bits of the
3336  * result.
3337  * 2) Use the 8 most significant bits as a hash into a 256-entry
3338  * table.  The table is controlled through 8 32-bit registers:
3339  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
3340  * gaddr7.  This means that the 3 most significant bits in the
3341  * hash index which gaddr register to use, and the 5 other bits
3342  * indicate which bit (assuming an IBM numbering scheme, which
3343  * for PowerPC (tm) is usually the case) in the register holds
3344  * the entry.
3345  */
3346 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3347 {
3348         u32 tempval;
3349         struct gfar_private *priv = netdev_priv(dev);
3350         u32 result = ether_crc(ETH_ALEN, addr);
3351         int width = priv->hash_width;
3352         u8 whichbit = (result >> (32 - width)) & 0x1f;
3353         u8 whichreg = result >> (32 - width + 5);
3354         u32 value = (1 << (31-whichbit));
3355
3356         tempval = gfar_read(priv->hash_regs[whichreg]);
3357         tempval |= value;
3358         gfar_write(priv->hash_regs[whichreg], tempval);
3359 }
3360
3361
3362 /* There are multiple MAC Address register pairs on some controllers
3363  * This function sets the numth pair to a given address
3364  */
3365 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3366                                   const u8 *addr)
3367 {
3368         struct gfar_private *priv = netdev_priv(dev);
3369         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3370         u32 tempval;
3371         u32 __iomem *macptr = &regs->macstnaddr1;
3372
3373         macptr += num*2;
3374
3375         /* For a station address of 0x12345678ABCD in transmission
3376          * order (BE), MACnADDR1 is set to 0xCDAB7856 and
3377          * MACnADDR2 is set to 0x34120000.
3378          */
3379         tempval = (addr[5] << 24) | (addr[4] << 16) |
3380                   (addr[3] << 8)  |  addr[2];
3381
3382         gfar_write(macptr, tempval);
3383
3384         tempval = (addr[1] << 24) | (addr[0] << 16);
3385
3386         gfar_write(macptr+1, tempval);
3387 }
3388
3389 /* GFAR error interrupt handler */
3390 static irqreturn_t gfar_error(int irq, void *grp_id)
3391 {
3392         struct gfar_priv_grp *gfargrp = grp_id;
3393         struct gfar __iomem *regs = gfargrp->regs;
3394         struct gfar_private *priv= gfargrp->priv;
3395         struct net_device *dev = priv->ndev;
3396
3397         /* Save ievent for future reference */
3398         u32 events = gfar_read(&regs->ievent);
3399
3400         /* Clear IEVENT */
3401         gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
3402
3403         /* Magic Packet is not an error. */
3404         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3405             (events & IEVENT_MAG))
3406                 events &= ~IEVENT_MAG;
3407
3408         /* Hmm... */
3409         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3410                 netdev_dbg(dev,
3411                            "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3412                            events, gfar_read(&regs->imask));
3413
3414         /* Update the error counters */
3415         if (events & IEVENT_TXE) {
3416                 dev->stats.tx_errors++;
3417
3418                 if (events & IEVENT_LC)
3419                         dev->stats.tx_window_errors++;
3420                 if (events & IEVENT_CRL)
3421                         dev->stats.tx_aborted_errors++;
3422                 if (events & IEVENT_XFUN) {
3423                         netif_dbg(priv, tx_err, dev,
3424                                   "TX FIFO underrun, packet dropped\n");
3425                         dev->stats.tx_dropped++;
3426                         atomic64_inc(&priv->extra_stats.tx_underrun);
3427
3428                         schedule_work(&priv->reset_task);
3429                 }
3430                 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
3431         }
3432         if (events & IEVENT_BSY) {
3433                 dev->stats.rx_errors++;
3434                 atomic64_inc(&priv->extra_stats.rx_bsy);
3435
3436                 gfar_receive(irq, grp_id);
3437
3438                 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3439                           gfar_read(&regs->rstat));
3440         }
3441         if (events & IEVENT_BABR) {
3442                 dev->stats.rx_errors++;
3443                 atomic64_inc(&priv->extra_stats.rx_babr);
3444
3445                 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
3446         }
3447         if (events & IEVENT_EBERR) {
3448                 atomic64_inc(&priv->extra_stats.eberr);
3449                 netif_dbg(priv, rx_err, dev, "bus error\n");
3450         }
3451         if (events & IEVENT_RXC)
3452                 netif_dbg(priv, rx_status, dev, "control frame\n");
3453
3454         if (events & IEVENT_BABT) {
3455                 atomic64_inc(&priv->extra_stats.tx_babt);
3456                 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3457         }
3458         return IRQ_HANDLED;
3459 }
3460
3461 static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv)
3462 {
3463         struct phy_device *phydev = priv->phydev;
3464         u32 val = 0;
3465
3466         if (!phydev->duplex)
3467                 return val;
3468
3469         if (!priv->pause_aneg_en) {
3470                 if (priv->tx_pause_en)
3471                         val |= MACCFG1_TX_FLOW;
3472                 if (priv->rx_pause_en)
3473                         val |= MACCFG1_RX_FLOW;
3474         } else {
3475                 u16 lcl_adv, rmt_adv;
3476                 u8 flowctrl;
3477                 /* get link partner capabilities */
3478                 rmt_adv = 0;
3479                 if (phydev->pause)
3480                         rmt_adv = LPA_PAUSE_CAP;
3481                 if (phydev->asym_pause)
3482                         rmt_adv |= LPA_PAUSE_ASYM;
3483
3484                 lcl_adv = 0;
3485                 if (phydev->advertising & ADVERTISED_Pause)
3486                         lcl_adv |= ADVERTISE_PAUSE_CAP;
3487                 if (phydev->advertising & ADVERTISED_Asym_Pause)
3488                         lcl_adv |= ADVERTISE_PAUSE_ASYM;
3489
3490                 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
3491                 if (flowctrl & FLOW_CTRL_TX)
3492                         val |= MACCFG1_TX_FLOW;
3493                 if (flowctrl & FLOW_CTRL_RX)
3494                         val |= MACCFG1_RX_FLOW;
3495         }
3496
3497         return val;
3498 }
3499
3500 static noinline void gfar_update_link_state(struct gfar_private *priv)
3501 {
3502         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3503         struct phy_device *phydev = priv->phydev;
3504         struct gfar_priv_rx_q *rx_queue = NULL;
3505         int i;
3506         struct rxbd8 *bdp;
3507
3508         if (unlikely(test_bit(GFAR_RESETTING, &priv->state)))
3509                 return;
3510
3511         if (phydev->link) {
3512                 u32 tempval1 = gfar_read(&regs->maccfg1);
3513                 u32 tempval = gfar_read(&regs->maccfg2);
3514                 u32 ecntrl = gfar_read(&regs->ecntrl);
3515                 u32 tx_flow_oldval = (tempval & MACCFG1_TX_FLOW);
3516
3517                 if (phydev->duplex != priv->oldduplex) {
3518                         if (!(phydev->duplex))
3519                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
3520                         else
3521                                 tempval |= MACCFG2_FULL_DUPLEX;
3522
3523                         priv->oldduplex = phydev->duplex;
3524                 }
3525
3526                 if (phydev->speed != priv->oldspeed) {
3527                         switch (phydev->speed) {
3528                         case 1000:
3529                                 tempval =
3530                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
3531
3532                                 ecntrl &= ~(ECNTRL_R100);
3533                                 break;
3534                         case 100:
3535                         case 10:
3536                                 tempval =
3537                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
3538
3539                                 /* Reduced mode distinguishes
3540                                  * between 10 and 100
3541                                  */
3542                                 if (phydev->speed == SPEED_100)
3543                                         ecntrl |= ECNTRL_R100;
3544                                 else
3545                                         ecntrl &= ~(ECNTRL_R100);
3546                                 break;
3547                         default:
3548                                 netif_warn(priv, link, priv->ndev,
3549                                            "Ack!  Speed (%d) is not 10/100/1000!\n",
3550                                            phydev->speed);
3551                                 break;
3552                         }
3553
3554                         priv->oldspeed = phydev->speed;
3555                 }
3556
3557                 tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
3558                 tempval1 |= gfar_get_flowctrl_cfg(priv);
3559
3560                 /* Turn last free buffer recording on */
3561                 if ((tempval1 & MACCFG1_TX_FLOW) && !tx_flow_oldval) {
3562                         for (i = 0; i < priv->num_rx_queues; i++) {
3563                                 rx_queue = priv->rx_queue[i];
3564                                 bdp = gfar_rxbd_lastfree(rx_queue);
3565                                 gfar_write(rx_queue->rfbptr, (u32)bdp);
3566                         }
3567
3568                         priv->tx_actual_en = 1;
3569                 }
3570
3571                 if (unlikely(!(tempval1 & MACCFG1_TX_FLOW) && tx_flow_oldval))
3572                         priv->tx_actual_en = 0;
3573
3574                 gfar_write(&regs->maccfg1, tempval1);
3575                 gfar_write(&regs->maccfg2, tempval);
3576                 gfar_write(&regs->ecntrl, ecntrl);
3577
3578                 if (!priv->oldlink)
3579                         priv->oldlink = 1;
3580
3581         } else if (priv->oldlink) {
3582                 priv->oldlink = 0;
3583                 priv->oldspeed = 0;
3584                 priv->oldduplex = -1;
3585         }
3586
3587         if (netif_msg_link(priv))
3588                 phy_print_status(phydev);
3589 }
3590
3591 static const struct of_device_id gfar_match[] =
3592 {
3593         {
3594                 .type = "network",
3595                 .compatible = "gianfar",
3596         },
3597         {
3598                 .compatible = "fsl,etsec2",
3599         },
3600         {},
3601 };
3602 MODULE_DEVICE_TABLE(of, gfar_match);
3603
3604 /* Structure for a device driver */
3605 static struct platform_driver gfar_driver = {
3606         .driver = {
3607                 .name = "fsl-gianfar",
3608                 .pm = GFAR_PM_OPS,
3609                 .of_match_table = gfar_match,
3610         },
3611         .probe = gfar_probe,
3612         .remove = gfar_remove,
3613 };
3614
3615 module_platform_driver(gfar_driver);