drivers/net/ethernet/freescale/gianfar.c

   1 /* drivers/net/ethernet/freescale/gianfar.c
   2  *
   3  * Gianfar Ethernet Driver
   4  * This driver is designed for the non-CPM ethernet controllers
   5  * on the 85xx and 83xx family of integrated processors
   6  * Based on 8260_io/fcc_enet.c
   7  *
   8  * Author: Andy Fleming
   9  * Maintainer: Kumar Gala
  10  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
  11  *
  12  * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
  13  * Copyright 2007 MontaVista Software, Inc.
  14  *
  15  * This program is free software; you can redistribute  it and/or modify it
  16  * under  the terms of  the GNU General  Public License as published by the
  17  * Free Software Foundation;  either version 2 of the  License, or (at your
  18  * option) any later version.
  19  *
  20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  21  *  RA 11 31 24.2
  22  *  Dec +69 19 52
  23  *  V 3.84
  24  *  B-V +1.62
  25  *
  26  *  Theory of operation
  27  *
  28  *  The driver is initialized through of_device. Configuration information
  29  *  is therefore conveyed through an OF-style device tree.
  30  *
  31  *  The Gianfar Ethernet Controller uses a ring of buffer
  32  *  descriptors.  The beginning is indicated by a register
  33  *  pointing to the physical address of the start of the ring.
  34  *  The end is determined by a "wrap" bit being set in the
  35  *  last descriptor of the ring.
  36  *
  37  *  When a packet is received, the RXF bit in the
  38  *  IEVENT register is set, triggering an interrupt when the
  39  *  corresponding bit in the IMASK register is also set (if
  40  *  interrupt coalescing is active, then the interrupt may not
  41  *  happen immediately, but will wait until either a set number
  42  *  of frames or amount of time have passed).  In NAPI, the
  43  *  interrupt handler will signal there is work to be done, and
  44  *  exit. This method will start at the last known empty
  45  *  descriptor, and process every subsequent descriptor until there
  46  *  are none left with data (NAPI will stop after a set number of
  47  *  packets to give time to other tasks, but will eventually
  48  *  process all the packets).  The data arrives inside a
  49  *  pre-allocated skb, and so after the skb is passed up to the
  50  *  stack, a new skb must be allocated, and the address field in
  51  *  the buffer descriptor must be updated to indicate this new
  52  *  skb.
  53  *
  54  *  When the kernel requests that a packet be transmitted, the
  55  *  driver starts where it left off last time, and points the
  56  *  descriptor at the buffer which was passed in.  The driver
  57  *  then informs the DMA engine that there are packets ready to
  58  *  be transmitted.  Once the controller is finished transmitting
  59  *  the packet, an interrupt may be triggered (under the same
  60  *  conditions as for reception, but depending on the TXF bit).
  61  *  The driver then cleans up the buffer.
  62  */
  63
  64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  65 #define DEBUG
  66
  67 #include <linux/kernel.h>
  68 #include <linux/string.h>
  69 #include <linux/errno.h>
  70 #include <linux/unistd.h>
  71 #include <linux/slab.h>
  72 #include <linux/interrupt.h>
  73 #include <linux/delay.h>
  74 #include <linux/netdevice.h>
  75 #include <linux/etherdevice.h>
  76 #include <linux/skbuff.h>
  77 #include <linux/if_vlan.h>
  78 #include <linux/spinlock.h>
  79 #include <linux/mm.h>
  80 #include <linux/of_address.h>
  81 #include <linux/of_irq.h>
  82 #include <linux/of_mdio.h>
  83 #include <linux/of_platform.h>
  84 #include <linux/ip.h>
  85 #include <linux/tcp.h>
  86 #include <linux/udp.h>
  87 #include <linux/in.h>
  88 #include <linux/net_tstamp.h>
  89
  90 #include <asm/io.h>
  91 #ifdef CONFIG_PPC
  92 #include <asm/reg.h>
  93 #include <asm/mpc85xx.h>
  94 #endif
  95 #include <asm/irq.h>
  96 #include <asm/uaccess.h>
  97 #include <linux/module.h>
  98 #include <linux/dma-mapping.h>
  99 #include <linux/crc32.h>
 100 #include <linux/mii.h>
 101 #include <linux/phy.h>
 102 #include <linux/phy_fixed.h>
 103 #include <linux/of.h>
 104 #include <linux/of_net.h>
 105 #include <linux/of_address.h>
 106 #include <linux/of_irq.h>
 107
 108 #include "gianfar.h"
 109
 110 #define TX_TIMEOUT      (1*HZ)
 111
 112 const char gfar_driver_version[] = "1.3";
 113
 114 static int gfar_enet_open(struct net_device *dev);
 115 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
 116 static void gfar_reset_task(struct work_struct *work);
 117 static void gfar_timeout(struct net_device *dev);
 118 static int gfar_close(struct net_device *dev);
 119 static struct sk_buff *gfar_new_skb(struct net_device *dev,
 120                                     dma_addr_t *bufaddr);
 121 static int gfar_set_mac_address(struct net_device *dev);
 122 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
 123 static irqreturn_t gfar_error(int irq, void *dev_id);
 124 static irqreturn_t gfar_transmit(int irq, void *dev_id);
 125 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
 126 static void adjust_link(struct net_device *dev);
 127 static noinline void gfar_update_link_state(struct gfar_private *priv);
 128 static int init_phy(struct net_device *dev);
 129 static int gfar_probe(struct platform_device *ofdev);
 130 static int gfar_remove(struct platform_device *ofdev);
 131 static void free_skb_resources(struct gfar_private *priv);
 132 static void gfar_set_multi(struct net_device *dev);
 133 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
 134 static void gfar_configure_serdes(struct net_device *dev);
 135 static int gfar_poll_rx(struct napi_struct *napi, int budget);
 136 static int gfar_poll_tx(struct napi_struct *napi, int budget);
 137 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget);
 138 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget);
 139 #ifdef CONFIG_NET_POLL_CONTROLLER
 140 static void gfar_netpoll(struct net_device *dev);
 141 #endif
 142 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
 143 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
 144 static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
 145                                int amount_pull, struct napi_struct *napi);
 146 static void gfar_halt_nodisable(struct gfar_private *priv);
 147 static void gfar_clear_exact_match(struct net_device *dev);
 148 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
 149                                   const u8 *addr);
 150 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 151
 152 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 153 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 154 MODULE_LICENSE("GPL");
 155
 156 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 157                             dma_addr_t buf)
 158 {
 159         u32 lstatus;
 160
 161         bdp->bufPtr = buf;
 162
 163         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
 164         if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
 165                 lstatus |= BD_LFLAG(RXBD_WRAP);
 166
 167         gfar_wmb();
 168
 169         bdp->lstatus = lstatus;
 170 }
 171
 172 static int gfar_init_bds(struct net_device *ndev)
 173 {
 174         struct gfar_private *priv = netdev_priv(ndev);
 175         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 176         struct gfar_priv_tx_q *tx_queue = NULL;
 177         struct gfar_priv_rx_q *rx_queue = NULL;
 178         struct txbd8 *txbdp;
 179         struct rxbd8 *rxbdp;
 180         u32 *rfbptr;
 181         int i, j;
 182         dma_addr_t bufaddr;
 183
 184         for (i = 0; i < priv->num_tx_queues; i++) {
 185                 tx_queue = priv->tx_queue[i];
 186                 /* Initialize some variables in our dev structure */
 187                 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
 188                 tx_queue->dirty_tx = tx_queue->tx_bd_base;
 189                 tx_queue->cur_tx = tx_queue->tx_bd_base;
 190                 tx_queue->skb_curtx = 0;
 191                 tx_queue->skb_dirtytx = 0;
 192
 193                 /* Initialize Transmit Descriptor Ring */
 194                 txbdp = tx_queue->tx_bd_base;
 195                 for (j = 0; j < tx_queue->tx_ring_size; j++) {
 196                         txbdp->lstatus = 0;
 197                         txbdp->bufPtr = 0;
 198                         txbdp++;
 199                 }
 200
 201                 /* Set the last descriptor in the ring to indicate wrap */
 202                 txbdp--;
 203                 txbdp->status |= TXBD_WRAP;
 204         }
 205
 206         rfbptr = &regs->rfbptr0;
 207         for (i = 0; i < priv->num_rx_queues; i++) {
 208                 rx_queue = priv->rx_queue[i];
 209                 rx_queue->cur_rx = rx_queue->rx_bd_base;
 210                 rx_queue->skb_currx = 0;
 211                 rxbdp = rx_queue->rx_bd_base;
 212
 213                 for (j = 0; j < rx_queue->rx_ring_size; j++) {
 214                         struct sk_buff *skb = rx_queue->rx_skbuff[j];
 215
 216                         if (skb) {
 217                                 bufaddr = rxbdp->bufPtr;
 218                         } else {
 219                                 skb = gfar_new_skb(ndev, &bufaddr);
 220                                 if (!skb) {
 221                                         netdev_err(ndev, "Can't allocate RX buffers\n");
 222                                         return -ENOMEM;
 223                                 }
 224                                 rx_queue->rx_skbuff[j] = skb;
 225                         }
 226
 227                         gfar_init_rxbdp(rx_queue, rxbdp, bufaddr);
 228                         rxbdp++;
 229                 }
 230
 231                 rx_queue->rfbptr = rfbptr;
 232                 rfbptr += 2;
 233         }
 234
 235         return 0;
 236 }
 237
 238 static int gfar_alloc_skb_resources(struct net_device *ndev)
 239 {
 240         void *vaddr;
 241         dma_addr_t addr;
 242         int i, j, k;
 243         struct gfar_private *priv = netdev_priv(ndev);
 244         struct device *dev = priv->dev;
 245         struct gfar_priv_tx_q *tx_queue = NULL;
 246         struct gfar_priv_rx_q *rx_queue = NULL;
 247
 248         priv->total_tx_ring_size = 0;
 249         for (i = 0; i < priv->num_tx_queues; i++)
 250                 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
 251
 252         priv->total_rx_ring_size = 0;
 253         for (i = 0; i < priv->num_rx_queues; i++)
 254                 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
 255
 256         /* Allocate memory for the buffer descriptors */
 257         vaddr = dma_alloc_coherent(dev,
 258                                    (priv->total_tx_ring_size *
 259                                     sizeof(struct txbd8)) +
 260                                    (priv->total_rx_ring_size *
 261                                     sizeof(struct rxbd8)),
 262                                    &addr, GFP_KERNEL);
 263         if (!vaddr)
 264                 return -ENOMEM;
 265
 266         for (i = 0; i < priv->num_tx_queues; i++) {
 267                 tx_queue = priv->tx_queue[i];
 268                 tx_queue->tx_bd_base = vaddr;
 269                 tx_queue->tx_bd_dma_base = addr;
 270                 tx_queue->dev = ndev;
 271                 /* enet DMA only understands physical addresses */
 272                 addr  += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 273                 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 274         }
 275
 276         /* Start the rx descriptor ring where the tx ring leaves off */
 277         for (i = 0; i < priv->num_rx_queues; i++) {
 278                 rx_queue = priv->rx_queue[i];
 279                 rx_queue->rx_bd_base = vaddr;
 280                 rx_queue->rx_bd_dma_base = addr;
 281                 rx_queue->dev = ndev;
 282                 addr  += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 283                 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 284         }
 285
 286         /* Setup the skbuff rings */
 287         for (i = 0; i < priv->num_tx_queues; i++) {
 288                 tx_queue = priv->tx_queue[i];
 289                 tx_queue->tx_skbuff =
 290                         kmalloc_array(tx_queue->tx_ring_size,
 291                                       sizeof(*tx_queue->tx_skbuff),
 292                                       GFP_KERNEL);
 293                 if (!tx_queue->tx_skbuff)
 294                         goto cleanup;
 295
 296                 for (k = 0; k < tx_queue->tx_ring_size; k++)
 297                         tx_queue->tx_skbuff[k] = NULL;
 298         }
 299
 300         for (i = 0; i < priv->num_rx_queues; i++) {
 301                 rx_queue = priv->rx_queue[i];
 302                 rx_queue->rx_skbuff =
 303                         kmalloc_array(rx_queue->rx_ring_size,
 304                                       sizeof(*rx_queue->rx_skbuff),
 305                                       GFP_KERNEL);
 306                 if (!rx_queue->rx_skbuff)
 307                         goto cleanup;
 308
 309                 for (j = 0; j < rx_queue->rx_ring_size; j++)
 310                         rx_queue->rx_skbuff[j] = NULL;
 311         }
 312
 313         if (gfar_init_bds(ndev))
 314                 goto cleanup;
 315
 316         return 0;
 317
 318 cleanup:
 319         free_skb_resources(priv);
 320         return -ENOMEM;
 321 }
 322
 323 static void gfar_init_tx_rx_base(struct gfar_private *priv)
 324 {
 325         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 326         u32 __iomem *baddr;
 327         int i;
 328
 329         baddr = &regs->tbase0;
 330         for (i = 0; i < priv->num_tx_queues; i++) {
 331                 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
 332                 baddr += 2;
 333         }
 334
 335         baddr = &regs->rbase0;
 336         for (i = 0; i < priv->num_rx_queues; i++) {
 337                 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
 338                 baddr += 2;
 339         }
 340 }
 341
 342 static void gfar_init_rqprm(struct gfar_private *priv)
 343 {
 344         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 345         u32 __iomem *baddr;
 346         int i;
 347
 348         baddr = &regs->rqprm0;
 349         for (i = 0; i < priv->num_rx_queues; i++) {
 350                 gfar_write(baddr, priv->rx_queue[i]->rx_ring_size |
 351                            (DEFAULT_RX_LFC_THR << FBTHR_SHIFT));
 352                 baddr++;
 353         }
 354 }
 355
 356 static void gfar_rx_buff_size_config(struct gfar_private *priv)
 357 {
 358         int frame_size = priv->ndev->mtu + ETH_HLEN + ETH_FCS_LEN;
 359
 360         /* set this when rx hw offload (TOE) functions are being used */
 361         priv->uses_rxfcb = 0;
 362
 363         if (priv->ndev->features & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX))
 364                 priv->uses_rxfcb = 1;
 365
 366         if (priv->hwts_rx_en)
 367                 priv->uses_rxfcb = 1;
 368
 369         if (priv->uses_rxfcb)
 370                 frame_size += GMAC_FCB_LEN;
 371
 372         frame_size += priv->padding;
 373
 374         frame_size = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
 375                      INCREMENTAL_BUFFER_SIZE;
 376
 377         priv->rx_buffer_size = frame_size;
 378 }
 379
 380 static void gfar_mac_rx_config(struct gfar_private *priv)
 381 {
 382         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 383         u32 rctrl = 0;
 384
 385         if (priv->rx_filer_enable) {
 386                 rctrl |= RCTRL_FILREN;
 387                 /* Program the RIR0 reg with the required distribution */
 388                 if (priv->poll_mode == GFAR_SQ_POLLING)
 389                         gfar_write(&regs->rir0, DEFAULT_2RXQ_RIR0);
 390                 else /* GFAR_MQ_POLLING */
 391                         gfar_write(&regs->rir0, DEFAULT_8RXQ_RIR0);
 392         }
 393
 394         /* Restore PROMISC mode */
 395         if (priv->ndev->flags & IFF_PROMISC)
 396                 rctrl |= RCTRL_PROM;
 397
 398         if (priv->ndev->features & NETIF_F_RXCSUM)
 399                 rctrl |= RCTRL_CHECKSUMMING;
 400
 401         if (priv->extended_hash)
 402                 rctrl |= RCTRL_EXTHASH | RCTRL_EMEN;
 403
 404         if (priv->padding) {
 405                 rctrl &= ~RCTRL_PAL_MASK;
 406                 rctrl |= RCTRL_PADDING(priv->padding);
 407         }
 408
 409         /* Enable HW time stamping if requested from user space */
 410         if (priv->hwts_rx_en)
 411                 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
 412
 413         if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)
 414                 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
 415
 416         /* Clear the LFC bit */
 417         gfar_write(&regs->rctrl, rctrl);
 418         /* Init flow control threshold values */
 419         gfar_init_rqprm(priv);
 420         gfar_write(&regs->ptv, DEFAULT_LFC_PTVVAL);
 421         rctrl |= RCTRL_LFC;
 422
 423         /* Init rctrl based on our settings */
 424         gfar_write(&regs->rctrl, rctrl);
 425 }
 426
 427 static void gfar_mac_tx_config(struct gfar_private *priv)
 428 {
 429         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 430         u32 tctrl = 0;
 431
 432         if (priv->ndev->features & NETIF_F_IP_CSUM)
 433                 tctrl |= TCTRL_INIT_CSUM;
 434
 435         if (priv->prio_sched_en)
 436                 tctrl |= TCTRL_TXSCHED_PRIO;
 437         else {
 438                 tctrl |= TCTRL_TXSCHED_WRRS;
 439                 gfar_write(&regs->tr03wt, DEFAULT_WRRS_WEIGHT);
 440                 gfar_write(&regs->tr47wt, DEFAULT_WRRS_WEIGHT);
 441         }
 442
 443         if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_TX)
 444                 tctrl |= TCTRL_VLINS;
 445
 446         gfar_write(&regs->tctrl, tctrl);
 447 }
 448
 449 static void gfar_configure_coalescing(struct gfar_private *priv,
 450                                unsigned long tx_mask, unsigned long rx_mask)
 451 {
 452         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 453         u32 __iomem *baddr;
 454
 455         if (priv->mode == MQ_MG_MODE) {
 456                 int i = 0;
 457
 458                 baddr = &regs->txic0;
 459                 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
 460                         gfar_write(baddr + i, 0);
 461                         if (likely(priv->tx_queue[i]->txcoalescing))
 462                                 gfar_write(baddr + i, priv->tx_queue[i]->txic);
 463                 }
 464
 465                 baddr = &regs->rxic0;
 466                 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
 467                         gfar_write(baddr + i, 0);
 468                         if (likely(priv->rx_queue[i]->rxcoalescing))
 469                                 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
 470                 }
 471         } else {
 472                 /* Backward compatible case -- even if we enable
 473                  * multiple queues, there's only single reg to program
 474                  */
 475                 gfar_write(&regs->txic, 0);
 476                 if (likely(priv->tx_queue[0]->txcoalescing))
 477                         gfar_write(&regs->txic, priv->tx_queue[0]->txic);
 478
 479                 gfar_write(&regs->rxic, 0);
 480                 if (unlikely(priv->rx_queue[0]->rxcoalescing))
 481                         gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
 482         }
 483 }
 484
 485 void gfar_configure_coalescing_all(struct gfar_private *priv)
 486 {
 487         gfar_configure_coalescing(priv, 0xFF, 0xFF);
 488 }
 489
 490 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
 491 {
 492         struct gfar_private *priv = netdev_priv(dev);
 493         unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
 494         unsigned long tx_packets = 0, tx_bytes = 0;
 495         int i;
 496
 497         for (i = 0; i < priv->num_rx_queues; i++) {
 498                 rx_packets += priv->rx_queue[i]->stats.rx_packets;
 499                 rx_bytes   += priv->rx_queue[i]->stats.rx_bytes;
 500                 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
 501         }
 502
 503         dev->stats.rx_packets = rx_packets;
 504         dev->stats.rx_bytes   = rx_bytes;
 505         dev->stats.rx_dropped = rx_dropped;
 506
 507         for (i = 0; i < priv->num_tx_queues; i++) {
 508                 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
 509                 tx_packets += priv->tx_queue[i]->stats.tx_packets;
 510         }
 511
 512         dev->stats.tx_bytes   = tx_bytes;
 513         dev->stats.tx_packets = tx_packets;
 514
 515         return &dev->stats;
 516 }
 517
 518 static const struct net_device_ops gfar_netdev_ops = {
 519         .ndo_open = gfar_enet_open,
 520         .ndo_start_xmit = gfar_start_xmit,
 521         .ndo_stop = gfar_close,
 522         .ndo_change_mtu = gfar_change_mtu,
 523         .ndo_set_features = gfar_set_features,
 524         .ndo_set_rx_mode = gfar_set_multi,
 525         .ndo_tx_timeout = gfar_timeout,
 526         .ndo_do_ioctl = gfar_ioctl,
 527         .ndo_get_stats = gfar_get_stats,
 528         .ndo_set_mac_address = eth_mac_addr,
 529         .ndo_validate_addr = eth_validate_addr,
 530 #ifdef CONFIG_NET_POLL_CONTROLLER
 531         .ndo_poll_controller = gfar_netpoll,
 532 #endif
 533 };
 534
 535 static void gfar_ints_disable(struct gfar_private *priv)
 536 {
 537         int i;
 538         for (i = 0; i < priv->num_grps; i++) {
 539                 struct gfar __iomem *regs = priv->gfargrp[i].regs;
 540                 /* Clear IEVENT */
 541                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
 542
 543                 /* Initialize IMASK */
 544                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
 545         }
 546 }
 547
 548 static void gfar_ints_enable(struct gfar_private *priv)
 549 {
 550         int i;
 551         for (i = 0; i < priv->num_grps; i++) {
 552                 struct gfar __iomem *regs = priv->gfargrp[i].regs;
 553                 /* Unmask the interrupts we look for */
 554                 gfar_write(&regs->imask, IMASK_DEFAULT);
 555         }
 556 }
 557
 558 static void lock_tx_qs(struct gfar_private *priv)
 559 {
 560         int i;
 561
 562         for (i = 0; i < priv->num_tx_queues; i++)
 563                 spin_lock(&priv->tx_queue[i]->txlock);
 564 }
 565
 566 static void unlock_tx_qs(struct gfar_private *priv)
 567 {
 568         int i;
 569
 570         for (i = 0; i < priv->num_tx_queues; i++)
 571                 spin_unlock(&priv->tx_queue[i]->txlock);
 572 }
 573
 574 static int gfar_alloc_tx_queues(struct gfar_private *priv)
 575 {
 576         int i;
 577
 578         for (i = 0; i < priv->num_tx_queues; i++) {
 579                 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
 580                                             GFP_KERNEL);
 581                 if (!priv->tx_queue[i])
 582                         return -ENOMEM;
 583
 584                 priv->tx_queue[i]->tx_skbuff = NULL;
 585                 priv->tx_queue[i]->qindex = i;
 586                 priv->tx_queue[i]->dev = priv->ndev;
 587                 spin_lock_init(&(priv->tx_queue[i]->txlock));
 588         }
 589         return 0;
 590 }
 591
 592 static int gfar_alloc_rx_queues(struct gfar_private *priv)
 593 {
 594         int i;
 595
 596         for (i = 0; i < priv->num_rx_queues; i++) {
 597                 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
 598                                             GFP_KERNEL);
 599                 if (!priv->rx_queue[i])
 600                         return -ENOMEM;
 601
 602                 priv->rx_queue[i]->rx_skbuff = NULL;
 603                 priv->rx_queue[i]->qindex = i;
 604                 priv->rx_queue[i]->dev = priv->ndev;
 605         }
 606         return 0;
 607 }
 608
 609 static void gfar_free_tx_queues(struct gfar_private *priv)
 610 {
 611         int i;
 612
 613         for (i = 0; i < priv->num_tx_queues; i++)
 614                 kfree(priv->tx_queue[i]);
 615 }
 616
 617 static void gfar_free_rx_queues(struct gfar_private *priv)
 618 {
 619         int i;
 620
 621         for (i = 0; i < priv->num_rx_queues; i++)
 622                 kfree(priv->rx_queue[i]);
 623 }
 624
 625 static void unmap_group_regs(struct gfar_private *priv)
 626 {
 627         int i;
 628
 629         for (i = 0; i < MAXGROUPS; i++)
 630                 if (priv->gfargrp[i].regs)
 631                         iounmap(priv->gfargrp[i].regs);
 632 }
 633
 634 static void free_gfar_dev(struct gfar_private *priv)
 635 {
 636         int i, j;
 637
 638         for (i = 0; i < priv->num_grps; i++)
 639                 for (j = 0; j < GFAR_NUM_IRQS; j++) {
 640                         kfree(priv->gfargrp[i].irqinfo[j]);
 641                         priv->gfargrp[i].irqinfo[j] = NULL;
 642                 }
 643
 644         free_netdev(priv->ndev);
 645 }
 646
 647 static void disable_napi(struct gfar_private *priv)
 648 {
 649         int i;
 650
 651         for (i = 0; i < priv->num_grps; i++) {
 652                 napi_disable(&priv->gfargrp[i].napi_rx);
 653                 napi_disable(&priv->gfargrp[i].napi_tx);
 654         }
 655 }
 656
 657 static void enable_napi(struct gfar_private *priv)
 658 {
 659         int i;
 660
 661         for (i = 0; i < priv->num_grps; i++) {
 662                 napi_enable(&priv->gfargrp[i].napi_rx);
 663                 napi_enable(&priv->gfargrp[i].napi_tx);
 664         }
 665 }
 666
 667 static int gfar_parse_group(struct device_node *np,
 668                             struct gfar_private *priv, const char *model)
 669 {
 670         struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
 671         int i;
 672
 673         for (i = 0; i < GFAR_NUM_IRQS; i++) {
 674                 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
 675                                           GFP_KERNEL);
 676                 if (!grp->irqinfo[i])
 677                         return -ENOMEM;
 678         }
 679
 680         grp->regs = of_iomap(np, 0);
 681         if (!grp->regs)
 682                 return -ENOMEM;
 683
 684         gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
 685
 686         /* If we aren't the FEC we have multiple interrupts */
 687         if (model && strcasecmp(model, "FEC")) {
 688                 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
 689                 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
 690                 if (gfar_irq(grp, TX)->irq == NO_IRQ ||
 691                     gfar_irq(grp, RX)->irq == NO_IRQ ||
 692                     gfar_irq(grp, ER)->irq == NO_IRQ)
 693                         return -EINVAL;
 694         }
 695
 696         grp->priv = priv;
 697         spin_lock_init(&grp->grplock);
 698         if (priv->mode == MQ_MG_MODE) {
 699                 u32 *rxq_mask, *txq_mask;
 700                 rxq_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL);
 701                 txq_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL);
 702
 703                 if (priv->poll_mode == GFAR_SQ_POLLING) {
 704                         /* One Q per interrupt group: Q0 to G0, Q1 to G1 */
 705                         grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 706                         grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 707                 } else { /* GFAR_MQ_POLLING */
 708                         grp->rx_bit_map = rxq_mask ?
 709                         *rxq_mask : (DEFAULT_MAPPING >> priv->num_grps);
 710                         grp->tx_bit_map = txq_mask ?
 711                         *txq_mask : (DEFAULT_MAPPING >> priv->num_grps);
 712                 }
 713         } else {
 714                 grp->rx_bit_map = 0xFF;
 715                 grp->tx_bit_map = 0xFF;
 716         }
 717
 718         /* bit_map's MSB is q0 (from q0 to q7) but, for_each_set_bit parses
 719          * right to left, so we need to revert the 8 bits to get the q index
 720          */
 721         grp->rx_bit_map = bitrev8(grp->rx_bit_map);
 722         grp->tx_bit_map = bitrev8(grp->tx_bit_map);
 723
 724         /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
 725          * also assign queues to groups
 726          */
 727         for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
 728                 if (!grp->rx_queue)
 729                         grp->rx_queue = priv->rx_queue[i];
 730                 grp->num_rx_queues++;
 731                 grp->rstat |= (RSTAT_CLEAR_RHALT >> i);
 732                 priv->rqueue |= ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
 733                 priv->rx_queue[i]->grp = grp;
 734         }
 735
 736         for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
 737                 if (!grp->tx_queue)
 738                         grp->tx_queue = priv->tx_queue[i];
 739                 grp->num_tx_queues++;
 740                 grp->tstat |= (TSTAT_CLEAR_THALT >> i);
 741                 priv->tqueue |= (TQUEUE_EN0 >> i);
 742                 priv->tx_queue[i]->grp = grp;
 743         }
 744
 745         priv->num_grps++;
 746
 747         return 0;
 748 }
 749
 750 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
 751 {
 752         const char *model;
 753         const char *ctype;
 754         const void *mac_addr;
 755         int err = 0, i;
 756         struct net_device *dev = NULL;
 757         struct gfar_private *priv = NULL;
 758         struct device_node *np = ofdev->dev.of_node;
 759         struct device_node *child = NULL;
 760         const u32 *stash;
 761         const u32 *stash_len;
 762         const u32 *stash_idx;
 763         unsigned int num_tx_qs, num_rx_qs;
 764         u32 *tx_queues, *rx_queues;
 765         unsigned short mode, poll_mode;
 766
 767         if (!np || !of_device_is_available(np))
 768                 return -ENODEV;
 769
 770         if (of_device_is_compatible(np, "fsl,etsec2")) {
 771                 mode = MQ_MG_MODE;
 772                 poll_mode = GFAR_SQ_POLLING;
 773         } else {
 774                 mode = SQ_SG_MODE;
 775                 poll_mode = GFAR_SQ_POLLING;
 776         }
 777
 778         /* parse the num of HW tx and rx queues */
 779         tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
 780         rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
 781
 782         if (mode == SQ_SG_MODE) {
 783                 num_tx_qs = 1;
 784                 num_rx_qs = 1;
 785         } else { /* MQ_MG_MODE */
 786                 /* get the actual number of supported groups */
 787                 unsigned int num_grps = of_get_available_child_count(np);
 788
 789                 if (num_grps == 0 || num_grps > MAXGROUPS) {
 790                         dev_err(&ofdev->dev, "Invalid # of int groups(%d)\n",
 791                                 num_grps);
 792                         pr_err("Cannot do alloc_etherdev, aborting\n");
 793                         return -EINVAL;
 794                 }
 795
 796                 if (poll_mode == GFAR_SQ_POLLING) {
 797                         num_tx_qs = num_grps; /* one txq per int group */
 798                         num_rx_qs = num_grps; /* one rxq per int group */
 799                 } else { /* GFAR_MQ_POLLING */
 800                         num_tx_qs = tx_queues ? *tx_queues : 1;
 801                         num_rx_qs = rx_queues ? *rx_queues : 1;
 802                 }
 803         }
 804
 805         if (num_tx_qs > MAX_TX_QS) {
 806                 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
 807                        num_tx_qs, MAX_TX_QS);
 808                 pr_err("Cannot do alloc_etherdev, aborting\n");
 809                 return -EINVAL;
 810         }
 811
 812         if (num_rx_qs > MAX_RX_QS) {
 813                 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
 814                        num_rx_qs, MAX_RX_QS);
 815                 pr_err("Cannot do alloc_etherdev, aborting\n");
 816                 return -EINVAL;
 817         }
 818
 819         *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
 820         dev = *pdev;
 821         if (NULL == dev)
 822                 return -ENOMEM;
 823
 824         priv = netdev_priv(dev);
 825         priv->ndev = dev;
 826
 827         priv->mode = mode;
 828         priv->poll_mode = poll_mode;
 829
 830         priv->num_tx_queues = num_tx_qs;
 831         netif_set_real_num_rx_queues(dev, num_rx_qs);
 832         priv->num_rx_queues = num_rx_qs;
 833
 834         err = gfar_alloc_tx_queues(priv);
 835         if (err)
 836                 goto tx_alloc_failed;
 837
 838         err = gfar_alloc_rx_queues(priv);
 839         if (err)
 840                 goto rx_alloc_failed;
 841
 842         /* Init Rx queue filer rule set linked list */
 843         INIT_LIST_HEAD(&priv->rx_list.list);
 844         priv->rx_list.count = 0;
 845         mutex_init(&priv->rx_queue_access);
 846
 847         model = of_get_property(np, "model", NULL);
 848
 849         for (i = 0; i < MAXGROUPS; i++)
 850                 priv->gfargrp[i].regs = NULL;
 851
 852         /* Parse and initialize group specific information */
 853         if (priv->mode == MQ_MG_MODE) {
 854                 for_each_child_of_node(np, child) {
 855                         err = gfar_parse_group(child, priv, model);
 856                         if (err)
 857                                 goto err_grp_init;
 858                 }
 859         } else { /* SQ_SG_MODE */
 860                 err = gfar_parse_group(np, priv, model);
 861                 if (err)
 862                         goto err_grp_init;
 863         }
 864
 865         stash = of_get_property(np, "bd-stash", NULL);
 866
 867         if (stash) {
 868                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
 869                 priv->bd_stash_en = 1;
 870         }
 871
 872         stash_len = of_get_property(np, "rx-stash-len", NULL);
 873
 874         if (stash_len)
 875                 priv->rx_stash_size = *stash_len;
 876
 877         stash_idx = of_get_property(np, "rx-stash-idx", NULL);
 878
 879         if (stash_idx)
 880                 priv->rx_stash_index = *stash_idx;
 881
 882         if (stash_len || stash_idx)
 883                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
 884
 885         mac_addr = of_get_mac_address(np);
 886
 887         if (mac_addr)
 888                 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
 889
 890         if (model && !strcasecmp(model, "TSEC"))
 891                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
 892                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 893                                      FSL_GIANFAR_DEV_HAS_RMON |
 894                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR;
 895
 896         if (model && !strcasecmp(model, "eTSEC"))
 897                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
 898                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 899                                      FSL_GIANFAR_DEV_HAS_RMON |
 900                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR |
 901                                      FSL_GIANFAR_DEV_HAS_CSUM |
 902                                      FSL_GIANFAR_DEV_HAS_VLAN |
 903                                      FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
 904                                      FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
 905                                      FSL_GIANFAR_DEV_HAS_TIMER;
 906
 907         ctype = of_get_property(np, "phy-connection-type", NULL);
 908
 909         /* We only care about rgmii-id.  The rest are autodetected */
 910         if (ctype && !strcmp(ctype, "rgmii-id"))
 911                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
 912         else
 913                 priv->interface = PHY_INTERFACE_MODE_MII;
 914
 915         if (of_get_property(np, "fsl,magic-packet", NULL))
 916                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
 917
 918         priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
 919
 920         /* In the case of a fixed PHY, the DT node associated
 921          * to the PHY is the Ethernet MAC DT node.
 922          */
 923         if (!priv->phy_node && of_phy_is_fixed_link(np)) {
 924                 err = of_phy_register_fixed_link(np);
 925                 if (err)
 926                         goto err_grp_init;
 927
 928                 priv->phy_node = of_node_get(np);
 929         }
 930
 931         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
 932         priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
 933
 934         return 0;
 935
 936 err_grp_init:
 937         unmap_group_regs(priv);
 938 rx_alloc_failed:
 939         gfar_free_rx_queues(priv);
 940 tx_alloc_failed:
 941         gfar_free_tx_queues(priv);
 942         free_gfar_dev(priv);
 943         return err;
 944 }
 945
 946 static int gfar_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
 947 {
 948         struct hwtstamp_config config;
 949         struct gfar_private *priv = netdev_priv(netdev);
 950
 951         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
 952                 return -EFAULT;
 953
 954         /* reserved for future extensions */
 955         if (config.flags)
 956                 return -EINVAL;
 957
 958         switch (config.tx_type) {
 959         case HWTSTAMP_TX_OFF:
 960                 priv->hwts_tx_en = 0;
 961                 break;
 962         case HWTSTAMP_TX_ON:
 963                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 964                         return -ERANGE;
 965                 priv->hwts_tx_en = 1;
 966                 break;
 967         default:
 968                 return -ERANGE;
 969         }
 970
 971         switch (config.rx_filter) {
 972         case HWTSTAMP_FILTER_NONE:
 973                 if (priv->hwts_rx_en) {
 974                         priv->hwts_rx_en = 0;
 975                         reset_gfar(netdev);
 976                 }
 977                 break;
 978         default:
 979                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 980                         return -ERANGE;
 981                 if (!priv->hwts_rx_en) {
 982                         priv->hwts_rx_en = 1;
 983                         reset_gfar(netdev);
 984                 }
 985                 config.rx_filter = HWTSTAMP_FILTER_ALL;
 986                 break;
 987         }
 988
 989         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 990                 -EFAULT : 0;
 991 }
 992
 993 static int gfar_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
 994 {
 995         struct hwtstamp_config config;
 996         struct gfar_private *priv = netdev_priv(netdev);
 997
 998         config.flags = 0;
 999         config.tx_type = priv->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1000         config.rx_filter = (priv->hwts_rx_en ?
1001                             HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE);
1002
1003         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1004                 -EFAULT : 0;
1005 }
1006
1007 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1008 {
1009         struct gfar_private *priv = netdev_priv(dev);
1010
1011         if (!netif_running(dev))
1012                 return -EINVAL;
1013
1014         if (cmd == SIOCSHWTSTAMP)
1015                 return gfar_hwtstamp_set(dev, rq);
1016         if (cmd == SIOCGHWTSTAMP)
1017                 return gfar_hwtstamp_get(dev, rq);
1018
1019         if (!priv->phydev)
1020                 return -ENODEV;
1021
1022         return phy_mii_ioctl(priv->phydev, rq, cmd);
1023 }
1024
1025 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
1026                                    u32 class)
1027 {
1028         u32 rqfpr = FPR_FILER_MASK;
1029         u32 rqfcr = 0x0;
1030
1031         rqfar--;
1032         rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
1033         priv->ftp_rqfpr[rqfar] = rqfpr;
1034         priv->ftp_rqfcr[rqfar] = rqfcr;
1035         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1036
1037         rqfar--;
1038         rqfcr = RQFCR_CMP_NOMATCH;
1039         priv->ftp_rqfpr[rqfar] = rqfpr;
1040         priv->ftp_rqfcr[rqfar] = rqfcr;
1041         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1042
1043         rqfar--;
1044         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
1045         rqfpr = class;
1046         priv->ftp_rqfcr[rqfar] = rqfcr;
1047         priv->ftp_rqfpr[rqfar] = rqfpr;
1048         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1049
1050         rqfar--;
1051         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
1052         rqfpr = class;
1053         priv->ftp_rqfcr[rqfar] = rqfcr;
1054         priv->ftp_rqfpr[rqfar] = rqfpr;
1055         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1056
1057         return rqfar;
1058 }
1059
1060 static void gfar_init_filer_table(struct gfar_private *priv)
1061 {
1062         int i = 0x0;
1063         u32 rqfar = MAX_FILER_IDX;
1064         u32 rqfcr = 0x0;
1065         u32 rqfpr = FPR_FILER_MASK;
1066
1067         /* Default rule */
1068         rqfcr = RQFCR_CMP_MATCH;
1069         priv->ftp_rqfcr[rqfar] = rqfcr;
1070         priv->ftp_rqfpr[rqfar] = rqfpr;
1071         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1072
1073         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
1074         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
1075         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
1076         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
1077         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
1078         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
1079
1080         /* cur_filer_idx indicated the first non-masked rule */
1081         priv->cur_filer_idx = rqfar;
1082
1083         /* Rest are masked rules */
1084         rqfcr = RQFCR_CMP_NOMATCH;
1085         for (i = 0; i < rqfar; i++) {
1086                 priv->ftp_rqfcr[i] = rqfcr;
1087                 priv->ftp_rqfpr[i] = rqfpr;
1088                 gfar_write_filer(priv, i, rqfcr, rqfpr);
1089         }
1090 }
1091
1092 #ifdef CONFIG_PPC
1093 static void __gfar_detect_errata_83xx(struct gfar_private *priv)
1094 {
1095         unsigned int pvr = mfspr(SPRN_PVR);
1096         unsigned int svr = mfspr(SPRN_SVR);
1097         unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
1098         unsigned int rev = svr & 0xffff;
1099
1100         /* MPC8313 Rev 2.0 and higher; All MPC837x */
1101         if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
1102             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
1103                 priv->errata |= GFAR_ERRATA_74;
1104
1105         /* MPC8313 and MPC837x all rev */
1106         if ((pvr == 0x80850010 && mod == 0x80b0) ||
1107             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
1108                 priv->errata |= GFAR_ERRATA_76;
1109
1110         /* MPC8313 Rev < 2.0 */
1111         if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020)
1112                 priv->errata |= GFAR_ERRATA_12;
1113 }
1114
1115 static void __gfar_detect_errata_85xx(struct gfar_private *priv)
1116 {
1117         unsigned int svr = mfspr(SPRN_SVR);
1118
1119         if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20))
1120                 priv->errata |= GFAR_ERRATA_12;
1121         if (((SVR_SOC_VER(svr) == SVR_P2020) && (SVR_REV(svr) < 0x20)) ||
1122             ((SVR_SOC_VER(svr) == SVR_P2010) && (SVR_REV(svr) < 0x20)))
1123                 priv->errata |= GFAR_ERRATA_76; /* aka eTSEC 20 */
1124 }
1125 #endif
1126
1127 static void gfar_detect_errata(struct gfar_private *priv)
1128 {
1129         struct device *dev = &priv->ofdev->dev;
1130
1131         /* no plans to fix */
1132         priv->errata |= GFAR_ERRATA_A002;
1133
1134 #ifdef CONFIG_PPC
1135         if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2))
1136                 __gfar_detect_errata_85xx(priv);
1137         else /* non-mpc85xx parts, i.e. e300 core based */
1138                 __gfar_detect_errata_83xx(priv);
1139 #endif
1140
1141         if (priv->errata)
1142                 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
1143                          priv->errata);
1144 }
1145
1146 void gfar_mac_reset(struct gfar_private *priv)
1147 {
1148         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1149         u32 tempval;
1150
1151         /* Reset MAC layer */
1152         gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1153
1154         /* We need to delay at least 3 TX clocks */
1155         udelay(3);
1156
1157         /* the soft reset bit is not self-resetting, so we need to
1158          * clear it before resuming normal operation
1159          */
1160         gfar_write(&regs->maccfg1, 0);
1161
1162         udelay(3);
1163
1164         /* Compute rx_buff_size based on config flags */
1165         gfar_rx_buff_size_config(priv);
1166
1167         /* Initialize the max receive frame/buffer lengths */
1168         gfar_write(&regs->maxfrm, priv->rx_buffer_size);
1169         gfar_write(&regs->mrblr, priv->rx_buffer_size);
1170
1171         /* Initialize the Minimum Frame Length Register */
1172         gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1173
1174         /* Initialize MACCFG2. */
1175         tempval = MACCFG2_INIT_SETTINGS;
1176
1177         /* If the mtu is larger than the max size for standard
1178          * ethernet frames (ie, a jumbo frame), then set maccfg2
1179          * to allow huge frames, and to check the length
1180          */
1181         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
1182             gfar_has_errata(priv, GFAR_ERRATA_74))
1183                 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1184
1185         gfar_write(&regs->maccfg2, tempval);
1186
1187         /* Clear mac addr hash registers */
1188         gfar_write(&regs->igaddr0, 0);
1189         gfar_write(&regs->igaddr1, 0);
1190         gfar_write(&regs->igaddr2, 0);
1191         gfar_write(&regs->igaddr3, 0);
1192         gfar_write(&regs->igaddr4, 0);
1193         gfar_write(&regs->igaddr5, 0);
1194         gfar_write(&regs->igaddr6, 0);
1195         gfar_write(&regs->igaddr7, 0);
1196
1197         gfar_write(&regs->gaddr0, 0);
1198         gfar_write(&regs->gaddr1, 0);
1199         gfar_write(&regs->gaddr2, 0);
1200         gfar_write(&regs->gaddr3, 0);
1201         gfar_write(&regs->gaddr4, 0);
1202         gfar_write(&regs->gaddr5, 0);
1203         gfar_write(&regs->gaddr6, 0);
1204         gfar_write(&regs->gaddr7, 0);
1205
1206         if (priv->extended_hash)
1207                 gfar_clear_exact_match(priv->ndev);
1208
1209         gfar_mac_rx_config(priv);
1210
1211         gfar_mac_tx_config(priv);
1212
1213         gfar_set_mac_address(priv->ndev);
1214
1215         gfar_set_multi(priv->ndev);
1216
1217         /* clear ievent and imask before configuring coalescing */
1218         gfar_ints_disable(priv);
1219
1220         /* Configure the coalescing support */
1221         gfar_configure_coalescing_all(priv);
1222 }
1223
1224 static void gfar_hw_init(struct gfar_private *priv)
1225 {
1226         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1227         u32 attrs;
1228
1229         /* Stop the DMA engine now, in case it was running before
1230          * (The firmware could have used it, and left it running).
1231          */
1232         gfar_halt(priv);
1233
1234         gfar_mac_reset(priv);
1235
1236         /* Zero out the rmon mib registers if it has them */
1237         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1238                 memset_io(&(regs->rmon), 0, sizeof(struct rmon_mib));
1239
1240                 /* Mask off the CAM interrupts */
1241                 gfar_write(&regs->rmon.cam1, 0xffffffff);
1242                 gfar_write(&regs->rmon.cam2, 0xffffffff);
1243         }
1244
1245         /* Initialize ECNTRL */
1246         gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1247
1248         /* Set the extraction length and index */
1249         attrs = ATTRELI_EL(priv->rx_stash_size) |
1250                 ATTRELI_EI(priv->rx_stash_index);
1251
1252         gfar_write(&regs->attreli, attrs);
1253
1254         /* Start with defaults, and add stashing
1255          * depending on driver parameters
1256          */
1257         attrs = ATTR_INIT_SETTINGS;
1258
1259         if (priv->bd_stash_en)
1260                 attrs |= ATTR_BDSTASH;
1261
1262         if (priv->rx_stash_size != 0)
1263                 attrs |= ATTR_BUFSTASH;
1264
1265         gfar_write(&regs->attr, attrs);
1266
1267         /* FIFO configs */
1268         gfar_write(&regs->fifo_tx_thr, DEFAULT_FIFO_TX_THR);
1269         gfar_write(&regs->fifo_tx_starve, DEFAULT_FIFO_TX_STARVE);
1270         gfar_write(&regs->fifo_tx_starve_shutoff, DEFAULT_FIFO_TX_STARVE_OFF);
1271
1272         /* Program the interrupt steering regs, only for MG devices */
1273         if (priv->num_grps > 1)
1274                 gfar_write_isrg(priv);
1275 }
1276
1277 static void gfar_init_addr_hash_table(struct gfar_private *priv)
1278 {
1279         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1280
1281         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1282                 priv->extended_hash = 1;
1283                 priv->hash_width = 9;
1284
1285                 priv->hash_regs[0] = &regs->igaddr0;
1286                 priv->hash_regs[1] = &regs->igaddr1;
1287                 priv->hash_regs[2] = &regs->igaddr2;
1288                 priv->hash_regs[3] = &regs->igaddr3;
1289                 priv->hash_regs[4] = &regs->igaddr4;
1290                 priv->hash_regs[5] = &regs->igaddr5;
1291                 priv->hash_regs[6] = &regs->igaddr6;
1292                 priv->hash_regs[7] = &regs->igaddr7;
1293                 priv->hash_regs[8] = &regs->gaddr0;
1294                 priv->hash_regs[9] = &regs->gaddr1;
1295                 priv->hash_regs[10] = &regs->gaddr2;
1296                 priv->hash_regs[11] = &regs->gaddr3;
1297                 priv->hash_regs[12] = &regs->gaddr4;
1298                 priv->hash_regs[13] = &regs->gaddr5;
1299                 priv->hash_regs[14] = &regs->gaddr6;
1300                 priv->hash_regs[15] = &regs->gaddr7;
1301
1302         } else {
1303                 priv->extended_hash = 0;
1304                 priv->hash_width = 8;
1305
1306                 priv->hash_regs[0] = &regs->gaddr0;
1307                 priv->hash_regs[1] = &regs->gaddr1;
1308                 priv->hash_regs[2] = &regs->gaddr2;
1309                 priv->hash_regs[3] = &regs->gaddr3;
1310                 priv->hash_regs[4] = &regs->gaddr4;
1311                 priv->hash_regs[5] = &regs->gaddr5;
1312                 priv->hash_regs[6] = &regs->gaddr6;
1313                 priv->hash_regs[7] = &regs->gaddr7;
1314         }
1315 }
1316
1317 /* Set up the ethernet device structure, private data,
1318  * and anything else we need before we start
1319  */
1320 static int gfar_probe(struct platform_device *ofdev)
1321 {
1322         struct net_device *dev = NULL;
1323         struct gfar_private *priv = NULL;
1324         int err = 0, i;
1325
1326         err = gfar_of_init(ofdev, &dev);
1327
1328         if (err)
1329                 return err;
1330
1331         priv = netdev_priv(dev);
1332         priv->ndev = dev;
1333         priv->ofdev = ofdev;
1334         priv->dev = &ofdev->dev;
1335         SET_NETDEV_DEV(dev, &ofdev->dev);
1336
1337         spin_lock_init(&priv->bflock);
1338         INIT_WORK(&priv->reset_task, gfar_reset_task);
1339
1340         platform_set_drvdata(ofdev, priv);
1341
1342         gfar_detect_errata(priv);
1343
1344         /* Set the dev->base_addr to the gfar reg region */
1345         dev->base_addr = (unsigned long) priv->gfargrp[0].regs;
1346
1347         /* Fill in the dev structure */
1348         dev->watchdog_timeo = TX_TIMEOUT;
1349         dev->mtu = 1500;
1350         dev->netdev_ops = &gfar_netdev_ops;
1351         dev->ethtool_ops = &gfar_ethtool_ops;
1352
1353         /* Register for napi ...We are registering NAPI for each grp */
1354         for (i = 0; i < priv->num_grps; i++) {
1355                 if (priv->poll_mode == GFAR_SQ_POLLING) {
1356                         netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1357                                        gfar_poll_rx_sq, GFAR_DEV_WEIGHT);
1358                         netif_napi_add(dev, &priv->gfargrp[i].napi_tx,
1359                                        gfar_poll_tx_sq, 2);
1360                 } else {
1361                         netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1362                                        gfar_poll_rx, GFAR_DEV_WEIGHT);
1363                         netif_napi_add(dev, &priv->gfargrp[i].napi_tx,
1364                                        gfar_poll_tx, 2);
1365                 }
1366         }
1367
1368         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1369                 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1370                                    NETIF_F_RXCSUM;
1371                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1372                                  NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1373         }
1374
1375         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
1376                 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
1377                                     NETIF_F_HW_VLAN_CTAG_RX;
1378                 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
1379         }
1380
1381         gfar_init_addr_hash_table(priv);
1382
1383         /* Insert receive time stamps into padding alignment bytes */
1384         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1385                 priv->padding = 8;
1386
1387         if (dev->features & NETIF_F_IP_CSUM ||
1388             priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1389                 dev->needed_headroom = GMAC_FCB_LEN;
1390
1391         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1392
1393         /* Initializing some of the rx/tx queue level parameters */
1394         for (i = 0; i < priv->num_tx_queues; i++) {
1395                 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1396                 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1397                 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1398                 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1399         }
1400
1401         for (i = 0; i < priv->num_rx_queues; i++) {
1402                 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1403                 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1404                 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1405         }
1406
1407         /* always enable rx filer */
1408         priv->rx_filer_enable = 1;
1409         /* Enable most messages by default */
1410         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1411         /* use pritority h/w tx queue scheduling for single queue devices */
1412         if (priv->num_tx_queues == 1)
1413                 priv->prio_sched_en = 1;
1414
1415         set_bit(GFAR_DOWN, &priv->state);
1416
1417         gfar_hw_init(priv);
1418
1419         /* Carrier starts down, phylib will bring it up */
1420         netif_carrier_off(dev);
1421
1422         err = register_netdev(dev);
1423
1424         if (err) {
1425                 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1426                 goto register_fail;
1427         }
1428
1429         device_init_wakeup(&dev->dev,
1430                            priv->device_flags &
1431                            FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1432
1433         /* fill out IRQ number and name fields */
1434         for (i = 0; i < priv->num_grps; i++) {
1435                 struct gfar_priv_grp *grp = &priv->gfargrp[i];
1436                 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1437                         sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
1438                                 dev->name, "_g", '0' + i, "_tx");
1439                         sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
1440                                 dev->name, "_g", '0' + i, "_rx");
1441                         sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
1442                                 dev->name, "_g", '0' + i, "_er");
1443                 } else
1444                         strcpy(gfar_irq(grp, TX)->name, dev->name);
1445         }
1446
1447         /* Initialize the filer table */
1448         gfar_init_filer_table(priv);
1449
1450         /* Print out the device info */
1451         netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1452
1453         /* Even more device info helps when determining which kernel
1454          * provided which set of benchmarks.
1455          */
1456         netdev_info(dev, "Running with NAPI enabled\n");
1457         for (i = 0; i < priv->num_rx_queues; i++)
1458                 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1459                             i, priv->rx_queue[i]->rx_ring_size);
1460         for (i = 0; i < priv->num_tx_queues; i++)
1461                 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1462                             i, priv->tx_queue[i]->tx_ring_size);
1463
1464         return 0;
1465
1466 register_fail:
1467         unmap_group_regs(priv);
1468         gfar_free_rx_queues(priv);
1469         gfar_free_tx_queues(priv);
1470         of_node_put(priv->phy_node);
1471         of_node_put(priv->tbi_node);
1472         free_gfar_dev(priv);
1473         return err;
1474 }
1475
1476 static int gfar_remove(struct platform_device *ofdev)
1477 {
1478         struct gfar_private *priv = platform_get_drvdata(ofdev);
1479
1480         of_node_put(priv->phy_node);
1481         of_node_put(priv->tbi_node);
1482
1483         unregister_netdev(priv->ndev);
1484         unmap_group_regs(priv);
1485         gfar_free_rx_queues(priv);
1486         gfar_free_tx_queues(priv);
1487         free_gfar_dev(priv);
1488
1489         return 0;
1490 }
1491
1492 #ifdef CONFIG_PM
1493
1494 static int gfar_suspend(struct device *dev)
1495 {
1496         struct gfar_private *priv = dev_get_drvdata(dev);
1497         struct net_device *ndev = priv->ndev;
1498         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1499         unsigned long flags;
1500         u32 tempval;
1501
1502         int magic_packet = priv->wol_en &&
1503                            (priv->device_flags &
1504                             FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1505
1506         netif_device_detach(ndev);
1507
1508         if (netif_running(ndev)) {
1509
1510                 local_irq_save(flags);
1511                 lock_tx_qs(priv);
1512
1513                 gfar_halt_nodisable(priv);
1514
1515                 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1516                 tempval = gfar_read(&regs->maccfg1);
1517
1518                 tempval &= ~MACCFG1_TX_EN;
1519
1520                 if (!magic_packet)
1521                         tempval &= ~MACCFG1_RX_EN;
1522
1523                 gfar_write(&regs->maccfg1, tempval);
1524
1525                 unlock_tx_qs(priv);
1526                 local_irq_restore(flags);
1527
1528                 disable_napi(priv);
1529
1530                 if (magic_packet) {
1531                         /* Enable interrupt on Magic Packet */
1532                         gfar_write(&regs->imask, IMASK_MAG);
1533
1534                         /* Enable Magic Packet mode */
1535                         tempval = gfar_read(&regs->maccfg2);
1536                         tempval |= MACCFG2_MPEN;
1537                         gfar_write(&regs->maccfg2, tempval);
1538                 } else {
1539                         phy_stop(priv->phydev);
1540                 }
1541         }
1542
1543         return 0;
1544 }
1545
1546 static int gfar_resume(struct device *dev)
1547 {
1548         struct gfar_private *priv = dev_get_drvdata(dev);
1549         struct net_device *ndev = priv->ndev;
1550         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1551         unsigned long flags;
1552         u32 tempval;
1553         int magic_packet = priv->wol_en &&
1554                            (priv->device_flags &
1555                             FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1556
1557         if (!netif_running(ndev)) {
1558                 netif_device_attach(ndev);
1559                 return 0;
1560         }
1561
1562         if (!magic_packet && priv->phydev)
1563                 phy_start(priv->phydev);
1564
1565         /* Disable Magic Packet mode, in case something
1566          * else woke us up.
1567          */
1568         local_irq_save(flags);
1569         lock_tx_qs(priv);
1570
1571         tempval = gfar_read(&regs->maccfg2);
1572         tempval &= ~MACCFG2_MPEN;
1573         gfar_write(&regs->maccfg2, tempval);
1574
1575         gfar_start(priv);
1576
1577         unlock_tx_qs(priv);
1578         local_irq_restore(flags);
1579
1580         netif_device_attach(ndev);
1581
1582         enable_napi(priv);
1583
1584         return 0;
1585 }
1586
1587 static int gfar_restore(struct device *dev)
1588 {
1589         struct gfar_private *priv = dev_get_drvdata(dev);
1590         struct net_device *ndev = priv->ndev;
1591
1592         if (!netif_running(ndev)) {
1593                 netif_device_attach(ndev);
1594
1595                 return 0;
1596         }
1597
1598         if (gfar_init_bds(ndev)) {
1599                 free_skb_resources(priv);
1600                 return -ENOMEM;
1601         }
1602
1603         gfar_mac_reset(priv);
1604
1605         gfar_init_tx_rx_base(priv);
1606
1607         gfar_start(priv);
1608
1609         priv->oldlink = 0;
1610         priv->oldspeed = 0;
1611         priv->oldduplex = -1;
1612
1613         if (priv->phydev)
1614                 phy_start(priv->phydev);
1615
1616         netif_device_attach(ndev);
1617         enable_napi(priv);
1618
1619         return 0;
1620 }
1621
1622 static struct dev_pm_ops gfar_pm_ops = {
1623         .suspend = gfar_suspend,
1624         .resume = gfar_resume,
1625         .freeze = gfar_suspend,
1626         .thaw = gfar_resume,
1627         .restore = gfar_restore,
1628 };
1629
1630 #define GFAR_PM_OPS (&gfar_pm_ops)
1631
1632 #else
1633
1634 #define GFAR_PM_OPS NULL
1635
1636 #endif
1637
1638 /* Reads the controller's registers to determine what interface
1639  * connects it to the PHY.
1640  */
1641 static phy_interface_t gfar_get_interface(struct net_device *dev)
1642 {
1643         struct gfar_private *priv = netdev_priv(dev);
1644         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1645         u32 ecntrl;
1646
1647         ecntrl = gfar_read(&regs->ecntrl);
1648
1649         if (ecntrl & ECNTRL_SGMII_MODE)
1650                 return PHY_INTERFACE_MODE_SGMII;
1651
1652         if (ecntrl & ECNTRL_TBI_MODE) {
1653                 if (ecntrl & ECNTRL_REDUCED_MODE)
1654                         return PHY_INTERFACE_MODE_RTBI;
1655                 else
1656                         return PHY_INTERFACE_MODE_TBI;
1657         }
1658
1659         if (ecntrl & ECNTRL_REDUCED_MODE) {
1660                 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
1661                         return PHY_INTERFACE_MODE_RMII;
1662                 }
1663                 else {
1664                         phy_interface_t interface = priv->interface;
1665
1666                         /* This isn't autodetected right now, so it must
1667                          * be set by the device tree or platform code.
1668                          */
1669                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1670                                 return PHY_INTERFACE_MODE_RGMII_ID;
1671
1672                         return PHY_INTERFACE_MODE_RGMII;
1673                 }
1674         }
1675
1676         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1677                 return PHY_INTERFACE_MODE_GMII;
1678
1679         return PHY_INTERFACE_MODE_MII;
1680 }
1681
1682
1683 /* Initializes driver's PHY state, and attaches to the PHY.
1684  * Returns 0 on success.
1685  */
1686 static int init_phy(struct net_device *dev)
1687 {
1688         struct gfar_private *priv = netdev_priv(dev);
1689         uint gigabit_support =
1690                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1691                 GFAR_SUPPORTED_GBIT : 0;
1692         phy_interface_t interface;
1693
1694         priv->oldlink = 0;
1695         priv->oldspeed = 0;
1696         priv->oldduplex = -1;
1697
1698         interface = gfar_get_interface(dev);
1699
1700         priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1701                                       interface);
1702         if (!priv->phydev) {
1703                 dev_err(&dev->dev, "could not attach to PHY\n");
1704                 return -ENODEV;
1705         }
1706
1707         if (interface == PHY_INTERFACE_MODE_SGMII)
1708                 gfar_configure_serdes(dev);
1709
1710         /* Remove any features not supported by the controller */
1711         priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1712         priv->phydev->advertising = priv->phydev->supported;
1713
1714         /* Add support for flow control, but don't advertise it by default */
1715         priv->phydev->supported |= (SUPPORTED_Pause | SUPPORTED_Asym_Pause);
1716
1717         return 0;
1718 }
1719
1720 /* Initialize TBI PHY interface for communicating with the
1721  * SERDES lynx PHY on the chip.  We communicate with this PHY
1722  * through the MDIO bus on each controller, treating it as a
1723  * "normal" PHY at the address found in the TBIPA register.  We assume
1724  * that the TBIPA register is valid.  Either the MDIO bus code will set
1725  * it to a value that doesn't conflict with other PHYs on the bus, or the
1726  * value doesn't matter, as there are no other PHYs on the bus.
1727  */
1728 static void gfar_configure_serdes(struct net_device *dev)
1729 {
1730         struct gfar_private *priv = netdev_priv(dev);
1731         struct phy_device *tbiphy;
1732
1733         if (!priv->tbi_node) {
1734                 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1735                                     "device tree specify a tbi-handle\n");
1736                 return;
1737         }
1738
1739         tbiphy = of_phy_find_device(priv->tbi_node);
1740         if (!tbiphy) {
1741                 dev_err(&dev->dev, "error: Could not get TBI device\n");
1742                 return;
1743         }
1744
1745         /* If the link is already up, we must already be ok, and don't need to
1746          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
1747          * everything for us?  Resetting it takes the link down and requires
1748          * several seconds for it to come back.
1749          */
1750         if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
1751                 return;
1752
1753         /* Single clk mode, mii mode off(for serdes communication) */
1754         phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1755
1756         phy_write(tbiphy, MII_ADVERTISE,
1757                   ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1758                   ADVERTISE_1000XPSE_ASYM);
1759
1760         phy_write(tbiphy, MII_BMCR,
1761                   BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1762                   BMCR_SPEED1000);
1763 }
1764
1765 static int __gfar_is_rx_idle(struct gfar_private *priv)
1766 {
1767         u32 res;
1768
1769         /* Normaly TSEC should not hang on GRS commands, so we should
1770          * actually wait for IEVENT_GRSC flag.
1771          */
1772         if (!gfar_has_errata(priv, GFAR_ERRATA_A002))
1773                 return 0;
1774
1775         /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1776          * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1777          * and the Rx can be safely reset.
1778          */
1779         res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1780         res &= 0x7f807f80;
1781         if ((res & 0xffff) == (res >> 16))
1782                 return 1;
1783
1784         return 0;
1785 }
1786
1787 /* Halt the receive and transmit queues */
1788 static void gfar_halt_nodisable(struct gfar_private *priv)
1789 {
1790         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1791         u32 tempval;
1792         unsigned int timeout;
1793         int stopped;
1794
1795         gfar_ints_disable(priv);
1796
1797         if (gfar_is_dma_stopped(priv))
1798                 return;
1799
1800         /* Stop the DMA, and wait for it to stop */
1801         tempval = gfar_read(&regs->dmactrl);
1802         tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1803         gfar_write(&regs->dmactrl, tempval);
1804
1805 retry:
1806         timeout = 1000;
1807         while (!(stopped = gfar_is_dma_stopped(priv)) && timeout) {
1808                 cpu_relax();
1809                 timeout--;
1810         }
1811
1812         if (!timeout)
1813                 stopped = gfar_is_dma_stopped(priv);
1814
1815         if (!stopped && !gfar_is_rx_dma_stopped(priv) &&
1816             !__gfar_is_rx_idle(priv))
1817                 goto retry;
1818 }
1819
1820 /* Halt the receive and transmit queues */
1821 void gfar_halt(struct gfar_private *priv)
1822 {
1823         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1824         u32 tempval;
1825
1826         /* Dissable the Rx/Tx hw queues */
1827         gfar_write(&regs->rqueue, 0);
1828         gfar_write(&regs->tqueue, 0);
1829
1830         mdelay(10);
1831
1832         gfar_halt_nodisable(priv);
1833
1834         /* Disable Rx/Tx DMA */
1835         tempval = gfar_read(&regs->maccfg1);
1836         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1837         gfar_write(&regs->maccfg1, tempval);
1838 }
1839
1840 void stop_gfar(struct net_device *dev)
1841 {
1842         struct gfar_private *priv = netdev_priv(dev);
1843
1844         netif_tx_stop_all_queues(dev);
1845
1846         smp_mb__before_atomic();
1847         set_bit(GFAR_DOWN, &priv->state);
1848         smp_mb__after_atomic();
1849
1850         disable_napi(priv);
1851
1852         /* disable ints and gracefully shut down Rx/Tx DMA */
1853         gfar_halt(priv);
1854
1855         phy_stop(priv->phydev);
1856
1857         free_skb_resources(priv);
1858 }
1859
1860 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1861 {
1862         struct txbd8 *txbdp;
1863         struct gfar_private *priv = netdev_priv(tx_queue->dev);
1864         int i, j;
1865
1866         txbdp = tx_queue->tx_bd_base;
1867
1868         for (i = 0; i < tx_queue->tx_ring_size; i++) {
1869                 if (!tx_queue->tx_skbuff[i])
1870                         continue;
1871
1872                 dma_unmap_single(priv->dev, txbdp->bufPtr,
1873                                  txbdp->length, DMA_TO_DEVICE);
1874                 txbdp->lstatus = 0;
1875                 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1876                      j++) {
1877                         txbdp++;
1878                         dma_unmap_page(priv->dev, txbdp->bufPtr,
1879                                        txbdp->length, DMA_TO_DEVICE);
1880                 }
1881                 txbdp++;
1882                 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1883                 tx_queue->tx_skbuff[i] = NULL;
1884         }
1885         kfree(tx_queue->tx_skbuff);
1886         tx_queue->tx_skbuff = NULL;
1887 }
1888
1889 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1890 {
1891         struct rxbd8 *rxbdp;
1892         struct gfar_private *priv = netdev_priv(rx_queue->dev);
1893         int i;
1894
1895         rxbdp = rx_queue->rx_bd_base;
1896
1897         for (i = 0; i < rx_queue->rx_ring_size; i++) {
1898                 if (rx_queue->rx_skbuff[i]) {
1899                         dma_unmap_single(priv->dev, rxbdp->bufPtr,
1900                                          priv->rx_buffer_size,
1901                                          DMA_FROM_DEVICE);
1902                         dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1903                         rx_queue->rx_skbuff[i] = NULL;
1904                 }
1905                 rxbdp->lstatus = 0;
1906                 rxbdp->bufPtr = 0;
1907                 rxbdp++;
1908         }
1909         kfree(rx_queue->rx_skbuff);
1910         rx_queue->rx_skbuff = NULL;
1911 }
1912
1913 /* If there are any tx skbs or rx skbs still around, free them.
1914  * Then free tx_skbuff and rx_skbuff
1915  */
1916 static void free_skb_resources(struct gfar_private *priv)
1917 {
1918         struct gfar_priv_tx_q *tx_queue = NULL;
1919         struct gfar_priv_rx_q *rx_queue = NULL;
1920         int i;
1921
1922         /* Go through all the buffer descriptors and free their data buffers */
1923         for (i = 0; i < priv->num_tx_queues; i++) {
1924                 struct netdev_queue *txq;
1925
1926                 tx_queue = priv->tx_queue[i];
1927                 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
1928                 if (tx_queue->tx_skbuff)
1929                         free_skb_tx_queue(tx_queue);
1930                 netdev_tx_reset_queue(txq);
1931         }
1932
1933         for (i = 0; i < priv->num_rx_queues; i++) {
1934                 rx_queue = priv->rx_queue[i];
1935                 if (rx_queue->rx_skbuff)
1936                         free_skb_rx_queue(rx_queue);
1937         }
1938
1939         dma_free_coherent(priv->dev,
1940                           sizeof(struct txbd8) * priv->total_tx_ring_size +
1941                           sizeof(struct rxbd8) * priv->total_rx_ring_size,
1942                           priv->tx_queue[0]->tx_bd_base,
1943                           priv->tx_queue[0]->tx_bd_dma_base);
1944 }
1945
1946 void gfar_start(struct gfar_private *priv)
1947 {
1948         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1949         u32 tempval;
1950         int i = 0;
1951
1952         /* Enable Rx/Tx hw queues */
1953         gfar_write(&regs->rqueue, priv->rqueue);
1954         gfar_write(&regs->tqueue, priv->tqueue);
1955
1956         /* Initialize DMACTRL to have WWR and WOP */
1957         tempval = gfar_read(&regs->dmactrl);
1958         tempval |= DMACTRL_INIT_SETTINGS;
1959         gfar_write(&regs->dmactrl, tempval);
1960
1961         /* Make sure we aren't stopped */
1962         tempval = gfar_read(&regs->dmactrl);
1963         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1964         gfar_write(&regs->dmactrl, tempval);
1965
1966         for (i = 0; i < priv->num_grps; i++) {
1967                 regs = priv->gfargrp[i].regs;
1968                 /* Clear THLT/RHLT, so that the DMA starts polling now */
1969                 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1970                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1971         }
1972
1973         /* Enable Rx/Tx DMA */
1974         tempval = gfar_read(&regs->maccfg1);
1975         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1976         gfar_write(&regs->maccfg1, tempval);
1977
1978         gfar_ints_enable(priv);
1979
1980         priv->ndev->trans_start = jiffies; /* prevent tx timeout */
1981 }
1982
1983 static void free_grp_irqs(struct gfar_priv_grp *grp)
1984 {
1985         free_irq(gfar_irq(grp, TX)->irq, grp);
1986         free_irq(gfar_irq(grp, RX)->irq, grp);
1987         free_irq(gfar_irq(grp, ER)->irq, grp);
1988 }
1989
1990 static int register_grp_irqs(struct gfar_priv_grp *grp)
1991 {
1992         struct gfar_private *priv = grp->priv;
1993         struct net_device *dev = priv->ndev;
1994         int err;
1995
1996         /* If the device has multiple interrupts, register for
1997          * them.  Otherwise, only register for the one
1998          */
1999         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2000                 /* Install our interrupt handlers for Error,
2001                  * Transmit, and Receive
2002                  */
2003                 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
2004                                   gfar_irq(grp, ER)->name, grp);
2005                 if (err < 0) {
2006                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2007                                   gfar_irq(grp, ER)->irq);
2008
2009                         goto err_irq_fail;
2010                 }
2011                 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
2012                                   gfar_irq(grp, TX)->name, grp);
2013                 if (err < 0) {
2014                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2015                                   gfar_irq(grp, TX)->irq);
2016                         goto tx_irq_fail;
2017                 }
2018                 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
2019                                   gfar_irq(grp, RX)->name, grp);
2020                 if (err < 0) {
2021                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2022                                   gfar_irq(grp, RX)->irq);
2023                         goto rx_irq_fail;
2024                 }
2025         } else {
2026                 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
2027                                   gfar_irq(grp, TX)->name, grp);
2028                 if (err < 0) {
2029                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2030                                   gfar_irq(grp, TX)->irq);
2031                         goto err_irq_fail;
2032                 }
2033         }
2034
2035         return 0;
2036
2037 rx_irq_fail:
2038         free_irq(gfar_irq(grp, TX)->irq, grp);
2039 tx_irq_fail:
2040         free_irq(gfar_irq(grp, ER)->irq, grp);
2041 err_irq_fail:
2042         return err;
2043
2044 }
2045
2046 static void gfar_free_irq(struct gfar_private *priv)
2047 {
2048         int i;
2049
2050         /* Free the IRQs */
2051         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2052                 for (i = 0; i < priv->num_grps; i++)
2053                         free_grp_irqs(&priv->gfargrp[i]);
2054         } else {
2055                 for (i = 0; i < priv->num_grps; i++)
2056                         free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
2057                                  &priv->gfargrp[i]);
2058         }
2059 }
2060
2061 static int gfar_request_irq(struct gfar_private *priv)
2062 {
2063         int err, i, j;
2064
2065         for (i = 0; i < priv->num_grps; i++) {
2066                 err = register_grp_irqs(&priv->gfargrp[i]);
2067                 if (err) {
2068                         for (j = 0; j < i; j++)
2069                                 free_grp_irqs(&priv->gfargrp[j]);
2070                         return err;
2071                 }
2072         }
2073
2074         return 0;
2075 }
2076
2077 /* Bring the controller up and running */
2078 int startup_gfar(struct net_device *ndev)
2079 {
2080         struct gfar_private *priv = netdev_priv(ndev);
2081         int err;
2082
2083         gfar_mac_reset(priv);
2084
2085         err = gfar_alloc_skb_resources(ndev);
2086         if (err)
2087                 return err;
2088
2089         gfar_init_tx_rx_base(priv);
2090
2091         smp_mb__before_atomic();
2092         clear_bit(GFAR_DOWN, &priv->state);
2093         smp_mb__after_atomic();
2094
2095         /* Start Rx/Tx DMA and enable the interrupts */
2096         gfar_start(priv);
2097
2098         phy_start(priv->phydev);
2099
2100         enable_napi(priv);
2101
2102         netif_tx_wake_all_queues(ndev);
2103
2104         return 0;
2105 }
2106
2107 /* Called when something needs to use the ethernet device
2108  * Returns 0 for success.
2109  */
2110 static int gfar_enet_open(struct net_device *dev)
2111 {
2112         struct gfar_private *priv = netdev_priv(dev);
2113         int err;
2114
2115         err = init_phy(dev);
2116         if (err)
2117                 return err;
2118
2119         err = gfar_request_irq(priv);
2120         if (err)
2121                 return err;
2122
2123         err = startup_gfar(dev);
2124         if (err)
2125                 return err;
2126
2127         device_set_wakeup_enable(&dev->dev, priv->wol_en);
2128
2129         return err;
2130 }
2131
2132 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
2133 {
2134         struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
2135
2136         memset(fcb, 0, GMAC_FCB_LEN);
2137
2138         return fcb;
2139 }
2140
2141 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
2142                                     int fcb_length)
2143 {
2144         /* If we're here, it's a IP packet with a TCP or UDP
2145          * payload.  We set it to checksum, using a pseudo-header
2146          * we provide
2147          */
2148         u8 flags = TXFCB_DEFAULT;
2149
2150         /* Tell the controller what the protocol is
2151          * And provide the already calculated phcs
2152          */
2153         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
2154                 flags |= TXFCB_UDP;
2155                 fcb->phcs = udp_hdr(skb)->check;
2156         } else
2157                 fcb->phcs = tcp_hdr(skb)->check;
2158
2159         /* l3os is the distance between the start of the
2160          * frame (skb->data) and the start of the IP hdr.
2161          * l4os is the distance between the start of the
2162          * l3 hdr and the l4 hdr
2163          */
2164         fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length);
2165         fcb->l4os = skb_network_header_len(skb);
2166
2167         fcb->flags = flags;
2168 }
2169
2170 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2171 {
2172         fcb->flags |= TXFCB_VLN;
2173         fcb->vlctl = vlan_tx_tag_get(skb);
2174 }
2175
2176 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2177                                       struct txbd8 *base, int ring_size)
2178 {
2179         struct txbd8 *new_bd = bdp + stride;
2180
2181         return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2182 }
2183
2184 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2185                                       int ring_size)
2186 {
2187         return skip_txbd(bdp, 1, base, ring_size);
2188 }
2189
2190 /* eTSEC12: csum generation not supported for some fcb offsets */
2191 static inline bool gfar_csum_errata_12(struct gfar_private *priv,
2192                                        unsigned long fcb_addr)
2193 {
2194         return (gfar_has_errata(priv, GFAR_ERRATA_12) &&
2195                (fcb_addr % 0x20) > 0x18);
2196 }
2197
2198 /* eTSEC76: csum generation for frames larger than 2500 may
2199  * cause excess delays before start of transmission
2200  */
2201 static inline bool gfar_csum_errata_76(struct gfar_private *priv,
2202                                        unsigned int len)
2203 {
2204         return (gfar_has_errata(priv, GFAR_ERRATA_76) &&
2205                (len > 2500));
2206 }
2207
2208 /* This is called by the kernel when a frame is ready for transmission.
2209  * It is pointed to by the dev->hard_start_xmit function pointer
2210  */
2211 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2212 {
2213         struct gfar_private *priv = netdev_priv(dev);
2214         struct gfar_priv_tx_q *tx_queue = NULL;
2215         struct netdev_queue *txq;
2216         struct gfar __iomem *regs = NULL;
2217         struct txfcb *fcb = NULL;
2218         struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2219         u32 lstatus;
2220         int i, rq = 0;
2221         int do_tstamp, do_csum, do_vlan;
2222         u32 bufaddr;
2223         unsigned long flags;
2224         unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0;
2225
2226         rq = skb->queue_mapping;
2227         tx_queue = priv->tx_queue[rq];
2228         txq = netdev_get_tx_queue(dev, rq);
2229         base = tx_queue->tx_bd_base;
2230         regs = tx_queue->grp->regs;
2231
2232         do_csum = (CHECKSUM_PARTIAL == skb->ip_summed);
2233         do_vlan = vlan_tx_tag_present(skb);
2234         do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2235                     priv->hwts_tx_en;
2236
2237         if (do_csum || do_vlan)
2238                 fcb_len = GMAC_FCB_LEN;
2239
2240         /* check if time stamp should be generated */
2241         if (unlikely(do_tstamp))
2242                 fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2243
2244         /* make space for additional header when fcb is needed */
2245         if (fcb_len && unlikely(skb_headroom(skb) < fcb_len)) {
2246                 struct sk_buff *skb_new;
2247
2248                 skb_new = skb_realloc_headroom(skb, fcb_len);
2249                 if (!skb_new) {
2250                         dev->stats.tx_errors++;
2251                         dev_kfree_skb_any(skb);
2252                         return NETDEV_TX_OK;
2253                 }
2254
2255                 if (skb->sk)
2256                         skb_set_owner_w(skb_new, skb->sk);
2257                 dev_consume_skb_any(skb);
2258                 skb = skb_new;
2259         }
2260
2261         /* total number of fragments in the SKB */
2262         nr_frags = skb_shinfo(skb)->nr_frags;
2263
2264         /* calculate the required number of TxBDs for this skb */
2265         if (unlikely(do_tstamp))
2266                 nr_txbds = nr_frags + 2;
2267         else
2268                 nr_txbds = nr_frags + 1;
2269
2270         /* check if there is space to queue this packet */
2271         if (nr_txbds > tx_queue->num_txbdfree) {
2272                 /* no space, stop the queue */
2273                 netif_tx_stop_queue(txq);
2274                 dev->stats.tx_fifo_errors++;
2275                 return NETDEV_TX_BUSY;
2276         }
2277
2278         /* Update transmit stats */
2279         bytes_sent = skb->len;
2280         tx_queue->stats.tx_bytes += bytes_sent;
2281         /* keep Tx bytes on wire for BQL accounting */
2282         GFAR_CB(skb)->bytes_sent = bytes_sent;
2283         tx_queue->stats.tx_packets++;
2284
2285         txbdp = txbdp_start = tx_queue->cur_tx;
2286         lstatus = txbdp->lstatus;
2287
2288         /* Time stamp insertion requires one additional TxBD */
2289         if (unlikely(do_tstamp))
2290                 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2291                                                  tx_queue->tx_ring_size);
2292
2293         if (nr_frags == 0) {
2294                 if (unlikely(do_tstamp))
2295                         txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
2296                                                           TXBD_INTERRUPT);
2297                 else
2298                         lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2299         } else {
2300                 /* Place the fragment addresses and lengths into the TxBDs */
2301                 for (i = 0; i < nr_frags; i++) {
2302                         unsigned int frag_len;
2303                         /* Point at the next BD, wrapping as needed */
2304                         txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2305
2306                         frag_len = skb_shinfo(skb)->frags[i].size;
2307
2308                         lstatus = txbdp->lstatus | frag_len |
2309                                   BD_LFLAG(TXBD_READY);
2310
2311                         /* Handle the last BD specially */
2312                         if (i == nr_frags - 1)
2313                                 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2314
2315                         bufaddr = skb_frag_dma_map(priv->dev,
2316                                                    &skb_shinfo(skb)->frags[i],
2317                                                    0,
2318                                                    frag_len,
2319                                                    DMA_TO_DEVICE);
2320                         if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
2321                                 goto dma_map_err;
2322
2323                         /* set the TxBD length and buffer pointer */
2324                         txbdp->bufPtr = bufaddr;
2325                         txbdp->lstatus = lstatus;
2326                 }
2327
2328                 lstatus = txbdp_start->lstatus;
2329         }
2330
2331         /* Add TxPAL between FCB and frame if required */
2332         if (unlikely(do_tstamp)) {
2333                 skb_push(skb, GMAC_TXPAL_LEN);
2334                 memset(skb->data, 0, GMAC_TXPAL_LEN);
2335         }
2336
2337         /* Add TxFCB if required */
2338         if (fcb_len) {
2339                 fcb = gfar_add_fcb(skb);
2340                 lstatus |= BD_LFLAG(TXBD_TOE);
2341         }
2342
2343         /* Set up checksumming */
2344         if (do_csum) {
2345                 gfar_tx_checksum(skb, fcb, fcb_len);
2346
2347                 if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) ||
2348                     unlikely(gfar_csum_errata_76(priv, skb->len))) {
2349                         __skb_pull(skb, GMAC_FCB_LEN);
2350                         skb_checksum_help(skb);
2351                         if (do_vlan || do_tstamp) {
2352                                 /* put back a new fcb for vlan/tstamp TOE */
2353                                 fcb = gfar_add_fcb(skb);
2354                         } else {
2355                                 /* Tx TOE not used */
2356                                 lstatus &= ~(BD_LFLAG(TXBD_TOE));
2357                                 fcb = NULL;
2358                         }
2359                 }
2360         }
2361
2362         if (do_vlan)
2363                 gfar_tx_vlan(skb, fcb);
2364
2365         /* Setup tx hardware time stamping if requested */
2366         if (unlikely(do_tstamp)) {
2367                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2368                 fcb->ptp = 1;
2369         }
2370
2371         bufaddr = dma_map_single(priv->dev, skb->data, skb_headlen(skb),
2372                                  DMA_TO_DEVICE);
2373         if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
2374                 goto dma_map_err;
2375
2376         txbdp_start->bufPtr = bufaddr;
2377
2378         /* If time stamping is requested one additional TxBD must be set up. The
2379          * first TxBD points to the FCB and must have a data length of
2380          * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2381          * the full frame length.
2382          */
2383         if (unlikely(do_tstamp)) {
2384                 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_len;
2385                 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
2386                                          (skb_headlen(skb) - fcb_len);
2387                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2388         } else {
2389                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2390         }
2391
2392         netdev_tx_sent_queue(txq, bytes_sent);
2393
2394         /* We can work in parallel with gfar_clean_tx_ring(), except
2395          * when modifying num_txbdfree. Note that we didn't grab the lock
2396          * when we were reading the num_txbdfree and checking for available
2397          * space, that's because outside of this function it can only grow,
2398          * and once we've got needed space, it cannot suddenly disappear.
2399          *
2400          * The lock also protects us from gfar_error(), which can modify
2401          * regs->tstat and thus retrigger the transfers, which is why we
2402          * also must grab the lock before setting ready bit for the first
2403          * to be transmitted BD.
2404          */
2405         spin_lock_irqsave(&tx_queue->txlock, flags);
2406
2407         gfar_wmb();
2408
2409         txbdp_start->lstatus = lstatus;
2410
2411         gfar_wmb(); /* force lstatus write before tx_skbuff */
2412
2413         tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2414
2415         /* Update the current skb pointer to the next entry we will use
2416          * (wrapping if necessary)
2417          */
2418         tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2419                               TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2420
2421         tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2422
2423         /* reduce TxBD free count */
2424         tx_queue->num_txbdfree -= (nr_txbds);
2425
2426         /* If the next BD still needs to be cleaned up, then the bds
2427          * are full.  We need to tell the kernel to stop sending us stuff.
2428          */
2429         if (!tx_queue->num_txbdfree) {
2430                 netif_tx_stop_queue(txq);
2431
2432                 dev->stats.tx_fifo_errors++;
2433         }
2434
2435         /* Tell the DMA to go go go */
2436         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2437
2438         /* Unlock priv */
2439         spin_unlock_irqrestore(&tx_queue->txlock, flags);
2440
2441         return NETDEV_TX_OK;
2442
2443 dma_map_err:
2444         txbdp = next_txbd(txbdp_start, base, tx_queue->tx_ring_size);
2445         if (do_tstamp)
2446                 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2447         for (i = 0; i < nr_frags; i++) {
2448                 lstatus = txbdp->lstatus;
2449                 if (!(lstatus & BD_LFLAG(TXBD_READY)))
2450                         break;
2451
2452                 txbdp->lstatus = lstatus & ~BD_LFLAG(TXBD_READY);
2453                 bufaddr = txbdp->bufPtr;
2454                 dma_unmap_page(priv->dev, bufaddr, txbdp->length,
2455                                DMA_TO_DEVICE);
2456                 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2457         }
2458         gfar_wmb();
2459         dev_kfree_skb_any(skb);
2460         return NETDEV_TX_OK;
2461 }
2462
2463 /* Stops the kernel queue, and halts the controller */
2464 static int gfar_close(struct net_device *dev)
2465 {
2466         struct gfar_private *priv = netdev_priv(dev);
2467
2468         cancel_work_sync(&priv->reset_task);
2469         stop_gfar(dev);
2470
2471         /* Disconnect from the PHY */
2472         phy_disconnect(priv->phydev);
2473         priv->phydev = NULL;
2474
2475         gfar_free_irq(priv);
2476
2477         return 0;
2478 }
2479
2480 /* Changes the mac address if the controller is not running. */
2481 static int gfar_set_mac_address(struct net_device *dev)
2482 {
2483         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2484
2485         return 0;
2486 }
2487
2488 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2489 {
2490         struct gfar_private *priv = netdev_priv(dev);
2491         int frame_size = new_mtu + ETH_HLEN;
2492
2493         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
2494                 netif_err(priv, drv, dev, "Invalid MTU setting\n");
2495                 return -EINVAL;
2496         }
2497
2498         while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2499                 cpu_relax();
2500
2501         if (dev->flags & IFF_UP)
2502                 stop_gfar(dev);
2503
2504         dev->mtu = new_mtu;
2505
2506         if (dev->flags & IFF_UP)
2507                 startup_gfar(dev);
2508
2509         clear_bit_unlock(GFAR_RESETTING, &priv->state);
2510
2511         return 0;
2512 }
2513
2514 void reset_gfar(struct net_device *ndev)
2515 {
2516         struct gfar_private *priv = netdev_priv(ndev);
2517
2518         while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2519                 cpu_relax();
2520
2521         stop_gfar(ndev);
2522         startup_gfar(ndev);
2523
2524         clear_bit_unlock(GFAR_RESETTING, &priv->state);
2525 }
2526
2527 /* gfar_reset_task gets scheduled when a packet has not been
2528  * transmitted after a set amount of time.
2529  * For now, assume that clearing out all the structures, and
2530  * starting over will fix the problem.
2531  */
2532 static void gfar_reset_task(struct work_struct *work)
2533 {
2534         struct gfar_private *priv = container_of(work, struct gfar_private,
2535                                                  reset_task);
2536         reset_gfar(priv->ndev);
2537 }
2538
2539 static void gfar_timeout(struct net_device *dev)
2540 {
2541         struct gfar_private *priv = netdev_priv(dev);
2542
2543         dev->stats.tx_errors++;
2544         schedule_work(&priv->reset_task);
2545 }
2546
2547 static void gfar_align_skb(struct sk_buff *skb)
2548 {
2549         /* We need the data buffer to be aligned properly.  We will reserve
2550          * as many bytes as needed to align the data properly
2551          */
2552         skb_reserve(skb, RXBUF_ALIGNMENT -
2553                     (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
2554 }
2555
2556 /* Interrupt Handler for Transmit complete */
2557 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2558 {
2559         struct net_device *dev = tx_queue->dev;
2560         struct netdev_queue *txq;
2561         struct gfar_private *priv = netdev_priv(dev);
2562         struct txbd8 *bdp, *next = NULL;
2563         struct txbd8 *lbdp = NULL;
2564         struct txbd8 *base = tx_queue->tx_bd_base;
2565         struct sk_buff *skb;
2566         int skb_dirtytx;
2567         int tx_ring_size = tx_queue->tx_ring_size;
2568         int frags = 0, nr_txbds = 0;
2569         int i;
2570         int howmany = 0;
2571         int tqi = tx_queue->qindex;
2572         unsigned int bytes_sent = 0;
2573         u32 lstatus;
2574         size_t buflen;
2575
2576         txq = netdev_get_tx_queue(dev, tqi);
2577         bdp = tx_queue->dirty_tx;
2578         skb_dirtytx = tx_queue->skb_dirtytx;
2579
2580         while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2581                 unsigned long flags;
2582
2583                 frags = skb_shinfo(skb)->nr_frags;
2584
2585                 /* When time stamping, one additional TxBD must be freed.
2586                  * Also, we need to dma_unmap_single() the TxPAL.
2587                  */
2588                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2589                         nr_txbds = frags + 2;
2590                 else
2591                         nr_txbds = frags + 1;
2592
2593                 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2594
2595                 lstatus = lbdp->lstatus;
2596
2597                 /* Only clean completed frames */
2598                 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2599                     (lstatus & BD_LENGTH_MASK))
2600                         break;
2601
2602                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2603                         next = next_txbd(bdp, base, tx_ring_size);
2604                         buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2605                 } else
2606                         buflen = bdp->length;
2607
2608                 dma_unmap_single(priv->dev, bdp->bufPtr,
2609                                  buflen, DMA_TO_DEVICE);
2610
2611                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2612                         struct skb_shared_hwtstamps shhwtstamps;
2613                         u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
2614
2615                         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2616                         shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2617                         skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2618                         skb_tstamp_tx(skb, &shhwtstamps);
2619                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2620                         bdp = next;
2621                 }
2622
2623                 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2624                 bdp = next_txbd(bdp, base, tx_ring_size);
2625
2626                 for (i = 0; i < frags; i++) {
2627                         dma_unmap_page(priv->dev, bdp->bufPtr,
2628                                        bdp->length, DMA_TO_DEVICE);
2629                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2630                         bdp = next_txbd(bdp, base, tx_ring_size);
2631                 }
2632
2633                 bytes_sent += GFAR_CB(skb)->bytes_sent;
2634
2635                 dev_kfree_skb_any(skb);
2636
2637                 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2638
2639                 skb_dirtytx = (skb_dirtytx + 1) &
2640                               TX_RING_MOD_MASK(tx_ring_size);
2641
2642                 howmany++;
2643                 spin_lock_irqsave(&tx_queue->txlock, flags);
2644                 tx_queue->num_txbdfree += nr_txbds;
2645                 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2646         }
2647
2648         /* If we freed a buffer, we can restart transmission, if necessary */
2649         if (tx_queue->num_txbdfree &&
2650             netif_tx_queue_stopped(txq) &&
2651             !(test_bit(GFAR_DOWN, &priv->state)))
2652                 netif_wake_subqueue(priv->ndev, tqi);
2653
2654         /* Update dirty indicators */
2655         tx_queue->skb_dirtytx = skb_dirtytx;
2656         tx_queue->dirty_tx = bdp;
2657
2658         netdev_tx_completed_queue(txq, howmany, bytes_sent);
2659 }
2660
2661 static struct sk_buff *gfar_alloc_skb(struct net_device *dev)
2662 {
2663         struct gfar_private *priv = netdev_priv(dev);
2664         struct sk_buff *skb;
2665
2666         skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
2667         if (!skb)
2668                 return NULL;
2669
2670         gfar_align_skb(skb);
2671
2672         return skb;
2673 }
2674
2675 static struct sk_buff *gfar_new_skb(struct net_device *dev, dma_addr_t *bufaddr)
2676 {
2677         struct gfar_private *priv = netdev_priv(dev);
2678         struct sk_buff *skb;
2679         dma_addr_t addr;
2680
2681         skb = gfar_alloc_skb(dev);
2682         if (!skb)
2683                 return NULL;
2684
2685         addr = dma_map_single(priv->dev, skb->data,
2686                               priv->rx_buffer_size, DMA_FROM_DEVICE);
2687         if (unlikely(dma_mapping_error(priv->dev, addr))) {
2688                 dev_kfree_skb_any(skb);
2689                 return NULL;
2690         }
2691
2692         *bufaddr = addr;
2693         return skb;
2694 }
2695
2696 static inline void count_errors(unsigned short status, struct net_device *dev)
2697 {
2698         struct gfar_private *priv = netdev_priv(dev);
2699         struct net_device_stats *stats = &dev->stats;
2700         struct gfar_extra_stats *estats = &priv->extra_stats;
2701
2702         /* If the packet was truncated, none of the other errors matter */
2703         if (status & RXBD_TRUNCATED) {
2704                 stats->rx_length_errors++;
2705
2706                 atomic64_inc(&estats->rx_trunc);
2707
2708                 return;
2709         }
2710         /* Count the errors, if there were any */
2711         if (status & (RXBD_LARGE | RXBD_SHORT)) {
2712                 stats->rx_length_errors++;
2713
2714                 if (status & RXBD_LARGE)
2715                         atomic64_inc(&estats->rx_large);
2716                 else
2717                         atomic64_inc(&estats->rx_short);
2718         }
2719         if (status & RXBD_NONOCTET) {
2720                 stats->rx_frame_errors++;
2721                 atomic64_inc(&estats->rx_nonoctet);
2722         }
2723         if (status & RXBD_CRCERR) {
2724                 atomic64_inc(&estats->rx_crcerr);
2725                 stats->rx_crc_errors++;
2726         }
2727         if (status & RXBD_OVERRUN) {
2728                 atomic64_inc(&estats->rx_overrun);
2729                 stats->rx_crc_errors++;
2730         }
2731 }
2732
2733 irqreturn_t gfar_receive(int irq, void *grp_id)
2734 {
2735         struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2736         unsigned long flags;
2737         u32 imask;
2738
2739         if (likely(napi_schedule_prep(&grp->napi_rx))) {
2740                 spin_lock_irqsave(&grp->grplock, flags);
2741                 imask = gfar_read(&grp->regs->imask);
2742                 imask &= IMASK_RX_DISABLED;
2743                 gfar_write(&grp->regs->imask, imask);
2744                 spin_unlock_irqrestore(&grp->grplock, flags);
2745                 __napi_schedule(&grp->napi_rx);
2746         } else {
2747                 /* Clear IEVENT, so interrupts aren't called again
2748                  * because of the packets that have already arrived.
2749                  */
2750                 gfar_write(&grp->regs->ievent, IEVENT_RX_MASK);
2751         }
2752
2753         return IRQ_HANDLED;
2754 }
2755
2756 /* Interrupt Handler for Transmit complete */
2757 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2758 {
2759         struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2760         unsigned long flags;
2761         u32 imask;
2762
2763         if (likely(napi_schedule_prep(&grp->napi_tx))) {
2764                 spin_lock_irqsave(&grp->grplock, flags);
2765                 imask = gfar_read(&grp->regs->imask);
2766                 imask &= IMASK_TX_DISABLED;
2767                 gfar_write(&grp->regs->imask, imask);
2768                 spin_unlock_irqrestore(&grp->grplock, flags);
2769                 __napi_schedule(&grp->napi_tx);
2770         } else {
2771                 /* Clear IEVENT, so interrupts aren't called again
2772                  * because of the packets that have already arrived.
2773                  */
2774                 gfar_write(&grp->regs->ievent, IEVENT_TX_MASK);
2775         }
2776
2777         return IRQ_HANDLED;
2778 }
2779
2780 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2781 {
2782         /* If valid headers were found, and valid sums
2783          * were verified, then we tell the kernel that no
2784          * checksumming is necessary.  Otherwise, it is [FIXME]
2785          */
2786         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
2787                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2788         else
2789                 skb_checksum_none_assert(skb);
2790 }
2791
2792
2793 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
2794 static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2795                                int amount_pull, struct napi_struct *napi)
2796 {
2797         struct gfar_private *priv = netdev_priv(dev);
2798         struct rxfcb *fcb = NULL;
2799
2800         /* fcb is at the beginning if exists */
2801         fcb = (struct rxfcb *)skb->data;
2802
2803         /* Remove the FCB from the skb
2804          * Remove the padded bytes, if there are any
2805          */
2806         if (amount_pull) {
2807                 skb_record_rx_queue(skb, fcb->rq);
2808                 skb_pull(skb, amount_pull);
2809         }
2810
2811         /* Get receive timestamp from the skb */
2812         if (priv->hwts_rx_en) {
2813                 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2814                 u64 *ns = (u64 *) skb->data;
2815
2816                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2817                 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2818         }
2819
2820         if (priv->padding)
2821                 skb_pull(skb, priv->padding);
2822
2823         if (dev->features & NETIF_F_RXCSUM)
2824                 gfar_rx_checksum(skb, fcb);
2825
2826         /* Tell the skb what kind of packet this is */
2827         skb->protocol = eth_type_trans(skb, dev);
2828
2829         /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here.
2830          * Even if vlan rx accel is disabled, on some chips
2831          * RXFCB_VLN is pseudo randomly set.
2832          */
2833         if (dev->features & NETIF_F_HW_VLAN_CTAG_RX &&
2834             fcb->flags & RXFCB_VLN)
2835                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), fcb->vlctl);
2836
2837         /* Send the packet up the stack */
2838         napi_gro_receive(napi, skb);
2839
2840 }
2841
2842 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2843  * until the budget/quota has been reached. Returns the number
2844  * of frames handled
2845  */
2846 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
2847 {
2848         struct net_device *dev = rx_queue->dev;
2849         struct rxbd8 *bdp, *base;
2850         struct sk_buff *skb;
2851         int pkt_len;
2852         int amount_pull;
2853         int howmany = 0;
2854         struct gfar_private *priv = netdev_priv(dev);
2855
2856         /* Get the first full descriptor */
2857         bdp = rx_queue->cur_rx;
2858         base = rx_queue->rx_bd_base;
2859
2860         amount_pull = priv->uses_rxfcb ? GMAC_FCB_LEN : 0;
2861
2862         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
2863                 struct sk_buff *newskb;
2864                 dma_addr_t bufaddr;
2865
2866                 rmb();
2867
2868                 /* Add another skb for the future */
2869                 newskb = gfar_new_skb(dev, &bufaddr);
2870
2871                 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
2872
2873                 dma_unmap_single(priv->dev, bdp->bufPtr,
2874                                  priv->rx_buffer_size, DMA_FROM_DEVICE);
2875
2876                 if (unlikely(!(bdp->status & RXBD_ERR) &&
2877                              bdp->length > priv->rx_buffer_size))
2878                         bdp->status = RXBD_LARGE;
2879
2880                 /* We drop the frame if we failed to allocate a new buffer */
2881                 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2882                              bdp->status & RXBD_ERR)) {
2883                         count_errors(bdp->status, dev);
2884
2885                         if (unlikely(!newskb)) {
2886                                 newskb = skb;
2887                                 bufaddr = bdp->bufPtr;
2888                         } else if (skb)
2889                                 dev_kfree_skb(skb);
2890                 } else {
2891                         /* Increment the number of packets */
2892                         rx_queue->stats.rx_packets++;
2893                         howmany++;
2894
2895                         if (likely(skb)) {
2896                                 pkt_len = bdp->length - ETH_FCS_LEN;
2897                                 /* Remove the FCS from the packet length */
2898                                 skb_put(skb, pkt_len);
2899                                 rx_queue->stats.rx_bytes += pkt_len;
2900                                 skb_record_rx_queue(skb, rx_queue->qindex);
2901                                 gfar_process_frame(dev, skb, amount_pull,
2902                                                    &rx_queue->grp->napi_rx);
2903
2904                         } else {
2905                                 netif_warn(priv, rx_err, dev, "Missing skb!\n");
2906                                 rx_queue->stats.rx_dropped++;
2907                                 atomic64_inc(&priv->extra_stats.rx_skbmissing);
2908                         }
2909
2910                 }
2911
2912                 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
2913
2914                 /* Setup the new bdp */
2915                 gfar_init_rxbdp(rx_queue, bdp, bufaddr);
2916
2917                 /* Update Last Free RxBD pointer for LFC */
2918                 if (unlikely(rx_queue->rfbptr && priv->tx_actual_en))
2919                         gfar_write(rx_queue->rfbptr, (u32)bdp);
2920
2921                 /* Update to the next pointer */
2922                 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
2923
2924                 /* update to point at the next skb */
2925                 rx_queue->skb_currx = (rx_queue->skb_currx + 1) &
2926                                       RX_RING_MOD_MASK(rx_queue->rx_ring_size);
2927         }
2928
2929         /* Update the current rxbd pointer to be the next one */
2930         rx_queue->cur_rx = bdp;
2931
2932         return howmany;
2933 }
2934
2935 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget)
2936 {
2937         struct gfar_priv_grp *gfargrp =
2938                 container_of(napi, struct gfar_priv_grp, napi_rx);
2939         struct gfar __iomem *regs = gfargrp->regs;
2940         struct gfar_priv_rx_q *rx_queue = gfargrp->rx_queue;
2941         int work_done = 0;
2942
2943         /* Clear IEVENT, so interrupts aren't called again
2944          * because of the packets that have already arrived
2945          */
2946         gfar_write(&regs->ievent, IEVENT_RX_MASK);
2947
2948         work_done = gfar_clean_rx_ring(rx_queue, budget);
2949
2950         if (work_done < budget) {
2951                 u32 imask;
2952                 napi_complete(napi);
2953                 /* Clear the halt bit in RSTAT */
2954                 gfar_write(&regs->rstat, gfargrp->rstat);
2955
2956                 spin_lock_irq(&gfargrp->grplock);
2957                 imask = gfar_read(&regs->imask);
2958                 imask |= IMASK_RX_DEFAULT;
2959                 gfar_write(&regs->imask, imask);
2960                 spin_unlock_irq(&gfargrp->grplock);
2961         }
2962
2963         return work_done;
2964 }
2965
2966 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget)
2967 {
2968         struct gfar_priv_grp *gfargrp =
2969                 container_of(napi, struct gfar_priv_grp, napi_tx);
2970         struct gfar __iomem *regs = gfargrp->regs;
2971         struct gfar_priv_tx_q *tx_queue = gfargrp->tx_queue;
2972         u32 imask;
2973
2974         /* Clear IEVENT, so interrupts aren't called again
2975          * because of the packets that have already arrived
2976          */
2977         gfar_write(&regs->ievent, IEVENT_TX_MASK);
2978
2979         /* run Tx cleanup to completion */
2980         if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx])
2981                 gfar_clean_tx_ring(tx_queue);
2982
2983         napi_complete(napi);
2984
2985         spin_lock_irq(&gfargrp->grplock);
2986         imask = gfar_read(&regs->imask);
2987         imask |= IMASK_TX_DEFAULT;
2988         gfar_write(&regs->imask, imask);
2989         spin_unlock_irq(&gfargrp->grplock);
2990
2991         return 0;
2992 }
2993
2994 static int gfar_poll_rx(struct napi_struct *napi, int budget)
2995 {
2996         struct gfar_priv_grp *gfargrp =
2997                 container_of(napi, struct gfar_priv_grp, napi_rx);
2998         struct gfar_private *priv = gfargrp->priv;
2999         struct gfar __iomem *regs = gfargrp->regs;
3000         struct gfar_priv_rx_q *rx_queue = NULL;
3001         int work_done = 0, work_done_per_q = 0;
3002         int i, budget_per_q = 0;
3003         unsigned long rstat_rxf;
3004         int num_act_queues;
3005
3006         /* Clear IEVENT, so interrupts aren't called again
3007          * because of the packets that have already arrived
3008          */
3009         gfar_write(&regs->ievent, IEVENT_RX_MASK);
3010
3011         rstat_rxf = gfar_read(&regs->rstat) & RSTAT_RXF_MASK;
3012
3013         num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS);
3014         if (num_act_queues)
3015                 budget_per_q = budget/num_act_queues;
3016
3017         for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
3018                 /* skip queue if not active */
3019                 if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i)))
3020                         continue;
3021
3022                 rx_queue = priv->rx_queue[i];
3023                 work_done_per_q =
3024                         gfar_clean_rx_ring(rx_queue, budget_per_q);
3025                 work_done += work_done_per_q;
3026
3027                 /* finished processing this queue */
3028                 if (work_done_per_q < budget_per_q) {
3029                         /* clear active queue hw indication */
3030                         gfar_write(&regs->rstat,
3031                                    RSTAT_CLEAR_RXF0 >> i);
3032                         num_act_queues--;
3033
3034                         if (!num_act_queues)
3035                                 break;
3036                 }
3037         }
3038
3039         if (!num_act_queues) {
3040                 u32 imask;
3041                 napi_complete(napi);
3042
3043                 /* Clear the halt bit in RSTAT */
3044                 gfar_write(&regs->rstat, gfargrp->rstat);
3045
3046                 spin_lock_irq(&gfargrp->grplock);
3047                 imask = gfar_read(&regs->imask);
3048                 imask |= IMASK_RX_DEFAULT;
3049                 gfar_write(&regs->imask, imask);
3050                 spin_unlock_irq(&gfargrp->grplock);
3051         }
3052
3053         return work_done;
3054 }
3055
3056 static int gfar_poll_tx(struct napi_struct *napi, int budget)
3057 {
3058         struct gfar_priv_grp *gfargrp =
3059                 container_of(napi, struct gfar_priv_grp, napi_tx);
3060         struct gfar_private *priv = gfargrp->priv;
3061         struct gfar __iomem *regs = gfargrp->regs;
3062         struct gfar_priv_tx_q *tx_queue = NULL;
3063         int has_tx_work = 0;
3064         int i;
3065
3066         /* Clear IEVENT, so interrupts aren't called again
3067          * because of the packets that have already arrived
3068          */
3069         gfar_write(&regs->ievent, IEVENT_TX_MASK);
3070
3071         for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) {
3072                 tx_queue = priv->tx_queue[i];
3073                 /* run Tx cleanup to completion */
3074                 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) {
3075                         gfar_clean_tx_ring(tx_queue);
3076                         has_tx_work = 1;
3077                 }
3078         }
3079
3080         if (!has_tx_work) {
3081                 u32 imask;
3082                 napi_complete(napi);
3083
3084                 spin_lock_irq(&gfargrp->grplock);
3085                 imask = gfar_read(&regs->imask);
3086                 imask |= IMASK_TX_DEFAULT;
3087                 gfar_write(&regs->imask, imask);
3088                 spin_unlock_irq(&gfargrp->grplock);
3089         }
3090
3091         return 0;
3092 }
3093
3094
3095 #ifdef CONFIG_NET_POLL_CONTROLLER
3096 /* Polling 'interrupt' - used by things like netconsole to send skbs
3097  * without having to re-enable interrupts. It's not called while
3098  * the interrupt routine is executing.
3099  */
3100 static void gfar_netpoll(struct net_device *dev)
3101 {
3102         struct gfar_private *priv = netdev_priv(dev);
3103         int i;
3104
3105         /* If the device has multiple interrupts, run tx/rx */
3106         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
3107                 for (i = 0; i < priv->num_grps; i++) {
3108                         struct gfar_priv_grp *grp = &priv->gfargrp[i];
3109
3110                         disable_irq(gfar_irq(grp, TX)->irq);
3111                         disable_irq(gfar_irq(grp, RX)->irq);
3112                         disable_irq(gfar_irq(grp, ER)->irq);
3113                         gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3114                         enable_irq(gfar_irq(grp, ER)->irq);
3115                         enable_irq(gfar_irq(grp, RX)->irq);
3116                         enable_irq(gfar_irq(grp, TX)->irq);
3117                 }
3118         } else {
3119                 for (i = 0; i < priv->num_grps; i++) {
3120                         struct gfar_priv_grp *grp = &priv->gfargrp[i];
3121
3122                         disable_irq(gfar_irq(grp, TX)->irq);
3123                         gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3124                         enable_irq(gfar_irq(grp, TX)->irq);
3125                 }
3126         }
3127 }
3128 #endif
3129
3130 /* The interrupt handler for devices with one interrupt */
3131 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
3132 {
3133         struct gfar_priv_grp *gfargrp = grp_id;
3134
3135         /* Save ievent for future reference */
3136         u32 events = gfar_read(&gfargrp->regs->ievent);
3137
3138         /* Check for reception */
3139         if (events & IEVENT_RX_MASK)
3140                 gfar_receive(irq, grp_id);
3141
3142         /* Check for transmit completion */
3143         if (events & IEVENT_TX_MASK)
3144                 gfar_transmit(irq, grp_id);
3145
3146         /* Check for errors */
3147         if (events & IEVENT_ERR_MASK)
3148                 gfar_error(irq, grp_id);
3149
3150         return IRQ_HANDLED;
3151 }
3152
3153 /* Called every time the controller might need to be made
3154  * aware of new link state.  The PHY code conveys this
3155  * information through variables in the phydev structure, and this
3156  * function converts those variables into the appropriate
3157  * register values, and can bring down the device if needed.
3158  */
3159 static void adjust_link(struct net_device *dev)
3160 {
3161         struct gfar_private *priv = netdev_priv(dev);
3162         struct phy_device *phydev = priv->phydev;
3163
3164         if (unlikely(phydev->link != priv->oldlink ||
3165                      phydev->duplex != priv->oldduplex ||
3166                      phydev->speed != priv->oldspeed))
3167                 gfar_update_link_state(priv);
3168 }
3169
3170 /* Update the hash table based on the current list of multicast
3171  * addresses we subscribe to.  Also, change the promiscuity of
3172  * the device based on the flags (this function is called
3173  * whenever dev->flags is changed
3174  */
3175 static void gfar_set_multi(struct net_device *dev)
3176 {
3177         struct netdev_hw_addr *ha;
3178         struct gfar_private *priv = netdev_priv(dev);
3179         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3180         u32 tempval;
3181
3182         if (dev->flags & IFF_PROMISC) {
3183                 /* Set RCTRL to PROM */
3184                 tempval = gfar_read(&regs->rctrl);
3185                 tempval |= RCTRL_PROM;
3186                 gfar_write(&regs->rctrl, tempval);
3187         } else {
3188                 /* Set RCTRL to not PROM */
3189                 tempval = gfar_read(&regs->rctrl);
3190                 tempval &= ~(RCTRL_PROM);
3191                 gfar_write(&regs->rctrl, tempval);
3192         }
3193
3194         if (dev->flags & IFF_ALLMULTI) {
3195                 /* Set the hash to rx all multicast frames */
3196                 gfar_write(&regs->igaddr0, 0xffffffff);
3197                 gfar_write(&regs->igaddr1, 0xffffffff);
3198                 gfar_write(&regs->igaddr2, 0xffffffff);
3199                 gfar_write(&regs->igaddr3, 0xffffffff);
3200                 gfar_write(&regs->igaddr4, 0xffffffff);
3201                 gfar_write(&regs->igaddr5, 0xffffffff);
3202                 gfar_write(&regs->igaddr6, 0xffffffff);
3203                 gfar_write(&regs->igaddr7, 0xffffffff);
3204                 gfar_write(&regs->gaddr0, 0xffffffff);
3205                 gfar_write(&regs->gaddr1, 0xffffffff);
3206                 gfar_write(&regs->gaddr2, 0xffffffff);
3207                 gfar_write(&regs->gaddr3, 0xffffffff);
3208                 gfar_write(&regs->gaddr4, 0xffffffff);
3209                 gfar_write(&regs->gaddr5, 0xffffffff);
3210                 gfar_write(&regs->gaddr6, 0xffffffff);
3211                 gfar_write(&regs->gaddr7, 0xffffffff);
3212         } else {
3213                 int em_num;
3214                 int idx;
3215
3216                 /* zero out the hash */
3217                 gfar_write(&regs->igaddr0, 0x0);
3218                 gfar_write(&regs->igaddr1, 0x0);
3219                 gfar_write(&regs->igaddr2, 0x0);
3220                 gfar_write(&regs->igaddr3, 0x0);
3221                 gfar_write(&regs->igaddr4, 0x0);
3222                 gfar_write(&regs->igaddr5, 0x0);
3223                 gfar_write(&regs->igaddr6, 0x0);
3224                 gfar_write(&regs->igaddr7, 0x0);
3225                 gfar_write(&regs->gaddr0, 0x0);
3226                 gfar_write(&regs->gaddr1, 0x0);
3227                 gfar_write(&regs->gaddr2, 0x0);
3228                 gfar_write(&regs->gaddr3, 0x0);
3229                 gfar_write(&regs->gaddr4, 0x0);
3230                 gfar_write(&regs->gaddr5, 0x0);
3231                 gfar_write(&regs->gaddr6, 0x0);
3232                 gfar_write(&regs->gaddr7, 0x0);
3233
3234                 /* If we have extended hash tables, we need to
3235                  * clear the exact match registers to prepare for
3236                  * setting them
3237                  */
3238                 if (priv->extended_hash) {
3239                         em_num = GFAR_EM_NUM + 1;
3240                         gfar_clear_exact_match(dev);
3241                         idx = 1;
3242                 } else {
3243                         idx = 0;
3244                         em_num = 0;
3245                 }
3246
3247                 if (netdev_mc_empty(dev))
3248                         return;
3249
3250                 /* Parse the list, and set the appropriate bits */
3251                 netdev_for_each_mc_addr(ha, dev) {
3252                         if (idx < em_num) {
3253                                 gfar_set_mac_for_addr(dev, idx, ha->addr);
3254                                 idx++;
3255                         } else
3256                                 gfar_set_hash_for_addr(dev, ha->addr);
3257                 }
3258         }
3259 }
3260
3261
3262 /* Clears each of the exact match registers to zero, so they
3263  * don't interfere with normal reception
3264  */
3265 static void gfar_clear_exact_match(struct net_device *dev)
3266 {
3267         int idx;
3268         static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3269
3270         for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3271                 gfar_set_mac_for_addr(dev, idx, zero_arr);
3272 }
3273
3274 /* Set the appropriate hash bit for the given addr */
3275 /* The algorithm works like so:
3276  * 1) Take the Destination Address (ie the multicast address), and
3277  * do a CRC on it (little endian), and reverse the bits of the
3278  * result.
3279  * 2) Use the 8 most significant bits as a hash into a 256-entry
3280  * table.  The table is controlled through 8 32-bit registers:
3281  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
3282  * gaddr7.  This means that the 3 most significant bits in the
3283  * hash index which gaddr register to use, and the 5 other bits
3284  * indicate which bit (assuming an IBM numbering scheme, which
3285  * for PowerPC (tm) is usually the case) in the register holds
3286  * the entry.
3287  */
3288 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3289 {
3290         u32 tempval;
3291         struct gfar_private *priv = netdev_priv(dev);
3292         u32 result = ether_crc(ETH_ALEN, addr);
3293         int width = priv->hash_width;
3294         u8 whichbit = (result >> (32 - width)) & 0x1f;
3295         u8 whichreg = result >> (32 - width + 5);
3296         u32 value = (1 << (31-whichbit));
3297
3298         tempval = gfar_read(priv->hash_regs[whichreg]);
3299         tempval |= value;
3300         gfar_write(priv->hash_regs[whichreg], tempval);
3301 }
3302
3303
3304 /* There are multiple MAC Address register pairs on some controllers
3305  * This function sets the numth pair to a given address
3306  */
3307 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3308                                   const u8 *addr)
3309 {
3310         struct gfar_private *priv = netdev_priv(dev);
3311         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3312         u32 tempval;
3313         u32 __iomem *macptr = &regs->macstnaddr1;
3314
3315         macptr += num*2;
3316
3317         /* For a station address of 0x12345678ABCD in transmission
3318          * order (BE), MACnADDR1 is set to 0xCDAB7856 and
3319          * MACnADDR2 is set to 0x34120000.
3320          */
3321         tempval = (addr[5] << 24) | (addr[4] << 16) |
3322                   (addr[3] << 8)  |  addr[2];
3323
3324         gfar_write(macptr, tempval);
3325
3326         tempval = (addr[1] << 24) | (addr[0] << 16);
3327
3328         gfar_write(macptr+1, tempval);
3329 }
3330
3331 /* GFAR error interrupt handler */
3332 static irqreturn_t gfar_error(int irq, void *grp_id)
3333 {
3334         struct gfar_priv_grp *gfargrp = grp_id;
3335         struct gfar __iomem *regs = gfargrp->regs;
3336         struct gfar_private *priv= gfargrp->priv;
3337         struct net_device *dev = priv->ndev;
3338
3339         /* Save ievent for future reference */
3340         u32 events = gfar_read(&regs->ievent);
3341
3342         /* Clear IEVENT */
3343         gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
3344
3345         /* Magic Packet is not an error. */
3346         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3347             (events & IEVENT_MAG))
3348                 events &= ~IEVENT_MAG;
3349
3350         /* Hmm... */
3351         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3352                 netdev_dbg(dev,
3353                            "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3354                            events, gfar_read(&regs->imask));
3355
3356         /* Update the error counters */
3357         if (events & IEVENT_TXE) {
3358                 dev->stats.tx_errors++;
3359
3360                 if (events & IEVENT_LC)
3361                         dev->stats.tx_window_errors++;
3362                 if (events & IEVENT_CRL)
3363                         dev->stats.tx_aborted_errors++;
3364                 if (events & IEVENT_XFUN) {
3365                         unsigned long flags;
3366
3367                         netif_dbg(priv, tx_err, dev,
3368                                   "TX FIFO underrun, packet dropped\n");
3369                         dev->stats.tx_dropped++;
3370                         atomic64_inc(&priv->extra_stats.tx_underrun);
3371
3372                         local_irq_save(flags);
3373                         lock_tx_qs(priv);
3374
3375                         /* Reactivate the Tx Queues */
3376                         gfar_write(&regs->tstat, gfargrp->tstat);
3377
3378                         unlock_tx_qs(priv);
3379                         local_irq_restore(flags);
3380                 }
3381                 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
3382         }
3383         if (events & IEVENT_BSY) {
3384                 dev->stats.rx_errors++;
3385                 atomic64_inc(&priv->extra_stats.rx_bsy);
3386
3387                 gfar_receive(irq, grp_id);
3388
3389                 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3390                           gfar_read(&regs->rstat));
3391         }
3392         if (events & IEVENT_BABR) {
3393                 dev->stats.rx_errors++;
3394                 atomic64_inc(&priv->extra_stats.rx_babr);
3395
3396                 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
3397         }
3398         if (events & IEVENT_EBERR) {
3399                 atomic64_inc(&priv->extra_stats.eberr);
3400                 netif_dbg(priv, rx_err, dev, "bus error\n");
3401         }
3402         if (events & IEVENT_RXC)
3403                 netif_dbg(priv, rx_status, dev, "control frame\n");
3404
3405         if (events & IEVENT_BABT) {
3406                 atomic64_inc(&priv->extra_stats.tx_babt);
3407                 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3408         }
3409         return IRQ_HANDLED;
3410 }
3411
3412 static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv)
3413 {
3414         struct phy_device *phydev = priv->phydev;
3415         u32 val = 0;
3416
3417         if (!phydev->duplex)
3418                 return val;
3419
3420         if (!priv->pause_aneg_en) {
3421                 if (priv->tx_pause_en)
3422                         val |= MACCFG1_TX_FLOW;
3423                 if (priv->rx_pause_en)
3424                         val |= MACCFG1_RX_FLOW;
3425         } else {
3426                 u16 lcl_adv, rmt_adv;
3427                 u8 flowctrl;
3428                 /* get link partner capabilities */
3429                 rmt_adv = 0;
3430                 if (phydev->pause)
3431                         rmt_adv = LPA_PAUSE_CAP;
3432                 if (phydev->asym_pause)
3433                         rmt_adv |= LPA_PAUSE_ASYM;
3434
3435                 lcl_adv = 0;
3436                 if (phydev->advertising & ADVERTISED_Pause)
3437                         lcl_adv |= ADVERTISE_PAUSE_CAP;
3438                 if (phydev->advertising & ADVERTISED_Asym_Pause)
3439                         lcl_adv |= ADVERTISE_PAUSE_ASYM;
3440
3441                 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
3442                 if (flowctrl & FLOW_CTRL_TX)
3443                         val |= MACCFG1_TX_FLOW;
3444                 if (flowctrl & FLOW_CTRL_RX)
3445                         val |= MACCFG1_RX_FLOW;
3446         }
3447
3448         return val;
3449 }
3450
3451 static noinline void gfar_update_link_state(struct gfar_private *priv)
3452 {
3453         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3454         struct phy_device *phydev = priv->phydev;
3455         struct gfar_priv_rx_q *rx_queue = NULL;
3456         int i;
3457         struct rxbd8 *bdp;
3458
3459         if (unlikely(test_bit(GFAR_RESETTING, &priv->state)))
3460                 return;
3461
3462         if (phydev->link) {
3463                 u32 tempval1 = gfar_read(&regs->maccfg1);
3464                 u32 tempval = gfar_read(&regs->maccfg2);
3465                 u32 ecntrl = gfar_read(&regs->ecntrl);
3466                 u32 tx_flow_oldval = (tempval & MACCFG1_TX_FLOW);
3467
3468                 if (phydev->duplex != priv->oldduplex) {
3469                         if (!(phydev->duplex))
3470                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
3471                         else
3472                                 tempval |= MACCFG2_FULL_DUPLEX;
3473
3474                         priv->oldduplex = phydev->duplex;
3475                 }
3476
3477                 if (phydev->speed != priv->oldspeed) {
3478                         switch (phydev->speed) {
3479                         case 1000:
3480                                 tempval =
3481                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
3482
3483                                 ecntrl &= ~(ECNTRL_R100);
3484                                 break;
3485                         case 100:
3486                         case 10:
3487                                 tempval =
3488                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
3489
3490                                 /* Reduced mode distinguishes
3491                                  * between 10 and 100
3492                                  */
3493                                 if (phydev->speed == SPEED_100)
3494                                         ecntrl |= ECNTRL_R100;
3495                                 else
3496                                         ecntrl &= ~(ECNTRL_R100);
3497                                 break;
3498                         default:
3499                                 netif_warn(priv, link, priv->ndev,
3500                                            "Ack!  Speed (%d) is not 10/100/1000!\n",
3501                                            phydev->speed);
3502                                 break;
3503                         }
3504
3505                         priv->oldspeed = phydev->speed;
3506                 }
3507
3508                 tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
3509                 tempval1 |= gfar_get_flowctrl_cfg(priv);
3510
3511                 /* Turn last free buffer recording on */
3512                 if ((tempval1 & MACCFG1_TX_FLOW) && !tx_flow_oldval) {
3513                         for (i = 0; i < priv->num_rx_queues; i++) {
3514                                 rx_queue = priv->rx_queue[i];
3515                                 bdp = rx_queue->cur_rx;
3516                                 /* skip to previous bd */
3517                                 bdp = skip_bd(bdp, rx_queue->rx_ring_size - 1,
3518                                               rx_queue->rx_bd_base,
3519                                               rx_queue->rx_ring_size);
3520
3521                                 if (rx_queue->rfbptr)
3522                                         gfar_write(rx_queue->rfbptr, (u32)bdp);
3523                         }
3524
3525                         priv->tx_actual_en = 1;
3526                 }
3527
3528                 if (unlikely(!(tempval1 & MACCFG1_TX_FLOW) && tx_flow_oldval))
3529                         priv->tx_actual_en = 0;
3530
3531                 gfar_write(&regs->maccfg1, tempval1);
3532                 gfar_write(&regs->maccfg2, tempval);
3533                 gfar_write(&regs->ecntrl, ecntrl);
3534
3535                 if (!priv->oldlink)
3536                         priv->oldlink = 1;
3537
3538         } else if (priv->oldlink) {
3539                 priv->oldlink = 0;
3540                 priv->oldspeed = 0;
3541                 priv->oldduplex = -1;
3542         }
3543
3544         if (netif_msg_link(priv))
3545                 phy_print_status(phydev);
3546 }
3547
3548 static struct of_device_id gfar_match[] =
3549 {
3550         {
3551                 .type = "network",
3552                 .compatible = "gianfar",
3553         },
3554         {
3555                 .compatible = "fsl,etsec2",
3556         },
3557         {},
3558 };
3559 MODULE_DEVICE_TABLE(of, gfar_match);
3560
3561 /* Structure for a device driver */
3562 static struct platform_driver gfar_driver = {
3563         .driver = {
3564                 .name = "fsl-gianfar",
3565                 .pm = GFAR_PM_OPS,
3566                 .of_match_table = gfar_match,
3567         },
3568         .probe = gfar_probe,
3569         .remove = gfar_remove,
3570 };
3571
3572 module_platform_driver(gfar_driver);