drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c

   1 /*
   2  * Copyright (c) 2014-2015 Hisilicon Limited.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9
  10 #include <linux/acpi.h>
  11 #include <linux/device.h>
  12 #include <linux/init.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/netdevice.h>
  17 #include <linux/mfd/syscon.h>
  18 #include <linux/of.h>
  19 #include <linux/of_address.h>
  20 #include <linux/of_irq.h>
  21 #include <linux/of_platform.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/vmalloc.h>
  24
  25 #include "hns_dsaf_mac.h"
  26 #include "hns_dsaf_main.h"
  27 #include "hns_dsaf_ppe.h"
  28 #include "hns_dsaf_rcb.h"
  29 #include "hns_dsaf_misc.h"
  30
  31 const char *g_dsaf_mode_match[DSAF_MODE_MAX] = {
  32         [DSAF_MODE_DISABLE_2PORT_64VM] = "2port-64vf",
  33         [DSAF_MODE_DISABLE_6PORT_0VM] = "6port-16rss",
  34         [DSAF_MODE_DISABLE_6PORT_16VM] = "6port-16vf",
  35         [DSAF_MODE_DISABLE_SP] = "single-port",
  36 };
  37
  38 static const struct acpi_device_id hns_dsaf_acpi_match[] = {
  39         { "HISI00B1", 0 },
  40         { "HISI00B2", 0 },
  41         { },
  42 };
  43 MODULE_DEVICE_TABLE(acpi, hns_dsaf_acpi_match);
  44
  45 int hns_dsaf_get_cfg(struct dsaf_device *dsaf_dev)
  46 {
  47         int ret, i;
  48         u32 desc_num;
  49         u32 buf_size;
  50         u32 reset_offset = 0;
  51         u32 res_idx = 0;
  52         const char *mode_str;
  53         struct regmap *syscon;
  54         struct resource *res;
  55         struct device_node *np = dsaf_dev->dev->of_node, *np_temp;
  56         struct platform_device *pdev = to_platform_device(dsaf_dev->dev);
  57
  58         if (dev_of_node(dsaf_dev->dev)) {
  59                 if (of_device_is_compatible(np, "hisilicon,hns-dsaf-v1"))
  60                         dsaf_dev->dsaf_ver = AE_VERSION_1;
  61                 else
  62                         dsaf_dev->dsaf_ver = AE_VERSION_2;
  63         } else if (is_acpi_node(dsaf_dev->dev->fwnode)) {
  64                 if (acpi_dev_found(hns_dsaf_acpi_match[0].id))
  65                         dsaf_dev->dsaf_ver = AE_VERSION_1;
  66                 else if (acpi_dev_found(hns_dsaf_acpi_match[1].id))
  67                         dsaf_dev->dsaf_ver = AE_VERSION_2;
  68                 else
  69                         return -ENXIO;
  70         } else {
  71                 dev_err(dsaf_dev->dev, "cannot get cfg data from of or acpi\n");
  72                 return -ENXIO;
  73         }
  74
  75         ret = device_property_read_string(dsaf_dev->dev, "mode", &mode_str);
  76         if (ret) {
  77                 dev_err(dsaf_dev->dev, "get dsaf mode fail, ret=%d!\n", ret);
  78                 return ret;
  79         }
  80         for (i = 0; i < DSAF_MODE_MAX; i++) {
  81                 if (g_dsaf_mode_match[i] &&
  82                     !strcmp(mode_str, g_dsaf_mode_match[i]))
  83                         break;
  84         }
  85         if (i >= DSAF_MODE_MAX ||
  86             i == DSAF_MODE_INVALID || i == DSAF_MODE_ENABLE) {
  87                 dev_err(dsaf_dev->dev,
  88                         "%s prs mode str fail!\n", dsaf_dev->ae_dev.name);
  89                 return -EINVAL;
  90         }
  91         dsaf_dev->dsaf_mode = (enum dsaf_mode)i;
  92
  93         if (dsaf_dev->dsaf_mode > DSAF_MODE_ENABLE)
  94                 dsaf_dev->dsaf_en = HRD_DSAF_NO_DSAF_MODE;
  95         else
  96                 dsaf_dev->dsaf_en = HRD_DSAF_MODE;
  97
  98         if ((i == DSAF_MODE_ENABLE_16VM) ||
  99             (i == DSAF_MODE_DISABLE_2PORT_8VM) ||
 100             (i == DSAF_MODE_DISABLE_6PORT_2VM))
 101                 dsaf_dev->dsaf_tc_mode = HRD_DSAF_8TC_MODE;
 102         else
 103                 dsaf_dev->dsaf_tc_mode = HRD_DSAF_4TC_MODE;
 104
 105         if (dev_of_node(dsaf_dev->dev)) {
 106                 np_temp = of_parse_phandle(np, "subctrl-syscon", 0);
 107                 syscon = syscon_node_to_regmap(np_temp);
 108                 of_node_put(np_temp);
 109                 if (IS_ERR_OR_NULL(syscon)) {
 110                         res = platform_get_resource(pdev, IORESOURCE_MEM,
 111                                                     res_idx++);
 112                         if (!res) {
 113                                 dev_err(dsaf_dev->dev, "subctrl info is needed!\n");
 114                                 return -ENOMEM;
 115                         }
 116
 117                         dsaf_dev->sc_base = devm_ioremap_resource(&pdev->dev,
 118                                                                   res);
 119                         if (IS_ERR(dsaf_dev->sc_base)) {
 120                                 dev_err(dsaf_dev->dev, "subctrl can not map!\n");
 121                                 return PTR_ERR(dsaf_dev->sc_base);
 122                         }
 123
 124                         res = platform_get_resource(pdev, IORESOURCE_MEM,
 125                                                     res_idx++);
 126                         if (!res) {
 127                                 dev_err(dsaf_dev->dev, "serdes-ctrl info is needed!\n");
 128                                 return -ENOMEM;
 129                         }
 130
 131                         dsaf_dev->sds_base = devm_ioremap_resource(&pdev->dev,
 132                                                                    res);
 133                         if (IS_ERR(dsaf_dev->sds_base)) {
 134                                 dev_err(dsaf_dev->dev, "serdes-ctrl can not map!\n");
 135                                 return PTR_ERR(dsaf_dev->sds_base);
 136                         }
 137                 } else {
 138                         dsaf_dev->sub_ctrl = syscon;
 139                 }
 140         }
 141
 142         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ppe-base");
 143         if (!res) {
 144                 res = platform_get_resource(pdev, IORESOURCE_MEM, res_idx++);
 145                 if (!res) {
 146                         dev_err(dsaf_dev->dev, "ppe-base info is needed!\n");
 147                         return -ENOMEM;
 148                 }
 149         }
 150         dsaf_dev->ppe_base = devm_ioremap_resource(&pdev->dev, res);
 151         if (IS_ERR(dsaf_dev->ppe_base)) {
 152                 dev_err(dsaf_dev->dev, "ppe-base resource can not map!\n");
 153                 return PTR_ERR(dsaf_dev->ppe_base);
 154         }
 155         dsaf_dev->ppe_paddr = res->start;
 156
 157         if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
 158                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 159                                                    "dsaf-base");
 160                 if (!res) {
 161                         res = platform_get_resource(pdev, IORESOURCE_MEM,
 162                                                     res_idx);
 163                         if (!res) {
 164                                 dev_err(dsaf_dev->dev,
 165                                         "dsaf-base info is needed!\n");
 166                                 return -ENOMEM;
 167                         }
 168                 }
 169                 dsaf_dev->io_base = devm_ioremap_resource(&pdev->dev, res);
 170                 if (IS_ERR(dsaf_dev->io_base)) {
 171                         dev_err(dsaf_dev->dev, "dsaf-base resource can not map!\n");
 172                         return PTR_ERR(dsaf_dev->io_base);
 173                 }
 174         }
 175
 176         ret = device_property_read_u32(dsaf_dev->dev, "desc-num", &desc_num);
 177         if (ret < 0 || desc_num < HNS_DSAF_MIN_DESC_CNT ||
 178             desc_num > HNS_DSAF_MAX_DESC_CNT) {
 179                 dev_err(dsaf_dev->dev, "get desc-num(%d) fail, ret=%d!\n",
 180                         desc_num, ret);
 181                 return -EINVAL;
 182         }
 183         dsaf_dev->desc_num = desc_num;
 184
 185         ret = device_property_read_u32(dsaf_dev->dev, "reset-field-offset",
 186                                        &reset_offset);
 187         if (ret < 0) {
 188                 dev_dbg(dsaf_dev->dev,
 189                         "get reset-field-offset fail, ret=%d!\r\n", ret);
 190         }
 191         dsaf_dev->reset_offset = reset_offset;
 192
 193         ret = device_property_read_u32(dsaf_dev->dev, "buf-size", &buf_size);
 194         if (ret < 0) {
 195                 dev_err(dsaf_dev->dev,
 196                         "get buf-size fail, ret=%d!\r\n", ret);
 197                 return ret;
 198         }
 199         dsaf_dev->buf_size = buf_size;
 200
 201         dsaf_dev->buf_size_type = hns_rcb_buf_size2type(buf_size);
 202         if (dsaf_dev->buf_size_type < 0) {
 203                 dev_err(dsaf_dev->dev,
 204                         "buf_size(%d) is wrong!\n", buf_size);
 205                 return -EINVAL;
 206         }
 207
 208         dsaf_dev->misc_op = hns_misc_op_get(dsaf_dev);
 209         if (!dsaf_dev->misc_op)
 210                 return -ENOMEM;
 211
 212         if (!dma_set_mask_and_coherent(dsaf_dev->dev, DMA_BIT_MASK(64ULL)))
 213                 dev_dbg(dsaf_dev->dev, "set mask to 64bit\n");
 214         else
 215                 dev_err(dsaf_dev->dev, "set mask to 64bit fail!\n");
 216
 217         return 0;
 218 }
 219
 220 /**
 221  * hns_dsaf_sbm_link_sram_init_en - config dsaf_sbm_init_en
 222  * @dsaf_id: dsa fabric id
 223  */
 224 static void hns_dsaf_sbm_link_sram_init_en(struct dsaf_device *dsaf_dev)
 225 {
 226         dsaf_set_dev_bit(dsaf_dev, DSAF_CFG_0_REG, DSAF_CFG_SBM_INIT_S, 1);
 227 }
 228
 229 /**
 230  * hns_dsaf_reg_cnt_clr_ce - config hns_dsaf_reg_cnt_clr_ce
 231  * @dsaf_id: dsa fabric id
 232  * @hns_dsaf_reg_cnt_clr_ce: config value
 233  */
 234 static void
 235 hns_dsaf_reg_cnt_clr_ce(struct dsaf_device *dsaf_dev, u32 reg_cnt_clr_ce)
 236 {
 237         dsaf_set_dev_bit(dsaf_dev, DSAF_DSA_REG_CNT_CLR_CE_REG,
 238                          DSAF_CNT_CLR_CE_S, reg_cnt_clr_ce);
 239 }
 240
 241 /**
 242  * hns_ppe_qid_cfg - config ppe qid
 243  * @dsaf_id: dsa fabric id
 244  * @pppe_qid_cfg: value array
 245  */
 246 static void
 247 hns_dsaf_ppe_qid_cfg(struct dsaf_device *dsaf_dev, u32 qid_cfg)
 248 {
 249         u32 i;
 250
 251         for (i = 0; i < DSAF_COMM_CHN; i++) {
 252                 dsaf_set_dev_field(dsaf_dev,
 253                                    DSAF_PPE_QID_CFG_0_REG + 0x0004 * i,
 254                                    DSAF_PPE_QID_CFG_M, DSAF_PPE_QID_CFG_S,
 255                                    qid_cfg);
 256         }
 257 }
 258
 259 static void hns_dsaf_mix_def_qid_cfg(struct dsaf_device *dsaf_dev)
 260 {
 261         u16 max_q_per_vf, max_vfn;
 262         u32 q_id, q_num_per_port;
 263         u32 i;
 264
 265         hns_rcb_get_queue_mode(dsaf_dev->dsaf_mode, &max_vfn, &max_q_per_vf);
 266         q_num_per_port = max_vfn * max_q_per_vf;
 267
 268         for (i = 0, q_id = 0; i < DSAF_SERVICE_NW_NUM; i++) {
 269                 dsaf_set_dev_field(dsaf_dev,
 270                                    DSAF_MIX_DEF_QID_0_REG + 0x0004 * i,
 271                                    0xff, 0, q_id);
 272                 q_id += q_num_per_port;
 273         }
 274 }
 275
 276 static void hns_dsaf_inner_qid_cfg(struct dsaf_device *dsaf_dev)
 277 {
 278         u16 max_q_per_vf, max_vfn;
 279         u32 q_id, q_num_per_port;
 280         u32 mac_id;
 281
 282         if (AE_IS_VER1(dsaf_dev->dsaf_ver))
 283                 return;
 284
 285         hns_rcb_get_queue_mode(dsaf_dev->dsaf_mode, &max_vfn, &max_q_per_vf);
 286         q_num_per_port = max_vfn * max_q_per_vf;
 287
 288         for (mac_id = 0, q_id = 0; mac_id < DSAF_SERVICE_NW_NUM; mac_id++) {
 289                 dsaf_set_dev_field(dsaf_dev,
 290                                    DSAFV2_SERDES_LBK_0_REG + 4 * mac_id,
 291                                    DSAFV2_SERDES_LBK_QID_M,
 292                                    DSAFV2_SERDES_LBK_QID_S,
 293                                    q_id);
 294                 q_id += q_num_per_port;
 295         }
 296 }
 297
 298 /**
 299  * hns_dsaf_sw_port_type_cfg - cfg sw type
 300  * @dsaf_id: dsa fabric id
 301  * @psw_port_type: array
 302  */
 303 static void hns_dsaf_sw_port_type_cfg(struct dsaf_device *dsaf_dev,
 304                                       enum dsaf_sw_port_type port_type)
 305 {
 306         u32 i;
 307
 308         for (i = 0; i < DSAF_SW_PORT_NUM; i++) {
 309                 dsaf_set_dev_field(dsaf_dev,
 310                                    DSAF_SW_PORT_TYPE_0_REG + 0x0004 * i,
 311                                    DSAF_SW_PORT_TYPE_M, DSAF_SW_PORT_TYPE_S,
 312                                    port_type);
 313         }
 314 }
 315
 316 /**
 317  * hns_dsaf_stp_port_type_cfg - cfg stp type
 318  * @dsaf_id: dsa fabric id
 319  * @pstp_port_type: array
 320  */
 321 static void hns_dsaf_stp_port_type_cfg(struct dsaf_device *dsaf_dev,
 322                                        enum dsaf_stp_port_type port_type)
 323 {
 324         u32 i;
 325
 326         for (i = 0; i < DSAF_COMM_CHN; i++) {
 327                 dsaf_set_dev_field(dsaf_dev,
 328                                    DSAF_STP_PORT_TYPE_0_REG + 0x0004 * i,
 329                                    DSAF_STP_PORT_TYPE_M, DSAF_STP_PORT_TYPE_S,
 330                                    port_type);
 331         }
 332 }
 333
 334 #define HNS_DSAF_SBM_NUM(dev) \
 335         (AE_IS_VER1((dev)->dsaf_ver) ? DSAF_SBM_NUM : DSAFV2_SBM_NUM)
 336 /**
 337  * hns_dsaf_sbm_cfg - config sbm
 338  * @dsaf_id: dsa fabric id
 339  */
 340 static void hns_dsaf_sbm_cfg(struct dsaf_device *dsaf_dev)
 341 {
 342         u32 o_sbm_cfg;
 343         u32 i;
 344
 345         for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) {
 346                 o_sbm_cfg = dsaf_read_dev(dsaf_dev,
 347                                           DSAF_SBM_CFG_REG_0_REG + 0x80 * i);
 348                 dsaf_set_bit(o_sbm_cfg, DSAF_SBM_CFG_EN_S, 1);
 349                 dsaf_set_bit(o_sbm_cfg, DSAF_SBM_CFG_SHCUT_EN_S, 0);
 350                 dsaf_write_dev(dsaf_dev,
 351                                DSAF_SBM_CFG_REG_0_REG + 0x80 * i, o_sbm_cfg);
 352         }
 353 }
 354
 355 /**
 356  * hns_dsaf_sbm_cfg_mib_en - config sbm
 357  * @dsaf_id: dsa fabric id
 358  */
 359 static int hns_dsaf_sbm_cfg_mib_en(struct dsaf_device *dsaf_dev)
 360 {
 361         u32 sbm_cfg_mib_en;
 362         u32 i;
 363         u32 reg;
 364         u32 read_cnt;
 365
 366         /* validate configure by setting SBM_CFG_MIB_EN bit from 0 to 1. */
 367         for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) {
 368                 reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i;
 369                 dsaf_set_dev_bit(dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S, 0);
 370         }
 371
 372         for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) {
 373                 reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i;
 374                 dsaf_set_dev_bit(dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S, 1);
 375         }
 376
 377         /* waitint for all sbm enable finished */
 378         for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) {
 379                 read_cnt = 0;
 380                 reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i;
 381                 do {
 382                         udelay(1);
 383                         sbm_cfg_mib_en = dsaf_get_dev_bit(
 384                                         dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S);
 385                         read_cnt++;
 386                 } while (sbm_cfg_mib_en == 0 &&
 387                         read_cnt < DSAF_CFG_READ_CNT);
 388
 389                 if (sbm_cfg_mib_en == 0) {
 390                         dev_err(dsaf_dev->dev,
 391                                 "sbm_cfg_mib_en fail,%s,sbm_num=%d\n",
 392                                 dsaf_dev->ae_dev.name, i);
 393                         return -ENODEV;
 394                 }
 395         }
 396
 397         return 0;
 398 }
 399
 400 /**
 401  * hns_dsaf_sbm_bp_wl_cfg - config sbm
 402  * @dsaf_id: dsa fabric id
 403  */
 404 static void hns_dsaf_sbm_bp_wl_cfg(struct dsaf_device *dsaf_dev)
 405 {
 406         u32 o_sbm_bp_cfg;
 407         u32 reg;
 408         u32 i;
 409
 410         /* XGE */
 411         for (i = 0; i < DSAF_XGE_NUM; i++) {
 412                 reg = DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + 0x80 * i;
 413                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 414                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG0_COM_MAX_BUF_NUM_M,
 415                                DSAF_SBM_CFG0_COM_MAX_BUF_NUM_S, 512);
 416                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG0_VC0_MAX_BUF_NUM_M,
 417                                DSAF_SBM_CFG0_VC0_MAX_BUF_NUM_S, 0);
 418                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG0_VC1_MAX_BUF_NUM_M,
 419                                DSAF_SBM_CFG0_VC1_MAX_BUF_NUM_S, 0);
 420                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 421
 422                 reg = DSAF_SBM_BP_CFG_1_REG_0_REG + 0x80 * i;
 423                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 424                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG1_TC4_MAX_BUF_NUM_M,
 425                                DSAF_SBM_CFG1_TC4_MAX_BUF_NUM_S, 0);
 426                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG1_TC0_MAX_BUF_NUM_M,
 427                                DSAF_SBM_CFG1_TC0_MAX_BUF_NUM_S, 0);
 428                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 429
 430                 reg = DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + 0x80 * i;
 431                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 432                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_SET_BUF_NUM_M,
 433                                DSAF_SBM_CFG2_SET_BUF_NUM_S, 104);
 434                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_RESET_BUF_NUM_M,
 435                                DSAF_SBM_CFG2_RESET_BUF_NUM_S, 128);
 436                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 437
 438                 reg = DSAF_SBM_BP_CFG_3_REG_0_REG + 0x80 * i;
 439                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 440                 dsaf_set_field(o_sbm_bp_cfg,
 441                                DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_M,
 442                                DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_S, 110);
 443                 dsaf_set_field(o_sbm_bp_cfg,
 444                                DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M,
 445                                DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S, 160);
 446                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 447
 448                 /* for no enable pfc mode */
 449                 reg = DSAF_SBM_BP_CFG_4_REG_0_REG + 0x80 * i;
 450                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 451                 dsaf_set_field(o_sbm_bp_cfg,
 452                                DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_M,
 453                                DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_S, 128);
 454                 dsaf_set_field(o_sbm_bp_cfg,
 455                                DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M,
 456                                DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S, 192);
 457                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 458         }
 459
 460         /* PPE */
 461         for (i = 0; i < DSAF_COMM_CHN; i++) {
 462                 reg = DSAF_SBM_BP_CFG_2_PPE_REG_0_REG + 0x80 * i;
 463                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 464                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_SET_BUF_NUM_M,
 465                                DSAF_SBM_CFG2_SET_BUF_NUM_S, 10);
 466                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_RESET_BUF_NUM_M,
 467                                DSAF_SBM_CFG2_RESET_BUF_NUM_S, 12);
 468                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 469         }
 470
 471         /* RoCEE */
 472         for (i = 0; i < DSAF_COMM_CHN; i++) {
 473                 reg = DSAF_SBM_BP_CFG_2_ROCEE_REG_0_REG + 0x80 * i;
 474                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 475                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_SET_BUF_NUM_M,
 476                                DSAF_SBM_CFG2_SET_BUF_NUM_S, 2);
 477                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_RESET_BUF_NUM_M,
 478                                DSAF_SBM_CFG2_RESET_BUF_NUM_S, 4);
 479                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 480         }
 481 }
 482
 483 static void hns_dsafv2_sbm_bp_wl_cfg(struct dsaf_device *dsaf_dev)
 484 {
 485         u32 o_sbm_bp_cfg;
 486         u32 reg;
 487         u32 i;
 488
 489         /* XGE */
 490         for (i = 0; i < DSAFV2_SBM_XGE_CHN; i++) {
 491                 reg = DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + 0x80 * i;
 492                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 493                 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG0_COM_MAX_BUF_NUM_M,
 494                                DSAFV2_SBM_CFG0_COM_MAX_BUF_NUM_S, 256);
 495                 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG0_VC0_MAX_BUF_NUM_M,
 496                                DSAFV2_SBM_CFG0_VC0_MAX_BUF_NUM_S, 0);
 497                 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG0_VC1_MAX_BUF_NUM_M,
 498                                DSAFV2_SBM_CFG0_VC1_MAX_BUF_NUM_S, 0);
 499                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 500
 501                 reg = DSAF_SBM_BP_CFG_1_REG_0_REG + 0x80 * i;
 502                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 503                 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG1_TC4_MAX_BUF_NUM_M,
 504                                DSAFV2_SBM_CFG1_TC4_MAX_BUF_NUM_S, 0);
 505                 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG1_TC0_MAX_BUF_NUM_M,
 506                                DSAFV2_SBM_CFG1_TC0_MAX_BUF_NUM_S, 0);
 507                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 508
 509                 reg = DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + 0x80 * i;
 510                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 511                 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG2_SET_BUF_NUM_M,
 512                                DSAFV2_SBM_CFG2_SET_BUF_NUM_S, 104);
 513                 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG2_RESET_BUF_NUM_M,
 514                                DSAFV2_SBM_CFG2_RESET_BUF_NUM_S, 128);
 515                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 516
 517                 reg = DSAF_SBM_BP_CFG_3_REG_0_REG + 0x80 * i;
 518                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 519                 dsaf_set_field(o_sbm_bp_cfg,
 520                                DSAFV2_SBM_CFG3_SET_BUF_NUM_NO_PFC_M,
 521                                DSAFV2_SBM_CFG3_SET_BUF_NUM_NO_PFC_S, 48);
 522                 dsaf_set_field(o_sbm_bp_cfg,
 523                                DSAFV2_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M,
 524                                DSAFV2_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S, 80);
 525                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 526
 527                 /* for no enable pfc mode */
 528                 reg = DSAF_SBM_BP_CFG_4_REG_0_REG + 0x80 * i;
 529                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 530                 dsaf_set_field(o_sbm_bp_cfg,
 531                                DSAFV2_SBM_CFG4_SET_BUF_NUM_NO_PFC_M,
 532                                DSAFV2_SBM_CFG4_SET_BUF_NUM_NO_PFC_S, 192);
 533                 dsaf_set_field(o_sbm_bp_cfg,
 534                                DSAFV2_SBM_CFG4_RESET_BUF_NUM_NO_PFC_M,
 535                                DSAFV2_SBM_CFG4_RESET_BUF_NUM_NO_PFC_S, 240);
 536                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 537         }
 538
 539         /* PPE */
 540         for (i = 0; i < DSAFV2_SBM_PPE_CHN; i++) {
 541                 reg = DSAF_SBM_BP_CFG_2_PPE_REG_0_REG + 0x80 * i;
 542                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 543                 dsaf_set_field(o_sbm_bp_cfg,
 544                                DSAFV2_SBM_CFG2_PPE_SET_BUF_NUM_M,
 545                                DSAFV2_SBM_CFG2_PPE_SET_BUF_NUM_S, 2);
 546                 dsaf_set_field(o_sbm_bp_cfg,
 547                                DSAFV2_SBM_CFG2_PPE_RESET_BUF_NUM_M,
 548                                DSAFV2_SBM_CFG2_PPE_RESET_BUF_NUM_S, 3);
 549                 dsaf_set_field(o_sbm_bp_cfg,
 550                                DSAFV2_SBM_CFG2_PPE_CFG_USEFUL_NUM_M,
 551                                DSAFV2_SBM_CFG2_PPE_CFG_USEFUL_NUM_S, 52);
 552                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 553         }
 554
 555         /* RoCEE */
 556         for (i = 0; i < DASFV2_ROCEE_CRD_NUM; i++) {
 557                 reg = DSAFV2_SBM_BP_CFG_2_ROCEE_REG_0_REG + 0x80 * i;
 558                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 559                 dsaf_set_field(o_sbm_bp_cfg,
 560                                DSAFV2_SBM_CFG2_ROCEE_SET_BUF_NUM_M,
 561                                DSAFV2_SBM_CFG2_ROCEE_SET_BUF_NUM_S, 2);
 562                 dsaf_set_field(o_sbm_bp_cfg,
 563                                DSAFV2_SBM_CFG2_ROCEE_RESET_BUF_NUM_M,
 564                                DSAFV2_SBM_CFG2_ROCEE_RESET_BUF_NUM_S, 4);
 565                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 566         }
 567 }
 568
 569 /**
 570  * hns_dsaf_voq_bp_all_thrd_cfg -  voq
 571  * @dsaf_id: dsa fabric id
 572  */
 573 static void hns_dsaf_voq_bp_all_thrd_cfg(struct dsaf_device *dsaf_dev)
 574 {
 575         u32 voq_bp_all_thrd;
 576         u32 i;
 577
 578         for (i = 0; i < DSAF_VOQ_NUM; i++) {
 579                 voq_bp_all_thrd = dsaf_read_dev(
 580                         dsaf_dev, DSAF_VOQ_BP_ALL_THRD_0_REG + 0x40 * i);
 581                 if (i < DSAF_XGE_NUM) {
 582                         dsaf_set_field(voq_bp_all_thrd,
 583                                        DSAF_VOQ_BP_ALL_DOWNTHRD_M,
 584                                        DSAF_VOQ_BP_ALL_DOWNTHRD_S, 930);
 585                         dsaf_set_field(voq_bp_all_thrd,
 586                                        DSAF_VOQ_BP_ALL_UPTHRD_M,
 587                                        DSAF_VOQ_BP_ALL_UPTHRD_S, 950);
 588                 } else {
 589                         dsaf_set_field(voq_bp_all_thrd,
 590                                        DSAF_VOQ_BP_ALL_DOWNTHRD_M,
 591                                        DSAF_VOQ_BP_ALL_DOWNTHRD_S, 220);
 592                         dsaf_set_field(voq_bp_all_thrd,
 593                                        DSAF_VOQ_BP_ALL_UPTHRD_M,
 594                                        DSAF_VOQ_BP_ALL_UPTHRD_S, 230);
 595                 }
 596                 dsaf_write_dev(
 597                         dsaf_dev, DSAF_VOQ_BP_ALL_THRD_0_REG + 0x40 * i,
 598                         voq_bp_all_thrd);
 599         }
 600 }
 601
 602 /**
 603  * hns_dsaf_tbl_tcam_data_cfg - tbl
 604  * @dsaf_id: dsa fabric id
 605  * @ptbl_tcam_data: addr
 606  */
 607 static void hns_dsaf_tbl_tcam_data_cfg(
 608         struct dsaf_device *dsaf_dev,
 609         struct dsaf_tbl_tcam_data *ptbl_tcam_data)
 610 {
 611         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_LOW_0_REG,
 612                        ptbl_tcam_data->tbl_tcam_data_low);
 613         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_HIGH_0_REG,
 614                        ptbl_tcam_data->tbl_tcam_data_high);
 615 }
 616
 617 /**
 618  * dsaf_tbl_tcam_mcast_cfg - tbl
 619  * @dsaf_id: dsa fabric id
 620  * @ptbl_tcam_mcast: addr
 621  */
 622 static void hns_dsaf_tbl_tcam_mcast_cfg(
 623         struct dsaf_device *dsaf_dev,
 624         struct dsaf_tbl_tcam_mcast_cfg *mcast)
 625 {
 626         u32 mcast_cfg4;
 627
 628         mcast_cfg4 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG);
 629         dsaf_set_bit(mcast_cfg4, DSAF_TBL_MCAST_CFG4_ITEM_VLD_S,
 630                      mcast->tbl_mcast_item_vld);
 631         dsaf_set_bit(mcast_cfg4, DSAF_TBL_MCAST_CFG4_OLD_EN_S,
 632                      mcast->tbl_mcast_old_en);
 633         dsaf_set_field(mcast_cfg4, DSAF_TBL_MCAST_CFG4_VM128_112_M,
 634                        DSAF_TBL_MCAST_CFG4_VM128_112_S,
 635                        mcast->tbl_mcast_port_msk[4]);
 636         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG, mcast_cfg4);
 637
 638         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG,
 639                        mcast->tbl_mcast_port_msk[3]);
 640
 641         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG,
 642                        mcast->tbl_mcast_port_msk[2]);
 643
 644         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG,
 645                        mcast->tbl_mcast_port_msk[1]);
 646
 647         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG,
 648                        mcast->tbl_mcast_port_msk[0]);
 649 }
 650
 651 /**
 652  * hns_dsaf_tbl_tcam_ucast_cfg - tbl
 653  * @dsaf_id: dsa fabric id
 654  * @ptbl_tcam_ucast: addr
 655  */
 656 static void hns_dsaf_tbl_tcam_ucast_cfg(
 657         struct dsaf_device *dsaf_dev,
 658         struct dsaf_tbl_tcam_ucast_cfg *tbl_tcam_ucast)
 659 {
 660         u32 ucast_cfg1;
 661
 662         ucast_cfg1 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_UCAST_CFG_0_REG);
 663         dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_MAC_DISCARD_S,
 664                      tbl_tcam_ucast->tbl_ucast_mac_discard);
 665         dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_ITEM_VLD_S,
 666                      tbl_tcam_ucast->tbl_ucast_item_vld);
 667         dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_OLD_EN_S,
 668                      tbl_tcam_ucast->tbl_ucast_old_en);
 669         dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_DVC_S,
 670                      tbl_tcam_ucast->tbl_ucast_dvc);
 671         dsaf_set_field(ucast_cfg1, DSAF_TBL_UCAST_CFG1_OUT_PORT_M,
 672                        DSAF_TBL_UCAST_CFG1_OUT_PORT_S,
 673                        tbl_tcam_ucast->tbl_ucast_out_port);
 674         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_UCAST_CFG_0_REG, ucast_cfg1);
 675 }
 676
 677 /**
 678  * hns_dsaf_tbl_line_cfg - tbl
 679  * @dsaf_id: dsa fabric id
 680  * @ptbl_lin: addr
 681  */
 682 static void hns_dsaf_tbl_line_cfg(struct dsaf_device *dsaf_dev,
 683                                   struct dsaf_tbl_line_cfg *tbl_lin)
 684 {
 685         u32 tbl_line;
 686
 687         tbl_line = dsaf_read_dev(dsaf_dev, DSAF_TBL_LIN_CFG_0_REG);
 688         dsaf_set_bit(tbl_line, DSAF_TBL_LINE_CFG_MAC_DISCARD_S,
 689                      tbl_lin->tbl_line_mac_discard);
 690         dsaf_set_bit(tbl_line, DSAF_TBL_LINE_CFG_DVC_S,
 691                      tbl_lin->tbl_line_dvc);
 692         dsaf_set_field(tbl_line, DSAF_TBL_LINE_CFG_OUT_PORT_M,
 693                        DSAF_TBL_LINE_CFG_OUT_PORT_S,
 694                        tbl_lin->tbl_line_out_port);
 695         dsaf_write_dev(dsaf_dev, DSAF_TBL_LIN_CFG_0_REG, tbl_line);
 696 }
 697
 698 /**
 699  * hns_dsaf_tbl_tcam_mcast_pul - tbl
 700  * @dsaf_id: dsa fabric id
 701  */
 702 static void hns_dsaf_tbl_tcam_mcast_pul(struct dsaf_device *dsaf_dev)
 703 {
 704         u32 o_tbl_pul;
 705
 706         o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG);
 707         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 1);
 708         dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
 709         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 0);
 710         dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
 711 }
 712
 713 /**
 714  * hns_dsaf_tbl_line_pul - tbl
 715  * @dsaf_id: dsa fabric id
 716  */
 717 static void hns_dsaf_tbl_line_pul(struct dsaf_device *dsaf_dev)
 718 {
 719         u32 tbl_pul;
 720
 721         tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG);
 722         dsaf_set_bit(tbl_pul, DSAF_TBL_PUL_LINE_VLD_S, 1);
 723         dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, tbl_pul);
 724         dsaf_set_bit(tbl_pul, DSAF_TBL_PUL_LINE_VLD_S, 0);
 725         dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, tbl_pul);
 726 }
 727
 728 /**
 729  * hns_dsaf_tbl_tcam_data_mcast_pul - tbl
 730  * @dsaf_id: dsa fabric id
 731  */
 732 static void hns_dsaf_tbl_tcam_data_mcast_pul(
 733         struct dsaf_device *dsaf_dev)
 734 {
 735         u32 o_tbl_pul;
 736
 737         o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG);
 738         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 1);
 739         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 1);
 740         dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
 741         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 0);
 742         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 0);
 743         dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
 744 }
 745
 746 /**
 747  * hns_dsaf_tbl_tcam_data_ucast_pul - tbl
 748  * @dsaf_id: dsa fabric id
 749  */
 750 static void hns_dsaf_tbl_tcam_data_ucast_pul(
 751         struct dsaf_device *dsaf_dev)
 752 {
 753         u32 o_tbl_pul;
 754
 755         o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG);
 756         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 1);
 757         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_UCAST_VLD_S, 1);
 758         dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
 759         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 0);
 760         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_UCAST_VLD_S, 0);
 761         dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
 762 }
 763
 764 void hns_dsaf_set_promisc_mode(struct dsaf_device *dsaf_dev, u32 en)
 765 {
 766         if (!HNS_DSAF_IS_DEBUG(dsaf_dev))
 767                 dsaf_set_dev_bit(dsaf_dev, DSAF_CFG_0_REG,
 768                                  DSAF_CFG_MIX_MODE_S, !!en);
 769 }
 770
 771 void hns_dsaf_set_inner_lb(struct dsaf_device *dsaf_dev, u32 mac_id, u32 en)
 772 {
 773         if (AE_IS_VER1(dsaf_dev->dsaf_ver) ||
 774             dsaf_dev->mac_cb[mac_id]->mac_type == HNAE_PORT_DEBUG)
 775                 return;
 776
 777         dsaf_set_dev_bit(dsaf_dev, DSAFV2_SERDES_LBK_0_REG + 4 * mac_id,
 778                          DSAFV2_SERDES_LBK_EN_B, !!en);
 779 }
 780
 781 /**
 782  * hns_dsaf_tbl_stat_en - tbl
 783  * @dsaf_id: dsa fabric id
 784  * @ptbl_stat_en: addr
 785  */
 786 static void hns_dsaf_tbl_stat_en(struct dsaf_device *dsaf_dev)
 787 {
 788         u32 o_tbl_ctrl;
 789
 790         o_tbl_ctrl = dsaf_read_dev(dsaf_dev, DSAF_TBL_DFX_CTRL_0_REG);
 791         dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_LINE_LKUP_NUM_EN_S, 1);
 792         dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_UC_LKUP_NUM_EN_S, 1);
 793         dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_MC_LKUP_NUM_EN_S, 1);
 794         dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_BC_LKUP_NUM_EN_S, 1);
 795         dsaf_write_dev(dsaf_dev, DSAF_TBL_DFX_CTRL_0_REG, o_tbl_ctrl);
 796 }
 797
 798 /**
 799  * hns_dsaf_rocee_bp_en - rocee back press enable
 800  * @dsaf_id: dsa fabric id
 801  */
 802 static void hns_dsaf_rocee_bp_en(struct dsaf_device *dsaf_dev)
 803 {
 804         if (AE_IS_VER1(dsaf_dev->dsaf_ver))
 805                 dsaf_set_dev_bit(dsaf_dev, DSAF_XGE_CTRL_SIG_CFG_0_REG,
 806                                  DSAF_FC_XGE_TX_PAUSE_S, 1);
 807 }
 808
 809 /* set msk for dsaf exception irq*/
 810 static void hns_dsaf_int_xge_msk_set(struct dsaf_device *dsaf_dev,
 811                                      u32 chnn_num, u32 mask_set)
 812 {
 813         dsaf_write_dev(dsaf_dev,
 814                        DSAF_XGE_INT_MSK_0_REG + 0x4 * chnn_num, mask_set);
 815 }
 816
 817 static void hns_dsaf_int_ppe_msk_set(struct dsaf_device *dsaf_dev,
 818                                      u32 chnn_num, u32 msk_set)
 819 {
 820         dsaf_write_dev(dsaf_dev,
 821                        DSAF_PPE_INT_MSK_0_REG + 0x4 * chnn_num, msk_set);
 822 }
 823
 824 static void hns_dsaf_int_rocee_msk_set(struct dsaf_device *dsaf_dev,
 825                                        u32 chnn, u32 msk_set)
 826 {
 827         dsaf_write_dev(dsaf_dev,
 828                        DSAF_ROCEE_INT_MSK_0_REG + 0x4 * chnn, msk_set);
 829 }
 830
 831 static void
 832 hns_dsaf_int_tbl_msk_set(struct dsaf_device *dsaf_dev, u32 msk_set)
 833 {
 834         dsaf_write_dev(dsaf_dev, DSAF_TBL_INT_MSK_0_REG, msk_set);
 835 }
 836
 837 /* clr dsaf exception irq*/
 838 static void hns_dsaf_int_xge_src_clr(struct dsaf_device *dsaf_dev,
 839                                      u32 chnn_num, u32 int_src)
 840 {
 841         dsaf_write_dev(dsaf_dev,
 842                        DSAF_XGE_INT_SRC_0_REG + 0x4 * chnn_num, int_src);
 843 }
 844
 845 static void hns_dsaf_int_ppe_src_clr(struct dsaf_device *dsaf_dev,
 846                                      u32 chnn, u32 int_src)
 847 {
 848         dsaf_write_dev(dsaf_dev,
 849                        DSAF_PPE_INT_SRC_0_REG + 0x4 * chnn, int_src);
 850 }
 851
 852 static void hns_dsaf_int_rocee_src_clr(struct dsaf_device *dsaf_dev,
 853                                        u32 chnn, u32 int_src)
 854 {
 855         dsaf_write_dev(dsaf_dev,
 856                        DSAF_ROCEE_INT_SRC_0_REG + 0x4 * chnn, int_src);
 857 }
 858
 859 static void hns_dsaf_int_tbl_src_clr(struct dsaf_device *dsaf_dev,
 860                                      u32 int_src)
 861 {
 862         dsaf_write_dev(dsaf_dev, DSAF_TBL_INT_SRC_0_REG, int_src);
 863 }
 864
 865 /**
 866  * hns_dsaf_single_line_tbl_cfg - INT
 867  * @dsaf_id: dsa fabric id
 868  * @address:
 869  * @ptbl_line:
 870  */
 871 static void hns_dsaf_single_line_tbl_cfg(
 872         struct dsaf_device *dsaf_dev,
 873         u32 address, struct dsaf_tbl_line_cfg *ptbl_line)
 874 {
 875         spin_lock_bh(&dsaf_dev->tcam_lock);
 876
 877         /*Write Addr*/
 878         hns_dsaf_tbl_line_addr_cfg(dsaf_dev, address);
 879
 880         /*Write Line*/
 881         hns_dsaf_tbl_line_cfg(dsaf_dev, ptbl_line);
 882
 883         /*Write Plus*/
 884         hns_dsaf_tbl_line_pul(dsaf_dev);
 885
 886         spin_unlock_bh(&dsaf_dev->tcam_lock);
 887 }
 888
 889 /**
 890  * hns_dsaf_tcam_uc_cfg - INT
 891  * @dsaf_id: dsa fabric id
 892  * @address,
 893  * @ptbl_tcam_data,
 894  */
 895 static void hns_dsaf_tcam_uc_cfg(
 896         struct dsaf_device *dsaf_dev, u32 address,
 897         struct dsaf_tbl_tcam_data *ptbl_tcam_data,
 898         struct dsaf_tbl_tcam_ucast_cfg *ptbl_tcam_ucast)
 899 {
 900         spin_lock_bh(&dsaf_dev->tcam_lock);
 901
 902         /*Write Addr*/
 903         hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
 904         /*Write Tcam Data*/
 905         hns_dsaf_tbl_tcam_data_cfg(dsaf_dev, ptbl_tcam_data);
 906         /*Write Tcam Ucast*/
 907         hns_dsaf_tbl_tcam_ucast_cfg(dsaf_dev, ptbl_tcam_ucast);
 908         /*Write Plus*/
 909         hns_dsaf_tbl_tcam_data_ucast_pul(dsaf_dev);
 910
 911         spin_unlock_bh(&dsaf_dev->tcam_lock);
 912 }
 913
 914 /**
 915  * hns_dsaf_tcam_mc_cfg - INT
 916  * @dsaf_id: dsa fabric id
 917  * @address,
 918  * @ptbl_tcam_data,
 919  * @ptbl_tcam_mcast,
 920  */
 921 static void hns_dsaf_tcam_mc_cfg(
 922         struct dsaf_device *dsaf_dev, u32 address,
 923         struct dsaf_tbl_tcam_data *ptbl_tcam_data,
 924         struct dsaf_tbl_tcam_mcast_cfg *ptbl_tcam_mcast)
 925 {
 926         spin_lock_bh(&dsaf_dev->tcam_lock);
 927
 928         /*Write Addr*/
 929         hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
 930         /*Write Tcam Data*/
 931         hns_dsaf_tbl_tcam_data_cfg(dsaf_dev, ptbl_tcam_data);
 932         /*Write Tcam Mcast*/
 933         hns_dsaf_tbl_tcam_mcast_cfg(dsaf_dev, ptbl_tcam_mcast);
 934         /*Write Plus*/
 935         hns_dsaf_tbl_tcam_data_mcast_pul(dsaf_dev);
 936
 937         spin_unlock_bh(&dsaf_dev->tcam_lock);
 938 }
 939
 940 /**
 941  * hns_dsaf_tcam_mc_invld - INT
 942  * @dsaf_id: dsa fabric id
 943  * @address
 944  */
 945 static void hns_dsaf_tcam_mc_invld(struct dsaf_device *dsaf_dev, u32 address)
 946 {
 947         spin_lock_bh(&dsaf_dev->tcam_lock);
 948
 949         /*Write Addr*/
 950         hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
 951
 952         /*write tcam mcast*/
 953         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG, 0);
 954         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG, 0);
 955         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG, 0);
 956         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG, 0);
 957         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG, 0);
 958
 959         /*Write Plus*/
 960         hns_dsaf_tbl_tcam_mcast_pul(dsaf_dev);
 961
 962         spin_unlock_bh(&dsaf_dev->tcam_lock);
 963 }
 964
 965 /**
 966  * hns_dsaf_tcam_uc_get - INT
 967  * @dsaf_id: dsa fabric id
 968  * @address
 969  * @ptbl_tcam_data
 970  * @ptbl_tcam_ucast
 971  */
 972 static void hns_dsaf_tcam_uc_get(
 973         struct dsaf_device *dsaf_dev, u32 address,
 974         struct dsaf_tbl_tcam_data *ptbl_tcam_data,
 975         struct dsaf_tbl_tcam_ucast_cfg *ptbl_tcam_ucast)
 976 {
 977         u32 tcam_read_data0;
 978         u32 tcam_read_data4;
 979
 980         spin_lock_bh(&dsaf_dev->tcam_lock);
 981
 982         /*Write Addr*/
 983         hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
 984
 985         /*read tcam item puls*/
 986         hns_dsaf_tbl_tcam_load_pul(dsaf_dev);
 987
 988         /*read tcam data*/
 989         ptbl_tcam_data->tbl_tcam_data_high
 990                 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_HIGH_0_REG);
 991         ptbl_tcam_data->tbl_tcam_data_low
 992                 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_LOW_0_REG);
 993
 994         /*read tcam mcast*/
 995         tcam_read_data0 = dsaf_read_dev(dsaf_dev,
 996                                         DSAF_TBL_TCAM_RAM_RDATA0_0_REG);
 997         tcam_read_data4 = dsaf_read_dev(dsaf_dev,
 998                                         DSAF_TBL_TCAM_RAM_RDATA4_0_REG);
 999
1000         ptbl_tcam_ucast->tbl_ucast_item_vld
1001                 = dsaf_get_bit(tcam_read_data4,
1002                                DSAF_TBL_MCAST_CFG4_ITEM_VLD_S);
1003         ptbl_tcam_ucast->tbl_ucast_old_en
1004                 = dsaf_get_bit(tcam_read_data4, DSAF_TBL_MCAST_CFG4_OLD_EN_S);
1005         ptbl_tcam_ucast->tbl_ucast_mac_discard
1006                 = dsaf_get_bit(tcam_read_data0,
1007                                DSAF_TBL_UCAST_CFG1_MAC_DISCARD_S);
1008         ptbl_tcam_ucast->tbl_ucast_out_port
1009                 = dsaf_get_field(tcam_read_data0,
1010                                  DSAF_TBL_UCAST_CFG1_OUT_PORT_M,
1011                                  DSAF_TBL_UCAST_CFG1_OUT_PORT_S);
1012         ptbl_tcam_ucast->tbl_ucast_dvc
1013                 = dsaf_get_bit(tcam_read_data0, DSAF_TBL_UCAST_CFG1_DVC_S);
1014
1015         spin_unlock_bh(&dsaf_dev->tcam_lock);
1016 }
1017
1018 /**
1019  * hns_dsaf_tcam_mc_get - INT
1020  * @dsaf_id: dsa fabric id
1021  * @address
1022  * @ptbl_tcam_data
1023  * @ptbl_tcam_ucast
1024  */
1025 static void hns_dsaf_tcam_mc_get(
1026         struct dsaf_device *dsaf_dev, u32 address,
1027         struct dsaf_tbl_tcam_data *ptbl_tcam_data,
1028         struct dsaf_tbl_tcam_mcast_cfg *ptbl_tcam_mcast)
1029 {
1030         u32 data_tmp;
1031
1032         spin_lock_bh(&dsaf_dev->tcam_lock);
1033
1034         /*Write Addr*/
1035         hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
1036
1037         /*read tcam item puls*/
1038         hns_dsaf_tbl_tcam_load_pul(dsaf_dev);
1039
1040         /*read tcam data*/
1041         ptbl_tcam_data->tbl_tcam_data_high =
1042                 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_HIGH_0_REG);
1043         ptbl_tcam_data->tbl_tcam_data_low =
1044                 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_LOW_0_REG);
1045
1046         /*read tcam mcast*/
1047         ptbl_tcam_mcast->tbl_mcast_port_msk[0] =
1048                 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA0_0_REG);
1049         ptbl_tcam_mcast->tbl_mcast_port_msk[1] =
1050                 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA1_0_REG);
1051         ptbl_tcam_mcast->tbl_mcast_port_msk[2] =
1052                 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA2_0_REG);
1053         ptbl_tcam_mcast->tbl_mcast_port_msk[3] =
1054                 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA3_0_REG);
1055
1056         data_tmp = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA4_0_REG);
1057         ptbl_tcam_mcast->tbl_mcast_item_vld =
1058                 dsaf_get_bit(data_tmp, DSAF_TBL_MCAST_CFG4_ITEM_VLD_S);
1059         ptbl_tcam_mcast->tbl_mcast_old_en =
1060                 dsaf_get_bit(data_tmp, DSAF_TBL_MCAST_CFG4_OLD_EN_S);
1061         ptbl_tcam_mcast->tbl_mcast_port_msk[4] =
1062                 dsaf_get_field(data_tmp, DSAF_TBL_MCAST_CFG4_VM128_112_M,
1063                                DSAF_TBL_MCAST_CFG4_VM128_112_S);
1064
1065         spin_unlock_bh(&dsaf_dev->tcam_lock);
1066 }
1067
1068 /**
1069  * hns_dsaf_tbl_line_init - INT
1070  * @dsaf_id: dsa fabric id
1071  */
1072 static void hns_dsaf_tbl_line_init(struct dsaf_device *dsaf_dev)
1073 {
1074         u32 i;
1075         /* defaultly set all lineal mac table entry resulting discard */
1076         struct dsaf_tbl_line_cfg tbl_line[] = {{1, 0, 0} };
1077
1078         for (i = 0; i < DSAF_LINE_SUM; i++)
1079                 hns_dsaf_single_line_tbl_cfg(dsaf_dev, i, tbl_line);
1080 }
1081
1082 /**
1083  * hns_dsaf_tbl_tcam_init - INT
1084  * @dsaf_id: dsa fabric id
1085  */
1086 static void hns_dsaf_tbl_tcam_init(struct dsaf_device *dsaf_dev)
1087 {
1088         u32 i;
1089         struct dsaf_tbl_tcam_data tcam_data[] = {{0, 0} };
1090         struct dsaf_tbl_tcam_ucast_cfg tcam_ucast[] = {{0, 0, 0, 0, 0} };
1091
1092         /*tcam tbl*/
1093         for (i = 0; i < DSAF_TCAM_SUM; i++)
1094                 hns_dsaf_tcam_uc_cfg(dsaf_dev, i, tcam_data, tcam_ucast);
1095 }
1096
1097 /**
1098  * hns_dsaf_pfc_en_cfg - dsaf pfc pause cfg
1099  * @mac_cb: mac contrl block
1100  */
1101 static void hns_dsaf_pfc_en_cfg(struct dsaf_device *dsaf_dev,
1102                                 int mac_id, int tc_en)
1103 {
1104         dsaf_write_dev(dsaf_dev, DSAF_PFC_EN_0_REG + mac_id * 4, tc_en);
1105 }
1106
1107 static void hns_dsaf_set_pfc_pause(struct dsaf_device *dsaf_dev,
1108                                    int mac_id, int tx_en, int rx_en)
1109 {
1110         if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1111                 if (!tx_en || !rx_en)
1112                         dev_err(dsaf_dev->dev, "dsaf v1 can not close pfc!\n");
1113
1114                 return;
1115         }
1116
1117         dsaf_set_dev_bit(dsaf_dev, DSAF_PAUSE_CFG_REG + mac_id * 4,
1118                          DSAF_PFC_PAUSE_RX_EN_B, !!rx_en);
1119         dsaf_set_dev_bit(dsaf_dev, DSAF_PAUSE_CFG_REG + mac_id * 4,
1120                          DSAF_PFC_PAUSE_TX_EN_B, !!tx_en);
1121 }
1122
1123 int hns_dsaf_set_rx_mac_pause_en(struct dsaf_device *dsaf_dev, int mac_id,
1124                                  u32 en)
1125 {
1126         if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1127                 if (!en) {
1128                         dev_err(dsaf_dev->dev, "dsafv1 can't close rx_pause!\n");
1129                         return -EINVAL;
1130                 }
1131         }
1132
1133         dsaf_set_dev_bit(dsaf_dev, DSAF_PAUSE_CFG_REG + mac_id * 4,
1134                          DSAF_MAC_PAUSE_RX_EN_B, !!en);
1135
1136         return 0;
1137 }
1138
1139 void hns_dsaf_get_rx_mac_pause_en(struct dsaf_device *dsaf_dev, int mac_id,
1140                                   u32 *en)
1141 {
1142         if (AE_IS_VER1(dsaf_dev->dsaf_ver))
1143                 *en = 1;
1144         else
1145                 *en = dsaf_get_dev_bit(dsaf_dev,
1146                                        DSAF_PAUSE_CFG_REG + mac_id * 4,
1147                                        DSAF_MAC_PAUSE_RX_EN_B);
1148 }
1149
1150 /**
1151  * hns_dsaf_tbl_tcam_init - INT
1152  * @dsaf_id: dsa fabric id
1153  * @dsaf_mode
1154  */
1155 static void hns_dsaf_comm_init(struct dsaf_device *dsaf_dev)
1156 {
1157         u32 i;
1158         u32 o_dsaf_cfg;
1159         bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver);
1160
1161         o_dsaf_cfg = dsaf_read_dev(dsaf_dev, DSAF_CFG_0_REG);
1162         dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_EN_S, dsaf_dev->dsaf_en);
1163         dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_TC_MODE_S, dsaf_dev->dsaf_tc_mode);
1164         dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_CRC_EN_S, 0);
1165         dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_MIX_MODE_S, 0);
1166         dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_LOCA_ADDR_EN_S, 0);
1167         dsaf_write_dev(dsaf_dev, DSAF_CFG_0_REG, o_dsaf_cfg);
1168
1169         hns_dsaf_reg_cnt_clr_ce(dsaf_dev, 1);
1170         hns_dsaf_stp_port_type_cfg(dsaf_dev, DSAF_STP_PORT_TYPE_FORWARD);
1171
1172         /* set 22 queue per tx ppe engine, only used in switch mode */
1173         hns_dsaf_ppe_qid_cfg(dsaf_dev, DSAF_DEFAUTL_QUEUE_NUM_PER_PPE);
1174
1175         /* set promisc def queue id */
1176         hns_dsaf_mix_def_qid_cfg(dsaf_dev);
1177
1178         /* set inner loopback queue id */
1179         hns_dsaf_inner_qid_cfg(dsaf_dev);
1180
1181         /* in non switch mode, set all port to access mode */
1182         hns_dsaf_sw_port_type_cfg(dsaf_dev, DSAF_SW_PORT_TYPE_NON_VLAN);
1183
1184         /*set dsaf pfc  to 0 for parseing rx pause*/
1185         for (i = 0; i < DSAF_COMM_CHN; i++) {
1186                 hns_dsaf_pfc_en_cfg(dsaf_dev, i, 0);
1187                 hns_dsaf_set_pfc_pause(dsaf_dev, i, is_ver1, is_ver1);
1188         }
1189
1190         /*msk and  clr exception irqs */
1191         for (i = 0; i < DSAF_COMM_CHN; i++) {
1192                 hns_dsaf_int_xge_src_clr(dsaf_dev, i, 0xfffffffful);
1193                 hns_dsaf_int_ppe_src_clr(dsaf_dev, i, 0xfffffffful);
1194                 hns_dsaf_int_rocee_src_clr(dsaf_dev, i, 0xfffffffful);
1195
1196                 hns_dsaf_int_xge_msk_set(dsaf_dev, i, 0xfffffffful);
1197                 hns_dsaf_int_ppe_msk_set(dsaf_dev, i, 0xfffffffful);
1198                 hns_dsaf_int_rocee_msk_set(dsaf_dev, i, 0xfffffffful);
1199         }
1200         hns_dsaf_int_tbl_src_clr(dsaf_dev, 0xfffffffful);
1201         hns_dsaf_int_tbl_msk_set(dsaf_dev, 0xfffffffful);
1202 }
1203
1204 /**
1205  * hns_dsaf_inode_init - INT
1206  * @dsaf_id: dsa fabric id
1207  */
1208 static void hns_dsaf_inode_init(struct dsaf_device *dsaf_dev)
1209 {
1210         u32 reg;
1211         u32 tc_cfg;
1212         u32 i;
1213
1214         if (dsaf_dev->dsaf_tc_mode == HRD_DSAF_4TC_MODE)
1215                 tc_cfg = HNS_DSAF_I4TC_CFG;
1216         else
1217                 tc_cfg = HNS_DSAF_I8TC_CFG;
1218
1219         if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1220                 for (i = 0; i < DSAF_INODE_NUM; i++) {
1221                         reg = DSAF_INODE_IN_PORT_NUM_0_REG + 0x80 * i;
1222                         dsaf_set_dev_field(dsaf_dev, reg,
1223                                            DSAF_INODE_IN_PORT_NUM_M,
1224                                            DSAF_INODE_IN_PORT_NUM_S,
1225                                            i % DSAF_XGE_NUM);
1226                 }
1227         } else {
1228                 for (i = 0; i < DSAF_PORT_TYPE_NUM; i++) {
1229                         reg = DSAF_INODE_IN_PORT_NUM_0_REG + 0x80 * i;
1230                         dsaf_set_dev_field(dsaf_dev, reg,
1231                                            DSAF_INODE_IN_PORT_NUM_M,
1232                                            DSAF_INODE_IN_PORT_NUM_S, 0);
1233                         dsaf_set_dev_field(dsaf_dev, reg,
1234                                            DSAFV2_INODE_IN_PORT1_NUM_M,
1235                                            DSAFV2_INODE_IN_PORT1_NUM_S, 1);
1236                         dsaf_set_dev_field(dsaf_dev, reg,
1237                                            DSAFV2_INODE_IN_PORT2_NUM_M,
1238                                            DSAFV2_INODE_IN_PORT2_NUM_S, 2);
1239                         dsaf_set_dev_field(dsaf_dev, reg,
1240                                            DSAFV2_INODE_IN_PORT3_NUM_M,
1241                                            DSAFV2_INODE_IN_PORT3_NUM_S, 3);
1242                         dsaf_set_dev_field(dsaf_dev, reg,
1243                                            DSAFV2_INODE_IN_PORT4_NUM_M,
1244                                            DSAFV2_INODE_IN_PORT4_NUM_S, 4);
1245                         dsaf_set_dev_field(dsaf_dev, reg,
1246                                            DSAFV2_INODE_IN_PORT5_NUM_M,
1247                                            DSAFV2_INODE_IN_PORT5_NUM_S, 5);
1248                 }
1249         }
1250         for (i = 0; i < DSAF_INODE_NUM; i++) {
1251                 reg = DSAF_INODE_PRI_TC_CFG_0_REG + 0x80 * i;
1252                 dsaf_write_dev(dsaf_dev, reg, tc_cfg);
1253         }
1254 }
1255
1256 /**
1257  * hns_dsaf_sbm_init - INT
1258  * @dsaf_id: dsa fabric id
1259  */
1260 static int hns_dsaf_sbm_init(struct dsaf_device *dsaf_dev)
1261 {
1262         u32 flag;
1263         u32 finish_msk;
1264         u32 cnt = 0;
1265         int ret;
1266
1267         if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1268                 hns_dsaf_sbm_bp_wl_cfg(dsaf_dev);
1269                 finish_msk = DSAF_SRAM_INIT_OVER_M;
1270         } else {
1271                 hns_dsafv2_sbm_bp_wl_cfg(dsaf_dev);
1272                 finish_msk = DSAFV2_SRAM_INIT_OVER_M;
1273         }
1274
1275         /* enable sbm chanel, disable sbm chanel shcut function*/
1276         hns_dsaf_sbm_cfg(dsaf_dev);
1277
1278         /* enable sbm mib */
1279         ret = hns_dsaf_sbm_cfg_mib_en(dsaf_dev);
1280         if (ret) {
1281                 dev_err(dsaf_dev->dev,
1282                         "hns_dsaf_sbm_cfg_mib_en fail,%s, ret=%d\n",
1283                         dsaf_dev->ae_dev.name, ret);
1284                 return ret;
1285         }
1286
1287         /* enable sbm initial link sram */
1288         hns_dsaf_sbm_link_sram_init_en(dsaf_dev);
1289
1290         do {
1291                 usleep_range(200, 210);/*udelay(200);*/
1292                 flag = dsaf_get_dev_field(dsaf_dev, DSAF_SRAM_INIT_OVER_0_REG,
1293                                           finish_msk, DSAF_SRAM_INIT_OVER_S);
1294                 cnt++;
1295         } while (flag != (finish_msk >> DSAF_SRAM_INIT_OVER_S) &&
1296                  cnt < DSAF_CFG_READ_CNT);
1297
1298         if (flag != (finish_msk >> DSAF_SRAM_INIT_OVER_S)) {
1299                 dev_err(dsaf_dev->dev,
1300                         "hns_dsaf_sbm_init fail %s, flag=%d, cnt=%d\n",
1301                         dsaf_dev->ae_dev.name, flag, cnt);
1302                 return -ENODEV;
1303         }
1304
1305         hns_dsaf_rocee_bp_en(dsaf_dev);
1306
1307         return 0;
1308 }
1309
1310 /**
1311  * hns_dsaf_tbl_init - INT
1312  * @dsaf_id: dsa fabric id
1313  */
1314 static void hns_dsaf_tbl_init(struct dsaf_device *dsaf_dev)
1315 {
1316         hns_dsaf_tbl_stat_en(dsaf_dev);
1317
1318         hns_dsaf_tbl_tcam_init(dsaf_dev);
1319         hns_dsaf_tbl_line_init(dsaf_dev);
1320 }
1321
1322 /**
1323  * hns_dsaf_voq_init - INT
1324  * @dsaf_id: dsa fabric id
1325  */
1326 static void hns_dsaf_voq_init(struct dsaf_device *dsaf_dev)
1327 {
1328         hns_dsaf_voq_bp_all_thrd_cfg(dsaf_dev);
1329 }
1330
1331 /**
1332  * hns_dsaf_init_hw - init dsa fabric hardware
1333  * @dsaf_dev: dsa fabric device struct pointer
1334  */
1335 static int hns_dsaf_init_hw(struct dsaf_device *dsaf_dev)
1336 {
1337         int ret;
1338
1339         dev_dbg(dsaf_dev->dev,
1340                 "hns_dsaf_init_hw begin %s !\n", dsaf_dev->ae_dev.name);
1341
1342         dsaf_dev->misc_op->dsaf_reset(dsaf_dev, 0);
1343         mdelay(10);
1344         dsaf_dev->misc_op->dsaf_reset(dsaf_dev, 1);
1345
1346         hns_dsaf_comm_init(dsaf_dev);
1347
1348         /*init XBAR_INODE*/
1349         hns_dsaf_inode_init(dsaf_dev);
1350
1351         /*init SBM*/
1352         ret = hns_dsaf_sbm_init(dsaf_dev);
1353         if (ret)
1354                 return ret;
1355
1356         /*init TBL*/
1357         hns_dsaf_tbl_init(dsaf_dev);
1358
1359         /*init VOQ*/
1360         hns_dsaf_voq_init(dsaf_dev);
1361
1362         return 0;
1363 }
1364
1365 /**
1366  * hns_dsaf_remove_hw - uninit dsa fabric hardware
1367  * @dsaf_dev: dsa fabric device struct pointer
1368  */
1369 static void hns_dsaf_remove_hw(struct dsaf_device *dsaf_dev)
1370 {
1371         /*reset*/
1372         dsaf_dev->misc_op->dsaf_reset(dsaf_dev, 0);
1373 }
1374
1375 /**
1376  * hns_dsaf_init - init dsa fabric
1377  * @dsaf_dev: dsa fabric device struct pointer
1378  * retuen 0 - success , negative --fail
1379  */
1380 static int hns_dsaf_init(struct dsaf_device *dsaf_dev)
1381 {
1382         struct dsaf_drv_priv *priv =
1383             (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1384         u32 i;
1385         int ret;
1386
1387         if (HNS_DSAF_IS_DEBUG(dsaf_dev))
1388                 return 0;
1389
1390         spin_lock_init(&dsaf_dev->tcam_lock);
1391         ret = hns_dsaf_init_hw(dsaf_dev);
1392         if (ret)
1393                 return ret;
1394
1395         /* malloc mem for tcam mac key(vlan+mac) */
1396         priv->soft_mac_tbl = vzalloc(sizeof(*priv->soft_mac_tbl)
1397                   * DSAF_TCAM_SUM);
1398         if (!priv->soft_mac_tbl) {
1399                 ret = -ENOMEM;
1400                 goto remove_hw;
1401         }
1402
1403         /*all entry invall */
1404         for (i = 0; i < DSAF_TCAM_SUM; i++)
1405                 (priv->soft_mac_tbl + i)->index = DSAF_INVALID_ENTRY_IDX;
1406
1407         return 0;
1408
1409 remove_hw:
1410         hns_dsaf_remove_hw(dsaf_dev);
1411         return ret;
1412 }
1413
1414 /**
1415  * hns_dsaf_free - free dsa fabric
1416  * @dsaf_dev: dsa fabric device struct pointer
1417  */
1418 static void hns_dsaf_free(struct dsaf_device *dsaf_dev)
1419 {
1420         struct dsaf_drv_priv *priv =
1421             (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1422
1423         hns_dsaf_remove_hw(dsaf_dev);
1424
1425         /* free all mac mem */
1426         vfree(priv->soft_mac_tbl);
1427         priv->soft_mac_tbl = NULL;
1428 }
1429
1430 /**
1431  * hns_dsaf_find_soft_mac_entry - find dsa fabric soft entry
1432  * @dsaf_dev: dsa fabric device struct pointer
1433  * @mac_key: mac entry struct pointer
1434  */
1435 static u16 hns_dsaf_find_soft_mac_entry(
1436         struct dsaf_device *dsaf_dev,
1437         struct dsaf_drv_tbl_tcam_key *mac_key)
1438 {
1439         struct dsaf_drv_priv *priv =
1440             (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1441         struct dsaf_drv_soft_mac_tbl *soft_mac_entry;
1442         u32 i;
1443
1444         soft_mac_entry = priv->soft_mac_tbl;
1445         for (i = 0; i < DSAF_TCAM_SUM; i++) {
1446                 /* invall tab entry */
1447                 if ((soft_mac_entry->index != DSAF_INVALID_ENTRY_IDX) &&
1448                     (soft_mac_entry->tcam_key.high.val == mac_key->high.val) &&
1449                     (soft_mac_entry->tcam_key.low.val == mac_key->low.val))
1450                         /* return find result --soft index */
1451                         return soft_mac_entry->index;
1452
1453                 soft_mac_entry++;
1454         }
1455         return DSAF_INVALID_ENTRY_IDX;
1456 }
1457
1458 /**
1459  * hns_dsaf_find_empty_mac_entry - search dsa fabric soft empty-entry
1460  * @dsaf_dev: dsa fabric device struct pointer
1461  */
1462 static u16 hns_dsaf_find_empty_mac_entry(struct dsaf_device *dsaf_dev)
1463 {
1464         struct dsaf_drv_priv *priv =
1465             (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1466         struct dsaf_drv_soft_mac_tbl *soft_mac_entry;
1467         u32 i;
1468
1469         soft_mac_entry = priv->soft_mac_tbl;
1470         for (i = 0; i < DSAF_TCAM_SUM; i++) {
1471                 /* inv all entry */
1472                 if (soft_mac_entry->index == DSAF_INVALID_ENTRY_IDX)
1473                         /* return find result --soft index */
1474                         return i;
1475
1476                 soft_mac_entry++;
1477         }
1478         return DSAF_INVALID_ENTRY_IDX;
1479 }
1480
1481 /**
1482  * hns_dsaf_set_mac_key - set mac key
1483  * @dsaf_dev: dsa fabric device struct pointer
1484  * @mac_key: tcam key pointer
1485  * @vlan_id: vlan id
1486  * @in_port_num: input port num
1487  * @addr: mac addr
1488  */
1489 static void hns_dsaf_set_mac_key(
1490         struct dsaf_device *dsaf_dev,
1491         struct dsaf_drv_tbl_tcam_key *mac_key, u16 vlan_id, u8 in_port_num,
1492         u8 *addr)
1493 {
1494         u8 port;
1495
1496         if (dsaf_dev->dsaf_mode <= DSAF_MODE_ENABLE)
1497                 /*DSAF mode : in port id fixed 0*/
1498                 port = 0;
1499         else
1500                 /*non-dsaf mode*/
1501                 port = in_port_num;
1502
1503         mac_key->high.bits.mac_0 = addr[0];
1504         mac_key->high.bits.mac_1 = addr[1];
1505         mac_key->high.bits.mac_2 = addr[2];
1506         mac_key->high.bits.mac_3 = addr[3];
1507         mac_key->low.bits.mac_4 = addr[4];
1508         mac_key->low.bits.mac_5 = addr[5];
1509         mac_key->low.bits.vlan = vlan_id;
1510         mac_key->low.bits.port = port;
1511 }
1512
1513 /**
1514  * hns_dsaf_set_mac_uc_entry - set mac uc-entry
1515  * @dsaf_dev: dsa fabric device struct pointer
1516  * @mac_entry: uc-mac entry
1517  */
1518 int hns_dsaf_set_mac_uc_entry(
1519         struct dsaf_device *dsaf_dev,
1520         struct dsaf_drv_mac_single_dest_entry *mac_entry)
1521 {
1522         u16 entry_index = DSAF_INVALID_ENTRY_IDX;
1523         struct dsaf_drv_tbl_tcam_key mac_key;
1524         struct dsaf_tbl_tcam_ucast_cfg mac_data;
1525         struct dsaf_drv_priv *priv =
1526             (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1527         struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl;
1528
1529         /* mac addr check */
1530         if (MAC_IS_ALL_ZEROS(mac_entry->addr) ||
1531             MAC_IS_BROADCAST(mac_entry->addr) ||
1532             MAC_IS_MULTICAST(mac_entry->addr)) {
1533                 dev_err(dsaf_dev->dev, "set_uc %s Mac %pM err!\n",
1534                         dsaf_dev->ae_dev.name, mac_entry->addr);
1535                 return -EINVAL;
1536         }
1537
1538         /* config key */
1539         hns_dsaf_set_mac_key(dsaf_dev, &mac_key, mac_entry->in_vlan_id,
1540                              mac_entry->in_port_num, mac_entry->addr);
1541
1542         /* entry ie exist? */
1543         entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1544         if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1545                 /*if has not inv entry,find a empty entry */
1546                 entry_index = hns_dsaf_find_empty_mac_entry(dsaf_dev);
1547                 if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1548                         /* has not empty,return error */
1549                         dev_err(dsaf_dev->dev,
1550                                 "set_uc_entry failed, %s Mac key(%#x:%#x)\n",
1551                                 dsaf_dev->ae_dev.name,
1552                                 mac_key.high.val, mac_key.low.val);
1553                         return -EINVAL;
1554                 }
1555         }
1556
1557         dev_dbg(dsaf_dev->dev,
1558                 "set_uc_entry, %s Mac key(%#x:%#x) entry_index%d\n",
1559                 dsaf_dev->ae_dev.name, mac_key.high.val,
1560                 mac_key.low.val, entry_index);
1561
1562         /* config hardware entry */
1563         mac_data.tbl_ucast_item_vld = 1;
1564         mac_data.tbl_ucast_mac_discard = 0;
1565         mac_data.tbl_ucast_old_en = 0;
1566         /* default config dvc to 0 */
1567         mac_data.tbl_ucast_dvc = 0;
1568         mac_data.tbl_ucast_out_port = mac_entry->port_num;
1569         hns_dsaf_tcam_uc_cfg(
1570                 dsaf_dev, entry_index,
1571                 (struct dsaf_tbl_tcam_data *)(&mac_key), &mac_data);
1572
1573         /* config software entry */
1574         soft_mac_entry += entry_index;
1575         soft_mac_entry->index = entry_index;
1576         soft_mac_entry->tcam_key.high.val = mac_key.high.val;
1577         soft_mac_entry->tcam_key.low.val = mac_key.low.val;
1578
1579         return 0;
1580 }
1581
1582 /**
1583  * hns_dsaf_set_mac_mc_entry - set mac mc-entry
1584  * @dsaf_dev: dsa fabric device struct pointer
1585  * @mac_entry: mc-mac entry
1586  */
1587 int hns_dsaf_set_mac_mc_entry(
1588         struct dsaf_device *dsaf_dev,
1589         struct dsaf_drv_mac_multi_dest_entry *mac_entry)
1590 {
1591         u16 entry_index = DSAF_INVALID_ENTRY_IDX;
1592         struct dsaf_drv_tbl_tcam_key mac_key;
1593         struct dsaf_tbl_tcam_mcast_cfg mac_data;
1594         struct dsaf_drv_priv *priv =
1595             (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1596         struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl;
1597         struct dsaf_drv_tbl_tcam_key tmp_mac_key;
1598
1599         /* mac addr check */
1600         if (MAC_IS_ALL_ZEROS(mac_entry->addr)) {
1601                 dev_err(dsaf_dev->dev, "set uc %s Mac %pM err!\n",
1602                         dsaf_dev->ae_dev.name, mac_entry->addr);
1603                 return -EINVAL;
1604         }
1605
1606         /*config key */
1607         hns_dsaf_set_mac_key(dsaf_dev, &mac_key,
1608                              mac_entry->in_vlan_id,
1609                              mac_entry->in_port_num, mac_entry->addr);
1610
1611         /* entry ie exist? */
1612         entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1613         if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1614                 /*if hasnot, find enpty entry*/
1615                 entry_index = hns_dsaf_find_empty_mac_entry(dsaf_dev);
1616                 if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1617                         /*if hasnot empty, error*/
1618                         dev_err(dsaf_dev->dev,
1619                                 "set_uc_entry failed, %s Mac key(%#x:%#x)\n",
1620                                 dsaf_dev->ae_dev.name,
1621                                 mac_key.high.val, mac_key.low.val);
1622                         return -EINVAL;
1623                 }
1624
1625                 /* config hardware entry */
1626                 memset(mac_data.tbl_mcast_port_msk,
1627                        0, sizeof(mac_data.tbl_mcast_port_msk));
1628         } else {
1629                 /* config hardware entry */
1630                 hns_dsaf_tcam_mc_get(
1631                         dsaf_dev, entry_index,
1632                         (struct dsaf_tbl_tcam_data *)(&tmp_mac_key), &mac_data);
1633         }
1634         mac_data.tbl_mcast_old_en = 0;
1635         mac_data.tbl_mcast_item_vld = 1;
1636         dsaf_set_field(mac_data.tbl_mcast_port_msk[0],
1637                        0x3F, 0, mac_entry->port_mask[0]);
1638
1639         dev_dbg(dsaf_dev->dev,
1640                 "set_uc_entry, %s key(%#x:%#x) entry_index%d\n",
1641                 dsaf_dev->ae_dev.name, mac_key.high.val,
1642                 mac_key.low.val, entry_index);
1643
1644         hns_dsaf_tcam_mc_cfg(
1645                 dsaf_dev, entry_index,
1646                 (struct dsaf_tbl_tcam_data *)(&mac_key), &mac_data);
1647
1648         /* config software entry */
1649         soft_mac_entry += entry_index;
1650         soft_mac_entry->index = entry_index;
1651         soft_mac_entry->tcam_key.high.val = mac_key.high.val;
1652         soft_mac_entry->tcam_key.low.val = mac_key.low.val;
1653
1654         return 0;
1655 }
1656
1657 /**
1658  * hns_dsaf_add_mac_mc_port - add mac mc-port
1659  * @dsaf_dev: dsa fabric device struct pointer
1660  * @mac_entry: mc-mac entry
1661  */
1662 int hns_dsaf_add_mac_mc_port(struct dsaf_device *dsaf_dev,
1663                              struct dsaf_drv_mac_single_dest_entry *mac_entry)
1664 {
1665         u16 entry_index = DSAF_INVALID_ENTRY_IDX;
1666         struct dsaf_drv_tbl_tcam_key mac_key;
1667         struct dsaf_tbl_tcam_mcast_cfg mac_data;
1668         struct dsaf_drv_priv *priv =
1669             (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1670         struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl;
1671         struct dsaf_drv_tbl_tcam_key tmp_mac_key;
1672         int mskid;
1673
1674         /*chechk mac addr */
1675         if (MAC_IS_ALL_ZEROS(mac_entry->addr)) {
1676                 dev_err(dsaf_dev->dev, "set_entry failed,addr %pM!\n",
1677                         mac_entry->addr);
1678                 return -EINVAL;
1679         }
1680
1681         /*config key */
1682         hns_dsaf_set_mac_key(
1683                 dsaf_dev, &mac_key, mac_entry->in_vlan_id,
1684                 mac_entry->in_port_num, mac_entry->addr);
1685
1686         memset(&mac_data, 0, sizeof(struct dsaf_tbl_tcam_mcast_cfg));
1687
1688         /*check exist? */
1689         entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1690         if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1691                 /*if hasnot , find a empty*/
1692                 entry_index = hns_dsaf_find_empty_mac_entry(dsaf_dev);
1693                 if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1694                         /*if hasnot empty, error*/
1695                         dev_err(dsaf_dev->dev,
1696                                 "set_uc_entry failed, %s Mac key(%#x:%#x)\n",
1697                                 dsaf_dev->ae_dev.name, mac_key.high.val,
1698                                 mac_key.low.val);
1699                         return -EINVAL;
1700                 }
1701         } else {
1702                 /*if exist, add in */
1703                 hns_dsaf_tcam_mc_get(
1704                         dsaf_dev, entry_index,
1705                         (struct dsaf_tbl_tcam_data *)(&tmp_mac_key), &mac_data);
1706         }
1707         /* config hardware entry */
1708         if (mac_entry->port_num < DSAF_SERVICE_NW_NUM) {
1709                 mskid = mac_entry->port_num;
1710         } else if (mac_entry->port_num >= DSAF_BASE_INNER_PORT_NUM) {
1711                 mskid = mac_entry->port_num -
1712                         DSAF_BASE_INNER_PORT_NUM + DSAF_SERVICE_NW_NUM;
1713         } else {
1714                 dev_err(dsaf_dev->dev,
1715                         "%s,pnum(%d)error,key(%#x:%#x)\n",
1716                         dsaf_dev->ae_dev.name, mac_entry->port_num,
1717                         mac_key.high.val, mac_key.low.val);
1718                 return -EINVAL;
1719         }
1720         dsaf_set_bit(mac_data.tbl_mcast_port_msk[mskid / 32], mskid % 32, 1);
1721         mac_data.tbl_mcast_old_en = 0;
1722         mac_data.tbl_mcast_item_vld = 1;
1723
1724         dev_dbg(dsaf_dev->dev,
1725                 "set_uc_entry, %s Mac key(%#x:%#x) entry_index%d\n",
1726                 dsaf_dev->ae_dev.name, mac_key.high.val,
1727                 mac_key.low.val, entry_index);
1728
1729         hns_dsaf_tcam_mc_cfg(
1730                 dsaf_dev, entry_index,
1731                 (struct dsaf_tbl_tcam_data *)(&mac_key), &mac_data);
1732
1733         /*config software entry */
1734         soft_mac_entry += entry_index;
1735         soft_mac_entry->index = entry_index;
1736         soft_mac_entry->tcam_key.high.val = mac_key.high.val;
1737         soft_mac_entry->tcam_key.low.val = mac_key.low.val;
1738
1739         return 0;
1740 }
1741
1742 /**
1743  * hns_dsaf_del_mac_entry - del mac mc-port
1744  * @dsaf_dev: dsa fabric device struct pointer
1745  * @vlan_id: vlian id
1746  * @in_port_num: input port num
1747  * @addr : mac addr
1748  */
1749 int hns_dsaf_del_mac_entry(struct dsaf_device *dsaf_dev, u16 vlan_id,
1750                            u8 in_port_num, u8 *addr)
1751 {
1752         u16 entry_index = DSAF_INVALID_ENTRY_IDX;
1753         struct dsaf_drv_tbl_tcam_key mac_key;
1754         struct dsaf_drv_priv *priv =
1755             (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1756         struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl;
1757
1758         /*check mac addr */
1759         if (MAC_IS_ALL_ZEROS(addr) || MAC_IS_BROADCAST(addr)) {
1760                 dev_err(dsaf_dev->dev, "del_entry failed,addr %pM!\n",
1761                         addr);
1762                 return -EINVAL;
1763         }
1764
1765         /*config key */
1766         hns_dsaf_set_mac_key(dsaf_dev, &mac_key, vlan_id, in_port_num, addr);
1767
1768         /*exist ?*/
1769         entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1770         if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1771                 /*not exist, error */
1772                 dev_err(dsaf_dev->dev,
1773                         "del_mac_entry failed, %s Mac key(%#x:%#x)\n",
1774                         dsaf_dev->ae_dev.name,
1775                         mac_key.high.val, mac_key.low.val);
1776                 return -EINVAL;
1777         }
1778         dev_dbg(dsaf_dev->dev,
1779                 "del_mac_entry, %s Mac key(%#x:%#x) entry_index%d\n",
1780                 dsaf_dev->ae_dev.name, mac_key.high.val,
1781                 mac_key.low.val, entry_index);
1782
1783         /*do del opt*/
1784         hns_dsaf_tcam_mc_invld(dsaf_dev, entry_index);
1785
1786         /*del soft emtry */
1787         soft_mac_entry += entry_index;
1788         soft_mac_entry->index = DSAF_INVALID_ENTRY_IDX;
1789
1790         return 0;
1791 }
1792
1793 /**
1794  * hns_dsaf_del_mac_mc_port - del mac mc- port
1795  * @dsaf_dev: dsa fabric device struct pointer
1796  * @mac_entry: mac entry
1797  */
1798 int hns_dsaf_del_mac_mc_port(struct dsaf_device *dsaf_dev,
1799                              struct dsaf_drv_mac_single_dest_entry *mac_entry)
1800 {
1801         u16 entry_index = DSAF_INVALID_ENTRY_IDX;
1802         struct dsaf_drv_tbl_tcam_key mac_key;
1803         struct dsaf_drv_priv *priv =
1804             (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1805         struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl;
1806         u16 vlan_id;
1807         u8 in_port_num;
1808         struct dsaf_tbl_tcam_mcast_cfg mac_data;
1809         struct dsaf_drv_tbl_tcam_key tmp_mac_key;
1810         int mskid;
1811         const u8 empty_msk[sizeof(mac_data.tbl_mcast_port_msk)] = {0};
1812
1813         if (!(void *)mac_entry) {
1814                 dev_err(dsaf_dev->dev,
1815                         "hns_dsaf_del_mac_mc_port mac_entry is NULL\n");
1816                 return -EINVAL;
1817         }
1818
1819         /*get key info*/
1820         vlan_id = mac_entry->in_vlan_id;
1821         in_port_num = mac_entry->in_port_num;
1822
1823         /*check mac addr */
1824         if (MAC_IS_ALL_ZEROS(mac_entry->addr)) {
1825                 dev_err(dsaf_dev->dev, "del_port failed, addr %pM!\n",
1826                         mac_entry->addr);
1827                 return -EINVAL;
1828         }
1829
1830         /*config key */
1831         hns_dsaf_set_mac_key(dsaf_dev, &mac_key, vlan_id, in_port_num,
1832                              mac_entry->addr);
1833
1834         /*check is exist? */
1835         entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1836         if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1837                 /*find none */
1838                 dev_err(dsaf_dev->dev,
1839                         "find_soft_mac_entry failed, %s Mac key(%#x:%#x)\n",
1840                         dsaf_dev->ae_dev.name,
1841                         mac_key.high.val, mac_key.low.val);
1842                 return -EINVAL;
1843         }
1844
1845         dev_dbg(dsaf_dev->dev,
1846                 "del_mac_mc_port, %s key(%#x:%#x) index%d\n",
1847                 dsaf_dev->ae_dev.name, mac_key.high.val,
1848                 mac_key.low.val, entry_index);
1849
1850         /*read entry*/
1851         hns_dsaf_tcam_mc_get(
1852                 dsaf_dev, entry_index,
1853                 (struct dsaf_tbl_tcam_data *)(&tmp_mac_key), &mac_data);
1854
1855         /*del the port*/
1856         if (mac_entry->port_num < DSAF_SERVICE_NW_NUM) {
1857                 mskid = mac_entry->port_num;
1858         } else if (mac_entry->port_num >= DSAF_BASE_INNER_PORT_NUM) {
1859                 mskid = mac_entry->port_num -
1860                         DSAF_BASE_INNER_PORT_NUM + DSAF_SERVICE_NW_NUM;
1861         } else {
1862                 dev_err(dsaf_dev->dev,
1863                         "%s,pnum(%d)error,key(%#x:%#x)\n",
1864                         dsaf_dev->ae_dev.name, mac_entry->port_num,
1865                         mac_key.high.val, mac_key.low.val);
1866                 return -EINVAL;
1867         }
1868         dsaf_set_bit(mac_data.tbl_mcast_port_msk[mskid / 32], mskid % 32, 0);
1869
1870         /*check non port, do del entry */
1871         if (!memcmp(mac_data.tbl_mcast_port_msk, empty_msk,
1872                     sizeof(mac_data.tbl_mcast_port_msk))) {
1873                 hns_dsaf_tcam_mc_invld(dsaf_dev, entry_index);
1874
1875                 /* del soft entry */
1876                 soft_mac_entry += entry_index;
1877                 soft_mac_entry->index = DSAF_INVALID_ENTRY_IDX;
1878         } else { /* not zer, just del port, updata*/
1879                 hns_dsaf_tcam_mc_cfg(
1880                         dsaf_dev, entry_index,
1881                         (struct dsaf_tbl_tcam_data *)(&mac_key), &mac_data);
1882         }
1883
1884         return 0;
1885 }
1886
1887 /**
1888  * hns_dsaf_get_mac_uc_entry - get mac uc entry
1889  * @dsaf_dev: dsa fabric device struct pointer
1890  * @mac_entry: mac entry
1891  */
1892 int hns_dsaf_get_mac_uc_entry(struct dsaf_device *dsaf_dev,
1893                               struct dsaf_drv_mac_single_dest_entry *mac_entry)
1894 {
1895         u16 entry_index = DSAF_INVALID_ENTRY_IDX;
1896         struct dsaf_drv_tbl_tcam_key mac_key;
1897
1898         struct dsaf_tbl_tcam_ucast_cfg mac_data;
1899
1900         /* check macaddr */
1901         if (MAC_IS_ALL_ZEROS(mac_entry->addr) ||
1902             MAC_IS_BROADCAST(mac_entry->addr)) {
1903                 dev_err(dsaf_dev->dev, "get_entry failed,addr %pM\n",
1904                         mac_entry->addr);
1905                 return -EINVAL;
1906         }
1907
1908         /*config key */
1909         hns_dsaf_set_mac_key(dsaf_dev, &mac_key, mac_entry->in_vlan_id,
1910                              mac_entry->in_port_num, mac_entry->addr);
1911
1912         /*check exist? */
1913         entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1914         if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1915                 /*find none, error */
1916                 dev_err(dsaf_dev->dev,
1917                         "get_uc_entry failed, %s Mac key(%#x:%#x)\n",
1918                         dsaf_dev->ae_dev.name,
1919                         mac_key.high.val, mac_key.low.val);
1920                 return -EINVAL;
1921         }
1922         dev_dbg(dsaf_dev->dev,
1923                 "get_uc_entry, %s Mac key(%#x:%#x) entry_index%d\n",
1924                 dsaf_dev->ae_dev.name, mac_key.high.val,
1925                 mac_key.low.val, entry_index);
1926
1927         /*read entry*/
1928         hns_dsaf_tcam_uc_get(dsaf_dev, entry_index,
1929                              (struct dsaf_tbl_tcam_data *)&mac_key, &mac_data);
1930         mac_entry->port_num = mac_data.tbl_ucast_out_port;
1931
1932         return 0;
1933 }
1934
1935 /**
1936  * hns_dsaf_get_mac_mc_entry - get mac mc entry
1937  * @dsaf_dev: dsa fabric device struct pointer
1938  * @mac_entry: mac entry
1939  */
1940 int hns_dsaf_get_mac_mc_entry(struct dsaf_device *dsaf_dev,
1941                               struct dsaf_drv_mac_multi_dest_entry *mac_entry)
1942 {
1943         u16 entry_index = DSAF_INVALID_ENTRY_IDX;
1944         struct dsaf_drv_tbl_tcam_key mac_key;
1945
1946         struct dsaf_tbl_tcam_mcast_cfg mac_data;
1947
1948         /*check mac addr */
1949         if (MAC_IS_ALL_ZEROS(mac_entry->addr) ||
1950             MAC_IS_BROADCAST(mac_entry->addr)) {
1951                 dev_err(dsaf_dev->dev, "get_entry failed,addr %pM\n",
1952                         mac_entry->addr);
1953                 return -EINVAL;
1954         }
1955
1956         /*config key */
1957         hns_dsaf_set_mac_key(dsaf_dev, &mac_key, mac_entry->in_vlan_id,
1958                              mac_entry->in_port_num, mac_entry->addr);
1959
1960         /*check exist? */
1961         entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1962         if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1963                 /* find none, error */
1964                 dev_err(dsaf_dev->dev,
1965                         "get_mac_uc_entry failed, %s Mac key(%#x:%#x)\n",
1966                         dsaf_dev->ae_dev.name, mac_key.high.val,
1967                         mac_key.low.val);
1968                 return -EINVAL;
1969         }
1970         dev_dbg(dsaf_dev->dev,
1971                 "get_mac_uc_entry, %s Mac key(%#x:%#x) entry_index%d\n",
1972                 dsaf_dev->ae_dev.name, mac_key.high.val,
1973                 mac_key.low.val, entry_index);
1974
1975         /*read entry */
1976         hns_dsaf_tcam_mc_get(dsaf_dev, entry_index,
1977                              (struct dsaf_tbl_tcam_data *)&mac_key, &mac_data);
1978
1979         mac_entry->port_mask[0] = mac_data.tbl_mcast_port_msk[0] & 0x3F;
1980         return 0;
1981 }
1982
1983 /**
1984  * hns_dsaf_get_mac_entry_by_index - get mac entry by tab index
1985  * @dsaf_dev: dsa fabric device struct pointer
1986  * @entry_index: tab entry index
1987  * @mac_entry: mac entry
1988  */
1989 int hns_dsaf_get_mac_entry_by_index(
1990         struct dsaf_device *dsaf_dev,
1991         u16 entry_index, struct dsaf_drv_mac_multi_dest_entry *mac_entry)
1992 {
1993         struct dsaf_drv_tbl_tcam_key mac_key;
1994
1995         struct dsaf_tbl_tcam_mcast_cfg mac_data;
1996         struct dsaf_tbl_tcam_ucast_cfg mac_uc_data;
1997         char mac_addr[MAC_NUM_OCTETS_PER_ADDR] = {0};
1998
1999         if (entry_index >= DSAF_TCAM_SUM) {
2000                 /* find none, del error */
2001                 dev_err(dsaf_dev->dev, "get_uc_entry failed, %s\n",
2002                         dsaf_dev->ae_dev.name);
2003                 return -EINVAL;
2004         }
2005
2006         /* mc entry, do read opt */
2007         hns_dsaf_tcam_mc_get(dsaf_dev, entry_index,
2008                              (struct dsaf_tbl_tcam_data *)&mac_key, &mac_data);
2009
2010         mac_entry->port_mask[0] = mac_data.tbl_mcast_port_msk[0] & 0x3F;
2011
2012         /***get mac addr*/
2013         mac_addr[0] = mac_key.high.bits.mac_0;
2014         mac_addr[1] = mac_key.high.bits.mac_1;
2015         mac_addr[2] = mac_key.high.bits.mac_2;
2016         mac_addr[3] = mac_key.high.bits.mac_3;
2017         mac_addr[4] = mac_key.low.bits.mac_4;
2018         mac_addr[5] = mac_key.low.bits.mac_5;
2019         /**is mc or uc*/
2020         if (MAC_IS_MULTICAST((u8 *)mac_addr) ||
2021             MAC_IS_L3_MULTICAST((u8 *)mac_addr)) {
2022                 /**mc donot do*/
2023         } else {
2024                 /*is not mc, just uc... */
2025                 hns_dsaf_tcam_uc_get(dsaf_dev, entry_index,
2026                                      (struct dsaf_tbl_tcam_data *)&mac_key,
2027                                      &mac_uc_data);
2028                 mac_entry->port_mask[0] = (1 << mac_uc_data.tbl_ucast_out_port);
2029         }
2030
2031         return 0;
2032 }
2033
2034 static struct dsaf_device *hns_dsaf_alloc_dev(struct device *dev,
2035                                               size_t sizeof_priv)
2036 {
2037         struct dsaf_device *dsaf_dev;
2038
2039         dsaf_dev = devm_kzalloc(dev,
2040                                 sizeof(*dsaf_dev) + sizeof_priv, GFP_KERNEL);
2041         if (unlikely(!dsaf_dev)) {
2042                 dsaf_dev = ERR_PTR(-ENOMEM);
2043         } else {
2044                 dsaf_dev->dev = dev;
2045                 dev_set_drvdata(dev, dsaf_dev);
2046         }
2047
2048         return dsaf_dev;
2049 }
2050
2051 /**
2052  * hns_dsaf_free_dev - free dev mem
2053  * @dev: struct device pointer
2054  */
2055 static void hns_dsaf_free_dev(struct dsaf_device *dsaf_dev)
2056 {
2057         (void)dev_set_drvdata(dsaf_dev->dev, NULL);
2058 }
2059
2060 /**
2061  * dsaf_pfc_unit_cnt - set pfc unit count
2062  * @dsaf_id: dsa fabric id
2063  * @pport_rate:  value array
2064  * @pdsaf_pfc_unit_cnt:  value array
2065  */
2066 static void hns_dsaf_pfc_unit_cnt(struct dsaf_device *dsaf_dev, int  mac_id,
2067                                   enum dsaf_port_rate_mode rate)
2068 {
2069         u32 unit_cnt;
2070
2071         switch (rate) {
2072         case DSAF_PORT_RATE_10000:
2073                 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_XGE;
2074                 break;
2075         case DSAF_PORT_RATE_1000:
2076                 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_GE_1000;
2077                 break;
2078         case DSAF_PORT_RATE_2500:
2079                 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_GE_1000;
2080                 break;
2081         default:
2082                 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_XGE;
2083         }
2084
2085         dsaf_set_dev_field(dsaf_dev,
2086                            (DSAF_PFC_UNIT_CNT_0_REG + 0x4 * (u64)mac_id),
2087                            DSAF_PFC_UNINT_CNT_M, DSAF_PFC_UNINT_CNT_S,
2088                            unit_cnt);
2089 }
2090
2091 /**
2092  * dsaf_port_work_rate_cfg - fifo
2093  * @dsaf_id: dsa fabric id
2094  * @xge_ge_work_mode
2095  */
2096 void hns_dsaf_port_work_rate_cfg(struct dsaf_device *dsaf_dev, int mac_id,
2097                                  enum dsaf_port_rate_mode rate_mode)
2098 {
2099         u32 port_work_mode;
2100
2101         port_work_mode = dsaf_read_dev(
2102                 dsaf_dev, DSAF_XGE_GE_WORK_MODE_0_REG + 0x4 * (u64)mac_id);
2103
2104         if (rate_mode == DSAF_PORT_RATE_10000)
2105                 dsaf_set_bit(port_work_mode, DSAF_XGE_GE_WORK_MODE_S, 1);
2106         else
2107                 dsaf_set_bit(port_work_mode, DSAF_XGE_GE_WORK_MODE_S, 0);
2108
2109         dsaf_write_dev(dsaf_dev,
2110                        DSAF_XGE_GE_WORK_MODE_0_REG + 0x4 * (u64)mac_id,
2111                        port_work_mode);
2112
2113         hns_dsaf_pfc_unit_cnt(dsaf_dev, mac_id, rate_mode);
2114 }
2115
2116 /**
2117  * hns_dsaf_fix_mac_mode - dsaf modify mac mode
2118  * @mac_cb: mac contrl block
2119  */
2120 void hns_dsaf_fix_mac_mode(struct hns_mac_cb *mac_cb)
2121 {
2122         enum dsaf_port_rate_mode mode;
2123         struct dsaf_device *dsaf_dev = mac_cb->dsaf_dev;
2124         int mac_id = mac_cb->mac_id;
2125
2126         if (mac_cb->mac_type != HNAE_PORT_SERVICE)
2127                 return;
2128         if (mac_cb->phy_if == PHY_INTERFACE_MODE_XGMII)
2129                 mode = DSAF_PORT_RATE_10000;
2130         else
2131                 mode = DSAF_PORT_RATE_1000;
2132
2133         hns_dsaf_port_work_rate_cfg(dsaf_dev, mac_id, mode);
2134 }
2135
2136 static u32 hns_dsaf_get_inode_prio_reg(int index)
2137 {
2138         int base_index, offset;
2139         u32 base_addr = DSAF_INODE_IN_PRIO_PAUSE_BASE_REG;
2140
2141         base_index = (index + 1) / DSAF_REG_PER_ZONE;
2142         offset = (index + 1) % DSAF_REG_PER_ZONE;
2143
2144         return base_addr + DSAF_INODE_IN_PRIO_PAUSE_BASE_OFFSET * base_index +
2145                 DSAF_INODE_IN_PRIO_PAUSE_OFFSET * offset;
2146 }
2147
2148 void hns_dsaf_update_stats(struct dsaf_device *dsaf_dev, u32 node_num)
2149 {
2150         struct dsaf_hw_stats *hw_stats
2151                 = &dsaf_dev->hw_stats[node_num];
2152         bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver);
2153         int i;
2154         u32 reg_tmp;
2155
2156         hw_stats->pad_drop += dsaf_read_dev(dsaf_dev,
2157                 DSAF_INODE_PAD_DISCARD_NUM_0_REG + 0x80 * (u64)node_num);
2158         hw_stats->man_pkts += dsaf_read_dev(dsaf_dev,
2159                 DSAF_INODE_FINAL_IN_MAN_NUM_0_REG + 0x80 * (u64)node_num);
2160         hw_stats->rx_pkts += dsaf_read_dev(dsaf_dev,
2161                 DSAF_INODE_FINAL_IN_PKT_NUM_0_REG + 0x80 * (u64)node_num);
2162         hw_stats->rx_pkt_id += dsaf_read_dev(dsaf_dev,
2163                 DSAF_INODE_SBM_PID_NUM_0_REG + 0x80 * (u64)node_num);
2164
2165         reg_tmp = is_ver1 ? DSAF_INODE_FINAL_IN_PAUSE_NUM_0_REG :
2166                             DSAFV2_INODE_FINAL_IN_PAUSE_NUM_0_REG;
2167         hw_stats->rx_pause_frame +=
2168                 dsaf_read_dev(dsaf_dev, reg_tmp + 0x80 * (u64)node_num);
2169
2170         hw_stats->release_buf_num += dsaf_read_dev(dsaf_dev,
2171                 DSAF_INODE_SBM_RELS_NUM_0_REG + 0x80 * (u64)node_num);
2172         hw_stats->sbm_drop += dsaf_read_dev(dsaf_dev,
2173                 DSAF_INODE_SBM_DROP_NUM_0_REG + 0x80 * (u64)node_num);
2174         hw_stats->crc_false += dsaf_read_dev(dsaf_dev,
2175                 DSAF_INODE_CRC_FALSE_NUM_0_REG + 0x80 * (u64)node_num);
2176         hw_stats->bp_drop += dsaf_read_dev(dsaf_dev,
2177                 DSAF_INODE_BP_DISCARD_NUM_0_REG + 0x80 * (u64)node_num);
2178         hw_stats->rslt_drop += dsaf_read_dev(dsaf_dev,
2179                 DSAF_INODE_RSLT_DISCARD_NUM_0_REG + 0x80 * (u64)node_num);
2180         hw_stats->local_addr_false += dsaf_read_dev(dsaf_dev,
2181                 DSAF_INODE_LOCAL_ADDR_FALSE_NUM_0_REG + 0x80 * (u64)node_num);
2182
2183         hw_stats->vlan_drop += dsaf_read_dev(dsaf_dev,
2184                 DSAF_INODE_SW_VLAN_TAG_DISC_0_REG + 0x80 * (u64)node_num);
2185         hw_stats->stp_drop += dsaf_read_dev(dsaf_dev,
2186                 DSAF_INODE_IN_DATA_STP_DISC_0_REG + 0x80 * (u64)node_num);
2187
2188         /* pfc pause frame statistics stored in dsaf inode*/
2189         if ((node_num < DSAF_SERVICE_NW_NUM) && !is_ver1) {
2190                 for (i = 0; i < DSAF_PRIO_NR; i++) {
2191                         reg_tmp = hns_dsaf_get_inode_prio_reg(i);
2192                         hw_stats->rx_pfc[i] += dsaf_read_dev(dsaf_dev,
2193                                 reg_tmp + 0x4 * (u64)node_num);
2194                         hw_stats->tx_pfc[i] += dsaf_read_dev(dsaf_dev,
2195                                 DSAF_XOD_XGE_PFC_PRIO_CNT_BASE_REG +
2196                                 DSAF_XOD_XGE_PFC_PRIO_CNT_OFFSET * i +
2197                                 0xF0 * (u64)node_num);
2198                 }
2199         }
2200         hw_stats->tx_pkts += dsaf_read_dev(dsaf_dev,
2201                 DSAF_XOD_RCVPKT_CNT_0_REG + 0x90 * (u64)node_num);
2202 }
2203
2204 /**
2205  *hns_dsaf_get_regs - dump dsaf regs
2206  *@dsaf_dev: dsaf device
2207  *@data:data for value of regs
2208  */
2209 void hns_dsaf_get_regs(struct dsaf_device *ddev, u32 port, void *data)
2210 {
2211         u32 i = 0;
2212         u32 j;
2213         u32 *p = data;
2214         u32 reg_tmp;
2215         bool is_ver1 = AE_IS_VER1(ddev->dsaf_ver);
2216
2217         /* dsaf common registers */
2218         p[0] = dsaf_read_dev(ddev, DSAF_SRAM_INIT_OVER_0_REG);
2219         p[1] = dsaf_read_dev(ddev, DSAF_CFG_0_REG);
2220         p[2] = dsaf_read_dev(ddev, DSAF_ECC_ERR_INVERT_0_REG);
2221         p[3] = dsaf_read_dev(ddev, DSAF_ABNORMAL_TIMEOUT_0_REG);
2222         p[4] = dsaf_read_dev(ddev, DSAF_FSM_TIMEOUT_0_REG);
2223         p[5] = dsaf_read_dev(ddev, DSAF_DSA_REG_CNT_CLR_CE_REG);
2224         p[6] = dsaf_read_dev(ddev, DSAF_DSA_SBM_INF_FIFO_THRD_REG);
2225         p[7] = dsaf_read_dev(ddev, DSAF_DSA_SRAM_1BIT_ECC_SEL_REG);
2226         p[8] = dsaf_read_dev(ddev, DSAF_DSA_SRAM_1BIT_ECC_CNT_REG);
2227
2228         p[9] = dsaf_read_dev(ddev, DSAF_PFC_EN_0_REG + port * 4);
2229         p[10] = dsaf_read_dev(ddev, DSAF_PFC_UNIT_CNT_0_REG + port * 4);
2230         p[11] = dsaf_read_dev(ddev, DSAF_XGE_INT_MSK_0_REG + port * 4);
2231         p[12] = dsaf_read_dev(ddev, DSAF_XGE_INT_SRC_0_REG + port * 4);
2232         p[13] = dsaf_read_dev(ddev, DSAF_XGE_INT_STS_0_REG + port * 4);
2233         p[14] = dsaf_read_dev(ddev, DSAF_XGE_INT_MSK_0_REG + port * 4);
2234         p[15] = dsaf_read_dev(ddev, DSAF_PPE_INT_MSK_0_REG + port * 4);
2235         p[16] = dsaf_read_dev(ddev, DSAF_ROCEE_INT_MSK_0_REG + port * 4);
2236         p[17] = dsaf_read_dev(ddev, DSAF_XGE_INT_SRC_0_REG + port * 4);
2237         p[18] = dsaf_read_dev(ddev, DSAF_PPE_INT_SRC_0_REG + port * 4);
2238         p[19] =  dsaf_read_dev(ddev, DSAF_ROCEE_INT_SRC_0_REG + port * 4);
2239         p[20] = dsaf_read_dev(ddev, DSAF_XGE_INT_STS_0_REG + port * 4);
2240         p[21] = dsaf_read_dev(ddev, DSAF_PPE_INT_STS_0_REG + port * 4);
2241         p[22] = dsaf_read_dev(ddev, DSAF_ROCEE_INT_STS_0_REG + port * 4);
2242         p[23] = dsaf_read_dev(ddev, DSAF_PPE_QID_CFG_0_REG + port * 4);
2243
2244         for (i = 0; i < DSAF_SW_PORT_NUM; i++)
2245                 p[24 + i] = dsaf_read_dev(ddev,
2246                                 DSAF_SW_PORT_TYPE_0_REG + i * 4);
2247
2248         p[32] = dsaf_read_dev(ddev, DSAF_MIX_DEF_QID_0_REG + port * 4);
2249
2250         for (i = 0; i < DSAF_SW_PORT_NUM; i++)
2251                 p[33 + i] = dsaf_read_dev(ddev,
2252                                 DSAF_PORT_DEF_VLAN_0_REG + i * 4);
2253
2254         for (i = 0; i < DSAF_TOTAL_QUEUE_NUM; i++)
2255                 p[41 + i] = dsaf_read_dev(ddev,
2256                                 DSAF_VM_DEF_VLAN_0_REG + i * 4);
2257
2258         /* dsaf inode registers */
2259         p[170] = dsaf_read_dev(ddev, DSAF_INODE_CUT_THROUGH_CFG_0_REG);
2260
2261         p[171] = dsaf_read_dev(ddev,
2262                         DSAF_INODE_ECC_ERR_ADDR_0_REG + port * 0x80);
2263
2264         for (i = 0; i < DSAF_INODE_NUM / DSAF_COMM_CHN; i++) {
2265                 j = i * DSAF_COMM_CHN + port;
2266                 p[172 + i] = dsaf_read_dev(ddev,
2267                                 DSAF_INODE_IN_PORT_NUM_0_REG + j * 0x80);
2268                 p[175 + i] = dsaf_read_dev(ddev,
2269                                 DSAF_INODE_PRI_TC_CFG_0_REG + j * 0x80);
2270                 p[178 + i] = dsaf_read_dev(ddev,
2271                                 DSAF_INODE_BP_STATUS_0_REG + j * 0x80);
2272                 p[181 + i] = dsaf_read_dev(ddev,
2273                                 DSAF_INODE_PAD_DISCARD_NUM_0_REG + j * 0x80);
2274                 p[184 + i] = dsaf_read_dev(ddev,
2275                                 DSAF_INODE_FINAL_IN_MAN_NUM_0_REG + j * 0x80);
2276                 p[187 + i] = dsaf_read_dev(ddev,
2277                                 DSAF_INODE_FINAL_IN_PKT_NUM_0_REG + j * 0x80);
2278                 p[190 + i] = dsaf_read_dev(ddev,
2279                                 DSAF_INODE_SBM_PID_NUM_0_REG + j * 0x80);
2280                 reg_tmp = is_ver1 ? DSAF_INODE_FINAL_IN_PAUSE_NUM_0_REG :
2281                                     DSAFV2_INODE_FINAL_IN_PAUSE_NUM_0_REG;
2282                 p[193 + i] = dsaf_read_dev(ddev, reg_tmp + j * 0x80);
2283                 p[196 + i] = dsaf_read_dev(ddev,
2284                                 DSAF_INODE_SBM_RELS_NUM_0_REG + j * 0x80);
2285                 p[199 + i] = dsaf_read_dev(ddev,
2286                                 DSAF_INODE_SBM_DROP_NUM_0_REG + j * 0x80);
2287                 p[202 + i] = dsaf_read_dev(ddev,
2288                                 DSAF_INODE_CRC_FALSE_NUM_0_REG + j * 0x80);
2289                 p[205 + i] = dsaf_read_dev(ddev,
2290                                 DSAF_INODE_BP_DISCARD_NUM_0_REG + j * 0x80);
2291                 p[208 + i] = dsaf_read_dev(ddev,
2292                                 DSAF_INODE_RSLT_DISCARD_NUM_0_REG + j * 0x80);
2293                 p[211 + i] = dsaf_read_dev(ddev,
2294                         DSAF_INODE_LOCAL_ADDR_FALSE_NUM_0_REG + j * 0x80);
2295                 p[214 + i] = dsaf_read_dev(ddev,
2296                                 DSAF_INODE_VOQ_OVER_NUM_0_REG + j * 0x80);
2297                 p[217 + i] = dsaf_read_dev(ddev,
2298                                 DSAF_INODE_BD_SAVE_STATUS_0_REG + j * 4);
2299                 p[220 + i] = dsaf_read_dev(ddev,
2300                                 DSAF_INODE_BD_ORDER_STATUS_0_REG + j * 4);
2301                 p[223 + i] = dsaf_read_dev(ddev,
2302                                 DSAF_INODE_SW_VLAN_TAG_DISC_0_REG + j * 4);
2303                 p[224 + i] = dsaf_read_dev(ddev,
2304                                 DSAF_INODE_IN_DATA_STP_DISC_0_REG + j * 4);
2305         }
2306
2307         p[227] = dsaf_read_dev(ddev, DSAF_INODE_GE_FC_EN_0_REG + port * 4);
2308
2309         for (i = 0; i < DSAF_INODE_NUM / DSAF_COMM_CHN; i++) {
2310                 j = i * DSAF_COMM_CHN + port;
2311                 p[228 + i] = dsaf_read_dev(ddev,
2312                                 DSAF_INODE_VC0_IN_PKT_NUM_0_REG + j * 4);
2313         }
2314
2315         p[231] = dsaf_read_dev(ddev,
2316                 DSAF_INODE_VC1_IN_PKT_NUM_0_REG + port * 4);
2317
2318         /* dsaf inode registers */
2319         for (i = 0; i < HNS_DSAF_SBM_NUM(ddev) / DSAF_COMM_CHN; i++) {
2320                 j = i * DSAF_COMM_CHN + port;
2321                 p[232 + i] = dsaf_read_dev(ddev,
2322                                 DSAF_SBM_CFG_REG_0_REG + j * 0x80);
2323                 p[235 + i] = dsaf_read_dev(ddev,
2324                                 DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + j * 0x80);
2325                 p[238 + i] = dsaf_read_dev(ddev,
2326                                 DSAF_SBM_BP_CFG_1_REG_0_REG + j * 0x80);
2327                 p[241 + i] = dsaf_read_dev(ddev,
2328                                 DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + j * 0x80);
2329                 p[244 + i] = dsaf_read_dev(ddev,
2330                                 DSAF_SBM_FREE_CNT_0_0_REG + j * 0x80);
2331                 p[245 + i] = dsaf_read_dev(ddev,
2332                                 DSAF_SBM_FREE_CNT_1_0_REG + j * 0x80);
2333                 p[248 + i] = dsaf_read_dev(ddev,
2334                                 DSAF_SBM_BP_CNT_0_0_REG + j * 0x80);
2335                 p[251 + i] = dsaf_read_dev(ddev,
2336                                 DSAF_SBM_BP_CNT_1_0_REG + j * 0x80);
2337                 p[254 + i] = dsaf_read_dev(ddev,
2338                                 DSAF_SBM_BP_CNT_2_0_REG + j * 0x80);
2339                 p[257 + i] = dsaf_read_dev(ddev,
2340                                 DSAF_SBM_BP_CNT_3_0_REG + j * 0x80);
2341                 p[260 + i] = dsaf_read_dev(ddev,
2342                                 DSAF_SBM_INER_ST_0_REG + j * 0x80);
2343                 p[263 + i] = dsaf_read_dev(ddev,
2344                                 DSAF_SBM_MIB_REQ_FAILED_TC_0_REG + j * 0x80);
2345                 p[266 + i] = dsaf_read_dev(ddev,
2346                                 DSAF_SBM_LNK_INPORT_CNT_0_REG + j * 0x80);
2347                 p[269 + i] = dsaf_read_dev(ddev,
2348                                 DSAF_SBM_LNK_DROP_CNT_0_REG + j * 0x80);
2349                 p[272 + i] = dsaf_read_dev(ddev,
2350                                 DSAF_SBM_INF_OUTPORT_CNT_0_REG + j * 0x80);
2351                 p[275 + i] = dsaf_read_dev(ddev,
2352                                 DSAF_SBM_LNK_INPORT_TC0_CNT_0_REG + j * 0x80);
2353                 p[278 + i] = dsaf_read_dev(ddev,
2354                                 DSAF_SBM_LNK_INPORT_TC1_CNT_0_REG + j * 0x80);
2355                 p[281 + i] = dsaf_read_dev(ddev,
2356                                 DSAF_SBM_LNK_INPORT_TC2_CNT_0_REG + j * 0x80);
2357                 p[284 + i] = dsaf_read_dev(ddev,
2358                                 DSAF_SBM_LNK_INPORT_TC3_CNT_0_REG + j * 0x80);
2359                 p[287 + i] = dsaf_read_dev(ddev,
2360                                 DSAF_SBM_LNK_INPORT_TC4_CNT_0_REG + j * 0x80);
2361                 p[290 + i] = dsaf_read_dev(ddev,
2362                                 DSAF_SBM_LNK_INPORT_TC5_CNT_0_REG + j * 0x80);
2363                 p[293 + i] = dsaf_read_dev(ddev,
2364                                 DSAF_SBM_LNK_INPORT_TC6_CNT_0_REG + j * 0x80);
2365                 p[296 + i] = dsaf_read_dev(ddev,
2366                                 DSAF_SBM_LNK_INPORT_TC7_CNT_0_REG + j * 0x80);
2367                 p[299 + i] = dsaf_read_dev(ddev,
2368                                 DSAF_SBM_LNK_REQ_CNT_0_REG + j * 0x80);
2369                 p[302 + i] = dsaf_read_dev(ddev,
2370                                 DSAF_SBM_LNK_RELS_CNT_0_REG + j * 0x80);
2371                 p[305 + i] = dsaf_read_dev(ddev,
2372                                 DSAF_SBM_BP_CFG_3_REG_0_REG + j * 0x80);
2373                 p[308 + i] = dsaf_read_dev(ddev,
2374                                 DSAF_SBM_BP_CFG_4_REG_0_REG + j * 0x80);
2375         }
2376
2377         /* dsaf onode registers */
2378         for (i = 0; i < DSAF_XOD_NUM; i++) {
2379                 p[311 + i] = dsaf_read_dev(ddev,
2380                                 DSAF_XOD_ETS_TSA_TC0_TC3_CFG_0_REG + i * 0x90);
2381                 p[319 + i] = dsaf_read_dev(ddev,
2382                                 DSAF_XOD_ETS_TSA_TC4_TC7_CFG_0_REG + i * 0x90);
2383                 p[327 + i] = dsaf_read_dev(ddev,
2384                                 DSAF_XOD_ETS_BW_TC0_TC3_CFG_0_REG + i * 0x90);
2385                 p[335 + i] = dsaf_read_dev(ddev,
2386                                 DSAF_XOD_ETS_BW_TC4_TC7_CFG_0_REG + i * 0x90);
2387                 p[343 + i] = dsaf_read_dev(ddev,
2388                                 DSAF_XOD_ETS_BW_OFFSET_CFG_0_REG + i * 0x90);
2389                 p[351 + i] = dsaf_read_dev(ddev,
2390                                 DSAF_XOD_ETS_TOKEN_CFG_0_REG + i * 0x90);
2391         }
2392
2393         p[359] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_0_0_REG + port * 0x90);
2394         p[360] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_1_0_REG + port * 0x90);
2395         p[361] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_2_0_REG + port * 0x90);
2396
2397         for (i = 0; i < DSAF_XOD_BIG_NUM / DSAF_COMM_CHN; i++) {
2398                 j = i * DSAF_COMM_CHN + port;
2399                 p[362 + i] = dsaf_read_dev(ddev,
2400                                 DSAF_XOD_GNT_L_0_REG + j * 0x90);
2401                 p[365 + i] = dsaf_read_dev(ddev,
2402                                 DSAF_XOD_GNT_H_0_REG + j * 0x90);
2403                 p[368 + i] = dsaf_read_dev(ddev,
2404                                 DSAF_XOD_CONNECT_STATE_0_REG + j * 0x90);
2405                 p[371 + i] = dsaf_read_dev(ddev,
2406                                 DSAF_XOD_RCVPKT_CNT_0_REG + j * 0x90);
2407                 p[374 + i] = dsaf_read_dev(ddev,
2408                                 DSAF_XOD_RCVTC0_CNT_0_REG + j * 0x90);
2409                 p[377 + i] = dsaf_read_dev(ddev,
2410                                 DSAF_XOD_RCVTC1_CNT_0_REG + j * 0x90);
2411                 p[380 + i] = dsaf_read_dev(ddev,
2412                                 DSAF_XOD_RCVTC2_CNT_0_REG + j * 0x90);
2413                 p[383 + i] = dsaf_read_dev(ddev,
2414                                 DSAF_XOD_RCVTC3_CNT_0_REG + j * 0x90);
2415                 p[386 + i] = dsaf_read_dev(ddev,
2416                                 DSAF_XOD_RCVVC0_CNT_0_REG + j * 0x90);
2417                 p[389 + i] = dsaf_read_dev(ddev,
2418                                 DSAF_XOD_RCVVC1_CNT_0_REG + j * 0x90);
2419         }
2420
2421         p[392] = dsaf_read_dev(ddev,
2422                 DSAF_XOD_XGE_RCVIN0_CNT_0_REG + port * 0x90);
2423         p[393] = dsaf_read_dev(ddev,
2424                 DSAF_XOD_XGE_RCVIN1_CNT_0_REG + port * 0x90);
2425         p[394] = dsaf_read_dev(ddev,
2426                 DSAF_XOD_XGE_RCVIN2_CNT_0_REG + port * 0x90);
2427         p[395] = dsaf_read_dev(ddev,
2428                 DSAF_XOD_XGE_RCVIN3_CNT_0_REG + port * 0x90);
2429         p[396] = dsaf_read_dev(ddev,
2430                 DSAF_XOD_XGE_RCVIN4_CNT_0_REG + port * 0x90);
2431         p[397] = dsaf_read_dev(ddev,
2432                 DSAF_XOD_XGE_RCVIN5_CNT_0_REG + port * 0x90);
2433         p[398] = dsaf_read_dev(ddev,
2434                 DSAF_XOD_XGE_RCVIN6_CNT_0_REG + port * 0x90);
2435         p[399] = dsaf_read_dev(ddev,
2436                 DSAF_XOD_XGE_RCVIN7_CNT_0_REG + port * 0x90);
2437         p[400] = dsaf_read_dev(ddev,
2438                 DSAF_XOD_PPE_RCVIN0_CNT_0_REG + port * 0x90);
2439         p[401] = dsaf_read_dev(ddev,
2440                 DSAF_XOD_PPE_RCVIN1_CNT_0_REG + port * 0x90);
2441         p[402] = dsaf_read_dev(ddev,
2442                 DSAF_XOD_ROCEE_RCVIN0_CNT_0_REG + port * 0x90);
2443         p[403] = dsaf_read_dev(ddev,
2444                 DSAF_XOD_ROCEE_RCVIN1_CNT_0_REG + port * 0x90);
2445         p[404] = dsaf_read_dev(ddev,
2446                 DSAF_XOD_FIFO_STATUS_0_REG + port * 0x90);
2447
2448         /* dsaf voq registers */
2449         for (i = 0; i < DSAF_VOQ_NUM / DSAF_COMM_CHN; i++) {
2450                 j = (i * DSAF_COMM_CHN + port) * 0x90;
2451                 p[405 + i] = dsaf_read_dev(ddev,
2452                         DSAF_VOQ_ECC_INVERT_EN_0_REG + j);
2453                 p[408 + i] = dsaf_read_dev(ddev,
2454                         DSAF_VOQ_SRAM_PKT_NUM_0_REG + j);
2455                 p[411 + i] = dsaf_read_dev(ddev, DSAF_VOQ_IN_PKT_NUM_0_REG + j);
2456                 p[414 + i] = dsaf_read_dev(ddev,
2457                         DSAF_VOQ_OUT_PKT_NUM_0_REG + j);
2458                 p[417 + i] = dsaf_read_dev(ddev,
2459                         DSAF_VOQ_ECC_ERR_ADDR_0_REG + j);
2460                 p[420 + i] = dsaf_read_dev(ddev, DSAF_VOQ_BP_STATUS_0_REG + j);
2461                 p[423 + i] = dsaf_read_dev(ddev, DSAF_VOQ_SPUP_IDLE_0_REG + j);
2462                 p[426 + i] = dsaf_read_dev(ddev,
2463                         DSAF_VOQ_XGE_XOD_REQ_0_0_REG + j);
2464                 p[429 + i] = dsaf_read_dev(ddev,
2465                         DSAF_VOQ_XGE_XOD_REQ_1_0_REG + j);
2466                 p[432 + i] = dsaf_read_dev(ddev,
2467                         DSAF_VOQ_PPE_XOD_REQ_0_REG + j);
2468                 p[435 + i] = dsaf_read_dev(ddev,
2469                         DSAF_VOQ_ROCEE_XOD_REQ_0_REG + j);
2470                 p[438 + i] = dsaf_read_dev(ddev,
2471                         DSAF_VOQ_BP_ALL_THRD_0_REG + j);
2472         }
2473
2474         /* dsaf tbl registers */
2475         p[441] = dsaf_read_dev(ddev, DSAF_TBL_CTRL_0_REG);
2476         p[442] = dsaf_read_dev(ddev, DSAF_TBL_INT_MSK_0_REG);
2477         p[443] = dsaf_read_dev(ddev, DSAF_TBL_INT_SRC_0_REG);
2478         p[444] = dsaf_read_dev(ddev, DSAF_TBL_INT_STS_0_REG);
2479         p[445] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_ADDR_0_REG);
2480         p[446] = dsaf_read_dev(ddev, DSAF_TBL_LINE_ADDR_0_REG);
2481         p[447] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_HIGH_0_REG);
2482         p[448] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_LOW_0_REG);
2483         p[449] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG);
2484         p[450] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG);
2485         p[451] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG);
2486         p[452] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG);
2487         p[453] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG);
2488         p[454] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_UCAST_CFG_0_REG);
2489         p[455] = dsaf_read_dev(ddev, DSAF_TBL_LIN_CFG_0_REG);
2490         p[456] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RDATA_HIGH_0_REG);
2491         p[457] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RDATA_LOW_0_REG);
2492         p[458] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA4_0_REG);
2493         p[459] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA3_0_REG);
2494         p[460] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA2_0_REG);
2495         p[461] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA1_0_REG);
2496         p[462] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA0_0_REG);
2497         p[463] = dsaf_read_dev(ddev, DSAF_TBL_LIN_RDATA_0_REG);
2498
2499         for (i = 0; i < DSAF_SW_PORT_NUM; i++) {
2500                 j = i * 0x8;
2501                 p[464 + 2 * i] = dsaf_read_dev(ddev,
2502                         DSAF_TBL_DA0_MIS_INFO1_0_REG + j);
2503                 p[465 + 2 * i] = dsaf_read_dev(ddev,
2504                         DSAF_TBL_DA0_MIS_INFO0_0_REG + j);
2505         }
2506
2507         p[480] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO2_0_REG);
2508         p[481] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO1_0_REG);
2509         p[482] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO0_0_REG);
2510         p[483] = dsaf_read_dev(ddev, DSAF_TBL_PUL_0_REG);
2511         p[484] = dsaf_read_dev(ddev, DSAF_TBL_OLD_RSLT_0_REG);
2512         p[485] = dsaf_read_dev(ddev, DSAF_TBL_OLD_SCAN_VAL_0_REG);
2513         p[486] = dsaf_read_dev(ddev, DSAF_TBL_DFX_CTRL_0_REG);
2514         p[487] = dsaf_read_dev(ddev, DSAF_TBL_DFX_STAT_0_REG);
2515         p[488] = dsaf_read_dev(ddev, DSAF_TBL_DFX_STAT_2_0_REG);
2516         p[489] = dsaf_read_dev(ddev, DSAF_TBL_LKUP_NUM_I_0_REG);
2517         p[490] = dsaf_read_dev(ddev, DSAF_TBL_LKUP_NUM_O_0_REG);
2518         p[491] = dsaf_read_dev(ddev, DSAF_TBL_UCAST_BCAST_MIS_INFO_0_0_REG);
2519
2520         /* dsaf other registers */
2521         p[492] = dsaf_read_dev(ddev, DSAF_INODE_FIFO_WL_0_REG + port * 0x4);
2522         p[493] = dsaf_read_dev(ddev, DSAF_ONODE_FIFO_WL_0_REG + port * 0x4);
2523         p[494] = dsaf_read_dev(ddev, DSAF_XGE_GE_WORK_MODE_0_REG + port * 0x4);
2524         p[495] = dsaf_read_dev(ddev,
2525                 DSAF_XGE_APP_RX_LINK_UP_0_REG + port * 0x4);
2526         p[496] = dsaf_read_dev(ddev, DSAF_NETPORT_CTRL_SIG_0_REG + port * 0x4);
2527         p[497] = dsaf_read_dev(ddev, DSAF_XGE_CTRL_SIG_CFG_0_REG + port * 0x4);
2528
2529         if (!is_ver1)
2530                 p[498] = dsaf_read_dev(ddev, DSAF_PAUSE_CFG_REG + port * 0x4);
2531
2532         /* mark end of dsaf regs */
2533         for (i = 499; i < 504; i++)
2534                 p[i] = 0xdddddddd;
2535 }
2536
2537 static char *hns_dsaf_get_node_stats_strings(char *data, int node,
2538                                              struct dsaf_device *dsaf_dev)
2539 {
2540         char *buff = data;
2541         int i;
2542         bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver);
2543
2544         snprintf(buff, ETH_GSTRING_LEN, "innod%d_pad_drop_pkts", node);
2545         buff += ETH_GSTRING_LEN;
2546         snprintf(buff, ETH_GSTRING_LEN, "innod%d_manage_pkts", node);
2547         buff += ETH_GSTRING_LEN;
2548         snprintf(buff, ETH_GSTRING_LEN, "innod%d_rx_pkts", node);
2549         buff += ETH_GSTRING_LEN;
2550         snprintf(buff, ETH_GSTRING_LEN, "innod%d_rx_pkt_id", node);
2551         buff += ETH_GSTRING_LEN;
2552         snprintf(buff, ETH_GSTRING_LEN, "innod%d_rx_pause_frame", node);
2553         buff += ETH_GSTRING_LEN;
2554         snprintf(buff, ETH_GSTRING_LEN, "innod%d_release_buf_num", node);
2555         buff += ETH_GSTRING_LEN;
2556         snprintf(buff, ETH_GSTRING_LEN, "innod%d_sbm_drop_pkts", node);
2557         buff += ETH_GSTRING_LEN;
2558         snprintf(buff, ETH_GSTRING_LEN, "innod%d_crc_false_pkts", node);
2559         buff += ETH_GSTRING_LEN;
2560         snprintf(buff, ETH_GSTRING_LEN, "innod%d_bp_drop_pkts", node);
2561         buff += ETH_GSTRING_LEN;
2562         snprintf(buff, ETH_GSTRING_LEN, "innod%d_lookup_rslt_drop_pkts", node);
2563         buff += ETH_GSTRING_LEN;
2564         snprintf(buff, ETH_GSTRING_LEN, "innod%d_local_rslt_fail_pkts", node);
2565         buff += ETH_GSTRING_LEN;
2566         snprintf(buff, ETH_GSTRING_LEN, "innod%d_vlan_drop_pkts", node);
2567         buff += ETH_GSTRING_LEN;
2568         snprintf(buff, ETH_GSTRING_LEN, "innod%d_stp_drop_pkts", node);
2569         buff += ETH_GSTRING_LEN;
2570         if (node < DSAF_SERVICE_NW_NUM && !is_ver1) {
2571                 for (i = 0; i < DSAF_PRIO_NR; i++) {
2572                         snprintf(buff + 0 * ETH_GSTRING_LEN * DSAF_PRIO_NR,
2573                                  ETH_GSTRING_LEN, "inod%d_pfc_prio%d_pkts",
2574                                  node, i);
2575                         snprintf(buff + 1 * ETH_GSTRING_LEN * DSAF_PRIO_NR,
2576                                  ETH_GSTRING_LEN, "onod%d_pfc_prio%d_pkts",
2577                                  node, i);
2578                         buff += ETH_GSTRING_LEN;
2579                 }
2580                 buff += 1 * DSAF_PRIO_NR * ETH_GSTRING_LEN;
2581         }
2582         snprintf(buff, ETH_GSTRING_LEN, "onnod%d_tx_pkts", node);
2583         buff += ETH_GSTRING_LEN;
2584
2585         return buff;
2586 }
2587
2588 static u64 *hns_dsaf_get_node_stats(struct dsaf_device *ddev, u64 *data,
2589                                     int node_num)
2590 {
2591         u64 *p = data;
2592         int i;
2593         struct dsaf_hw_stats *hw_stats = &ddev->hw_stats[node_num];
2594         bool is_ver1 = AE_IS_VER1(ddev->dsaf_ver);
2595
2596         p[0] = hw_stats->pad_drop;
2597         p[1] = hw_stats->man_pkts;
2598         p[2] = hw_stats->rx_pkts;
2599         p[3] = hw_stats->rx_pkt_id;
2600         p[4] = hw_stats->rx_pause_frame;
2601         p[5] = hw_stats->release_buf_num;
2602         p[6] = hw_stats->sbm_drop;
2603         p[7] = hw_stats->crc_false;
2604         p[8] = hw_stats->bp_drop;
2605         p[9] = hw_stats->rslt_drop;
2606         p[10] = hw_stats->local_addr_false;
2607         p[11] = hw_stats->vlan_drop;
2608         p[12] = hw_stats->stp_drop;
2609         if (node_num < DSAF_SERVICE_NW_NUM && !is_ver1) {
2610                 for (i = 0; i < DSAF_PRIO_NR; i++) {
2611                         p[13 + i + 0 * DSAF_PRIO_NR] = hw_stats->rx_pfc[i];
2612                         p[13 + i + 1 * DSAF_PRIO_NR] = hw_stats->tx_pfc[i];
2613                 }
2614                 p[29] = hw_stats->tx_pkts;
2615                 return &p[30];
2616         }
2617
2618         p[13] = hw_stats->tx_pkts;
2619         return &p[14];
2620 }
2621
2622 /**
2623  *hns_dsaf_get_stats - get dsaf statistic
2624  *@ddev: dsaf device
2625  *@data:statistic value
2626  *@port: port num
2627  */
2628 void hns_dsaf_get_stats(struct dsaf_device *ddev, u64 *data, int port)
2629 {
2630         u64 *p = data;
2631         int node_num = port;
2632
2633         /* for ge/xge node info */
2634         p = hns_dsaf_get_node_stats(ddev, p, node_num);
2635
2636         /* for ppe node info */
2637         node_num = port + DSAF_PPE_INODE_BASE;
2638         (void)hns_dsaf_get_node_stats(ddev, p, node_num);
2639 }
2640
2641 /**
2642  *hns_dsaf_get_sset_count - get dsaf string set count
2643  *@stringset: type of values in data
2644  *return dsaf string name count
2645  */
2646 int hns_dsaf_get_sset_count(struct dsaf_device *dsaf_dev, int stringset)
2647 {
2648         bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver);
2649
2650         if (stringset == ETH_SS_STATS) {
2651                 if (is_ver1)
2652                         return DSAF_STATIC_NUM;
2653                 else
2654                         return DSAF_V2_STATIC_NUM;
2655         }
2656         return 0;
2657 }
2658
2659 /**
2660  *hns_dsaf_get_strings - get dsaf string set
2661  *@stringset:srting set index
2662  *@data:strings name value
2663  *@port:port index
2664  */
2665 void hns_dsaf_get_strings(int stringset, u8 *data, int port,
2666                           struct dsaf_device *dsaf_dev)
2667 {
2668         char *buff = (char *)data;
2669         int node = port;
2670
2671         if (stringset != ETH_SS_STATS)
2672                 return;
2673
2674         /* for ge/xge node info */
2675         buff = hns_dsaf_get_node_stats_strings(buff, node, dsaf_dev);
2676
2677         /* for ppe node info */
2678         node = port + DSAF_PPE_INODE_BASE;
2679         (void)hns_dsaf_get_node_stats_strings(buff, node, dsaf_dev);
2680 }
2681
2682 /**
2683  *hns_dsaf_get_sset_count - get dsaf regs count
2684  *return dsaf regs count
2685  */
2686 int hns_dsaf_get_regs_count(void)
2687 {
2688         return DSAF_DUMP_REGS_NUM;
2689 }
2690
2691 /**
2692  * dsaf_probe - probo dsaf dev
2693  * @pdev: dasf platform device
2694  * retuen 0 - success , negative --fail
2695  */
2696 static int hns_dsaf_probe(struct platform_device *pdev)
2697 {
2698         struct dsaf_device *dsaf_dev;
2699         int ret;
2700
2701         dsaf_dev = hns_dsaf_alloc_dev(&pdev->dev, sizeof(struct dsaf_drv_priv));
2702         if (IS_ERR(dsaf_dev)) {
2703                 ret = PTR_ERR(dsaf_dev);
2704                 dev_err(&pdev->dev,
2705                         "dsaf_probe dsaf_alloc_dev failed, ret = %#x!\n", ret);
2706                 return ret;
2707         }
2708
2709         ret = hns_dsaf_get_cfg(dsaf_dev);
2710         if (ret)
2711                 goto free_dev;
2712
2713         ret = hns_dsaf_init(dsaf_dev);
2714         if (ret)
2715                 goto free_dev;
2716
2717         ret = hns_mac_init(dsaf_dev);
2718         if (ret)
2719                 goto uninit_dsaf;
2720
2721         ret = hns_ppe_init(dsaf_dev);
2722         if (ret)
2723                 goto uninit_mac;
2724
2725         ret = hns_dsaf_ae_init(dsaf_dev);
2726         if (ret)
2727                 goto uninit_ppe;
2728
2729         return 0;
2730
2731 uninit_ppe:
2732         hns_ppe_uninit(dsaf_dev);
2733
2734 uninit_mac:
2735         hns_mac_uninit(dsaf_dev);
2736
2737 uninit_dsaf:
2738         hns_dsaf_free(dsaf_dev);
2739
2740 free_dev:
2741         hns_dsaf_free_dev(dsaf_dev);
2742
2743         return ret;
2744 }
2745
2746 /**
2747  * dsaf_remove - remove dsaf dev
2748  * @pdev: dasf platform device
2749  */
2750 static int hns_dsaf_remove(struct platform_device *pdev)
2751 {
2752         struct dsaf_device *dsaf_dev = dev_get_drvdata(&pdev->dev);
2753
2754         hns_dsaf_ae_uninit(dsaf_dev);
2755
2756         hns_ppe_uninit(dsaf_dev);
2757
2758         hns_mac_uninit(dsaf_dev);
2759
2760         hns_dsaf_free(dsaf_dev);
2761
2762         hns_dsaf_free_dev(dsaf_dev);
2763
2764         return 0;
2765 }
2766
2767 static const struct of_device_id g_dsaf_match[] = {
2768         {.compatible = "hisilicon,hns-dsaf-v1"},
2769         {.compatible = "hisilicon,hns-dsaf-v2"},
2770         {}
2771 };
2772
2773 static struct platform_driver g_dsaf_driver = {
2774         .probe = hns_dsaf_probe,
2775         .remove = hns_dsaf_remove,
2776         .driver = {
2777                 .name = DSAF_DRV_NAME,
2778                 .of_match_table = g_dsaf_match,
2779                 .acpi_match_table = hns_dsaf_acpi_match,
2780         },
2781 };
2782
2783 module_platform_driver(g_dsaf_driver);
2784
2785 /**
2786  * hns_dsaf_roce_reset - reset dsaf and roce
2787  * @dsaf_fwnode: Pointer to framework node for the dasf
2788  * @enable: false - request reset , true - drop reset
2789  * retuen 0 - success , negative -fail
2790  */
2791 int hns_dsaf_roce_reset(struct fwnode_handle *dsaf_fwnode, bool dereset)
2792 {
2793         struct dsaf_device *dsaf_dev;
2794         struct platform_device *pdev;
2795         u32 mp;
2796         u32 sl;
2797         u32 credit;
2798         int i;
2799         const u32 port_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE_NUM] = {
2800                 {DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0},
2801                 {DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0},
2802                 {DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0},
2803                 {DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0},
2804                 {DSAF_ROCE_PORT_4, DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1},
2805                 {DSAF_ROCE_PORT_4, DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1},
2806                 {DSAF_ROCE_PORT_5, DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1},
2807                 {DSAF_ROCE_PORT_5, DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1},
2808         };
2809         const u32 sl_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE_NUM] = {
2810                 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_0},
2811                 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_1, DSAF_ROCE_SL_1},
2812                 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_2},
2813                 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_1, DSAF_ROCE_SL_3},
2814                 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_0},
2815                 {DSAF_ROCE_SL_1, DSAF_ROCE_SL_1, DSAF_ROCE_SL_1},
2816                 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_2},
2817                 {DSAF_ROCE_SL_1, DSAF_ROCE_SL_1, DSAF_ROCE_SL_3},
2818         };
2819
2820         /* find the platform device corresponding to fwnode */
2821         if (is_of_node(dsaf_fwnode)) {
2822                 pdev = of_find_device_by_node(to_of_node(dsaf_fwnode));
2823         } else if (is_acpi_device_node(dsaf_fwnode)) {
2824                 pdev = hns_dsaf_find_platform_device(dsaf_fwnode);
2825         } else {
2826                 pr_err("fwnode is neither OF or ACPI type\n");
2827                 return -EINVAL;
2828         }
2829
2830         /* check if we were a success in fetching pdev */
2831         if (!pdev) {
2832                 pr_err("couldn't find platform device for node\n");
2833                 return -ENODEV;
2834         }
2835
2836         /* retrieve the dsaf_device from the driver data */
2837         dsaf_dev = dev_get_drvdata(&pdev->dev);
2838         if (!dsaf_dev) {
2839                 dev_err(&pdev->dev, "dsaf_dev is NULL\n");
2840                 return -ENODEV;
2841         }
2842
2843         /* now, make sure we are running on compatible SoC */
2844         if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
2845                 dev_err(dsaf_dev->dev, "%s v1 chip doesn't support RoCE!\n",
2846                         dsaf_dev->ae_dev.name);
2847                 return -ENODEV;
2848         }
2849
2850         /* do reset or de-reset according to the flag */
2851         if (!dereset) {
2852                 /* reset rocee-channels in dsaf and rocee */
2853                 dsaf_dev->misc_op->hns_dsaf_srst_chns(dsaf_dev, DSAF_CHNS_MASK,
2854                                                       false);
2855                 dsaf_dev->misc_op->hns_dsaf_roce_srst(dsaf_dev, false);
2856         } else {
2857                 /* configure dsaf tx roce correspond to port map and sl map */
2858                 mp = dsaf_read_dev(dsaf_dev, DSAF_ROCE_PORT_MAP_REG);
2859                 for (i = 0; i < DSAF_ROCE_CREDIT_CHN; i++)
2860                         dsaf_set_field(mp, 7 << i * 3, i * 3,
2861                                        port_map[i][DSAF_ROCE_6PORT_MODE]);
2862                 dsaf_set_field(mp, 3 << i * 3, i * 3, 0);
2863                 dsaf_write_dev(dsaf_dev, DSAF_ROCE_PORT_MAP_REG, mp);
2864
2865                 sl = dsaf_read_dev(dsaf_dev, DSAF_ROCE_SL_MAP_REG);
2866                 for (i = 0; i < DSAF_ROCE_CREDIT_CHN; i++)
2867                         dsaf_set_field(sl, 3 << i * 2, i * 2,
2868                                        sl_map[i][DSAF_ROCE_6PORT_MODE]);
2869                 dsaf_write_dev(dsaf_dev, DSAF_ROCE_SL_MAP_REG, sl);
2870
2871                 /* de-reset rocee-channels in dsaf and rocee */
2872                 dsaf_dev->misc_op->hns_dsaf_srst_chns(dsaf_dev, DSAF_CHNS_MASK,
2873                                                       true);
2874                 msleep(SRST_TIME_INTERVAL);
2875                 dsaf_dev->misc_op->hns_dsaf_roce_srst(dsaf_dev, true);
2876
2877                 /* enable dsaf channel rocee credit */
2878                 credit = dsaf_read_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG);
2879                 dsaf_set_bit(credit, DSAF_SBM_ROCEE_CFG_CRD_EN_B, 0);
2880                 dsaf_write_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG, credit);
2881
2882                 dsaf_set_bit(credit, DSAF_SBM_ROCEE_CFG_CRD_EN_B, 1);
2883                 dsaf_write_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG, credit);
2884         }
2885         return 0;
2886 }
2887 EXPORT_SYMBOL(hns_dsaf_roce_reset);
2888
2889 MODULE_LICENSE("GPL");
2890 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
2891 MODULE_DESCRIPTION("HNS DSAF driver");
2892 MODULE_VERSION(DSAF_MOD_VERSION);