drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.h

   1 /*
   2  * Copyright (c) 2014-2015 Hisilicon Limited.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9
  10 #ifndef __HNS_DSAF_MAIN_H
  11 #define __HNS_DSAF_MAIN_H
  12 #include "hnae.h"
  13
  14 #include "hns_dsaf_reg.h"
  15 #include "hns_dsaf_mac.h"
  16
  17 struct hns_mac_cb;
  18
  19 #define DSAF_DRV_NAME "hns_dsaf"
  20 #define DSAF_MOD_VERSION "v1.0"
  21
  22 #define HNS_DSAF_DEBUG_NW_REG_OFFSET 0x100000
  23
  24 #define DSAF_BASE_INNER_PORT_NUM 127/* mac tbl qid*/
  25
  26 #define DSAF_MAX_CHIP_NUM 2  /*max 2 chips */
  27
  28 #define DSAF_DEFAUTL_QUEUE_NUM_PER_PPE 22
  29
  30 #define HNS_DSAF_MAX_DESC_CNT 1024
  31 #define HNS_DSAF_MIN_DESC_CNT 16
  32
  33 #define DSAF_INVALID_ENTRY_IDX 0xffff
  34
  35 #define DSAF_CFG_READ_CNT   30
  36
  37 #define MAC_NUM_OCTETS_PER_ADDR 6
  38
  39 #define DSAF_DUMP_REGS_NUM 504
  40 #define DSAF_STATIC_NUM 28
  41
  42 #define DSAF_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
  43
  44 enum hal_dsaf_mode {
  45         HRD_DSAF_NO_DSAF_MODE   = 0x0,
  46         HRD_DSAF_MODE           = 0x1,
  47 };
  48
  49 enum hal_dsaf_tc_mode {
  50         HRD_DSAF_4TC_MODE               = 0X0,
  51         HRD_DSAF_8TC_MODE               = 0X1,
  52 };
  53
  54 struct dsaf_vm_def_vlan {
  55         u32 vm_def_vlan_id;
  56         u32 vm_def_vlan_cfi;
  57         u32 vm_def_vlan_pri;
  58 };
  59
  60 struct dsaf_tbl_tcam_data {
  61         u32 tbl_tcam_data_high;
  62         u32 tbl_tcam_data_low;
  63 };
  64
  65 #define DSAF_PORT_MSK_NUM \
  66         ((DSAF_TOTAL_QUEUE_NUM + DSAF_SERVICE_NW_NUM - 1) / 32 + 1)
  67 struct dsaf_tbl_tcam_mcast_cfg {
  68         u8 tbl_mcast_old_en;
  69         u8 tbl_mcast_item_vld;
  70         u32 tbl_mcast_port_msk[DSAF_PORT_MSK_NUM];
  71 };
  72
  73 struct dsaf_tbl_tcam_ucast_cfg {
  74         u32 tbl_ucast_old_en;
  75         u32 tbl_ucast_item_vld;
  76         u32 tbl_ucast_mac_discard;
  77         u32 tbl_ucast_dvc;
  78         u32 tbl_ucast_out_port;
  79 };
  80
  81 struct dsaf_tbl_line_cfg {
  82         u32 tbl_line_mac_discard;
  83         u32 tbl_line_dvc;
  84         u32 tbl_line_out_port;
  85 };
  86
  87 enum dsaf_port_rate_mode {
  88         DSAF_PORT_RATE_1000 = 0,
  89         DSAF_PORT_RATE_2500,
  90         DSAF_PORT_RATE_10000
  91 };
  92
  93 enum dsaf_stp_port_type {
  94         DSAF_STP_PORT_TYPE_DISCARD = 0,
  95         DSAF_STP_PORT_TYPE_BLOCK = 1,
  96         DSAF_STP_PORT_TYPE_LISTEN = 2,
  97         DSAF_STP_PORT_TYPE_LEARN = 3,
  98         DSAF_STP_PORT_TYPE_FORWARD = 4
  99 };
 100
 101 enum dsaf_sw_port_type {
 102         DSAF_SW_PORT_TYPE_NON_VLAN = 0,
 103         DSAF_SW_PORT_TYPE_ACCESS = 1,
 104         DSAF_SW_PORT_TYPE_TRUNK = 2,
 105 };
 106
 107 #define DSAF_SUB_BASE_SIZE                        (0x10000)
 108
 109 /* dsaf mode define */
 110 enum dsaf_mode {
 111         DSAF_MODE_INVALID = 0,  /**< Invalid dsaf mode */
 112         DSAF_MODE_ENABLE_FIX,   /**< en DSAF-mode, fixed to queue*/
 113         DSAF_MODE_ENABLE_0VM,   /**< en DSAF-mode, support 0 VM */
 114         DSAF_MODE_ENABLE_8VM,   /**< en DSAF-mode, support 8 VM */
 115         DSAF_MODE_ENABLE_16VM,  /**< en DSAF-mode, support 16 VM */
 116         DSAF_MODE_ENABLE_32VM,  /**< en DSAF-mode, support 32 VM */
 117         DSAF_MODE_ENABLE_128VM, /**< en DSAF-mode, support 128 VM */
 118         DSAF_MODE_ENABLE,               /**< before is enable DSAF mode*/
 119         DSAF_MODE_DISABLE_FIX,  /**< non-dasf, fixed to queue*/
 120         DSAF_MODE_DISABLE_2PORT_8VM,    /**< non-dasf, 2port 8VM */
 121         DSAF_MODE_DISABLE_2PORT_16VM,   /**< non-dasf, 2port 16VM */
 122         DSAF_MODE_DISABLE_2PORT_64VM,   /**< non-dasf, 2port 64VM */
 123         DSAF_MODE_DISABLE_6PORT_0VM,    /**< non-dasf, 6port 0VM */
 124         DSAF_MODE_DISABLE_6PORT_2VM,    /**< non-dasf, 6port 2VM */
 125         DSAF_MODE_DISABLE_6PORT_4VM,    /**< non-dasf, 6port 4VM */
 126         DSAF_MODE_DISABLE_6PORT_16VM,   /**< non-dasf, 6port 16VM */
 127         DSAF_MODE_MAX           /**< the last one, use as the num */
 128 };
 129
 130 #define DSAF_DEST_PORT_NUM 256  /* DSAF max port num */
 131 #define DSAF_WORD_BIT_CNT 32  /* the num bit of word */
 132
 133 /*mac entry, mc or uc entry*/
 134 struct dsaf_drv_mac_single_dest_entry {
 135         /* mac addr, match the entry*/
 136         u8 addr[MAC_NUM_OCTETS_PER_ADDR];
 137         u16 in_vlan_id; /* value of VlanId */
 138
 139         /* the vld input port num, dsaf-mode fix 0, */
 140         /*      non-dasf is the entry whitch port vld*/
 141         u8 in_port_num;
 142
 143         u8 port_num; /*output port num*/
 144         u8 rsv[6];
 145 };
 146
 147 /*only mc entry*/
 148 struct dsaf_drv_mac_multi_dest_entry {
 149         /* mac addr, match the entry*/
 150         u8 addr[MAC_NUM_OCTETS_PER_ADDR];
 151         u16 in_vlan_id;
 152         /* this mac addr output port,*/
 153         /*      bit0-bit5 means Port0-Port5(1bit is vld)**/
 154         u32 port_mask[DSAF_DEST_PORT_NUM / DSAF_WORD_BIT_CNT];
 155
 156         /* the vld input port num, dsaf-mode fix 0,*/
 157         /*      non-dasf is the entry whitch port vld*/
 158         u8 in_port_num;
 159         u8 rsv[7];
 160 };
 161
 162 struct dsaf_hw_stats {
 163         u64 pad_drop;
 164         u64 man_pkts;
 165         u64 rx_pkts;
 166         u64 rx_pkt_id;
 167         u64 rx_pause_frame;
 168         u64 release_buf_num;
 169         u64 sbm_drop;
 170         u64 crc_false;
 171         u64 bp_drop;
 172         u64 rslt_drop;
 173         u64 local_addr_false;
 174         u64 vlan_drop;
 175         u64 stp_drop;
 176         u64 tx_pkts;
 177 };
 178
 179 struct hnae_vf_cb {
 180         u8 port_index;
 181         struct hns_mac_cb *mac_cb;
 182         struct dsaf_device *dsaf_dev;
 183         struct hnae_handle  ae_handle; /* must be the last number */
 184 };
 185
 186 struct dsaf_int_xge_src {
 187         u32    xid_xge_ecc_err_int_src;
 188         u32    xid_xge_fsm_timout_int_src;
 189         u32    sbm_xge_lnk_fsm_timout_int_src;
 190         u32    sbm_xge_lnk_ecc_2bit_int_src;
 191         u32    sbm_xge_mib_req_failed_int_src;
 192         u32    sbm_xge_mib_req_fsm_timout_int_src;
 193         u32    sbm_xge_mib_rels_fsm_timout_int_src;
 194         u32    sbm_xge_sram_ecc_2bit_int_src;
 195         u32    sbm_xge_mib_buf_sum_err_int_src;
 196         u32    sbm_xge_mib_req_extra_int_src;
 197         u32    sbm_xge_mib_rels_extra_int_src;
 198         u32    voq_xge_start_to_over_0_int_src;
 199         u32    voq_xge_start_to_over_1_int_src;
 200         u32    voq_xge_ecc_err_int_src;
 201 };
 202
 203 struct dsaf_int_ppe_src {
 204         u32    xid_ppe_fsm_timout_int_src;
 205         u32    sbm_ppe_lnk_fsm_timout_int_src;
 206         u32    sbm_ppe_lnk_ecc_2bit_int_src;
 207         u32    sbm_ppe_mib_req_failed_int_src;
 208         u32    sbm_ppe_mib_req_fsm_timout_int_src;
 209         u32    sbm_ppe_mib_rels_fsm_timout_int_src;
 210         u32    sbm_ppe_sram_ecc_2bit_int_src;
 211         u32    sbm_ppe_mib_buf_sum_err_int_src;
 212         u32    sbm_ppe_mib_req_extra_int_src;
 213         u32    sbm_ppe_mib_rels_extra_int_src;
 214         u32    voq_ppe_start_to_over_0_int_src;
 215         u32    voq_ppe_ecc_err_int_src;
 216         u32    xod_ppe_fifo_rd_empty_int_src;
 217         u32    xod_ppe_fifo_wr_full_int_src;
 218 };
 219
 220 struct dsaf_int_rocee_src {
 221         u32    xid_rocee_fsm_timout_int_src;
 222         u32    sbm_rocee_lnk_fsm_timout_int_src;
 223         u32    sbm_rocee_lnk_ecc_2bit_int_src;
 224         u32    sbm_rocee_mib_req_failed_int_src;
 225         u32    sbm_rocee_mib_req_fsm_timout_int_src;
 226         u32    sbm_rocee_mib_rels_fsm_timout_int_src;
 227         u32    sbm_rocee_sram_ecc_2bit_int_src;
 228         u32    sbm_rocee_mib_buf_sum_err_int_src;
 229         u32    sbm_rocee_mib_req_extra_int_src;
 230         u32    sbm_rocee_mib_rels_extra_int_src;
 231         u32    voq_rocee_start_to_over_0_int_src;
 232         u32    voq_rocee_ecc_err_int_src;
 233 };
 234
 235 struct dsaf_int_tbl_src {
 236         u32    tbl_da0_mis_src;
 237         u32    tbl_da1_mis_src;
 238         u32    tbl_da2_mis_src;
 239         u32    tbl_da3_mis_src;
 240         u32    tbl_da4_mis_src;
 241         u32    tbl_da5_mis_src;
 242         u32    tbl_da6_mis_src;
 243         u32    tbl_da7_mis_src;
 244         u32    tbl_sa_mis_src;
 245         u32    tbl_old_sech_end_src;
 246         u32    lram_ecc_err1_src;
 247         u32    lram_ecc_err2_src;
 248         u32    tram_ecc_err1_src;
 249         u32    tram_ecc_err2_src;
 250         u32    tbl_ucast_bcast_xge0_src;
 251         u32    tbl_ucast_bcast_xge1_src;
 252         u32    tbl_ucast_bcast_xge2_src;
 253         u32    tbl_ucast_bcast_xge3_src;
 254         u32    tbl_ucast_bcast_xge4_src;
 255         u32    tbl_ucast_bcast_xge5_src;
 256         u32    tbl_ucast_bcast_ppe_src;
 257         u32    tbl_ucast_bcast_rocee_src;
 258 };
 259
 260 struct dsaf_int_stat {
 261         struct dsaf_int_xge_src dsaf_int_xge_stat[DSAF_COMM_CHN];
 262         struct dsaf_int_ppe_src dsaf_int_ppe_stat[DSAF_COMM_CHN];
 263         struct dsaf_int_rocee_src dsaf_int_rocee_stat[DSAF_COMM_CHN];
 264         struct dsaf_int_tbl_src dsaf_int_tbl_stat[1];
 265
 266 };
 267
 268 /* Dsaf device struct define ,and mac ->  dsaf */
 269 struct dsaf_device {
 270         struct device *dev;
 271         struct hnae_ae_dev ae_dev;
 272
 273         u8 __iomem *sc_base;
 274         u8 __iomem *sds_base;
 275         u8 __iomem *ppe_base;
 276         u8 __iomem *io_base;
 277         u8 __iomem *cpld_base;
 278
 279         u32 desc_num; /*  desc num per queue*/
 280         u32 buf_size; /*  ring buffer size */
 281         int buf_size_type; /* ring buffer size-type */
 282         enum dsaf_mode dsaf_mode;        /* dsaf mode  */
 283         enum hal_dsaf_mode dsaf_en;
 284         enum hal_dsaf_tc_mode dsaf_tc_mode;
 285         u32 dsaf_ver;
 286
 287         struct ppe_common_cb *ppe_common[DSAF_COMM_DEV_NUM];
 288         struct rcb_common_cb *rcb_common[DSAF_COMM_DEV_NUM];
 289         struct hns_mac_cb *mac_cb;
 290
 291         struct dsaf_hw_stats hw_stats[DSAF_NODE_NUM];
 292         struct dsaf_int_stat int_stat;
 293 };
 294
 295 static inline void *hns_dsaf_dev_priv(const struct dsaf_device *dsaf_dev)
 296 {
 297         return (void *)((u8 *)dsaf_dev + sizeof(*dsaf_dev));
 298 }
 299
 300 struct dsaf_drv_tbl_tcam_key {
 301         union {
 302                 struct {
 303                         u8 mac_3;
 304                         u8 mac_2;
 305                         u8 mac_1;
 306                         u8 mac_0;
 307                 } bits;
 308
 309                 u32 val;
 310         } high;
 311         union {
 312                 struct {
 313                         u32 port:4; /* port id, */
 314                         /* dsaf-mode fixed 0, non-dsaf-mode port id*/
 315                         u32 vlan:12; /* vlan id */
 316                         u32 mac_5:8;
 317                         u32 mac_4:8;
 318                 } bits;
 319
 320                 u32 val;
 321         } low;
 322 };
 323
 324 struct dsaf_drv_soft_mac_tbl {
 325         struct dsaf_drv_tbl_tcam_key tcam_key;
 326         u16 index; /*the entry's index in tcam tab*/
 327 };
 328
 329 struct dsaf_drv_priv {
 330         /* soft tab Mac key, for hardware tab*/
 331         struct dsaf_drv_soft_mac_tbl *soft_mac_tbl;
 332 };
 333
 334 static inline void hns_dsaf_tbl_tcam_addr_cfg(struct dsaf_device *dsaf_dev,
 335                                               u32 tab_tcam_addr)
 336 {
 337         dsaf_set_dev_field(dsaf_dev, DSAF_TBL_TCAM_ADDR_0_REG,
 338                            DSAF_TBL_TCAM_ADDR_M, DSAF_TBL_TCAM_ADDR_S,
 339                            tab_tcam_addr);
 340 }
 341
 342 static inline void hns_dsaf_tbl_tcam_load_pul(struct dsaf_device *dsaf_dev)
 343 {
 344         u32 o_tbl_pul;
 345
 346         o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG);
 347         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_LOAD_S, 1);
 348         dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
 349         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_LOAD_S, 0);
 350         dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
 351 }
 352
 353 static inline void hns_dsaf_tbl_line_addr_cfg(struct dsaf_device *dsaf_dev,
 354                                               u32 tab_line_addr)
 355 {
 356         dsaf_set_dev_field(dsaf_dev, DSAF_TBL_LINE_ADDR_0_REG,
 357                            DSAF_TBL_LINE_ADDR_M, DSAF_TBL_LINE_ADDR_S,
 358                            tab_line_addr);
 359 }
 360
 361 static inline int hns_dsaf_get_comm_idx_by_port(int port)
 362 {
 363         if ((port < DSAF_COMM_CHN) || (port == DSAF_MAX_PORT_NUM_PER_CHIP))
 364                 return 0;
 365         else
 366                 return (port - DSAF_COMM_CHN + 1);
 367 }
 368
 369 static inline struct hnae_vf_cb *hns_ae_get_vf_cb(
 370         struct hnae_handle *handle)
 371 {
 372         return container_of(handle, struct hnae_vf_cb, ae_handle);
 373 }
 374
 375 int hns_dsaf_set_mac_uc_entry(struct dsaf_device *dsaf_dev,
 376                               struct dsaf_drv_mac_single_dest_entry *mac_entry);
 377 int hns_dsaf_set_mac_mc_entry(struct dsaf_device *dsaf_dev,
 378                               struct dsaf_drv_mac_multi_dest_entry *mac_entry);
 379 int hns_dsaf_add_mac_mc_port(struct dsaf_device *dsaf_dev,
 380                              struct dsaf_drv_mac_single_dest_entry *mac_entry);
 381 int hns_dsaf_del_mac_entry(struct dsaf_device *dsaf_dev, u16 vlan_id,
 382                            u8 in_port_num, u8 *addr);
 383 int hns_dsaf_del_mac_mc_port(struct dsaf_device *dsaf_dev,
 384                              struct dsaf_drv_mac_single_dest_entry *mac_entry);
 385 int hns_dsaf_get_mac_uc_entry(struct dsaf_device *dsaf_dev,
 386                               struct dsaf_drv_mac_single_dest_entry *mac_entry);
 387 int hns_dsaf_get_mac_mc_entry(struct dsaf_device *dsaf_dev,
 388                               struct dsaf_drv_mac_multi_dest_entry *mac_entry);
 389 int hns_dsaf_get_mac_entry_by_index(
 390         struct dsaf_device *dsaf_dev,
 391         u16 entry_index,
 392         struct dsaf_drv_mac_multi_dest_entry *mac_entry);
 393
 394 void hns_dsaf_rst(struct dsaf_device *dsaf_dev, u32 val);
 395
 396 void hns_ppe_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val);
 397
 398 void hns_ppe_com_srst(struct ppe_common_cb *ppe_common, u32 val);
 399
 400 void hns_dsaf_fix_mac_mode(struct hns_mac_cb *mac_cb);
 401
 402 int hns_dsaf_ae_init(struct dsaf_device *dsaf_dev);
 403 void hns_dsaf_ae_uninit(struct dsaf_device *dsaf_dev);
 404
 405 void hns_dsaf_xge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val);
 406 void hns_dsaf_ge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val);
 407 void hns_dsaf_xge_core_srst_by_port(struct dsaf_device *dsaf_dev,
 408                                     u32 port, u32 val);
 409
 410 void hns_dsaf_update_stats(struct dsaf_device *dsaf_dev, u32 inode_num);
 411
 412 int hns_dsaf_get_sset_count(int stringset);
 413 void hns_dsaf_get_stats(struct dsaf_device *ddev, u64 *data, int port);
 414 void hns_dsaf_get_strings(int stringset, u8 *data, int port);
 415
 416 void hns_dsaf_get_regs(struct dsaf_device *ddev, u32 port, void *data);
 417 int hns_dsaf_get_regs_count(void);
 418 void hns_dsaf_set_promisc_mode(struct dsaf_device *dsaf_dev, u32 en);
 419
 420 #endif /* __HNS_DSAF_MAIN_H__ */