2 * Copyright (c) 2014-2015 Hisilicon Limited.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #include "hns_dsaf_mac.h"
11 #include "hns_dsaf_misc.h"
12 #include "hns_dsaf_ppe.h"
13 #include "hns_dsaf_reg.h"
16 HNS_OP_RESET_FUNC = 0x1,
17 HNS_OP_SERDES_LP_FUNC = 0x2,
18 HNS_OP_LED_SET_FUNC = 0x3,
19 HNS_OP_GET_PORT_TYPE_FUNC = 0x4,
20 HNS_OP_GET_SFP_STAT_FUNC = 0x5,
24 HNS_DSAF_RESET_FUNC = 0x1,
25 HNS_PPE_RESET_FUNC = 0x2,
26 HNS_XGE_CORE_RESET_FUNC = 0x3,
27 HNS_XGE_RESET_FUNC = 0x4,
28 HNS_GE_RESET_FUNC = 0x5,
31 const u8 hns_dsaf_acpi_dsm_uuid[] = {
32 0x1A, 0xAA, 0x85, 0x1A, 0x93, 0xE2, 0x5E, 0x41,
33 0x8E, 0x28, 0x8D, 0x69, 0x0A, 0x0F, 0x82, 0x0A
36 static void dsaf_write_sub(struct dsaf_device *dsaf_dev, u32 reg, u32 val)
38 if (dsaf_dev->sub_ctrl)
39 dsaf_write_syscon(dsaf_dev->sub_ctrl, reg, val);
41 dsaf_write_reg(dsaf_dev->sc_base, reg, val);
44 static u32 dsaf_read_sub(struct dsaf_device *dsaf_dev, u32 reg)
48 if (dsaf_dev->sub_ctrl)
49 ret = dsaf_read_syscon(dsaf_dev->sub_ctrl, reg);
51 ret = dsaf_read_reg(dsaf_dev->sc_base, reg);
56 static void hns_cpld_set_led(struct hns_mac_cb *mac_cb, int link_status,
63 pr_err("sfp_led_opt mac_dev is null!\n");
66 if (!mac_cb->cpld_ctrl) {
67 dev_err(mac_cb->dev, "mac_id=%d, cpld syscon is null !\n",
72 if (speed == MAC_SPEED_10000)
75 value = mac_cb->cpld_led_value;
78 dsaf_set_bit(value, DSAF_LED_LINK_B, link_status);
79 dsaf_set_field(value, DSAF_LED_SPEED_M,
80 DSAF_LED_SPEED_S, speed_reg);
81 dsaf_set_bit(value, DSAF_LED_DATA_B, data);
83 if (value != mac_cb->cpld_led_value) {
84 dsaf_write_syscon(mac_cb->cpld_ctrl,
85 mac_cb->cpld_ctrl_reg, value);
86 mac_cb->cpld_led_value = value;
89 value = (mac_cb->cpld_led_value) & (0x1 << DSAF_LED_ANCHOR_B);
90 dsaf_write_syscon(mac_cb->cpld_ctrl,
91 mac_cb->cpld_ctrl_reg, value);
92 mac_cb->cpld_led_value = value;
96 static void cpld_led_reset(struct hns_mac_cb *mac_cb)
98 if (!mac_cb || !mac_cb->cpld_ctrl)
101 dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
102 CPLD_LED_DEFAULT_VALUE);
103 mac_cb->cpld_led_value = CPLD_LED_DEFAULT_VALUE;
106 static int cpld_set_led_id(struct hns_mac_cb *mac_cb,
107 enum hnae_led_state status)
110 case HNAE_LED_ACTIVE:
111 mac_cb->cpld_led_value =
112 dsaf_read_syscon(mac_cb->cpld_ctrl,
113 mac_cb->cpld_ctrl_reg);
114 dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
116 dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
117 mac_cb->cpld_led_value);
119 case HNAE_LED_INACTIVE:
120 dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
121 CPLD_LED_DEFAULT_VALUE);
122 dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
123 mac_cb->cpld_led_value);
126 dev_err(mac_cb->dev, "invalid led state: %d!", status);
133 #define RESET_REQ_OR_DREQ 1
135 static void hns_dsaf_acpi_srst_by_port(struct dsaf_device *dsaf_dev, u8 op_type,
136 u32 port_type, u32 port, u32 val)
138 union acpi_object *obj;
139 union acpi_object obj_args[3], argv4;
141 obj_args[0].integer.type = ACPI_TYPE_INTEGER;
142 obj_args[0].integer.value = port_type;
143 obj_args[1].integer.type = ACPI_TYPE_INTEGER;
144 obj_args[1].integer.value = port;
145 obj_args[2].integer.type = ACPI_TYPE_INTEGER;
146 obj_args[2].integer.value = val;
148 argv4.type = ACPI_TYPE_PACKAGE;
149 argv4.package.count = 3;
150 argv4.package.elements = obj_args;
152 obj = acpi_evaluate_dsm(ACPI_HANDLE(dsaf_dev->dev),
153 hns_dsaf_acpi_dsm_uuid, 0, op_type, &argv4);
155 dev_warn(dsaf_dev->dev, "reset port_type%d port%d fail!",
163 static void hns_dsaf_rst(struct dsaf_device *dsaf_dev, bool dereset)
169 xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_REQ_REG;
170 nt_reg_addr = DSAF_SUB_SC_NT_RESET_REQ_REG;
172 xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_DREQ_REG;
173 nt_reg_addr = DSAF_SUB_SC_NT_RESET_DREQ_REG;
176 dsaf_write_sub(dsaf_dev, xbar_reg_addr, RESET_REQ_OR_DREQ);
177 dsaf_write_sub(dsaf_dev, nt_reg_addr, RESET_REQ_OR_DREQ);
180 static void hns_dsaf_rst_acpi(struct dsaf_device *dsaf_dev, bool dereset)
182 hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
187 static void hns_dsaf_xge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port,
193 if (port >= DSAF_XGE_NUM)
196 reg_val |= RESET_REQ_OR_DREQ;
197 reg_val |= 0x2082082 << dsaf_dev->mac_cb[port]->port_rst_off;
200 reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
202 reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG;
204 dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
207 static void hns_dsaf_xge_srst_by_port_acpi(struct dsaf_device *dsaf_dev,
208 u32 port, bool dereset)
210 hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
211 HNS_XGE_RESET_FUNC, port, dereset);
214 static void hns_dsaf_xge_core_srst_by_port(struct dsaf_device *dsaf_dev,
215 u32 port, bool dereset)
220 if (port >= DSAF_XGE_NUM)
223 reg_val |= XGMAC_TRX_CORE_SRST_M
224 << dsaf_dev->mac_cb[port]->port_rst_off;
227 reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
229 reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG;
231 dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
235 * hns_dsaf_srst_chns - reset dsaf channels
236 * @dsaf_dev: dsaf device struct pointer
237 * @msk: xbar channels mask value:
240 * bit12-17 for roce0-5
241 * bit18-19 for com/dfx
242 * @enable: false - request reset , true - drop reset
244 void hns_dsaf_srst_chns(struct dsaf_device *dsaf_dev, u32 msk, bool enable)
249 reg_addr = DSAF_SUB_SC_DSAF_RESET_REQ_REG;
251 reg_addr = DSAF_SUB_SC_DSAF_RESET_DREQ_REG;
253 dsaf_write_sub(dsaf_dev, reg_addr, msk);
256 void hns_dsaf_roce_srst(struct dsaf_device *dsaf_dev, bool enable)
259 dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_ROCEE_RESET_REQ_REG, 1);
261 dsaf_write_sub(dsaf_dev,
262 DSAF_SUB_SC_ROCEE_CLK_DIS_REG, 1);
263 dsaf_write_sub(dsaf_dev,
264 DSAF_SUB_SC_ROCEE_RESET_DREQ_REG, 1);
266 dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_ROCEE_CLK_EN_REG, 1);
271 hns_dsaf_xge_core_srst_by_port_acpi(struct dsaf_device *dsaf_dev,
272 u32 port, bool dereset)
274 hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
275 HNS_XGE_CORE_RESET_FUNC, port, dereset);
278 static void hns_dsaf_ge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port,
285 if (port >= DSAF_GE_NUM)
288 if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
289 reg_val_1 = 0x1 << port;
290 port_rst_off = dsaf_dev->mac_cb[port]->port_rst_off;
291 /* there is difference between V1 and V2 in register.*/
292 reg_val_2 = AE_IS_VER1(dsaf_dev->dsaf_ver) ?
293 0x1041041 : 0x2082082;
294 reg_val_2 <<= port_rst_off;
297 dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ1_REG,
300 dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ0_REG,
303 dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ0_REG,
306 dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ1_REG,
311 reg_val_2 = AE_IS_VER1(dsaf_dev->dsaf_ver) ? 0x100 : 0x40;
313 reg_val_1 <<= dsaf_dev->reset_offset;
314 reg_val_2 <<= dsaf_dev->reset_offset;
317 dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ1_REG,
320 dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_PPE_RESET_REQ_REG,
323 dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ1_REG,
326 dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_PPE_RESET_DREQ_REG,
332 static void hns_dsaf_ge_srst_by_port_acpi(struct dsaf_device *dsaf_dev,
333 u32 port, bool dereset)
335 hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
336 HNS_GE_RESET_FUNC, port, dereset);
339 static void hns_ppe_srst_by_port(struct dsaf_device *dsaf_dev, u32 port,
345 reg_val |= RESET_REQ_OR_DREQ << dsaf_dev->mac_cb[port]->port_rst_off;
348 reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
350 reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG;
352 dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
356 hns_ppe_srst_by_port_acpi(struct dsaf_device *dsaf_dev, u32 port, bool dereset)
358 hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
359 HNS_PPE_RESET_FUNC, port, dereset);
362 static void hns_ppe_com_srst(struct dsaf_device *dsaf_dev, bool dereset)
367 if (!(dev_of_node(dsaf_dev->dev)))
370 if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
371 reg_val = RESET_REQ_OR_DREQ;
373 reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_REQ_REG;
375 reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_DREQ_REG;
378 reg_val = 0x100 << dsaf_dev->reset_offset;
381 reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
383 reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG;
386 dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
390 * hns_mac_get_sds_mode - get phy ifterface form serdes mode
391 * @mac_cb: mac control block
392 * retuen phy interface
394 static phy_interface_t hns_mac_get_phy_if(struct hns_mac_cb *mac_cb)
398 bool is_ver1 = AE_IS_VER1(mac_cb->dsaf_dev->dsaf_ver);
399 int mac_id = mac_cb->mac_id;
400 phy_interface_t phy_if;
403 if (HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev))
404 return PHY_INTERFACE_MODE_SGMII;
406 if (mac_id >= 0 && mac_id <= 3)
407 reg = HNS_MAC_HILINK4_REG;
409 reg = HNS_MAC_HILINK3_REG;
411 if (!HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev) && mac_id <= 3)
412 reg = HNS_MAC_HILINK4V2_REG;
414 reg = HNS_MAC_HILINK3V2_REG;
417 mode = dsaf_read_sub(mac_cb->dsaf_dev, reg);
418 if (dsaf_get_bit(mode, mac_cb->port_mode_off))
419 phy_if = PHY_INTERFACE_MODE_XGMII;
421 phy_if = PHY_INTERFACE_MODE_SGMII;
426 static phy_interface_t hns_mac_get_phy_if_acpi(struct hns_mac_cb *mac_cb)
428 phy_interface_t phy_if = PHY_INTERFACE_MODE_NA;
429 union acpi_object *obj;
430 union acpi_object obj_args, argv4;
432 obj_args.integer.type = ACPI_TYPE_INTEGER;
433 obj_args.integer.value = mac_cb->mac_id;
435 argv4.type = ACPI_TYPE_PACKAGE,
436 argv4.package.count = 1,
437 argv4.package.elements = &obj_args,
439 obj = acpi_evaluate_dsm(ACPI_HANDLE(mac_cb->dev),
440 hns_dsaf_acpi_dsm_uuid, 0,
441 HNS_OP_GET_PORT_TYPE_FUNC, &argv4);
443 if (!obj || obj->type != ACPI_TYPE_INTEGER)
446 phy_if = obj->integer.value ?
447 PHY_INTERFACE_MODE_XGMII : PHY_INTERFACE_MODE_SGMII;
449 dev_dbg(mac_cb->dev, "mac_id=%d, phy_if=%d\n", mac_cb->mac_id, phy_if);
456 int hns_mac_get_sfp_prsnt(struct hns_mac_cb *mac_cb, int *sfp_prsnt)
458 if (!mac_cb->cpld_ctrl)
461 *sfp_prsnt = !dsaf_read_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg
462 + MAC_SFP_PORT_OFFSET);
468 * hns_mac_config_sds_loopback - set loop back for serdes
469 * @mac_cb: mac control block
470 * retuen 0 == success
472 static int hns_mac_config_sds_loopback(struct hns_mac_cb *mac_cb, bool en)
474 const u8 lane_id[] = {
475 0, /* mac 0 -> lane 0 */
476 1, /* mac 1 -> lane 1 */
477 2, /* mac 2 -> lane 2 */
478 3, /* mac 3 -> lane 3 */
479 2, /* mac 4 -> lane 2 */
480 3, /* mac 5 -> lane 3 */
481 0, /* mac 6 -> lane 0 */
482 1 /* mac 7 -> lane 1 */
484 #define RX_CSR(lane, reg) ((0x4080 + (reg) * 0x0002 + (lane) * 0x0200) * 2)
485 u64 reg_offset = RX_CSR(lane_id[mac_cb->mac_id], 0);
488 int ret = hns_mac_get_sfp_prsnt(mac_cb, &sfp_prsnt);
490 if (!mac_cb->phy_dev) {
492 pr_info("please confirm sfp is present or not\n");
495 pr_info("no sfp in this eth\n");
498 if (mac_cb->serdes_ctrl) {
501 if (!AE_IS_VER1(mac_cb->dsaf_dev->dsaf_ver)) {
502 #define HILINK_ACCESS_SEL_CFG 0x40008
503 /* hilink4 & hilink3 use the same xge training and
504 * xge u adaptor. There is a hilink access sel cfg
505 * register to select which one to be configed
507 if ((!HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev)) &&
508 (mac_cb->mac_id <= 3))
509 dsaf_write_syscon(mac_cb->serdes_ctrl,
510 HILINK_ACCESS_SEL_CFG, 0);
512 dsaf_write_syscon(mac_cb->serdes_ctrl,
513 HILINK_ACCESS_SEL_CFG, 3);
516 origin = dsaf_read_syscon(mac_cb->serdes_ctrl, reg_offset);
518 dsaf_set_field(origin, 1ull << 10, 10, en);
519 dsaf_write_syscon(mac_cb->serdes_ctrl, reg_offset, origin);
521 u8 *base_addr = (u8 *)mac_cb->serdes_vaddr +
522 (mac_cb->mac_id <= 3 ? 0x00280000 : 0x00200000);
523 dsaf_set_reg_field(base_addr, reg_offset, 1ull << 10, 10, en);
530 hns_mac_config_sds_loopback_acpi(struct hns_mac_cb *mac_cb, bool en)
532 union acpi_object *obj;
533 union acpi_object obj_args[3], argv4;
535 obj_args[0].integer.type = ACPI_TYPE_INTEGER;
536 obj_args[0].integer.value = mac_cb->mac_id;
537 obj_args[1].integer.type = ACPI_TYPE_INTEGER;
538 obj_args[1].integer.value = !!en;
540 argv4.type = ACPI_TYPE_PACKAGE;
541 argv4.package.count = 2;
542 argv4.package.elements = obj_args;
544 obj = acpi_evaluate_dsm(ACPI_HANDLE(mac_cb->dsaf_dev->dev),
545 hns_dsaf_acpi_dsm_uuid, 0,
546 HNS_OP_SERDES_LP_FUNC, &argv4);
548 dev_warn(mac_cb->dsaf_dev->dev, "set port%d serdes lp fail!",
559 struct dsaf_misc_op *hns_misc_op_get(struct dsaf_device *dsaf_dev)
561 struct dsaf_misc_op *misc_op;
563 misc_op = devm_kzalloc(dsaf_dev->dev, sizeof(*misc_op), GFP_KERNEL);
567 if (dev_of_node(dsaf_dev->dev)) {
568 misc_op->cpld_set_led = hns_cpld_set_led;
569 misc_op->cpld_reset_led = cpld_led_reset;
570 misc_op->cpld_set_led_id = cpld_set_led_id;
572 misc_op->dsaf_reset = hns_dsaf_rst;
573 misc_op->xge_srst = hns_dsaf_xge_srst_by_port;
574 misc_op->xge_core_srst = hns_dsaf_xge_core_srst_by_port;
575 misc_op->ge_srst = hns_dsaf_ge_srst_by_port;
576 misc_op->ppe_srst = hns_ppe_srst_by_port;
577 misc_op->ppe_comm_srst = hns_ppe_com_srst;
579 misc_op->get_phy_if = hns_mac_get_phy_if;
580 misc_op->get_sfp_prsnt = hns_mac_get_sfp_prsnt;
582 misc_op->cfg_serdes_loopback = hns_mac_config_sds_loopback;
583 } else if (is_acpi_node(dsaf_dev->dev->fwnode)) {
584 misc_op->cpld_set_led = hns_cpld_set_led;
585 misc_op->cpld_reset_led = cpld_led_reset;
586 misc_op->cpld_set_led_id = cpld_set_led_id;
588 misc_op->dsaf_reset = hns_dsaf_rst_acpi;
589 misc_op->xge_srst = hns_dsaf_xge_srst_by_port_acpi;
590 misc_op->xge_core_srst = hns_dsaf_xge_core_srst_by_port_acpi;
591 misc_op->ge_srst = hns_dsaf_ge_srst_by_port_acpi;
592 misc_op->ppe_srst = hns_ppe_srst_by_port_acpi;
593 misc_op->ppe_comm_srst = hns_ppe_com_srst;
595 misc_op->get_phy_if = hns_mac_get_phy_if_acpi;
596 misc_op->get_sfp_prsnt = hns_mac_get_sfp_prsnt;
598 misc_op->cfg_serdes_loopback = hns_mac_config_sds_loopback_acpi;
600 devm_kfree(dsaf_dev->dev, (void *)misc_op);
604 return (void *)misc_op;