drivers/net/ethernet/ibm/emac/core.c

   1 /*
   2  * drivers/net/ethernet/ibm/emac/core.c
   3  *
   4  * Driver for PowerPC 4xx on-chip ethernet controller.
   5  *
   6  * Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
   7  *                <benh@kernel.crashing.org>
   8  *
   9  * Based on the arch/ppc version of the driver:
  10  *
  11  * Copyright (c) 2004, 2005 Zultys Technologies.
  12  * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
  13  *
  14  * Based on original work by
  15  *      Matt Porter <mporter@kernel.crashing.org>
  16  *      (c) 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
  17  *      Armin Kuster <akuster@mvista.com>
  18  *      Johnnie Peters <jpeters@mvista.com>
  19  *
  20  * This program is free software; you can redistribute  it and/or modify it
  21  * under  the terms of  the GNU General  Public License as published by the
  22  * Free Software Foundation;  either version 2 of the  License, or (at your
  23  * option) any later version.
  24  *
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/sched.h>
  29 #include <linux/string.h>
  30 #include <linux/errno.h>
  31 #include <linux/delay.h>
  32 #include <linux/types.h>
  33 #include <linux/pci.h>
  34 #include <linux/etherdevice.h>
  35 #include <linux/skbuff.h>
  36 #include <linux/crc32.h>
  37 #include <linux/ethtool.h>
  38 #include <linux/mii.h>
  39 #include <linux/bitops.h>
  40 #include <linux/workqueue.h>
  41 #include <linux/of.h>
  42 #include <linux/of_address.h>
  43 #include <linux/of_irq.h>
  44 #include <linux/of_net.h>
  45 #include <linux/slab.h>
  46
  47 #include <asm/processor.h>
  48 #include <asm/io.h>
  49 #include <asm/dma.h>
  50 #include <asm/uaccess.h>
  51 #include <asm/dcr.h>
  52 #include <asm/dcr-regs.h>
  53
  54 #include "core.h"
  55
  56 /*
  57  * Lack of dma_unmap_???? calls is intentional.
  58  *
  59  * API-correct usage requires additional support state information to be
  60  * maintained for every RX and TX buffer descriptor (BD). Unfortunately, due to
  61  * EMAC design (e.g. TX buffer passed from network stack can be split into
  62  * several BDs, dma_map_single/dma_map_page can be used to map particular BD),
  63  * maintaining such information will add additional overhead.
  64  * Current DMA API implementation for 4xx processors only ensures cache coherency
  65  * and dma_unmap_???? routines are empty and are likely to stay this way.
  66  * I decided to omit dma_unmap_??? calls because I don't want to add additional
  67  * complexity just for the sake of following some abstract API, when it doesn't
  68  * add any real benefit to the driver. I understand that this decision maybe
  69  * controversial, but I really tried to make code API-correct and efficient
  70  * at the same time and didn't come up with code I liked :(.                --ebs
  71  */
  72
  73 #define DRV_NAME        "emac"
  74 #define DRV_VERSION     "3.54"
  75 #define DRV_DESC        "PPC 4xx OCP EMAC driver"
  76
  77 MODULE_DESCRIPTION(DRV_DESC);
  78 MODULE_AUTHOR
  79     ("Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>");
  80 MODULE_LICENSE("GPL");
  81
  82 /* minimum number of free TX descriptors required to wake up TX process */
  83 #define EMAC_TX_WAKEUP_THRESH           (NUM_TX_BUFF / 4)
  84
  85 /* If packet size is less than this number, we allocate small skb and copy packet
  86  * contents into it instead of just sending original big skb up
  87  */
  88 #define EMAC_RX_COPY_THRESH             CONFIG_IBM_EMAC_RX_COPY_THRESHOLD
  89
  90 /* Since multiple EMACs share MDIO lines in various ways, we need
  91  * to avoid re-using the same PHY ID in cases where the arch didn't
  92  * setup precise phy_map entries
  93  *
  94  * XXX This is something that needs to be reworked as we can have multiple
  95  * EMAC "sets" (multiple ASICs containing several EMACs) though we can
  96  * probably require in that case to have explicit PHY IDs in the device-tree
  97  */
  98 static u32 busy_phy_map;
  99 static DEFINE_MUTEX(emac_phy_map_lock);
 100
 101 /* This is the wait queue used to wait on any event related to probe, that
 102  * is discovery of MALs, other EMACs, ZMII/RGMIIs, etc...
 103  */
 104 static DECLARE_WAIT_QUEUE_HEAD(emac_probe_wait);
 105
 106 /* Having stable interface names is a doomed idea. However, it would be nice
 107  * if we didn't have completely random interface names at boot too :-) It's
 108  * just a matter of making everybody's life easier. Since we are doing
 109  * threaded probing, it's a bit harder though. The base idea here is that
 110  * we make up a list of all emacs in the device-tree before we register the
 111  * driver. Every emac will then wait for the previous one in the list to
 112  * initialize before itself. We should also keep that list ordered by
 113  * cell_index.
 114  * That list is only 4 entries long, meaning that additional EMACs don't
 115  * get ordering guarantees unless EMAC_BOOT_LIST_SIZE is increased.
 116  */
 117
 118 #define EMAC_BOOT_LIST_SIZE     4
 119 static struct device_node *emac_boot_list[EMAC_BOOT_LIST_SIZE];
 120
 121 /* How long should I wait for dependent devices ? */
 122 #define EMAC_PROBE_DEP_TIMEOUT  (HZ * 5)
 123
 124 /* I don't want to litter system log with timeout errors
 125  * when we have brain-damaged PHY.
 126  */
 127 static inline void emac_report_timeout_error(struct emac_instance *dev,
 128                                              const char *error)
 129 {
 130         if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX |
 131                                   EMAC_FTR_460EX_PHY_CLK_FIX |
 132                                   EMAC_FTR_440EP_PHY_CLK_FIX))
 133                 DBG(dev, "%s" NL, error);
 134         else if (net_ratelimit())
 135                 printk(KERN_ERR "%s: %s\n", dev->ofdev->dev.of_node->full_name,
 136                         error);
 137 }
 138
 139 /* EMAC PHY clock workaround:
 140  * 440EP/440GR has more sane SDR0_MFR register implementation than 440GX,
 141  * which allows controlling each EMAC clock
 142  */
 143 static inline void emac_rx_clk_tx(struct emac_instance *dev)
 144 {
 145 #ifdef CONFIG_PPC_DCR_NATIVE
 146         if (emac_has_feature(dev, EMAC_FTR_440EP_PHY_CLK_FIX))
 147                 dcri_clrset(SDR0, SDR0_MFR,
 148                             0, SDR0_MFR_ECS >> dev->cell_index);
 149 #endif
 150 }
 151
 152 static inline void emac_rx_clk_default(struct emac_instance *dev)
 153 {
 154 #ifdef CONFIG_PPC_DCR_NATIVE
 155         if (emac_has_feature(dev, EMAC_FTR_440EP_PHY_CLK_FIX))
 156                 dcri_clrset(SDR0, SDR0_MFR,
 157                             SDR0_MFR_ECS >> dev->cell_index, 0);
 158 #endif
 159 }
 160
 161 /* PHY polling intervals */
 162 #define PHY_POLL_LINK_ON        HZ
 163 #define PHY_POLL_LINK_OFF       (HZ / 5)
 164
 165 /* Graceful stop timeouts in us.
 166  * We should allow up to 1 frame time (full-duplex, ignoring collisions)
 167  */
 168 #define STOP_TIMEOUT_10         1230
 169 #define STOP_TIMEOUT_100        124
 170 #define STOP_TIMEOUT_1000       13
 171 #define STOP_TIMEOUT_1000_JUMBO 73
 172
 173 static unsigned char default_mcast_addr[] = {
 174         0x01, 0x80, 0xC2, 0x00, 0x00, 0x01
 175 };
 176
 177 /* Please, keep in sync with struct ibm_emac_stats/ibm_emac_error_stats */
 178 static const char emac_stats_keys[EMAC_ETHTOOL_STATS_COUNT][ETH_GSTRING_LEN] = {
 179         "rx_packets", "rx_bytes", "tx_packets", "tx_bytes", "rx_packets_csum",
 180         "tx_packets_csum", "tx_undo", "rx_dropped_stack", "rx_dropped_oom",
 181         "rx_dropped_error", "rx_dropped_resize", "rx_dropped_mtu",
 182         "rx_stopped", "rx_bd_errors", "rx_bd_overrun", "rx_bd_bad_packet",
 183         "rx_bd_runt_packet", "rx_bd_short_event", "rx_bd_alignment_error",
 184         "rx_bd_bad_fcs", "rx_bd_packet_too_long", "rx_bd_out_of_range",
 185         "rx_bd_in_range", "rx_parity", "rx_fifo_overrun", "rx_overrun",
 186         "rx_bad_packet", "rx_runt_packet", "rx_short_event",
 187         "rx_alignment_error", "rx_bad_fcs", "rx_packet_too_long",
 188         "rx_out_of_range", "rx_in_range", "tx_dropped", "tx_bd_errors",
 189         "tx_bd_bad_fcs", "tx_bd_carrier_loss", "tx_bd_excessive_deferral",
 190         "tx_bd_excessive_collisions", "tx_bd_late_collision",
 191         "tx_bd_multple_collisions", "tx_bd_single_collision",
 192         "tx_bd_underrun", "tx_bd_sqe", "tx_parity", "tx_underrun", "tx_sqe",
 193         "tx_errors"
 194 };
 195
 196 static irqreturn_t emac_irq(int irq, void *dev_instance);
 197 static void emac_clean_tx_ring(struct emac_instance *dev);
 198 static void __emac_set_multicast_list(struct emac_instance *dev);
 199
 200 static inline int emac_phy_supports_gige(int phy_mode)
 201 {
 202         return  phy_mode == PHY_MODE_GMII ||
 203                 phy_mode == PHY_MODE_RGMII ||
 204                 phy_mode == PHY_MODE_SGMII ||
 205                 phy_mode == PHY_MODE_TBI ||
 206                 phy_mode == PHY_MODE_RTBI;
 207 }
 208
 209 static inline int emac_phy_gpcs(int phy_mode)
 210 {
 211         return  phy_mode == PHY_MODE_SGMII ||
 212                 phy_mode == PHY_MODE_TBI ||
 213                 phy_mode == PHY_MODE_RTBI;
 214 }
 215
 216 static inline void emac_tx_enable(struct emac_instance *dev)
 217 {
 218         struct emac_regs __iomem *p = dev->emacp;
 219         u32 r;
 220
 221         DBG(dev, "tx_enable" NL);
 222
 223         r = in_be32(&p->mr0);
 224         if (!(r & EMAC_MR0_TXE))
 225                 out_be32(&p->mr0, r | EMAC_MR0_TXE);
 226 }
 227
 228 static void emac_tx_disable(struct emac_instance *dev)
 229 {
 230         struct emac_regs __iomem *p = dev->emacp;
 231         u32 r;
 232
 233         DBG(dev, "tx_disable" NL);
 234
 235         r = in_be32(&p->mr0);
 236         if (r & EMAC_MR0_TXE) {
 237                 int n = dev->stop_timeout;
 238                 out_be32(&p->mr0, r & ~EMAC_MR0_TXE);
 239                 while (!(in_be32(&p->mr0) & EMAC_MR0_TXI) && n) {
 240                         udelay(1);
 241                         --n;
 242                 }
 243                 if (unlikely(!n))
 244                         emac_report_timeout_error(dev, "TX disable timeout");
 245         }
 246 }
 247
 248 static void emac_rx_enable(struct emac_instance *dev)
 249 {
 250         struct emac_regs __iomem *p = dev->emacp;
 251         u32 r;
 252
 253         if (unlikely(test_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags)))
 254                 goto out;
 255
 256         DBG(dev, "rx_enable" NL);
 257
 258         r = in_be32(&p->mr0);
 259         if (!(r & EMAC_MR0_RXE)) {
 260                 if (unlikely(!(r & EMAC_MR0_RXI))) {
 261                         /* Wait if previous async disable is still in progress */
 262                         int n = dev->stop_timeout;
 263                         while (!(r = in_be32(&p->mr0) & EMAC_MR0_RXI) && n) {
 264                                 udelay(1);
 265                                 --n;
 266                         }
 267                         if (unlikely(!n))
 268                                 emac_report_timeout_error(dev,
 269                                                           "RX disable timeout");
 270                 }
 271                 out_be32(&p->mr0, r | EMAC_MR0_RXE);
 272         }
 273  out:
 274         ;
 275 }
 276
 277 static void emac_rx_disable(struct emac_instance *dev)
 278 {
 279         struct emac_regs __iomem *p = dev->emacp;
 280         u32 r;
 281
 282         DBG(dev, "rx_disable" NL);
 283
 284         r = in_be32(&p->mr0);
 285         if (r & EMAC_MR0_RXE) {
 286                 int n = dev->stop_timeout;
 287                 out_be32(&p->mr0, r & ~EMAC_MR0_RXE);
 288                 while (!(in_be32(&p->mr0) & EMAC_MR0_RXI) && n) {
 289                         udelay(1);
 290                         --n;
 291                 }
 292                 if (unlikely(!n))
 293                         emac_report_timeout_error(dev, "RX disable timeout");
 294         }
 295 }
 296
 297 static inline void emac_netif_stop(struct emac_instance *dev)
 298 {
 299         netif_tx_lock_bh(dev->ndev);
 300         netif_addr_lock(dev->ndev);
 301         dev->no_mcast = 1;
 302         netif_addr_unlock(dev->ndev);
 303         netif_tx_unlock_bh(dev->ndev);
 304         netif_trans_update(dev->ndev);  /* prevent tx timeout */
 305         mal_poll_disable(dev->mal, &dev->commac);
 306         netif_tx_disable(dev->ndev);
 307 }
 308
 309 static inline void emac_netif_start(struct emac_instance *dev)
 310 {
 311         netif_tx_lock_bh(dev->ndev);
 312         netif_addr_lock(dev->ndev);
 313         dev->no_mcast = 0;
 314         if (dev->mcast_pending && netif_running(dev->ndev))
 315                 __emac_set_multicast_list(dev);
 316         netif_addr_unlock(dev->ndev);
 317         netif_tx_unlock_bh(dev->ndev);
 318
 319         netif_wake_queue(dev->ndev);
 320
 321         /* NOTE: unconditional netif_wake_queue is only appropriate
 322          * so long as all callers are assured to have free tx slots
 323          * (taken from tg3... though the case where that is wrong is
 324          *  not terribly harmful)
 325          */
 326         mal_poll_enable(dev->mal, &dev->commac);
 327 }
 328
 329 static inline void emac_rx_disable_async(struct emac_instance *dev)
 330 {
 331         struct emac_regs __iomem *p = dev->emacp;
 332         u32 r;
 333
 334         DBG(dev, "rx_disable_async" NL);
 335
 336         r = in_be32(&p->mr0);
 337         if (r & EMAC_MR0_RXE)
 338                 out_be32(&p->mr0, r & ~EMAC_MR0_RXE);
 339 }
 340
 341 static int emac_reset(struct emac_instance *dev)
 342 {
 343         struct emac_regs __iomem *p = dev->emacp;
 344         int n = 20;
 345
 346         DBG(dev, "reset" NL);
 347
 348         if (!dev->reset_failed) {
 349                 /* 40x erratum suggests stopping RX channel before reset,
 350                  * we stop TX as well
 351                  */
 352                 emac_rx_disable(dev);
 353                 emac_tx_disable(dev);
 354         }
 355
 356 #ifdef CONFIG_PPC_DCR_NATIVE
 357         /*
 358          * PPC460EX/GT Embedded Processor Advanced User's Manual
 359          * section 28.10.1 Mode Register 0 (EMACx_MR0) states:
 360          * Note: The PHY must provide a TX Clk in order to perform a soft reset
 361          * of the EMAC. If none is present, select the internal clock
 362          * (SDR0_ETH_CFG[EMACx_PHY_CLK] = 1).
 363          * After a soft reset, select the external clock.
 364          */
 365         if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX)) {
 366                 if (dev->phy_address == 0xffffffff &&
 367                     dev->phy_map == 0xffffffff) {
 368                         /* No PHY: select internal loop clock before reset */
 369                         dcri_clrset(SDR0, SDR0_ETH_CFG,
 370                                     0, SDR0_ETH_CFG_ECS << dev->cell_index);
 371                 } else {
 372                         /* PHY present: select external clock before reset */
 373                         dcri_clrset(SDR0, SDR0_ETH_CFG,
 374                                     SDR0_ETH_CFG_ECS << dev->cell_index, 0);
 375                 }
 376         }
 377 #endif
 378
 379         out_be32(&p->mr0, EMAC_MR0_SRST);
 380         while ((in_be32(&p->mr0) & EMAC_MR0_SRST) && n)
 381                 --n;
 382
 383 #ifdef CONFIG_PPC_DCR_NATIVE
 384         if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX)) {
 385                 if (dev->phy_address == 0xffffffff &&
 386                     dev->phy_map == 0xffffffff) {
 387                         /* No PHY: restore external clock source after reset */
 388                         dcri_clrset(SDR0, SDR0_ETH_CFG,
 389                                     SDR0_ETH_CFG_ECS << dev->cell_index, 0);
 390                 }
 391         }
 392 #endif
 393
 394         if (n) {
 395                 dev->reset_failed = 0;
 396                 return 0;
 397         } else {
 398                 emac_report_timeout_error(dev, "reset timeout");
 399                 dev->reset_failed = 1;
 400                 return -ETIMEDOUT;
 401         }
 402 }
 403
 404 static void emac_hash_mc(struct emac_instance *dev)
 405 {
 406         const int regs = EMAC_XAHT_REGS(dev);
 407         u32 *gaht_base = emac_gaht_base(dev);
 408         u32 gaht_temp[regs];
 409         struct netdev_hw_addr *ha;
 410         int i;
 411
 412         DBG(dev, "hash_mc %d" NL, netdev_mc_count(dev->ndev));
 413
 414         memset(gaht_temp, 0, sizeof (gaht_temp));
 415
 416         netdev_for_each_mc_addr(ha, dev->ndev) {
 417                 int slot, reg, mask;
 418                 DBG2(dev, "mc %pM" NL, ha->addr);
 419
 420                 slot = EMAC_XAHT_CRC_TO_SLOT(dev,
 421                                              ether_crc(ETH_ALEN, ha->addr));
 422                 reg = EMAC_XAHT_SLOT_TO_REG(dev, slot);
 423                 mask = EMAC_XAHT_SLOT_TO_MASK(dev, slot);
 424
 425                 gaht_temp[reg] |= mask;
 426         }
 427
 428         for (i = 0; i < regs; i++)
 429                 out_be32(gaht_base + i, gaht_temp[i]);
 430 }
 431
 432 static inline u32 emac_iff2rmr(struct net_device *ndev)
 433 {
 434         struct emac_instance *dev = netdev_priv(ndev);
 435         u32 r;
 436
 437         r = EMAC_RMR_SP | EMAC_RMR_SFCS | EMAC_RMR_IAE | EMAC_RMR_BAE;
 438
 439         if (emac_has_feature(dev, EMAC_FTR_EMAC4))
 440             r |= EMAC4_RMR_BASE;
 441         else
 442             r |= EMAC_RMR_BASE;
 443
 444         if (ndev->flags & IFF_PROMISC)
 445                 r |= EMAC_RMR_PME;
 446         else if (ndev->flags & IFF_ALLMULTI ||
 447                          (netdev_mc_count(ndev) > EMAC_XAHT_SLOTS(dev)))
 448                 r |= EMAC_RMR_PMME;
 449         else if (!netdev_mc_empty(ndev))
 450                 r |= EMAC_RMR_MAE;
 451
 452         if (emac_has_feature(dev, EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE)) {
 453                 r &= ~EMAC4_RMR_MJS_MASK;
 454                 r |= EMAC4_RMR_MJS(ndev->mtu);
 455         }
 456
 457         return r;
 458 }
 459
 460 static u32 __emac_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size)
 461 {
 462         u32 ret = EMAC_MR1_VLE | EMAC_MR1_IST | EMAC_MR1_TR0_MULT;
 463
 464         DBG2(dev, "__emac_calc_base_mr1" NL);
 465
 466         switch(tx_size) {
 467         case 2048:
 468                 ret |= EMAC_MR1_TFS_2K;
 469                 break;
 470         default:
 471                 printk(KERN_WARNING "%s: Unknown Tx FIFO size %d\n",
 472                        dev->ndev->name, tx_size);
 473         }
 474
 475         switch(rx_size) {
 476         case 16384:
 477                 ret |= EMAC_MR1_RFS_16K;
 478                 break;
 479         case 4096:
 480                 ret |= EMAC_MR1_RFS_4K;
 481                 break;
 482         default:
 483                 printk(KERN_WARNING "%s: Unknown Rx FIFO size %d\n",
 484                        dev->ndev->name, rx_size);
 485         }
 486
 487         return ret;
 488 }
 489
 490 static u32 __emac4_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size)
 491 {
 492         u32 ret = EMAC_MR1_VLE | EMAC_MR1_IST | EMAC4_MR1_TR |
 493                 EMAC4_MR1_OBCI(dev->opb_bus_freq / 1000000);
 494
 495         DBG2(dev, "__emac4_calc_base_mr1" NL);
 496
 497         switch(tx_size) {
 498         case 16384:
 499                 ret |= EMAC4_MR1_TFS_16K;
 500                 break;
 501         case 4096:
 502                 ret |= EMAC4_MR1_TFS_4K;
 503                 break;
 504         case 2048:
 505                 ret |= EMAC4_MR1_TFS_2K;
 506                 break;
 507         default:
 508                 printk(KERN_WARNING "%s: Unknown Tx FIFO size %d\n",
 509                        dev->ndev->name, tx_size);
 510         }
 511
 512         switch(rx_size) {
 513         case 16384:
 514                 ret |= EMAC4_MR1_RFS_16K;
 515                 break;
 516         case 4096:
 517                 ret |= EMAC4_MR1_RFS_4K;
 518                 break;
 519         case 2048:
 520                 ret |= EMAC4_MR1_RFS_2K;
 521                 break;
 522         default:
 523                 printk(KERN_WARNING "%s: Unknown Rx FIFO size %d\n",
 524                        dev->ndev->name, rx_size);
 525         }
 526
 527         return ret;
 528 }
 529
 530 static u32 emac_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size)
 531 {
 532         return emac_has_feature(dev, EMAC_FTR_EMAC4) ?
 533                 __emac4_calc_base_mr1(dev, tx_size, rx_size) :
 534                 __emac_calc_base_mr1(dev, tx_size, rx_size);
 535 }
 536
 537 static inline u32 emac_calc_trtr(struct emac_instance *dev, unsigned int size)
 538 {
 539         if (emac_has_feature(dev, EMAC_FTR_EMAC4))
 540                 return ((size >> 6) - 1) << EMAC_TRTR_SHIFT_EMAC4;
 541         else
 542                 return ((size >> 6) - 1) << EMAC_TRTR_SHIFT;
 543 }
 544
 545 static inline u32 emac_calc_rwmr(struct emac_instance *dev,
 546                                  unsigned int low, unsigned int high)
 547 {
 548         if (emac_has_feature(dev, EMAC_FTR_EMAC4))
 549                 return (low << 22) | ( (high & 0x3ff) << 6);
 550         else
 551                 return (low << 23) | ( (high & 0x1ff) << 7);
 552 }
 553
 554 static int emac_configure(struct emac_instance *dev)
 555 {
 556         struct emac_regs __iomem *p = dev->emacp;
 557         struct net_device *ndev = dev->ndev;
 558         int tx_size, rx_size, link = netif_carrier_ok(dev->ndev);
 559         u32 r, mr1 = 0;
 560
 561         DBG(dev, "configure" NL);
 562
 563         if (!link) {
 564                 out_be32(&p->mr1, in_be32(&p->mr1)
 565                          | EMAC_MR1_FDE | EMAC_MR1_ILE);
 566                 udelay(100);
 567         } else if (emac_reset(dev) < 0)
 568                 return -ETIMEDOUT;
 569
 570         if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
 571                 tah_reset(dev->tah_dev);
 572
 573         DBG(dev, " link = %d duplex = %d, pause = %d, asym_pause = %d\n",
 574             link, dev->phy.duplex, dev->phy.pause, dev->phy.asym_pause);
 575
 576         /* Default fifo sizes */
 577         tx_size = dev->tx_fifo_size;
 578         rx_size = dev->rx_fifo_size;
 579
 580         /* No link, force loopback */
 581         if (!link)
 582                 mr1 = EMAC_MR1_FDE | EMAC_MR1_ILE;
 583
 584         /* Check for full duplex */
 585         else if (dev->phy.duplex == DUPLEX_FULL)
 586                 mr1 |= EMAC_MR1_FDE | EMAC_MR1_MWSW_001;
 587
 588         /* Adjust fifo sizes, mr1 and timeouts based on link speed */
 589         dev->stop_timeout = STOP_TIMEOUT_10;
 590         switch (dev->phy.speed) {
 591         case SPEED_1000:
 592                 if (emac_phy_gpcs(dev->phy.mode)) {
 593                         mr1 |= EMAC_MR1_MF_1000GPCS | EMAC_MR1_MF_IPPA(
 594                                 (dev->phy.gpcs_address != 0xffffffff) ?
 595                                  dev->phy.gpcs_address : dev->phy.address);
 596
 597                         /* Put some arbitrary OUI, Manuf & Rev IDs so we can
 598                          * identify this GPCS PHY later.
 599                          */
 600                         out_be32(&p->u1.emac4.ipcr, 0xdeadbeef);
 601                 } else
 602                         mr1 |= EMAC_MR1_MF_1000;
 603
 604                 /* Extended fifo sizes */
 605                 tx_size = dev->tx_fifo_size_gige;
 606                 rx_size = dev->rx_fifo_size_gige;
 607
 608                 if (dev->ndev->mtu > ETH_DATA_LEN) {
 609                         if (emac_has_feature(dev, EMAC_FTR_EMAC4))
 610                                 mr1 |= EMAC4_MR1_JPSM;
 611                         else
 612                                 mr1 |= EMAC_MR1_JPSM;
 613                         dev->stop_timeout = STOP_TIMEOUT_1000_JUMBO;
 614                 } else
 615                         dev->stop_timeout = STOP_TIMEOUT_1000;
 616                 break;
 617         case SPEED_100:
 618                 mr1 |= EMAC_MR1_MF_100;
 619                 dev->stop_timeout = STOP_TIMEOUT_100;
 620                 break;
 621         default: /* make gcc happy */
 622                 break;
 623         }
 624
 625         if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
 626                 rgmii_set_speed(dev->rgmii_dev, dev->rgmii_port,
 627                                 dev->phy.speed);
 628         if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
 629                 zmii_set_speed(dev->zmii_dev, dev->zmii_port, dev->phy.speed);
 630
 631         /* on 40x erratum forces us to NOT use integrated flow control,
 632          * let's hope it works on 44x ;)
 633          */
 634         if (!emac_has_feature(dev, EMAC_FTR_NO_FLOW_CONTROL_40x) &&
 635             dev->phy.duplex == DUPLEX_FULL) {
 636                 if (dev->phy.pause)
 637                         mr1 |= EMAC_MR1_EIFC | EMAC_MR1_APP;
 638                 else if (dev->phy.asym_pause)
 639                         mr1 |= EMAC_MR1_APP;
 640         }
 641
 642         /* Add base settings & fifo sizes & program MR1 */
 643         mr1 |= emac_calc_base_mr1(dev, tx_size, rx_size);
 644         out_be32(&p->mr1, mr1);
 645
 646         /* Set individual MAC address */
 647         out_be32(&p->iahr, (ndev->dev_addr[0] << 8) | ndev->dev_addr[1]);
 648         out_be32(&p->ialr, (ndev->dev_addr[2] << 24) |
 649                  (ndev->dev_addr[3] << 16) | (ndev->dev_addr[4] << 8) |
 650                  ndev->dev_addr[5]);
 651
 652         /* VLAN Tag Protocol ID */
 653         out_be32(&p->vtpid, 0x8100);
 654
 655         /* Receive mode register */
 656         r = emac_iff2rmr(ndev);
 657         if (r & EMAC_RMR_MAE)
 658                 emac_hash_mc(dev);
 659         out_be32(&p->rmr, r);
 660
 661         /* FIFOs thresholds */
 662         if (emac_has_feature(dev, EMAC_FTR_EMAC4))
 663                 r = EMAC4_TMR1((dev->mal_burst_size / dev->fifo_entry_size) + 1,
 664                                tx_size / 2 / dev->fifo_entry_size);
 665         else
 666                 r = EMAC_TMR1((dev->mal_burst_size / dev->fifo_entry_size) + 1,
 667                               tx_size / 2 / dev->fifo_entry_size);
 668         out_be32(&p->tmr1, r);
 669         out_be32(&p->trtr, emac_calc_trtr(dev, tx_size / 2));
 670
 671         /* PAUSE frame is sent when RX FIFO reaches its high-water mark,
 672            there should be still enough space in FIFO to allow the our link
 673            partner time to process this frame and also time to send PAUSE
 674            frame itself.
 675
 676            Here is the worst case scenario for the RX FIFO "headroom"
 677            (from "The Switch Book") (100Mbps, without preamble, inter-frame gap):
 678
 679            1) One maximum-length frame on TX                    1522 bytes
 680            2) One PAUSE frame time                                64 bytes
 681            3) PAUSE frame decode time allowance                   64 bytes
 682            4) One maximum-length frame on RX                    1522 bytes
 683            5) Round-trip propagation delay of the link (100Mb)    15 bytes
 684            ----------
 685            3187 bytes
 686
 687            I chose to set high-water mark to RX_FIFO_SIZE / 4 (1024 bytes)
 688            low-water mark  to RX_FIFO_SIZE / 8 (512 bytes)
 689          */
 690         r = emac_calc_rwmr(dev, rx_size / 8 / dev->fifo_entry_size,
 691                            rx_size / 4 / dev->fifo_entry_size);
 692         out_be32(&p->rwmr, r);
 693
 694         /* Set PAUSE timer to the maximum */
 695         out_be32(&p->ptr, 0xffff);
 696
 697         /* IRQ sources */
 698         r = EMAC_ISR_OVR | EMAC_ISR_BP | EMAC_ISR_SE |
 699                 EMAC_ISR_ALE | EMAC_ISR_BFCS | EMAC_ISR_PTLE | EMAC_ISR_ORE |
 700                 EMAC_ISR_IRE | EMAC_ISR_TE;
 701         if (emac_has_feature(dev, EMAC_FTR_EMAC4))
 702             r |= EMAC4_ISR_TXPE | EMAC4_ISR_RXPE /* | EMAC4_ISR_TXUE |
 703                                                   EMAC4_ISR_RXOE | */;
 704         out_be32(&p->iser,  r);
 705
 706         /* We need to take GPCS PHY out of isolate mode after EMAC reset */
 707         if (emac_phy_gpcs(dev->phy.mode)) {
 708                 if (dev->phy.gpcs_address != 0xffffffff)
 709                         emac_mii_reset_gpcs(&dev->phy);
 710                 else
 711                         emac_mii_reset_phy(&dev->phy);
 712         }
 713
 714         return 0;
 715 }
 716
 717 static void emac_reinitialize(struct emac_instance *dev)
 718 {
 719         DBG(dev, "reinitialize" NL);
 720
 721         emac_netif_stop(dev);
 722         if (!emac_configure(dev)) {
 723                 emac_tx_enable(dev);
 724                 emac_rx_enable(dev);
 725         }
 726         emac_netif_start(dev);
 727 }
 728
 729 static void emac_full_tx_reset(struct emac_instance *dev)
 730 {
 731         DBG(dev, "full_tx_reset" NL);
 732
 733         emac_tx_disable(dev);
 734         mal_disable_tx_channel(dev->mal, dev->mal_tx_chan);
 735         emac_clean_tx_ring(dev);
 736         dev->tx_cnt = dev->tx_slot = dev->ack_slot = 0;
 737
 738         emac_configure(dev);
 739
 740         mal_enable_tx_channel(dev->mal, dev->mal_tx_chan);
 741         emac_tx_enable(dev);
 742         emac_rx_enable(dev);
 743 }
 744
 745 static void emac_reset_work(struct work_struct *work)
 746 {
 747         struct emac_instance *dev = container_of(work, struct emac_instance, reset_work);
 748
 749         DBG(dev, "reset_work" NL);
 750
 751         mutex_lock(&dev->link_lock);
 752         if (dev->opened) {
 753                 emac_netif_stop(dev);
 754                 emac_full_tx_reset(dev);
 755                 emac_netif_start(dev);
 756         }
 757         mutex_unlock(&dev->link_lock);
 758 }
 759
 760 static void emac_tx_timeout(struct net_device *ndev)
 761 {
 762         struct emac_instance *dev = netdev_priv(ndev);
 763
 764         DBG(dev, "tx_timeout" NL);
 765
 766         schedule_work(&dev->reset_work);
 767 }
 768
 769
 770 static inline int emac_phy_done(struct emac_instance *dev, u32 stacr)
 771 {
 772         int done = !!(stacr & EMAC_STACR_OC);
 773
 774         if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT))
 775                 done = !done;
 776
 777         return done;
 778 };
 779
 780 static int __emac_mdio_read(struct emac_instance *dev, u8 id, u8 reg)
 781 {
 782         struct emac_regs __iomem *p = dev->emacp;
 783         u32 r = 0;
 784         int n, err = -ETIMEDOUT;
 785
 786         mutex_lock(&dev->mdio_lock);
 787
 788         DBG2(dev, "mdio_read(%02x,%02x)" NL, id, reg);
 789
 790         /* Enable proper MDIO port */
 791         if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
 792                 zmii_get_mdio(dev->zmii_dev, dev->zmii_port);
 793         if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
 794                 rgmii_get_mdio(dev->rgmii_dev, dev->rgmii_port);
 795
 796         /* Wait for management interface to become idle */
 797         n = 20;
 798         while (!emac_phy_done(dev, in_be32(&p->stacr))) {
 799                 udelay(1);
 800                 if (!--n) {
 801                         DBG2(dev, " -> timeout wait idle\n");
 802                         goto bail;
 803                 }
 804         }
 805
 806         /* Issue read command */
 807         if (emac_has_feature(dev, EMAC_FTR_EMAC4))
 808                 r = EMAC4_STACR_BASE(dev->opb_bus_freq);
 809         else
 810                 r = EMAC_STACR_BASE(dev->opb_bus_freq);
 811         if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT))
 812                 r |= EMAC_STACR_OC;
 813         if (emac_has_feature(dev, EMAC_FTR_HAS_NEW_STACR))
 814                 r |= EMACX_STACR_STAC_READ;
 815         else
 816                 r |= EMAC_STACR_STAC_READ;
 817         r |= (reg & EMAC_STACR_PRA_MASK)
 818                 | ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT);
 819         out_be32(&p->stacr, r);
 820
 821         /* Wait for read to complete */
 822         n = 200;
 823         while (!emac_phy_done(dev, (r = in_be32(&p->stacr)))) {
 824                 udelay(1);
 825                 if (!--n) {
 826                         DBG2(dev, " -> timeout wait complete\n");
 827                         goto bail;
 828                 }
 829         }
 830
 831         if (unlikely(r & EMAC_STACR_PHYE)) {
 832                 DBG(dev, "mdio_read(%02x, %02x) failed" NL, id, reg);
 833                 err = -EREMOTEIO;
 834                 goto bail;
 835         }
 836
 837         r = ((r >> EMAC_STACR_PHYD_SHIFT) & EMAC_STACR_PHYD_MASK);
 838
 839         DBG2(dev, "mdio_read -> %04x" NL, r);
 840         err = 0;
 841  bail:
 842         if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
 843                 rgmii_put_mdio(dev->rgmii_dev, dev->rgmii_port);
 844         if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
 845                 zmii_put_mdio(dev->zmii_dev, dev->zmii_port);
 846         mutex_unlock(&dev->mdio_lock);
 847
 848         return err == 0 ? r : err;
 849 }
 850
 851 static void __emac_mdio_write(struct emac_instance *dev, u8 id, u8 reg,
 852                               u16 val)
 853 {
 854         struct emac_regs __iomem *p = dev->emacp;
 855         u32 r = 0;
 856         int n, err = -ETIMEDOUT;
 857
 858         mutex_lock(&dev->mdio_lock);
 859
 860         DBG2(dev, "mdio_write(%02x,%02x,%04x)" NL, id, reg, val);
 861
 862         /* Enable proper MDIO port */
 863         if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
 864                 zmii_get_mdio(dev->zmii_dev, dev->zmii_port);
 865         if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
 866                 rgmii_get_mdio(dev->rgmii_dev, dev->rgmii_port);
 867
 868         /* Wait for management interface to be idle */
 869         n = 20;
 870         while (!emac_phy_done(dev, in_be32(&p->stacr))) {
 871                 udelay(1);
 872                 if (!--n) {
 873                         DBG2(dev, " -> timeout wait idle\n");
 874                         goto bail;
 875                 }
 876         }
 877
 878         /* Issue write command */
 879         if (emac_has_feature(dev, EMAC_FTR_EMAC4))
 880                 r = EMAC4_STACR_BASE(dev->opb_bus_freq);
 881         else
 882                 r = EMAC_STACR_BASE(dev->opb_bus_freq);
 883         if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT))
 884                 r |= EMAC_STACR_OC;
 885         if (emac_has_feature(dev, EMAC_FTR_HAS_NEW_STACR))
 886                 r |= EMACX_STACR_STAC_WRITE;
 887         else
 888                 r |= EMAC_STACR_STAC_WRITE;
 889         r |= (reg & EMAC_STACR_PRA_MASK) |
 890                 ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT) |
 891                 (val << EMAC_STACR_PHYD_SHIFT);
 892         out_be32(&p->stacr, r);
 893
 894         /* Wait for write to complete */
 895         n = 200;
 896         while (!emac_phy_done(dev, in_be32(&p->stacr))) {
 897                 udelay(1);
 898                 if (!--n) {
 899                         DBG2(dev, " -> timeout wait complete\n");
 900                         goto bail;
 901                 }
 902         }
 903         err = 0;
 904  bail:
 905         if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
 906                 rgmii_put_mdio(dev->rgmii_dev, dev->rgmii_port);
 907         if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
 908                 zmii_put_mdio(dev->zmii_dev, dev->zmii_port);
 909         mutex_unlock(&dev->mdio_lock);
 910 }
 911
 912 static int emac_mdio_read(struct net_device *ndev, int id, int reg)
 913 {
 914         struct emac_instance *dev = netdev_priv(ndev);
 915         int res;
 916
 917         res = __emac_mdio_read((dev->mdio_instance &&
 918                                 dev->phy.gpcs_address != id) ?
 919                                 dev->mdio_instance : dev,
 920                                (u8) id, (u8) reg);
 921         return res;
 922 }
 923
 924 static void emac_mdio_write(struct net_device *ndev, int id, int reg, int val)
 925 {
 926         struct emac_instance *dev = netdev_priv(ndev);
 927
 928         __emac_mdio_write((dev->mdio_instance &&
 929                            dev->phy.gpcs_address != id) ?
 930                            dev->mdio_instance : dev,
 931                           (u8) id, (u8) reg, (u16) val);
 932 }
 933
 934 /* Tx lock BH */
 935 static void __emac_set_multicast_list(struct emac_instance *dev)
 936 {
 937         struct emac_regs __iomem *p = dev->emacp;
 938         u32 rmr = emac_iff2rmr(dev->ndev);
 939
 940         DBG(dev, "__multicast %08x" NL, rmr);
 941
 942         /* I decided to relax register access rules here to avoid
 943          * full EMAC reset.
 944          *
 945          * There is a real problem with EMAC4 core if we use MWSW_001 bit
 946          * in MR1 register and do a full EMAC reset.
 947          * One TX BD status update is delayed and, after EMAC reset, it
 948          * never happens, resulting in TX hung (it'll be recovered by TX
 949          * timeout handler eventually, but this is just gross).
 950          * So we either have to do full TX reset or try to cheat here :)
 951          *
 952          * The only required change is to RX mode register, so I *think* all
 953          * we need is just to stop RX channel. This seems to work on all
 954          * tested SoCs.                                                --ebs
 955          *
 956          * If we need the full reset, we might just trigger the workqueue
 957          * and do it async... a bit nasty but should work --BenH
 958          */
 959         dev->mcast_pending = 0;
 960         emac_rx_disable(dev);
 961         if (rmr & EMAC_RMR_MAE)
 962                 emac_hash_mc(dev);
 963         out_be32(&p->rmr, rmr);
 964         emac_rx_enable(dev);
 965 }
 966
 967 /* Tx lock BH */
 968 static void emac_set_multicast_list(struct net_device *ndev)
 969 {
 970         struct emac_instance *dev = netdev_priv(ndev);
 971
 972         DBG(dev, "multicast" NL);
 973
 974         BUG_ON(!netif_running(dev->ndev));
 975
 976         if (dev->no_mcast) {
 977                 dev->mcast_pending = 1;
 978                 return;
 979         }
 980
 981         mutex_lock(&dev->link_lock);
 982         __emac_set_multicast_list(dev);
 983         mutex_unlock(&dev->link_lock);
 984 }
 985
 986 static int emac_set_mac_address(struct net_device *ndev, void *sa)
 987 {
 988         struct emac_instance *dev = netdev_priv(ndev);
 989         struct sockaddr *addr = sa;
 990         struct emac_regs __iomem *p = dev->emacp;
 991
 992         if (!is_valid_ether_addr(addr->sa_data))
 993                return -EADDRNOTAVAIL;
 994
 995         mutex_lock(&dev->link_lock);
 996
 997         memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
 998
 999         emac_rx_disable(dev);
1000         emac_tx_disable(dev);
1001         out_be32(&p->iahr, (ndev->dev_addr[0] << 8) | ndev->dev_addr[1]);
1002         out_be32(&p->ialr, (ndev->dev_addr[2] << 24) |
1003                 (ndev->dev_addr[3] << 16) | (ndev->dev_addr[4] << 8) |
1004                 ndev->dev_addr[5]);
1005         emac_tx_enable(dev);
1006         emac_rx_enable(dev);
1007
1008         mutex_unlock(&dev->link_lock);
1009
1010         return 0;
1011 }
1012
1013 static int emac_resize_rx_ring(struct emac_instance *dev, int new_mtu)
1014 {
1015         int rx_sync_size = emac_rx_sync_size(new_mtu);
1016         int rx_skb_size = emac_rx_skb_size(new_mtu);
1017         int i, ret = 0;
1018         int mr1_jumbo_bit_change = 0;
1019
1020         mutex_lock(&dev->link_lock);
1021         emac_netif_stop(dev);
1022         emac_rx_disable(dev);
1023         mal_disable_rx_channel(dev->mal, dev->mal_rx_chan);
1024
1025         if (dev->rx_sg_skb) {
1026                 ++dev->estats.rx_dropped_resize;
1027                 dev_kfree_skb(dev->rx_sg_skb);
1028                 dev->rx_sg_skb = NULL;
1029         }
1030
1031         /* Make a first pass over RX ring and mark BDs ready, dropping
1032          * non-processed packets on the way. We need this as a separate pass
1033          * to simplify error recovery in the case of allocation failure later.
1034          */
1035         for (i = 0; i < NUM_RX_BUFF; ++i) {
1036                 if (dev->rx_desc[i].ctrl & MAL_RX_CTRL_FIRST)
1037                         ++dev->estats.rx_dropped_resize;
1038
1039                 dev->rx_desc[i].data_len = 0;
1040                 dev->rx_desc[i].ctrl = MAL_RX_CTRL_EMPTY |
1041                     (i == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
1042         }
1043
1044         /* Reallocate RX ring only if bigger skb buffers are required */
1045         if (rx_skb_size <= dev->rx_skb_size)
1046                 goto skip;
1047
1048         /* Second pass, allocate new skbs */
1049         for (i = 0; i < NUM_RX_BUFF; ++i) {
1050                 struct sk_buff *skb = alloc_skb(rx_skb_size, GFP_ATOMIC);
1051                 if (!skb) {
1052                         ret = -ENOMEM;
1053                         goto oom;
1054                 }
1055
1056                 BUG_ON(!dev->rx_skb[i]);
1057                 dev_kfree_skb(dev->rx_skb[i]);
1058
1059                 skb_reserve(skb, EMAC_RX_SKB_HEADROOM + 2);
1060                 dev->rx_desc[i].data_ptr =
1061                     dma_map_single(&dev->ofdev->dev, skb->data - 2, rx_sync_size,
1062                                    DMA_FROM_DEVICE) + 2;
1063                 dev->rx_skb[i] = skb;
1064         }
1065  skip:
1066         /* Check if we need to change "Jumbo" bit in MR1 */
1067         if (emac_has_feature(dev, EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE)) {
1068                 mr1_jumbo_bit_change = (new_mtu > ETH_DATA_LEN) ||
1069                                 (dev->ndev->mtu > ETH_DATA_LEN);
1070         } else {
1071                 mr1_jumbo_bit_change = (new_mtu > ETH_DATA_LEN) ^
1072                                 (dev->ndev->mtu > ETH_DATA_LEN);
1073         }
1074
1075         if (mr1_jumbo_bit_change) {
1076                 /* This is to prevent starting RX channel in emac_rx_enable() */
1077                 set_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1078
1079                 dev->ndev->mtu = new_mtu;
1080                 emac_full_tx_reset(dev);
1081         }
1082
1083         mal_set_rcbs(dev->mal, dev->mal_rx_chan, emac_rx_size(new_mtu));
1084  oom:
1085         /* Restart RX */
1086         clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1087         dev->rx_slot = 0;
1088         mal_enable_rx_channel(dev->mal, dev->mal_rx_chan);
1089         emac_rx_enable(dev);
1090         emac_netif_start(dev);
1091         mutex_unlock(&dev->link_lock);
1092
1093         return ret;
1094 }
1095
1096 /* Process ctx, rtnl_lock semaphore */
1097 static int emac_change_mtu(struct net_device *ndev, int new_mtu)
1098 {
1099         struct emac_instance *dev = netdev_priv(ndev);
1100         int ret = 0;
1101
1102         if (new_mtu < EMAC_MIN_MTU || new_mtu > dev->max_mtu)
1103                 return -EINVAL;
1104
1105         DBG(dev, "change_mtu(%d)" NL, new_mtu);
1106
1107         if (netif_running(ndev)) {
1108                 /* Check if we really need to reinitialize RX ring */
1109                 if (emac_rx_skb_size(ndev->mtu) != emac_rx_skb_size(new_mtu))
1110                         ret = emac_resize_rx_ring(dev, new_mtu);
1111         }
1112
1113         if (!ret) {
1114                 ndev->mtu = new_mtu;
1115                 dev->rx_skb_size = emac_rx_skb_size(new_mtu);
1116                 dev->rx_sync_size = emac_rx_sync_size(new_mtu);
1117         }
1118
1119         return ret;
1120 }
1121
1122 static void emac_clean_tx_ring(struct emac_instance *dev)
1123 {
1124         int i;
1125
1126         for (i = 0; i < NUM_TX_BUFF; ++i) {
1127                 if (dev->tx_skb[i]) {
1128                         dev_kfree_skb(dev->tx_skb[i]);
1129                         dev->tx_skb[i] = NULL;
1130                         if (dev->tx_desc[i].ctrl & MAL_TX_CTRL_READY)
1131                                 ++dev->estats.tx_dropped;
1132                 }
1133                 dev->tx_desc[i].ctrl = 0;
1134                 dev->tx_desc[i].data_ptr = 0;
1135         }
1136 }
1137
1138 static void emac_clean_rx_ring(struct emac_instance *dev)
1139 {
1140         int i;
1141
1142         for (i = 0; i < NUM_RX_BUFF; ++i)
1143                 if (dev->rx_skb[i]) {
1144                         dev->rx_desc[i].ctrl = 0;
1145                         dev_kfree_skb(dev->rx_skb[i]);
1146                         dev->rx_skb[i] = NULL;
1147                         dev->rx_desc[i].data_ptr = 0;
1148                 }
1149
1150         if (dev->rx_sg_skb) {
1151                 dev_kfree_skb(dev->rx_sg_skb);
1152                 dev->rx_sg_skb = NULL;
1153         }
1154 }
1155
1156 static inline int emac_alloc_rx_skb(struct emac_instance *dev, int slot,
1157                                     gfp_t flags)
1158 {
1159         struct sk_buff *skb = alloc_skb(dev->rx_skb_size, flags);
1160         if (unlikely(!skb))
1161                 return -ENOMEM;
1162
1163         dev->rx_skb[slot] = skb;
1164         dev->rx_desc[slot].data_len = 0;
1165
1166         skb_reserve(skb, EMAC_RX_SKB_HEADROOM + 2);
1167         dev->rx_desc[slot].data_ptr =
1168             dma_map_single(&dev->ofdev->dev, skb->data - 2, dev->rx_sync_size,
1169                            DMA_FROM_DEVICE) + 2;
1170         wmb();
1171         dev->rx_desc[slot].ctrl = MAL_RX_CTRL_EMPTY |
1172             (slot == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
1173
1174         return 0;
1175 }
1176
1177 static void emac_print_link_status(struct emac_instance *dev)
1178 {
1179         if (netif_carrier_ok(dev->ndev))
1180                 printk(KERN_INFO "%s: link is up, %d %s%s\n",
1181                        dev->ndev->name, dev->phy.speed,
1182                        dev->phy.duplex == DUPLEX_FULL ? "FDX" : "HDX",
1183                        dev->phy.pause ? ", pause enabled" :
1184                        dev->phy.asym_pause ? ", asymmetric pause enabled" : "");
1185         else
1186                 printk(KERN_INFO "%s: link is down\n", dev->ndev->name);
1187 }
1188
1189 /* Process ctx, rtnl_lock semaphore */
1190 static int emac_open(struct net_device *ndev)
1191 {
1192         struct emac_instance *dev = netdev_priv(ndev);
1193         int err, i;
1194
1195         DBG(dev, "open" NL);
1196
1197         /* Setup error IRQ handler */
1198         err = request_irq(dev->emac_irq, emac_irq, 0, "EMAC", dev);
1199         if (err) {
1200                 printk(KERN_ERR "%s: failed to request IRQ %d\n",
1201                        ndev->name, dev->emac_irq);
1202                 return err;
1203         }
1204
1205         /* Allocate RX ring */
1206         for (i = 0; i < NUM_RX_BUFF; ++i)
1207                 if (emac_alloc_rx_skb(dev, i, GFP_KERNEL)) {
1208                         printk(KERN_ERR "%s: failed to allocate RX ring\n",
1209                                ndev->name);
1210                         goto oom;
1211                 }
1212
1213         dev->tx_cnt = dev->tx_slot = dev->ack_slot = dev->rx_slot = 0;
1214         clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1215         dev->rx_sg_skb = NULL;
1216
1217         mutex_lock(&dev->link_lock);
1218         dev->opened = 1;
1219
1220         /* Start PHY polling now.
1221          */
1222         if (dev->phy.address >= 0) {
1223                 int link_poll_interval;
1224                 if (dev->phy.def->ops->poll_link(&dev->phy)) {
1225                         dev->phy.def->ops->read_link(&dev->phy);
1226                         emac_rx_clk_default(dev);
1227                         netif_carrier_on(dev->ndev);
1228                         link_poll_interval = PHY_POLL_LINK_ON;
1229                 } else {
1230                         emac_rx_clk_tx(dev);
1231                         netif_carrier_off(dev->ndev);
1232                         link_poll_interval = PHY_POLL_LINK_OFF;
1233                 }
1234                 dev->link_polling = 1;
1235                 wmb();
1236                 schedule_delayed_work(&dev->link_work, link_poll_interval);
1237                 emac_print_link_status(dev);
1238         } else
1239                 netif_carrier_on(dev->ndev);
1240
1241         /* Required for Pause packet support in EMAC */
1242         dev_mc_add_global(ndev, default_mcast_addr);
1243
1244         emac_configure(dev);
1245         mal_poll_add(dev->mal, &dev->commac);
1246         mal_enable_tx_channel(dev->mal, dev->mal_tx_chan);
1247         mal_set_rcbs(dev->mal, dev->mal_rx_chan, emac_rx_size(ndev->mtu));
1248         mal_enable_rx_channel(dev->mal, dev->mal_rx_chan);
1249         emac_tx_enable(dev);
1250         emac_rx_enable(dev);
1251         emac_netif_start(dev);
1252
1253         mutex_unlock(&dev->link_lock);
1254
1255         return 0;
1256  oom:
1257         emac_clean_rx_ring(dev);
1258         free_irq(dev->emac_irq, dev);
1259
1260         return -ENOMEM;
1261 }
1262
1263 /* BHs disabled */
1264 #if 0
1265 static int emac_link_differs(struct emac_instance *dev)
1266 {
1267         u32 r = in_be32(&dev->emacp->mr1);
1268
1269         int duplex = r & EMAC_MR1_FDE ? DUPLEX_FULL : DUPLEX_HALF;
1270         int speed, pause, asym_pause;
1271
1272         if (r & EMAC_MR1_MF_1000)
1273                 speed = SPEED_1000;
1274         else if (r & EMAC_MR1_MF_100)
1275                 speed = SPEED_100;
1276         else
1277                 speed = SPEED_10;
1278
1279         switch (r & (EMAC_MR1_EIFC | EMAC_MR1_APP)) {
1280         case (EMAC_MR1_EIFC | EMAC_MR1_APP):
1281                 pause = 1;
1282                 asym_pause = 0;
1283                 break;
1284         case EMAC_MR1_APP:
1285                 pause = 0;
1286                 asym_pause = 1;
1287                 break;
1288         default:
1289                 pause = asym_pause = 0;
1290         }
1291         return speed != dev->phy.speed || duplex != dev->phy.duplex ||
1292             pause != dev->phy.pause || asym_pause != dev->phy.asym_pause;
1293 }
1294 #endif
1295
1296 static void emac_link_timer(struct work_struct *work)
1297 {
1298         struct emac_instance *dev =
1299                 container_of(to_delayed_work(work),
1300                              struct emac_instance, link_work);
1301         int link_poll_interval;
1302
1303         mutex_lock(&dev->link_lock);
1304         DBG2(dev, "link timer" NL);
1305
1306         if (!dev->opened)
1307                 goto bail;
1308
1309         if (dev->phy.def->ops->poll_link(&dev->phy)) {
1310                 if (!netif_carrier_ok(dev->ndev)) {
1311                         emac_rx_clk_default(dev);
1312                         /* Get new link parameters */
1313                         dev->phy.def->ops->read_link(&dev->phy);
1314
1315                         netif_carrier_on(dev->ndev);
1316                         emac_netif_stop(dev);
1317                         emac_full_tx_reset(dev);
1318                         emac_netif_start(dev);
1319                         emac_print_link_status(dev);
1320                 }
1321                 link_poll_interval = PHY_POLL_LINK_ON;
1322         } else {
1323                 if (netif_carrier_ok(dev->ndev)) {
1324                         emac_rx_clk_tx(dev);
1325                         netif_carrier_off(dev->ndev);
1326                         netif_tx_disable(dev->ndev);
1327                         emac_reinitialize(dev);
1328                         emac_print_link_status(dev);
1329                 }
1330                 link_poll_interval = PHY_POLL_LINK_OFF;
1331         }
1332         schedule_delayed_work(&dev->link_work, link_poll_interval);
1333  bail:
1334         mutex_unlock(&dev->link_lock);
1335 }
1336
1337 static void emac_force_link_update(struct emac_instance *dev)
1338 {
1339         netif_carrier_off(dev->ndev);
1340         smp_rmb();
1341         if (dev->link_polling) {
1342                 cancel_delayed_work_sync(&dev->link_work);
1343                 if (dev->link_polling)
1344                         schedule_delayed_work(&dev->link_work,  PHY_POLL_LINK_OFF);
1345         }
1346 }
1347
1348 /* Process ctx, rtnl_lock semaphore */
1349 static int emac_close(struct net_device *ndev)
1350 {
1351         struct emac_instance *dev = netdev_priv(ndev);
1352
1353         DBG(dev, "close" NL);
1354
1355         if (dev->phy.address >= 0) {
1356                 dev->link_polling = 0;
1357                 cancel_delayed_work_sync(&dev->link_work);
1358         }
1359         mutex_lock(&dev->link_lock);
1360         emac_netif_stop(dev);
1361         dev->opened = 0;
1362         mutex_unlock(&dev->link_lock);
1363
1364         emac_rx_disable(dev);
1365         emac_tx_disable(dev);
1366         mal_disable_rx_channel(dev->mal, dev->mal_rx_chan);
1367         mal_disable_tx_channel(dev->mal, dev->mal_tx_chan);
1368         mal_poll_del(dev->mal, &dev->commac);
1369
1370         emac_clean_tx_ring(dev);
1371         emac_clean_rx_ring(dev);
1372
1373         free_irq(dev->emac_irq, dev);
1374
1375         netif_carrier_off(ndev);
1376
1377         return 0;
1378 }
1379
1380 static inline u16 emac_tx_csum(struct emac_instance *dev,
1381                                struct sk_buff *skb)
1382 {
1383         if (emac_has_feature(dev, EMAC_FTR_HAS_TAH) &&
1384                 (skb->ip_summed == CHECKSUM_PARTIAL)) {
1385                 ++dev->stats.tx_packets_csum;
1386                 return EMAC_TX_CTRL_TAH_CSUM;
1387         }
1388         return 0;
1389 }
1390
1391 static inline int emac_xmit_finish(struct emac_instance *dev, int len)
1392 {
1393         struct emac_regs __iomem *p = dev->emacp;
1394         struct net_device *ndev = dev->ndev;
1395
1396         /* Send the packet out. If the if makes a significant perf
1397          * difference, then we can store the TMR0 value in "dev"
1398          * instead
1399          */
1400         if (emac_has_feature(dev, EMAC_FTR_EMAC4))
1401                 out_be32(&p->tmr0, EMAC4_TMR0_XMIT);
1402         else
1403                 out_be32(&p->tmr0, EMAC_TMR0_XMIT);
1404
1405         if (unlikely(++dev->tx_cnt == NUM_TX_BUFF)) {
1406                 netif_stop_queue(ndev);
1407                 DBG2(dev, "stopped TX queue" NL);
1408         }
1409
1410         netif_trans_update(ndev);
1411         ++dev->stats.tx_packets;
1412         dev->stats.tx_bytes += len;
1413
1414         return NETDEV_TX_OK;
1415 }
1416
1417 /* Tx lock BH */
1418 static int emac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1419 {
1420         struct emac_instance *dev = netdev_priv(ndev);
1421         unsigned int len = skb->len;
1422         int slot;
1423
1424         u16 ctrl = EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP | MAL_TX_CTRL_READY |
1425             MAL_TX_CTRL_LAST | emac_tx_csum(dev, skb);
1426
1427         slot = dev->tx_slot++;
1428         if (dev->tx_slot == NUM_TX_BUFF) {
1429                 dev->tx_slot = 0;
1430                 ctrl |= MAL_TX_CTRL_WRAP;
1431         }
1432
1433         DBG2(dev, "xmit(%u) %d" NL, len, slot);
1434
1435         dev->tx_skb[slot] = skb;
1436         dev->tx_desc[slot].data_ptr = dma_map_single(&dev->ofdev->dev,
1437                                                      skb->data, len,
1438                                                      DMA_TO_DEVICE);
1439         dev->tx_desc[slot].data_len = (u16) len;
1440         wmb();
1441         dev->tx_desc[slot].ctrl = ctrl;
1442
1443         return emac_xmit_finish(dev, len);
1444 }
1445
1446 static inline int emac_xmit_split(struct emac_instance *dev, int slot,
1447                                   u32 pd, int len, int last, u16 base_ctrl)
1448 {
1449         while (1) {
1450                 u16 ctrl = base_ctrl;
1451                 int chunk = min(len, MAL_MAX_TX_SIZE);
1452                 len -= chunk;
1453
1454                 slot = (slot + 1) % NUM_TX_BUFF;
1455
1456                 if (last && !len)
1457                         ctrl |= MAL_TX_CTRL_LAST;
1458                 if (slot == NUM_TX_BUFF - 1)
1459                         ctrl |= MAL_TX_CTRL_WRAP;
1460
1461                 dev->tx_skb[slot] = NULL;
1462                 dev->tx_desc[slot].data_ptr = pd;
1463                 dev->tx_desc[slot].data_len = (u16) chunk;
1464                 dev->tx_desc[slot].ctrl = ctrl;
1465                 ++dev->tx_cnt;
1466
1467                 if (!len)
1468                         break;
1469
1470                 pd += chunk;
1471         }
1472         return slot;
1473 }
1474
1475 /* Tx lock BH disabled (SG version for TAH equipped EMACs) */
1476 static int emac_start_xmit_sg(struct sk_buff *skb, struct net_device *ndev)
1477 {
1478         struct emac_instance *dev = netdev_priv(ndev);
1479         int nr_frags = skb_shinfo(skb)->nr_frags;
1480         int len = skb->len, chunk;
1481         int slot, i;
1482         u16 ctrl;
1483         u32 pd;
1484
1485         /* This is common "fast" path */
1486         if (likely(!nr_frags && len <= MAL_MAX_TX_SIZE))
1487                 return emac_start_xmit(skb, ndev);
1488
1489         len -= skb->data_len;
1490
1491         /* Note, this is only an *estimation*, we can still run out of empty
1492          * slots because of the additional fragmentation into
1493          * MAL_MAX_TX_SIZE-sized chunks
1494          */
1495         if (unlikely(dev->tx_cnt + nr_frags + mal_tx_chunks(len) > NUM_TX_BUFF))
1496                 goto stop_queue;
1497
1498         ctrl = EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP | MAL_TX_CTRL_READY |
1499             emac_tx_csum(dev, skb);
1500         slot = dev->tx_slot;
1501
1502         /* skb data */
1503         dev->tx_skb[slot] = NULL;
1504         chunk = min(len, MAL_MAX_TX_SIZE);
1505         dev->tx_desc[slot].data_ptr = pd =
1506             dma_map_single(&dev->ofdev->dev, skb->data, len, DMA_TO_DEVICE);
1507         dev->tx_desc[slot].data_len = (u16) chunk;
1508         len -= chunk;
1509         if (unlikely(len))
1510                 slot = emac_xmit_split(dev, slot, pd + chunk, len, !nr_frags,
1511                                        ctrl);
1512         /* skb fragments */
1513         for (i = 0; i < nr_frags; ++i) {
1514                 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
1515                 len = skb_frag_size(frag);
1516
1517                 if (unlikely(dev->tx_cnt + mal_tx_chunks(len) >= NUM_TX_BUFF))
1518                         goto undo_frame;
1519
1520                 pd = skb_frag_dma_map(&dev->ofdev->dev, frag, 0, len,
1521                                       DMA_TO_DEVICE);
1522
1523                 slot = emac_xmit_split(dev, slot, pd, len, i == nr_frags - 1,
1524                                        ctrl);
1525         }
1526
1527         DBG2(dev, "xmit_sg(%u) %d - %d" NL, skb->len, dev->tx_slot, slot);
1528
1529         /* Attach skb to the last slot so we don't release it too early */
1530         dev->tx_skb[slot] = skb;
1531
1532         /* Send the packet out */
1533         if (dev->tx_slot == NUM_TX_BUFF - 1)
1534                 ctrl |= MAL_TX_CTRL_WRAP;
1535         wmb();
1536         dev->tx_desc[dev->tx_slot].ctrl = ctrl;
1537         dev->tx_slot = (slot + 1) % NUM_TX_BUFF;
1538
1539         return emac_xmit_finish(dev, skb->len);
1540
1541  undo_frame:
1542         /* Well, too bad. Our previous estimation was overly optimistic.
1543          * Undo everything.
1544          */
1545         while (slot != dev->tx_slot) {
1546                 dev->tx_desc[slot].ctrl = 0;
1547                 --dev->tx_cnt;
1548                 if (--slot < 0)
1549                         slot = NUM_TX_BUFF - 1;
1550         }
1551         ++dev->estats.tx_undo;
1552
1553  stop_queue:
1554         netif_stop_queue(ndev);
1555         DBG2(dev, "stopped TX queue" NL);
1556         return NETDEV_TX_BUSY;
1557 }
1558
1559 /* Tx lock BHs */
1560 static void emac_parse_tx_error(struct emac_instance *dev, u16 ctrl)
1561 {
1562         struct emac_error_stats *st = &dev->estats;
1563
1564         DBG(dev, "BD TX error %04x" NL, ctrl);
1565
1566         ++st->tx_bd_errors;
1567         if (ctrl & EMAC_TX_ST_BFCS)
1568                 ++st->tx_bd_bad_fcs;
1569         if (ctrl & EMAC_TX_ST_LCS)
1570                 ++st->tx_bd_carrier_loss;
1571         if (ctrl & EMAC_TX_ST_ED)
1572                 ++st->tx_bd_excessive_deferral;
1573         if (ctrl & EMAC_TX_ST_EC)
1574                 ++st->tx_bd_excessive_collisions;
1575         if (ctrl & EMAC_TX_ST_LC)
1576                 ++st->tx_bd_late_collision;
1577         if (ctrl & EMAC_TX_ST_MC)
1578                 ++st->tx_bd_multple_collisions;
1579         if (ctrl & EMAC_TX_ST_SC)
1580                 ++st->tx_bd_single_collision;
1581         if (ctrl & EMAC_TX_ST_UR)
1582                 ++st->tx_bd_underrun;
1583         if (ctrl & EMAC_TX_ST_SQE)
1584                 ++st->tx_bd_sqe;
1585 }
1586
1587 static void emac_poll_tx(void *param)
1588 {
1589         struct emac_instance *dev = param;
1590         u32 bad_mask;
1591
1592         DBG2(dev, "poll_tx, %d %d" NL, dev->tx_cnt, dev->ack_slot);
1593
1594         if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
1595                 bad_mask = EMAC_IS_BAD_TX_TAH;
1596         else
1597                 bad_mask = EMAC_IS_BAD_TX;
1598
1599         netif_tx_lock_bh(dev->ndev);
1600         if (dev->tx_cnt) {
1601                 u16 ctrl;
1602                 int slot = dev->ack_slot, n = 0;
1603         again:
1604                 ctrl = dev->tx_desc[slot].ctrl;
1605                 if (!(ctrl & MAL_TX_CTRL_READY)) {
1606                         struct sk_buff *skb = dev->tx_skb[slot];
1607                         ++n;
1608
1609                         if (skb) {
1610                                 dev_kfree_skb(skb);
1611                                 dev->tx_skb[slot] = NULL;
1612                         }
1613                         slot = (slot + 1) % NUM_TX_BUFF;
1614
1615                         if (unlikely(ctrl & bad_mask))
1616                                 emac_parse_tx_error(dev, ctrl);
1617
1618                         if (--dev->tx_cnt)
1619                                 goto again;
1620                 }
1621                 if (n) {
1622                         dev->ack_slot = slot;
1623                         if (netif_queue_stopped(dev->ndev) &&
1624                             dev->tx_cnt < EMAC_TX_WAKEUP_THRESH)
1625                                 netif_wake_queue(dev->ndev);
1626
1627                         DBG2(dev, "tx %d pkts" NL, n);
1628                 }
1629         }
1630         netif_tx_unlock_bh(dev->ndev);
1631 }
1632
1633 static inline void emac_recycle_rx_skb(struct emac_instance *dev, int slot,
1634                                        int len)
1635 {
1636         struct sk_buff *skb = dev->rx_skb[slot];
1637
1638         DBG2(dev, "recycle %d %d" NL, slot, len);
1639
1640         if (len)
1641                 dma_map_single(&dev->ofdev->dev, skb->data - 2,
1642                                EMAC_DMA_ALIGN(len + 2), DMA_FROM_DEVICE);
1643
1644         dev->rx_desc[slot].data_len = 0;
1645         wmb();
1646         dev->rx_desc[slot].ctrl = MAL_RX_CTRL_EMPTY |
1647             (slot == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
1648 }
1649
1650 static void emac_parse_rx_error(struct emac_instance *dev, u16 ctrl)
1651 {
1652         struct emac_error_stats *st = &dev->estats;
1653
1654         DBG(dev, "BD RX error %04x" NL, ctrl);
1655
1656         ++st->rx_bd_errors;
1657         if (ctrl & EMAC_RX_ST_OE)
1658                 ++st->rx_bd_overrun;
1659         if (ctrl & EMAC_RX_ST_BP)
1660                 ++st->rx_bd_bad_packet;
1661         if (ctrl & EMAC_RX_ST_RP)
1662                 ++st->rx_bd_runt_packet;
1663         if (ctrl & EMAC_RX_ST_SE)
1664                 ++st->rx_bd_short_event;
1665         if (ctrl & EMAC_RX_ST_AE)
1666                 ++st->rx_bd_alignment_error;
1667         if (ctrl & EMAC_RX_ST_BFCS)
1668                 ++st->rx_bd_bad_fcs;
1669         if (ctrl & EMAC_RX_ST_PTL)
1670                 ++st->rx_bd_packet_too_long;
1671         if (ctrl & EMAC_RX_ST_ORE)
1672                 ++st->rx_bd_out_of_range;
1673         if (ctrl & EMAC_RX_ST_IRE)
1674                 ++st->rx_bd_in_range;
1675 }
1676
1677 static inline void emac_rx_csum(struct emac_instance *dev,
1678                                 struct sk_buff *skb, u16 ctrl)
1679 {
1680 #ifdef CONFIG_IBM_EMAC_TAH
1681         if (!ctrl && dev->tah_dev) {
1682                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1683                 ++dev->stats.rx_packets_csum;
1684         }
1685 #endif
1686 }
1687
1688 static inline int emac_rx_sg_append(struct emac_instance *dev, int slot)
1689 {
1690         if (likely(dev->rx_sg_skb != NULL)) {
1691                 int len = dev->rx_desc[slot].data_len;
1692                 int tot_len = dev->rx_sg_skb->len + len;
1693
1694                 if (unlikely(tot_len + 2 > dev->rx_skb_size)) {
1695                         ++dev->estats.rx_dropped_mtu;
1696                         dev_kfree_skb(dev->rx_sg_skb);
1697                         dev->rx_sg_skb = NULL;
1698                 } else {
1699                         memcpy(skb_tail_pointer(dev->rx_sg_skb),
1700                                          dev->rx_skb[slot]->data, len);
1701                         skb_put(dev->rx_sg_skb, len);
1702                         emac_recycle_rx_skb(dev, slot, len);
1703                         return 0;
1704                 }
1705         }
1706         emac_recycle_rx_skb(dev, slot, 0);
1707         return -1;
1708 }
1709
1710 /* NAPI poll context */
1711 static int emac_poll_rx(void *param, int budget)
1712 {
1713         struct emac_instance *dev = param;
1714         int slot = dev->rx_slot, received = 0;
1715
1716         DBG2(dev, "poll_rx(%d)" NL, budget);
1717
1718  again:
1719         while (budget > 0) {
1720                 int len;
1721                 struct sk_buff *skb;
1722                 u16 ctrl = dev->rx_desc[slot].ctrl;
1723
1724                 if (ctrl & MAL_RX_CTRL_EMPTY)
1725                         break;
1726
1727                 skb = dev->rx_skb[slot];
1728                 mb();
1729                 len = dev->rx_desc[slot].data_len;
1730
1731                 if (unlikely(!MAL_IS_SINGLE_RX(ctrl)))
1732                         goto sg;
1733
1734                 ctrl &= EMAC_BAD_RX_MASK;
1735                 if (unlikely(ctrl && ctrl != EMAC_RX_TAH_BAD_CSUM)) {
1736                         emac_parse_rx_error(dev, ctrl);
1737                         ++dev->estats.rx_dropped_error;
1738                         emac_recycle_rx_skb(dev, slot, 0);
1739                         len = 0;
1740                         goto next;
1741                 }
1742
1743                 if (len < ETH_HLEN) {
1744                         ++dev->estats.rx_dropped_stack;
1745                         emac_recycle_rx_skb(dev, slot, len);
1746                         goto next;
1747                 }
1748
1749                 if (len && len < EMAC_RX_COPY_THRESH) {
1750                         struct sk_buff *copy_skb =
1751                             alloc_skb(len + EMAC_RX_SKB_HEADROOM + 2, GFP_ATOMIC);
1752                         if (unlikely(!copy_skb))
1753                                 goto oom;
1754
1755                         skb_reserve(copy_skb, EMAC_RX_SKB_HEADROOM + 2);
1756                         memcpy(copy_skb->data - 2, skb->data - 2, len + 2);
1757                         emac_recycle_rx_skb(dev, slot, len);
1758                         skb = copy_skb;
1759                 } else if (unlikely(emac_alloc_rx_skb(dev, slot, GFP_ATOMIC)))
1760                         goto oom;
1761
1762                 skb_put(skb, len);
1763         push_packet:
1764                 skb->protocol = eth_type_trans(skb, dev->ndev);
1765                 emac_rx_csum(dev, skb, ctrl);
1766
1767                 if (unlikely(netif_receive_skb(skb) == NET_RX_DROP))
1768                         ++dev->estats.rx_dropped_stack;
1769         next:
1770                 ++dev->stats.rx_packets;
1771         skip:
1772                 dev->stats.rx_bytes += len;
1773                 slot = (slot + 1) % NUM_RX_BUFF;
1774                 --budget;
1775                 ++received;
1776                 continue;
1777         sg:
1778                 if (ctrl & MAL_RX_CTRL_FIRST) {
1779                         BUG_ON(dev->rx_sg_skb);
1780                         if (unlikely(emac_alloc_rx_skb(dev, slot, GFP_ATOMIC))) {
1781                                 DBG(dev, "rx OOM %d" NL, slot);
1782                                 ++dev->estats.rx_dropped_oom;
1783                                 emac_recycle_rx_skb(dev, slot, 0);
1784                         } else {
1785                                 dev->rx_sg_skb = skb;
1786                                 skb_put(skb, len);
1787                         }
1788                 } else if (!emac_rx_sg_append(dev, slot) &&
1789                            (ctrl & MAL_RX_CTRL_LAST)) {
1790
1791                         skb = dev->rx_sg_skb;
1792                         dev->rx_sg_skb = NULL;
1793
1794                         ctrl &= EMAC_BAD_RX_MASK;
1795                         if (unlikely(ctrl && ctrl != EMAC_RX_TAH_BAD_CSUM)) {
1796                                 emac_parse_rx_error(dev, ctrl);
1797                                 ++dev->estats.rx_dropped_error;
1798                                 dev_kfree_skb(skb);
1799                                 len = 0;
1800                         } else
1801                                 goto push_packet;
1802                 }
1803                 goto skip;
1804         oom:
1805                 DBG(dev, "rx OOM %d" NL, slot);
1806                 /* Drop the packet and recycle skb */
1807                 ++dev->estats.rx_dropped_oom;
1808                 emac_recycle_rx_skb(dev, slot, 0);
1809                 goto next;
1810         }
1811
1812         if (received) {
1813                 DBG2(dev, "rx %d BDs" NL, received);
1814                 dev->rx_slot = slot;
1815         }
1816
1817         if (unlikely(budget && test_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags))) {
1818                 mb();
1819                 if (!(dev->rx_desc[slot].ctrl & MAL_RX_CTRL_EMPTY)) {
1820                         DBG2(dev, "rx restart" NL);
1821                         received = 0;
1822                         goto again;
1823                 }
1824
1825                 if (dev->rx_sg_skb) {
1826                         DBG2(dev, "dropping partial rx packet" NL);
1827                         ++dev->estats.rx_dropped_error;
1828                         dev_kfree_skb(dev->rx_sg_skb);
1829                         dev->rx_sg_skb = NULL;
1830                 }
1831
1832                 clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1833                 mal_enable_rx_channel(dev->mal, dev->mal_rx_chan);
1834                 emac_rx_enable(dev);
1835                 dev->rx_slot = 0;
1836         }
1837         return received;
1838 }
1839
1840 /* NAPI poll context */
1841 static int emac_peek_rx(void *param)
1842 {
1843         struct emac_instance *dev = param;
1844
1845         return !(dev->rx_desc[dev->rx_slot].ctrl & MAL_RX_CTRL_EMPTY);
1846 }
1847
1848 /* NAPI poll context */
1849 static int emac_peek_rx_sg(void *param)
1850 {
1851         struct emac_instance *dev = param;
1852
1853         int slot = dev->rx_slot;
1854         while (1) {
1855                 u16 ctrl = dev->rx_desc[slot].ctrl;
1856                 if (ctrl & MAL_RX_CTRL_EMPTY)
1857                         return 0;
1858                 else if (ctrl & MAL_RX_CTRL_LAST)
1859                         return 1;
1860
1861                 slot = (slot + 1) % NUM_RX_BUFF;
1862
1863                 /* I'm just being paranoid here :) */
1864                 if (unlikely(slot == dev->rx_slot))
1865                         return 0;
1866         }
1867 }
1868
1869 /* Hard IRQ */
1870 static void emac_rxde(void *param)
1871 {
1872         struct emac_instance *dev = param;
1873
1874         ++dev->estats.rx_stopped;
1875         emac_rx_disable_async(dev);
1876 }
1877
1878 /* Hard IRQ */
1879 static irqreturn_t emac_irq(int irq, void *dev_instance)
1880 {
1881         struct emac_instance *dev = dev_instance;
1882         struct emac_regs __iomem *p = dev->emacp;
1883         struct emac_error_stats *st = &dev->estats;
1884         u32 isr;
1885
1886         spin_lock(&dev->lock);
1887
1888         isr = in_be32(&p->isr);
1889         out_be32(&p->isr, isr);
1890
1891         DBG(dev, "isr = %08x" NL, isr);
1892
1893         if (isr & EMAC4_ISR_TXPE)
1894                 ++st->tx_parity;
1895         if (isr & EMAC4_ISR_RXPE)
1896                 ++st->rx_parity;
1897         if (isr & EMAC4_ISR_TXUE)
1898                 ++st->tx_underrun;
1899         if (isr & EMAC4_ISR_RXOE)
1900                 ++st->rx_fifo_overrun;
1901         if (isr & EMAC_ISR_OVR)
1902                 ++st->rx_overrun;
1903         if (isr & EMAC_ISR_BP)
1904                 ++st->rx_bad_packet;
1905         if (isr & EMAC_ISR_RP)
1906                 ++st->rx_runt_packet;
1907         if (isr & EMAC_ISR_SE)
1908                 ++st->rx_short_event;
1909         if (isr & EMAC_ISR_ALE)
1910                 ++st->rx_alignment_error;
1911         if (isr & EMAC_ISR_BFCS)
1912                 ++st->rx_bad_fcs;
1913         if (isr & EMAC_ISR_PTLE)
1914                 ++st->rx_packet_too_long;
1915         if (isr & EMAC_ISR_ORE)
1916                 ++st->rx_out_of_range;
1917         if (isr & EMAC_ISR_IRE)
1918                 ++st->rx_in_range;
1919         if (isr & EMAC_ISR_SQE)
1920                 ++st->tx_sqe;
1921         if (isr & EMAC_ISR_TE)
1922                 ++st->tx_errors;
1923
1924         spin_unlock(&dev->lock);
1925
1926         return IRQ_HANDLED;
1927 }
1928
1929 static struct net_device_stats *emac_stats(struct net_device *ndev)
1930 {
1931         struct emac_instance *dev = netdev_priv(ndev);
1932         struct emac_stats *st = &dev->stats;
1933         struct emac_error_stats *est = &dev->estats;
1934         struct net_device_stats *nst = &dev->nstats;
1935         unsigned long flags;
1936
1937         DBG2(dev, "stats" NL);
1938
1939         /* Compute "legacy" statistics */
1940         spin_lock_irqsave(&dev->lock, flags);
1941         nst->rx_packets = (unsigned long)st->rx_packets;
1942         nst->rx_bytes = (unsigned long)st->rx_bytes;
1943         nst->tx_packets = (unsigned long)st->tx_packets;
1944         nst->tx_bytes = (unsigned long)st->tx_bytes;
1945         nst->rx_dropped = (unsigned long)(est->rx_dropped_oom +
1946                                           est->rx_dropped_error +
1947                                           est->rx_dropped_resize +
1948                                           est->rx_dropped_mtu);
1949         nst->tx_dropped = (unsigned long)est->tx_dropped;
1950
1951         nst->rx_errors = (unsigned long)est->rx_bd_errors;
1952         nst->rx_fifo_errors = (unsigned long)(est->rx_bd_overrun +
1953                                               est->rx_fifo_overrun +
1954                                               est->rx_overrun);
1955         nst->rx_frame_errors = (unsigned long)(est->rx_bd_alignment_error +
1956                                                est->rx_alignment_error);
1957         nst->rx_crc_errors = (unsigned long)(est->rx_bd_bad_fcs +
1958                                              est->rx_bad_fcs);
1959         nst->rx_length_errors = (unsigned long)(est->rx_bd_runt_packet +
1960                                                 est->rx_bd_short_event +
1961                                                 est->rx_bd_packet_too_long +
1962                                                 est->rx_bd_out_of_range +
1963                                                 est->rx_bd_in_range +
1964                                                 est->rx_runt_packet +
1965                                                 est->rx_short_event +
1966                                                 est->rx_packet_too_long +
1967                                                 est->rx_out_of_range +
1968                                                 est->rx_in_range);
1969
1970         nst->tx_errors = (unsigned long)(est->tx_bd_errors + est->tx_errors);
1971         nst->tx_fifo_errors = (unsigned long)(est->tx_bd_underrun +
1972                                               est->tx_underrun);
1973         nst->tx_carrier_errors = (unsigned long)est->tx_bd_carrier_loss;
1974         nst->collisions = (unsigned long)(est->tx_bd_excessive_deferral +
1975                                           est->tx_bd_excessive_collisions +
1976                                           est->tx_bd_late_collision +
1977                                           est->tx_bd_multple_collisions);
1978         spin_unlock_irqrestore(&dev->lock, flags);
1979         return nst;
1980 }
1981
1982 static struct mal_commac_ops emac_commac_ops = {
1983         .poll_tx = &emac_poll_tx,
1984         .poll_rx = &emac_poll_rx,
1985         .peek_rx = &emac_peek_rx,
1986         .rxde = &emac_rxde,
1987 };
1988
1989 static struct mal_commac_ops emac_commac_sg_ops = {
1990         .poll_tx = &emac_poll_tx,
1991         .poll_rx = &emac_poll_rx,
1992         .peek_rx = &emac_peek_rx_sg,
1993         .rxde = &emac_rxde,
1994 };
1995
1996 /* Ethtool support */
1997 static int emac_ethtool_get_settings(struct net_device *ndev,
1998                                      struct ethtool_cmd *cmd)
1999 {
2000         struct emac_instance *dev = netdev_priv(ndev);
2001
2002         cmd->supported = dev->phy.features;
2003         cmd->port = PORT_MII;
2004         cmd->phy_address = dev->phy.address;
2005         cmd->transceiver =
2006             dev->phy.address >= 0 ? XCVR_EXTERNAL : XCVR_INTERNAL;
2007
2008         mutex_lock(&dev->link_lock);
2009         cmd->advertising = dev->phy.advertising;
2010         cmd->autoneg = dev->phy.autoneg;
2011         cmd->speed = dev->phy.speed;
2012         cmd->duplex = dev->phy.duplex;
2013         mutex_unlock(&dev->link_lock);
2014
2015         return 0;
2016 }
2017
2018 static int emac_ethtool_set_settings(struct net_device *ndev,
2019                                      struct ethtool_cmd *cmd)
2020 {
2021         struct emac_instance *dev = netdev_priv(ndev);
2022         u32 f = dev->phy.features;
2023
2024         DBG(dev, "set_settings(%d, %d, %d, 0x%08x)" NL,
2025             cmd->autoneg, cmd->speed, cmd->duplex, cmd->advertising);
2026
2027         /* Basic sanity checks */
2028         if (dev->phy.address < 0)
2029                 return -EOPNOTSUPP;
2030         if (cmd->autoneg != AUTONEG_ENABLE && cmd->autoneg != AUTONEG_DISABLE)
2031                 return -EINVAL;
2032         if (cmd->autoneg == AUTONEG_ENABLE && cmd->advertising == 0)
2033                 return -EINVAL;
2034         if (cmd->duplex != DUPLEX_HALF && cmd->duplex != DUPLEX_FULL)
2035                 return -EINVAL;
2036
2037         if (cmd->autoneg == AUTONEG_DISABLE) {
2038                 switch (cmd->speed) {
2039                 case SPEED_10:
2040                         if (cmd->duplex == DUPLEX_HALF &&
2041                             !(f & SUPPORTED_10baseT_Half))
2042                                 return -EINVAL;
2043                         if (cmd->duplex == DUPLEX_FULL &&
2044                             !(f & SUPPORTED_10baseT_Full))
2045                                 return -EINVAL;
2046                         break;
2047                 case SPEED_100:
2048                         if (cmd->duplex == DUPLEX_HALF &&
2049                             !(f & SUPPORTED_100baseT_Half))
2050                                 return -EINVAL;
2051                         if (cmd->duplex == DUPLEX_FULL &&
2052                             !(f & SUPPORTED_100baseT_Full))
2053                                 return -EINVAL;
2054                         break;
2055                 case SPEED_1000:
2056                         if (cmd->duplex == DUPLEX_HALF &&
2057                             !(f & SUPPORTED_1000baseT_Half))
2058                                 return -EINVAL;
2059                         if (cmd->duplex == DUPLEX_FULL &&
2060                             !(f & SUPPORTED_1000baseT_Full))
2061                                 return -EINVAL;
2062                         break;
2063                 default:
2064                         return -EINVAL;
2065                 }
2066
2067                 mutex_lock(&dev->link_lock);
2068                 dev->phy.def->ops->setup_forced(&dev->phy, cmd->speed,
2069                                                 cmd->duplex);
2070                 mutex_unlock(&dev->link_lock);
2071
2072         } else {
2073                 if (!(f & SUPPORTED_Autoneg))
2074                         return -EINVAL;
2075
2076                 mutex_lock(&dev->link_lock);
2077                 dev->phy.def->ops->setup_aneg(&dev->phy,
2078                                               (cmd->advertising & f) |
2079                                               (dev->phy.advertising &
2080                                                (ADVERTISED_Pause |
2081                                                 ADVERTISED_Asym_Pause)));
2082                 mutex_unlock(&dev->link_lock);
2083         }
2084         emac_force_link_update(dev);
2085
2086         return 0;
2087 }
2088
2089 static void emac_ethtool_get_ringparam(struct net_device *ndev,
2090                                        struct ethtool_ringparam *rp)
2091 {
2092         rp->rx_max_pending = rp->rx_pending = NUM_RX_BUFF;
2093         rp->tx_max_pending = rp->tx_pending = NUM_TX_BUFF;
2094 }
2095
2096 static void emac_ethtool_get_pauseparam(struct net_device *ndev,
2097                                         struct ethtool_pauseparam *pp)
2098 {
2099         struct emac_instance *dev = netdev_priv(ndev);
2100
2101         mutex_lock(&dev->link_lock);
2102         if ((dev->phy.features & SUPPORTED_Autoneg) &&
2103             (dev->phy.advertising & (ADVERTISED_Pause | ADVERTISED_Asym_Pause)))
2104                 pp->autoneg = 1;
2105
2106         if (dev->phy.duplex == DUPLEX_FULL) {
2107                 if (dev->phy.pause)
2108                         pp->rx_pause = pp->tx_pause = 1;
2109                 else if (dev->phy.asym_pause)
2110                         pp->tx_pause = 1;
2111         }
2112         mutex_unlock(&dev->link_lock);
2113 }
2114
2115 static int emac_get_regs_len(struct emac_instance *dev)
2116 {
2117                 return sizeof(struct emac_ethtool_regs_subhdr) +
2118                         sizeof(struct emac_regs);
2119 }
2120
2121 static int emac_ethtool_get_regs_len(struct net_device *ndev)
2122 {
2123         struct emac_instance *dev = netdev_priv(ndev);
2124         int size;
2125
2126         size = sizeof(struct emac_ethtool_regs_hdr) +
2127                 emac_get_regs_len(dev) + mal_get_regs_len(dev->mal);
2128         if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
2129                 size += zmii_get_regs_len(dev->zmii_dev);
2130         if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
2131                 size += rgmii_get_regs_len(dev->rgmii_dev);
2132         if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
2133                 size += tah_get_regs_len(dev->tah_dev);
2134
2135         return size;
2136 }
2137
2138 static void *emac_dump_regs(struct emac_instance *dev, void *buf)
2139 {
2140         struct emac_ethtool_regs_subhdr *hdr = buf;
2141
2142         hdr->index = dev->cell_index;
2143         if (emac_has_feature(dev, EMAC_FTR_EMAC4SYNC)) {
2144                 hdr->version = EMAC4SYNC_ETHTOOL_REGS_VER;
2145         } else if (emac_has_feature(dev, EMAC_FTR_EMAC4)) {
2146                 hdr->version = EMAC4_ETHTOOL_REGS_VER;
2147         } else {
2148                 hdr->version = EMAC_ETHTOOL_REGS_VER;
2149         }
2150         memcpy_fromio(hdr + 1, dev->emacp, sizeof(struct emac_regs));
2151         return (void *)(hdr + 1) + sizeof(struct emac_regs);
2152 }
2153
2154 static void emac_ethtool_get_regs(struct net_device *ndev,
2155                                   struct ethtool_regs *regs, void *buf)
2156 {
2157         struct emac_instance *dev = netdev_priv(ndev);
2158         struct emac_ethtool_regs_hdr *hdr = buf;
2159
2160         hdr->components = 0;
2161         buf = hdr + 1;
2162
2163         buf = mal_dump_regs(dev->mal, buf);
2164         buf = emac_dump_regs(dev, buf);
2165         if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) {
2166                 hdr->components |= EMAC_ETHTOOL_REGS_ZMII;
2167                 buf = zmii_dump_regs(dev->zmii_dev, buf);
2168         }
2169         if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) {
2170                 hdr->components |= EMAC_ETHTOOL_REGS_RGMII;
2171                 buf = rgmii_dump_regs(dev->rgmii_dev, buf);
2172         }
2173         if (emac_has_feature(dev, EMAC_FTR_HAS_TAH)) {
2174                 hdr->components |= EMAC_ETHTOOL_REGS_TAH;
2175                 buf = tah_dump_regs(dev->tah_dev, buf);
2176         }
2177 }
2178
2179 static int emac_ethtool_nway_reset(struct net_device *ndev)
2180 {
2181         struct emac_instance *dev = netdev_priv(ndev);
2182         int res = 0;
2183
2184         DBG(dev, "nway_reset" NL);
2185
2186         if (dev->phy.address < 0)
2187                 return -EOPNOTSUPP;
2188
2189         mutex_lock(&dev->link_lock);
2190         if (!dev->phy.autoneg) {
2191                 res = -EINVAL;
2192                 goto out;
2193         }
2194
2195         dev->phy.def->ops->setup_aneg(&dev->phy, dev->phy.advertising);
2196  out:
2197         mutex_unlock(&dev->link_lock);
2198         emac_force_link_update(dev);
2199         return res;
2200 }
2201
2202 static int emac_ethtool_get_sset_count(struct net_device *ndev, int stringset)
2203 {
2204         if (stringset == ETH_SS_STATS)
2205                 return EMAC_ETHTOOL_STATS_COUNT;
2206         else
2207                 return -EINVAL;
2208 }
2209
2210 static void emac_ethtool_get_strings(struct net_device *ndev, u32 stringset,
2211                                      u8 * buf)
2212 {
2213         if (stringset == ETH_SS_STATS)
2214                 memcpy(buf, &emac_stats_keys, sizeof(emac_stats_keys));
2215 }
2216
2217 static void emac_ethtool_get_ethtool_stats(struct net_device *ndev,
2218                                            struct ethtool_stats *estats,
2219                                            u64 * tmp_stats)
2220 {
2221         struct emac_instance *dev = netdev_priv(ndev);
2222
2223         memcpy(tmp_stats, &dev->stats, sizeof(dev->stats));
2224         tmp_stats += sizeof(dev->stats) / sizeof(u64);
2225         memcpy(tmp_stats, &dev->estats, sizeof(dev->estats));
2226 }
2227
2228 static void emac_ethtool_get_drvinfo(struct net_device *ndev,
2229                                      struct ethtool_drvinfo *info)
2230 {
2231         struct emac_instance *dev = netdev_priv(ndev);
2232
2233         strlcpy(info->driver, "ibm_emac", sizeof(info->driver));
2234         strlcpy(info->version, DRV_VERSION, sizeof(info->version));
2235         snprintf(info->bus_info, sizeof(info->bus_info), "PPC 4xx EMAC-%d %s",
2236                  dev->cell_index, dev->ofdev->dev.of_node->full_name);
2237 }
2238
2239 static const struct ethtool_ops emac_ethtool_ops = {
2240         .get_settings = emac_ethtool_get_settings,
2241         .set_settings = emac_ethtool_set_settings,
2242         .get_drvinfo = emac_ethtool_get_drvinfo,
2243
2244         .get_regs_len = emac_ethtool_get_regs_len,
2245         .get_regs = emac_ethtool_get_regs,
2246
2247         .nway_reset = emac_ethtool_nway_reset,
2248
2249         .get_ringparam = emac_ethtool_get_ringparam,
2250         .get_pauseparam = emac_ethtool_get_pauseparam,
2251
2252         .get_strings = emac_ethtool_get_strings,
2253         .get_sset_count = emac_ethtool_get_sset_count,
2254         .get_ethtool_stats = emac_ethtool_get_ethtool_stats,
2255
2256         .get_link = ethtool_op_get_link,
2257 };
2258
2259 static int emac_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2260 {
2261         struct emac_instance *dev = netdev_priv(ndev);
2262         struct mii_ioctl_data *data = if_mii(rq);
2263
2264         DBG(dev, "ioctl %08x" NL, cmd);
2265
2266         if (dev->phy.address < 0)
2267                 return -EOPNOTSUPP;
2268
2269         switch (cmd) {
2270         case SIOCGMIIPHY:
2271                 data->phy_id = dev->phy.address;
2272                 /* Fall through */
2273         case SIOCGMIIREG:
2274                 data->val_out = emac_mdio_read(ndev, dev->phy.address,
2275                                                data->reg_num);
2276                 return 0;
2277
2278         case SIOCSMIIREG:
2279                 emac_mdio_write(ndev, dev->phy.address, data->reg_num,
2280                                 data->val_in);
2281                 return 0;
2282         default:
2283                 return -EOPNOTSUPP;
2284         }
2285 }
2286
2287 struct emac_depentry {
2288         u32                     phandle;
2289         struct device_node      *node;
2290         struct platform_device  *ofdev;
2291         void                    *drvdata;
2292 };
2293
2294 #define EMAC_DEP_MAL_IDX        0
2295 #define EMAC_DEP_ZMII_IDX       1
2296 #define EMAC_DEP_RGMII_IDX      2
2297 #define EMAC_DEP_TAH_IDX        3
2298 #define EMAC_DEP_MDIO_IDX       4
2299 #define EMAC_DEP_PREV_IDX       5
2300 #define EMAC_DEP_COUNT          6
2301
2302 static int emac_check_deps(struct emac_instance *dev,
2303                            struct emac_depentry *deps)
2304 {
2305         int i, there = 0;
2306         struct device_node *np;
2307
2308         for (i = 0; i < EMAC_DEP_COUNT; i++) {
2309                 /* no dependency on that item, allright */
2310                 if (deps[i].phandle == 0) {
2311                         there++;
2312                         continue;
2313                 }
2314                 /* special case for blist as the dependency might go away */
2315                 if (i == EMAC_DEP_PREV_IDX) {
2316                         np = *(dev->blist - 1);
2317                         if (np == NULL) {
2318                                 deps[i].phandle = 0;
2319                                 there++;
2320                                 continue;
2321                         }
2322                         if (deps[i].node == NULL)
2323                                 deps[i].node = of_node_get(np);
2324                 }
2325                 if (deps[i].node == NULL)
2326                         deps[i].node = of_find_node_by_phandle(deps[i].phandle);
2327                 if (deps[i].node == NULL)
2328                         continue;
2329                 if (deps[i].ofdev == NULL)
2330                         deps[i].ofdev = of_find_device_by_node(deps[i].node);
2331                 if (deps[i].ofdev == NULL)
2332                         continue;
2333                 if (deps[i].drvdata == NULL)
2334                         deps[i].drvdata = platform_get_drvdata(deps[i].ofdev);
2335                 if (deps[i].drvdata != NULL)
2336                         there++;
2337         }
2338         return there == EMAC_DEP_COUNT;
2339 }
2340
2341 static void emac_put_deps(struct emac_instance *dev)
2342 {
2343         of_dev_put(dev->mal_dev);
2344         of_dev_put(dev->zmii_dev);
2345         of_dev_put(dev->rgmii_dev);
2346         of_dev_put(dev->mdio_dev);
2347         of_dev_put(dev->tah_dev);
2348 }
2349
2350 static int emac_of_bus_notify(struct notifier_block *nb, unsigned long action,
2351                               void *data)
2352 {
2353         /* We are only intereted in device addition */
2354         if (action == BUS_NOTIFY_BOUND_DRIVER)
2355                 wake_up_all(&emac_probe_wait);
2356         return 0;
2357 }
2358
2359 static struct notifier_block emac_of_bus_notifier = {
2360         .notifier_call = emac_of_bus_notify
2361 };
2362
2363 static int emac_wait_deps(struct emac_instance *dev)
2364 {
2365         struct emac_depentry deps[EMAC_DEP_COUNT];
2366         int i, err;
2367
2368         memset(&deps, 0, sizeof(deps));
2369
2370         deps[EMAC_DEP_MAL_IDX].phandle = dev->mal_ph;
2371         deps[EMAC_DEP_ZMII_IDX].phandle = dev->zmii_ph;
2372         deps[EMAC_DEP_RGMII_IDX].phandle = dev->rgmii_ph;
2373         if (dev->tah_ph)
2374                 deps[EMAC_DEP_TAH_IDX].phandle = dev->tah_ph;
2375         if (dev->mdio_ph)
2376                 deps[EMAC_DEP_MDIO_IDX].phandle = dev->mdio_ph;
2377         if (dev->blist && dev->blist > emac_boot_list)
2378                 deps[EMAC_DEP_PREV_IDX].phandle = 0xffffffffu;
2379         bus_register_notifier(&platform_bus_type, &emac_of_bus_notifier);
2380         wait_event_timeout(emac_probe_wait,
2381                            emac_check_deps(dev, deps),
2382                            EMAC_PROBE_DEP_TIMEOUT);
2383         bus_unregister_notifier(&platform_bus_type, &emac_of_bus_notifier);
2384         err = emac_check_deps(dev, deps) ? 0 : -ENODEV;
2385         for (i = 0; i < EMAC_DEP_COUNT; i++) {
2386                 of_node_put(deps[i].node);
2387                 if (err)
2388                         of_dev_put(deps[i].ofdev);
2389         }
2390         if (err == 0) {
2391                 dev->mal_dev = deps[EMAC_DEP_MAL_IDX].ofdev;
2392                 dev->zmii_dev = deps[EMAC_DEP_ZMII_IDX].ofdev;
2393                 dev->rgmii_dev = deps[EMAC_DEP_RGMII_IDX].ofdev;
2394                 dev->tah_dev = deps[EMAC_DEP_TAH_IDX].ofdev;
2395                 dev->mdio_dev = deps[EMAC_DEP_MDIO_IDX].ofdev;
2396         }
2397         of_dev_put(deps[EMAC_DEP_PREV_IDX].ofdev);
2398         return err;
2399 }
2400
2401 static int emac_read_uint_prop(struct device_node *np, const char *name,
2402                                u32 *val, int fatal)
2403 {
2404         int len;
2405         const u32 *prop = of_get_property(np, name, &len);
2406         if (prop == NULL || len < sizeof(u32)) {
2407                 if (fatal)
2408                         printk(KERN_ERR "%s: missing %s property\n",
2409                                np->full_name, name);
2410                 return -ENODEV;
2411         }
2412         *val = *prop;
2413         return 0;
2414 }
2415
2416 static int emac_init_phy(struct emac_instance *dev)
2417 {
2418         struct device_node *np = dev->ofdev->dev.of_node;
2419         struct net_device *ndev = dev->ndev;
2420         u32 phy_map, adv;
2421         int i;
2422
2423         dev->phy.dev = ndev;
2424         dev->phy.mode = dev->phy_mode;
2425
2426         /* PHY-less configuration.
2427          * XXX I probably should move these settings to the dev tree
2428          */
2429         if (dev->phy_address == 0xffffffff && dev->phy_map == 0xffffffff) {
2430                 emac_reset(dev);
2431
2432                 /* PHY-less configuration.
2433                  * XXX I probably should move these settings to the dev tree
2434                  */
2435                 dev->phy.address = -1;
2436                 dev->phy.features = SUPPORTED_MII;
2437                 if (emac_phy_supports_gige(dev->phy_mode))
2438                         dev->phy.features |= SUPPORTED_1000baseT_Full;
2439                 else
2440                         dev->phy.features |= SUPPORTED_100baseT_Full;
2441                 dev->phy.pause = 1;
2442
2443                 return 0;
2444         }
2445
2446         mutex_lock(&emac_phy_map_lock);
2447         phy_map = dev->phy_map | busy_phy_map;
2448
2449         DBG(dev, "PHY maps %08x %08x" NL, dev->phy_map, busy_phy_map);
2450
2451         dev->phy.mdio_read = emac_mdio_read;
2452         dev->phy.mdio_write = emac_mdio_write;
2453
2454         /* Enable internal clock source */
2455 #ifdef CONFIG_PPC_DCR_NATIVE
2456         if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX))
2457                 dcri_clrset(SDR0, SDR0_MFR, 0, SDR0_MFR_ECS);
2458 #endif
2459         /* PHY clock workaround */
2460         emac_rx_clk_tx(dev);
2461
2462         /* Enable internal clock source on 440GX*/
2463 #ifdef CONFIG_PPC_DCR_NATIVE
2464         if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX))
2465                 dcri_clrset(SDR0, SDR0_MFR, 0, SDR0_MFR_ECS);
2466 #endif
2467         /* Configure EMAC with defaults so we can at least use MDIO
2468          * This is needed mostly for 440GX
2469          */
2470         if (emac_phy_gpcs(dev->phy.mode)) {
2471                 /* XXX
2472                  * Make GPCS PHY address equal to EMAC index.
2473                  * We probably should take into account busy_phy_map
2474                  * and/or phy_map here.
2475                  *
2476                  * Note that the busy_phy_map is currently global
2477                  * while it should probably be per-ASIC...
2478                  */
2479                 dev->phy.gpcs_address = dev->gpcs_address;
2480                 if (dev->phy.gpcs_address == 0xffffffff)
2481                         dev->phy.address = dev->cell_index;
2482         }
2483
2484         emac_configure(dev);
2485
2486         if (dev->phy_address != 0xffffffff)
2487                 phy_map = ~(1 << dev->phy_address);
2488
2489         for (i = 0; i < 0x20; phy_map >>= 1, ++i)
2490                 if (!(phy_map & 1)) {
2491                         int r;
2492                         busy_phy_map |= 1 << i;
2493
2494                         /* Quick check if there is a PHY at the address */
2495                         r = emac_mdio_read(dev->ndev, i, MII_BMCR);
2496                         if (r == 0xffff || r < 0)
2497                                 continue;
2498                         if (!emac_mii_phy_probe(&dev->phy, i))
2499                                 break;
2500                 }
2501
2502         /* Enable external clock source */
2503 #ifdef CONFIG_PPC_DCR_NATIVE
2504         if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX))
2505                 dcri_clrset(SDR0, SDR0_MFR, SDR0_MFR_ECS, 0);
2506 #endif
2507         mutex_unlock(&emac_phy_map_lock);
2508         if (i == 0x20) {
2509                 printk(KERN_WARNING "%s: can't find PHY!\n", np->full_name);
2510                 return -ENXIO;
2511         }
2512
2513         /* Init PHY */
2514         if (dev->phy.def->ops->init)
2515                 dev->phy.def->ops->init(&dev->phy);
2516
2517         /* Disable any PHY features not supported by the platform */
2518         dev->phy.def->features &= ~dev->phy_feat_exc;
2519         dev->phy.features &= ~dev->phy_feat_exc;
2520
2521         /* Setup initial link parameters */
2522         if (dev->phy.features & SUPPORTED_Autoneg) {
2523                 adv = dev->phy.features;
2524                 if (!emac_has_feature(dev, EMAC_FTR_NO_FLOW_CONTROL_40x))
2525                         adv |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
2526                 /* Restart autonegotiation */
2527                 dev->phy.def->ops->setup_aneg(&dev->phy, adv);
2528         } else {
2529                 u32 f = dev->phy.def->features;
2530                 int speed = SPEED_10, fd = DUPLEX_HALF;
2531
2532                 /* Select highest supported speed/duplex */
2533                 if (f & SUPPORTED_1000baseT_Full) {
2534                         speed = SPEED_1000;
2535                         fd = DUPLEX_FULL;
2536                 } else if (f & SUPPORTED_1000baseT_Half)
2537                         speed = SPEED_1000;
2538                 else if (f & SUPPORTED_100baseT_Full) {
2539                         speed = SPEED_100;
2540                         fd = DUPLEX_FULL;
2541                 } else if (f & SUPPORTED_100baseT_Half)
2542                         speed = SPEED_100;
2543                 else if (f & SUPPORTED_10baseT_Full)
2544                         fd = DUPLEX_FULL;
2545
2546                 /* Force link parameters */
2547                 dev->phy.def->ops->setup_forced(&dev->phy, speed, fd);
2548         }
2549         return 0;
2550 }
2551
2552 static int emac_init_config(struct emac_instance *dev)
2553 {
2554         struct device_node *np = dev->ofdev->dev.of_node;
2555         const void *p;
2556
2557         /* Read config from device-tree */
2558         if (emac_read_uint_prop(np, "mal-device", &dev->mal_ph, 1))
2559                 return -ENXIO;
2560         if (emac_read_uint_prop(np, "mal-tx-channel", &dev->mal_tx_chan, 1))
2561                 return -ENXIO;
2562         if (emac_read_uint_prop(np, "mal-rx-channel", &dev->mal_rx_chan, 1))
2563                 return -ENXIO;
2564         if (emac_read_uint_prop(np, "cell-index", &dev->cell_index, 1))
2565                 return -ENXIO;
2566         if (emac_read_uint_prop(np, "max-frame-size", &dev->max_mtu, 0))
2567                 dev->max_mtu = 1500;
2568         if (emac_read_uint_prop(np, "rx-fifo-size", &dev->rx_fifo_size, 0))
2569                 dev->rx_fifo_size = 2048;
2570         if (emac_read_uint_prop(np, "tx-fifo-size", &dev->tx_fifo_size, 0))
2571                 dev->tx_fifo_size = 2048;
2572         if (emac_read_uint_prop(np, "rx-fifo-size-gige", &dev->rx_fifo_size_gige, 0))
2573                 dev->rx_fifo_size_gige = dev->rx_fifo_size;
2574         if (emac_read_uint_prop(np, "tx-fifo-size-gige", &dev->tx_fifo_size_gige, 0))
2575                 dev->tx_fifo_size_gige = dev->tx_fifo_size;
2576         if (emac_read_uint_prop(np, "phy-address", &dev->phy_address, 0))
2577                 dev->phy_address = 0xffffffff;
2578         if (emac_read_uint_prop(np, "phy-map", &dev->phy_map, 0))
2579                 dev->phy_map = 0xffffffff;
2580         if (emac_read_uint_prop(np, "gpcs-address", &dev->gpcs_address, 0))
2581                 dev->gpcs_address = 0xffffffff;
2582         if (emac_read_uint_prop(np->parent, "clock-frequency", &dev->opb_bus_freq, 1))
2583                 return -ENXIO;
2584         if (emac_read_uint_prop(np, "tah-device", &dev->tah_ph, 0))
2585                 dev->tah_ph = 0;
2586         if (emac_read_uint_prop(np, "tah-channel", &dev->tah_port, 0))
2587                 dev->tah_port = 0;
2588         if (emac_read_uint_prop(np, "mdio-device", &dev->mdio_ph, 0))
2589                 dev->mdio_ph = 0;
2590         if (emac_read_uint_prop(np, "zmii-device", &dev->zmii_ph, 0))
2591                 dev->zmii_ph = 0;
2592         if (emac_read_uint_prop(np, "zmii-channel", &dev->zmii_port, 0))
2593                 dev->zmii_port = 0xffffffff;
2594         if (emac_read_uint_prop(np, "rgmii-device", &dev->rgmii_ph, 0))
2595                 dev->rgmii_ph = 0;
2596         if (emac_read_uint_prop(np, "rgmii-channel", &dev->rgmii_port, 0))
2597                 dev->rgmii_port = 0xffffffff;
2598         if (emac_read_uint_prop(np, "fifo-entry-size", &dev->fifo_entry_size, 0))
2599                 dev->fifo_entry_size = 16;
2600         if (emac_read_uint_prop(np, "mal-burst-size", &dev->mal_burst_size, 0))
2601                 dev->mal_burst_size = 256;
2602
2603         /* PHY mode needs some decoding */
2604         dev->phy_mode = of_get_phy_mode(np);
2605         if (dev->phy_mode < 0)
2606                 dev->phy_mode = PHY_MODE_NA;
2607
2608         /* Check EMAC version */
2609         if (of_device_is_compatible(np, "ibm,emac4sync")) {
2610                 dev->features |= (EMAC_FTR_EMAC4 | EMAC_FTR_EMAC4SYNC);
2611                 if (of_device_is_compatible(np, "ibm,emac-460ex") ||
2612                     of_device_is_compatible(np, "ibm,emac-460gt"))
2613                         dev->features |= EMAC_FTR_460EX_PHY_CLK_FIX;
2614                 if (of_device_is_compatible(np, "ibm,emac-405ex") ||
2615                     of_device_is_compatible(np, "ibm,emac-405exr"))
2616                         dev->features |= EMAC_FTR_440EP_PHY_CLK_FIX;
2617                 if (of_device_is_compatible(np, "ibm,emac-apm821xx")) {
2618                         dev->features |= (EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE |
2619                                           EMAC_FTR_APM821XX_NO_HALF_DUPLEX |
2620                                           EMAC_FTR_460EX_PHY_CLK_FIX);
2621                 }
2622         } else if (of_device_is_compatible(np, "ibm,emac4")) {
2623                 dev->features |= EMAC_FTR_EMAC4;
2624                 if (of_device_is_compatible(np, "ibm,emac-440gx"))
2625                         dev->features |= EMAC_FTR_440GX_PHY_CLK_FIX;
2626         } else {
2627                 if (of_device_is_compatible(np, "ibm,emac-440ep") ||
2628                     of_device_is_compatible(np, "ibm,emac-440gr"))
2629                         dev->features |= EMAC_FTR_440EP_PHY_CLK_FIX;
2630                 if (of_device_is_compatible(np, "ibm,emac-405ez")) {
2631 #ifdef CONFIG_IBM_EMAC_NO_FLOW_CTRL
2632                         dev->features |= EMAC_FTR_NO_FLOW_CONTROL_40x;
2633 #else
2634                         printk(KERN_ERR "%s: Flow control not disabled!\n",
2635                                         np->full_name);
2636                         return -ENXIO;
2637 #endif
2638                 }
2639
2640         }
2641
2642         /* Fixup some feature bits based on the device tree */
2643         if (of_get_property(np, "has-inverted-stacr-oc", NULL))
2644                 dev->features |= EMAC_FTR_STACR_OC_INVERT;
2645         if (of_get_property(np, "has-new-stacr-staopc", NULL))
2646                 dev->features |= EMAC_FTR_HAS_NEW_STACR;
2647
2648         /* CAB lacks the appropriate properties */
2649         if (of_device_is_compatible(np, "ibm,emac-axon"))
2650                 dev->features |= EMAC_FTR_HAS_NEW_STACR |
2651                         EMAC_FTR_STACR_OC_INVERT;
2652
2653         /* Enable TAH/ZMII/RGMII features as found */
2654         if (dev->tah_ph != 0) {
2655 #ifdef CONFIG_IBM_EMAC_TAH
2656                 dev->features |= EMAC_FTR_HAS_TAH;
2657 #else
2658                 printk(KERN_ERR "%s: TAH support not enabled !\n",
2659                        np->full_name);
2660                 return -ENXIO;
2661 #endif
2662         }
2663
2664         if (dev->zmii_ph != 0) {
2665 #ifdef CONFIG_IBM_EMAC_ZMII
2666                 dev->features |= EMAC_FTR_HAS_ZMII;
2667 #else
2668                 printk(KERN_ERR "%s: ZMII support not enabled !\n",
2669                        np->full_name);
2670                 return -ENXIO;
2671 #endif
2672         }
2673
2674         if (dev->rgmii_ph != 0) {
2675 #ifdef CONFIG_IBM_EMAC_RGMII
2676                 dev->features |= EMAC_FTR_HAS_RGMII;
2677 #else
2678                 printk(KERN_ERR "%s: RGMII support not enabled !\n",
2679                        np->full_name);
2680                 return -ENXIO;
2681 #endif
2682         }
2683
2684         /* Read MAC-address */
2685         p = of_get_property(np, "local-mac-address", NULL);
2686         if (p == NULL) {
2687                 printk(KERN_ERR "%s: Can't find local-mac-address property\n",
2688                        np->full_name);
2689                 return -ENXIO;
2690         }
2691         memcpy(dev->ndev->dev_addr, p, ETH_ALEN);
2692
2693         /* IAHT and GAHT filter parameterization */
2694         if (emac_has_feature(dev, EMAC_FTR_EMAC4SYNC)) {
2695                 dev->xaht_slots_shift = EMAC4SYNC_XAHT_SLOTS_SHIFT;
2696                 dev->xaht_width_shift = EMAC4SYNC_XAHT_WIDTH_SHIFT;
2697         } else {
2698                 dev->xaht_slots_shift = EMAC4_XAHT_SLOTS_SHIFT;
2699                 dev->xaht_width_shift = EMAC4_XAHT_WIDTH_SHIFT;
2700         }
2701
2702         DBG(dev, "features     : 0x%08x / 0x%08x\n", dev->features, EMAC_FTRS_POSSIBLE);
2703         DBG(dev, "tx_fifo_size : %d (%d gige)\n", dev->tx_fifo_size, dev->tx_fifo_size_gige);
2704         DBG(dev, "rx_fifo_size : %d (%d gige)\n", dev->rx_fifo_size, dev->rx_fifo_size_gige);
2705         DBG(dev, "max_mtu      : %d\n", dev->max_mtu);
2706         DBG(dev, "OPB freq     : %d\n", dev->opb_bus_freq);
2707
2708         return 0;
2709 }
2710
2711 static const struct net_device_ops emac_netdev_ops = {
2712         .ndo_open               = emac_open,
2713         .ndo_stop               = emac_close,
2714         .ndo_get_stats          = emac_stats,
2715         .ndo_set_rx_mode        = emac_set_multicast_list,
2716         .ndo_do_ioctl           = emac_ioctl,
2717         .ndo_tx_timeout         = emac_tx_timeout,
2718         .ndo_validate_addr      = eth_validate_addr,
2719         .ndo_set_mac_address    = emac_set_mac_address,
2720         .ndo_start_xmit         = emac_start_xmit,
2721         .ndo_change_mtu         = eth_change_mtu,
2722 };
2723
2724 static const struct net_device_ops emac_gige_netdev_ops = {
2725         .ndo_open               = emac_open,
2726         .ndo_stop               = emac_close,
2727         .ndo_get_stats          = emac_stats,
2728         .ndo_set_rx_mode        = emac_set_multicast_list,
2729         .ndo_do_ioctl           = emac_ioctl,
2730         .ndo_tx_timeout         = emac_tx_timeout,
2731         .ndo_validate_addr      = eth_validate_addr,
2732         .ndo_set_mac_address    = emac_set_mac_address,
2733         .ndo_start_xmit         = emac_start_xmit_sg,
2734         .ndo_change_mtu         = emac_change_mtu,
2735 };
2736
2737 static int emac_probe(struct platform_device *ofdev)
2738 {
2739         struct net_device *ndev;
2740         struct emac_instance *dev;
2741         struct device_node *np = ofdev->dev.of_node;
2742         struct device_node **blist = NULL;
2743         int err, i;
2744
2745         /* Skip unused/unwired EMACS.  We leave the check for an unused
2746          * property here for now, but new flat device trees should set a
2747          * status property to "disabled" instead.
2748          */
2749         if (of_get_property(np, "unused", NULL) || !of_device_is_available(np))
2750                 return -ENODEV;
2751
2752         /* Find ourselves in the bootlist if we are there */
2753         for (i = 0; i < EMAC_BOOT_LIST_SIZE; i++)
2754                 if (emac_boot_list[i] == np)
2755                         blist = &emac_boot_list[i];
2756
2757         /* Allocate our net_device structure */
2758         err = -ENOMEM;
2759         ndev = alloc_etherdev(sizeof(struct emac_instance));
2760         if (!ndev)
2761                 goto err_gone;
2762
2763         dev = netdev_priv(ndev);
2764         dev->ndev = ndev;
2765         dev->ofdev = ofdev;
2766         dev->blist = blist;
2767         SET_NETDEV_DEV(ndev, &ofdev->dev);
2768
2769         /* Initialize some embedded data structures */
2770         mutex_init(&dev->mdio_lock);
2771         mutex_init(&dev->link_lock);
2772         spin_lock_init(&dev->lock);
2773         INIT_WORK(&dev->reset_work, emac_reset_work);
2774
2775         /* Init various config data based on device-tree */
2776         err = emac_init_config(dev);
2777         if (err != 0)
2778                 goto err_free;
2779
2780         /* Get interrupts. EMAC irq is mandatory, WOL irq is optional */
2781         dev->emac_irq = irq_of_parse_and_map(np, 0);
2782         dev->wol_irq = irq_of_parse_and_map(np, 1);
2783         if (!dev->emac_irq) {
2784                 printk(KERN_ERR "%s: Can't map main interrupt\n", np->full_name);
2785                 goto err_free;
2786         }
2787         ndev->irq = dev->emac_irq;
2788
2789         /* Map EMAC regs */
2790         if (of_address_to_resource(np, 0, &dev->rsrc_regs)) {
2791                 printk(KERN_ERR "%s: Can't get registers address\n",
2792                        np->full_name);
2793                 goto err_irq_unmap;
2794         }
2795         // TODO : request_mem_region
2796         dev->emacp = ioremap(dev->rsrc_regs.start,
2797                              resource_size(&dev->rsrc_regs));
2798         if (dev->emacp == NULL) {
2799                 printk(KERN_ERR "%s: Can't map device registers!\n",
2800                        np->full_name);
2801                 err = -ENOMEM;
2802                 goto err_irq_unmap;
2803         }
2804
2805         /* Wait for dependent devices */
2806         err = emac_wait_deps(dev);
2807         if (err) {
2808                 printk(KERN_ERR
2809                        "%s: Timeout waiting for dependent devices\n",
2810                        np->full_name);
2811                 /*  display more info about what's missing ? */
2812                 goto err_reg_unmap;
2813         }
2814         dev->mal = platform_get_drvdata(dev->mal_dev);
2815         if (dev->mdio_dev != NULL)
2816                 dev->mdio_instance = platform_get_drvdata(dev->mdio_dev);
2817
2818         /* Register with MAL */
2819         dev->commac.ops = &emac_commac_ops;
2820         dev->commac.dev = dev;
2821         dev->commac.tx_chan_mask = MAL_CHAN_MASK(dev->mal_tx_chan);
2822         dev->commac.rx_chan_mask = MAL_CHAN_MASK(dev->mal_rx_chan);
2823         err = mal_register_commac(dev->mal, &dev->commac);
2824         if (err) {
2825                 printk(KERN_ERR "%s: failed to register with mal %s!\n",
2826                        np->full_name, dev->mal_dev->dev.of_node->full_name);
2827                 goto err_rel_deps;
2828         }
2829         dev->rx_skb_size = emac_rx_skb_size(ndev->mtu);
2830         dev->rx_sync_size = emac_rx_sync_size(ndev->mtu);
2831
2832         /* Get pointers to BD rings */
2833         dev->tx_desc =
2834             dev->mal->bd_virt + mal_tx_bd_offset(dev->mal, dev->mal_tx_chan);
2835         dev->rx_desc =
2836             dev->mal->bd_virt + mal_rx_bd_offset(dev->mal, dev->mal_rx_chan);
2837
2838         DBG(dev, "tx_desc %p" NL, dev->tx_desc);
2839         DBG(dev, "rx_desc %p" NL, dev->rx_desc);
2840
2841         /* Clean rings */
2842         memset(dev->tx_desc, 0, NUM_TX_BUFF * sizeof(struct mal_descriptor));
2843         memset(dev->rx_desc, 0, NUM_RX_BUFF * sizeof(struct mal_descriptor));
2844         memset(dev->tx_skb, 0, NUM_TX_BUFF * sizeof(struct sk_buff *));
2845         memset(dev->rx_skb, 0, NUM_RX_BUFF * sizeof(struct sk_buff *));
2846
2847         /* Attach to ZMII, if needed */
2848         if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII) &&
2849             (err = zmii_attach(dev->zmii_dev, dev->zmii_port, &dev->phy_mode)) != 0)
2850                 goto err_unreg_commac;
2851
2852         /* Attach to RGMII, if needed */
2853         if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII) &&
2854             (err = rgmii_attach(dev->rgmii_dev, dev->rgmii_port, dev->phy_mode)) != 0)
2855                 goto err_detach_zmii;
2856
2857         /* Attach to TAH, if needed */
2858         if (emac_has_feature(dev, EMAC_FTR_HAS_TAH) &&
2859             (err = tah_attach(dev->tah_dev, dev->tah_port)) != 0)
2860                 goto err_detach_rgmii;
2861
2862         /* Set some link defaults before we can find out real parameters */
2863         dev->phy.speed = SPEED_100;
2864         dev->phy.duplex = DUPLEX_FULL;
2865         dev->phy.autoneg = AUTONEG_DISABLE;
2866         dev->phy.pause = dev->phy.asym_pause = 0;
2867         dev->stop_timeout = STOP_TIMEOUT_100;
2868         INIT_DELAYED_WORK(&dev->link_work, emac_link_timer);
2869
2870         /* Some SoCs like APM821xx does not support Half Duplex mode. */
2871         if (emac_has_feature(dev, EMAC_FTR_APM821XX_NO_HALF_DUPLEX)) {
2872                 dev->phy_feat_exc = (SUPPORTED_1000baseT_Half |
2873                                      SUPPORTED_100baseT_Half |
2874                                      SUPPORTED_10baseT_Half);
2875         }
2876
2877         /* Find PHY if any */
2878         err = emac_init_phy(dev);
2879         if (err != 0)
2880                 goto err_detach_tah;
2881
2882         if (dev->tah_dev) {
2883                 ndev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG;
2884                 ndev->features |= ndev->hw_features | NETIF_F_RXCSUM;
2885         }
2886         ndev->watchdog_timeo = 5 * HZ;
2887         if (emac_phy_supports_gige(dev->phy_mode)) {
2888                 ndev->netdev_ops = &emac_gige_netdev_ops;
2889                 dev->commac.ops = &emac_commac_sg_ops;
2890         } else
2891                 ndev->netdev_ops = &emac_netdev_ops;
2892         ndev->ethtool_ops = &emac_ethtool_ops;
2893
2894         netif_carrier_off(ndev);
2895
2896         err = register_netdev(ndev);
2897         if (err) {
2898                 printk(KERN_ERR "%s: failed to register net device (%d)!\n",
2899                        np->full_name, err);
2900                 goto err_detach_tah;
2901         }
2902
2903         /* Set our drvdata last as we don't want them visible until we are
2904          * fully initialized
2905          */
2906         wmb();
2907         platform_set_drvdata(ofdev, dev);
2908
2909         /* There's a new kid in town ! Let's tell everybody */
2910         wake_up_all(&emac_probe_wait);
2911
2912
2913         printk(KERN_INFO "%s: EMAC-%d %s, MAC %pM\n",
2914                ndev->name, dev->cell_index, np->full_name, ndev->dev_addr);
2915
2916         if (dev->phy_mode == PHY_MODE_SGMII)
2917                 printk(KERN_NOTICE "%s: in SGMII mode\n", ndev->name);
2918
2919         if (dev->phy.address >= 0)
2920                 printk("%s: found %s PHY (0x%02x)\n", ndev->name,
2921                        dev->phy.def->name, dev->phy.address);
2922
2923         emac_dbg_register(dev);
2924
2925         /* Life is good */
2926         return 0;
2927
2928         /* I have a bad feeling about this ... */
2929
2930  err_detach_tah:
2931         if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
2932                 tah_detach(dev->tah_dev, dev->tah_port);
2933  err_detach_rgmii:
2934         if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
2935                 rgmii_detach(dev->rgmii_dev, dev->rgmii_port);
2936  err_detach_zmii:
2937         if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
2938                 zmii_detach(dev->zmii_dev, dev->zmii_port);
2939  err_unreg_commac:
2940         mal_unregister_commac(dev->mal, &dev->commac);
2941  err_rel_deps:
2942         emac_put_deps(dev);
2943  err_reg_unmap:
2944         iounmap(dev->emacp);
2945  err_irq_unmap:
2946         if (dev->wol_irq)
2947                 irq_dispose_mapping(dev->wol_irq);
2948         if (dev->emac_irq)
2949                 irq_dispose_mapping(dev->emac_irq);
2950  err_free:
2951         free_netdev(ndev);
2952  err_gone:
2953         /* if we were on the bootlist, remove us as we won't show up and
2954          * wake up all waiters to notify them in case they were waiting
2955          * on us
2956          */
2957         if (blist) {
2958                 *blist = NULL;
2959                 wake_up_all(&emac_probe_wait);
2960         }
2961         return err;
2962 }
2963
2964 static int emac_remove(struct platform_device *ofdev)
2965 {
2966         struct emac_instance *dev = platform_get_drvdata(ofdev);
2967
2968         DBG(dev, "remove" NL);
2969
2970         unregister_netdev(dev->ndev);
2971
2972         cancel_work_sync(&dev->reset_work);
2973
2974         if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
2975                 tah_detach(dev->tah_dev, dev->tah_port);
2976         if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
2977                 rgmii_detach(dev->rgmii_dev, dev->rgmii_port);
2978         if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
2979                 zmii_detach(dev->zmii_dev, dev->zmii_port);
2980
2981         busy_phy_map &= ~(1 << dev->phy.address);
2982         DBG(dev, "busy_phy_map now %#x" NL, busy_phy_map);
2983
2984         mal_unregister_commac(dev->mal, &dev->commac);
2985         emac_put_deps(dev);
2986
2987         emac_dbg_unregister(dev);
2988         iounmap(dev->emacp);
2989
2990         if (dev->wol_irq)
2991                 irq_dispose_mapping(dev->wol_irq);
2992         if (dev->emac_irq)
2993                 irq_dispose_mapping(dev->emac_irq);
2994
2995         free_netdev(dev->ndev);
2996
2997         return 0;
2998 }
2999
3000 /* XXX Features in here should be replaced by properties... */
3001 static const struct of_device_id emac_match[] =
3002 {
3003         {
3004                 .type           = "network",
3005                 .compatible     = "ibm,emac",
3006         },
3007         {
3008                 .type           = "network",
3009                 .compatible     = "ibm,emac4",
3010         },
3011         {
3012                 .type           = "network",
3013                 .compatible     = "ibm,emac4sync",
3014         },
3015         {},
3016 };
3017 MODULE_DEVICE_TABLE(of, emac_match);
3018
3019 static struct platform_driver emac_driver = {
3020         .driver = {
3021                 .name = "emac",
3022                 .of_match_table = emac_match,
3023         },
3024         .probe = emac_probe,
3025         .remove = emac_remove,
3026 };
3027
3028 static void __init emac_make_bootlist(void)
3029 {
3030         struct device_node *np = NULL;
3031         int j, max, i = 0;
3032         int cell_indices[EMAC_BOOT_LIST_SIZE];
3033
3034         /* Collect EMACs */
3035         while((np = of_find_all_nodes(np)) != NULL) {
3036                 const u32 *idx;
3037
3038                 if (of_match_node(emac_match, np) == NULL)
3039                         continue;
3040                 if (of_get_property(np, "unused", NULL))
3041                         continue;
3042                 idx = of_get_property(np, "cell-index", NULL);
3043                 if (idx == NULL)
3044                         continue;
3045                 cell_indices[i] = *idx;
3046                 emac_boot_list[i++] = of_node_get(np);
3047                 if (i >= EMAC_BOOT_LIST_SIZE) {
3048                         of_node_put(np);
3049                         break;
3050                 }
3051         }
3052         max = i;
3053
3054         /* Bubble sort them (doh, what a creative algorithm :-) */
3055         for (i = 0; max > 1 && (i < (max - 1)); i++)
3056                 for (j = i; j < max; j++) {
3057                         if (cell_indices[i] > cell_indices[j]) {
3058                                 swap(emac_boot_list[i], emac_boot_list[j]);
3059                                 swap(cell_indices[i], cell_indices[j]);
3060                         }
3061                 }
3062 }
3063
3064 static int __init emac_init(void)
3065 {
3066         int rc;
3067
3068         printk(KERN_INFO DRV_DESC ", version " DRV_VERSION "\n");
3069
3070         /* Init debug stuff */
3071         emac_init_debug();
3072
3073         /* Build EMAC boot list */
3074         emac_make_bootlist();
3075
3076         /* Init submodules */
3077         rc = mal_init();
3078         if (rc)
3079                 goto err;
3080         rc = zmii_init();
3081         if (rc)
3082                 goto err_mal;
3083         rc = rgmii_init();
3084         if (rc)
3085                 goto err_zmii;
3086         rc = tah_init();
3087         if (rc)
3088                 goto err_rgmii;
3089         rc = platform_driver_register(&emac_driver);
3090         if (rc)
3091                 goto err_tah;
3092
3093         return 0;
3094
3095  err_tah:
3096         tah_exit();
3097  err_rgmii:
3098         rgmii_exit();
3099  err_zmii:
3100         zmii_exit();
3101  err_mal:
3102         mal_exit();
3103  err:
3104         return rc;
3105 }
3106
3107 static void __exit emac_exit(void)
3108 {
3109         int i;
3110
3111         platform_driver_unregister(&emac_driver);
3112
3113         tah_exit();
3114         rgmii_exit();
3115         zmii_exit();
3116         mal_exit();
3117         emac_fini_debug();
3118
3119         /* Destroy EMAC boot list */
3120         for (i = 0; i < EMAC_BOOT_LIST_SIZE; i++)
3121                 of_node_put(emac_boot_list[i]);
3122 }
3123
3124 module_init(emac_init);
3125 module_exit(emac_exit);