1 /*******************************************************************************
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2015 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 ******************************************************************************/
30 #include "i40e_status.h"
31 #include "i40e_osdep.h"
32 #include "i40e_register.h"
33 #include "i40e_adminq.h"
35 #include "i40e_lan_hmc.h"
38 #define I40E_DEV_ID_SFP_XL710 0x1572
39 #define I40E_DEV_ID_QEMU 0x1574
40 #define I40E_DEV_ID_KX_A 0x157F
41 #define I40E_DEV_ID_KX_B 0x1580
42 #define I40E_DEV_ID_KX_C 0x1581
43 #define I40E_DEV_ID_QSFP_A 0x1583
44 #define I40E_DEV_ID_QSFP_B 0x1584
45 #define I40E_DEV_ID_QSFP_C 0x1585
46 #define I40E_DEV_ID_10G_BASE_T 0x1586
47 #define I40E_DEV_ID_20G_KR2 0x1587
48 #define I40E_DEV_ID_VF 0x154C
49 #define I40E_DEV_ID_VF_HV 0x1571
50 #define I40E_DEV_ID_SFP_X722 0x37D0
51 #define I40E_DEV_ID_1G_BASE_T_X722 0x37D1
52 #define I40E_DEV_ID_10G_BASE_T_X722 0x37D2
53 #define I40E_DEV_ID_X722_VF 0x37CD
54 #define I40E_DEV_ID_X722_VF_HV 0x37D9
56 #define i40e_is_40G_device(d) ((d) == I40E_DEV_ID_QSFP_A || \
57 (d) == I40E_DEV_ID_QSFP_B || \
58 (d) == I40E_DEV_ID_QSFP_C)
60 /* I40E_MASK is a macro used on 32 bit registers */
61 #define I40E_MASK(mask, shift) (mask << shift)
63 #define I40E_MAX_VSI_QP 16
64 #define I40E_MAX_VF_VSI 3
65 #define I40E_MAX_CHAINED_RX_BUFFERS 5
66 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
68 /* Max default timeout in ms, */
69 #define I40E_MAX_NVM_TIMEOUT 18000
71 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
72 #define I40E_MS_TO_GTIME(time) ((time) * 1000)
74 /* forward declaration */
76 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
78 /* Data type manipulation macros. */
80 #define I40E_DESC_UNUSED(R) \
81 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
82 (R)->next_to_clean - (R)->next_to_use - 1)
84 /* bitfields for Tx queue mapping in QTX_CTL */
85 #define I40E_QTX_CTL_VF_QUEUE 0x0
86 #define I40E_QTX_CTL_VM_QUEUE 0x1
87 #define I40E_QTX_CTL_PF_QUEUE 0x2
89 /* debug masks - set these bits in hw->debug_mask to control output */
90 enum i40e_debug_mask {
91 I40E_DEBUG_INIT = 0x00000001,
92 I40E_DEBUG_RELEASE = 0x00000002,
94 I40E_DEBUG_LINK = 0x00000010,
95 I40E_DEBUG_PHY = 0x00000020,
96 I40E_DEBUG_HMC = 0x00000040,
97 I40E_DEBUG_NVM = 0x00000080,
98 I40E_DEBUG_LAN = 0x00000100,
99 I40E_DEBUG_FLOW = 0x00000200,
100 I40E_DEBUG_DCB = 0x00000400,
101 I40E_DEBUG_DIAG = 0x00000800,
102 I40E_DEBUG_FD = 0x00001000,
104 I40E_DEBUG_AQ_MESSAGE = 0x01000000,
105 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
106 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
107 I40E_DEBUG_AQ_COMMAND = 0x06000000,
108 I40E_DEBUG_AQ = 0x0F000000,
110 I40E_DEBUG_USER = 0xF0000000,
112 I40E_DEBUG_ALL = 0xFFFFFFFF
115 /* These are structs for managing the hardware information and the operations.
116 * The structures of function pointers are filled out at init time when we
117 * know for sure exactly which hardware we're working with. This gives us the
118 * flexibility of using the same main driver code but adapting to slightly
119 * different hardware needs as new parts are developed. For this architecture,
120 * the Firmware and AdminQ are intended to insulate the driver from most of the
121 * future changes, but these structures will also do part of the job.
124 I40E_MAC_UNKNOWN = 0,
133 enum i40e_media_type {
134 I40E_MEDIA_TYPE_UNKNOWN = 0,
135 I40E_MEDIA_TYPE_FIBER,
136 I40E_MEDIA_TYPE_BASET,
137 I40E_MEDIA_TYPE_BACKPLANE,
140 I40E_MEDIA_TYPE_VIRTUAL
152 enum i40e_set_fc_aq_failures {
153 I40E_SET_FC_AQ_FAIL_NONE = 0,
154 I40E_SET_FC_AQ_FAIL_GET = 1,
155 I40E_SET_FC_AQ_FAIL_SET = 2,
156 I40E_SET_FC_AQ_FAIL_UPDATE = 4,
157 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
169 I40E_VSI_TYPE_UNKNOWN
172 enum i40e_queue_type {
173 I40E_QUEUE_TYPE_RX = 0,
175 I40E_QUEUE_TYPE_PE_CEQ,
176 I40E_QUEUE_TYPE_UNKNOWN
179 struct i40e_link_status {
180 enum i40e_aq_phy_type phy_type;
181 enum i40e_aq_link_speed link_speed;
186 /* is Link Status Event notification to SW enabled */
194 struct i40e_phy_info {
195 struct i40e_link_status link_info;
196 struct i40e_link_status link_info_old;
197 u32 autoneg_advertised;
201 enum i40e_media_type media_type;
204 #define I40E_HW_CAP_MAX_GPIO 30
205 /* Capabilities of a PF or a VF or the whole device */
206 struct i40e_hw_capabilities {
208 #define I40E_NVM_IMAGE_TYPE_EVB 0x0
209 #define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
210 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
218 bool evb_802_1_qbg; /* Edge Virtual Bridging */
219 bool evb_802_1_qbh; /* Bridge Port Extension */
222 bool iscsi; /* Indicates iSCSI enabled */
226 #define I40E_FLEX10_MODE_UNKNOWN 0x0
227 #define I40E_FLEX10_MODE_DCC 0x1
228 #define I40E_FLEX10_MODE_DCI 0x2
231 #define I40E_FLEX10_STATUS_DCC_ERROR 0x1
232 #define I40E_FLEX10_STATUS_VC_MODE 0x2
238 u32 fd_filters_guaranteed;
239 u32 fd_filters_best_effort;
242 u32 rss_table_entry_width;
243 bool led[I40E_HW_CAP_MAX_GPIO];
244 bool sdp[I40E_HW_CAP_MAX_GPIO];
246 u32 num_flow_director_filters;
253 u32 num_msix_vectors;
254 u32 num_msix_vectors_vf;
265 struct i40e_mac_info {
266 enum i40e_mac_type type;
268 u8 perm_addr[ETH_ALEN];
269 u8 san_addr[ETH_ALEN];
270 u8 port_addr[ETH_ALEN];
274 enum i40e_aq_resources_ids {
275 I40E_NVM_RESOURCE_ID = 1
278 enum i40e_aq_resource_access_type {
279 I40E_RESOURCE_READ = 1,
283 struct i40e_nvm_info {
284 u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
285 u32 timeout; /* [ms] */
286 u16 sr_size; /* Shadow RAM size in words */
287 bool blank_nvm_mode; /* is NVM empty (no FW present)*/
288 u16 version; /* NVM package version */
289 u32 eetrack; /* NVM data version */
292 /* definitions used in NVM update support */
294 enum i40e_nvmupd_cmd {
296 I40E_NVMUPD_READ_CON,
297 I40E_NVMUPD_READ_SNT,
298 I40E_NVMUPD_READ_LCB,
300 I40E_NVMUPD_WRITE_ERA,
301 I40E_NVMUPD_WRITE_CON,
302 I40E_NVMUPD_WRITE_SNT,
303 I40E_NVMUPD_WRITE_LCB,
304 I40E_NVMUPD_WRITE_SA,
305 I40E_NVMUPD_CSUM_CON,
307 I40E_NVMUPD_CSUM_LCB,
312 enum i40e_nvmupd_state {
313 I40E_NVMUPD_STATE_INIT,
314 I40E_NVMUPD_STATE_READING,
315 I40E_NVMUPD_STATE_WRITING,
316 I40E_NVMUPD_STATE_INIT_WAIT,
317 I40E_NVMUPD_STATE_WRITE_WAIT,
320 /* nvm_access definition and its masks/shifts need to be accessible to
321 * application, core driver, and shared code. Where is the right file?
323 #define I40E_NVM_READ 0xB
324 #define I40E_NVM_WRITE 0xC
326 #define I40E_NVM_MOD_PNT_MASK 0xFF
328 #define I40E_NVM_TRANS_SHIFT 8
329 #define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT)
330 #define I40E_NVM_CON 0x0
331 #define I40E_NVM_SNT 0x1
332 #define I40E_NVM_LCB 0x2
333 #define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB)
334 #define I40E_NVM_ERA 0x4
335 #define I40E_NVM_CSUM 0x8
336 #define I40E_NVM_EXEC 0xf
338 #define I40E_NVM_ADAPT_SHIFT 16
339 #define I40E_NVM_ADAPT_MASK (0xffff << I40E_NVM_ADAPT_SHIFT)
341 #define I40E_NVMUPD_MAX_DATA 4096
342 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
344 struct i40e_nvm_access {
347 u32 offset; /* in bytes */
348 u32 data_size; /* in bytes */
354 i40e_bus_type_unknown = 0,
357 i40e_bus_type_pci_express,
358 i40e_bus_type_reserved
362 enum i40e_bus_speed {
363 i40e_bus_speed_unknown = 0,
364 i40e_bus_speed_33 = 33,
365 i40e_bus_speed_66 = 66,
366 i40e_bus_speed_100 = 100,
367 i40e_bus_speed_120 = 120,
368 i40e_bus_speed_133 = 133,
369 i40e_bus_speed_2500 = 2500,
370 i40e_bus_speed_5000 = 5000,
371 i40e_bus_speed_8000 = 8000,
372 i40e_bus_speed_reserved
376 enum i40e_bus_width {
377 i40e_bus_width_unknown = 0,
378 i40e_bus_width_pcie_x1 = 1,
379 i40e_bus_width_pcie_x2 = 2,
380 i40e_bus_width_pcie_x4 = 4,
381 i40e_bus_width_pcie_x8 = 8,
382 i40e_bus_width_32 = 32,
383 i40e_bus_width_64 = 64,
384 i40e_bus_width_reserved
388 struct i40e_bus_info {
389 enum i40e_bus_speed speed;
390 enum i40e_bus_width width;
391 enum i40e_bus_type type;
398 /* Flow control (FC) parameters */
399 struct i40e_fc_info {
400 enum i40e_fc_mode current_mode; /* FC mode in effect */
401 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
404 #define I40E_MAX_TRAFFIC_CLASS 8
405 #define I40E_MAX_USER_PRIORITY 8
406 #define I40E_DCBX_MAX_APPS 32
407 #define I40E_LLDPDU_SIZE 1500
408 #define I40E_TLV_STATUS_OPER 0x1
409 #define I40E_TLV_STATUS_SYNC 0x2
410 #define I40E_TLV_STATUS_ERR 0x4
411 #define I40E_CEE_OPER_MAX_APPS 3
412 #define I40E_APP_PROTOID_FCOE 0x8906
413 #define I40E_APP_PROTOID_ISCSI 0x0cbc
414 #define I40E_APP_PROTOID_FIP 0x8914
415 #define I40E_APP_SEL_ETHTYPE 0x1
416 #define I40E_APP_SEL_TCPIP 0x2
418 /* CEE or IEEE 802.1Qaz ETS Configuration data */
419 struct i40e_dcb_ets_config {
423 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
424 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
425 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
428 /* CEE or IEEE 802.1Qaz PFC Configuration data */
429 struct i40e_dcb_pfc_config {
436 /* CEE or IEEE 802.1Qaz Application Priority data */
437 struct i40e_dcb_app_priority_table {
443 struct i40e_dcbx_config {
445 #define I40E_DCBX_MODE_CEE 0x1
446 #define I40E_DCBX_MODE_IEEE 0x2
448 u32 tlv_status; /* CEE mode TLV status */
449 struct i40e_dcb_ets_config etscfg;
450 struct i40e_dcb_ets_config etsrec;
451 struct i40e_dcb_pfc_config pfc;
452 struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
455 /* Port hardware description */
460 /* subsystem structs */
461 struct i40e_phy_info phy;
462 struct i40e_mac_info mac;
463 struct i40e_bus_info bus;
464 struct i40e_nvm_info nvm;
465 struct i40e_fc_info fc;
470 u16 subsystem_device_id;
471 u16 subsystem_vendor_id;
474 bool adapter_stopped;
476 /* capabilities for entire device and PCI func */
477 struct i40e_hw_capabilities dev_caps;
478 struct i40e_hw_capabilities func_caps;
480 /* Flow Director shared filter space */
481 u16 fdir_shared_filter_count;
483 /* device profile info */
487 /* for multi-function MACs */
492 /* Closest numa node to the device */
495 /* Admin Queue info */
496 struct i40e_adminq_info aq;
498 /* state of nvm update process */
499 enum i40e_nvmupd_state nvmupd_state;
500 struct i40e_aq_desc nvm_wb_desc;
501 struct i40e_virt_mem nvm_buff;
504 struct i40e_hmc_info hmc; /* HMC info struct */
506 /* LLDP/DCBX Status */
510 struct i40e_dcbx_config local_dcbx_config;
511 struct i40e_dcbx_config remote_dcbx_config;
518 static inline bool i40e_is_vf(struct i40e_hw *hw)
520 return (hw->mac.type == I40E_MAC_VF ||
521 hw->mac.type == I40E_MAC_X722_VF);
524 struct i40e_driver_version {
529 u8 driver_string[32];
533 union i40e_16byte_rx_desc {
535 __le64 pkt_addr; /* Packet buffer address */
536 __le64 hdr_addr; /* Header buffer address */
542 __le16 mirroring_status;
548 __le32 rss; /* RSS Hash */
549 __le32 fd_id; /* Flow director filter id */
550 __le32 fcoe_param; /* FCoE DDP Context id */
554 /* ext status/error/pktype/length */
555 __le64 status_error_len;
557 } wb; /* writeback */
560 union i40e_32byte_rx_desc {
562 __le64 pkt_addr; /* Packet buffer address */
563 __le64 hdr_addr; /* Header buffer address */
564 /* bit 0 of hdr_buffer_addr is DD bit */
572 __le16 mirroring_status;
578 __le32 rss; /* RSS Hash */
579 __le32 fcoe_param; /* FCoE DDP Context id */
580 /* Flow director filter id in case of
581 * Programming status desc WB
587 /* status/error/pktype/length */
588 __le64 status_error_len;
591 __le16 ext_status; /* extended status */
598 __le32 flex_bytes_lo;
602 __le32 flex_bytes_hi;
606 } wb; /* writeback */
609 enum i40e_rx_desc_status_bits {
610 /* Note: These are predefined bit offsets */
611 I40E_RX_DESC_STATUS_DD_SHIFT = 0,
612 I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
613 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
614 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
615 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
616 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
617 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
618 /* Note: Bit 8 is reserved in X710 and XL710 */
619 I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT = 8,
620 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
621 I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
622 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */
623 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
624 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
625 I40E_RX_DESC_STATUS_RESERVED_SHIFT = 16, /* 2 BITS */
626 /* Note: For non-tunnel packets INT_UDP_0 is the right status for
629 I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT = 18,
630 I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
633 #define I40E_RXD_QW1_STATUS_SHIFT 0
634 #define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) \
635 << I40E_RXD_QW1_STATUS_SHIFT)
637 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
638 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
639 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
641 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
642 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK \
643 BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
645 enum i40e_rx_desc_fltstat_values {
646 I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
647 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
648 I40E_RX_DESC_FLTSTAT_RSV = 2,
649 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3,
652 #define I40E_RXD_QW1_ERROR_SHIFT 19
653 #define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
655 enum i40e_rx_desc_error_bits {
656 /* Note: These are predefined bit offsets */
657 I40E_RX_DESC_ERROR_RXE_SHIFT = 0,
658 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1,
659 I40E_RX_DESC_ERROR_HBO_SHIFT = 2,
660 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */
661 I40E_RX_DESC_ERROR_IPE_SHIFT = 3,
662 I40E_RX_DESC_ERROR_L4E_SHIFT = 4,
663 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5,
664 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6,
665 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7
668 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
669 I40E_RX_DESC_ERROR_L3L4E_NONE = 0,
670 I40E_RX_DESC_ERROR_L3L4E_PROT = 1,
671 I40E_RX_DESC_ERROR_L3L4E_FC = 2,
672 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
673 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
676 #define I40E_RXD_QW1_PTYPE_SHIFT 30
677 #define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
679 /* Packet type non-ip values */
680 enum i40e_rx_l2_ptype {
681 I40E_RX_PTYPE_L2_RESERVED = 0,
682 I40E_RX_PTYPE_L2_MAC_PAY2 = 1,
683 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
684 I40E_RX_PTYPE_L2_FIP_PAY2 = 3,
685 I40E_RX_PTYPE_L2_OUI_PAY2 = 4,
686 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
687 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6,
688 I40E_RX_PTYPE_L2_ECP_PAY2 = 7,
689 I40E_RX_PTYPE_L2_EVB_PAY2 = 8,
690 I40E_RX_PTYPE_L2_QCN_PAY2 = 9,
691 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10,
692 I40E_RX_PTYPE_L2_ARP = 11,
693 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12,
694 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
695 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
696 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
697 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
698 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
699 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
700 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
701 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
702 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21,
703 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
704 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
705 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
706 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153
709 struct i40e_rx_ptype_decoded {
716 u32 tunnel_end_prot:2;
717 u32 tunnel_end_frag:1;
722 enum i40e_rx_ptype_outer_ip {
723 I40E_RX_PTYPE_OUTER_L2 = 0,
724 I40E_RX_PTYPE_OUTER_IP = 1
727 enum i40e_rx_ptype_outer_ip_ver {
728 I40E_RX_PTYPE_OUTER_NONE = 0,
729 I40E_RX_PTYPE_OUTER_IPV4 = 0,
730 I40E_RX_PTYPE_OUTER_IPV6 = 1
733 enum i40e_rx_ptype_outer_fragmented {
734 I40E_RX_PTYPE_NOT_FRAG = 0,
735 I40E_RX_PTYPE_FRAG = 1
738 enum i40e_rx_ptype_tunnel_type {
739 I40E_RX_PTYPE_TUNNEL_NONE = 0,
740 I40E_RX_PTYPE_TUNNEL_IP_IP = 1,
741 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
742 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
743 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
746 enum i40e_rx_ptype_tunnel_end_prot {
747 I40E_RX_PTYPE_TUNNEL_END_NONE = 0,
748 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1,
749 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2,
752 enum i40e_rx_ptype_inner_prot {
753 I40E_RX_PTYPE_INNER_PROT_NONE = 0,
754 I40E_RX_PTYPE_INNER_PROT_UDP = 1,
755 I40E_RX_PTYPE_INNER_PROT_TCP = 2,
756 I40E_RX_PTYPE_INNER_PROT_SCTP = 3,
757 I40E_RX_PTYPE_INNER_PROT_ICMP = 4,
758 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5
761 enum i40e_rx_ptype_payload_layer {
762 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
763 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
764 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
765 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
768 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
769 #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
770 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
772 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
773 #define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
774 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
776 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
777 #define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
779 enum i40e_rx_desc_ext_status_bits {
780 /* Note: These are predefined bit offsets */
781 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
782 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
783 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */
784 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */
785 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
786 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
787 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
790 enum i40e_rx_desc_pe_status_bits {
791 /* Note: These are predefined bit offsets */
792 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */
793 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */
794 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */
795 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
796 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
797 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
798 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27,
799 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
800 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
803 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
804 #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
806 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
807 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
808 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
810 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
811 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
812 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
814 enum i40e_rx_prog_status_desc_status_bits {
815 /* Note: These are predefined bit offsets */
816 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
817 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */
820 enum i40e_rx_prog_status_desc_prog_id_masks {
821 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
822 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
823 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
826 enum i40e_rx_prog_status_desc_error_bits {
827 /* Note: These are predefined bit offsets */
828 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
829 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1,
830 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
831 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
835 struct i40e_tx_desc {
836 __le64 buffer_addr; /* Address of descriptor's data buf */
837 __le64 cmd_type_offset_bsz;
840 #define I40E_TXD_QW1_DTYPE_SHIFT 0
841 #define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
843 enum i40e_tx_desc_dtype_value {
844 I40E_TX_DESC_DTYPE_DATA = 0x0,
845 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */
846 I40E_TX_DESC_DTYPE_CONTEXT = 0x1,
847 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2,
848 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8,
849 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9,
850 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB,
851 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
852 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
853 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF
856 #define I40E_TXD_QW1_CMD_SHIFT 4
857 #define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
859 enum i40e_tx_desc_cmd_bits {
860 I40E_TX_DESC_CMD_EOP = 0x0001,
861 I40E_TX_DESC_CMD_RS = 0x0002,
862 I40E_TX_DESC_CMD_ICRC = 0x0004,
863 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008,
864 I40E_TX_DESC_CMD_DUMMY = 0x0010,
865 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */
866 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */
867 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */
868 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */
869 I40E_TX_DESC_CMD_FCOET = 0x0080,
870 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */
871 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */
872 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */
873 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */
874 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */
875 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */
876 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */
877 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */
880 #define I40E_TXD_QW1_OFFSET_SHIFT 16
881 #define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
882 I40E_TXD_QW1_OFFSET_SHIFT)
884 enum i40e_tx_desc_length_fields {
885 /* Note: These are predefined bit offsets */
886 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */
887 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */
888 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */
891 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
892 #define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
893 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
895 #define I40E_TXD_QW1_L2TAG1_SHIFT 48
896 #define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
898 /* Context descriptors */
899 struct i40e_tx_context_desc {
900 __le32 tunneling_params;
903 __le64 type_cmd_tso_mss;
906 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
907 #define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
909 #define I40E_TXD_CTX_QW1_CMD_SHIFT 4
910 #define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
912 enum i40e_tx_ctx_desc_cmd_bits {
913 I40E_TX_CTX_DESC_TSO = 0x01,
914 I40E_TX_CTX_DESC_TSYN = 0x02,
915 I40E_TX_CTX_DESC_IL2TAG2 = 0x04,
916 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
917 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
918 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
919 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
920 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30,
921 I40E_TX_CTX_DESC_SWPE = 0x40
924 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
925 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
926 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
928 #define I40E_TXD_CTX_QW1_MSS_SHIFT 50
929 #define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
930 I40E_TXD_CTX_QW1_MSS_SHIFT)
932 #define I40E_TXD_CTX_QW1_VSI_SHIFT 50
933 #define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
935 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
936 #define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
937 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
939 enum i40e_tx_ctx_desc_eipt_offload {
940 I40E_TX_CTX_EXT_IP_NONE = 0x0,
941 I40E_TX_CTX_EXT_IP_IPV6 = 0x1,
942 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
943 I40E_TX_CTX_EXT_IP_IPV4 = 0x3
946 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
947 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
948 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
950 #define I40E_TXD_CTX_QW0_NATT_SHIFT 9
951 #define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
953 #define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
954 #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
956 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
957 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK \
958 BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
960 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
962 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
963 #define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
964 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
966 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
967 #define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
968 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
970 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT 23
971 #define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
972 struct i40e_filter_program_desc {
973 __le32 qindex_flex_ptype_vsi;
975 __le32 dtype_cmd_cntindex;
978 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
979 #define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
980 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
981 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
982 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
983 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
984 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
985 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
986 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
988 /* Packet Classifier Types for filters */
989 enum i40e_filter_pctype {
990 /* Note: Values 0-28 are reserved for future use.
991 * Value 29, 30, 32 are not supported on XL710 and X710.
993 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29,
994 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30,
995 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
996 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32,
997 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
998 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
999 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
1000 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
1001 /* Note: Values 37-38 are reserved for future use.
1002 * Value 39, 40, 42 are not supported on XL710 and X710.
1004 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39,
1005 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40,
1006 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
1007 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42,
1008 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
1009 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
1010 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
1011 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
1012 /* Note: Value 47 is reserved for future use */
1013 I40E_FILTER_PCTYPE_FCOE_OX = 48,
1014 I40E_FILTER_PCTYPE_FCOE_RX = 49,
1015 I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
1016 /* Note: Values 51-62 are reserved for future use */
1017 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
1020 enum i40e_filter_program_desc_dest {
1021 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
1022 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
1023 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
1026 enum i40e_filter_program_desc_fd_status {
1027 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
1028 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
1029 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
1030 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
1033 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
1034 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK \
1035 BIT_ULL(I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1037 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
1038 #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
1039 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1041 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1042 #define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1044 enum i40e_filter_program_desc_pcmd {
1045 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
1046 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
1049 #define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1050 #define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1052 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1053 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1055 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
1056 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1057 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1058 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1060 #define I40E_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \
1061 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1062 #define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1064 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1065 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1066 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1068 enum i40e_filter_type {
1069 I40E_FLOW_DIRECTOR_FLTR = 0,
1070 I40E_PE_QUAD_HASH_FLTR = 1,
1071 I40E_ETHERTYPE_FLTR,
1077 struct i40e_vsi_context {
1082 u16 vsis_unallocated;
1087 struct i40e_aqc_vsi_properties_data info;
1090 struct i40e_veb_context {
1095 u16 vebs_unallocated;
1097 struct i40e_aqc_get_veb_parameters_completion info;
1100 /* Statistics collected by each port, VSI, VEB, and S-channel */
1101 struct i40e_eth_stats {
1102 u64 rx_bytes; /* gorc */
1103 u64 rx_unicast; /* uprc */
1104 u64 rx_multicast; /* mprc */
1105 u64 rx_broadcast; /* bprc */
1106 u64 rx_discards; /* rdpc */
1107 u64 rx_unknown_protocol; /* rupp */
1108 u64 tx_bytes; /* gotc */
1109 u64 tx_unicast; /* uptc */
1110 u64 tx_multicast; /* mptc */
1111 u64 tx_broadcast; /* bptc */
1112 u64 tx_discards; /* tdpc */
1113 u64 tx_errors; /* tepc */
1116 /* Statistics collected per VEB per TC */
1117 struct i40e_veb_tc_stats {
1118 u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1119 u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1120 u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1121 u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1125 /* Statistics collected per function for FCoE */
1126 struct i40e_fcoe_stats {
1127 u64 rx_fcoe_packets; /* fcoeprc */
1128 u64 rx_fcoe_dwords; /* focedwrc */
1129 u64 rx_fcoe_dropped; /* fcoerpdc */
1130 u64 tx_fcoe_packets; /* fcoeptc */
1131 u64 tx_fcoe_dwords; /* focedwtc */
1132 u64 fcoe_bad_fccrc; /* fcoecrc */
1133 u64 fcoe_last_error; /* fcoelast */
1134 u64 fcoe_ddp_count; /* fcoeddpc */
1137 /* offset to per function FCoE statistics block */
1138 #define I40E_FCOE_VF_STAT_OFFSET 0
1139 #define I40E_FCOE_PF_STAT_OFFSET 128
1140 #define I40E_FCOE_STAT_MAX (I40E_FCOE_PF_STAT_OFFSET + I40E_MAX_PF)
1143 /* Statistics collected by the MAC */
1144 struct i40e_hw_port_stats {
1145 /* eth stats collected by the port */
1146 struct i40e_eth_stats eth;
1148 /* additional port specific stats */
1149 u64 tx_dropped_link_down; /* tdold */
1150 u64 crc_errors; /* crcerrs */
1151 u64 illegal_bytes; /* illerrc */
1152 u64 error_bytes; /* errbc */
1153 u64 mac_local_faults; /* mlfc */
1154 u64 mac_remote_faults; /* mrfc */
1155 u64 rx_length_errors; /* rlec */
1156 u64 link_xon_rx; /* lxonrxc */
1157 u64 link_xoff_rx; /* lxoffrxc */
1158 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1159 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1160 u64 link_xon_tx; /* lxontxc */
1161 u64 link_xoff_tx; /* lxofftxc */
1162 u64 priority_xon_tx[8]; /* pxontxc[8] */
1163 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1164 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1165 u64 rx_size_64; /* prc64 */
1166 u64 rx_size_127; /* prc127 */
1167 u64 rx_size_255; /* prc255 */
1168 u64 rx_size_511; /* prc511 */
1169 u64 rx_size_1023; /* prc1023 */
1170 u64 rx_size_1522; /* prc1522 */
1171 u64 rx_size_big; /* prc9522 */
1172 u64 rx_undersize; /* ruc */
1173 u64 rx_fragments; /* rfc */
1174 u64 rx_oversize; /* roc */
1175 u64 rx_jabber; /* rjc */
1176 u64 tx_size_64; /* ptc64 */
1177 u64 tx_size_127; /* ptc127 */
1178 u64 tx_size_255; /* ptc255 */
1179 u64 tx_size_511; /* ptc511 */
1180 u64 tx_size_1023; /* ptc1023 */
1181 u64 tx_size_1522; /* ptc1522 */
1182 u64 tx_size_big; /* ptc9522 */
1183 u64 mac_short_packet_dropped; /* mspdc */
1184 u64 checksum_error; /* xec */
1185 /* flow director stats */
1188 u64 fd_atr_tunnel_match;
1194 u64 tx_lpi_count; /* etlpic */
1195 u64 rx_lpi_count; /* erlpic */
1198 /* Checksum and Shadow RAM pointers */
1199 #define I40E_SR_NVM_CONTROL_WORD 0x00
1200 #define I40E_SR_EMP_MODULE_PTR 0x0F
1201 #define I40E_SR_PBA_FLAGS 0x15
1202 #define I40E_SR_PBA_BLOCK_PTR 0x16
1203 #define I40E_SR_NVM_DEV_STARTER_VERSION 0x18
1204 #define I40E_SR_NVM_WAKE_ON_LAN 0x19
1205 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1206 #define I40E_SR_NVM_EETRACK_LO 0x2D
1207 #define I40E_SR_NVM_EETRACK_HI 0x2E
1208 #define I40E_SR_VPD_PTR 0x2F
1209 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1210 #define I40E_SR_SW_CHECKSUM_WORD 0x3F
1212 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1213 #define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1214 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1215 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1216 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1218 /* Shadow RAM related */
1219 #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1220 #define I40E_SR_WORDS_IN_1KB 512
1221 /* Checksum should be calculated such that after adding all the words,
1222 * including the checksum word itself, the sum should be 0xBABA.
1224 #define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1226 #define I40E_SRRD_SRCTL_ATTEMPTS 100000
1229 /* FCoE Tx context descriptor - Use the i40e_tx_context_desc struct */
1231 enum i40E_fcoe_tx_ctx_desc_cmd_bits {
1232 I40E_FCOE_TX_CTX_DESC_OPCODE_SINGLE_SEND = 0x00, /* 4 BITS */
1233 I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS2 = 0x01, /* 4 BITS */
1234 I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS3 = 0x05, /* 4 BITS */
1235 I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS2 = 0x02, /* 4 BITS */
1236 I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS3 = 0x06, /* 4 BITS */
1237 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS2 = 0x03, /* 4 BITS */
1238 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS3 = 0x07, /* 4 BITS */
1239 I40E_FCOE_TX_CTX_DESC_OPCODE_DDP_CTX_INVL = 0x08, /* 4 BITS */
1240 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_CTX_INVL = 0x09, /* 4 BITS */
1241 I40E_FCOE_TX_CTX_DESC_RELOFF = 0x10,
1242 I40E_FCOE_TX_CTX_DESC_CLRSEQ = 0x20,
1243 I40E_FCOE_TX_CTX_DESC_DIFENA = 0x40,
1244 I40E_FCOE_TX_CTX_DESC_IL2TAG2 = 0x80
1247 /* FCoE DDP Context descriptor */
1248 struct i40e_fcoe_ddp_context_desc {
1250 __le64 type_cmd_foff_lsize;
1253 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT 0
1254 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_MASK (0xFULL << \
1255 I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT)
1257 #define I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT 4
1258 #define I40E_FCOE_DDP_CTX_QW1_CMD_MASK (0xFULL << \
1259 I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT)
1261 enum i40e_fcoe_ddp_ctx_desc_cmd_bits {
1262 I40E_FCOE_DDP_CTX_DESC_BSIZE_512B = 0x00, /* 2 BITS */
1263 I40E_FCOE_DDP_CTX_DESC_BSIZE_4K = 0x01, /* 2 BITS */
1264 I40E_FCOE_DDP_CTX_DESC_BSIZE_8K = 0x02, /* 2 BITS */
1265 I40E_FCOE_DDP_CTX_DESC_BSIZE_16K = 0x03, /* 2 BITS */
1266 I40E_FCOE_DDP_CTX_DESC_DIFENA = 0x04, /* 1 BIT */
1267 I40E_FCOE_DDP_CTX_DESC_LASTSEQH = 0x08, /* 1 BIT */
1270 #define I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT 16
1271 #define I40E_FCOE_DDP_CTX_QW1_FOFF_MASK (0x3FFFULL << \
1272 I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT)
1274 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT 32
1275 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_MASK (0x3FFFULL << \
1276 I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT)
1278 /* FCoE DDP/DWO Queue Context descriptor */
1279 struct i40e_fcoe_queue_context_desc {
1280 __le64 dmaindx_fbase; /* 0:11 DMAINDX, 12:63 FBASE */
1281 __le64 flen_tph; /* 0:12 FLEN, 13:15 TPH */
1284 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT 0
1285 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_MASK (0xFFFULL << \
1286 I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT)
1288 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT 12
1289 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_MASK (0xFFFFFFFFFFFFFULL << \
1290 I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT)
1292 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT 0
1293 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_MASK (0x1FFFULL << \
1294 I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1296 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_SHIFT 13
1297 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_MASK (0x7ULL << \
1298 I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1300 enum i40e_fcoe_queue_ctx_desc_tph_bits {
1301 I40E_FCOE_QUEUE_CTX_DESC_TPHRDESC = 0x1,
1302 I40E_FCOE_QUEUE_CTX_DESC_TPHDATA = 0x2
1305 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT 30
1306 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_MASK (0x3ULL << \
1307 I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT)
1309 /* FCoE DDP/DWO Filter Context descriptor */
1310 struct i40e_fcoe_filter_context_desc {
1314 /* 48:51(0:3) RSVD, 52:63(4:15) DMAINDX */
1315 __le16 rsvd_dmaindx;
1317 /* 0:7 FLAGS, 8:52 RSVD, 53:63 LANQ */
1318 __le64 flags_rsvd_lanq;
1321 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT 4
1322 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_MASK (0xFFF << \
1323 I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT)
1325 enum i40e_fcoe_filter_ctx_desc_flags_bits {
1326 I40E_FCOE_FILTER_CTX_DESC_CTYP_DDP = 0x00,
1327 I40E_FCOE_FILTER_CTX_DESC_CTYP_DWO = 0x01,
1328 I40E_FCOE_FILTER_CTX_DESC_ENODE_INIT = 0x00,
1329 I40E_FCOE_FILTER_CTX_DESC_ENODE_RSP = 0x02,
1330 I40E_FCOE_FILTER_CTX_DESC_FC_CLASS2 = 0x00,
1331 I40E_FCOE_FILTER_CTX_DESC_FC_CLASS3 = 0x04
1334 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT 0
1335 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_MASK (0xFFULL << \
1336 I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT)
1338 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT 8
1339 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_MASK (0x3FULL << \
1340 I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT)
1342 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT 53
1343 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_MASK (0x7FFULL << \
1344 I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT)
1346 #endif /* I40E_FCOE */
1347 enum i40e_switch_element_types {
1348 I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
1349 I40E_SWITCH_ELEMENT_TYPE_PF = 2,
1350 I40E_SWITCH_ELEMENT_TYPE_VF = 3,
1351 I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
1352 I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
1353 I40E_SWITCH_ELEMENT_TYPE_PE = 16,
1354 I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
1355 I40E_SWITCH_ELEMENT_TYPE_PA = 18,
1356 I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
1359 /* Supported EtherType filters */
1360 enum i40e_ether_type_index {
1361 I40E_ETHER_TYPE_1588 = 0,
1362 I40E_ETHER_TYPE_FIP = 1,
1363 I40E_ETHER_TYPE_OUI_EXTENDED = 2,
1364 I40E_ETHER_TYPE_MAC_CONTROL = 3,
1365 I40E_ETHER_TYPE_LLDP = 4,
1366 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
1367 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
1368 I40E_ETHER_TYPE_QCN_CNM = 7,
1369 I40E_ETHER_TYPE_8021X = 8,
1370 I40E_ETHER_TYPE_ARP = 9,
1371 I40E_ETHER_TYPE_RSV1 = 10,
1372 I40E_ETHER_TYPE_RSV2 = 11,
1375 /* Filter context base size is 1K */
1376 #define I40E_HASH_FILTER_BASE_SIZE 1024
1377 /* Supported Hash filter values */
1378 enum i40e_hash_filter_size {
1379 I40E_HASH_FILTER_SIZE_1K = 0,
1380 I40E_HASH_FILTER_SIZE_2K = 1,
1381 I40E_HASH_FILTER_SIZE_4K = 2,
1382 I40E_HASH_FILTER_SIZE_8K = 3,
1383 I40E_HASH_FILTER_SIZE_16K = 4,
1384 I40E_HASH_FILTER_SIZE_32K = 5,
1385 I40E_HASH_FILTER_SIZE_64K = 6,
1386 I40E_HASH_FILTER_SIZE_128K = 7,
1387 I40E_HASH_FILTER_SIZE_256K = 8,
1388 I40E_HASH_FILTER_SIZE_512K = 9,
1389 I40E_HASH_FILTER_SIZE_1M = 10,
1392 /* DMA context base size is 0.5K */
1393 #define I40E_DMA_CNTX_BASE_SIZE 512
1394 /* Supported DMA context values */
1395 enum i40e_dma_cntx_size {
1396 I40E_DMA_CNTX_SIZE_512 = 0,
1397 I40E_DMA_CNTX_SIZE_1K = 1,
1398 I40E_DMA_CNTX_SIZE_2K = 2,
1399 I40E_DMA_CNTX_SIZE_4K = 3,
1400 I40E_DMA_CNTX_SIZE_8K = 4,
1401 I40E_DMA_CNTX_SIZE_16K = 5,
1402 I40E_DMA_CNTX_SIZE_32K = 6,
1403 I40E_DMA_CNTX_SIZE_64K = 7,
1404 I40E_DMA_CNTX_SIZE_128K = 8,
1405 I40E_DMA_CNTX_SIZE_256K = 9,
1408 /* Supported Hash look up table (LUT) sizes */
1409 enum i40e_hash_lut_size {
1410 I40E_HASH_LUT_SIZE_128 = 0,
1411 I40E_HASH_LUT_SIZE_512 = 1,
1414 /* Structure to hold a per PF filter control settings */
1415 struct i40e_filter_control_settings {
1416 /* number of PE Quad Hash filter buckets */
1417 enum i40e_hash_filter_size pe_filt_num;
1418 /* number of PE Quad Hash contexts */
1419 enum i40e_dma_cntx_size pe_cntx_num;
1420 /* number of FCoE filter buckets */
1421 enum i40e_hash_filter_size fcoe_filt_num;
1422 /* number of FCoE DDP contexts */
1423 enum i40e_dma_cntx_size fcoe_cntx_num;
1424 /* size of the Hash LUT */
1425 enum i40e_hash_lut_size hash_lut_size;
1426 /* enable FDIR filters for PF and its VFs */
1428 /* enable Ethertype filters for PF and its VFs */
1429 bool enable_ethtype;
1430 /* enable MAC/VLAN filters for PF and its VFs */
1431 bool enable_macvlan;
1434 /* Structure to hold device level control filter counts */
1435 struct i40e_control_filter_stats {
1436 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */
1437 u16 etype_used; /* Used perfect EtherType filters */
1438 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */
1439 u16 etype_free; /* Un-used perfect EtherType filters */
1442 enum i40e_reset_type {
1444 I40E_RESET_CORER = 1,
1445 I40E_RESET_GLOBR = 2,
1446 I40E_RESET_EMPR = 3,
1449 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1450 #define I40E_NVM_LLDP_CFG_PTR 0xD
1451 struct i40e_lldp_variables {
1461 /* Offsets into Alternate Ram */
1462 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET 0 /* in dwords */
1463 #define I40E_ALT_STRUCT_DWORDS_PER_PF 64 /* in dwords */
1464 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET 0xD /* in dwords */
1465 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET 0xC /* in dwords */
1466 #define I40E_ALT_STRUCT_MIN_BW_OFFSET 0xE /* in dwords */
1467 #define I40E_ALT_STRUCT_MAX_BW_OFFSET 0xF /* in dwords */
1469 /* Alternate Ram Bandwidth Masks */
1470 #define I40E_ALT_BW_VALUE_MASK 0xFF
1471 #define I40E_ALT_BW_RELATIVE_MASK 0x40000000
1472 #define I40E_ALT_BW_VALID_MASK 0x80000000
1474 /* RSS Hash Table Size */
1475 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1476 #endif /* _I40E_TYPE_H_ */