drivers/net/ethernet/intel/i40evf/i40e_adminq.c

   1 /*******************************************************************************
   2  *
   3  * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
   4  * Copyright(c) 2013 - 2014 Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  * Contact Information:
  22  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  ******************************************************************************/
  26
  27 #include "i40e_status.h"
  28 #include "i40e_type.h"
  29 #include "i40e_register.h"
  30 #include "i40e_adminq.h"
  31 #include "i40e_prototype.h"
  32
  33 /**
  34  * i40e_is_nvm_update_op - return true if this is an NVM update operation
  35  * @desc: API request descriptor
  36  **/
  37 static inline bool i40e_is_nvm_update_op(struct i40e_aq_desc *desc)
  38 {
  39         return (desc->opcode == i40e_aqc_opc_nvm_erase) ||
  40                (desc->opcode == i40e_aqc_opc_nvm_update);
  41 }
  42
  43 /**
  44  *  i40e_adminq_init_regs - Initialize AdminQ registers
  45  *  @hw: pointer to the hardware structure
  46  *
  47  *  This assumes the alloc_asq and alloc_arq functions have already been called
  48  **/
  49 static void i40e_adminq_init_regs(struct i40e_hw *hw)
  50 {
  51         /* set head and tail registers in our local struct */
  52         if (i40e_is_vf(hw)) {
  53                 hw->aq.asq.tail = I40E_VF_ATQT1;
  54                 hw->aq.asq.head = I40E_VF_ATQH1;
  55                 hw->aq.asq.len  = I40E_VF_ATQLEN1;
  56                 hw->aq.asq.bal  = I40E_VF_ATQBAL1;
  57                 hw->aq.asq.bah  = I40E_VF_ATQBAH1;
  58                 hw->aq.arq.tail = I40E_VF_ARQT1;
  59                 hw->aq.arq.head = I40E_VF_ARQH1;
  60                 hw->aq.arq.len  = I40E_VF_ARQLEN1;
  61                 hw->aq.arq.bal  = I40E_VF_ARQBAL1;
  62                 hw->aq.arq.bah  = I40E_VF_ARQBAH1;
  63         }
  64 }
  65
  66 /**
  67  *  i40e_alloc_adminq_asq_ring - Allocate Admin Queue send rings
  68  *  @hw: pointer to the hardware structure
  69  **/
  70 static i40e_status i40e_alloc_adminq_asq_ring(struct i40e_hw *hw)
  71 {
  72         i40e_status ret_code;
  73
  74         ret_code = i40e_allocate_dma_mem(hw, &hw->aq.asq.desc_buf,
  75                                          i40e_mem_atq_ring,
  76                                          (hw->aq.num_asq_entries *
  77                                          sizeof(struct i40e_aq_desc)),
  78                                          I40E_ADMINQ_DESC_ALIGNMENT);
  79         if (ret_code)
  80                 return ret_code;
  81
  82         ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.cmd_buf,
  83                                           (hw->aq.num_asq_entries *
  84                                           sizeof(struct i40e_asq_cmd_details)));
  85         if (ret_code) {
  86                 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
  87                 return ret_code;
  88         }
  89
  90         return ret_code;
  91 }
  92
  93 /**
  94  *  i40e_alloc_adminq_arq_ring - Allocate Admin Queue receive rings
  95  *  @hw: pointer to the hardware structure
  96  **/
  97 static i40e_status i40e_alloc_adminq_arq_ring(struct i40e_hw *hw)
  98 {
  99         i40e_status ret_code;
 100
 101         ret_code = i40e_allocate_dma_mem(hw, &hw->aq.arq.desc_buf,
 102                                          i40e_mem_arq_ring,
 103                                          (hw->aq.num_arq_entries *
 104                                          sizeof(struct i40e_aq_desc)),
 105                                          I40E_ADMINQ_DESC_ALIGNMENT);
 106
 107         return ret_code;
 108 }
 109
 110 /**
 111  *  i40e_free_adminq_asq - Free Admin Queue send rings
 112  *  @hw: pointer to the hardware structure
 113  *
 114  *  This assumes the posted send buffers have already been cleaned
 115  *  and de-allocated
 116  **/
 117 static void i40e_free_adminq_asq(struct i40e_hw *hw)
 118 {
 119         i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
 120 }
 121
 122 /**
 123  *  i40e_free_adminq_arq - Free Admin Queue receive rings
 124  *  @hw: pointer to the hardware structure
 125  *
 126  *  This assumes the posted receive buffers have already been cleaned
 127  *  and de-allocated
 128  **/
 129 static void i40e_free_adminq_arq(struct i40e_hw *hw)
 130 {
 131         i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf);
 132 }
 133
 134 /**
 135  *  i40e_alloc_arq_bufs - Allocate pre-posted buffers for the receive queue
 136  *  @hw: pointer to the hardware structure
 137  **/
 138 static i40e_status i40e_alloc_arq_bufs(struct i40e_hw *hw)
 139 {
 140         i40e_status ret_code;
 141         struct i40e_aq_desc *desc;
 142         struct i40e_dma_mem *bi;
 143         int i;
 144
 145         /* We'll be allocating the buffer info memory first, then we can
 146          * allocate the mapped buffers for the event processing
 147          */
 148
 149         /* buffer_info structures do not need alignment */
 150         ret_code = i40e_allocate_virt_mem(hw, &hw->aq.arq.dma_head,
 151                 (hw->aq.num_arq_entries * sizeof(struct i40e_dma_mem)));
 152         if (ret_code)
 153                 goto alloc_arq_bufs;
 154         hw->aq.arq.r.arq_bi = (struct i40e_dma_mem *)hw->aq.arq.dma_head.va;
 155
 156         /* allocate the mapped buffers */
 157         for (i = 0; i < hw->aq.num_arq_entries; i++) {
 158                 bi = &hw->aq.arq.r.arq_bi[i];
 159                 ret_code = i40e_allocate_dma_mem(hw, bi,
 160                                                  i40e_mem_arq_buf,
 161                                                  hw->aq.arq_buf_size,
 162                                                  I40E_ADMINQ_DESC_ALIGNMENT);
 163                 if (ret_code)
 164                         goto unwind_alloc_arq_bufs;
 165
 166                 /* now configure the descriptors for use */
 167                 desc = I40E_ADMINQ_DESC(hw->aq.arq, i);
 168
 169                 desc->flags = cpu_to_le16(I40E_AQ_FLAG_BUF);
 170                 if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF)
 171                         desc->flags |= cpu_to_le16(I40E_AQ_FLAG_LB);
 172                 desc->opcode = 0;
 173                 /* This is in accordance with Admin queue design, there is no
 174                  * register for buffer size configuration
 175                  */
 176                 desc->datalen = cpu_to_le16((u16)bi->size);
 177                 desc->retval = 0;
 178                 desc->cookie_high = 0;
 179                 desc->cookie_low = 0;
 180                 desc->params.external.addr_high =
 181                         cpu_to_le32(upper_32_bits(bi->pa));
 182                 desc->params.external.addr_low =
 183                         cpu_to_le32(lower_32_bits(bi->pa));
 184                 desc->params.external.param0 = 0;
 185                 desc->params.external.param1 = 0;
 186         }
 187
 188 alloc_arq_bufs:
 189         return ret_code;
 190
 191 unwind_alloc_arq_bufs:
 192         /* don't try to free the one that failed... */
 193         i--;
 194         for (; i >= 0; i--)
 195                 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);
 196         i40e_free_virt_mem(hw, &hw->aq.arq.dma_head);
 197
 198         return ret_code;
 199 }
 200
 201 /**
 202  *  i40e_alloc_asq_bufs - Allocate empty buffer structs for the send queue
 203  *  @hw: pointer to the hardware structure
 204  **/
 205 static i40e_status i40e_alloc_asq_bufs(struct i40e_hw *hw)
 206 {
 207         i40e_status ret_code;
 208         struct i40e_dma_mem *bi;
 209         int i;
 210
 211         /* No mapped memory needed yet, just the buffer info structures */
 212         ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.dma_head,
 213                 (hw->aq.num_asq_entries * sizeof(struct i40e_dma_mem)));
 214         if (ret_code)
 215                 goto alloc_asq_bufs;
 216         hw->aq.asq.r.asq_bi = (struct i40e_dma_mem *)hw->aq.asq.dma_head.va;
 217
 218         /* allocate the mapped buffers */
 219         for (i = 0; i < hw->aq.num_asq_entries; i++) {
 220                 bi = &hw->aq.asq.r.asq_bi[i];
 221                 ret_code = i40e_allocate_dma_mem(hw, bi,
 222                                                  i40e_mem_asq_buf,
 223                                                  hw->aq.asq_buf_size,
 224                                                  I40E_ADMINQ_DESC_ALIGNMENT);
 225                 if (ret_code)
 226                         goto unwind_alloc_asq_bufs;
 227         }
 228 alloc_asq_bufs:
 229         return ret_code;
 230
 231 unwind_alloc_asq_bufs:
 232         /* don't try to free the one that failed... */
 233         i--;
 234         for (; i >= 0; i--)
 235                 i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
 236         i40e_free_virt_mem(hw, &hw->aq.asq.dma_head);
 237
 238         return ret_code;
 239 }
 240
 241 /**
 242  *  i40e_free_arq_bufs - Free receive queue buffer info elements
 243  *  @hw: pointer to the hardware structure
 244  **/
 245 static void i40e_free_arq_bufs(struct i40e_hw *hw)
 246 {
 247         int i;
 248
 249         /* free descriptors */
 250         for (i = 0; i < hw->aq.num_arq_entries; i++)
 251                 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);
 252
 253         /* free the descriptor memory */
 254         i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf);
 255
 256         /* free the dma header */
 257         i40e_free_virt_mem(hw, &hw->aq.arq.dma_head);
 258 }
 259
 260 /**
 261  *  i40e_free_asq_bufs - Free send queue buffer info elements
 262  *  @hw: pointer to the hardware structure
 263  **/
 264 static void i40e_free_asq_bufs(struct i40e_hw *hw)
 265 {
 266         int i;
 267
 268         /* only unmap if the address is non-NULL */
 269         for (i = 0; i < hw->aq.num_asq_entries; i++)
 270                 if (hw->aq.asq.r.asq_bi[i].pa)
 271                         i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
 272
 273         /* free the buffer info list */
 274         i40e_free_virt_mem(hw, &hw->aq.asq.cmd_buf);
 275
 276         /* free the descriptor memory */
 277         i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
 278
 279         /* free the dma header */
 280         i40e_free_virt_mem(hw, &hw->aq.asq.dma_head);
 281 }
 282
 283 /**
 284  *  i40e_config_asq_regs - configure ASQ registers
 285  *  @hw: pointer to the hardware structure
 286  *
 287  *  Configure base address and length registers for the transmit queue
 288  **/
 289 static i40e_status i40e_config_asq_regs(struct i40e_hw *hw)
 290 {
 291         i40e_status ret_code = 0;
 292         u32 reg = 0;
 293
 294         /* Clear Head and Tail */
 295         wr32(hw, hw->aq.asq.head, 0);
 296         wr32(hw, hw->aq.asq.tail, 0);
 297
 298         /* set starting point */
 299         wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |
 300                                   I40E_VF_ATQLEN1_ATQENABLE_MASK));
 301         wr32(hw, hw->aq.asq.bal, lower_32_bits(hw->aq.asq.desc_buf.pa));
 302         wr32(hw, hw->aq.asq.bah, upper_32_bits(hw->aq.asq.desc_buf.pa));
 303
 304         /* Check one register to verify that config was applied */
 305         reg = rd32(hw, hw->aq.asq.bal);
 306         if (reg != lower_32_bits(hw->aq.asq.desc_buf.pa))
 307                 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
 308
 309         return ret_code;
 310 }
 311
 312 /**
 313  *  i40e_config_arq_regs - ARQ register configuration
 314  *  @hw: pointer to the hardware structure
 315  *
 316  * Configure base address and length registers for the receive (event queue)
 317  **/
 318 static i40e_status i40e_config_arq_regs(struct i40e_hw *hw)
 319 {
 320         i40e_status ret_code = 0;
 321         u32 reg = 0;
 322
 323         /* Clear Head and Tail */
 324         wr32(hw, hw->aq.arq.head, 0);
 325         wr32(hw, hw->aq.arq.tail, 0);
 326
 327         /* set starting point */
 328         wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries |
 329                                   I40E_VF_ARQLEN1_ARQENABLE_MASK));
 330         wr32(hw, hw->aq.arq.bal, lower_32_bits(hw->aq.arq.desc_buf.pa));
 331         wr32(hw, hw->aq.arq.bah, upper_32_bits(hw->aq.arq.desc_buf.pa));
 332
 333         /* Update tail in the HW to post pre-allocated buffers */
 334         wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1);
 335
 336         /* Check one register to verify that config was applied */
 337         reg = rd32(hw, hw->aq.arq.bal);
 338         if (reg != lower_32_bits(hw->aq.arq.desc_buf.pa))
 339                 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
 340
 341         return ret_code;
 342 }
 343
 344 /**
 345  *  i40e_init_asq - main initialization routine for ASQ
 346  *  @hw: pointer to the hardware structure
 347  *
 348  *  This is the main initialization routine for the Admin Send Queue
 349  *  Prior to calling this function, drivers *MUST* set the following fields
 350  *  in the hw->aq structure:
 351  *     - hw->aq.num_asq_entries
 352  *     - hw->aq.arq_buf_size
 353  *
 354  *  Do *NOT* hold the lock when calling this as the memory allocation routines
 355  *  called are not going to be atomic context safe
 356  **/
 357 static i40e_status i40e_init_asq(struct i40e_hw *hw)
 358 {
 359         i40e_status ret_code = 0;
 360
 361         if (hw->aq.asq.count > 0) {
 362                 /* queue already initialized */
 363                 ret_code = I40E_ERR_NOT_READY;
 364                 goto init_adminq_exit;
 365         }
 366
 367         /* verify input for valid configuration */
 368         if ((hw->aq.num_asq_entries == 0) ||
 369             (hw->aq.asq_buf_size == 0)) {
 370                 ret_code = I40E_ERR_CONFIG;
 371                 goto init_adminq_exit;
 372         }
 373
 374         hw->aq.asq.next_to_use = 0;
 375         hw->aq.asq.next_to_clean = 0;
 376
 377         /* allocate the ring memory */
 378         ret_code = i40e_alloc_adminq_asq_ring(hw);
 379         if (ret_code)
 380                 goto init_adminq_exit;
 381
 382         /* allocate buffers in the rings */
 383         ret_code = i40e_alloc_asq_bufs(hw);
 384         if (ret_code)
 385                 goto init_adminq_free_rings;
 386
 387         /* initialize base registers */
 388         ret_code = i40e_config_asq_regs(hw);
 389         if (ret_code)
 390                 goto init_adminq_free_rings;
 391
 392         /* success! */
 393         hw->aq.asq.count = hw->aq.num_asq_entries;
 394         goto init_adminq_exit;
 395
 396 init_adminq_free_rings:
 397         i40e_free_adminq_asq(hw);
 398
 399 init_adminq_exit:
 400         return ret_code;
 401 }
 402
 403 /**
 404  *  i40e_init_arq - initialize ARQ
 405  *  @hw: pointer to the hardware structure
 406  *
 407  *  The main initialization routine for the Admin Receive (Event) Queue.
 408  *  Prior to calling this function, drivers *MUST* set the following fields
 409  *  in the hw->aq structure:
 410  *     - hw->aq.num_asq_entries
 411  *     - hw->aq.arq_buf_size
 412  *
 413  *  Do *NOT* hold the lock when calling this as the memory allocation routines
 414  *  called are not going to be atomic context safe
 415  **/
 416 static i40e_status i40e_init_arq(struct i40e_hw *hw)
 417 {
 418         i40e_status ret_code = 0;
 419
 420         if (hw->aq.arq.count > 0) {
 421                 /* queue already initialized */
 422                 ret_code = I40E_ERR_NOT_READY;
 423                 goto init_adminq_exit;
 424         }
 425
 426         /* verify input for valid configuration */
 427         if ((hw->aq.num_arq_entries == 0) ||
 428             (hw->aq.arq_buf_size == 0)) {
 429                 ret_code = I40E_ERR_CONFIG;
 430                 goto init_adminq_exit;
 431         }
 432
 433         hw->aq.arq.next_to_use = 0;
 434         hw->aq.arq.next_to_clean = 0;
 435
 436         /* allocate the ring memory */
 437         ret_code = i40e_alloc_adminq_arq_ring(hw);
 438         if (ret_code)
 439                 goto init_adminq_exit;
 440
 441         /* allocate buffers in the rings */
 442         ret_code = i40e_alloc_arq_bufs(hw);
 443         if (ret_code)
 444                 goto init_adminq_free_rings;
 445
 446         /* initialize base registers */
 447         ret_code = i40e_config_arq_regs(hw);
 448         if (ret_code)
 449                 goto init_adminq_free_rings;
 450
 451         /* success! */
 452         hw->aq.arq.count = hw->aq.num_arq_entries;
 453         goto init_adminq_exit;
 454
 455 init_adminq_free_rings:
 456         i40e_free_adminq_arq(hw);
 457
 458 init_adminq_exit:
 459         return ret_code;
 460 }
 461
 462 /**
 463  *  i40e_shutdown_asq - shutdown the ASQ
 464  *  @hw: pointer to the hardware structure
 465  *
 466  *  The main shutdown routine for the Admin Send Queue
 467  **/
 468 static i40e_status i40e_shutdown_asq(struct i40e_hw *hw)
 469 {
 470         i40e_status ret_code = 0;
 471
 472         mutex_lock(&hw->aq.asq_mutex);
 473
 474         if (hw->aq.asq.count == 0) {
 475                 ret_code = I40E_ERR_NOT_READY;
 476                 goto shutdown_asq_out;
 477         }
 478
 479         /* Stop firmware AdminQ processing */
 480         wr32(hw, hw->aq.asq.head, 0);
 481         wr32(hw, hw->aq.asq.tail, 0);
 482         wr32(hw, hw->aq.asq.len, 0);
 483         wr32(hw, hw->aq.asq.bal, 0);
 484         wr32(hw, hw->aq.asq.bah, 0);
 485
 486         hw->aq.asq.count = 0; /* to indicate uninitialized queue */
 487
 488         /* free ring buffers */
 489         i40e_free_asq_bufs(hw);
 490
 491 shutdown_asq_out:
 492         mutex_unlock(&hw->aq.asq_mutex);
 493         return ret_code;
 494 }
 495
 496 /**
 497  *  i40e_shutdown_arq - shutdown ARQ
 498  *  @hw: pointer to the hardware structure
 499  *
 500  *  The main shutdown routine for the Admin Receive Queue
 501  **/
 502 static i40e_status i40e_shutdown_arq(struct i40e_hw *hw)
 503 {
 504         i40e_status ret_code = 0;
 505
 506         mutex_lock(&hw->aq.arq_mutex);
 507
 508         if (hw->aq.arq.count == 0) {
 509                 ret_code = I40E_ERR_NOT_READY;
 510                 goto shutdown_arq_out;
 511         }
 512
 513         /* Stop firmware AdminQ processing */
 514         wr32(hw, hw->aq.arq.head, 0);
 515         wr32(hw, hw->aq.arq.tail, 0);
 516         wr32(hw, hw->aq.arq.len, 0);
 517         wr32(hw, hw->aq.arq.bal, 0);
 518         wr32(hw, hw->aq.arq.bah, 0);
 519
 520         hw->aq.arq.count = 0; /* to indicate uninitialized queue */
 521
 522         /* free ring buffers */
 523         i40e_free_arq_bufs(hw);
 524
 525 shutdown_arq_out:
 526         mutex_unlock(&hw->aq.arq_mutex);
 527         return ret_code;
 528 }
 529
 530 /**
 531  *  i40evf_init_adminq - main initialization routine for Admin Queue
 532  *  @hw: pointer to the hardware structure
 533  *
 534  *  Prior to calling this function, drivers *MUST* set the following fields
 535  *  in the hw->aq structure:
 536  *     - hw->aq.num_asq_entries
 537  *     - hw->aq.num_arq_entries
 538  *     - hw->aq.arq_buf_size
 539  *     - hw->aq.asq_buf_size
 540  **/
 541 i40e_status i40evf_init_adminq(struct i40e_hw *hw)
 542 {
 543         i40e_status ret_code;
 544
 545         /* verify input for valid configuration */
 546         if ((hw->aq.num_arq_entries == 0) ||
 547             (hw->aq.num_asq_entries == 0) ||
 548             (hw->aq.arq_buf_size == 0) ||
 549             (hw->aq.asq_buf_size == 0)) {
 550                 ret_code = I40E_ERR_CONFIG;
 551                 goto init_adminq_exit;
 552         }
 553
 554         /* Set up register offsets */
 555         i40e_adminq_init_regs(hw);
 556
 557         /* setup ASQ command write back timeout */
 558         hw->aq.asq_cmd_timeout = I40E_ASQ_CMD_TIMEOUT;
 559
 560         /* allocate the ASQ */
 561         ret_code = i40e_init_asq(hw);
 562         if (ret_code)
 563                 goto init_adminq_destroy_locks;
 564
 565         /* allocate the ARQ */
 566         ret_code = i40e_init_arq(hw);
 567         if (ret_code)
 568                 goto init_adminq_free_asq;
 569
 570         /* success! */
 571         goto init_adminq_exit;
 572
 573 init_adminq_free_asq:
 574         i40e_shutdown_asq(hw);
 575 init_adminq_destroy_locks:
 576
 577 init_adminq_exit:
 578         return ret_code;
 579 }
 580
 581 /**
 582  *  i40evf_shutdown_adminq - shutdown routine for the Admin Queue
 583  *  @hw: pointer to the hardware structure
 584  **/
 585 i40e_status i40evf_shutdown_adminq(struct i40e_hw *hw)
 586 {
 587         i40e_status ret_code = 0;
 588
 589         if (i40evf_check_asq_alive(hw))
 590                 i40evf_aq_queue_shutdown(hw, true);
 591
 592         i40e_shutdown_asq(hw);
 593         i40e_shutdown_arq(hw);
 594
 595         if (hw->nvm_buff.va)
 596                 i40e_free_virt_mem(hw, &hw->nvm_buff);
 597
 598         return ret_code;
 599 }
 600
 601 /**
 602  *  i40e_clean_asq - cleans Admin send queue
 603  *  @hw: pointer to the hardware structure
 604  *
 605  *  returns the number of free desc
 606  **/
 607 static u16 i40e_clean_asq(struct i40e_hw *hw)
 608 {
 609         struct i40e_adminq_ring *asq = &(hw->aq.asq);
 610         struct i40e_asq_cmd_details *details;
 611         u16 ntc = asq->next_to_clean;
 612         struct i40e_aq_desc desc_cb;
 613         struct i40e_aq_desc *desc;
 614
 615         desc = I40E_ADMINQ_DESC(*asq, ntc);
 616         details = I40E_ADMINQ_DETAILS(*asq, ntc);
 617         while (rd32(hw, hw->aq.asq.head) != ntc) {
 618                 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
 619                            "ntc %d head %d.\n", ntc, rd32(hw, hw->aq.asq.head));
 620
 621                 if (details->callback) {
 622                         I40E_ADMINQ_CALLBACK cb_func =
 623                                         (I40E_ADMINQ_CALLBACK)details->callback;
 624                         desc_cb = *desc;
 625                         cb_func(hw, &desc_cb);
 626                 }
 627                 memset((void *)desc, 0, sizeof(struct i40e_aq_desc));
 628                 memset((void *)details, 0,
 629                        sizeof(struct i40e_asq_cmd_details));
 630                 ntc++;
 631                 if (ntc == asq->count)
 632                         ntc = 0;
 633                 desc = I40E_ADMINQ_DESC(*asq, ntc);
 634                 details = I40E_ADMINQ_DETAILS(*asq, ntc);
 635         }
 636
 637         asq->next_to_clean = ntc;
 638
 639         return I40E_DESC_UNUSED(asq);
 640 }
 641
 642 /**
 643  *  i40evf_asq_done - check if FW has processed the Admin Send Queue
 644  *  @hw: pointer to the hw struct
 645  *
 646  *  Returns true if the firmware has processed all descriptors on the
 647  *  admin send queue. Returns false if there are still requests pending.
 648  **/
 649 bool i40evf_asq_done(struct i40e_hw *hw)
 650 {
 651         /* AQ designers suggest use of head for better
 652          * timing reliability than DD bit
 653          */
 654         return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use;
 655
 656 }
 657
 658 /**
 659  *  i40evf_asq_send_command - send command to Admin Queue
 660  *  @hw: pointer to the hw struct
 661  *  @desc: prefilled descriptor describing the command (non DMA mem)
 662  *  @buff: buffer to use for indirect commands
 663  *  @buff_size: size of buffer for indirect commands
 664  *  @cmd_details: pointer to command details structure
 665  *
 666  *  This is the main send command driver routine for the Admin Queue send
 667  *  queue.  It runs the queue, cleans the queue, etc
 668  **/
 669 i40e_status i40evf_asq_send_command(struct i40e_hw *hw,
 670                                 struct i40e_aq_desc *desc,
 671                                 void *buff, /* can be NULL */
 672                                 u16  buff_size,
 673                                 struct i40e_asq_cmd_details *cmd_details)
 674 {
 675         i40e_status status = 0;
 676         struct i40e_dma_mem *dma_buff = NULL;
 677         struct i40e_asq_cmd_details *details;
 678         struct i40e_aq_desc *desc_on_ring;
 679         bool cmd_completed = false;
 680         u16  retval = 0;
 681         u32  val = 0;
 682
 683         mutex_lock(&hw->aq.asq_mutex);
 684
 685         if (hw->aq.asq.count == 0) {
 686                 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
 687                            "AQTX: Admin queue not initialized.\n");
 688                 status = I40E_ERR_QUEUE_EMPTY;
 689                 goto asq_send_command_error;
 690         }
 691
 692         hw->aq.asq_last_status = I40E_AQ_RC_OK;
 693
 694         val = rd32(hw, hw->aq.asq.head);
 695         if (val >= hw->aq.num_asq_entries) {
 696                 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
 697                            "AQTX: head overrun at %d\n", val);
 698                 status = I40E_ERR_QUEUE_EMPTY;
 699                 goto asq_send_command_error;
 700         }
 701
 702         details = I40E_ADMINQ_DETAILS(hw->aq.asq, hw->aq.asq.next_to_use);
 703         if (cmd_details) {
 704                 *details = *cmd_details;
 705
 706                 /* If the cmd_details are defined copy the cookie.  The
 707                  * cpu_to_le32 is not needed here because the data is ignored
 708                  * by the FW, only used by the driver
 709                  */
 710                 if (details->cookie) {
 711                         desc->cookie_high =
 712                                 cpu_to_le32(upper_32_bits(details->cookie));
 713                         desc->cookie_low =
 714                                 cpu_to_le32(lower_32_bits(details->cookie));
 715                 }
 716         } else {
 717                 memset(details, 0, sizeof(struct i40e_asq_cmd_details));
 718         }
 719
 720         /* clear requested flags and then set additional flags if defined */
 721         desc->flags &= ~cpu_to_le16(details->flags_dis);
 722         desc->flags |= cpu_to_le16(details->flags_ena);
 723
 724         if (buff_size > hw->aq.asq_buf_size) {
 725                 i40e_debug(hw,
 726                            I40E_DEBUG_AQ_MESSAGE,
 727                            "AQTX: Invalid buffer size: %d.\n",
 728                            buff_size);
 729                 status = I40E_ERR_INVALID_SIZE;
 730                 goto asq_send_command_error;
 731         }
 732
 733         if (details->postpone && !details->async) {
 734                 i40e_debug(hw,
 735                            I40E_DEBUG_AQ_MESSAGE,
 736                            "AQTX: Async flag not set along with postpone flag");
 737                 status = I40E_ERR_PARAM;
 738                 goto asq_send_command_error;
 739         }
 740
 741         /* call clean and check queue available function to reclaim the
 742          * descriptors that were processed by FW, the function returns the
 743          * number of desc available
 744          */
 745         /* the clean function called here could be called in a separate thread
 746          * in case of asynchronous completions
 747          */
 748         if (i40e_clean_asq(hw) == 0) {
 749                 i40e_debug(hw,
 750                            I40E_DEBUG_AQ_MESSAGE,
 751                            "AQTX: Error queue is full.\n");
 752                 status = I40E_ERR_ADMIN_QUEUE_FULL;
 753                 goto asq_send_command_error;
 754         }
 755
 756         /* initialize the temp desc pointer with the right desc */
 757         desc_on_ring = I40E_ADMINQ_DESC(hw->aq.asq, hw->aq.asq.next_to_use);
 758
 759         /* if the desc is available copy the temp desc to the right place */
 760         *desc_on_ring = *desc;
 761
 762         /* if buff is not NULL assume indirect command */
 763         if (buff != NULL) {
 764                 dma_buff = &(hw->aq.asq.r.asq_bi[hw->aq.asq.next_to_use]);
 765                 /* copy the user buff into the respective DMA buff */
 766                 memcpy(dma_buff->va, buff, buff_size);
 767                 desc_on_ring->datalen = cpu_to_le16(buff_size);
 768
 769                 /* Update the address values in the desc with the pa value
 770                  * for respective buffer
 771                  */
 772                 desc_on_ring->params.external.addr_high =
 773                                 cpu_to_le32(upper_32_bits(dma_buff->pa));
 774                 desc_on_ring->params.external.addr_low =
 775                                 cpu_to_le32(lower_32_bits(dma_buff->pa));
 776         }
 777
 778         /* bump the tail */
 779         i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQTX: desc and buffer:\n");
 780         i40evf_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc_on_ring,
 781                         buff, buff_size);
 782         (hw->aq.asq.next_to_use)++;
 783         if (hw->aq.asq.next_to_use == hw->aq.asq.count)
 784                 hw->aq.asq.next_to_use = 0;
 785         if (!details->postpone)
 786                 wr32(hw, hw->aq.asq.tail, hw->aq.asq.next_to_use);
 787
 788         /* if cmd_details are not defined or async flag is not set,
 789          * we need to wait for desc write back
 790          */
 791         if (!details->async && !details->postpone) {
 792                 u32 total_delay = 0;
 793
 794                 do {
 795                         /* AQ designers suggest use of head for better
 796                          * timing reliability than DD bit
 797                          */
 798                         if (i40evf_asq_done(hw))
 799                                 break;
 800                         usleep_range(1000, 2000);
 801                         total_delay++;
 802                 } while (total_delay < hw->aq.asq_cmd_timeout);
 803         }
 804
 805         /* if ready, copy the desc back to temp */
 806         if (i40evf_asq_done(hw)) {
 807                 *desc = *desc_on_ring;
 808                 if (buff != NULL)
 809                         memcpy(buff, dma_buff->va, buff_size);
 810                 retval = le16_to_cpu(desc->retval);
 811                 if (retval != 0) {
 812                         i40e_debug(hw,
 813                                    I40E_DEBUG_AQ_MESSAGE,
 814                                    "AQTX: Command completed with error 0x%X.\n",
 815                                    retval);
 816
 817                         /* strip off FW internal code */
 818                         retval &= 0xff;
 819                 }
 820                 cmd_completed = true;
 821                 if ((enum i40e_admin_queue_err)retval == I40E_AQ_RC_OK)
 822                         status = 0;
 823                 else
 824                         status = I40E_ERR_ADMIN_QUEUE_ERROR;
 825                 hw->aq.asq_last_status = (enum i40e_admin_queue_err)retval;
 826         }
 827
 828         i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
 829                    "AQTX: desc and buffer writeback:\n");
 830         i40evf_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, buff,
 831                         buff_size);
 832
 833         /* save writeback aq if requested */
 834         if (details->wb_desc)
 835                 *details->wb_desc = *desc_on_ring;
 836
 837         /* update the error if time out occurred */
 838         if ((!cmd_completed) &&
 839             (!details->async && !details->postpone)) {
 840                 i40e_debug(hw,
 841                            I40E_DEBUG_AQ_MESSAGE,
 842                            "AQTX: Writeback timeout.\n");
 843                 status = I40E_ERR_ADMIN_QUEUE_TIMEOUT;
 844         }
 845
 846 asq_send_command_error:
 847         mutex_unlock(&hw->aq.asq_mutex);
 848         return status;
 849 }
 850
 851 /**
 852  *  i40evf_fill_default_direct_cmd_desc - AQ descriptor helper function
 853  *  @desc:     pointer to the temp descriptor (non DMA mem)
 854  *  @opcode:   the opcode can be used to decide which flags to turn off or on
 855  *
 856  *  Fill the desc with default values
 857  **/
 858 void i40evf_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc,
 859                                        u16 opcode)
 860 {
 861         /* zero out the desc */
 862         memset((void *)desc, 0, sizeof(struct i40e_aq_desc));
 863         desc->opcode = cpu_to_le16(opcode);
 864         desc->flags = cpu_to_le16(I40E_AQ_FLAG_SI);
 865 }
 866
 867 /**
 868  *  i40evf_clean_arq_element
 869  *  @hw: pointer to the hw struct
 870  *  @e: event info from the receive descriptor, includes any buffers
 871  *  @pending: number of events that could be left to process
 872  *
 873  *  This function cleans one Admin Receive Queue element and returns
 874  *  the contents through e.  It can also return how many events are
 875  *  left to process through 'pending'
 876  **/
 877 i40e_status i40evf_clean_arq_element(struct i40e_hw *hw,
 878                                              struct i40e_arq_event_info *e,
 879                                              u16 *pending)
 880 {
 881         i40e_status ret_code = 0;
 882         u16 ntc = hw->aq.arq.next_to_clean;
 883         struct i40e_aq_desc *desc;
 884         struct i40e_dma_mem *bi;
 885         u16 desc_idx;
 886         u16 datalen;
 887         u16 flags;
 888         u16 ntu;
 889
 890         /* take the lock before we start messing with the ring */
 891         mutex_lock(&hw->aq.arq_mutex);
 892
 893         if (hw->aq.arq.count == 0) {
 894                 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
 895                            "AQRX: Admin queue not initialized.\n");
 896                 ret_code = I40E_ERR_QUEUE_EMPTY;
 897                 goto clean_arq_element_err;
 898         }
 899
 900         /* set next_to_use to head */
 901         ntu = (rd32(hw, hw->aq.arq.head) & I40E_VF_ARQH1_ARQH_MASK);
 902         if (ntu == ntc) {
 903                 /* nothing to do - shouldn't need to update ring's values */
 904                 ret_code = I40E_ERR_ADMIN_QUEUE_NO_WORK;
 905                 goto clean_arq_element_out;
 906         }
 907
 908         /* now clean the next descriptor */
 909         desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc);
 910         desc_idx = ntc;
 911
 912         flags = le16_to_cpu(desc->flags);
 913         if (flags & I40E_AQ_FLAG_ERR) {
 914                 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
 915                 hw->aq.arq_last_status =
 916                         (enum i40e_admin_queue_err)le16_to_cpu(desc->retval);
 917                 i40e_debug(hw,
 918                            I40E_DEBUG_AQ_MESSAGE,
 919                            "AQRX: Event received with error 0x%X.\n",
 920                            hw->aq.arq_last_status);
 921         }
 922
 923         e->desc = *desc;
 924         datalen = le16_to_cpu(desc->datalen);
 925         e->msg_len = min(datalen, e->buf_len);
 926         if (e->msg_buf != NULL && (e->msg_len != 0))
 927                 memcpy(e->msg_buf, hw->aq.arq.r.arq_bi[desc_idx].va,
 928                        e->msg_len);
 929
 930         i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQRX: desc and buffer:\n");
 931         i40evf_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, e->msg_buf,
 932                         hw->aq.arq_buf_size);
 933
 934         /* Restore the original datalen and buffer address in the desc,
 935          * FW updates datalen to indicate the event message
 936          * size
 937          */
 938         bi = &hw->aq.arq.r.arq_bi[ntc];
 939         memset((void *)desc, 0, sizeof(struct i40e_aq_desc));
 940
 941         desc->flags = cpu_to_le16(I40E_AQ_FLAG_BUF);
 942         if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF)
 943                 desc->flags |= cpu_to_le16(I40E_AQ_FLAG_LB);
 944         desc->datalen = cpu_to_le16((u16)bi->size);
 945         desc->params.external.addr_high = cpu_to_le32(upper_32_bits(bi->pa));
 946         desc->params.external.addr_low = cpu_to_le32(lower_32_bits(bi->pa));
 947
 948         /* set tail = the last cleaned desc index. */
 949         wr32(hw, hw->aq.arq.tail, ntc);
 950         /* ntc is updated to tail + 1 */
 951         ntc++;
 952         if (ntc == hw->aq.num_arq_entries)
 953                 ntc = 0;
 954         hw->aq.arq.next_to_clean = ntc;
 955         hw->aq.arq.next_to_use = ntu;
 956
 957 clean_arq_element_out:
 958         /* Set pending if needed, unlock and return */
 959         if (pending != NULL)
 960                 *pending = (ntc > ntu ? hw->aq.arq.count : 0) + (ntu - ntc);
 961
 962 clean_arq_element_err:
 963         mutex_unlock(&hw->aq.arq_mutex);
 964
 965         return ret_code;
 966 }
 967
 968 void i40evf_resume_aq(struct i40e_hw *hw)
 969 {
 970         /* Registers are reset after PF reset */
 971         hw->aq.asq.next_to_use = 0;
 972         hw->aq.asq.next_to_clean = 0;
 973
 974         i40e_config_asq_regs(hw);
 975
 976         hw->aq.arq.next_to_use = 0;
 977         hw->aq.arq.next_to_clean = 0;
 978
 979         i40e_config_arq_regs(hw);
 980 }