drivers/net/ethernet/intel/igb/e1000_82575.c

   1 /* Intel(R) Gigabit Ethernet Linux driver
   2  * Copyright(c) 2007-2014 Intel Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program; if not, see <http://www.gnu.org/licenses/>.
  15  *
  16  * The full GNU General Public License is included in this distribution in
  17  * the file called "COPYING".
  18  *
  19  * Contact Information:
  20  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  21  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  22  */
  23
  24 /* e1000_82575
  25  * e1000_82576
  26  */
  27
  28 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  29
  30 #include <linux/types.h>
  31 #include <linux/if_ether.h>
  32 #include <linux/i2c.h>
  33
  34 #include "e1000_mac.h"
  35 #include "e1000_82575.h"
  36 #include "e1000_i210.h"
  37
  38 static s32  igb_get_invariants_82575(struct e1000_hw *);
  39 static s32  igb_acquire_phy_82575(struct e1000_hw *);
  40 static void igb_release_phy_82575(struct e1000_hw *);
  41 static s32  igb_acquire_nvm_82575(struct e1000_hw *);
  42 static void igb_release_nvm_82575(struct e1000_hw *);
  43 static s32  igb_check_for_link_82575(struct e1000_hw *);
  44 static s32  igb_get_cfg_done_82575(struct e1000_hw *);
  45 static s32  igb_init_hw_82575(struct e1000_hw *);
  46 static s32  igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
  47 static s32  igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
  48 static s32  igb_read_phy_reg_82580(struct e1000_hw *, u32, u16 *);
  49 static s32  igb_write_phy_reg_82580(struct e1000_hw *, u32, u16);
  50 static s32  igb_reset_hw_82575(struct e1000_hw *);
  51 static s32  igb_reset_hw_82580(struct e1000_hw *);
  52 static s32  igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
  53 static s32  igb_set_d0_lplu_state_82580(struct e1000_hw *, bool);
  54 static s32  igb_set_d3_lplu_state_82580(struct e1000_hw *, bool);
  55 static s32  igb_setup_copper_link_82575(struct e1000_hw *);
  56 static s32  igb_setup_serdes_link_82575(struct e1000_hw *);
  57 static s32  igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
  58 static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
  59 static s32  igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
  60 static s32  igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
  61                                                  u16 *);
  62 static s32  igb_get_phy_id_82575(struct e1000_hw *);
  63 static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
  64 static bool igb_sgmii_active_82575(struct e1000_hw *);
  65 static s32  igb_reset_init_script_82575(struct e1000_hw *);
  66 static s32  igb_read_mac_addr_82575(struct e1000_hw *);
  67 static s32  igb_set_pcie_completion_timeout(struct e1000_hw *hw);
  68 static s32  igb_reset_mdicnfg_82580(struct e1000_hw *hw);
  69 static s32  igb_validate_nvm_checksum_82580(struct e1000_hw *hw);
  70 static s32  igb_update_nvm_checksum_82580(struct e1000_hw *hw);
  71 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw);
  72 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw);
  73 static const u16 e1000_82580_rxpbs_table[] = {
  74         36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
  75
  76 /**
  77  *  igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
  78  *  @hw: pointer to the HW structure
  79  *
  80  *  Called to determine if the I2C pins are being used for I2C or as an
  81  *  external MDIO interface since the two options are mutually exclusive.
  82  **/
  83 static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw)
  84 {
  85         u32 reg = 0;
  86         bool ext_mdio = false;
  87
  88         switch (hw->mac.type) {
  89         case e1000_82575:
  90         case e1000_82576:
  91                 reg = rd32(E1000_MDIC);
  92                 ext_mdio = !!(reg & E1000_MDIC_DEST);
  93                 break;
  94         case e1000_82580:
  95         case e1000_i350:
  96         case e1000_i354:
  97         case e1000_i210:
  98         case e1000_i211:
  99                 reg = rd32(E1000_MDICNFG);
 100                 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
 101                 break;
 102         default:
 103                 break;
 104         }
 105         return ext_mdio;
 106 }
 107
 108 /**
 109  *  igb_check_for_link_media_swap - Check which M88E1112 interface linked
 110  *  @hw: pointer to the HW structure
 111  *
 112  *  Poll the M88E1112 interfaces to see which interface achieved link.
 113  */
 114 static s32 igb_check_for_link_media_swap(struct e1000_hw *hw)
 115 {
 116         struct e1000_phy_info *phy = &hw->phy;
 117         s32 ret_val;
 118         u16 data;
 119         u8 port = 0;
 120
 121         /* Check the copper medium. */
 122         ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
 123         if (ret_val)
 124                 return ret_val;
 125
 126         ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
 127         if (ret_val)
 128                 return ret_val;
 129
 130         if (data & E1000_M88E1112_STATUS_LINK)
 131                 port = E1000_MEDIA_PORT_COPPER;
 132
 133         /* Check the other medium. */
 134         ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
 135         if (ret_val)
 136                 return ret_val;
 137
 138         ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
 139         if (ret_val)
 140                 return ret_val;
 141
 142         /* reset page to 0 */
 143         ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
 144         if (ret_val)
 145                 return ret_val;
 146
 147         if (data & E1000_M88E1112_STATUS_LINK)
 148                 port = E1000_MEDIA_PORT_OTHER;
 149
 150         /* Determine if a swap needs to happen. */
 151         if (port && (hw->dev_spec._82575.media_port != port)) {
 152                 hw->dev_spec._82575.media_port = port;
 153                 hw->dev_spec._82575.media_changed = true;
 154         } else {
 155                 ret_val = igb_check_for_link_82575(hw);
 156         }
 157
 158         return 0;
 159 }
 160
 161 /**
 162  *  igb_init_phy_params_82575 - Init PHY func ptrs.
 163  *  @hw: pointer to the HW structure
 164  **/
 165 static s32 igb_init_phy_params_82575(struct e1000_hw *hw)
 166 {
 167         struct e1000_phy_info *phy = &hw->phy;
 168         s32 ret_val = 0;
 169         u32 ctrl_ext;
 170
 171         if (hw->phy.media_type != e1000_media_type_copper) {
 172                 phy->type = e1000_phy_none;
 173                 goto out;
 174         }
 175
 176         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 177         phy->reset_delay_us     = 100;
 178
 179         ctrl_ext = rd32(E1000_CTRL_EXT);
 180
 181         if (igb_sgmii_active_82575(hw)) {
 182                 phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
 183                 ctrl_ext |= E1000_CTRL_I2C_ENA;
 184         } else {
 185                 phy->ops.reset = igb_phy_hw_reset;
 186                 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
 187         }
 188
 189         wr32(E1000_CTRL_EXT, ctrl_ext);
 190         igb_reset_mdicnfg_82580(hw);
 191
 192         if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) {
 193                 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
 194                 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
 195         } else {
 196                 switch (hw->mac.type) {
 197                 case e1000_82580:
 198                 case e1000_i350:
 199                 case e1000_i354:
 200                         phy->ops.read_reg = igb_read_phy_reg_82580;
 201                         phy->ops.write_reg = igb_write_phy_reg_82580;
 202                         break;
 203                 case e1000_i210:
 204                 case e1000_i211:
 205                         phy->ops.read_reg = igb_read_phy_reg_gs40g;
 206                         phy->ops.write_reg = igb_write_phy_reg_gs40g;
 207                         break;
 208                 default:
 209                         phy->ops.read_reg = igb_read_phy_reg_igp;
 210                         phy->ops.write_reg = igb_write_phy_reg_igp;
 211                 }
 212         }
 213
 214         /* set lan id */
 215         hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>
 216                         E1000_STATUS_FUNC_SHIFT;
 217
 218         /* Set phy->phy_addr and phy->id. */
 219         ret_val = igb_get_phy_id_82575(hw);
 220         if (ret_val)
 221                 return ret_val;
 222
 223         /* Verify phy id and set remaining function pointers */
 224         switch (phy->id) {
 225         case M88E1543_E_PHY_ID:
 226         case I347AT4_E_PHY_ID:
 227         case M88E1112_E_PHY_ID:
 228         case M88E1111_I_PHY_ID:
 229                 phy->type               = e1000_phy_m88;
 230                 phy->ops.check_polarity = igb_check_polarity_m88;
 231                 phy->ops.get_phy_info   = igb_get_phy_info_m88;
 232                 if (phy->id != M88E1111_I_PHY_ID)
 233                         phy->ops.get_cable_length =
 234                                          igb_get_cable_length_m88_gen2;
 235                 else
 236                         phy->ops.get_cable_length = igb_get_cable_length_m88;
 237                 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
 238                 /* Check if this PHY is confgured for media swap. */
 239                 if (phy->id == M88E1112_E_PHY_ID) {
 240                         u16 data;
 241
 242                         ret_val = phy->ops.write_reg(hw,
 243                                                      E1000_M88E1112_PAGE_ADDR,
 244                                                      2);
 245                         if (ret_val)
 246                                 goto out;
 247
 248                         ret_val = phy->ops.read_reg(hw,
 249                                                     E1000_M88E1112_MAC_CTRL_1,
 250                                                     &data);
 251                         if (ret_val)
 252                                 goto out;
 253
 254                         data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>
 255                                E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;
 256                         if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
 257                             data == E1000_M88E1112_AUTO_COPPER_BASEX)
 258                                 hw->mac.ops.check_for_link =
 259                                                 igb_check_for_link_media_swap;
 260                 }
 261                 break;
 262         case IGP03E1000_E_PHY_ID:
 263                 phy->type = e1000_phy_igp_3;
 264                 phy->ops.get_phy_info = igb_get_phy_info_igp;
 265                 phy->ops.get_cable_length = igb_get_cable_length_igp_2;
 266                 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
 267                 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
 268                 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
 269                 break;
 270         case I82580_I_PHY_ID:
 271         case I350_I_PHY_ID:
 272                 phy->type = e1000_phy_82580;
 273                 phy->ops.force_speed_duplex =
 274                                          igb_phy_force_speed_duplex_82580;
 275                 phy->ops.get_cable_length = igb_get_cable_length_82580;
 276                 phy->ops.get_phy_info = igb_get_phy_info_82580;
 277                 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
 278                 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
 279                 break;
 280         case I210_I_PHY_ID:
 281                 phy->type               = e1000_phy_i210;
 282                 phy->ops.check_polarity = igb_check_polarity_m88;
 283                 phy->ops.get_phy_info   = igb_get_phy_info_m88;
 284                 phy->ops.get_cable_length = igb_get_cable_length_m88_gen2;
 285                 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
 286                 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
 287                 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
 288                 break;
 289         default:
 290                 ret_val = -E1000_ERR_PHY;
 291                 goto out;
 292         }
 293
 294 out:
 295         return ret_val;
 296 }
 297
 298 /**
 299  *  igb_init_nvm_params_82575 - Init NVM func ptrs.
 300  *  @hw: pointer to the HW structure
 301  **/
 302 static s32 igb_init_nvm_params_82575(struct e1000_hw *hw)
 303 {
 304         struct e1000_nvm_info *nvm = &hw->nvm;
 305         u32 eecd = rd32(E1000_EECD);
 306         u16 size;
 307
 308         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 309                      E1000_EECD_SIZE_EX_SHIFT);
 310
 311         /* Added to a constant, "size" becomes the left-shift value
 312          * for setting word_size.
 313          */
 314         size += NVM_WORD_SIZE_BASE_SHIFT;
 315
 316         /* Just in case size is out of range, cap it to the largest
 317          * EEPROM size supported
 318          */
 319         if (size > 15)
 320                 size = 15;
 321
 322         nvm->word_size = 1 << size;
 323         nvm->opcode_bits = 8;
 324         nvm->delay_usec = 1;
 325
 326         switch (nvm->override) {
 327         case e1000_nvm_override_spi_large:
 328                 nvm->page_size = 32;
 329                 nvm->address_bits = 16;
 330                 break;
 331         case e1000_nvm_override_spi_small:
 332                 nvm->page_size = 8;
 333                 nvm->address_bits = 8;
 334                 break;
 335         default:
 336                 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 337                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
 338                                     16 : 8;
 339                 break;
 340         }
 341         if (nvm->word_size == (1 << 15))
 342                 nvm->page_size = 128;
 343
 344         nvm->type = e1000_nvm_eeprom_spi;
 345
 346         /* NVM Function Pointers */
 347         nvm->ops.acquire = igb_acquire_nvm_82575;
 348         nvm->ops.release = igb_release_nvm_82575;
 349         nvm->ops.write = igb_write_nvm_spi;
 350         nvm->ops.validate = igb_validate_nvm_checksum;
 351         nvm->ops.update = igb_update_nvm_checksum;
 352         if (nvm->word_size < (1 << 15))
 353                 nvm->ops.read = igb_read_nvm_eerd;
 354         else
 355                 nvm->ops.read = igb_read_nvm_spi;
 356
 357         /* override generic family function pointers for specific descendants */
 358         switch (hw->mac.type) {
 359         case e1000_82580:
 360                 nvm->ops.validate = igb_validate_nvm_checksum_82580;
 361                 nvm->ops.update = igb_update_nvm_checksum_82580;
 362                 break;
 363         case e1000_i354:
 364         case e1000_i350:
 365                 nvm->ops.validate = igb_validate_nvm_checksum_i350;
 366                 nvm->ops.update = igb_update_nvm_checksum_i350;
 367                 break;
 368         default:
 369                 break;
 370         }
 371
 372         return 0;
 373 }
 374
 375 /**
 376  *  igb_init_mac_params_82575 - Init MAC func ptrs.
 377  *  @hw: pointer to the HW structure
 378  **/
 379 static s32 igb_init_mac_params_82575(struct e1000_hw *hw)
 380 {
 381         struct e1000_mac_info *mac = &hw->mac;
 382         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
 383
 384         /* Set mta register count */
 385         mac->mta_reg_count = 128;
 386         /* Set rar entry count */
 387         switch (mac->type) {
 388         case e1000_82576:
 389                 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
 390                 break;
 391         case e1000_82580:
 392                 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
 393                 break;
 394         case e1000_i350:
 395         case e1000_i354:
 396                 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
 397                 break;
 398         default:
 399                 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
 400                 break;
 401         }
 402         /* reset */
 403         if (mac->type >= e1000_82580)
 404                 mac->ops.reset_hw = igb_reset_hw_82580;
 405         else
 406                 mac->ops.reset_hw = igb_reset_hw_82575;
 407
 408         if (mac->type >= e1000_i210) {
 409                 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_i210;
 410                 mac->ops.release_swfw_sync = igb_release_swfw_sync_i210;
 411
 412         } else {
 413                 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_82575;
 414                 mac->ops.release_swfw_sync = igb_release_swfw_sync_82575;
 415         }
 416
 417         /* Set if part includes ASF firmware */
 418         mac->asf_firmware_present = true;
 419         /* Set if manageability features are enabled. */
 420         mac->arc_subsystem_valid =
 421                 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
 422                         ? true : false;
 423         /* enable EEE on i350 parts and later parts */
 424         if (mac->type >= e1000_i350)
 425                 dev_spec->eee_disable = false;
 426         else
 427                 dev_spec->eee_disable = true;
 428         /* Allow a single clear of the SW semaphore on I210 and newer */
 429         if (mac->type >= e1000_i210)
 430                 dev_spec->clear_semaphore_once = true;
 431         /* physical interface link setup */
 432         mac->ops.setup_physical_interface =
 433                 (hw->phy.media_type == e1000_media_type_copper)
 434                         ? igb_setup_copper_link_82575
 435                         : igb_setup_serdes_link_82575;
 436
 437         if (mac->type == e1000_82580) {
 438                 switch (hw->device_id) {
 439                 /* feature not supported on these id's */
 440                 case E1000_DEV_ID_DH89XXCC_SGMII:
 441                 case E1000_DEV_ID_DH89XXCC_SERDES:
 442                 case E1000_DEV_ID_DH89XXCC_BACKPLANE:
 443                 case E1000_DEV_ID_DH89XXCC_SFP:
 444                         break;
 445                 default:
 446                         hw->dev_spec._82575.mas_capable = true;
 447                         break;
 448                 }
 449         }
 450         return 0;
 451 }
 452
 453 /**
 454  *  igb_set_sfp_media_type_82575 - derives SFP module media type.
 455  *  @hw: pointer to the HW structure
 456  *
 457  *  The media type is chosen based on SFP module.
 458  *  compatibility flags retrieved from SFP ID EEPROM.
 459  **/
 460 static s32 igb_set_sfp_media_type_82575(struct e1000_hw *hw)
 461 {
 462         s32 ret_val = E1000_ERR_CONFIG;
 463         u32 ctrl_ext = 0;
 464         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
 465         struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags;
 466         u8 tranceiver_type = 0;
 467         s32 timeout = 3;
 468
 469         /* Turn I2C interface ON and power on sfp cage */
 470         ctrl_ext = rd32(E1000_CTRL_EXT);
 471         ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
 472         wr32(E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
 473
 474         wrfl();
 475
 476         /* Read SFP module data */
 477         while (timeout) {
 478                 ret_val = igb_read_sfp_data_byte(hw,
 479                         E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
 480                         &tranceiver_type);
 481                 if (ret_val == 0)
 482                         break;
 483                 msleep(100);
 484                 timeout--;
 485         }
 486         if (ret_val != 0)
 487                 goto out;
 488
 489         ret_val = igb_read_sfp_data_byte(hw,
 490                         E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
 491                         (u8 *)eth_flags);
 492         if (ret_val != 0)
 493                 goto out;
 494
 495         /* Check if there is some SFP module plugged and powered */
 496         if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
 497             (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
 498                 dev_spec->module_plugged = true;
 499                 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
 500                         hw->phy.media_type = e1000_media_type_internal_serdes;
 501                 } else if (eth_flags->e100_base_fx) {
 502                         dev_spec->sgmii_active = true;
 503                         hw->phy.media_type = e1000_media_type_internal_serdes;
 504                 } else if (eth_flags->e1000_base_t) {
 505                         dev_spec->sgmii_active = true;
 506                         hw->phy.media_type = e1000_media_type_copper;
 507                 } else {
 508                         hw->phy.media_type = e1000_media_type_unknown;
 509                         hw_dbg("PHY module has not been recognized\n");
 510                         goto out;
 511                 }
 512         } else {
 513                 hw->phy.media_type = e1000_media_type_unknown;
 514         }
 515         ret_val = 0;
 516 out:
 517         /* Restore I2C interface setting */
 518         wr32(E1000_CTRL_EXT, ctrl_ext);
 519         return ret_val;
 520 }
 521
 522 static s32 igb_get_invariants_82575(struct e1000_hw *hw)
 523 {
 524         struct e1000_mac_info *mac = &hw->mac;
 525         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
 526         s32 ret_val;
 527         u32 ctrl_ext = 0;
 528         u32 link_mode = 0;
 529
 530         switch (hw->device_id) {
 531         case E1000_DEV_ID_82575EB_COPPER:
 532         case E1000_DEV_ID_82575EB_FIBER_SERDES:
 533         case E1000_DEV_ID_82575GB_QUAD_COPPER:
 534                 mac->type = e1000_82575;
 535                 break;
 536         case E1000_DEV_ID_82576:
 537         case E1000_DEV_ID_82576_NS:
 538         case E1000_DEV_ID_82576_NS_SERDES:
 539         case E1000_DEV_ID_82576_FIBER:
 540         case E1000_DEV_ID_82576_SERDES:
 541         case E1000_DEV_ID_82576_QUAD_COPPER:
 542         case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
 543         case E1000_DEV_ID_82576_SERDES_QUAD:
 544                 mac->type = e1000_82576;
 545                 break;
 546         case E1000_DEV_ID_82580_COPPER:
 547         case E1000_DEV_ID_82580_FIBER:
 548         case E1000_DEV_ID_82580_QUAD_FIBER:
 549         case E1000_DEV_ID_82580_SERDES:
 550         case E1000_DEV_ID_82580_SGMII:
 551         case E1000_DEV_ID_82580_COPPER_DUAL:
 552         case E1000_DEV_ID_DH89XXCC_SGMII:
 553         case E1000_DEV_ID_DH89XXCC_SERDES:
 554         case E1000_DEV_ID_DH89XXCC_BACKPLANE:
 555         case E1000_DEV_ID_DH89XXCC_SFP:
 556                 mac->type = e1000_82580;
 557                 break;
 558         case E1000_DEV_ID_I350_COPPER:
 559         case E1000_DEV_ID_I350_FIBER:
 560         case E1000_DEV_ID_I350_SERDES:
 561         case E1000_DEV_ID_I350_SGMII:
 562                 mac->type = e1000_i350;
 563                 break;
 564         case E1000_DEV_ID_I210_COPPER:
 565         case E1000_DEV_ID_I210_FIBER:
 566         case E1000_DEV_ID_I210_SERDES:
 567         case E1000_DEV_ID_I210_SGMII:
 568         case E1000_DEV_ID_I210_COPPER_FLASHLESS:
 569         case E1000_DEV_ID_I210_SERDES_FLASHLESS:
 570                 mac->type = e1000_i210;
 571                 break;
 572         case E1000_DEV_ID_I211_COPPER:
 573                 mac->type = e1000_i211;
 574                 break;
 575         case E1000_DEV_ID_I354_BACKPLANE_1GBPS:
 576         case E1000_DEV_ID_I354_SGMII:
 577         case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS:
 578                 mac->type = e1000_i354;
 579                 break;
 580         default:
 581                 return -E1000_ERR_MAC_INIT;
 582         }
 583
 584         /* Set media type */
 585         /* The 82575 uses bits 22:23 for link mode. The mode can be changed
 586          * based on the EEPROM. We cannot rely upon device ID. There
 587          * is no distinguishable difference between fiber and internal
 588          * SerDes mode on the 82575. There can be an external PHY attached
 589          * on the SGMII interface. For this, we'll set sgmii_active to true.
 590          */
 591         hw->phy.media_type = e1000_media_type_copper;
 592         dev_spec->sgmii_active = false;
 593         dev_spec->module_plugged = false;
 594
 595         ctrl_ext = rd32(E1000_CTRL_EXT);
 596
 597         link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
 598         switch (link_mode) {
 599         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
 600                 hw->phy.media_type = e1000_media_type_internal_serdes;
 601                 break;
 602         case E1000_CTRL_EXT_LINK_MODE_SGMII:
 603                 /* Get phy control interface type set (MDIO vs. I2C)*/
 604                 if (igb_sgmii_uses_mdio_82575(hw)) {
 605                         hw->phy.media_type = e1000_media_type_copper;
 606                         dev_spec->sgmii_active = true;
 607                         break;
 608                 }
 609                 /* fall through for I2C based SGMII */
 610         case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
 611                 /* read media type from SFP EEPROM */
 612                 ret_val = igb_set_sfp_media_type_82575(hw);
 613                 if ((ret_val != 0) ||
 614                     (hw->phy.media_type == e1000_media_type_unknown)) {
 615                         /* If media type was not identified then return media
 616                          * type defined by the CTRL_EXT settings.
 617                          */
 618                         hw->phy.media_type = e1000_media_type_internal_serdes;
 619
 620                         if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
 621                                 hw->phy.media_type = e1000_media_type_copper;
 622                                 dev_spec->sgmii_active = true;
 623                         }
 624
 625                         break;
 626                 }
 627
 628                 /* do not change link mode for 100BaseFX */
 629                 if (dev_spec->eth_flags.e100_base_fx)
 630                         break;
 631
 632                 /* change current link mode setting */
 633                 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
 634
 635                 if (hw->phy.media_type == e1000_media_type_copper)
 636                         ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
 637                 else
 638                         ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
 639
 640                 wr32(E1000_CTRL_EXT, ctrl_ext);
 641
 642                 break;
 643         default:
 644                 break;
 645         }
 646
 647         /* mac initialization and operations */
 648         ret_val = igb_init_mac_params_82575(hw);
 649         if (ret_val)
 650                 goto out;
 651
 652         /* NVM initialization */
 653         ret_val = igb_init_nvm_params_82575(hw);
 654         switch (hw->mac.type) {
 655         case e1000_i210:
 656         case e1000_i211:
 657                 ret_val = igb_init_nvm_params_i210(hw);
 658                 break;
 659         default:
 660                 break;
 661         }
 662
 663         if (ret_val)
 664                 goto out;
 665
 666         /* if part supports SR-IOV then initialize mailbox parameters */
 667         switch (mac->type) {
 668         case e1000_82576:
 669         case e1000_i350:
 670                 igb_init_mbx_params_pf(hw);
 671                 break;
 672         default:
 673                 break;
 674         }
 675
 676         /* setup PHY parameters */
 677         ret_val = igb_init_phy_params_82575(hw);
 678
 679 out:
 680         return ret_val;
 681 }
 682
 683 /**
 684  *  igb_acquire_phy_82575 - Acquire rights to access PHY
 685  *  @hw: pointer to the HW structure
 686  *
 687  *  Acquire access rights to the correct PHY.  This is a
 688  *  function pointer entry point called by the api module.
 689  **/
 690 static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
 691 {
 692         u16 mask = E1000_SWFW_PHY0_SM;
 693
 694         if (hw->bus.func == E1000_FUNC_1)
 695                 mask = E1000_SWFW_PHY1_SM;
 696         else if (hw->bus.func == E1000_FUNC_2)
 697                 mask = E1000_SWFW_PHY2_SM;
 698         else if (hw->bus.func == E1000_FUNC_3)
 699                 mask = E1000_SWFW_PHY3_SM;
 700
 701         return hw->mac.ops.acquire_swfw_sync(hw, mask);
 702 }
 703
 704 /**
 705  *  igb_release_phy_82575 - Release rights to access PHY
 706  *  @hw: pointer to the HW structure
 707  *
 708  *  A wrapper to release access rights to the correct PHY.  This is a
 709  *  function pointer entry point called by the api module.
 710  **/
 711 static void igb_release_phy_82575(struct e1000_hw *hw)
 712 {
 713         u16 mask = E1000_SWFW_PHY0_SM;
 714
 715         if (hw->bus.func == E1000_FUNC_1)
 716                 mask = E1000_SWFW_PHY1_SM;
 717         else if (hw->bus.func == E1000_FUNC_2)
 718                 mask = E1000_SWFW_PHY2_SM;
 719         else if (hw->bus.func == E1000_FUNC_3)
 720                 mask = E1000_SWFW_PHY3_SM;
 721
 722         hw->mac.ops.release_swfw_sync(hw, mask);
 723 }
 724
 725 /**
 726  *  igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
 727  *  @hw: pointer to the HW structure
 728  *  @offset: register offset to be read
 729  *  @data: pointer to the read data
 730  *
 731  *  Reads the PHY register at offset using the serial gigabit media independent
 732  *  interface and stores the retrieved information in data.
 733  **/
 734 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 735                                           u16 *data)
 736 {
 737         s32 ret_val = -E1000_ERR_PARAM;
 738
 739         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 740                 hw_dbg("PHY Address %u is out of range\n", offset);
 741                 goto out;
 742         }
 743
 744         ret_val = hw->phy.ops.acquire(hw);
 745         if (ret_val)
 746                 goto out;
 747
 748         ret_val = igb_read_phy_reg_i2c(hw, offset, data);
 749
 750         hw->phy.ops.release(hw);
 751
 752 out:
 753         return ret_val;
 754 }
 755
 756 /**
 757  *  igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
 758  *  @hw: pointer to the HW structure
 759  *  @offset: register offset to write to
 760  *  @data: data to write at register offset
 761  *
 762  *  Writes the data to PHY register at the offset using the serial gigabit
 763  *  media independent interface.
 764  **/
 765 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 766                                            u16 data)
 767 {
 768         s32 ret_val = -E1000_ERR_PARAM;
 769
 770
 771         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 772                 hw_dbg("PHY Address %d is out of range\n", offset);
 773                 goto out;
 774         }
 775
 776         ret_val = hw->phy.ops.acquire(hw);
 777         if (ret_val)
 778                 goto out;
 779
 780         ret_val = igb_write_phy_reg_i2c(hw, offset, data);
 781
 782         hw->phy.ops.release(hw);
 783
 784 out:
 785         return ret_val;
 786 }
 787
 788 /**
 789  *  igb_get_phy_id_82575 - Retrieve PHY addr and id
 790  *  @hw: pointer to the HW structure
 791  *
 792  *  Retrieves the PHY address and ID for both PHY's which do and do not use
 793  *  sgmi interface.
 794  **/
 795 static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
 796 {
 797         struct e1000_phy_info *phy = &hw->phy;
 798         s32  ret_val = 0;
 799         u16 phy_id;
 800         u32 ctrl_ext;
 801         u32 mdic;
 802
 803         /* Extra read required for some PHY's on i354 */
 804         if (hw->mac.type == e1000_i354)
 805                 igb_get_phy_id(hw);
 806
 807         /* For SGMII PHYs, we try the list of possible addresses until
 808          * we find one that works.  For non-SGMII PHYs
 809          * (e.g. integrated copper PHYs), an address of 1 should
 810          * work.  The result of this function should mean phy->phy_addr
 811          * and phy->id are set correctly.
 812          */
 813         if (!(igb_sgmii_active_82575(hw))) {
 814                 phy->addr = 1;
 815                 ret_val = igb_get_phy_id(hw);
 816                 goto out;
 817         }
 818
 819         if (igb_sgmii_uses_mdio_82575(hw)) {
 820                 switch (hw->mac.type) {
 821                 case e1000_82575:
 822                 case e1000_82576:
 823                         mdic = rd32(E1000_MDIC);
 824                         mdic &= E1000_MDIC_PHY_MASK;
 825                         phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
 826                         break;
 827                 case e1000_82580:
 828                 case e1000_i350:
 829                 case e1000_i354:
 830                 case e1000_i210:
 831                 case e1000_i211:
 832                         mdic = rd32(E1000_MDICNFG);
 833                         mdic &= E1000_MDICNFG_PHY_MASK;
 834                         phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
 835                         break;
 836                 default:
 837                         ret_val = -E1000_ERR_PHY;
 838                         goto out;
 839                 }
 840                 ret_val = igb_get_phy_id(hw);
 841                 goto out;
 842         }
 843
 844         /* Power on sgmii phy if it is disabled */
 845         ctrl_ext = rd32(E1000_CTRL_EXT);
 846         wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
 847         wrfl();
 848         msleep(300);
 849
 850         /* The address field in the I2CCMD register is 3 bits and 0 is invalid.
 851          * Therefore, we need to test 1-7
 852          */
 853         for (phy->addr = 1; phy->addr < 8; phy->addr++) {
 854                 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
 855                 if (ret_val == 0) {
 856                         hw_dbg("Vendor ID 0x%08X read at address %u\n",
 857                                phy_id, phy->addr);
 858                         /* At the time of this writing, The M88 part is
 859                          * the only supported SGMII PHY product.
 860                          */
 861                         if (phy_id == M88_VENDOR)
 862                                 break;
 863                 } else {
 864                         hw_dbg("PHY address %u was unreadable\n", phy->addr);
 865                 }
 866         }
 867
 868         /* A valid PHY type couldn't be found. */
 869         if (phy->addr == 8) {
 870                 phy->addr = 0;
 871                 ret_val = -E1000_ERR_PHY;
 872                 goto out;
 873         } else {
 874                 ret_val = igb_get_phy_id(hw);
 875         }
 876
 877         /* restore previous sfp cage power state */
 878         wr32(E1000_CTRL_EXT, ctrl_ext);
 879
 880 out:
 881         return ret_val;
 882 }
 883
 884 /**
 885  *  igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
 886  *  @hw: pointer to the HW structure
 887  *
 888  *  Resets the PHY using the serial gigabit media independent interface.
 889  **/
 890 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
 891 {
 892         s32 ret_val;
 893
 894         /* This isn't a true "hard" reset, but is the only reset
 895          * available to us at this time.
 896          */
 897
 898         hw_dbg("Soft resetting SGMII attached PHY...\n");
 899
 900         /* SFP documentation requires the following to configure the SPF module
 901          * to work on SGMII.  No further documentation is given.
 902          */
 903         ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
 904         if (ret_val)
 905                 goto out;
 906
 907         ret_val = igb_phy_sw_reset(hw);
 908
 909 out:
 910         return ret_val;
 911 }
 912
 913 /**
 914  *  igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
 915  *  @hw: pointer to the HW structure
 916  *  @active: true to enable LPLU, false to disable
 917  *
 918  *  Sets the LPLU D0 state according to the active flag.  When
 919  *  activating LPLU this function also disables smart speed
 920  *  and vice versa.  LPLU will not be activated unless the
 921  *  device autonegotiation advertisement meets standards of
 922  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 923  *  This is a function pointer entry point only called by
 924  *  PHY setup routines.
 925  **/
 926 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
 927 {
 928         struct e1000_phy_info *phy = &hw->phy;
 929         s32 ret_val;
 930         u16 data;
 931
 932         ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
 933         if (ret_val)
 934                 goto out;
 935
 936         if (active) {
 937                 data |= IGP02E1000_PM_D0_LPLU;
 938                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 939                                                  data);
 940                 if (ret_val)
 941                         goto out;
 942
 943                 /* When LPLU is enabled, we should disable SmartSpeed */
 944                 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 945                                                 &data);
 946                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 947                 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 948                                                  data);
 949                 if (ret_val)
 950                         goto out;
 951         } else {
 952                 data &= ~IGP02E1000_PM_D0_LPLU;
 953                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 954                                                  data);
 955                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 956                  * during Dx states where the power conservation is most
 957                  * important.  During driver activity we should enable
 958                  * SmartSpeed, so performance is maintained.
 959                  */
 960                 if (phy->smart_speed == e1000_smart_speed_on) {
 961                         ret_val = phy->ops.read_reg(hw,
 962                                         IGP01E1000_PHY_PORT_CONFIG, &data);
 963                         if (ret_val)
 964                                 goto out;
 965
 966                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 967                         ret_val = phy->ops.write_reg(hw,
 968                                         IGP01E1000_PHY_PORT_CONFIG, data);
 969                         if (ret_val)
 970                                 goto out;
 971                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 972                         ret_val = phy->ops.read_reg(hw,
 973                                         IGP01E1000_PHY_PORT_CONFIG, &data);
 974                         if (ret_val)
 975                                 goto out;
 976
 977                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 978                         ret_val = phy->ops.write_reg(hw,
 979                                         IGP01E1000_PHY_PORT_CONFIG, data);
 980                         if (ret_val)
 981                                 goto out;
 982                 }
 983         }
 984
 985 out:
 986         return ret_val;
 987 }
 988
 989 /**
 990  *  igb_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
 991  *  @hw: pointer to the HW structure
 992  *  @active: true to enable LPLU, false to disable
 993  *
 994  *  Sets the LPLU D0 state according to the active flag.  When
 995  *  activating LPLU this function also disables smart speed
 996  *  and vice versa.  LPLU will not be activated unless the
 997  *  device autonegotiation advertisement meets standards of
 998  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 999  *  This is a function pointer entry point only called by
1000  *  PHY setup routines.
1001  **/
1002 static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
1003 {
1004         struct e1000_phy_info *phy = &hw->phy;
1005         u16 data;
1006
1007         data = rd32(E1000_82580_PHY_POWER_MGMT);
1008
1009         if (active) {
1010                 data |= E1000_82580_PM_D0_LPLU;
1011
1012                 /* When LPLU is enabled, we should disable SmartSpeed */
1013                 data &= ~E1000_82580_PM_SPD;
1014         } else {
1015                 data &= ~E1000_82580_PM_D0_LPLU;
1016
1017                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1018                  * during Dx states where the power conservation is most
1019                  * important.  During driver activity we should enable
1020                  * SmartSpeed, so performance is maintained.
1021                  */
1022                 if (phy->smart_speed == e1000_smart_speed_on)
1023                         data |= E1000_82580_PM_SPD;
1024                 else if (phy->smart_speed == e1000_smart_speed_off)
1025                         data &= ~E1000_82580_PM_SPD; }
1026
1027         wr32(E1000_82580_PHY_POWER_MGMT, data);
1028         return 0;
1029 }
1030
1031 /**
1032  *  igb_set_d3_lplu_state_82580 - Sets low power link up state for D3
1033  *  @hw: pointer to the HW structure
1034  *  @active: boolean used to enable/disable lplu
1035  *
1036  *  Success returns 0, Failure returns 1
1037  *
1038  *  The low power link up (lplu) state is set to the power management level D3
1039  *  and SmartSpeed is disabled when active is true, else clear lplu for D3
1040  *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU
1041  *  is used during Dx states where the power conservation is most important.
1042  *  During driver activity, SmartSpeed should be enabled so performance is
1043  *  maintained.
1044  **/
1045 static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
1046 {
1047         struct e1000_phy_info *phy = &hw->phy;
1048         u16 data;
1049
1050         data = rd32(E1000_82580_PHY_POWER_MGMT);
1051
1052         if (!active) {
1053                 data &= ~E1000_82580_PM_D3_LPLU;
1054                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1055                  * during Dx states where the power conservation is most
1056                  * important.  During driver activity we should enable
1057                  * SmartSpeed, so performance is maintained.
1058                  */
1059                 if (phy->smart_speed == e1000_smart_speed_on)
1060                         data |= E1000_82580_PM_SPD;
1061                 else if (phy->smart_speed == e1000_smart_speed_off)
1062                         data &= ~E1000_82580_PM_SPD;
1063         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1064                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1065                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1066                 data |= E1000_82580_PM_D3_LPLU;
1067                 /* When LPLU is enabled, we should disable SmartSpeed */
1068                 data &= ~E1000_82580_PM_SPD;
1069         }
1070
1071         wr32(E1000_82580_PHY_POWER_MGMT, data);
1072         return 0;
1073 }
1074
1075 /**
1076  *  igb_acquire_nvm_82575 - Request for access to EEPROM
1077  *  @hw: pointer to the HW structure
1078  *
1079  *  Acquire the necessary semaphores for exclusive access to the EEPROM.
1080  *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
1081  *  Return successful if access grant bit set, else clear the request for
1082  *  EEPROM access and return -E1000_ERR_NVM (-1).
1083  **/
1084 static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
1085 {
1086         s32 ret_val;
1087
1088         ret_val = hw->mac.ops.acquire_swfw_sync(hw, E1000_SWFW_EEP_SM);
1089         if (ret_val)
1090                 goto out;
1091
1092         ret_val = igb_acquire_nvm(hw);
1093
1094         if (ret_val)
1095                 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
1096
1097 out:
1098         return ret_val;
1099 }
1100
1101 /**
1102  *  igb_release_nvm_82575 - Release exclusive access to EEPROM
1103  *  @hw: pointer to the HW structure
1104  *
1105  *  Stop any current commands to the EEPROM and clear the EEPROM request bit,
1106  *  then release the semaphores acquired.
1107  **/
1108 static void igb_release_nvm_82575(struct e1000_hw *hw)
1109 {
1110         igb_release_nvm(hw);
1111         hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
1112 }
1113
1114 /**
1115  *  igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
1116  *  @hw: pointer to the HW structure
1117  *  @mask: specifies which semaphore to acquire
1118  *
1119  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
1120  *  will also specify which port we're acquiring the lock for.
1121  **/
1122 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1123 {
1124         u32 swfw_sync;
1125         u32 swmask = mask;
1126         u32 fwmask = mask << 16;
1127         s32 ret_val = 0;
1128         s32 i = 0, timeout = 200;
1129
1130         while (i < timeout) {
1131                 if (igb_get_hw_semaphore(hw)) {
1132                         ret_val = -E1000_ERR_SWFW_SYNC;
1133                         goto out;
1134                 }
1135
1136                 swfw_sync = rd32(E1000_SW_FW_SYNC);
1137                 if (!(swfw_sync & (fwmask | swmask)))
1138                         break;
1139
1140                 /* Firmware currently using resource (fwmask)
1141                  * or other software thread using resource (swmask)
1142                  */
1143                 igb_put_hw_semaphore(hw);
1144                 mdelay(5);
1145                 i++;
1146         }
1147
1148         if (i == timeout) {
1149                 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
1150                 ret_val = -E1000_ERR_SWFW_SYNC;
1151                 goto out;
1152         }
1153
1154         swfw_sync |= swmask;
1155         wr32(E1000_SW_FW_SYNC, swfw_sync);
1156
1157         igb_put_hw_semaphore(hw);
1158
1159 out:
1160         return ret_val;
1161 }
1162
1163 /**
1164  *  igb_release_swfw_sync_82575 - Release SW/FW semaphore
1165  *  @hw: pointer to the HW structure
1166  *  @mask: specifies which semaphore to acquire
1167  *
1168  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
1169  *  will also specify which port we're releasing the lock for.
1170  **/
1171 static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1172 {
1173         u32 swfw_sync;
1174
1175         while (igb_get_hw_semaphore(hw) != 0)
1176                 ; /* Empty */
1177
1178         swfw_sync = rd32(E1000_SW_FW_SYNC);
1179         swfw_sync &= ~mask;
1180         wr32(E1000_SW_FW_SYNC, swfw_sync);
1181
1182         igb_put_hw_semaphore(hw);
1183 }
1184
1185 /**
1186  *  igb_get_cfg_done_82575 - Read config done bit
1187  *  @hw: pointer to the HW structure
1188  *
1189  *  Read the management control register for the config done bit for
1190  *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
1191  *  to read the config done bit, so an error is *ONLY* logged and returns
1192  *  0.  If we were to return with error, EEPROM-less silicon
1193  *  would not be able to be reset or change link.
1194  **/
1195 static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
1196 {
1197         s32 timeout = PHY_CFG_TIMEOUT;
1198         u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1199
1200         if (hw->bus.func == 1)
1201                 mask = E1000_NVM_CFG_DONE_PORT_1;
1202         else if (hw->bus.func == E1000_FUNC_2)
1203                 mask = E1000_NVM_CFG_DONE_PORT_2;
1204         else if (hw->bus.func == E1000_FUNC_3)
1205                 mask = E1000_NVM_CFG_DONE_PORT_3;
1206
1207         while (timeout) {
1208                 if (rd32(E1000_EEMNGCTL) & mask)
1209                         break;
1210                 usleep_range(1000, 2000);
1211                 timeout--;
1212         }
1213         if (!timeout)
1214                 hw_dbg("MNG configuration cycle has not completed.\n");
1215
1216         /* If EEPROM is not marked present, init the PHY manually */
1217         if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
1218             (hw->phy.type == e1000_phy_igp_3))
1219                 igb_phy_init_script_igp3(hw);
1220
1221         return 0;
1222 }
1223
1224 /**
1225  *  igb_get_link_up_info_82575 - Get link speed/duplex info
1226  *  @hw: pointer to the HW structure
1227  *  @speed: stores the current speed
1228  *  @duplex: stores the current duplex
1229  *
1230  *  This is a wrapper function, if using the serial gigabit media independent
1231  *  interface, use PCS to retrieve the link speed and duplex information.
1232  *  Otherwise, use the generic function to get the link speed and duplex info.
1233  **/
1234 static s32 igb_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1235                                         u16 *duplex)
1236 {
1237         s32 ret_val;
1238
1239         if (hw->phy.media_type != e1000_media_type_copper)
1240                 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, speed,
1241                                                                duplex);
1242         else
1243                 ret_val = igb_get_speed_and_duplex_copper(hw, speed,
1244                                                                     duplex);
1245
1246         return ret_val;
1247 }
1248
1249 /**
1250  *  igb_check_for_link_82575 - Check for link
1251  *  @hw: pointer to the HW structure
1252  *
1253  *  If sgmii is enabled, then use the pcs register to determine link, otherwise
1254  *  use the generic interface for determining link.
1255  **/
1256 static s32 igb_check_for_link_82575(struct e1000_hw *hw)
1257 {
1258         s32 ret_val;
1259         u16 speed, duplex;
1260
1261         if (hw->phy.media_type != e1000_media_type_copper) {
1262                 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
1263                                                              &duplex);
1264                 /* Use this flag to determine if link needs to be checked or
1265                  * not.  If  we have link clear the flag so that we do not
1266                  * continue to check for link.
1267                  */
1268                 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1269
1270                 /* Configure Flow Control now that Auto-Neg has completed.
1271                  * First, we need to restore the desired flow control
1272                  * settings because we may have had to re-autoneg with a
1273                  * different link partner.
1274                  */
1275                 ret_val = igb_config_fc_after_link_up(hw);
1276                 if (ret_val)
1277                         hw_dbg("Error configuring flow control\n");
1278         } else {
1279                 ret_val = igb_check_for_copper_link(hw);
1280         }
1281
1282         return ret_val;
1283 }
1284
1285 /**
1286  *  igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1287  *  @hw: pointer to the HW structure
1288  **/
1289 void igb_power_up_serdes_link_82575(struct e1000_hw *hw)
1290 {
1291         u32 reg;
1292
1293
1294         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1295             !igb_sgmii_active_82575(hw))
1296                 return;
1297
1298         /* Enable PCS to turn on link */
1299         reg = rd32(E1000_PCS_CFG0);
1300         reg |= E1000_PCS_CFG_PCS_EN;
1301         wr32(E1000_PCS_CFG0, reg);
1302
1303         /* Power up the laser */
1304         reg = rd32(E1000_CTRL_EXT);
1305         reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1306         wr32(E1000_CTRL_EXT, reg);
1307
1308         /* flush the write to verify completion */
1309         wrfl();
1310         usleep_range(1000, 2000);
1311 }
1312
1313 /**
1314  *  igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1315  *  @hw: pointer to the HW structure
1316  *  @speed: stores the current speed
1317  *  @duplex: stores the current duplex
1318  *
1319  *  Using the physical coding sub-layer (PCS), retrieve the current speed and
1320  *  duplex, then store the values in the pointers provided.
1321  **/
1322 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
1323                                                 u16 *duplex)
1324 {
1325         struct e1000_mac_info *mac = &hw->mac;
1326         u32 pcs, status;
1327
1328         /* Set up defaults for the return values of this function */
1329         mac->serdes_has_link = false;
1330         *speed = 0;
1331         *duplex = 0;
1332
1333         /* Read the PCS Status register for link state. For non-copper mode,
1334          * the status register is not accurate. The PCS status register is
1335          * used instead.
1336          */
1337         pcs = rd32(E1000_PCS_LSTAT);
1338
1339         /* The link up bit determines when link is up on autoneg. The sync ok
1340          * gets set once both sides sync up and agree upon link. Stable link
1341          * can be determined by checking for both link up and link sync ok
1342          */
1343         if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
1344                 mac->serdes_has_link = true;
1345
1346                 /* Detect and store PCS speed */
1347                 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1348                         *speed = SPEED_1000;
1349                 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1350                         *speed = SPEED_100;
1351                 else
1352                         *speed = SPEED_10;
1353
1354                 /* Detect and store PCS duplex */
1355                 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1356                         *duplex = FULL_DUPLEX;
1357                 else
1358                         *duplex = HALF_DUPLEX;
1359
1360         /* Check if it is an I354 2.5Gb backplane connection. */
1361                 if (mac->type == e1000_i354) {
1362                         status = rd32(E1000_STATUS);
1363                         if ((status & E1000_STATUS_2P5_SKU) &&
1364                             !(status & E1000_STATUS_2P5_SKU_OVER)) {
1365                                 *speed = SPEED_2500;
1366                                 *duplex = FULL_DUPLEX;
1367                                 hw_dbg("2500 Mbs, ");
1368                                 hw_dbg("Full Duplex\n");
1369                         }
1370                 }
1371
1372         }
1373
1374         return 0;
1375 }
1376
1377 /**
1378  *  igb_shutdown_serdes_link_82575 - Remove link during power down
1379  *  @hw: pointer to the HW structure
1380  *
1381  *  In the case of fiber serdes, shut down optics and PCS on driver unload
1382  *  when management pass thru is not enabled.
1383  **/
1384 void igb_shutdown_serdes_link_82575(struct e1000_hw *hw)
1385 {
1386         u32 reg;
1387
1388         if (hw->phy.media_type != e1000_media_type_internal_serdes &&
1389             igb_sgmii_active_82575(hw))
1390                 return;
1391
1392         if (!igb_enable_mng_pass_thru(hw)) {
1393                 /* Disable PCS to turn off link */
1394                 reg = rd32(E1000_PCS_CFG0);
1395                 reg &= ~E1000_PCS_CFG_PCS_EN;
1396                 wr32(E1000_PCS_CFG0, reg);
1397
1398                 /* shutdown the laser */
1399                 reg = rd32(E1000_CTRL_EXT);
1400                 reg |= E1000_CTRL_EXT_SDP3_DATA;
1401                 wr32(E1000_CTRL_EXT, reg);
1402
1403                 /* flush the write to verify completion */
1404                 wrfl();
1405                 usleep_range(1000, 2000);
1406         }
1407 }
1408
1409 /**
1410  *  igb_reset_hw_82575 - Reset hardware
1411  *  @hw: pointer to the HW structure
1412  *
1413  *  This resets the hardware into a known state.  This is a
1414  *  function pointer entry point called by the api module.
1415  **/
1416 static s32 igb_reset_hw_82575(struct e1000_hw *hw)
1417 {
1418         u32 ctrl;
1419         s32 ret_val;
1420
1421         /* Prevent the PCI-E bus from sticking if there is no TLP connection
1422          * on the last TLP read/write transaction when MAC is reset.
1423          */
1424         ret_val = igb_disable_pcie_master(hw);
1425         if (ret_val)
1426                 hw_dbg("PCI-E Master disable polling has failed.\n");
1427
1428         /* set the completion timeout for interface */
1429         ret_val = igb_set_pcie_completion_timeout(hw);
1430         if (ret_val)
1431                 hw_dbg("PCI-E Set completion timeout has failed.\n");
1432
1433         hw_dbg("Masking off all interrupts\n");
1434         wr32(E1000_IMC, 0xffffffff);
1435
1436         wr32(E1000_RCTL, 0);
1437         wr32(E1000_TCTL, E1000_TCTL_PSP);
1438         wrfl();
1439
1440         usleep_range(10000, 20000);
1441
1442         ctrl = rd32(E1000_CTRL);
1443
1444         hw_dbg("Issuing a global reset to MAC\n");
1445         wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
1446
1447         ret_val = igb_get_auto_rd_done(hw);
1448         if (ret_val) {
1449                 /* When auto config read does not complete, do not
1450                  * return with an error. This can happen in situations
1451                  * where there is no eeprom and prevents getting link.
1452                  */
1453                 hw_dbg("Auto Read Done did not complete\n");
1454         }
1455
1456         /* If EEPROM is not present, run manual init scripts */
1457         if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
1458                 igb_reset_init_script_82575(hw);
1459
1460         /* Clear any pending interrupt events. */
1461         wr32(E1000_IMC, 0xffffffff);
1462         rd32(E1000_ICR);
1463
1464         /* Install any alternate MAC address into RAR0 */
1465         ret_val = igb_check_alt_mac_addr(hw);
1466
1467         return ret_val;
1468 }
1469
1470 /**
1471  *  igb_init_hw_82575 - Initialize hardware
1472  *  @hw: pointer to the HW structure
1473  *
1474  *  This inits the hardware readying it for operation.
1475  **/
1476 static s32 igb_init_hw_82575(struct e1000_hw *hw)
1477 {
1478         struct e1000_mac_info *mac = &hw->mac;
1479         s32 ret_val;
1480         u16 i, rar_count = mac->rar_entry_count;
1481
1482         if ((hw->mac.type >= e1000_i210) &&
1483             !(igb_get_flash_presence_i210(hw))) {
1484                 ret_val = igb_pll_workaround_i210(hw);
1485                 if (ret_val)
1486                         return ret_val;
1487         }
1488
1489         /* Initialize identification LED */
1490         ret_val = igb_id_led_init(hw);
1491         if (ret_val) {
1492                 hw_dbg("Error initializing identification LED\n");
1493                 /* This is not fatal and we should not stop init due to this */
1494         }
1495
1496         /* Disabling VLAN filtering */
1497         hw_dbg("Initializing the IEEE VLAN\n");
1498         if ((hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i354))
1499                 igb_clear_vfta_i350(hw);
1500         else
1501                 igb_clear_vfta(hw);
1502
1503         /* Setup the receive address */
1504         igb_init_rx_addrs(hw, rar_count);
1505
1506         /* Zero out the Multicast HASH table */
1507         hw_dbg("Zeroing the MTA\n");
1508         for (i = 0; i < mac->mta_reg_count; i++)
1509                 array_wr32(E1000_MTA, i, 0);
1510
1511         /* Zero out the Unicast HASH table */
1512         hw_dbg("Zeroing the UTA\n");
1513         for (i = 0; i < mac->uta_reg_count; i++)
1514                 array_wr32(E1000_UTA, i, 0);
1515
1516         /* Setup link and flow control */
1517         ret_val = igb_setup_link(hw);
1518
1519         /* Clear all of the statistics registers (clear on read).  It is
1520          * important that we do this after we have tried to establish link
1521          * because the symbol error count will increment wildly if there
1522          * is no link.
1523          */
1524         igb_clear_hw_cntrs_82575(hw);
1525         return ret_val;
1526 }
1527
1528 /**
1529  *  igb_setup_copper_link_82575 - Configure copper link settings
1530  *  @hw: pointer to the HW structure
1531  *
1532  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1533  *  for link, once link is established calls to configure collision distance
1534  *  and flow control are called.
1535  **/
1536 static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
1537 {
1538         u32 ctrl;
1539         s32  ret_val;
1540         u32 phpm_reg;
1541
1542         ctrl = rd32(E1000_CTRL);
1543         ctrl |= E1000_CTRL_SLU;
1544         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1545         wr32(E1000_CTRL, ctrl);
1546
1547         /* Clear Go Link Disconnect bit on supported devices */
1548         switch (hw->mac.type) {
1549         case e1000_82580:
1550         case e1000_i350:
1551         case e1000_i210:
1552         case e1000_i211:
1553                 phpm_reg = rd32(E1000_82580_PHY_POWER_MGMT);
1554                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1555                 wr32(E1000_82580_PHY_POWER_MGMT, phpm_reg);
1556                 break;
1557         default:
1558                 break;
1559         }
1560
1561         ret_val = igb_setup_serdes_link_82575(hw);
1562         if (ret_val)
1563                 goto out;
1564
1565         if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
1566                 /* allow time for SFP cage time to power up phy */
1567                 msleep(300);
1568
1569                 ret_val = hw->phy.ops.reset(hw);
1570                 if (ret_val) {
1571                         hw_dbg("Error resetting the PHY.\n");
1572                         goto out;
1573                 }
1574         }
1575         switch (hw->phy.type) {
1576         case e1000_phy_i210:
1577         case e1000_phy_m88:
1578                 switch (hw->phy.id) {
1579                 case I347AT4_E_PHY_ID:
1580                 case M88E1112_E_PHY_ID:
1581                 case M88E1543_E_PHY_ID:
1582                 case I210_I_PHY_ID:
1583                         ret_val = igb_copper_link_setup_m88_gen2(hw);
1584                         break;
1585                 default:
1586                         ret_val = igb_copper_link_setup_m88(hw);
1587                         break;
1588                 }
1589                 break;
1590         case e1000_phy_igp_3:
1591                 ret_val = igb_copper_link_setup_igp(hw);
1592                 break;
1593         case e1000_phy_82580:
1594                 ret_val = igb_copper_link_setup_82580(hw);
1595                 break;
1596         default:
1597                 ret_val = -E1000_ERR_PHY;
1598                 break;
1599         }
1600
1601         if (ret_val)
1602                 goto out;
1603
1604         ret_val = igb_setup_copper_link(hw);
1605 out:
1606         return ret_val;
1607 }
1608
1609 /**
1610  *  igb_setup_serdes_link_82575 - Setup link for serdes
1611  *  @hw: pointer to the HW structure
1612  *
1613  *  Configure the physical coding sub-layer (PCS) link.  The PCS link is
1614  *  used on copper connections where the serialized gigabit media independent
1615  *  interface (sgmii), or serdes fiber is being used.  Configures the link
1616  *  for auto-negotiation or forces speed/duplex.
1617  **/
1618 static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
1619 {
1620         u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1621         bool pcs_autoneg;
1622         s32 ret_val = 0;
1623         u16 data;
1624
1625         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1626             !igb_sgmii_active_82575(hw))
1627                 return ret_val;
1628
1629
1630         /* On the 82575, SerDes loopback mode persists until it is
1631          * explicitly turned off or a power cycle is performed.  A read to
1632          * the register does not indicate its status.  Therefore, we ensure
1633          * loopback mode is disabled during initialization.
1634          */
1635         wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1636
1637         /* power on the sfp cage if present and turn on I2C */
1638         ctrl_ext = rd32(E1000_CTRL_EXT);
1639         ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1640         ctrl_ext |= E1000_CTRL_I2C_ENA;
1641         wr32(E1000_CTRL_EXT, ctrl_ext);
1642
1643         ctrl_reg = rd32(E1000_CTRL);
1644         ctrl_reg |= E1000_CTRL_SLU;
1645
1646         if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
1647                 /* set both sw defined pins */
1648                 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1649
1650                 /* Set switch control to serdes energy detect */
1651                 reg = rd32(E1000_CONNSW);
1652                 reg |= E1000_CONNSW_ENRGSRC;
1653                 wr32(E1000_CONNSW, reg);
1654         }
1655
1656         reg = rd32(E1000_PCS_LCTL);
1657
1658         /* default pcs_autoneg to the same setting as mac autoneg */
1659         pcs_autoneg = hw->mac.autoneg;
1660
1661         switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1662         case E1000_CTRL_EXT_LINK_MODE_SGMII:
1663                 /* sgmii mode lets the phy handle forcing speed/duplex */
1664                 pcs_autoneg = true;
1665                 /* autoneg time out should be disabled for SGMII mode */
1666                 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1667                 break;
1668         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1669                 /* disable PCS autoneg and support parallel detect only */
1670                 pcs_autoneg = false;
1671         default:
1672                 if (hw->mac.type == e1000_82575 ||
1673                     hw->mac.type == e1000_82576) {
1674                         ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1675                         if (ret_val) {
1676                                 hw_dbg(KERN_DEBUG "NVM Read Error\n\n");
1677                                 return ret_val;
1678                         }
1679
1680                         if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1681                                 pcs_autoneg = false;
1682                 }
1683
1684                 /* non-SGMII modes only supports a speed of 1000/Full for the
1685                  * link so it is best to just force the MAC and let the pcs
1686                  * link either autoneg or be forced to 1000/Full
1687                  */
1688                 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1689                                 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1690
1691                 /* set speed of 1000/Full if speed/duplex is forced */
1692                 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1693                 break;
1694         }
1695
1696         wr32(E1000_CTRL, ctrl_reg);
1697
1698         /* New SerDes mode allows for forcing speed or autonegotiating speed
1699          * at 1gb. Autoneg should be default set by most drivers. This is the
1700          * mode that will be compatible with older link partners and switches.
1701          * However, both are supported by the hardware and some drivers/tools.
1702          */
1703         reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1704                 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1705
1706         if (pcs_autoneg) {
1707                 /* Set PCS register for autoneg */
1708                 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1709                        E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1710
1711                 /* Disable force flow control for autoneg */
1712                 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1713
1714                 /* Configure flow control advertisement for autoneg */
1715                 anadv_reg = rd32(E1000_PCS_ANADV);
1716                 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1717                 switch (hw->fc.requested_mode) {
1718                 case e1000_fc_full:
1719                 case e1000_fc_rx_pause:
1720                         anadv_reg |= E1000_TXCW_ASM_DIR;
1721                         anadv_reg |= E1000_TXCW_PAUSE;
1722                         break;
1723                 case e1000_fc_tx_pause:
1724                         anadv_reg |= E1000_TXCW_ASM_DIR;
1725                         break;
1726                 default:
1727                         break;
1728                 }
1729                 wr32(E1000_PCS_ANADV, anadv_reg);
1730
1731                 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1732         } else {
1733                 /* Set PCS register for forced link */
1734                 reg |= E1000_PCS_LCTL_FSD;        /* Force Speed */
1735
1736                 /* Force flow control for forced link */
1737                 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1738
1739                 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1740         }
1741
1742         wr32(E1000_PCS_LCTL, reg);
1743
1744         if (!pcs_autoneg && !igb_sgmii_active_82575(hw))
1745                 igb_force_mac_fc(hw);
1746
1747         return ret_val;
1748 }
1749
1750 /**
1751  *  igb_sgmii_active_82575 - Return sgmii state
1752  *  @hw: pointer to the HW structure
1753  *
1754  *  82575 silicon has a serialized gigabit media independent interface (sgmii)
1755  *  which can be enabled for use in the embedded applications.  Simply
1756  *  return the current state of the sgmii interface.
1757  **/
1758 static bool igb_sgmii_active_82575(struct e1000_hw *hw)
1759 {
1760         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1761         return dev_spec->sgmii_active;
1762 }
1763
1764 /**
1765  *  igb_reset_init_script_82575 - Inits HW defaults after reset
1766  *  @hw: pointer to the HW structure
1767  *
1768  *  Inits recommended HW defaults after a reset when there is no EEPROM
1769  *  detected. This is only for the 82575.
1770  **/
1771 static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1772 {
1773         if (hw->mac.type == e1000_82575) {
1774                 hw_dbg("Running reset init script for 82575\n");
1775                 /* SerDes configuration via SERDESCTRL */
1776                 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1777                 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
1778                 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
1779                 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
1780
1781                 /* CCM configuration via CCMCTL register */
1782                 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
1783                 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
1784
1785                 /* PCIe lanes configuration */
1786                 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
1787                 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
1788                 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
1789                 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
1790
1791                 /* PCIe PLL Configuration */
1792                 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
1793                 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
1794                 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
1795         }
1796
1797         return 0;
1798 }
1799
1800 /**
1801  *  igb_read_mac_addr_82575 - Read device MAC address
1802  *  @hw: pointer to the HW structure
1803  **/
1804 static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
1805 {
1806         s32 ret_val = 0;
1807
1808         /* If there's an alternate MAC address place it in RAR0
1809          * so that it will override the Si installed default perm
1810          * address.
1811          */
1812         ret_val = igb_check_alt_mac_addr(hw);
1813         if (ret_val)
1814                 goto out;
1815
1816         ret_val = igb_read_mac_addr(hw);
1817
1818 out:
1819         return ret_val;
1820 }
1821
1822 /**
1823  * igb_power_down_phy_copper_82575 - Remove link during PHY power down
1824  * @hw: pointer to the HW structure
1825  *
1826  * In the case of a PHY power down to save power, or to turn off link during a
1827  * driver unload, or wake on lan is not enabled, remove the link.
1828  **/
1829 void igb_power_down_phy_copper_82575(struct e1000_hw *hw)
1830 {
1831         /* If the management interface is not enabled, then power down */
1832         if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw)))
1833                 igb_power_down_phy_copper(hw);
1834 }
1835
1836 /**
1837  *  igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
1838  *  @hw: pointer to the HW structure
1839  *
1840  *  Clears the hardware counters by reading the counter registers.
1841  **/
1842 static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
1843 {
1844         igb_clear_hw_cntrs_base(hw);
1845
1846         rd32(E1000_PRC64);
1847         rd32(E1000_PRC127);
1848         rd32(E1000_PRC255);
1849         rd32(E1000_PRC511);
1850         rd32(E1000_PRC1023);
1851         rd32(E1000_PRC1522);
1852         rd32(E1000_PTC64);
1853         rd32(E1000_PTC127);
1854         rd32(E1000_PTC255);
1855         rd32(E1000_PTC511);
1856         rd32(E1000_PTC1023);
1857         rd32(E1000_PTC1522);
1858
1859         rd32(E1000_ALGNERRC);
1860         rd32(E1000_RXERRC);
1861         rd32(E1000_TNCRS);
1862         rd32(E1000_CEXTERR);
1863         rd32(E1000_TSCTC);
1864         rd32(E1000_TSCTFC);
1865
1866         rd32(E1000_MGTPRC);
1867         rd32(E1000_MGTPDC);
1868         rd32(E1000_MGTPTC);
1869
1870         rd32(E1000_IAC);
1871         rd32(E1000_ICRXOC);
1872
1873         rd32(E1000_ICRXPTC);
1874         rd32(E1000_ICRXATC);
1875         rd32(E1000_ICTXPTC);
1876         rd32(E1000_ICTXATC);
1877         rd32(E1000_ICTXQEC);
1878         rd32(E1000_ICTXQMTC);
1879         rd32(E1000_ICRXDMTC);
1880
1881         rd32(E1000_CBTMPC);
1882         rd32(E1000_HTDPMC);
1883         rd32(E1000_CBRMPC);
1884         rd32(E1000_RPTHC);
1885         rd32(E1000_HGPTC);
1886         rd32(E1000_HTCBDPC);
1887         rd32(E1000_HGORCL);
1888         rd32(E1000_HGORCH);
1889         rd32(E1000_HGOTCL);
1890         rd32(E1000_HGOTCH);
1891         rd32(E1000_LENERRS);
1892
1893         /* This register should not be read in copper configurations */
1894         if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1895             igb_sgmii_active_82575(hw))
1896                 rd32(E1000_SCVPC);
1897 }
1898
1899 /**
1900  *  igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1901  *  @hw: pointer to the HW structure
1902  *
1903  *  After rx enable if managability is enabled then there is likely some
1904  *  bad data at the start of the fifo and possibly in the DMA fifo.  This
1905  *  function clears the fifos and flushes any packets that came in as rx was
1906  *  being enabled.
1907  **/
1908 void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
1909 {
1910         u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1911         int i, ms_wait;
1912
1913         if (hw->mac.type != e1000_82575 ||
1914             !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1915                 return;
1916
1917         /* Disable all RX queues */
1918         for (i = 0; i < 4; i++) {
1919                 rxdctl[i] = rd32(E1000_RXDCTL(i));
1920                 wr32(E1000_RXDCTL(i),
1921                      rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1922         }
1923         /* Poll all queues to verify they have shut down */
1924         for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1925                 usleep_range(1000, 2000);
1926                 rx_enabled = 0;
1927                 for (i = 0; i < 4; i++)
1928                         rx_enabled |= rd32(E1000_RXDCTL(i));
1929                 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1930                         break;
1931         }
1932
1933         if (ms_wait == 10)
1934                 hw_dbg("Queue disable timed out after 10ms\n");
1935
1936         /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1937          * incoming packets are rejected.  Set enable and wait 2ms so that
1938          * any packet that was coming in as RCTL.EN was set is flushed
1939          */
1940         rfctl = rd32(E1000_RFCTL);
1941         wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
1942
1943         rlpml = rd32(E1000_RLPML);
1944         wr32(E1000_RLPML, 0);
1945
1946         rctl = rd32(E1000_RCTL);
1947         temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1948         temp_rctl |= E1000_RCTL_LPE;
1949
1950         wr32(E1000_RCTL, temp_rctl);
1951         wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1952         wrfl();
1953         usleep_range(2000, 3000);
1954
1955         /* Enable RX queues that were previously enabled and restore our
1956          * previous state
1957          */
1958         for (i = 0; i < 4; i++)
1959                 wr32(E1000_RXDCTL(i), rxdctl[i]);
1960         wr32(E1000_RCTL, rctl);
1961         wrfl();
1962
1963         wr32(E1000_RLPML, rlpml);
1964         wr32(E1000_RFCTL, rfctl);
1965
1966         /* Flush receive errors generated by workaround */
1967         rd32(E1000_ROC);
1968         rd32(E1000_RNBC);
1969         rd32(E1000_MPC);
1970 }
1971
1972 /**
1973  *  igb_set_pcie_completion_timeout - set pci-e completion timeout
1974  *  @hw: pointer to the HW structure
1975  *
1976  *  The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
1977  *  however the hardware default for these parts is 500us to 1ms which is less
1978  *  than the 10ms recommended by the pci-e spec.  To address this we need to
1979  *  increase the value to either 10ms to 200ms for capability version 1 config,
1980  *  or 16ms to 55ms for version 2.
1981  **/
1982 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw)
1983 {
1984         u32 gcr = rd32(E1000_GCR);
1985         s32 ret_val = 0;
1986         u16 pcie_devctl2;
1987
1988         /* only take action if timeout value is defaulted to 0 */
1989         if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
1990                 goto out;
1991
1992         /* if capabilities version is type 1 we can write the
1993          * timeout of 10ms to 200ms through the GCR register
1994          */
1995         if (!(gcr & E1000_GCR_CAP_VER2)) {
1996                 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
1997                 goto out;
1998         }
1999
2000         /* for version 2 capabilities we need to write the config space
2001          * directly in order to set the completion timeout value for
2002          * 16ms to 55ms
2003          */
2004         ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2005                                         &pcie_devctl2);
2006         if (ret_val)
2007                 goto out;
2008
2009         pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2010
2011         ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2012                                          &pcie_devctl2);
2013 out:
2014         /* disable completion timeout resend */
2015         gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2016
2017         wr32(E1000_GCR, gcr);
2018         return ret_val;
2019 }
2020
2021 /**
2022  *  igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2023  *  @hw: pointer to the hardware struct
2024  *  @enable: state to enter, either enabled or disabled
2025  *  @pf: Physical Function pool - do not set anti-spoofing for the PF
2026  *
2027  *  enables/disables L2 switch anti-spoofing functionality.
2028  **/
2029 void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2030 {
2031         u32 reg_val, reg_offset;
2032
2033         switch (hw->mac.type) {
2034         case e1000_82576:
2035                 reg_offset = E1000_DTXSWC;
2036                 break;
2037         case e1000_i350:
2038         case e1000_i354:
2039                 reg_offset = E1000_TXSWC;
2040                 break;
2041         default:
2042                 return;
2043         }
2044
2045         reg_val = rd32(reg_offset);
2046         if (enable) {
2047                 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2048                              E1000_DTXSWC_VLAN_SPOOF_MASK);
2049                 /* The PF can spoof - it has to in order to
2050                  * support emulation mode NICs
2051                  */
2052                 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
2053         } else {
2054                 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2055                              E1000_DTXSWC_VLAN_SPOOF_MASK);
2056         }
2057         wr32(reg_offset, reg_val);
2058 }
2059
2060 /**
2061  *  igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
2062  *  @hw: pointer to the hardware struct
2063  *  @enable: state to enter, either enabled or disabled
2064  *
2065  *  enables/disables L2 switch loopback functionality.
2066  **/
2067 void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2068 {
2069         u32 dtxswc;
2070
2071         switch (hw->mac.type) {
2072         case e1000_82576:
2073                 dtxswc = rd32(E1000_DTXSWC);
2074                 if (enable)
2075                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2076                 else
2077                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2078                 wr32(E1000_DTXSWC, dtxswc);
2079                 break;
2080         case e1000_i354:
2081         case e1000_i350:
2082                 dtxswc = rd32(E1000_TXSWC);
2083                 if (enable)
2084                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2085                 else
2086                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2087                 wr32(E1000_TXSWC, dtxswc);
2088                 break;
2089         default:
2090                 /* Currently no other hardware supports loopback */
2091                 break;
2092         }
2093
2094 }
2095
2096 /**
2097  *  igb_vmdq_set_replication_pf - enable or disable vmdq replication
2098  *  @hw: pointer to the hardware struct
2099  *  @enable: state to enter, either enabled or disabled
2100  *
2101  *  enables/disables replication of packets across multiple pools.
2102  **/
2103 void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2104 {
2105         u32 vt_ctl = rd32(E1000_VT_CTL);
2106
2107         if (enable)
2108                 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2109         else
2110                 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2111
2112         wr32(E1000_VT_CTL, vt_ctl);
2113 }
2114
2115 /**
2116  *  igb_read_phy_reg_82580 - Read 82580 MDI control register
2117  *  @hw: pointer to the HW structure
2118  *  @offset: register offset to be read
2119  *  @data: pointer to the read data
2120  *
2121  *  Reads the MDI control register in the PHY at offset and stores the
2122  *  information read to data.
2123  **/
2124 static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2125 {
2126         s32 ret_val;
2127
2128         ret_val = hw->phy.ops.acquire(hw);
2129         if (ret_val)
2130                 goto out;
2131
2132         ret_val = igb_read_phy_reg_mdic(hw, offset, data);
2133
2134         hw->phy.ops.release(hw);
2135
2136 out:
2137         return ret_val;
2138 }
2139
2140 /**
2141  *  igb_write_phy_reg_82580 - Write 82580 MDI control register
2142  *  @hw: pointer to the HW structure
2143  *  @offset: register offset to write to
2144  *  @data: data to write to register at offset
2145  *
2146  *  Writes data to MDI control register in the PHY at offset.
2147  **/
2148 static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2149 {
2150         s32 ret_val;
2151
2152
2153         ret_val = hw->phy.ops.acquire(hw);
2154         if (ret_val)
2155                 goto out;
2156
2157         ret_val = igb_write_phy_reg_mdic(hw, offset, data);
2158
2159         hw->phy.ops.release(hw);
2160
2161 out:
2162         return ret_val;
2163 }
2164
2165 /**
2166  *  igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2167  *  @hw: pointer to the HW structure
2168  *
2169  *  This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2170  *  the values found in the EEPROM.  This addresses an issue in which these
2171  *  bits are not restored from EEPROM after reset.
2172  **/
2173 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw)
2174 {
2175         s32 ret_val = 0;
2176         u32 mdicnfg;
2177         u16 nvm_data = 0;
2178
2179         if (hw->mac.type != e1000_82580)
2180                 goto out;
2181         if (!igb_sgmii_active_82575(hw))
2182                 goto out;
2183
2184         ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2185                                    NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2186                                    &nvm_data);
2187         if (ret_val) {
2188                 hw_dbg("NVM Read Error\n");
2189                 goto out;
2190         }
2191
2192         mdicnfg = rd32(E1000_MDICNFG);
2193         if (nvm_data & NVM_WORD24_EXT_MDIO)
2194                 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2195         if (nvm_data & NVM_WORD24_COM_MDIO)
2196                 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2197         wr32(E1000_MDICNFG, mdicnfg);
2198 out:
2199         return ret_val;
2200 }
2201
2202 /**
2203  *  igb_reset_hw_82580 - Reset hardware
2204  *  @hw: pointer to the HW structure
2205  *
2206  *  This resets function or entire device (all ports, etc.)
2207  *  to a known state.
2208  **/
2209 static s32 igb_reset_hw_82580(struct e1000_hw *hw)
2210 {
2211         s32 ret_val = 0;
2212         /* BH SW mailbox bit in SW_FW_SYNC */
2213         u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2214         u32 ctrl;
2215         bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2216
2217         hw->dev_spec._82575.global_device_reset = false;
2218
2219         /* due to hw errata, global device reset doesn't always
2220          * work on 82580
2221          */
2222         if (hw->mac.type == e1000_82580)
2223                 global_device_reset = false;
2224
2225         /* Get current control state. */
2226         ctrl = rd32(E1000_CTRL);
2227
2228         /* Prevent the PCI-E bus from sticking if there is no TLP connection
2229          * on the last TLP read/write transaction when MAC is reset.
2230          */
2231         ret_val = igb_disable_pcie_master(hw);
2232         if (ret_val)
2233                 hw_dbg("PCI-E Master disable polling has failed.\n");
2234
2235         hw_dbg("Masking off all interrupts\n");
2236         wr32(E1000_IMC, 0xffffffff);
2237         wr32(E1000_RCTL, 0);
2238         wr32(E1000_TCTL, E1000_TCTL_PSP);
2239         wrfl();
2240
2241         usleep_range(10000, 11000);
2242
2243         /* Determine whether or not a global dev reset is requested */
2244         if (global_device_reset &&
2245                 hw->mac.ops.acquire_swfw_sync(hw, swmbsw_mask))
2246                         global_device_reset = false;
2247
2248         if (global_device_reset &&
2249                 !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET))
2250                 ctrl |= E1000_CTRL_DEV_RST;
2251         else
2252                 ctrl |= E1000_CTRL_RST;
2253
2254         wr32(E1000_CTRL, ctrl);
2255         wrfl();
2256
2257         /* Add delay to insure DEV_RST has time to complete */
2258         if (global_device_reset)
2259                 usleep_range(5000, 6000);
2260
2261         ret_val = igb_get_auto_rd_done(hw);
2262         if (ret_val) {
2263                 /* When auto config read does not complete, do not
2264                  * return with an error. This can happen in situations
2265                  * where there is no eeprom and prevents getting link.
2266                  */
2267                 hw_dbg("Auto Read Done did not complete\n");
2268         }
2269
2270         /* clear global device reset status bit */
2271         wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET);
2272
2273         /* Clear any pending interrupt events. */
2274         wr32(E1000_IMC, 0xffffffff);
2275         rd32(E1000_ICR);
2276
2277         ret_val = igb_reset_mdicnfg_82580(hw);
2278         if (ret_val)
2279                 hw_dbg("Could not reset MDICNFG based on EEPROM\n");
2280
2281         /* Install any alternate MAC address into RAR0 */
2282         ret_val = igb_check_alt_mac_addr(hw);
2283
2284         /* Release semaphore */
2285         if (global_device_reset)
2286                 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2287
2288         return ret_val;
2289 }
2290
2291 /**
2292  *  igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
2293  *  @data: data received by reading RXPBS register
2294  *
2295  *  The 82580 uses a table based approach for packet buffer allocation sizes.
2296  *  This function converts the retrieved value into the correct table value
2297  *     0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2298  *  0x0 36  72 144   1   2   4   8  16
2299  *  0x8 35  70 140 rsv rsv rsv rsv rsv
2300  */
2301 u16 igb_rxpbs_adjust_82580(u32 data)
2302 {
2303         u16 ret_val = 0;
2304
2305         if (data < ARRAY_SIZE(e1000_82580_rxpbs_table))
2306                 ret_val = e1000_82580_rxpbs_table[data];
2307
2308         return ret_val;
2309 }
2310
2311 /**
2312  *  igb_validate_nvm_checksum_with_offset - Validate EEPROM
2313  *  checksum
2314  *  @hw: pointer to the HW structure
2315  *  @offset: offset in words of the checksum protected region
2316  *
2317  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2318  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
2319  **/
2320 static s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
2321                                                  u16 offset)
2322 {
2323         s32 ret_val = 0;
2324         u16 checksum = 0;
2325         u16 i, nvm_data;
2326
2327         for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2328                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2329                 if (ret_val) {
2330                         hw_dbg("NVM Read Error\n");
2331                         goto out;
2332                 }
2333                 checksum += nvm_data;
2334         }
2335
2336         if (checksum != (u16) NVM_SUM) {
2337                 hw_dbg("NVM Checksum Invalid\n");
2338                 ret_val = -E1000_ERR_NVM;
2339                 goto out;
2340         }
2341
2342 out:
2343         return ret_val;
2344 }
2345
2346 /**
2347  *  igb_update_nvm_checksum_with_offset - Update EEPROM
2348  *  checksum
2349  *  @hw: pointer to the HW structure
2350  *  @offset: offset in words of the checksum protected region
2351  *
2352  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
2353  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
2354  *  value to the EEPROM.
2355  **/
2356 static s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2357 {
2358         s32 ret_val;
2359         u16 checksum = 0;
2360         u16 i, nvm_data;
2361
2362         for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2363                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2364                 if (ret_val) {
2365                         hw_dbg("NVM Read Error while updating checksum.\n");
2366                         goto out;
2367                 }
2368                 checksum += nvm_data;
2369         }
2370         checksum = (u16) NVM_SUM - checksum;
2371         ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2372                                 &checksum);
2373         if (ret_val)
2374                 hw_dbg("NVM Write Error while updating checksum.\n");
2375
2376 out:
2377         return ret_val;
2378 }
2379
2380 /**
2381  *  igb_validate_nvm_checksum_82580 - Validate EEPROM checksum
2382  *  @hw: pointer to the HW structure
2383  *
2384  *  Calculates the EEPROM section checksum by reading/adding each word of
2385  *  the EEPROM and then verifies that the sum of the EEPROM is
2386  *  equal to 0xBABA.
2387  **/
2388 static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw)
2389 {
2390         s32 ret_val = 0;
2391         u16 eeprom_regions_count = 1;
2392         u16 j, nvm_data;
2393         u16 nvm_offset;
2394
2395         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2396         if (ret_val) {
2397                 hw_dbg("NVM Read Error\n");
2398                 goto out;
2399         }
2400
2401         if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2402                 /* if checksums compatibility bit is set validate checksums
2403                  * for all 4 ports.
2404                  */
2405                 eeprom_regions_count = 4;
2406         }
2407
2408         for (j = 0; j < eeprom_regions_count; j++) {
2409                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2410                 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2411                                                                 nvm_offset);
2412                 if (ret_val != 0)
2413                         goto out;
2414         }
2415
2416 out:
2417         return ret_val;
2418 }
2419
2420 /**
2421  *  igb_update_nvm_checksum_82580 - Update EEPROM checksum
2422  *  @hw: pointer to the HW structure
2423  *
2424  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2425  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2426  *  checksum and writes the value to the EEPROM.
2427  **/
2428 static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw)
2429 {
2430         s32 ret_val;
2431         u16 j, nvm_data;
2432         u16 nvm_offset;
2433
2434         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2435         if (ret_val) {
2436                 hw_dbg("NVM Read Error while updating checksum compatibility bit.\n");
2437                 goto out;
2438         }
2439
2440         if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) {
2441                 /* set compatibility bit to validate checksums appropriately */
2442                 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2443                 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2444                                         &nvm_data);
2445                 if (ret_val) {
2446                         hw_dbg("NVM Write Error while updating checksum compatibility bit.\n");
2447                         goto out;
2448                 }
2449         }
2450
2451         for (j = 0; j < 4; j++) {
2452                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2453                 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2454                 if (ret_val)
2455                         goto out;
2456         }
2457
2458 out:
2459         return ret_val;
2460 }
2461
2462 /**
2463  *  igb_validate_nvm_checksum_i350 - Validate EEPROM checksum
2464  *  @hw: pointer to the HW structure
2465  *
2466  *  Calculates the EEPROM section checksum by reading/adding each word of
2467  *  the EEPROM and then verifies that the sum of the EEPROM is
2468  *  equal to 0xBABA.
2469  **/
2470 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw)
2471 {
2472         s32 ret_val = 0;
2473         u16 j;
2474         u16 nvm_offset;
2475
2476         for (j = 0; j < 4; j++) {
2477                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2478                 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2479                                                                 nvm_offset);
2480                 if (ret_val != 0)
2481                         goto out;
2482         }
2483
2484 out:
2485         return ret_val;
2486 }
2487
2488 /**
2489  *  igb_update_nvm_checksum_i350 - Update EEPROM checksum
2490  *  @hw: pointer to the HW structure
2491  *
2492  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2493  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2494  *  checksum and writes the value to the EEPROM.
2495  **/
2496 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw)
2497 {
2498         s32 ret_val = 0;
2499         u16 j;
2500         u16 nvm_offset;
2501
2502         for (j = 0; j < 4; j++) {
2503                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2504                 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2505                 if (ret_val != 0)
2506                         goto out;
2507         }
2508
2509 out:
2510         return ret_val;
2511 }
2512
2513 /**
2514  *  __igb_access_emi_reg - Read/write EMI register
2515  *  @hw: pointer to the HW structure
2516  *  @addr: EMI address to program
2517  *  @data: pointer to value to read/write from/to the EMI address
2518  *  @read: boolean flag to indicate read or write
2519  **/
2520 static s32 __igb_access_emi_reg(struct e1000_hw *hw, u16 address,
2521                                   u16 *data, bool read)
2522 {
2523         s32 ret_val = 0;
2524
2525         ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2526         if (ret_val)
2527                 return ret_val;
2528
2529         if (read)
2530                 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2531         else
2532                 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2533
2534         return ret_val;
2535 }
2536
2537 /**
2538  *  igb_read_emi_reg - Read Extended Management Interface register
2539  *  @hw: pointer to the HW structure
2540  *  @addr: EMI address to program
2541  *  @data: value to be read from the EMI address
2542  **/
2543 s32 igb_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2544 {
2545         return __igb_access_emi_reg(hw, addr, data, true);
2546 }
2547
2548 /**
2549  *  igb_set_eee_i350 - Enable/disable EEE support
2550  *  @hw: pointer to the HW structure
2551  *  @adv1G: boolean flag enabling 1G EEE advertisement
2552  *  @adv100m: boolean flag enabling 100M EEE advertisement
2553  *
2554  *  Enable/disable EEE based on setting in dev_spec structure.
2555  *
2556  **/
2557 s32 igb_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M)
2558 {
2559         u32 ipcnfg, eeer;
2560
2561         if ((hw->mac.type < e1000_i350) ||
2562             (hw->phy.media_type != e1000_media_type_copper))
2563                 goto out;
2564         ipcnfg = rd32(E1000_IPCNFG);
2565         eeer = rd32(E1000_EEER);
2566
2567         /* enable or disable per user setting */
2568         if (!(hw->dev_spec._82575.eee_disable)) {
2569                 u32 eee_su = rd32(E1000_EEE_SU);
2570
2571                 if (adv100M)
2572                         ipcnfg |= E1000_IPCNFG_EEE_100M_AN;
2573                 else
2574                         ipcnfg &= ~E1000_IPCNFG_EEE_100M_AN;
2575
2576                 if (adv1G)
2577                         ipcnfg |= E1000_IPCNFG_EEE_1G_AN;
2578                 else
2579                         ipcnfg &= ~E1000_IPCNFG_EEE_1G_AN;
2580
2581                 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2582                         E1000_EEER_LPI_FC);
2583
2584                 /* This bit should not be set in normal operation. */
2585                 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2586                         hw_dbg("LPI Clock Stop Bit should not be set!\n");
2587
2588         } else {
2589                 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN |
2590                         E1000_IPCNFG_EEE_100M_AN);
2591                 eeer &= ~(E1000_EEER_TX_LPI_EN |
2592                         E1000_EEER_RX_LPI_EN |
2593                         E1000_EEER_LPI_FC);
2594         }
2595         wr32(E1000_IPCNFG, ipcnfg);
2596         wr32(E1000_EEER, eeer);
2597         rd32(E1000_IPCNFG);
2598         rd32(E1000_EEER);
2599 out:
2600
2601         return 0;
2602 }
2603
2604 /**
2605  *  igb_set_eee_i354 - Enable/disable EEE support
2606  *  @hw: pointer to the HW structure
2607  *  @adv1G: boolean flag enabling 1G EEE advertisement
2608  *  @adv100m: boolean flag enabling 100M EEE advertisement
2609  *
2610  *  Enable/disable EEE legacy mode based on setting in dev_spec structure.
2611  *
2612  **/
2613 s32 igb_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M)
2614 {
2615         struct e1000_phy_info *phy = &hw->phy;
2616         s32 ret_val = 0;
2617         u16 phy_data;
2618
2619         if ((hw->phy.media_type != e1000_media_type_copper) ||
2620             (phy->id != M88E1543_E_PHY_ID))
2621                 goto out;
2622
2623         if (!hw->dev_spec._82575.eee_disable) {
2624                 /* Switch to PHY page 18. */
2625                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
2626                 if (ret_val)
2627                         goto out;
2628
2629                 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2630                                             &phy_data);
2631                 if (ret_val)
2632                         goto out;
2633
2634                 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
2635                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2636                                              phy_data);
2637                 if (ret_val)
2638                         goto out;
2639
2640                 /* Return the PHY to page 0. */
2641                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2642                 if (ret_val)
2643                         goto out;
2644
2645                 /* Turn on EEE advertisement. */
2646                 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2647                                              E1000_EEE_ADV_DEV_I354,
2648                                              &phy_data);
2649                 if (ret_val)
2650                         goto out;
2651
2652                 if (adv100M)
2653                         phy_data |= E1000_EEE_ADV_100_SUPPORTED;
2654                 else
2655                         phy_data &= ~E1000_EEE_ADV_100_SUPPORTED;
2656
2657                 if (adv1G)
2658                         phy_data |= E1000_EEE_ADV_1000_SUPPORTED;
2659                 else
2660                         phy_data &= ~E1000_EEE_ADV_1000_SUPPORTED;
2661
2662                 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2663                                                 E1000_EEE_ADV_DEV_I354,
2664                                                 phy_data);
2665         } else {
2666                 /* Turn off EEE advertisement. */
2667                 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2668                                              E1000_EEE_ADV_DEV_I354,
2669                                              &phy_data);
2670                 if (ret_val)
2671                         goto out;
2672
2673                 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
2674                               E1000_EEE_ADV_1000_SUPPORTED);
2675                 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2676                                               E1000_EEE_ADV_DEV_I354,
2677                                               phy_data);
2678         }
2679
2680 out:
2681         return ret_val;
2682 }
2683
2684 /**
2685  *  igb_get_eee_status_i354 - Get EEE status
2686  *  @hw: pointer to the HW structure
2687  *  @status: EEE status
2688  *
2689  *  Get EEE status by guessing based on whether Tx or Rx LPI indications have
2690  *  been received.
2691  **/
2692 s32 igb_get_eee_status_i354(struct e1000_hw *hw, bool *status)
2693 {
2694         struct e1000_phy_info *phy = &hw->phy;
2695         s32 ret_val = 0;
2696         u16 phy_data;
2697
2698         /* Check if EEE is supported on this device. */
2699         if ((hw->phy.media_type != e1000_media_type_copper) ||
2700             (phy->id != M88E1543_E_PHY_ID))
2701                 goto out;
2702
2703         ret_val = igb_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
2704                                      E1000_PCS_STATUS_DEV_I354,
2705                                      &phy_data);
2706         if (ret_val)
2707                 goto out;
2708
2709         *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
2710                               E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;
2711
2712 out:
2713         return ret_val;
2714 }
2715
2716 static const u8 e1000_emc_temp_data[4] = {
2717         E1000_EMC_INTERNAL_DATA,
2718         E1000_EMC_DIODE1_DATA,
2719         E1000_EMC_DIODE2_DATA,
2720         E1000_EMC_DIODE3_DATA
2721 };
2722 static const u8 e1000_emc_therm_limit[4] = {
2723         E1000_EMC_INTERNAL_THERM_LIMIT,
2724         E1000_EMC_DIODE1_THERM_LIMIT,
2725         E1000_EMC_DIODE2_THERM_LIMIT,
2726         E1000_EMC_DIODE3_THERM_LIMIT
2727 };
2728
2729 #ifdef CONFIG_IGB_HWMON
2730 /**
2731  *  igb_get_thermal_sensor_data_generic - Gathers thermal sensor data
2732  *  @hw: pointer to hardware structure
2733  *
2734  *  Updates the temperatures in mac.thermal_sensor_data
2735  **/
2736 static s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw)
2737 {
2738         u16 ets_offset;
2739         u16 ets_cfg;
2740         u16 ets_sensor;
2741         u8  num_sensors;
2742         u8  sensor_index;
2743         u8  sensor_location;
2744         u8  i;
2745         struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2746
2747         if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2748                 return E1000_NOT_IMPLEMENTED;
2749
2750         data->sensor[0].temp = (rd32(E1000_THMJT) & 0xFF);
2751
2752         /* Return the internal sensor only if ETS is unsupported */
2753         hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2754         if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2755                 return 0;
2756
2757         hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2758         if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2759             != NVM_ETS_TYPE_EMC)
2760                 return E1000_NOT_IMPLEMENTED;
2761
2762         num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2763         if (num_sensors > E1000_MAX_SENSORS)
2764                 num_sensors = E1000_MAX_SENSORS;
2765
2766         for (i = 1; i < num_sensors; i++) {
2767                 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2768                 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2769                                 NVM_ETS_DATA_INDEX_SHIFT);
2770                 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2771                                    NVM_ETS_DATA_LOC_SHIFT);
2772
2773                 if (sensor_location != 0)
2774                         hw->phy.ops.read_i2c_byte(hw,
2775                                         e1000_emc_temp_data[sensor_index],
2776                                         E1000_I2C_THERMAL_SENSOR_ADDR,
2777                                         &data->sensor[i].temp);
2778         }
2779         return 0;
2780 }
2781
2782 /**
2783  *  igb_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds
2784  *  @hw: pointer to hardware structure
2785  *
2786  *  Sets the thermal sensor thresholds according to the NVM map
2787  *  and save off the threshold and location values into mac.thermal_sensor_data
2788  **/
2789 static s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *hw)
2790 {
2791         u16 ets_offset;
2792         u16 ets_cfg;
2793         u16 ets_sensor;
2794         u8  low_thresh_delta;
2795         u8  num_sensors;
2796         u8  sensor_index;
2797         u8  sensor_location;
2798         u8  therm_limit;
2799         u8  i;
2800         struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2801
2802         if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2803                 return E1000_NOT_IMPLEMENTED;
2804
2805         memset(data, 0, sizeof(struct e1000_thermal_sensor_data));
2806
2807         data->sensor[0].location = 0x1;
2808         data->sensor[0].caution_thresh =
2809                 (rd32(E1000_THHIGHTC) & 0xFF);
2810         data->sensor[0].max_op_thresh =
2811                 (rd32(E1000_THLOWTC) & 0xFF);
2812
2813         /* Return the internal sensor only if ETS is unsupported */
2814         hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2815         if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2816                 return 0;
2817
2818         hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2819         if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2820             != NVM_ETS_TYPE_EMC)
2821                 return E1000_NOT_IMPLEMENTED;
2822
2823         low_thresh_delta = ((ets_cfg & NVM_ETS_LTHRES_DELTA_MASK) >>
2824                             NVM_ETS_LTHRES_DELTA_SHIFT);
2825         num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2826
2827         for (i = 1; i <= num_sensors; i++) {
2828                 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2829                 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2830                                 NVM_ETS_DATA_INDEX_SHIFT);
2831                 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2832                                    NVM_ETS_DATA_LOC_SHIFT);
2833                 therm_limit = ets_sensor & NVM_ETS_DATA_HTHRESH_MASK;
2834
2835                 hw->phy.ops.write_i2c_byte(hw,
2836                         e1000_emc_therm_limit[sensor_index],
2837                         E1000_I2C_THERMAL_SENSOR_ADDR,
2838                         therm_limit);
2839
2840                 if ((i < E1000_MAX_SENSORS) && (sensor_location != 0)) {
2841                         data->sensor[i].location = sensor_location;
2842                         data->sensor[i].caution_thresh = therm_limit;
2843                         data->sensor[i].max_op_thresh = therm_limit -
2844                                                         low_thresh_delta;
2845                 }
2846         }
2847         return 0;
2848 }
2849
2850 #endif
2851 static struct e1000_mac_operations e1000_mac_ops_82575 = {
2852         .init_hw              = igb_init_hw_82575,
2853         .check_for_link       = igb_check_for_link_82575,
2854         .rar_set              = igb_rar_set,
2855         .read_mac_addr        = igb_read_mac_addr_82575,
2856         .get_speed_and_duplex = igb_get_link_up_info_82575,
2857 #ifdef CONFIG_IGB_HWMON
2858         .get_thermal_sensor_data = igb_get_thermal_sensor_data_generic,
2859         .init_thermal_sensor_thresh = igb_init_thermal_sensor_thresh_generic,
2860 #endif
2861 };
2862
2863 static struct e1000_phy_operations e1000_phy_ops_82575 = {
2864         .acquire              = igb_acquire_phy_82575,
2865         .get_cfg_done         = igb_get_cfg_done_82575,
2866         .release              = igb_release_phy_82575,
2867         .write_i2c_byte       = igb_write_i2c_byte,
2868         .read_i2c_byte        = igb_read_i2c_byte,
2869 };
2870
2871 static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
2872         .acquire              = igb_acquire_nvm_82575,
2873         .read                 = igb_read_nvm_eerd,
2874         .release              = igb_release_nvm_82575,
2875         .write                = igb_write_nvm_spi,
2876 };
2877
2878 const struct e1000_info e1000_82575_info = {
2879         .get_invariants = igb_get_invariants_82575,
2880         .mac_ops = &e1000_mac_ops_82575,
2881         .phy_ops = &e1000_phy_ops_82575,
2882         .nvm_ops = &e1000_nvm_ops_82575,
2883 };
2884