drivers/net/ethernet/intel/igb/igb_main.c

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2013 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  29
  30 #include <linux/module.h>
  31 #include <linux/types.h>
  32 #include <linux/init.h>
  33 #include <linux/bitops.h>
  34 #include <linux/vmalloc.h>
  35 #include <linux/pagemap.h>
  36 #include <linux/netdevice.h>
  37 #include <linux/ipv6.h>
  38 #include <linux/slab.h>
  39 #include <net/checksum.h>
  40 #include <net/ip6_checksum.h>
  41 #include <linux/net_tstamp.h>
  42 #include <linux/mii.h>
  43 #include <linux/ethtool.h>
  44 #include <linux/if.h>
  45 #include <linux/if_vlan.h>
  46 #include <linux/pci.h>
  47 #include <linux/pci-aspm.h>
  48 #include <linux/delay.h>
  49 #include <linux/interrupt.h>
  50 #include <linux/ip.h>
  51 #include <linux/tcp.h>
  52 #include <linux/sctp.h>
  53 #include <linux/if_ether.h>
  54 #include <linux/aer.h>
  55 #include <linux/prefetch.h>
  56 #include <linux/pm_runtime.h>
  57 #ifdef CONFIG_IGB_DCA
  58 #include <linux/dca.h>
  59 #endif
  60 #include <linux/i2c.h>
  61 #include "igb.h"
  62
  63 #define MAJ 5
  64 #define MIN 0
  65 #define BUILD 5
  66 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
  67 __stringify(BUILD) "-k"
  68 char igb_driver_name[] = "igb";
  69 char igb_driver_version[] = DRV_VERSION;
  70 static const char igb_driver_string[] =
  71                                 "Intel(R) Gigabit Ethernet Network Driver";
  72 static const char igb_copyright[] =
  73                                 "Copyright (c) 2007-2013 Intel Corporation.";
  74
  75 static const struct e1000_info *igb_info_tbl[] = {
  76         [board_82575] = &e1000_82575_info,
  77 };
  78
  79 static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
  80         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
  81         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
  82         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
  83         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
  84         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
  85         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
  86         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
  87         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
  88         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
  89         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
  90         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
  91         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
  92         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
  93         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
  94         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
  95         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
  96         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
  97         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
  98         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
  99         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
 100         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
 101         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
 102         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
 103         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
 104         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
 105         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
 106         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
 107         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
 108         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
 109         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
 110         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
 111         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
 112         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
 113         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
 114         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
 115         /* required last entry */
 116         {0, }
 117 };
 118
 119 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
 120
 121 void igb_reset(struct igb_adapter *);
 122 static int igb_setup_all_tx_resources(struct igb_adapter *);
 123 static int igb_setup_all_rx_resources(struct igb_adapter *);
 124 static void igb_free_all_tx_resources(struct igb_adapter *);
 125 static void igb_free_all_rx_resources(struct igb_adapter *);
 126 static void igb_setup_mrqc(struct igb_adapter *);
 127 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
 128 static void igb_remove(struct pci_dev *pdev);
 129 static int igb_sw_init(struct igb_adapter *);
 130 static int igb_open(struct net_device *);
 131 static int igb_close(struct net_device *);
 132 static void igb_configure(struct igb_adapter *);
 133 static void igb_configure_tx(struct igb_adapter *);
 134 static void igb_configure_rx(struct igb_adapter *);
 135 static void igb_clean_all_tx_rings(struct igb_adapter *);
 136 static void igb_clean_all_rx_rings(struct igb_adapter *);
 137 static void igb_clean_tx_ring(struct igb_ring *);
 138 static void igb_clean_rx_ring(struct igb_ring *);
 139 static void igb_set_rx_mode(struct net_device *);
 140 static void igb_update_phy_info(unsigned long);
 141 static void igb_watchdog(unsigned long);
 142 static void igb_watchdog_task(struct work_struct *);
 143 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
 144 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
 145                                                  struct rtnl_link_stats64 *stats);
 146 static int igb_change_mtu(struct net_device *, int);
 147 static int igb_set_mac(struct net_device *, void *);
 148 static void igb_set_uta(struct igb_adapter *adapter);
 149 static irqreturn_t igb_intr(int irq, void *);
 150 static irqreturn_t igb_intr_msi(int irq, void *);
 151 static irqreturn_t igb_msix_other(int irq, void *);
 152 static irqreturn_t igb_msix_ring(int irq, void *);
 153 #ifdef CONFIG_IGB_DCA
 154 static void igb_update_dca(struct igb_q_vector *);
 155 static void igb_setup_dca(struct igb_adapter *);
 156 #endif /* CONFIG_IGB_DCA */
 157 static int igb_poll(struct napi_struct *, int);
 158 static bool igb_clean_tx_irq(struct igb_q_vector *);
 159 static bool igb_clean_rx_irq(struct igb_q_vector *, int);
 160 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
 161 static void igb_tx_timeout(struct net_device *);
 162 static void igb_reset_task(struct work_struct *);
 163 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features);
 164 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
 165 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
 166 static void igb_restore_vlan(struct igb_adapter *);
 167 static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
 168 static void igb_ping_all_vfs(struct igb_adapter *);
 169 static void igb_msg_task(struct igb_adapter *);
 170 static void igb_vmm_control(struct igb_adapter *);
 171 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
 172 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
 173 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
 174 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
 175                                int vf, u16 vlan, u8 qos);
 176 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
 177 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
 178                                    bool setting);
 179 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
 180                                  struct ifla_vf_info *ivi);
 181 static void igb_check_vf_rate_limit(struct igb_adapter *);
 182
 183 #ifdef CONFIG_PCI_IOV
 184 static int igb_vf_configure(struct igb_adapter *adapter, int vf);
 185 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
 186 #endif
 187
 188 #ifdef CONFIG_PM
 189 #ifdef CONFIG_PM_SLEEP
 190 static int igb_suspend(struct device *);
 191 #endif
 192 static int igb_resume(struct device *);
 193 #ifdef CONFIG_PM_RUNTIME
 194 static int igb_runtime_suspend(struct device *dev);
 195 static int igb_runtime_resume(struct device *dev);
 196 static int igb_runtime_idle(struct device *dev);
 197 #endif
 198 static const struct dev_pm_ops igb_pm_ops = {
 199         SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
 200         SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
 201                         igb_runtime_idle)
 202 };
 203 #endif
 204 static void igb_shutdown(struct pci_dev *);
 205 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
 206 #ifdef CONFIG_IGB_DCA
 207 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
 208 static struct notifier_block dca_notifier = {
 209         .notifier_call  = igb_notify_dca,
 210         .next           = NULL,
 211         .priority       = 0
 212 };
 213 #endif
 214 #ifdef CONFIG_NET_POLL_CONTROLLER
 215 /* for netdump / net console */
 216 static void igb_netpoll(struct net_device *);
 217 #endif
 218 #ifdef CONFIG_PCI_IOV
 219 static unsigned int max_vfs = 0;
 220 module_param(max_vfs, uint, 0);
 221 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
 222                  "per physical function");
 223 #endif /* CONFIG_PCI_IOV */
 224
 225 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
 226                      pci_channel_state_t);
 227 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
 228 static void igb_io_resume(struct pci_dev *);
 229
 230 static const struct pci_error_handlers igb_err_handler = {
 231         .error_detected = igb_io_error_detected,
 232         .slot_reset = igb_io_slot_reset,
 233         .resume = igb_io_resume,
 234 };
 235
 236 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
 237
 238 static struct pci_driver igb_driver = {
 239         .name     = igb_driver_name,
 240         .id_table = igb_pci_tbl,
 241         .probe    = igb_probe,
 242         .remove   = igb_remove,
 243 #ifdef CONFIG_PM
 244         .driver.pm = &igb_pm_ops,
 245 #endif
 246         .shutdown = igb_shutdown,
 247         .sriov_configure = igb_pci_sriov_configure,
 248         .err_handler = &igb_err_handler
 249 };
 250
 251 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
 252 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
 253 MODULE_LICENSE("GPL");
 254 MODULE_VERSION(DRV_VERSION);
 255
 256 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
 257 static int debug = -1;
 258 module_param(debug, int, 0);
 259 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
 260
 261 struct igb_reg_info {
 262         u32 ofs;
 263         char *name;
 264 };
 265
 266 static const struct igb_reg_info igb_reg_info_tbl[] = {
 267
 268         /* General Registers */
 269         {E1000_CTRL, "CTRL"},
 270         {E1000_STATUS, "STATUS"},
 271         {E1000_CTRL_EXT, "CTRL_EXT"},
 272
 273         /* Interrupt Registers */
 274         {E1000_ICR, "ICR"},
 275
 276         /* RX Registers */
 277         {E1000_RCTL, "RCTL"},
 278         {E1000_RDLEN(0), "RDLEN"},
 279         {E1000_RDH(0), "RDH"},
 280         {E1000_RDT(0), "RDT"},
 281         {E1000_RXDCTL(0), "RXDCTL"},
 282         {E1000_RDBAL(0), "RDBAL"},
 283         {E1000_RDBAH(0), "RDBAH"},
 284
 285         /* TX Registers */
 286         {E1000_TCTL, "TCTL"},
 287         {E1000_TDBAL(0), "TDBAL"},
 288         {E1000_TDBAH(0), "TDBAH"},
 289         {E1000_TDLEN(0), "TDLEN"},
 290         {E1000_TDH(0), "TDH"},
 291         {E1000_TDT(0), "TDT"},
 292         {E1000_TXDCTL(0), "TXDCTL"},
 293         {E1000_TDFH, "TDFH"},
 294         {E1000_TDFT, "TDFT"},
 295         {E1000_TDFHS, "TDFHS"},
 296         {E1000_TDFPC, "TDFPC"},
 297
 298         /* List Terminator */
 299         {}
 300 };
 301
 302 /* igb_regdump - register printout routine */
 303 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
 304 {
 305         int n = 0;
 306         char rname[16];
 307         u32 regs[8];
 308
 309         switch (reginfo->ofs) {
 310         case E1000_RDLEN(0):
 311                 for (n = 0; n < 4; n++)
 312                         regs[n] = rd32(E1000_RDLEN(n));
 313                 break;
 314         case E1000_RDH(0):
 315                 for (n = 0; n < 4; n++)
 316                         regs[n] = rd32(E1000_RDH(n));
 317                 break;
 318         case E1000_RDT(0):
 319                 for (n = 0; n < 4; n++)
 320                         regs[n] = rd32(E1000_RDT(n));
 321                 break;
 322         case E1000_RXDCTL(0):
 323                 for (n = 0; n < 4; n++)
 324                         regs[n] = rd32(E1000_RXDCTL(n));
 325                 break;
 326         case E1000_RDBAL(0):
 327                 for (n = 0; n < 4; n++)
 328                         regs[n] = rd32(E1000_RDBAL(n));
 329                 break;
 330         case E1000_RDBAH(0):
 331                 for (n = 0; n < 4; n++)
 332                         regs[n] = rd32(E1000_RDBAH(n));
 333                 break;
 334         case E1000_TDBAL(0):
 335                 for (n = 0; n < 4; n++)
 336                         regs[n] = rd32(E1000_RDBAL(n));
 337                 break;
 338         case E1000_TDBAH(0):
 339                 for (n = 0; n < 4; n++)
 340                         regs[n] = rd32(E1000_TDBAH(n));
 341                 break;
 342         case E1000_TDLEN(0):
 343                 for (n = 0; n < 4; n++)
 344                         regs[n] = rd32(E1000_TDLEN(n));
 345                 break;
 346         case E1000_TDH(0):
 347                 for (n = 0; n < 4; n++)
 348                         regs[n] = rd32(E1000_TDH(n));
 349                 break;
 350         case E1000_TDT(0):
 351                 for (n = 0; n < 4; n++)
 352                         regs[n] = rd32(E1000_TDT(n));
 353                 break;
 354         case E1000_TXDCTL(0):
 355                 for (n = 0; n < 4; n++)
 356                         regs[n] = rd32(E1000_TXDCTL(n));
 357                 break;
 358         default:
 359                 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
 360                 return;
 361         }
 362
 363         snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
 364         pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
 365                 regs[2], regs[3]);
 366 }
 367
 368 /* igb_dump - Print registers, Tx-rings and Rx-rings */
 369 static void igb_dump(struct igb_adapter *adapter)
 370 {
 371         struct net_device *netdev = adapter->netdev;
 372         struct e1000_hw *hw = &adapter->hw;
 373         struct igb_reg_info *reginfo;
 374         struct igb_ring *tx_ring;
 375         union e1000_adv_tx_desc *tx_desc;
 376         struct my_u0 { u64 a; u64 b; } *u0;
 377         struct igb_ring *rx_ring;
 378         union e1000_adv_rx_desc *rx_desc;
 379         u32 staterr;
 380         u16 i, n;
 381
 382         if (!netif_msg_hw(adapter))
 383                 return;
 384
 385         /* Print netdevice Info */
 386         if (netdev) {
 387                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 388                 pr_info("Device Name     state            trans_start      "
 389                         "last_rx\n");
 390                 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
 391                         netdev->state, netdev->trans_start, netdev->last_rx);
 392         }
 393
 394         /* Print Registers */
 395         dev_info(&adapter->pdev->dev, "Register Dump\n");
 396         pr_info(" Register Name   Value\n");
 397         for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
 398              reginfo->name; reginfo++) {
 399                 igb_regdump(hw, reginfo);
 400         }
 401
 402         /* Print TX Ring Summary */
 403         if (!netdev || !netif_running(netdev))
 404                 goto exit;
 405
 406         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 407         pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
 408         for (n = 0; n < adapter->num_tx_queues; n++) {
 409                 struct igb_tx_buffer *buffer_info;
 410                 tx_ring = adapter->tx_ring[n];
 411                 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 412                 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
 413                         n, tx_ring->next_to_use, tx_ring->next_to_clean,
 414                         (u64)dma_unmap_addr(buffer_info, dma),
 415                         dma_unmap_len(buffer_info, len),
 416                         buffer_info->next_to_watch,
 417                         (u64)buffer_info->time_stamp);
 418         }
 419
 420         /* Print TX Rings */
 421         if (!netif_msg_tx_done(adapter))
 422                 goto rx_ring_summary;
 423
 424         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 425
 426         /* Transmit Descriptor Formats
 427          *
 428          * Advanced Transmit Descriptor
 429          *   +--------------------------------------------------------------+
 430          * 0 |         Buffer Address [63:0]                                |
 431          *   +--------------------------------------------------------------+
 432          * 8 | PAYLEN  | PORTS  |CC|IDX | STA | DCMD  |DTYP|MAC|RSV| DTALEN |
 433          *   +--------------------------------------------------------------+
 434          *   63      46 45    40 39 38 36 35 32 31   24             15       0
 435          */
 436
 437         for (n = 0; n < adapter->num_tx_queues; n++) {
 438                 tx_ring = adapter->tx_ring[n];
 439                 pr_info("------------------------------------\n");
 440                 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 441                 pr_info("------------------------------------\n");
 442                 pr_info("T [desc]     [address 63:0  ] [PlPOCIStDDM Ln] "
 443                         "[bi->dma       ] leng  ntw timestamp        "
 444                         "bi->skb\n");
 445
 446                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 447                         const char *next_desc;
 448                         struct igb_tx_buffer *buffer_info;
 449                         tx_desc = IGB_TX_DESC(tx_ring, i);
 450                         buffer_info = &tx_ring->tx_buffer_info[i];
 451                         u0 = (struct my_u0 *)tx_desc;
 452                         if (i == tx_ring->next_to_use &&
 453                             i == tx_ring->next_to_clean)
 454                                 next_desc = " NTC/U";
 455                         else if (i == tx_ring->next_to_use)
 456                                 next_desc = " NTU";
 457                         else if (i == tx_ring->next_to_clean)
 458                                 next_desc = " NTC";
 459                         else
 460                                 next_desc = "";
 461
 462                         pr_info("T [0x%03X]    %016llX %016llX %016llX"
 463                                 " %04X  %p %016llX %p%s\n", i,
 464                                 le64_to_cpu(u0->a),
 465                                 le64_to_cpu(u0->b),
 466                                 (u64)dma_unmap_addr(buffer_info, dma),
 467                                 dma_unmap_len(buffer_info, len),
 468                                 buffer_info->next_to_watch,
 469                                 (u64)buffer_info->time_stamp,
 470                                 buffer_info->skb, next_desc);
 471
 472                         if (netif_msg_pktdata(adapter) && buffer_info->skb)
 473                                 print_hex_dump(KERN_INFO, "",
 474                                         DUMP_PREFIX_ADDRESS,
 475                                         16, 1, buffer_info->skb->data,
 476                                         dma_unmap_len(buffer_info, len),
 477                                         true);
 478                 }
 479         }
 480
 481         /* Print RX Rings Summary */
 482 rx_ring_summary:
 483         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 484         pr_info("Queue [NTU] [NTC]\n");
 485         for (n = 0; n < adapter->num_rx_queues; n++) {
 486                 rx_ring = adapter->rx_ring[n];
 487                 pr_info(" %5d %5X %5X\n",
 488                         n, rx_ring->next_to_use, rx_ring->next_to_clean);
 489         }
 490
 491         /* Print RX Rings */
 492         if (!netif_msg_rx_status(adapter))
 493                 goto exit;
 494
 495         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 496
 497         /* Advanced Receive Descriptor (Read) Format
 498          *    63                                           1        0
 499          *    +-----------------------------------------------------+
 500          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 501          *    +----------------------------------------------+------+
 502          *  8 |       Header Buffer Address [63:1]           |  DD  |
 503          *    +-----------------------------------------------------+
 504          *
 505          *
 506          * Advanced Receive Descriptor (Write-Back) Format
 507          *
 508          *   63       48 47    32 31  30      21 20 17 16   4 3     0
 509          *   +------------------------------------------------------+
 510          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 511          *   | Checksum   Ident  |   |           |    | Type | Type |
 512          *   +------------------------------------------------------+
 513          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 514          *   +------------------------------------------------------+
 515          *   63       48 47    32 31            20 19               0
 516          */
 517
 518         for (n = 0; n < adapter->num_rx_queues; n++) {
 519                 rx_ring = adapter->rx_ring[n];
 520                 pr_info("------------------------------------\n");
 521                 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 522                 pr_info("------------------------------------\n");
 523                 pr_info("R  [desc]      [ PktBuf     A0] [  HeadBuf   DD] "
 524                         "[bi->dma       ] [bi->skb] <-- Adv Rx Read format\n");
 525                 pr_info("RWB[desc]      [PcsmIpSHl PtRs] [vl er S cks ln] -----"
 526                         "----------- [bi->skb] <-- Adv Rx Write-Back format\n");
 527
 528                 for (i = 0; i < rx_ring->count; i++) {
 529                         const char *next_desc;
 530                         struct igb_rx_buffer *buffer_info;
 531                         buffer_info = &rx_ring->rx_buffer_info[i];
 532                         rx_desc = IGB_RX_DESC(rx_ring, i);
 533                         u0 = (struct my_u0 *)rx_desc;
 534                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 535
 536                         if (i == rx_ring->next_to_use)
 537                                 next_desc = " NTU";
 538                         else if (i == rx_ring->next_to_clean)
 539                                 next_desc = " NTC";
 540                         else
 541                                 next_desc = "";
 542
 543                         if (staterr & E1000_RXD_STAT_DD) {
 544                                 /* Descriptor Done */
 545                                 pr_info("%s[0x%03X]     %016llX %016llX ---------------- %s\n",
 546                                         "RWB", i,
 547                                         le64_to_cpu(u0->a),
 548                                         le64_to_cpu(u0->b),
 549                                         next_desc);
 550                         } else {
 551                                 pr_info("%s[0x%03X]     %016llX %016llX %016llX %s\n",
 552                                         "R  ", i,
 553                                         le64_to_cpu(u0->a),
 554                                         le64_to_cpu(u0->b),
 555                                         (u64)buffer_info->dma,
 556                                         next_desc);
 557
 558                                 if (netif_msg_pktdata(adapter) &&
 559                                     buffer_info->dma && buffer_info->page) {
 560                                         print_hex_dump(KERN_INFO, "",
 561                                           DUMP_PREFIX_ADDRESS,
 562                                           16, 1,
 563                                           page_address(buffer_info->page) +
 564                                                       buffer_info->page_offset,
 565                                           IGB_RX_BUFSZ, true);
 566                                 }
 567                         }
 568                 }
 569         }
 570
 571 exit:
 572         return;
 573 }
 574
 575 /**
 576  *  igb_get_i2c_data - Reads the I2C SDA data bit
 577  *  @hw: pointer to hardware structure
 578  *  @i2cctl: Current value of I2CCTL register
 579  *
 580  *  Returns the I2C data bit value
 581  **/
 582 static int igb_get_i2c_data(void *data)
 583 {
 584         struct igb_adapter *adapter = (struct igb_adapter *)data;
 585         struct e1000_hw *hw = &adapter->hw;
 586         s32 i2cctl = rd32(E1000_I2CPARAMS);
 587
 588         return ((i2cctl & E1000_I2C_DATA_IN) != 0);
 589 }
 590
 591 /**
 592  *  igb_set_i2c_data - Sets the I2C data bit
 593  *  @data: pointer to hardware structure
 594  *  @state: I2C data value (0 or 1) to set
 595  *
 596  *  Sets the I2C data bit
 597  **/
 598 static void igb_set_i2c_data(void *data, int state)
 599 {
 600         struct igb_adapter *adapter = (struct igb_adapter *)data;
 601         struct e1000_hw *hw = &adapter->hw;
 602         s32 i2cctl = rd32(E1000_I2CPARAMS);
 603
 604         if (state)
 605                 i2cctl |= E1000_I2C_DATA_OUT;
 606         else
 607                 i2cctl &= ~E1000_I2C_DATA_OUT;
 608
 609         i2cctl &= ~E1000_I2C_DATA_OE_N;
 610         i2cctl |= E1000_I2C_CLK_OE_N;
 611         wr32(E1000_I2CPARAMS, i2cctl);
 612         wrfl();
 613
 614 }
 615
 616 /**
 617  *  igb_set_i2c_clk - Sets the I2C SCL clock
 618  *  @data: pointer to hardware structure
 619  *  @state: state to set clock
 620  *
 621  *  Sets the I2C clock line to state
 622  **/
 623 static void igb_set_i2c_clk(void *data, int state)
 624 {
 625         struct igb_adapter *adapter = (struct igb_adapter *)data;
 626         struct e1000_hw *hw = &adapter->hw;
 627         s32 i2cctl = rd32(E1000_I2CPARAMS);
 628
 629         if (state) {
 630                 i2cctl |= E1000_I2C_CLK_OUT;
 631                 i2cctl &= ~E1000_I2C_CLK_OE_N;
 632         } else {
 633                 i2cctl &= ~E1000_I2C_CLK_OUT;
 634                 i2cctl &= ~E1000_I2C_CLK_OE_N;
 635         }
 636         wr32(E1000_I2CPARAMS, i2cctl);
 637         wrfl();
 638 }
 639
 640 /**
 641  *  igb_get_i2c_clk - Gets the I2C SCL clock state
 642  *  @data: pointer to hardware structure
 643  *
 644  *  Gets the I2C clock state
 645  **/
 646 static int igb_get_i2c_clk(void *data)
 647 {
 648         struct igb_adapter *adapter = (struct igb_adapter *)data;
 649         struct e1000_hw *hw = &adapter->hw;
 650         s32 i2cctl = rd32(E1000_I2CPARAMS);
 651
 652         return ((i2cctl & E1000_I2C_CLK_IN) != 0);
 653 }
 654
 655 static const struct i2c_algo_bit_data igb_i2c_algo = {
 656         .setsda         = igb_set_i2c_data,
 657         .setscl         = igb_set_i2c_clk,
 658         .getsda         = igb_get_i2c_data,
 659         .getscl         = igb_get_i2c_clk,
 660         .udelay         = 5,
 661         .timeout        = 20,
 662 };
 663
 664 /**
 665  *  igb_get_hw_dev - return device
 666  *  @hw: pointer to hardware structure
 667  *
 668  *  used by hardware layer to print debugging information
 669  **/
 670 struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
 671 {
 672         struct igb_adapter *adapter = hw->back;
 673         return adapter->netdev;
 674 }
 675
 676 /**
 677  *  igb_init_module - Driver Registration Routine
 678  *
 679  *  igb_init_module is the first routine called when the driver is
 680  *  loaded. All it does is register with the PCI subsystem.
 681  **/
 682 static int __init igb_init_module(void)
 683 {
 684         int ret;
 685         pr_info("%s - version %s\n",
 686                igb_driver_string, igb_driver_version);
 687
 688         pr_info("%s\n", igb_copyright);
 689
 690 #ifdef CONFIG_IGB_DCA
 691         dca_register_notify(&dca_notifier);
 692 #endif
 693         ret = pci_register_driver(&igb_driver);
 694         return ret;
 695 }
 696
 697 module_init(igb_init_module);
 698
 699 /**
 700  *  igb_exit_module - Driver Exit Cleanup Routine
 701  *
 702  *  igb_exit_module is called just before the driver is removed
 703  *  from memory.
 704  **/
 705 static void __exit igb_exit_module(void)
 706 {
 707 #ifdef CONFIG_IGB_DCA
 708         dca_unregister_notify(&dca_notifier);
 709 #endif
 710         pci_unregister_driver(&igb_driver);
 711 }
 712
 713 module_exit(igb_exit_module);
 714
 715 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
 716 /**
 717  *  igb_cache_ring_register - Descriptor ring to register mapping
 718  *  @adapter: board private structure to initialize
 719  *
 720  *  Once we know the feature-set enabled for the device, we'll cache
 721  *  the register offset the descriptor ring is assigned to.
 722  **/
 723 static void igb_cache_ring_register(struct igb_adapter *adapter)
 724 {
 725         int i = 0, j = 0;
 726         u32 rbase_offset = adapter->vfs_allocated_count;
 727
 728         switch (adapter->hw.mac.type) {
 729         case e1000_82576:
 730                 /* The queues are allocated for virtualization such that VF 0
 731                  * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
 732                  * In order to avoid collision we start at the first free queue
 733                  * and continue consuming queues in the same sequence
 734                  */
 735                 if (adapter->vfs_allocated_count) {
 736                         for (; i < adapter->rss_queues; i++)
 737                                 adapter->rx_ring[i]->reg_idx = rbase_offset +
 738                                                                Q_IDX_82576(i);
 739                 }
 740         case e1000_82575:
 741         case e1000_82580:
 742         case e1000_i350:
 743         case e1000_i354:
 744         case e1000_i210:
 745         case e1000_i211:
 746         default:
 747                 for (; i < adapter->num_rx_queues; i++)
 748                         adapter->rx_ring[i]->reg_idx = rbase_offset + i;
 749                 for (; j < adapter->num_tx_queues; j++)
 750                         adapter->tx_ring[j]->reg_idx = rbase_offset + j;
 751                 break;
 752         }
 753 }
 754
 755 /**
 756  *  igb_write_ivar - configure ivar for given MSI-X vector
 757  *  @hw: pointer to the HW structure
 758  *  @msix_vector: vector number we are allocating to a given ring
 759  *  @index: row index of IVAR register to write within IVAR table
 760  *  @offset: column offset of in IVAR, should be multiple of 8
 761  *
 762  *  This function is intended to handle the writing of the IVAR register
 763  *  for adapters 82576 and newer.  The IVAR table consists of 2 columns,
 764  *  each containing an cause allocation for an Rx and Tx ring, and a
 765  *  variable number of rows depending on the number of queues supported.
 766  **/
 767 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
 768                            int index, int offset)
 769 {
 770         u32 ivar = array_rd32(E1000_IVAR0, index);
 771
 772         /* clear any bits that are currently set */
 773         ivar &= ~((u32)0xFF << offset);
 774
 775         /* write vector and valid bit */
 776         ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
 777
 778         array_wr32(E1000_IVAR0, index, ivar);
 779 }
 780
 781 #define IGB_N0_QUEUE -1
 782 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
 783 {
 784         struct igb_adapter *adapter = q_vector->adapter;
 785         struct e1000_hw *hw = &adapter->hw;
 786         int rx_queue = IGB_N0_QUEUE;
 787         int tx_queue = IGB_N0_QUEUE;
 788         u32 msixbm = 0;
 789
 790         if (q_vector->rx.ring)
 791                 rx_queue = q_vector->rx.ring->reg_idx;
 792         if (q_vector->tx.ring)
 793                 tx_queue = q_vector->tx.ring->reg_idx;
 794
 795         switch (hw->mac.type) {
 796         case e1000_82575:
 797                 /* The 82575 assigns vectors using a bitmask, which matches the
 798                  * bitmask for the EICR/EIMS/EIMC registers.  To assign one
 799                  * or more queues to a vector, we write the appropriate bits
 800                  * into the MSIXBM register for that vector.
 801                  */
 802                 if (rx_queue > IGB_N0_QUEUE)
 803                         msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
 804                 if (tx_queue > IGB_N0_QUEUE)
 805                         msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
 806                 if (!adapter->msix_entries && msix_vector == 0)
 807                         msixbm |= E1000_EIMS_OTHER;
 808                 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
 809                 q_vector->eims_value = msixbm;
 810                 break;
 811         case e1000_82576:
 812                 /* 82576 uses a table that essentially consists of 2 columns
 813                  * with 8 rows.  The ordering is column-major so we use the
 814                  * lower 3 bits as the row index, and the 4th bit as the
 815                  * column offset.
 816                  */
 817                 if (rx_queue > IGB_N0_QUEUE)
 818                         igb_write_ivar(hw, msix_vector,
 819                                        rx_queue & 0x7,
 820                                        (rx_queue & 0x8) << 1);
 821                 if (tx_queue > IGB_N0_QUEUE)
 822                         igb_write_ivar(hw, msix_vector,
 823                                        tx_queue & 0x7,
 824                                        ((tx_queue & 0x8) << 1) + 8);
 825                 q_vector->eims_value = 1 << msix_vector;
 826                 break;
 827         case e1000_82580:
 828         case e1000_i350:
 829         case e1000_i354:
 830         case e1000_i210:
 831         case e1000_i211:
 832                 /* On 82580 and newer adapters the scheme is similar to 82576
 833                  * however instead of ordering column-major we have things
 834                  * ordered row-major.  So we traverse the table by using
 835                  * bit 0 as the column offset, and the remaining bits as the
 836                  * row index.
 837                  */
 838                 if (rx_queue > IGB_N0_QUEUE)
 839                         igb_write_ivar(hw, msix_vector,
 840                                        rx_queue >> 1,
 841                                        (rx_queue & 0x1) << 4);
 842                 if (tx_queue > IGB_N0_QUEUE)
 843                         igb_write_ivar(hw, msix_vector,
 844                                        tx_queue >> 1,
 845                                        ((tx_queue & 0x1) << 4) + 8);
 846                 q_vector->eims_value = 1 << msix_vector;
 847                 break;
 848         default:
 849                 BUG();
 850                 break;
 851         }
 852
 853         /* add q_vector eims value to global eims_enable_mask */
 854         adapter->eims_enable_mask |= q_vector->eims_value;
 855
 856         /* configure q_vector to set itr on first interrupt */
 857         q_vector->set_itr = 1;
 858 }
 859
 860 /**
 861  *  igb_configure_msix - Configure MSI-X hardware
 862  *  @adapter: board private structure to initialize
 863  *
 864  *  igb_configure_msix sets up the hardware to properly
 865  *  generate MSI-X interrupts.
 866  **/
 867 static void igb_configure_msix(struct igb_adapter *adapter)
 868 {
 869         u32 tmp;
 870         int i, vector = 0;
 871         struct e1000_hw *hw = &adapter->hw;
 872
 873         adapter->eims_enable_mask = 0;
 874
 875         /* set vector for other causes, i.e. link changes */
 876         switch (hw->mac.type) {
 877         case e1000_82575:
 878                 tmp = rd32(E1000_CTRL_EXT);
 879                 /* enable MSI-X PBA support*/
 880                 tmp |= E1000_CTRL_EXT_PBA_CLR;
 881
 882                 /* Auto-Mask interrupts upon ICR read. */
 883                 tmp |= E1000_CTRL_EXT_EIAME;
 884                 tmp |= E1000_CTRL_EXT_IRCA;
 885
 886                 wr32(E1000_CTRL_EXT, tmp);
 887
 888                 /* enable msix_other interrupt */
 889                 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
 890                 adapter->eims_other = E1000_EIMS_OTHER;
 891
 892                 break;
 893
 894         case e1000_82576:
 895         case e1000_82580:
 896         case e1000_i350:
 897         case e1000_i354:
 898         case e1000_i210:
 899         case e1000_i211:
 900                 /* Turn on MSI-X capability first, or our settings
 901                  * won't stick.  And it will take days to debug.
 902                  */
 903                 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
 904                      E1000_GPIE_PBA | E1000_GPIE_EIAME |
 905                      E1000_GPIE_NSICR);
 906
 907                 /* enable msix_other interrupt */
 908                 adapter->eims_other = 1 << vector;
 909                 tmp = (vector++ | E1000_IVAR_VALID) << 8;
 910
 911                 wr32(E1000_IVAR_MISC, tmp);
 912                 break;
 913         default:
 914                 /* do nothing, since nothing else supports MSI-X */
 915                 break;
 916         } /* switch (hw->mac.type) */
 917
 918         adapter->eims_enable_mask |= adapter->eims_other;
 919
 920         for (i = 0; i < adapter->num_q_vectors; i++)
 921                 igb_assign_vector(adapter->q_vector[i], vector++);
 922
 923         wrfl();
 924 }
 925
 926 /**
 927  *  igb_request_msix - Initialize MSI-X interrupts
 928  *  @adapter: board private structure to initialize
 929  *
 930  *  igb_request_msix allocates MSI-X vectors and requests interrupts from the
 931  *  kernel.
 932  **/
 933 static int igb_request_msix(struct igb_adapter *adapter)
 934 {
 935         struct net_device *netdev = adapter->netdev;
 936         struct e1000_hw *hw = &adapter->hw;
 937         int i, err = 0, vector = 0, free_vector = 0;
 938
 939         err = request_irq(adapter->msix_entries[vector].vector,
 940                           igb_msix_other, 0, netdev->name, adapter);
 941         if (err)
 942                 goto err_out;
 943
 944         for (i = 0; i < adapter->num_q_vectors; i++) {
 945                 struct igb_q_vector *q_vector = adapter->q_vector[i];
 946
 947                 vector++;
 948
 949                 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
 950
 951                 if (q_vector->rx.ring && q_vector->tx.ring)
 952                         sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
 953                                 q_vector->rx.ring->queue_index);
 954                 else if (q_vector->tx.ring)
 955                         sprintf(q_vector->name, "%s-tx-%u", netdev->name,
 956                                 q_vector->tx.ring->queue_index);
 957                 else if (q_vector->rx.ring)
 958                         sprintf(q_vector->name, "%s-rx-%u", netdev->name,
 959                                 q_vector->rx.ring->queue_index);
 960                 else
 961                         sprintf(q_vector->name, "%s-unused", netdev->name);
 962
 963                 err = request_irq(adapter->msix_entries[vector].vector,
 964                                   igb_msix_ring, 0, q_vector->name,
 965                                   q_vector);
 966                 if (err)
 967                         goto err_free;
 968         }
 969
 970         igb_configure_msix(adapter);
 971         return 0;
 972
 973 err_free:
 974         /* free already assigned IRQs */
 975         free_irq(adapter->msix_entries[free_vector++].vector, adapter);
 976
 977         vector--;
 978         for (i = 0; i < vector; i++) {
 979                 free_irq(adapter->msix_entries[free_vector++].vector,
 980                          adapter->q_vector[i]);
 981         }
 982 err_out:
 983         return err;
 984 }
 985
 986 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
 987 {
 988         if (adapter->msix_entries) {
 989                 pci_disable_msix(adapter->pdev);
 990                 kfree(adapter->msix_entries);
 991                 adapter->msix_entries = NULL;
 992         } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
 993                 pci_disable_msi(adapter->pdev);
 994         }
 995 }
 996
 997 /**
 998  *  igb_free_q_vector - Free memory allocated for specific interrupt vector
 999  *  @adapter: board private structure to initialize
1000  *  @v_idx: Index of vector to be freed
1001  *
1002  *  This function frees the memory allocated to the q_vector.  In addition if
1003  *  NAPI is enabled it will delete any references to the NAPI struct prior
1004  *  to freeing the q_vector.
1005  **/
1006 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1007 {
1008         struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1009
1010         if (q_vector->tx.ring)
1011                 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1012
1013         if (q_vector->rx.ring)
1014                 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL;
1015
1016         adapter->q_vector[v_idx] = NULL;
1017         netif_napi_del(&q_vector->napi);
1018
1019         /* igb_get_stats64() might access the rings on this vector,
1020          * we must wait a grace period before freeing it.
1021          */
1022         kfree_rcu(q_vector, rcu);
1023 }
1024
1025 /**
1026  *  igb_free_q_vectors - Free memory allocated for interrupt vectors
1027  *  @adapter: board private structure to initialize
1028  *
1029  *  This function frees the memory allocated to the q_vectors.  In addition if
1030  *  NAPI is enabled it will delete any references to the NAPI struct prior
1031  *  to freeing the q_vector.
1032  **/
1033 static void igb_free_q_vectors(struct igb_adapter *adapter)
1034 {
1035         int v_idx = adapter->num_q_vectors;
1036
1037         adapter->num_tx_queues = 0;
1038         adapter->num_rx_queues = 0;
1039         adapter->num_q_vectors = 0;
1040
1041         while (v_idx--)
1042                 igb_free_q_vector(adapter, v_idx);
1043 }
1044
1045 /**
1046  *  igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1047  *  @adapter: board private structure to initialize
1048  *
1049  *  This function resets the device so that it has 0 Rx queues, Tx queues, and
1050  *  MSI-X interrupts allocated.
1051  */
1052 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1053 {
1054         igb_free_q_vectors(adapter);
1055         igb_reset_interrupt_capability(adapter);
1056 }
1057
1058 /**
1059  *  igb_set_interrupt_capability - set MSI or MSI-X if supported
1060  *  @adapter: board private structure to initialize
1061  *  @msix: boolean value of MSIX capability
1062  *
1063  *  Attempt to configure interrupts using the best available
1064  *  capabilities of the hardware and kernel.
1065  **/
1066 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
1067 {
1068         int err;
1069         int numvecs, i;
1070
1071         if (!msix)
1072                 goto msi_only;
1073
1074         /* Number of supported queues. */
1075         adapter->num_rx_queues = adapter->rss_queues;
1076         if (adapter->vfs_allocated_count)
1077                 adapter->num_tx_queues = 1;
1078         else
1079                 adapter->num_tx_queues = adapter->rss_queues;
1080
1081         /* start with one vector for every Rx queue */
1082         numvecs = adapter->num_rx_queues;
1083
1084         /* if Tx handler is separate add 1 for every Tx queue */
1085         if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1086                 numvecs += adapter->num_tx_queues;
1087
1088         /* store the number of vectors reserved for queues */
1089         adapter->num_q_vectors = numvecs;
1090
1091         /* add 1 vector for link status interrupts */
1092         numvecs++;
1093         adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
1094                                         GFP_KERNEL);
1095
1096         if (!adapter->msix_entries)
1097                 goto msi_only;
1098
1099         for (i = 0; i < numvecs; i++)
1100                 adapter->msix_entries[i].entry = i;
1101
1102         err = pci_enable_msix(adapter->pdev,
1103                               adapter->msix_entries,
1104                               numvecs);
1105         if (err == 0)
1106                 return;
1107
1108         igb_reset_interrupt_capability(adapter);
1109
1110         /* If we can't do MSI-X, try MSI */
1111 msi_only:
1112 #ifdef CONFIG_PCI_IOV
1113         /* disable SR-IOV for non MSI-X configurations */
1114         if (adapter->vf_data) {
1115                 struct e1000_hw *hw = &adapter->hw;
1116                 /* disable iov and allow time for transactions to clear */
1117                 pci_disable_sriov(adapter->pdev);
1118                 msleep(500);
1119
1120                 kfree(adapter->vf_data);
1121                 adapter->vf_data = NULL;
1122                 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1123                 wrfl();
1124                 msleep(100);
1125                 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1126         }
1127 #endif
1128         adapter->vfs_allocated_count = 0;
1129         adapter->rss_queues = 1;
1130         adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
1131         adapter->num_rx_queues = 1;
1132         adapter->num_tx_queues = 1;
1133         adapter->num_q_vectors = 1;
1134         if (!pci_enable_msi(adapter->pdev))
1135                 adapter->flags |= IGB_FLAG_HAS_MSI;
1136 }
1137
1138 static void igb_add_ring(struct igb_ring *ring,
1139                          struct igb_ring_container *head)
1140 {
1141         head->ring = ring;
1142         head->count++;
1143 }
1144
1145 /**
1146  *  igb_alloc_q_vector - Allocate memory for a single interrupt vector
1147  *  @adapter: board private structure to initialize
1148  *  @v_count: q_vectors allocated on adapter, used for ring interleaving
1149  *  @v_idx: index of vector in adapter struct
1150  *  @txr_count: total number of Tx rings to allocate
1151  *  @txr_idx: index of first Tx ring to allocate
1152  *  @rxr_count: total number of Rx rings to allocate
1153  *  @rxr_idx: index of first Rx ring to allocate
1154  *
1155  *  We allocate one q_vector.  If allocation fails we return -ENOMEM.
1156  **/
1157 static int igb_alloc_q_vector(struct igb_adapter *adapter,
1158                               int v_count, int v_idx,
1159                               int txr_count, int txr_idx,
1160                               int rxr_count, int rxr_idx)
1161 {
1162         struct igb_q_vector *q_vector;
1163         struct igb_ring *ring;
1164         int ring_count, size;
1165
1166         /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1167         if (txr_count > 1 || rxr_count > 1)
1168                 return -ENOMEM;
1169
1170         ring_count = txr_count + rxr_count;
1171         size = sizeof(struct igb_q_vector) +
1172                (sizeof(struct igb_ring) * ring_count);
1173
1174         /* allocate q_vector and rings */
1175         q_vector = kzalloc(size, GFP_KERNEL);
1176         if (!q_vector)
1177                 return -ENOMEM;
1178
1179         /* initialize NAPI */
1180         netif_napi_add(adapter->netdev, &q_vector->napi,
1181                        igb_poll, 64);
1182
1183         /* tie q_vector and adapter together */
1184         adapter->q_vector[v_idx] = q_vector;
1185         q_vector->adapter = adapter;
1186
1187         /* initialize work limits */
1188         q_vector->tx.work_limit = adapter->tx_work_limit;
1189
1190         /* initialize ITR configuration */
1191         q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1192         q_vector->itr_val = IGB_START_ITR;
1193
1194         /* initialize pointer to rings */
1195         ring = q_vector->ring;
1196
1197         /* intialize ITR */
1198         if (rxr_count) {
1199                 /* rx or rx/tx vector */
1200                 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1201                         q_vector->itr_val = adapter->rx_itr_setting;
1202         } else {
1203                 /* tx only vector */
1204                 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1205                         q_vector->itr_val = adapter->tx_itr_setting;
1206         }
1207
1208         if (txr_count) {
1209                 /* assign generic ring traits */
1210                 ring->dev = &adapter->pdev->dev;
1211                 ring->netdev = adapter->netdev;
1212
1213                 /* configure backlink on ring */
1214                 ring->q_vector = q_vector;
1215
1216                 /* update q_vector Tx values */
1217                 igb_add_ring(ring, &q_vector->tx);
1218
1219                 /* For 82575, context index must be unique per ring. */
1220                 if (adapter->hw.mac.type == e1000_82575)
1221                         set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1222
1223                 /* apply Tx specific ring traits */
1224                 ring->count = adapter->tx_ring_count;
1225                 ring->queue_index = txr_idx;
1226
1227                 /* assign ring to adapter */
1228                 adapter->tx_ring[txr_idx] = ring;
1229
1230                 /* push pointer to next ring */
1231                 ring++;
1232         }
1233
1234         if (rxr_count) {
1235                 /* assign generic ring traits */
1236                 ring->dev = &adapter->pdev->dev;
1237                 ring->netdev = adapter->netdev;
1238
1239                 /* configure backlink on ring */
1240                 ring->q_vector = q_vector;
1241
1242                 /* update q_vector Rx values */
1243                 igb_add_ring(ring, &q_vector->rx);
1244
1245                 /* set flag indicating ring supports SCTP checksum offload */
1246                 if (adapter->hw.mac.type >= e1000_82576)
1247                         set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
1248
1249                 /*
1250                  * On i350, i354, i210, and i211, loopback VLAN packets
1251                  * have the tag byte-swapped.
1252                  */
1253                 if (adapter->hw.mac.type >= e1000_i350)
1254                         set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
1255
1256                 /* apply Rx specific ring traits */
1257                 ring->count = adapter->rx_ring_count;
1258                 ring->queue_index = rxr_idx;
1259
1260                 /* assign ring to adapter */
1261                 adapter->rx_ring[rxr_idx] = ring;
1262         }
1263
1264         return 0;
1265 }
1266
1267
1268 /**
1269  *  igb_alloc_q_vectors - Allocate memory for interrupt vectors
1270  *  @adapter: board private structure to initialize
1271  *
1272  *  We allocate one q_vector per queue interrupt.  If allocation fails we
1273  *  return -ENOMEM.
1274  **/
1275 static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1276 {
1277         int q_vectors = adapter->num_q_vectors;
1278         int rxr_remaining = adapter->num_rx_queues;
1279         int txr_remaining = adapter->num_tx_queues;
1280         int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1281         int err;
1282
1283         if (q_vectors >= (rxr_remaining + txr_remaining)) {
1284                 for (; rxr_remaining; v_idx++) {
1285                         err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1286                                                  0, 0, 1, rxr_idx);
1287
1288                         if (err)
1289                                 goto err_out;
1290
1291                         /* update counts and index */
1292                         rxr_remaining--;
1293                         rxr_idx++;
1294                 }
1295         }
1296
1297         for (; v_idx < q_vectors; v_idx++) {
1298                 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1299                 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1300                 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1301                                          tqpv, txr_idx, rqpv, rxr_idx);
1302
1303                 if (err)
1304                         goto err_out;
1305
1306                 /* update counts and index */
1307                 rxr_remaining -= rqpv;
1308                 txr_remaining -= tqpv;
1309                 rxr_idx++;
1310                 txr_idx++;
1311         }
1312
1313         return 0;
1314
1315 err_out:
1316         adapter->num_tx_queues = 0;
1317         adapter->num_rx_queues = 0;
1318         adapter->num_q_vectors = 0;
1319
1320         while (v_idx--)
1321                 igb_free_q_vector(adapter, v_idx);
1322
1323         return -ENOMEM;
1324 }
1325
1326 /**
1327  *  igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1328  *  @adapter: board private structure to initialize
1329  *  @msix: boolean value of MSIX capability
1330  *
1331  *  This function initializes the interrupts and allocates all of the queues.
1332  **/
1333 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
1334 {
1335         struct pci_dev *pdev = adapter->pdev;
1336         int err;
1337
1338         igb_set_interrupt_capability(adapter, msix);
1339
1340         err = igb_alloc_q_vectors(adapter);
1341         if (err) {
1342                 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1343                 goto err_alloc_q_vectors;
1344         }
1345
1346         igb_cache_ring_register(adapter);
1347
1348         return 0;
1349
1350 err_alloc_q_vectors:
1351         igb_reset_interrupt_capability(adapter);
1352         return err;
1353 }
1354
1355 /**
1356  *  igb_request_irq - initialize interrupts
1357  *  @adapter: board private structure to initialize
1358  *
1359  *  Attempts to configure interrupts using the best available
1360  *  capabilities of the hardware and kernel.
1361  **/
1362 static int igb_request_irq(struct igb_adapter *adapter)
1363 {
1364         struct net_device *netdev = adapter->netdev;
1365         struct pci_dev *pdev = adapter->pdev;
1366         int err = 0;
1367
1368         if (adapter->msix_entries) {
1369                 err = igb_request_msix(adapter);
1370                 if (!err)
1371                         goto request_done;
1372                 /* fall back to MSI */
1373                 igb_free_all_tx_resources(adapter);
1374                 igb_free_all_rx_resources(adapter);
1375
1376                 igb_clear_interrupt_scheme(adapter);
1377                 err = igb_init_interrupt_scheme(adapter, false);
1378                 if (err)
1379                         goto request_done;
1380
1381                 igb_setup_all_tx_resources(adapter);
1382                 igb_setup_all_rx_resources(adapter);
1383                 igb_configure(adapter);
1384         }
1385
1386         igb_assign_vector(adapter->q_vector[0], 0);
1387
1388         if (adapter->flags & IGB_FLAG_HAS_MSI) {
1389                 err = request_irq(pdev->irq, igb_intr_msi, 0,
1390                                   netdev->name, adapter);
1391                 if (!err)
1392                         goto request_done;
1393
1394                 /* fall back to legacy interrupts */
1395                 igb_reset_interrupt_capability(adapter);
1396                 adapter->flags &= ~IGB_FLAG_HAS_MSI;
1397         }
1398
1399         err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
1400                           netdev->name, adapter);
1401
1402         if (err)
1403                 dev_err(&pdev->dev, "Error %d getting interrupt\n",
1404                         err);
1405
1406 request_done:
1407         return err;
1408 }
1409
1410 static void igb_free_irq(struct igb_adapter *adapter)
1411 {
1412         if (adapter->msix_entries) {
1413                 int vector = 0, i;
1414
1415                 free_irq(adapter->msix_entries[vector++].vector, adapter);
1416
1417                 for (i = 0; i < adapter->num_q_vectors; i++)
1418                         free_irq(adapter->msix_entries[vector++].vector,
1419                                  adapter->q_vector[i]);
1420         } else {
1421                 free_irq(adapter->pdev->irq, adapter);
1422         }
1423 }
1424
1425 /**
1426  *  igb_irq_disable - Mask off interrupt generation on the NIC
1427  *  @adapter: board private structure
1428  **/
1429 static void igb_irq_disable(struct igb_adapter *adapter)
1430 {
1431         struct e1000_hw *hw = &adapter->hw;
1432
1433         /* we need to be careful when disabling interrupts.  The VFs are also
1434          * mapped into these registers and so clearing the bits can cause
1435          * issues on the VF drivers so we only need to clear what we set
1436          */
1437         if (adapter->msix_entries) {
1438                 u32 regval = rd32(E1000_EIAM);
1439                 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1440                 wr32(E1000_EIMC, adapter->eims_enable_mask);
1441                 regval = rd32(E1000_EIAC);
1442                 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
1443         }
1444
1445         wr32(E1000_IAM, 0);
1446         wr32(E1000_IMC, ~0);
1447         wrfl();
1448         if (adapter->msix_entries) {
1449                 int i;
1450                 for (i = 0; i < adapter->num_q_vectors; i++)
1451                         synchronize_irq(adapter->msix_entries[i].vector);
1452         } else {
1453                 synchronize_irq(adapter->pdev->irq);
1454         }
1455 }
1456
1457 /**
1458  *  igb_irq_enable - Enable default interrupt generation settings
1459  *  @adapter: board private structure
1460  **/
1461 static void igb_irq_enable(struct igb_adapter *adapter)
1462 {
1463         struct e1000_hw *hw = &adapter->hw;
1464
1465         if (adapter->msix_entries) {
1466                 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
1467                 u32 regval = rd32(E1000_EIAC);
1468                 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1469                 regval = rd32(E1000_EIAM);
1470                 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
1471                 wr32(E1000_EIMS, adapter->eims_enable_mask);
1472                 if (adapter->vfs_allocated_count) {
1473                         wr32(E1000_MBVFIMR, 0xFF);
1474                         ims |= E1000_IMS_VMMB;
1475                 }
1476                 wr32(E1000_IMS, ims);
1477         } else {
1478                 wr32(E1000_IMS, IMS_ENABLE_MASK |
1479                                 E1000_IMS_DRSTA);
1480                 wr32(E1000_IAM, IMS_ENABLE_MASK |
1481                                 E1000_IMS_DRSTA);
1482         }
1483 }
1484
1485 static void igb_update_mng_vlan(struct igb_adapter *adapter)
1486 {
1487         struct e1000_hw *hw = &adapter->hw;
1488         u16 vid = adapter->hw.mng_cookie.vlan_id;
1489         u16 old_vid = adapter->mng_vlan_id;
1490
1491         if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1492                 /* add VID to filter table */
1493                 igb_vfta_set(hw, vid, true);
1494                 adapter->mng_vlan_id = vid;
1495         } else {
1496                 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1497         }
1498
1499         if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1500             (vid != old_vid) &&
1501             !test_bit(old_vid, adapter->active_vlans)) {
1502                 /* remove VID from filter table */
1503                 igb_vfta_set(hw, old_vid, false);
1504         }
1505 }
1506
1507 /**
1508  *  igb_release_hw_control - release control of the h/w to f/w
1509  *  @adapter: address of board private structure
1510  *
1511  *  igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1512  *  For ASF and Pass Through versions of f/w this means that the
1513  *  driver is no longer loaded.
1514  **/
1515 static void igb_release_hw_control(struct igb_adapter *adapter)
1516 {
1517         struct e1000_hw *hw = &adapter->hw;
1518         u32 ctrl_ext;
1519
1520         /* Let firmware take over control of h/w */
1521         ctrl_ext = rd32(E1000_CTRL_EXT);
1522         wr32(E1000_CTRL_EXT,
1523                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1524 }
1525
1526 /**
1527  *  igb_get_hw_control - get control of the h/w from f/w
1528  *  @adapter: address of board private structure
1529  *
1530  *  igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1531  *  For ASF and Pass Through versions of f/w this means that
1532  *  the driver is loaded.
1533  **/
1534 static void igb_get_hw_control(struct igb_adapter *adapter)
1535 {
1536         struct e1000_hw *hw = &adapter->hw;
1537         u32 ctrl_ext;
1538
1539         /* Let firmware know the driver has taken over */
1540         ctrl_ext = rd32(E1000_CTRL_EXT);
1541         wr32(E1000_CTRL_EXT,
1542                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1543 }
1544
1545 /**
1546  *  igb_configure - configure the hardware for RX and TX
1547  *  @adapter: private board structure
1548  **/
1549 static void igb_configure(struct igb_adapter *adapter)
1550 {
1551         struct net_device *netdev = adapter->netdev;
1552         int i;
1553
1554         igb_get_hw_control(adapter);
1555         igb_set_rx_mode(netdev);
1556
1557         igb_restore_vlan(adapter);
1558
1559         igb_setup_tctl(adapter);
1560         igb_setup_mrqc(adapter);
1561         igb_setup_rctl(adapter);
1562
1563         igb_configure_tx(adapter);
1564         igb_configure_rx(adapter);
1565
1566         igb_rx_fifo_flush_82575(&adapter->hw);
1567
1568         /* call igb_desc_unused which always leaves
1569          * at least 1 descriptor unused to make sure
1570          * next_to_use != next_to_clean
1571          */
1572         for (i = 0; i < adapter->num_rx_queues; i++) {
1573                 struct igb_ring *ring = adapter->rx_ring[i];
1574                 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
1575         }
1576 }
1577
1578 /**
1579  *  igb_power_up_link - Power up the phy/serdes link
1580  *  @adapter: address of board private structure
1581  **/
1582 void igb_power_up_link(struct igb_adapter *adapter)
1583 {
1584         igb_reset_phy(&adapter->hw);
1585
1586         if (adapter->hw.phy.media_type == e1000_media_type_copper)
1587                 igb_power_up_phy_copper(&adapter->hw);
1588         else
1589                 igb_power_up_serdes_link_82575(&adapter->hw);
1590 }
1591
1592 /**
1593  *  igb_power_down_link - Power down the phy/serdes link
1594  *  @adapter: address of board private structure
1595  */
1596 static void igb_power_down_link(struct igb_adapter *adapter)
1597 {
1598         if (adapter->hw.phy.media_type == e1000_media_type_copper)
1599                 igb_power_down_phy_copper_82575(&adapter->hw);
1600         else
1601                 igb_shutdown_serdes_link_82575(&adapter->hw);
1602 }
1603
1604 /**
1605  *  igb_up - Open the interface and prepare it to handle traffic
1606  *  @adapter: board private structure
1607  **/
1608 int igb_up(struct igb_adapter *adapter)
1609 {
1610         struct e1000_hw *hw = &adapter->hw;
1611         int i;
1612
1613         /* hardware has been reset, we need to reload some things */
1614         igb_configure(adapter);
1615
1616         clear_bit(__IGB_DOWN, &adapter->state);
1617
1618         for (i = 0; i < adapter->num_q_vectors; i++)
1619                 napi_enable(&(adapter->q_vector[i]->napi));
1620
1621         if (adapter->msix_entries)
1622                 igb_configure_msix(adapter);
1623         else
1624                 igb_assign_vector(adapter->q_vector[0], 0);
1625
1626         /* Clear any pending interrupts. */
1627         rd32(E1000_ICR);
1628         igb_irq_enable(adapter);
1629
1630         /* notify VFs that reset has been completed */
1631         if (adapter->vfs_allocated_count) {
1632                 u32 reg_data = rd32(E1000_CTRL_EXT);
1633                 reg_data |= E1000_CTRL_EXT_PFRSTD;
1634                 wr32(E1000_CTRL_EXT, reg_data);
1635         }
1636
1637         netif_tx_start_all_queues(adapter->netdev);
1638
1639         /* start the watchdog. */
1640         hw->mac.get_link_status = 1;
1641         schedule_work(&adapter->watchdog_task);
1642
1643         return 0;
1644 }
1645
1646 void igb_down(struct igb_adapter *adapter)
1647 {
1648         struct net_device *netdev = adapter->netdev;
1649         struct e1000_hw *hw = &adapter->hw;
1650         u32 tctl, rctl;
1651         int i;
1652
1653         /* signal that we're down so the interrupt handler does not
1654          * reschedule our watchdog timer
1655          */
1656         set_bit(__IGB_DOWN, &adapter->state);
1657
1658         /* disable receives in the hardware */
1659         rctl = rd32(E1000_RCTL);
1660         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1661         /* flush and sleep below */
1662
1663         netif_tx_stop_all_queues(netdev);
1664
1665         /* disable transmits in the hardware */
1666         tctl = rd32(E1000_TCTL);
1667         tctl &= ~E1000_TCTL_EN;
1668         wr32(E1000_TCTL, tctl);
1669         /* flush both disables and wait for them to finish */
1670         wrfl();
1671         msleep(10);
1672
1673         igb_irq_disable(adapter);
1674
1675         adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
1676
1677         for (i = 0; i < adapter->num_q_vectors; i++) {
1678                 napi_synchronize(&(adapter->q_vector[i]->napi));
1679                 napi_disable(&(adapter->q_vector[i]->napi));
1680         }
1681
1682
1683         del_timer_sync(&adapter->watchdog_timer);
1684         del_timer_sync(&adapter->phy_info_timer);
1685
1686         netif_carrier_off(netdev);
1687
1688         /* record the stats before reset*/
1689         spin_lock(&adapter->stats64_lock);
1690         igb_update_stats(adapter, &adapter->stats64);
1691         spin_unlock(&adapter->stats64_lock);
1692
1693         adapter->link_speed = 0;
1694         adapter->link_duplex = 0;
1695
1696         if (!pci_channel_offline(adapter->pdev))
1697                 igb_reset(adapter);
1698         igb_clean_all_tx_rings(adapter);
1699         igb_clean_all_rx_rings(adapter);
1700 #ifdef CONFIG_IGB_DCA
1701
1702         /* since we reset the hardware DCA settings were cleared */
1703         igb_setup_dca(adapter);
1704 #endif
1705 }
1706
1707 void igb_reinit_locked(struct igb_adapter *adapter)
1708 {
1709         WARN_ON(in_interrupt());
1710         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1711                 msleep(1);
1712         igb_down(adapter);
1713         igb_up(adapter);
1714         clear_bit(__IGB_RESETTING, &adapter->state);
1715 }
1716
1717 void igb_reset(struct igb_adapter *adapter)
1718 {
1719         struct pci_dev *pdev = adapter->pdev;
1720         struct e1000_hw *hw = &adapter->hw;
1721         struct e1000_mac_info *mac = &hw->mac;
1722         struct e1000_fc_info *fc = &hw->fc;
1723         u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
1724
1725         /* Repartition Pba for greater than 9k mtu
1726          * To take effect CTRL.RST is required.
1727          */
1728         switch (mac->type) {
1729         case e1000_i350:
1730         case e1000_i354:
1731         case e1000_82580:
1732                 pba = rd32(E1000_RXPBS);
1733                 pba = igb_rxpbs_adjust_82580(pba);
1734                 break;
1735         case e1000_82576:
1736                 pba = rd32(E1000_RXPBS);
1737                 pba &= E1000_RXPBS_SIZE_MASK_82576;
1738                 break;
1739         case e1000_82575:
1740         case e1000_i210:
1741         case e1000_i211:
1742         default:
1743                 pba = E1000_PBA_34K;
1744                 break;
1745         }
1746
1747         if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1748             (mac->type < e1000_82576)) {
1749                 /* adjust PBA for jumbo frames */
1750                 wr32(E1000_PBA, pba);
1751
1752                 /* To maintain wire speed transmits, the Tx FIFO should be
1753                  * large enough to accommodate two full transmit packets,
1754                  * rounded up to the next 1KB and expressed in KB.  Likewise,
1755                  * the Rx FIFO should be large enough to accommodate at least
1756                  * one full receive packet and is similarly rounded up and
1757                  * expressed in KB.
1758                  */
1759                 pba = rd32(E1000_PBA);
1760                 /* upper 16 bits has Tx packet buffer allocation size in KB */
1761                 tx_space = pba >> 16;
1762                 /* lower 16 bits has Rx packet buffer allocation size in KB */
1763                 pba &= 0xffff;
1764                 /* the Tx fifo also stores 16 bytes of information about the Tx
1765                  * but don't include ethernet FCS because hardware appends it
1766                  */
1767                 min_tx_space = (adapter->max_frame_size +
1768                                 sizeof(union e1000_adv_tx_desc) -
1769                                 ETH_FCS_LEN) * 2;
1770                 min_tx_space = ALIGN(min_tx_space, 1024);
1771                 min_tx_space >>= 10;
1772                 /* software strips receive CRC, so leave room for it */
1773                 min_rx_space = adapter->max_frame_size;
1774                 min_rx_space = ALIGN(min_rx_space, 1024);
1775                 min_rx_space >>= 10;
1776
1777                 /* If current Tx allocation is less than the min Tx FIFO size,
1778                  * and the min Tx FIFO size is less than the current Rx FIFO
1779                  * allocation, take space away from current Rx allocation
1780                  */
1781                 if (tx_space < min_tx_space &&
1782                     ((min_tx_space - tx_space) < pba)) {
1783                         pba = pba - (min_tx_space - tx_space);
1784
1785                         /* if short on Rx space, Rx wins and must trump Tx
1786                          * adjustment
1787                          */
1788                         if (pba < min_rx_space)
1789                                 pba = min_rx_space;
1790                 }
1791                 wr32(E1000_PBA, pba);
1792         }
1793
1794         /* flow control settings */
1795         /* The high water mark must be low enough to fit one full frame
1796          * (or the size used for early receive) above it in the Rx FIFO.
1797          * Set it to the lower of:
1798          * - 90% of the Rx FIFO size, or
1799          * - the full Rx FIFO size minus one full frame
1800          */
1801         hwm = min(((pba << 10) * 9 / 10),
1802                         ((pba << 10) - 2 * adapter->max_frame_size));
1803
1804         fc->high_water = hwm & 0xFFFFFFF0;      /* 16-byte granularity */
1805         fc->low_water = fc->high_water - 16;
1806         fc->pause_time = 0xFFFF;
1807         fc->send_xon = 1;
1808         fc->current_mode = fc->requested_mode;
1809
1810         /* disable receive for all VFs and wait one second */
1811         if (adapter->vfs_allocated_count) {
1812                 int i;
1813                 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1814                         adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
1815
1816                 /* ping all the active vfs to let them know we are going down */
1817                 igb_ping_all_vfs(adapter);
1818
1819                 /* disable transmits and receives */
1820                 wr32(E1000_VFRE, 0);
1821                 wr32(E1000_VFTE, 0);
1822         }
1823
1824         /* Allow time for pending master requests to run */
1825         hw->mac.ops.reset_hw(hw);
1826         wr32(E1000_WUC, 0);
1827
1828         if (hw->mac.ops.init_hw(hw))
1829                 dev_err(&pdev->dev, "Hardware Error\n");
1830
1831         /* Flow control settings reset on hardware reset, so guarantee flow
1832          * control is off when forcing speed.
1833          */
1834         if (!hw->mac.autoneg)
1835                 igb_force_mac_fc(hw);
1836
1837         igb_init_dmac(adapter, pba);
1838 #ifdef CONFIG_IGB_HWMON
1839         /* Re-initialize the thermal sensor on i350 devices. */
1840         if (!test_bit(__IGB_DOWN, &adapter->state)) {
1841                 if (mac->type == e1000_i350 && hw->bus.func == 0) {
1842                         /* If present, re-initialize the external thermal sensor
1843                          * interface.
1844                          */
1845                         if (adapter->ets)
1846                                 mac->ops.init_thermal_sensor_thresh(hw);
1847                 }
1848         }
1849 #endif
1850         if (!netif_running(adapter->netdev))
1851                 igb_power_down_link(adapter);
1852
1853         igb_update_mng_vlan(adapter);
1854
1855         /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1856         wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1857
1858         /* Re-enable PTP, where applicable. */
1859         igb_ptp_reset(adapter);
1860
1861         igb_get_phy_info(hw);
1862 }
1863
1864 static netdev_features_t igb_fix_features(struct net_device *netdev,
1865         netdev_features_t features)
1866 {
1867         /* Since there is no support for separate Rx/Tx vlan accel
1868          * enable/disable make sure Tx flag is always in same state as Rx.
1869          */
1870         if (features & NETIF_F_HW_VLAN_CTAG_RX)
1871                 features |= NETIF_F_HW_VLAN_CTAG_TX;
1872         else
1873                 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
1874
1875         return features;
1876 }
1877
1878 static int igb_set_features(struct net_device *netdev,
1879         netdev_features_t features)
1880 {
1881         netdev_features_t changed = netdev->features ^ features;
1882         struct igb_adapter *adapter = netdev_priv(netdev);
1883
1884         if (changed & NETIF_F_HW_VLAN_CTAG_RX)
1885                 igb_vlan_mode(netdev, features);
1886
1887         if (!(changed & NETIF_F_RXALL))
1888                 return 0;
1889
1890         netdev->features = features;
1891
1892         if (netif_running(netdev))
1893                 igb_reinit_locked(adapter);
1894         else
1895                 igb_reset(adapter);
1896
1897         return 0;
1898 }
1899
1900 static const struct net_device_ops igb_netdev_ops = {
1901         .ndo_open               = igb_open,
1902         .ndo_stop               = igb_close,
1903         .ndo_start_xmit         = igb_xmit_frame,
1904         .ndo_get_stats64        = igb_get_stats64,
1905         .ndo_set_rx_mode        = igb_set_rx_mode,
1906         .ndo_set_mac_address    = igb_set_mac,
1907         .ndo_change_mtu         = igb_change_mtu,
1908         .ndo_do_ioctl           = igb_ioctl,
1909         .ndo_tx_timeout         = igb_tx_timeout,
1910         .ndo_validate_addr      = eth_validate_addr,
1911         .ndo_vlan_rx_add_vid    = igb_vlan_rx_add_vid,
1912         .ndo_vlan_rx_kill_vid   = igb_vlan_rx_kill_vid,
1913         .ndo_set_vf_mac         = igb_ndo_set_vf_mac,
1914         .ndo_set_vf_vlan        = igb_ndo_set_vf_vlan,
1915         .ndo_set_vf_tx_rate     = igb_ndo_set_vf_bw,
1916         .ndo_set_vf_spoofchk    = igb_ndo_set_vf_spoofchk,
1917         .ndo_get_vf_config      = igb_ndo_get_vf_config,
1918 #ifdef CONFIG_NET_POLL_CONTROLLER
1919         .ndo_poll_controller    = igb_netpoll,
1920 #endif
1921         .ndo_fix_features       = igb_fix_features,
1922         .ndo_set_features       = igb_set_features,
1923 };
1924
1925 /**
1926  * igb_set_fw_version - Configure version string for ethtool
1927  * @adapter: adapter struct
1928  **/
1929 void igb_set_fw_version(struct igb_adapter *adapter)
1930 {
1931         struct e1000_hw *hw = &adapter->hw;
1932         struct e1000_fw_version fw;
1933
1934         igb_get_fw_version(hw, &fw);
1935
1936         switch (hw->mac.type) {
1937         case e1000_i210:
1938         case e1000_i211:
1939                 if (!(igb_get_flash_presence_i210(hw))) {
1940                         snprintf(adapter->fw_version,
1941                                  sizeof(adapter->fw_version),
1942                                  "%2d.%2d-%d",
1943                                  fw.invm_major, fw.invm_minor,
1944                                  fw.invm_img_type);
1945                         break;
1946                 }
1947                 /* fall through */
1948         default:
1949                 /* if option is rom valid, display its version too */
1950                 if (fw.or_valid) {
1951                         snprintf(adapter->fw_version,
1952                                  sizeof(adapter->fw_version),
1953                                  "%d.%d, 0x%08x, %d.%d.%d",
1954                                  fw.eep_major, fw.eep_minor, fw.etrack_id,
1955                                  fw.or_major, fw.or_build, fw.or_patch);
1956                 /* no option rom */
1957                 } else if (fw.etrack_id != 0X0000) {
1958                         snprintf(adapter->fw_version,
1959                             sizeof(adapter->fw_version),
1960                             "%d.%d, 0x%08x",
1961                             fw.eep_major, fw.eep_minor, fw.etrack_id);
1962                 } else {
1963                 snprintf(adapter->fw_version,
1964                     sizeof(adapter->fw_version),
1965                     "%d.%d.%d",
1966                     fw.eep_major, fw.eep_minor, fw.eep_build);
1967                 }
1968                 break;
1969         }
1970         return;
1971 }
1972
1973 /**
1974  *  igb_init_i2c - Init I2C interface
1975  *  @adapter: pointer to adapter structure
1976  **/
1977 static s32 igb_init_i2c(struct igb_adapter *adapter)
1978 {
1979         s32 status = E1000_SUCCESS;
1980
1981         /* I2C interface supported on i350 devices */
1982         if (adapter->hw.mac.type != e1000_i350)
1983                 return E1000_SUCCESS;
1984
1985         /* Initialize the i2c bus which is controlled by the registers.
1986          * This bus will use the i2c_algo_bit structue that implements
1987          * the protocol through toggling of the 4 bits in the register.
1988          */
1989         adapter->i2c_adap.owner = THIS_MODULE;
1990         adapter->i2c_algo = igb_i2c_algo;
1991         adapter->i2c_algo.data = adapter;
1992         adapter->i2c_adap.algo_data = &adapter->i2c_algo;
1993         adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
1994         strlcpy(adapter->i2c_adap.name, "igb BB",
1995                 sizeof(adapter->i2c_adap.name));
1996         status = i2c_bit_add_bus(&adapter->i2c_adap);
1997         return status;
1998 }
1999
2000 /**
2001  *  igb_probe - Device Initialization Routine
2002  *  @pdev: PCI device information struct
2003  *  @ent: entry in igb_pci_tbl
2004  *
2005  *  Returns 0 on success, negative on failure
2006  *
2007  *  igb_probe initializes an adapter identified by a pci_dev structure.
2008  *  The OS initialization, configuring of the adapter private structure,
2009  *  and a hardware reset occur.
2010  **/
2011 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2012 {
2013         struct net_device *netdev;
2014         struct igb_adapter *adapter;
2015         struct e1000_hw *hw;
2016         u16 eeprom_data = 0;
2017         s32 ret_val;
2018         static int global_quad_port_a; /* global quad port a indication */
2019         const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2020         unsigned long mmio_start, mmio_len;
2021         int err, pci_using_dac;
2022         u8 part_str[E1000_PBANUM_LENGTH];
2023
2024         /* Catch broken hardware that put the wrong VF device ID in
2025          * the PCIe SR-IOV capability.
2026          */
2027         if (pdev->is_virtfn) {
2028                 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
2029                         pci_name(pdev), pdev->vendor, pdev->device);
2030                 return -EINVAL;
2031         }
2032
2033         err = pci_enable_device_mem(pdev);
2034         if (err)
2035                 return err;
2036
2037         pci_using_dac = 0;
2038         err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
2039         if (!err) {
2040                 pci_using_dac = 1;
2041         } else {
2042                 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
2043                 if (err) {
2044                         dev_err(&pdev->dev,
2045                                 "No usable DMA configuration, aborting\n");
2046                         goto err_dma;
2047                 }
2048         }
2049
2050         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
2051                                            IORESOURCE_MEM),
2052                                            igb_driver_name);
2053         if (err)
2054                 goto err_pci_reg;
2055
2056         pci_enable_pcie_error_reporting(pdev);
2057
2058         pci_set_master(pdev);
2059         pci_save_state(pdev);
2060
2061         err = -ENOMEM;
2062         netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
2063                                    IGB_MAX_TX_QUEUES);
2064         if (!netdev)
2065                 goto err_alloc_etherdev;
2066
2067         SET_NETDEV_DEV(netdev, &pdev->dev);
2068
2069         pci_set_drvdata(pdev, netdev);
2070         adapter = netdev_priv(netdev);
2071         adapter->netdev = netdev;
2072         adapter->pdev = pdev;
2073         hw = &adapter->hw;
2074         hw->back = adapter;
2075         adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
2076
2077         mmio_start = pci_resource_start(pdev, 0);
2078         mmio_len = pci_resource_len(pdev, 0);
2079
2080         err = -EIO;
2081         hw->hw_addr = ioremap(mmio_start, mmio_len);
2082         if (!hw->hw_addr)
2083                 goto err_ioremap;
2084
2085         netdev->netdev_ops = &igb_netdev_ops;
2086         igb_set_ethtool_ops(netdev);
2087         netdev->watchdog_timeo = 5 * HZ;
2088
2089         strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2090
2091         netdev->mem_start = mmio_start;
2092         netdev->mem_end = mmio_start + mmio_len;
2093
2094         /* PCI config space info */
2095         hw->vendor_id = pdev->vendor;
2096         hw->device_id = pdev->device;
2097         hw->revision_id = pdev->revision;
2098         hw->subsystem_vendor_id = pdev->subsystem_vendor;
2099         hw->subsystem_device_id = pdev->subsystem_device;
2100
2101         /* Copy the default MAC, PHY and NVM function pointers */
2102         memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2103         memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2104         memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2105         /* Initialize skew-specific constants */
2106         err = ei->get_invariants(hw);
2107         if (err)
2108                 goto err_sw_init;
2109
2110         /* setup the private structure */
2111         err = igb_sw_init(adapter);
2112         if (err)
2113                 goto err_sw_init;
2114
2115         igb_get_bus_info_pcie(hw);
2116
2117         hw->phy.autoneg_wait_to_complete = false;
2118
2119         /* Copper options */
2120         if (hw->phy.media_type == e1000_media_type_copper) {
2121                 hw->phy.mdix = AUTO_ALL_MODES;
2122                 hw->phy.disable_polarity_correction = false;
2123                 hw->phy.ms_type = e1000_ms_hw_default;
2124         }
2125
2126         if (igb_check_reset_block(hw))
2127                 dev_info(&pdev->dev,
2128                         "PHY reset is blocked due to SOL/IDER session.\n");
2129
2130         /* features is initialized to 0 in allocation, it might have bits
2131          * set by igb_sw_init so we should use an or instead of an
2132          * assignment.
2133          */
2134         netdev->features |= NETIF_F_SG |
2135                             NETIF_F_IP_CSUM |
2136                             NETIF_F_IPV6_CSUM |
2137                             NETIF_F_TSO |
2138                             NETIF_F_TSO6 |
2139                             NETIF_F_RXHASH |
2140                             NETIF_F_RXCSUM |
2141                             NETIF_F_HW_VLAN_CTAG_RX |
2142                             NETIF_F_HW_VLAN_CTAG_TX;
2143
2144         /* copy netdev features into list of user selectable features */
2145         netdev->hw_features |= netdev->features;
2146         netdev->hw_features |= NETIF_F_RXALL;
2147
2148         /* set this bit last since it cannot be part of hw_features */
2149         netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2150
2151         netdev->vlan_features |= NETIF_F_TSO |
2152                                  NETIF_F_TSO6 |
2153                                  NETIF_F_IP_CSUM |
2154                                  NETIF_F_IPV6_CSUM |
2155                                  NETIF_F_SG;
2156
2157         netdev->priv_flags |= IFF_SUPP_NOFCS;
2158
2159         if (pci_using_dac) {
2160                 netdev->features |= NETIF_F_HIGHDMA;
2161                 netdev->vlan_features |= NETIF_F_HIGHDMA;
2162         }
2163
2164         if (hw->mac.type >= e1000_82576) {
2165                 netdev->hw_features |= NETIF_F_SCTP_CSUM;
2166                 netdev->features |= NETIF_F_SCTP_CSUM;
2167         }
2168
2169         netdev->priv_flags |= IFF_UNICAST_FLT;
2170
2171         adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
2172
2173         /* before reading the NVM, reset the controller to put the device in a
2174          * known good starting state
2175          */
2176         hw->mac.ops.reset_hw(hw);
2177
2178         /* make sure the NVM is good , i211/i210 parts can have special NVM
2179          * that doesn't contain a checksum
2180          */
2181         switch (hw->mac.type) {
2182         case e1000_i210:
2183         case e1000_i211:
2184                 if (igb_get_flash_presence_i210(hw)) {
2185                         if (hw->nvm.ops.validate(hw) < 0) {
2186                                 dev_err(&pdev->dev,
2187                                         "The NVM Checksum Is Not Valid\n");
2188                                 err = -EIO;
2189                                 goto err_eeprom;
2190                         }
2191                 }
2192                 break;
2193         default:
2194                 if (hw->nvm.ops.validate(hw) < 0) {
2195                         dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2196                         err = -EIO;
2197                         goto err_eeprom;
2198                 }
2199                 break;
2200         }
2201
2202         /* copy the MAC address out of the NVM */
2203         if (hw->mac.ops.read_mac_addr(hw))
2204                 dev_err(&pdev->dev, "NVM Read Error\n");
2205
2206         memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
2207
2208         if (!is_valid_ether_addr(netdev->dev_addr)) {
2209                 dev_err(&pdev->dev, "Invalid MAC Address\n");
2210                 err = -EIO;
2211                 goto err_eeprom;
2212         }
2213
2214         /* get firmware version for ethtool -i */
2215         igb_set_fw_version(adapter);
2216
2217         setup_timer(&adapter->watchdog_timer, igb_watchdog,
2218                     (unsigned long) adapter);
2219         setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
2220                     (unsigned long) adapter);
2221
2222         INIT_WORK(&adapter->reset_task, igb_reset_task);
2223         INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2224
2225         /* Initialize link properties that are user-changeable */
2226         adapter->fc_autoneg = true;
2227         hw->mac.autoneg = true;
2228         hw->phy.autoneg_advertised = 0x2f;
2229
2230         hw->fc.requested_mode = e1000_fc_default;
2231         hw->fc.current_mode = e1000_fc_default;
2232
2233         igb_validate_mdi_setting(hw);
2234
2235         /* By default, support wake on port A */
2236         if (hw->bus.func == 0)
2237                 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2238
2239         /* Check the NVM for wake support on non-port A ports */
2240         if (hw->mac.type >= e1000_82580)
2241                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2242                                  NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2243                                  &eeprom_data);
2244         else if (hw->bus.func == 1)
2245                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
2246
2247         if (eeprom_data & IGB_EEPROM_APME)
2248                 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2249
2250         /* now that we have the eeprom settings, apply the special cases where
2251          * the eeprom may be wrong or the board simply won't support wake on
2252          * lan on a particular port
2253          */
2254         switch (pdev->device) {
2255         case E1000_DEV_ID_82575GB_QUAD_COPPER:
2256                 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2257                 break;
2258         case E1000_DEV_ID_82575EB_FIBER_SERDES:
2259         case E1000_DEV_ID_82576_FIBER:
2260         case E1000_DEV_ID_82576_SERDES:
2261                 /* Wake events only supported on port A for dual fiber
2262                  * regardless of eeprom setting
2263                  */
2264                 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
2265                         adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2266                 break;
2267         case E1000_DEV_ID_82576_QUAD_COPPER:
2268         case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
2269                 /* if quad port adapter, disable WoL on all but port A */
2270                 if (global_quad_port_a != 0)
2271                         adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2272                 else
2273                         adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2274                 /* Reset for multiple quad port adapters */
2275                 if (++global_quad_port_a == 4)
2276                         global_quad_port_a = 0;
2277                 break;
2278         default:
2279                 /* If the device can't wake, don't set software support */
2280                 if (!device_can_wakeup(&adapter->pdev->dev))
2281                         adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2282         }
2283
2284         /* initialize the wol settings based on the eeprom settings */
2285         if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2286                 adapter->wol |= E1000_WUFC_MAG;
2287
2288         /* Some vendors want WoL disabled by default, but still supported */
2289         if ((hw->mac.type == e1000_i350) &&
2290             (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2291                 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2292                 adapter->wol = 0;
2293         }
2294
2295         device_set_wakeup_enable(&adapter->pdev->dev,
2296                                  adapter->flags & IGB_FLAG_WOL_SUPPORTED);
2297
2298         /* reset the hardware with the new settings */
2299         igb_reset(adapter);
2300
2301         /* Init the I2C interface */
2302         err = igb_init_i2c(adapter);
2303         if (err) {
2304                 dev_err(&pdev->dev, "failed to init i2c interface\n");
2305                 goto err_eeprom;
2306         }
2307
2308         /* let the f/w know that the h/w is now under the control of the
2309          * driver. */
2310         igb_get_hw_control(adapter);
2311
2312         strcpy(netdev->name, "eth%d");
2313         err = register_netdev(netdev);
2314         if (err)
2315                 goto err_register;
2316
2317         /* carrier off reporting is important to ethtool even BEFORE open */
2318         netif_carrier_off(netdev);
2319
2320 #ifdef CONFIG_IGB_DCA
2321         if (dca_add_requester(&pdev->dev) == 0) {
2322                 adapter->flags |= IGB_FLAG_DCA_ENABLED;
2323                 dev_info(&pdev->dev, "DCA enabled\n");
2324                 igb_setup_dca(adapter);
2325         }
2326
2327 #endif
2328 #ifdef CONFIG_IGB_HWMON
2329         /* Initialize the thermal sensor on i350 devices. */
2330         if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2331                 u16 ets_word;
2332
2333                 /* Read the NVM to determine if this i350 device supports an
2334                  * external thermal sensor.
2335                  */
2336                 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2337                 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2338                         adapter->ets = true;
2339                 else
2340                         adapter->ets = false;
2341                 if (igb_sysfs_init(adapter))
2342                         dev_err(&pdev->dev,
2343                                 "failed to allocate sysfs resources\n");
2344         } else {
2345                 adapter->ets = false;
2346         }
2347 #endif
2348         /* do hw tstamp init after resetting */
2349         igb_ptp_init(adapter);
2350
2351         dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
2352         /* print bus type/speed/width info, not applicable to i354 */
2353         if (hw->mac.type != e1000_i354) {
2354                 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2355                          netdev->name,
2356                          ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2357                           (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2358                            "unknown"),
2359                          ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2360                           "Width x4" :
2361                           (hw->bus.width == e1000_bus_width_pcie_x2) ?
2362                           "Width x2" :
2363                           (hw->bus.width == e1000_bus_width_pcie_x1) ?
2364                           "Width x1" : "unknown"), netdev->dev_addr);
2365         }
2366
2367         if ((hw->mac.type >= e1000_i210 ||
2368              igb_get_flash_presence_i210(hw))) {
2369                 ret_val = igb_read_part_string(hw, part_str,
2370                                                E1000_PBANUM_LENGTH);
2371         } else {
2372                 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
2373         }
2374
2375         if (ret_val)
2376                 strcpy(part_str, "Unknown");
2377         dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
2378         dev_info(&pdev->dev,
2379                 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2380                 adapter->msix_entries ? "MSI-X" :
2381                 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
2382                 adapter->num_rx_queues, adapter->num_tx_queues);
2383         switch (hw->mac.type) {
2384         case e1000_i350:
2385         case e1000_i210:
2386         case e1000_i211:
2387                 igb_set_eee_i350(hw);
2388                 break;
2389         case e1000_i354:
2390                 if (hw->phy.media_type == e1000_media_type_copper) {
2391                         if ((rd32(E1000_CTRL_EXT) &
2392                             E1000_CTRL_EXT_LINK_MODE_SGMII))
2393                                 igb_set_eee_i354(hw);
2394                 }
2395                 break;
2396         default:
2397                 break;
2398         }
2399
2400         pm_runtime_put_noidle(&pdev->dev);
2401         return 0;
2402
2403 err_register:
2404         igb_release_hw_control(adapter);
2405         memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
2406 err_eeprom:
2407         if (!igb_check_reset_block(hw))
2408                 igb_reset_phy(hw);
2409
2410         if (hw->flash_address)
2411                 iounmap(hw->flash_address);
2412 err_sw_init:
2413         igb_clear_interrupt_scheme(adapter);
2414         iounmap(hw->hw_addr);
2415 err_ioremap:
2416         free_netdev(netdev);
2417 err_alloc_etherdev:
2418         pci_release_selected_regions(pdev,
2419                                      pci_select_bars(pdev, IORESOURCE_MEM));
2420 err_pci_reg:
2421 err_dma:
2422         pci_disable_device(pdev);
2423         return err;
2424 }
2425
2426 #ifdef CONFIG_PCI_IOV
2427 static int igb_disable_sriov(struct pci_dev *pdev)
2428 {
2429         struct net_device *netdev = pci_get_drvdata(pdev);
2430         struct igb_adapter *adapter = netdev_priv(netdev);
2431         struct e1000_hw *hw = &adapter->hw;
2432
2433         /* reclaim resources allocated to VFs */
2434         if (adapter->vf_data) {
2435                 /* disable iov and allow time for transactions to clear */
2436                 if (pci_vfs_assigned(pdev)) {
2437                         dev_warn(&pdev->dev,
2438                                  "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2439                         return -EPERM;
2440                 } else {
2441                         pci_disable_sriov(pdev);
2442                         msleep(500);
2443                 }
2444
2445                 kfree(adapter->vf_data);
2446                 adapter->vf_data = NULL;
2447                 adapter->vfs_allocated_count = 0;
2448                 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2449                 wrfl();
2450                 msleep(100);
2451                 dev_info(&pdev->dev, "IOV Disabled\n");
2452
2453                 /* Re-enable DMA Coalescing flag since IOV is turned off */
2454                 adapter->flags |= IGB_FLAG_DMAC;
2455         }
2456
2457         return 0;
2458 }
2459
2460 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2461 {
2462         struct net_device *netdev = pci_get_drvdata(pdev);
2463         struct igb_adapter *adapter = netdev_priv(netdev);
2464         int old_vfs = pci_num_vf(pdev);
2465         int err = 0;
2466         int i;
2467
2468         if (!adapter->msix_entries || num_vfs > 7) {
2469                 err = -EPERM;
2470                 goto out;
2471         }
2472         if (!num_vfs)
2473                 goto out;
2474
2475         if (old_vfs) {
2476                 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
2477                          old_vfs, max_vfs);
2478                 adapter->vfs_allocated_count = old_vfs;
2479         } else
2480                 adapter->vfs_allocated_count = num_vfs;
2481
2482         adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2483                                 sizeof(struct vf_data_storage), GFP_KERNEL);
2484
2485         /* if allocation failed then we do not support SR-IOV */
2486         if (!adapter->vf_data) {
2487                 adapter->vfs_allocated_count = 0;
2488                 dev_err(&pdev->dev,
2489                         "Unable to allocate memory for VF Data Storage\n");
2490                 err = -ENOMEM;
2491                 goto out;
2492         }
2493
2494         /* only call pci_enable_sriov() if no VFs are allocated already */
2495         if (!old_vfs) {
2496                 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2497                 if (err)
2498                         goto err_out;
2499         }
2500         dev_info(&pdev->dev, "%d VFs allocated\n",
2501                  adapter->vfs_allocated_count);
2502         for (i = 0; i < adapter->vfs_allocated_count; i++)
2503                 igb_vf_configure(adapter, i);
2504
2505         /* DMA Coalescing is not supported in IOV mode. */
2506         adapter->flags &= ~IGB_FLAG_DMAC;
2507         goto out;
2508
2509 err_out:
2510         kfree(adapter->vf_data);
2511         adapter->vf_data = NULL;
2512         adapter->vfs_allocated_count = 0;
2513 out:
2514         return err;
2515 }
2516
2517 #endif
2518 /**
2519  *  igb_remove_i2c - Cleanup  I2C interface
2520  *  @adapter: pointer to adapter structure
2521  **/
2522 static void igb_remove_i2c(struct igb_adapter *adapter)
2523 {
2524         /* free the adapter bus structure */
2525         i2c_del_adapter(&adapter->i2c_adap);
2526 }
2527
2528 /**
2529  *  igb_remove - Device Removal Routine
2530  *  @pdev: PCI device information struct
2531  *
2532  *  igb_remove is called by the PCI subsystem to alert the driver
2533  *  that it should release a PCI device.  The could be caused by a
2534  *  Hot-Plug event, or because the driver is going to be removed from
2535  *  memory.
2536  **/
2537 static void igb_remove(struct pci_dev *pdev)
2538 {
2539         struct net_device *netdev = pci_get_drvdata(pdev);
2540         struct igb_adapter *adapter = netdev_priv(netdev);
2541         struct e1000_hw *hw = &adapter->hw;
2542
2543         pm_runtime_get_noresume(&pdev->dev);
2544 #ifdef CONFIG_IGB_HWMON
2545         igb_sysfs_exit(adapter);
2546 #endif
2547         igb_remove_i2c(adapter);
2548         igb_ptp_stop(adapter);
2549         /* The watchdog timer may be rescheduled, so explicitly
2550          * disable watchdog from being rescheduled.
2551          */
2552         set_bit(__IGB_DOWN, &adapter->state);
2553         del_timer_sync(&adapter->watchdog_timer);
2554         del_timer_sync(&adapter->phy_info_timer);
2555
2556         cancel_work_sync(&adapter->reset_task);
2557         cancel_work_sync(&adapter->watchdog_task);
2558
2559 #ifdef CONFIG_IGB_DCA
2560         if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
2561                 dev_info(&pdev->dev, "DCA disabled\n");
2562                 dca_remove_requester(&pdev->dev);
2563                 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
2564                 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
2565         }
2566 #endif
2567
2568         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
2569          * would have already happened in close and is redundant.
2570          */
2571         igb_release_hw_control(adapter);
2572
2573         unregister_netdev(netdev);
2574
2575         igb_clear_interrupt_scheme(adapter);
2576
2577 #ifdef CONFIG_PCI_IOV
2578         igb_disable_sriov(pdev);
2579 #endif
2580
2581         iounmap(hw->hw_addr);
2582         if (hw->flash_address)
2583                 iounmap(hw->flash_address);
2584         pci_release_selected_regions(pdev,
2585                                      pci_select_bars(pdev, IORESOURCE_MEM));
2586
2587         kfree(adapter->shadow_vfta);
2588         free_netdev(netdev);
2589
2590         pci_disable_pcie_error_reporting(pdev);
2591
2592         pci_disable_device(pdev);
2593 }
2594
2595 /**
2596  *  igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2597  *  @adapter: board private structure to initialize
2598  *
2599  *  This function initializes the vf specific data storage and then attempts to
2600  *  allocate the VFs.  The reason for ordering it this way is because it is much
2601  *  mor expensive time wise to disable SR-IOV than it is to allocate and free
2602  *  the memory for the VFs.
2603  **/
2604 static void igb_probe_vfs(struct igb_adapter *adapter)
2605 {
2606 #ifdef CONFIG_PCI_IOV
2607         struct pci_dev *pdev = adapter->pdev;
2608         struct e1000_hw *hw = &adapter->hw;
2609
2610         /* Virtualization features not supported on i210 family. */
2611         if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2612                 return;
2613
2614         pci_sriov_set_totalvfs(pdev, 7);
2615         igb_pci_enable_sriov(pdev, max_vfs);
2616
2617 #endif /* CONFIG_PCI_IOV */
2618 }
2619
2620 static void igb_init_queue_configuration(struct igb_adapter *adapter)
2621 {
2622         struct e1000_hw *hw = &adapter->hw;
2623         u32 max_rss_queues;
2624
2625         /* Determine the maximum number of RSS queues supported. */
2626         switch (hw->mac.type) {
2627         case e1000_i211:
2628                 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2629                 break;
2630         case e1000_82575:
2631         case e1000_i210:
2632                 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2633                 break;
2634         case e1000_i350:
2635                 /* I350 cannot do RSS and SR-IOV at the same time */
2636                 if (!!adapter->vfs_allocated_count) {
2637                         max_rss_queues = 1;
2638                         break;
2639                 }
2640                 /* fall through */
2641         case e1000_82576:
2642                 if (!!adapter->vfs_allocated_count) {
2643                         max_rss_queues = 2;
2644                         break;
2645                 }
2646                 /* fall through */
2647         case e1000_82580:
2648         case e1000_i354:
2649         default:
2650                 max_rss_queues = IGB_MAX_RX_QUEUES;
2651                 break;
2652         }
2653
2654         adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2655
2656         /* Determine if we need to pair queues. */
2657         switch (hw->mac.type) {
2658         case e1000_82575:
2659         case e1000_i211:
2660                 /* Device supports enough interrupts without queue pairing. */
2661                 break;
2662         case e1000_82576:
2663                 /* If VFs are going to be allocated with RSS queues then we
2664                  * should pair the queues in order to conserve interrupts due
2665                  * to limited supply.
2666                  */
2667                 if ((adapter->rss_queues > 1) &&
2668                     (adapter->vfs_allocated_count > 6))
2669                         adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2670                 /* fall through */
2671         case e1000_82580:
2672         case e1000_i350:
2673         case e1000_i354:
2674         case e1000_i210:
2675         default:
2676                 /* If rss_queues > half of max_rss_queues, pair the queues in
2677                  * order to conserve interrupts due to limited supply.
2678                  */
2679                 if (adapter->rss_queues > (max_rss_queues / 2))
2680                         adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2681                 break;
2682         }
2683 }
2684
2685 /**
2686  *  igb_sw_init - Initialize general software structures (struct igb_adapter)
2687  *  @adapter: board private structure to initialize
2688  *
2689  *  igb_sw_init initializes the Adapter private data structure.
2690  *  Fields are initialized based on PCI device information and
2691  *  OS network device settings (MTU size).
2692  **/
2693 static int igb_sw_init(struct igb_adapter *adapter)
2694 {
2695         struct e1000_hw *hw = &adapter->hw;
2696         struct net_device *netdev = adapter->netdev;
2697         struct pci_dev *pdev = adapter->pdev;
2698
2699         pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2700
2701         /* set default ring sizes */
2702         adapter->tx_ring_count = IGB_DEFAULT_TXD;
2703         adapter->rx_ring_count = IGB_DEFAULT_RXD;
2704
2705         /* set default ITR values */
2706         adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2707         adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2708
2709         /* set default work limits */
2710         adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2711
2712         adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2713                                   VLAN_HLEN;
2714         adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2715
2716         spin_lock_init(&adapter->stats64_lock);
2717 #ifdef CONFIG_PCI_IOV
2718         switch (hw->mac.type) {
2719         case e1000_82576:
2720         case e1000_i350:
2721                 if (max_vfs > 7) {
2722                         dev_warn(&pdev->dev,
2723                                  "Maximum of 7 VFs per PF, using max\n");
2724                         max_vfs = adapter->vfs_allocated_count = 7;
2725                 } else
2726                         adapter->vfs_allocated_count = max_vfs;
2727                 if (adapter->vfs_allocated_count)
2728                         dev_warn(&pdev->dev,
2729                                  "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2730                 break;
2731         default:
2732                 break;
2733         }
2734 #endif /* CONFIG_PCI_IOV */
2735
2736         igb_init_queue_configuration(adapter);
2737
2738         /* Setup and initialize a copy of the hw vlan table array */
2739         adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
2740                                        GFP_ATOMIC);
2741
2742         /* This call may decrease the number of queues */
2743         if (igb_init_interrupt_scheme(adapter, true)) {
2744                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2745                 return -ENOMEM;
2746         }
2747
2748         igb_probe_vfs(adapter);
2749
2750         /* Explicitly disable IRQ since the NIC can be in any state. */
2751         igb_irq_disable(adapter);
2752
2753         if (hw->mac.type >= e1000_i350)
2754                 adapter->flags &= ~IGB_FLAG_DMAC;
2755
2756         set_bit(__IGB_DOWN, &adapter->state);
2757         return 0;
2758 }
2759
2760 /**
2761  *  igb_open - Called when a network interface is made active
2762  *  @netdev: network interface device structure
2763  *
2764  *  Returns 0 on success, negative value on failure
2765  *
2766  *  The open entry point is called when a network interface is made
2767  *  active by the system (IFF_UP).  At this point all resources needed
2768  *  for transmit and receive operations are allocated, the interrupt
2769  *  handler is registered with the OS, the watchdog timer is started,
2770  *  and the stack is notified that the interface is ready.
2771  **/
2772 static int __igb_open(struct net_device *netdev, bool resuming)
2773 {
2774         struct igb_adapter *adapter = netdev_priv(netdev);
2775         struct e1000_hw *hw = &adapter->hw;
2776         struct pci_dev *pdev = adapter->pdev;
2777         int err;
2778         int i;
2779
2780         /* disallow open during test */
2781         if (test_bit(__IGB_TESTING, &adapter->state)) {
2782                 WARN_ON(resuming);
2783                 return -EBUSY;
2784         }
2785
2786         if (!resuming)
2787                 pm_runtime_get_sync(&pdev->dev);
2788
2789         netif_carrier_off(netdev);
2790
2791         /* allocate transmit descriptors */
2792         err = igb_setup_all_tx_resources(adapter);
2793         if (err)
2794                 goto err_setup_tx;
2795
2796         /* allocate receive descriptors */
2797         err = igb_setup_all_rx_resources(adapter);
2798         if (err)
2799                 goto err_setup_rx;
2800
2801         igb_power_up_link(adapter);
2802
2803         /* before we allocate an interrupt, we must be ready to handle it.
2804          * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
2805          * as soon as we call pci_request_irq, so we have to setup our
2806          * clean_rx handler before we do so.
2807          */
2808         igb_configure(adapter);
2809
2810         err = igb_request_irq(adapter);
2811         if (err)
2812                 goto err_req_irq;
2813
2814         /* Notify the stack of the actual queue counts. */
2815         err = netif_set_real_num_tx_queues(adapter->netdev,
2816                                            adapter->num_tx_queues);
2817         if (err)
2818                 goto err_set_queues;
2819
2820         err = netif_set_real_num_rx_queues(adapter->netdev,
2821                                            adapter->num_rx_queues);
2822         if (err)
2823                 goto err_set_queues;
2824
2825         /* From here on the code is the same as igb_up() */
2826         clear_bit(__IGB_DOWN, &adapter->state);
2827
2828         for (i = 0; i < adapter->num_q_vectors; i++)
2829                 napi_enable(&(adapter->q_vector[i]->napi));
2830
2831         /* Clear any pending interrupts. */
2832         rd32(E1000_ICR);
2833
2834         igb_irq_enable(adapter);
2835
2836         /* notify VFs that reset has been completed */
2837         if (adapter->vfs_allocated_count) {
2838                 u32 reg_data = rd32(E1000_CTRL_EXT);
2839                 reg_data |= E1000_CTRL_EXT_PFRSTD;
2840                 wr32(E1000_CTRL_EXT, reg_data);
2841         }
2842
2843         netif_tx_start_all_queues(netdev);
2844
2845         if (!resuming)
2846                 pm_runtime_put(&pdev->dev);
2847
2848         /* start the watchdog. */
2849         hw->mac.get_link_status = 1;
2850         schedule_work(&adapter->watchdog_task);
2851
2852         return 0;
2853
2854 err_set_queues:
2855         igb_free_irq(adapter);
2856 err_req_irq:
2857         igb_release_hw_control(adapter);
2858         igb_power_down_link(adapter);
2859         igb_free_all_rx_resources(adapter);
2860 err_setup_rx:
2861         igb_free_all_tx_resources(adapter);
2862 err_setup_tx:
2863         igb_reset(adapter);
2864         if (!resuming)
2865                 pm_runtime_put(&pdev->dev);
2866
2867         return err;
2868 }
2869
2870 static int igb_open(struct net_device *netdev)
2871 {
2872         return __igb_open(netdev, false);
2873 }
2874
2875 /**
2876  *  igb_close - Disables a network interface
2877  *  @netdev: network interface device structure
2878  *
2879  *  Returns 0, this is not allowed to fail
2880  *
2881  *  The close entry point is called when an interface is de-activated
2882  *  by the OS.  The hardware is still under the driver's control, but
2883  *  needs to be disabled.  A global MAC reset is issued to stop the
2884  *  hardware, and all transmit and receive resources are freed.
2885  **/
2886 static int __igb_close(struct net_device *netdev, bool suspending)
2887 {
2888         struct igb_adapter *adapter = netdev_priv(netdev);
2889         struct pci_dev *pdev = adapter->pdev;
2890
2891         WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
2892
2893         if (!suspending)
2894                 pm_runtime_get_sync(&pdev->dev);
2895
2896         igb_down(adapter);
2897         igb_free_irq(adapter);
2898
2899         igb_free_all_tx_resources(adapter);
2900         igb_free_all_rx_resources(adapter);
2901
2902         if (!suspending)
2903                 pm_runtime_put_sync(&pdev->dev);
2904         return 0;
2905 }
2906
2907 static int igb_close(struct net_device *netdev)
2908 {
2909         return __igb_close(netdev, false);
2910 }
2911
2912 /**
2913  *  igb_setup_tx_resources - allocate Tx resources (Descriptors)
2914  *  @tx_ring: tx descriptor ring (for a specific queue) to setup
2915  *
2916  *  Return 0 on success, negative on failure
2917  **/
2918 int igb_setup_tx_resources(struct igb_ring *tx_ring)
2919 {
2920         struct device *dev = tx_ring->dev;
2921         int size;
2922
2923         size = sizeof(struct igb_tx_buffer) * tx_ring->count;
2924
2925         tx_ring->tx_buffer_info = vzalloc(size);
2926         if (!tx_ring->tx_buffer_info)
2927                 goto err;
2928
2929         /* round up to nearest 4K */
2930         tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
2931         tx_ring->size = ALIGN(tx_ring->size, 4096);
2932
2933         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
2934                                            &tx_ring->dma, GFP_KERNEL);
2935         if (!tx_ring->desc)
2936                 goto err;
2937
2938         tx_ring->next_to_use = 0;
2939         tx_ring->next_to_clean = 0;
2940
2941         return 0;
2942
2943 err:
2944         vfree(tx_ring->tx_buffer_info);
2945         tx_ring->tx_buffer_info = NULL;
2946         dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
2947         return -ENOMEM;
2948 }
2949
2950 /**
2951  *  igb_setup_all_tx_resources - wrapper to allocate Tx resources
2952  *                               (Descriptors) for all queues
2953  *  @adapter: board private structure
2954  *
2955  *  Return 0 on success, negative on failure
2956  **/
2957 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2958 {
2959         struct pci_dev *pdev = adapter->pdev;
2960         int i, err = 0;
2961
2962         for (i = 0; i < adapter->num_tx_queues; i++) {
2963                 err = igb_setup_tx_resources(adapter->tx_ring[i]);
2964                 if (err) {
2965                         dev_err(&pdev->dev,
2966                                 "Allocation for Tx Queue %u failed\n", i);
2967                         for (i--; i >= 0; i--)
2968                                 igb_free_tx_resources(adapter->tx_ring[i]);
2969                         break;
2970                 }
2971         }
2972
2973         return err;
2974 }
2975
2976 /**
2977  *  igb_setup_tctl - configure the transmit control registers
2978  *  @adapter: Board private structure
2979  **/
2980 void igb_setup_tctl(struct igb_adapter *adapter)
2981 {
2982         struct e1000_hw *hw = &adapter->hw;
2983         u32 tctl;
2984
2985         /* disable queue 0 which is enabled by default on 82575 and 82576 */
2986         wr32(E1000_TXDCTL(0), 0);
2987
2988         /* Program the Transmit Control Register */
2989         tctl = rd32(E1000_TCTL);
2990         tctl &= ~E1000_TCTL_CT;
2991         tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2992                 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2993
2994         igb_config_collision_dist(hw);
2995
2996         /* Enable transmits */
2997         tctl |= E1000_TCTL_EN;
2998
2999         wr32(E1000_TCTL, tctl);
3000 }
3001
3002 /**
3003  *  igb_configure_tx_ring - Configure transmit ring after Reset
3004  *  @adapter: board private structure
3005  *  @ring: tx ring to configure
3006  *
3007  *  Configure a transmit ring after a reset.
3008  **/
3009 void igb_configure_tx_ring(struct igb_adapter *adapter,
3010                            struct igb_ring *ring)
3011 {
3012         struct e1000_hw *hw = &adapter->hw;
3013         u32 txdctl = 0;
3014         u64 tdba = ring->dma;
3015         int reg_idx = ring->reg_idx;
3016
3017         /* disable the queue */
3018         wr32(E1000_TXDCTL(reg_idx), 0);
3019         wrfl();
3020         mdelay(10);
3021
3022         wr32(E1000_TDLEN(reg_idx),
3023              ring->count * sizeof(union e1000_adv_tx_desc));
3024         wr32(E1000_TDBAL(reg_idx),
3025              tdba & 0x00000000ffffffffULL);
3026         wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3027
3028         ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
3029         wr32(E1000_TDH(reg_idx), 0);
3030         writel(0, ring->tail);
3031
3032         txdctl |= IGB_TX_PTHRESH;
3033         txdctl |= IGB_TX_HTHRESH << 8;
3034         txdctl |= IGB_TX_WTHRESH << 16;
3035
3036         txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3037         wr32(E1000_TXDCTL(reg_idx), txdctl);
3038 }
3039
3040 /**
3041  *  igb_configure_tx - Configure transmit Unit after Reset
3042  *  @adapter: board private structure
3043  *
3044  *  Configure the Tx unit of the MAC after a reset.
3045  **/
3046 static void igb_configure_tx(struct igb_adapter *adapter)
3047 {
3048         int i;
3049
3050         for (i = 0; i < adapter->num_tx_queues; i++)
3051                 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
3052 }
3053
3054 /**
3055  *  igb_setup_rx_resources - allocate Rx resources (Descriptors)
3056  *  @rx_ring: Rx descriptor ring (for a specific queue) to setup
3057  *
3058  *  Returns 0 on success, negative on failure
3059  **/
3060 int igb_setup_rx_resources(struct igb_ring *rx_ring)
3061 {
3062         struct device *dev = rx_ring->dev;
3063         int size;
3064
3065         size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3066
3067         rx_ring->rx_buffer_info = vzalloc(size);
3068         if (!rx_ring->rx_buffer_info)
3069                 goto err;
3070
3071         /* Round up to nearest 4K */
3072         rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
3073         rx_ring->size = ALIGN(rx_ring->size, 4096);
3074
3075         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3076                                            &rx_ring->dma, GFP_KERNEL);
3077         if (!rx_ring->desc)
3078                 goto err;
3079
3080         rx_ring->next_to_alloc = 0;
3081         rx_ring->next_to_clean = 0;
3082         rx_ring->next_to_use = 0;
3083
3084         return 0;
3085
3086 err:
3087         vfree(rx_ring->rx_buffer_info);
3088         rx_ring->rx_buffer_info = NULL;
3089         dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
3090         return -ENOMEM;
3091 }
3092
3093 /**
3094  *  igb_setup_all_rx_resources - wrapper to allocate Rx resources
3095  *                               (Descriptors) for all queues
3096  *  @adapter: board private structure
3097  *
3098  *  Return 0 on success, negative on failure
3099  **/
3100 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3101 {
3102         struct pci_dev *pdev = adapter->pdev;
3103         int i, err = 0;
3104
3105         for (i = 0; i < adapter->num_rx_queues; i++) {
3106                 err = igb_setup_rx_resources(adapter->rx_ring[i]);
3107                 if (err) {
3108                         dev_err(&pdev->dev,
3109                                 "Allocation for Rx Queue %u failed\n", i);
3110                         for (i--; i >= 0; i--)
3111                                 igb_free_rx_resources(adapter->rx_ring[i]);
3112                         break;
3113                 }
3114         }
3115
3116         return err;
3117 }
3118
3119 /**
3120  *  igb_setup_mrqc - configure the multiple receive queue control registers
3121  *  @adapter: Board private structure
3122  **/
3123 static void igb_setup_mrqc(struct igb_adapter *adapter)
3124 {
3125         struct e1000_hw *hw = &adapter->hw;
3126         u32 mrqc, rxcsum;
3127         u32 j, num_rx_queues;
3128         static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741,
3129                                         0xB08FA343, 0xCB2BCAD0, 0xB4307BAE,
3130                                         0xA32DCB77, 0x0CF23080, 0x3BB7426A,
3131                                         0xFA01ACBE };
3132
3133         /* Fill out hash function seeds */
3134         for (j = 0; j < 10; j++)
3135                 wr32(E1000_RSSRK(j), rsskey[j]);
3136
3137         num_rx_queues = adapter->rss_queues;
3138
3139         switch (hw->mac.type) {
3140         case e1000_82576:
3141                 /* 82576 supports 2 RSS queues for SR-IOV */
3142                 if (adapter->vfs_allocated_count)
3143                         num_rx_queues = 2;
3144                 break;
3145         default:
3146                 break;
3147         }
3148
3149         if (adapter->rss_indir_tbl_init != num_rx_queues) {
3150                 for (j = 0; j < IGB_RETA_SIZE; j++)
3151                         adapter->rss_indir_tbl[j] = (j * num_rx_queues) / IGB_RETA_SIZE;
3152                 adapter->rss_indir_tbl_init = num_rx_queues;
3153         }
3154         igb_write_rss_indir_tbl(adapter);
3155
3156         /* Disable raw packet checksumming so that RSS hash is placed in
3157          * descriptor on writeback.  No need to enable TCP/UDP/IP checksum
3158          * offloads as they are enabled by default
3159          */
3160         rxcsum = rd32(E1000_RXCSUM);
3161         rxcsum |= E1000_RXCSUM_PCSD;
3162
3163         if (adapter->hw.mac.type >= e1000_82576)
3164                 /* Enable Receive Checksum Offload for SCTP */
3165                 rxcsum |= E1000_RXCSUM_CRCOFL;
3166
3167         /* Don't need to set TUOFL or IPOFL, they default to 1 */
3168         wr32(E1000_RXCSUM, rxcsum);
3169
3170         /* Generate RSS hash based on packet types, TCP/UDP
3171          * port numbers and/or IPv4/v6 src and dst addresses
3172          */
3173         mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3174                E1000_MRQC_RSS_FIELD_IPV4_TCP |
3175                E1000_MRQC_RSS_FIELD_IPV6 |
3176                E1000_MRQC_RSS_FIELD_IPV6_TCP |
3177                E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
3178
3179         if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3180                 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3181         if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3182                 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3183
3184         /* If VMDq is enabled then we set the appropriate mode for that, else
3185          * we default to RSS so that an RSS hash is calculated per packet even
3186          * if we are only using one queue
3187          */
3188         if (adapter->vfs_allocated_count) {
3189                 if (hw->mac.type > e1000_82575) {
3190                         /* Set the default pool for the PF's first queue */
3191                         u32 vtctl = rd32(E1000_VT_CTL);
3192                         vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3193                                    E1000_VT_CTL_DISABLE_DEF_POOL);
3194                         vtctl |= adapter->vfs_allocated_count <<
3195                                 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3196                         wr32(E1000_VT_CTL, vtctl);
3197                 }
3198                 if (adapter->rss_queues > 1)
3199                         mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
3200                 else
3201                         mrqc |= E1000_MRQC_ENABLE_VMDQ;
3202         } else {
3203                 if (hw->mac.type != e1000_i211)
3204                         mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
3205         }
3206         igb_vmm_control(adapter);
3207
3208         wr32(E1000_MRQC, mrqc);
3209 }
3210
3211 /**
3212  *  igb_setup_rctl - configure the receive control registers
3213  *  @adapter: Board private structure
3214  **/
3215 void igb_setup_rctl(struct igb_adapter *adapter)
3216 {
3217         struct e1000_hw *hw = &adapter->hw;
3218         u32 rctl;
3219
3220         rctl = rd32(E1000_RCTL);
3221
3222         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3223         rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
3224
3225         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
3226                 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3227
3228         /* enable stripping of CRC. It's unlikely this will break BMC
3229          * redirection as it did with e1000. Newer features require
3230          * that the HW strips the CRC.
3231          */
3232         rctl |= E1000_RCTL_SECRC;
3233
3234         /* disable store bad packets and clear size bits. */
3235         rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
3236
3237         /* enable LPE to prevent packets larger than max_frame_size */
3238         rctl |= E1000_RCTL_LPE;
3239
3240         /* disable queue 0 to prevent tail write w/o re-config */
3241         wr32(E1000_RXDCTL(0), 0);
3242
3243         /* Attention!!!  For SR-IOV PF driver operations you must enable
3244          * queue drop for all VF and PF queues to prevent head of line blocking
3245          * if an un-trusted VF does not provide descriptors to hardware.
3246          */
3247         if (adapter->vfs_allocated_count) {
3248                 /* set all queue drop enable bits */
3249                 wr32(E1000_QDE, ALL_QUEUES);
3250         }
3251
3252         /* This is useful for sniffing bad packets. */
3253         if (adapter->netdev->features & NETIF_F_RXALL) {
3254                 /* UPE and MPE will be handled by normal PROMISC logic
3255                  * in e1000e_set_rx_mode
3256                  */
3257                 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3258                          E1000_RCTL_BAM | /* RX All Bcast Pkts */
3259                          E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3260
3261                 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3262                           E1000_RCTL_DPF | /* Allow filtered pause */
3263                           E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3264                 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3265                  * and that breaks VLANs.
3266                  */
3267         }
3268
3269         wr32(E1000_RCTL, rctl);
3270 }
3271
3272 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
3273                                    int vfn)
3274 {
3275         struct e1000_hw *hw = &adapter->hw;
3276         u32 vmolr;
3277
3278         /* if it isn't the PF check to see if VFs are enabled and
3279          * increase the size to support vlan tags
3280          */
3281         if (vfn < adapter->vfs_allocated_count &&
3282             adapter->vf_data[vfn].vlans_enabled)
3283                 size += VLAN_TAG_SIZE;
3284
3285         vmolr = rd32(E1000_VMOLR(vfn));
3286         vmolr &= ~E1000_VMOLR_RLPML_MASK;
3287         vmolr |= size | E1000_VMOLR_LPE;
3288         wr32(E1000_VMOLR(vfn), vmolr);
3289
3290         return 0;
3291 }
3292
3293 /**
3294  *  igb_rlpml_set - set maximum receive packet size
3295  *  @adapter: board private structure
3296  *
3297  *  Configure maximum receivable packet size.
3298  **/
3299 static void igb_rlpml_set(struct igb_adapter *adapter)
3300 {
3301         u32 max_frame_size = adapter->max_frame_size;
3302         struct e1000_hw *hw = &adapter->hw;
3303         u16 pf_id = adapter->vfs_allocated_count;
3304
3305         if (pf_id) {
3306                 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
3307                 /* If we're in VMDQ or SR-IOV mode, then set global RLPML
3308                  * to our max jumbo frame size, in case we need to enable
3309                  * jumbo frames on one of the rings later.
3310                  * This will not pass over-length frames into the default
3311                  * queue because it's gated by the VMOLR.RLPML.
3312                  */
3313                 max_frame_size = MAX_JUMBO_FRAME_SIZE;
3314         }
3315
3316         wr32(E1000_RLPML, max_frame_size);
3317 }
3318
3319 static inline void igb_set_vmolr(struct igb_adapter *adapter,
3320                                  int vfn, bool aupe)
3321 {
3322         struct e1000_hw *hw = &adapter->hw;
3323         u32 vmolr;
3324
3325         /* This register exists only on 82576 and newer so if we are older then
3326          * we should exit and do nothing
3327          */
3328         if (hw->mac.type < e1000_82576)
3329                 return;
3330
3331         vmolr = rd32(E1000_VMOLR(vfn));
3332         vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
3333         if (aupe)
3334                 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
3335         else
3336                 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
3337
3338         /* clear all bits that might not be set */
3339         vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3340
3341         if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
3342                 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
3343         /* for VMDq only allow the VFs and pool 0 to accept broadcast and
3344          * multicast packets
3345          */
3346         if (vfn <= adapter->vfs_allocated_count)
3347                 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
3348
3349         wr32(E1000_VMOLR(vfn), vmolr);
3350 }
3351
3352 /**
3353  *  igb_configure_rx_ring - Configure a receive ring after Reset
3354  *  @adapter: board private structure
3355  *  @ring: receive ring to be configured
3356  *
3357  *  Configure the Rx unit of the MAC after a reset.
3358  **/
3359 void igb_configure_rx_ring(struct igb_adapter *adapter,
3360                            struct igb_ring *ring)
3361 {
3362         struct e1000_hw *hw = &adapter->hw;
3363         u64 rdba = ring->dma;
3364         int reg_idx = ring->reg_idx;
3365         u32 srrctl = 0, rxdctl = 0;
3366
3367         /* disable the queue */
3368         wr32(E1000_RXDCTL(reg_idx), 0);
3369
3370         /* Set DMA base address registers */
3371         wr32(E1000_RDBAL(reg_idx),
3372              rdba & 0x00000000ffffffffULL);
3373         wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3374         wr32(E1000_RDLEN(reg_idx),
3375              ring->count * sizeof(union e1000_adv_rx_desc));
3376
3377         /* initialize head and tail */
3378         ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
3379         wr32(E1000_RDH(reg_idx), 0);
3380         writel(0, ring->tail);
3381
3382         /* set descriptor configuration */
3383         srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
3384         srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3385         srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3386         if (hw->mac.type >= e1000_82580)
3387                 srrctl |= E1000_SRRCTL_TIMESTAMP;
3388         /* Only set Drop Enable if we are supporting multiple queues */
3389         if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3390                 srrctl |= E1000_SRRCTL_DROP_EN;
3391
3392         wr32(E1000_SRRCTL(reg_idx), srrctl);
3393
3394         /* set filtering for VMDQ pools */
3395         igb_set_vmolr(adapter, reg_idx & 0x7, true);
3396
3397         rxdctl |= IGB_RX_PTHRESH;
3398         rxdctl |= IGB_RX_HTHRESH << 8;
3399         rxdctl |= IGB_RX_WTHRESH << 16;
3400
3401         /* enable receive descriptor fetching */
3402         rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3403         wr32(E1000_RXDCTL(reg_idx), rxdctl);
3404 }
3405
3406 /**
3407  *  igb_configure_rx - Configure receive Unit after Reset
3408  *  @adapter: board private structure
3409  *
3410  *  Configure the Rx unit of the MAC after a reset.
3411  **/
3412 static void igb_configure_rx(struct igb_adapter *adapter)
3413 {
3414         int i;
3415
3416         /* set UTA to appropriate mode */
3417         igb_set_uta(adapter);
3418
3419         /* set the correct pool for the PF default MAC address in entry 0 */
3420         igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
3421                          adapter->vfs_allocated_count);
3422
3423         /* Setup the HW Rx Head and Tail Descriptor Pointers and
3424          * the Base and Length of the Rx Descriptor Ring
3425          */
3426         for (i = 0; i < adapter->num_rx_queues; i++)
3427                 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
3428 }
3429
3430 /**
3431  *  igb_free_tx_resources - Free Tx Resources per Queue
3432  *  @tx_ring: Tx descriptor ring for a specific queue
3433  *
3434  *  Free all transmit software resources
3435  **/
3436 void igb_free_tx_resources(struct igb_ring *tx_ring)
3437 {
3438         igb_clean_tx_ring(tx_ring);
3439
3440         vfree(tx_ring->tx_buffer_info);
3441         tx_ring->tx_buffer_info = NULL;
3442
3443         /* if not set, then don't free */
3444         if (!tx_ring->desc)
3445                 return;
3446
3447         dma_free_coherent(tx_ring->dev, tx_ring->size,
3448                           tx_ring->desc, tx_ring->dma);
3449
3450         tx_ring->desc = NULL;
3451 }
3452
3453 /**
3454  *  igb_free_all_tx_resources - Free Tx Resources for All Queues
3455  *  @adapter: board private structure
3456  *
3457  *  Free all transmit software resources
3458  **/
3459 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3460 {
3461         int i;
3462
3463         for (i = 0; i < adapter->num_tx_queues; i++)
3464                 igb_free_tx_resources(adapter->tx_ring[i]);
3465 }
3466
3467 void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3468                                     struct igb_tx_buffer *tx_buffer)
3469 {
3470         if (tx_buffer->skb) {
3471                 dev_kfree_skb_any(tx_buffer->skb);
3472                 if (dma_unmap_len(tx_buffer, len))
3473                         dma_unmap_single(ring->dev,
3474                                          dma_unmap_addr(tx_buffer, dma),
3475                                          dma_unmap_len(tx_buffer, len),
3476                                          DMA_TO_DEVICE);
3477         } else if (dma_unmap_len(tx_buffer, len)) {
3478                 dma_unmap_page(ring->dev,
3479                                dma_unmap_addr(tx_buffer, dma),
3480                                dma_unmap_len(tx_buffer, len),
3481                                DMA_TO_DEVICE);
3482         }
3483         tx_buffer->next_to_watch = NULL;
3484         tx_buffer->skb = NULL;
3485         dma_unmap_len_set(tx_buffer, len, 0);
3486         /* buffer_info must be completely set up in the transmit path */
3487 }
3488
3489 /**
3490  *  igb_clean_tx_ring - Free Tx Buffers
3491  *  @tx_ring: ring to be cleaned
3492  **/
3493 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
3494 {
3495         struct igb_tx_buffer *buffer_info;
3496         unsigned long size;
3497         u16 i;
3498
3499         if (!tx_ring->tx_buffer_info)
3500                 return;
3501         /* Free all the Tx ring sk_buffs */
3502
3503         for (i = 0; i < tx_ring->count; i++) {
3504                 buffer_info = &tx_ring->tx_buffer_info[i];
3505                 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
3506         }
3507
3508         netdev_tx_reset_queue(txring_txq(tx_ring));
3509
3510         size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3511         memset(tx_ring->tx_buffer_info, 0, size);
3512
3513         /* Zero out the descriptor ring */
3514         memset(tx_ring->desc, 0, tx_ring->size);
3515
3516         tx_ring->next_to_use = 0;
3517         tx_ring->next_to_clean = 0;
3518 }
3519
3520 /**
3521  *  igb_clean_all_tx_rings - Free Tx Buffers for all queues
3522  *  @adapter: board private structure
3523  **/
3524 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3525 {
3526         int i;
3527
3528         for (i = 0; i < adapter->num_tx_queues; i++)
3529                 igb_clean_tx_ring(adapter->tx_ring[i]);
3530 }
3531
3532 /**
3533  *  igb_free_rx_resources - Free Rx Resources
3534  *  @rx_ring: ring to clean the resources from
3535  *
3536  *  Free all receive software resources
3537  **/
3538 void igb_free_rx_resources(struct igb_ring *rx_ring)
3539 {
3540         igb_clean_rx_ring(rx_ring);
3541
3542         vfree(rx_ring->rx_buffer_info);
3543         rx_ring->rx_buffer_info = NULL;
3544
3545         /* if not set, then don't free */
3546         if (!rx_ring->desc)
3547                 return;
3548
3549         dma_free_coherent(rx_ring->dev, rx_ring->size,
3550                           rx_ring->desc, rx_ring->dma);
3551
3552         rx_ring->desc = NULL;
3553 }
3554
3555 /**
3556  *  igb_free_all_rx_resources - Free Rx Resources for All Queues
3557  *  @adapter: board private structure
3558  *
3559  *  Free all receive software resources
3560  **/
3561 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3562 {
3563         int i;
3564
3565         for (i = 0; i < adapter->num_rx_queues; i++)
3566                 igb_free_rx_resources(adapter->rx_ring[i]);
3567 }
3568
3569 /**
3570  *  igb_clean_rx_ring - Free Rx Buffers per Queue
3571  *  @rx_ring: ring to free buffers from
3572  **/
3573 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
3574 {
3575         unsigned long size;
3576         u16 i;
3577
3578         if (rx_ring->skb)
3579                 dev_kfree_skb(rx_ring->skb);
3580         rx_ring->skb = NULL;
3581
3582         if (!rx_ring->rx_buffer_info)
3583                 return;
3584
3585         /* Free all the Rx ring sk_buffs */
3586         for (i = 0; i < rx_ring->count; i++) {
3587                 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
3588
3589                 if (!buffer_info->page)
3590                         continue;
3591
3592                 dma_unmap_page(rx_ring->dev,
3593                                buffer_info->dma,
3594                                PAGE_SIZE,
3595                                DMA_FROM_DEVICE);
3596                 __free_page(buffer_info->page);
3597
3598                 buffer_info->page = NULL;
3599         }
3600
3601         size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3602         memset(rx_ring->rx_buffer_info, 0, size);
3603
3604         /* Zero out the descriptor ring */
3605         memset(rx_ring->desc, 0, rx_ring->size);
3606
3607         rx_ring->next_to_alloc = 0;
3608         rx_ring->next_to_clean = 0;
3609         rx_ring->next_to_use = 0;
3610 }
3611
3612 /**
3613  *  igb_clean_all_rx_rings - Free Rx Buffers for all queues
3614  *  @adapter: board private structure
3615  **/
3616 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3617 {
3618         int i;
3619
3620         for (i = 0; i < adapter->num_rx_queues; i++)
3621                 igb_clean_rx_ring(adapter->rx_ring[i]);
3622 }
3623
3624 /**
3625  *  igb_set_mac - Change the Ethernet Address of the NIC
3626  *  @netdev: network interface device structure
3627  *  @p: pointer to an address structure
3628  *
3629  *  Returns 0 on success, negative on failure
3630  **/
3631 static int igb_set_mac(struct net_device *netdev, void *p)
3632 {
3633         struct igb_adapter *adapter = netdev_priv(netdev);
3634         struct e1000_hw *hw = &adapter->hw;
3635         struct sockaddr *addr = p;
3636
3637         if (!is_valid_ether_addr(addr->sa_data))
3638                 return -EADDRNOTAVAIL;
3639
3640         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3641         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
3642
3643         /* set the correct pool for the new PF MAC address in entry 0 */
3644         igb_rar_set_qsel(adapter, hw->mac.addr, 0,
3645                          adapter->vfs_allocated_count);
3646
3647         return 0;
3648 }
3649
3650 /**
3651  *  igb_write_mc_addr_list - write multicast addresses to MTA
3652  *  @netdev: network interface device structure
3653  *
3654  *  Writes multicast address list to the MTA hash table.
3655  *  Returns: -ENOMEM on failure
3656  *           0 on no addresses written
3657  *           X on writing X addresses to MTA
3658  **/
3659 static int igb_write_mc_addr_list(struct net_device *netdev)
3660 {
3661         struct igb_adapter *adapter = netdev_priv(netdev);
3662         struct e1000_hw *hw = &adapter->hw;
3663         struct netdev_hw_addr *ha;
3664         u8  *mta_list;
3665         int i;
3666
3667         if (netdev_mc_empty(netdev)) {
3668                 /* nothing to program, so clear mc list */
3669                 igb_update_mc_addr_list(hw, NULL, 0);
3670                 igb_restore_vf_multicasts(adapter);
3671                 return 0;
3672         }
3673
3674         mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
3675         if (!mta_list)
3676                 return -ENOMEM;
3677
3678         /* The shared function expects a packed array of only addresses. */
3679         i = 0;
3680         netdev_for_each_mc_addr(ha, netdev)
3681                 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3682
3683         igb_update_mc_addr_list(hw, mta_list, i);
3684         kfree(mta_list);
3685
3686         return netdev_mc_count(netdev);
3687 }
3688
3689 /**
3690  *  igb_write_uc_addr_list - write unicast addresses to RAR table
3691  *  @netdev: network interface device structure
3692  *
3693  *  Writes unicast address list to the RAR table.
3694  *  Returns: -ENOMEM on failure/insufficient address space
3695  *           0 on no addresses written
3696  *           X on writing X addresses to the RAR table
3697  **/
3698 static int igb_write_uc_addr_list(struct net_device *netdev)
3699 {
3700         struct igb_adapter *adapter = netdev_priv(netdev);
3701         struct e1000_hw *hw = &adapter->hw;
3702         unsigned int vfn = adapter->vfs_allocated_count;
3703         unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3704         int count = 0;
3705
3706         /* return ENOMEM indicating insufficient memory for addresses */
3707         if (netdev_uc_count(netdev) > rar_entries)
3708                 return -ENOMEM;
3709
3710         if (!netdev_uc_empty(netdev) && rar_entries) {
3711                 struct netdev_hw_addr *ha;
3712
3713                 netdev_for_each_uc_addr(ha, netdev) {
3714                         if (!rar_entries)
3715                                 break;
3716                         igb_rar_set_qsel(adapter, ha->addr,
3717                                          rar_entries--,
3718                                          vfn);
3719                         count++;
3720                 }
3721         }
3722         /* write the addresses in reverse order to avoid write combining */
3723         for (; rar_entries > 0 ; rar_entries--) {
3724                 wr32(E1000_RAH(rar_entries), 0);
3725                 wr32(E1000_RAL(rar_entries), 0);
3726         }
3727         wrfl();
3728
3729         return count;
3730 }
3731
3732 /**
3733  *  igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3734  *  @netdev: network interface device structure
3735  *
3736  *  The set_rx_mode entry point is called whenever the unicast or multicast
3737  *  address lists or the network interface flags are updated.  This routine is
3738  *  responsible for configuring the hardware for proper unicast, multicast,
3739  *  promiscuous mode, and all-multi behavior.
3740  **/
3741 static void igb_set_rx_mode(struct net_device *netdev)
3742 {
3743         struct igb_adapter *adapter = netdev_priv(netdev);
3744         struct e1000_hw *hw = &adapter->hw;
3745         unsigned int vfn = adapter->vfs_allocated_count;
3746         u32 rctl, vmolr = 0;
3747         int count;
3748
3749         /* Check for Promiscuous and All Multicast modes */
3750         rctl = rd32(E1000_RCTL);
3751
3752         /* clear the effected bits */
3753         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
3754
3755         if (netdev->flags & IFF_PROMISC) {
3756                 /* retain VLAN HW filtering if in VT mode */
3757                 if (adapter->vfs_allocated_count)
3758                         rctl |= E1000_RCTL_VFE;
3759                 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3760                 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
3761         } else {
3762                 if (netdev->flags & IFF_ALLMULTI) {
3763                         rctl |= E1000_RCTL_MPE;
3764                         vmolr |= E1000_VMOLR_MPME;
3765                 } else {
3766                         /* Write addresses to the MTA, if the attempt fails
3767                          * then we should just turn on promiscuous mode so
3768                          * that we can at least receive multicast traffic
3769                          */
3770                         count = igb_write_mc_addr_list(netdev);
3771                         if (count < 0) {
3772                                 rctl |= E1000_RCTL_MPE;
3773                                 vmolr |= E1000_VMOLR_MPME;
3774                         } else if (count) {
3775                                 vmolr |= E1000_VMOLR_ROMPE;
3776                         }
3777                 }
3778                 /* Write addresses to available RAR registers, if there is not
3779                  * sufficient space to store all the addresses then enable
3780                  * unicast promiscuous mode
3781                  */
3782                 count = igb_write_uc_addr_list(netdev);
3783                 if (count < 0) {
3784                         rctl |= E1000_RCTL_UPE;
3785                         vmolr |= E1000_VMOLR_ROPE;
3786                 }
3787                 rctl |= E1000_RCTL_VFE;
3788         }
3789         wr32(E1000_RCTL, rctl);
3790
3791         /* In order to support SR-IOV and eventually VMDq it is necessary to set
3792          * the VMOLR to enable the appropriate modes.  Without this workaround
3793          * we will have issues with VLAN tag stripping not being done for frames
3794          * that are only arriving because we are the default pool
3795          */
3796         if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
3797                 return;
3798
3799         vmolr |= rd32(E1000_VMOLR(vfn)) &
3800                  ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
3801         wr32(E1000_VMOLR(vfn), vmolr);
3802         igb_restore_vf_multicasts(adapter);
3803 }
3804
3805 static void igb_check_wvbr(struct igb_adapter *adapter)
3806 {
3807         struct e1000_hw *hw = &adapter->hw;
3808         u32 wvbr = 0;
3809
3810         switch (hw->mac.type) {
3811         case e1000_82576:
3812         case e1000_i350:
3813                 if (!(wvbr = rd32(E1000_WVBR)))
3814                         return;
3815                 break;
3816         default:
3817                 break;
3818         }
3819
3820         adapter->wvbr |= wvbr;
3821 }
3822
3823 #define IGB_STAGGERED_QUEUE_OFFSET 8
3824
3825 static void igb_spoof_check(struct igb_adapter *adapter)
3826 {
3827         int j;
3828
3829         if (!adapter->wvbr)
3830                 return;
3831
3832         for(j = 0; j < adapter->vfs_allocated_count; j++) {
3833                 if (adapter->wvbr & (1 << j) ||
3834                     adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
3835                         dev_warn(&adapter->pdev->dev,
3836                                 "Spoof event(s) detected on VF %d\n", j);
3837                         adapter->wvbr &=
3838                                 ~((1 << j) |
3839                                   (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
3840                 }
3841         }
3842 }
3843
3844 /* Need to wait a few seconds after link up to get diagnostic information from
3845  * the phy
3846  */
3847 static void igb_update_phy_info(unsigned long data)
3848 {
3849         struct igb_adapter *adapter = (struct igb_adapter *) data;
3850         igb_get_phy_info(&adapter->hw);
3851 }
3852
3853 /**
3854  *  igb_has_link - check shared code for link and determine up/down
3855  *  @adapter: pointer to driver private info
3856  **/
3857 bool igb_has_link(struct igb_adapter *adapter)
3858 {
3859         struct e1000_hw *hw = &adapter->hw;
3860         bool link_active = false;
3861
3862         /* get_link_status is set on LSC (link status) interrupt or
3863          * rx sequence error interrupt.  get_link_status will stay
3864          * false until the e1000_check_for_link establishes link
3865          * for copper adapters ONLY
3866          */
3867         switch (hw->phy.media_type) {
3868         case e1000_media_type_copper:
3869                 if (!hw->mac.get_link_status)
3870                         return true;
3871         case e1000_media_type_internal_serdes:
3872                 hw->mac.ops.check_for_link(hw);
3873                 link_active = !hw->mac.get_link_status;
3874                 break;
3875         default:
3876         case e1000_media_type_unknown:
3877                 break;
3878         }
3879
3880         if (((hw->mac.type == e1000_i210) ||
3881              (hw->mac.type == e1000_i211)) &&
3882              (hw->phy.id == I210_I_PHY_ID)) {
3883                 if (!netif_carrier_ok(adapter->netdev)) {
3884                         adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
3885                 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
3886                         adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
3887                         adapter->link_check_timeout = jiffies;
3888                 }
3889         }
3890
3891         return link_active;
3892 }
3893
3894 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
3895 {
3896         bool ret = false;
3897         u32 ctrl_ext, thstat;
3898
3899         /* check for thermal sensor event on i350 copper only */
3900         if (hw->mac.type == e1000_i350) {
3901                 thstat = rd32(E1000_THSTAT);
3902                 ctrl_ext = rd32(E1000_CTRL_EXT);
3903
3904                 if ((hw->phy.media_type == e1000_media_type_copper) &&
3905                     !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
3906                         ret = !!(thstat & event);
3907         }
3908
3909         return ret;
3910 }
3911
3912 /**
3913  *  igb_watchdog - Timer Call-back
3914  *  @data: pointer to adapter cast into an unsigned long
3915  **/
3916 static void igb_watchdog(unsigned long data)
3917 {
3918         struct igb_adapter *adapter = (struct igb_adapter *)data;
3919         /* Do the rest outside of interrupt context */
3920         schedule_work(&adapter->watchdog_task);
3921 }
3922
3923 static void igb_watchdog_task(struct work_struct *work)
3924 {
3925         struct igb_adapter *adapter = container_of(work,
3926                                                    struct igb_adapter,
3927                                                    watchdog_task);
3928         struct e1000_hw *hw = &adapter->hw;
3929         struct e1000_phy_info *phy = &hw->phy;
3930         struct net_device *netdev = adapter->netdev;
3931         u32 link;
3932         int i;
3933
3934         link = igb_has_link(adapter);
3935
3936         if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
3937                 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
3938                         adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
3939                 else
3940                         link = false;
3941         }
3942
3943         if (link) {
3944                 /* Cancel scheduled suspend requests. */
3945                 pm_runtime_resume(netdev->dev.parent);
3946
3947                 if (!netif_carrier_ok(netdev)) {
3948                         u32 ctrl;
3949                         hw->mac.ops.get_speed_and_duplex(hw,
3950                                                          &adapter->link_speed,
3951                                                          &adapter->link_duplex);
3952
3953                         ctrl = rd32(E1000_CTRL);
3954                         /* Links status message must follow this format */
3955                         printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s "
3956                                "Duplex, Flow Control: %s\n",
3957                                netdev->name,
3958                                adapter->link_speed,
3959                                adapter->link_duplex == FULL_DUPLEX ?
3960                                "Full" : "Half",
3961                                (ctrl & E1000_CTRL_TFCE) &&
3962                                (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
3963                                (ctrl & E1000_CTRL_RFCE) ?  "RX" :
3964                                (ctrl & E1000_CTRL_TFCE) ?  "TX" : "None");
3965
3966                         /* check if SmartSpeed worked */
3967                         igb_check_downshift(hw);
3968                         if (phy->speed_downgraded)
3969                                 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
3970
3971                         /* check for thermal sensor event */
3972                         if (igb_thermal_sensor_event(hw,
3973                             E1000_THSTAT_LINK_THROTTLE)) {
3974                                 netdev_info(netdev, "The network adapter link "
3975                                             "speed was downshifted because it "
3976                                             "overheated\n");
3977                         }
3978
3979                         /* adjust timeout factor according to speed/duplex */
3980                         adapter->tx_timeout_factor = 1;
3981                         switch (adapter->link_speed) {
3982                         case SPEED_10:
3983                                 adapter->tx_timeout_factor = 14;
3984                                 break;
3985                         case SPEED_100:
3986                                 /* maybe add some timeout factor ? */
3987                                 break;
3988                         }
3989
3990                         netif_carrier_on(netdev);
3991
3992                         igb_ping_all_vfs(adapter);
3993                         igb_check_vf_rate_limit(adapter);
3994
3995                         /* link state has changed, schedule phy info update */
3996                         if (!test_bit(__IGB_DOWN, &adapter->state))
3997                                 mod_timer(&adapter->phy_info_timer,
3998                                           round_jiffies(jiffies + 2 * HZ));
3999                 }
4000         } else {
4001                 if (netif_carrier_ok(netdev)) {
4002                         adapter->link_speed = 0;
4003                         adapter->link_duplex = 0;
4004
4005                         /* check for thermal sensor event */
4006                         if (igb_thermal_sensor_event(hw,
4007                             E1000_THSTAT_PWR_DOWN)) {
4008                                 netdev_err(netdev, "The network adapter was "
4009                                            "stopped because it overheated\n");
4010                         }
4011
4012                         /* Links status message must follow this format */
4013                         printk(KERN_INFO "igb: %s NIC Link is Down\n",
4014                                netdev->name);
4015                         netif_carrier_off(netdev);
4016
4017                         igb_ping_all_vfs(adapter);
4018
4019                         /* link state has changed, schedule phy info update */
4020                         if (!test_bit(__IGB_DOWN, &adapter->state))
4021                                 mod_timer(&adapter->phy_info_timer,
4022                                           round_jiffies(jiffies + 2 * HZ));
4023
4024                         pm_schedule_suspend(netdev->dev.parent,
4025                                             MSEC_PER_SEC * 5);
4026                 }
4027         }
4028
4029         spin_lock(&adapter->stats64_lock);
4030         igb_update_stats(adapter, &adapter->stats64);
4031         spin_unlock(&adapter->stats64_lock);
4032
4033         for (i = 0; i < adapter->num_tx_queues; i++) {
4034                 struct igb_ring *tx_ring = adapter->tx_ring[i];
4035                 if (!netif_carrier_ok(netdev)) {
4036                         /* We've lost link, so the controller stops DMA,
4037                          * but we've got queued Tx work that's never going
4038                          * to get done, so reset controller to flush Tx.
4039                          * (Do the reset outside of interrupt context).
4040                          */
4041                         if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4042                                 adapter->tx_timeout_count++;
4043                                 schedule_work(&adapter->reset_task);
4044                                 /* return immediately since reset is imminent */
4045                                 return;
4046                         }
4047                 }
4048
4049                 /* Force detection of hung controller every watchdog period */
4050                 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
4051         }
4052
4053         /* Cause software interrupt to ensure Rx ring is cleaned */
4054         if (adapter->msix_entries) {
4055                 u32 eics = 0;
4056                 for (i = 0; i < adapter->num_q_vectors; i++)
4057                         eics |= adapter->q_vector[i]->eims_value;
4058                 wr32(E1000_EICS, eics);
4059         } else {
4060                 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4061         }
4062
4063         igb_spoof_check(adapter);
4064         igb_ptp_rx_hang(adapter);
4065
4066         /* Reset the timer */
4067         if (!test_bit(__IGB_DOWN, &adapter->state)) {
4068                 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
4069                         mod_timer(&adapter->watchdog_timer,
4070                                   round_jiffies(jiffies +  HZ));
4071                 else
4072                         mod_timer(&adapter->watchdog_timer,
4073                                   round_jiffies(jiffies + 2 * HZ));
4074         }
4075 }
4076
4077 enum latency_range {
4078         lowest_latency = 0,
4079         low_latency = 1,
4080         bulk_latency = 2,
4081         latency_invalid = 255
4082 };
4083
4084 /**
4085  *  igb_update_ring_itr - update the dynamic ITR value based on packet size
4086  *  @q_vector: pointer to q_vector
4087  *
4088  *  Stores a new ITR value based on strictly on packet size.  This
4089  *  algorithm is less sophisticated than that used in igb_update_itr,
4090  *  due to the difficulty of synchronizing statistics across multiple
4091  *  receive rings.  The divisors and thresholds used by this function
4092  *  were determined based on theoretical maximum wire speed and testing
4093  *  data, in order to minimize response time while increasing bulk
4094  *  throughput.
4095  *  This functionality is controlled by the InterruptThrottleRate module
4096  *  parameter (see igb_param.c)
4097  *  NOTE:  This function is called only when operating in a multiqueue
4098  *         receive environment.
4099  **/
4100 static void igb_update_ring_itr(struct igb_q_vector *q_vector)
4101 {
4102         int new_val = q_vector->itr_val;
4103         int avg_wire_size = 0;
4104         struct igb_adapter *adapter = q_vector->adapter;
4105         unsigned int packets;
4106
4107         /* For non-gigabit speeds, just fix the interrupt rate at 4000
4108          * ints/sec - ITR timer value of 120 ticks.
4109          */
4110         if (adapter->link_speed != SPEED_1000) {
4111                 new_val = IGB_4K_ITR;
4112                 goto set_itr_val;
4113         }
4114
4115         packets = q_vector->rx.total_packets;
4116         if (packets)
4117                 avg_wire_size = q_vector->rx.total_bytes / packets;
4118
4119         packets = q_vector->tx.total_packets;
4120         if (packets)
4121                 avg_wire_size = max_t(u32, avg_wire_size,
4122                                       q_vector->tx.total_bytes / packets);
4123
4124         /* if avg_wire_size isn't set no work was done */
4125         if (!avg_wire_size)
4126                 goto clear_counts;
4127
4128         /* Add 24 bytes to size to account for CRC, preamble, and gap */
4129         avg_wire_size += 24;
4130
4131         /* Don't starve jumbo frames */
4132         avg_wire_size = min(avg_wire_size, 3000);
4133
4134         /* Give a little boost to mid-size frames */
4135         if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4136                 new_val = avg_wire_size / 3;
4137         else
4138                 new_val = avg_wire_size / 2;
4139
4140         /* conservative mode (itr 3) eliminates the lowest_latency setting */
4141         if (new_val < IGB_20K_ITR &&
4142             ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4143              (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4144                 new_val = IGB_20K_ITR;
4145
4146 set_itr_val:
4147         if (new_val != q_vector->itr_val) {
4148                 q_vector->itr_val = new_val;
4149                 q_vector->set_itr = 1;
4150         }
4151 clear_counts:
4152         q_vector->rx.total_bytes = 0;
4153         q_vector->rx.total_packets = 0;
4154         q_vector->tx.total_bytes = 0;
4155         q_vector->tx.total_packets = 0;
4156 }
4157
4158 /**
4159  *  igb_update_itr - update the dynamic ITR value based on statistics
4160  *  @q_vector: pointer to q_vector
4161  *  @ring_container: ring info to update the itr for
4162  *
4163  *  Stores a new ITR value based on packets and byte
4164  *  counts during the last interrupt.  The advantage of per interrupt
4165  *  computation is faster updates and more accurate ITR for the current
4166  *  traffic pattern.  Constants in this function were computed
4167  *  based on theoretical maximum wire speed and thresholds were set based
4168  *  on testing data as well as attempting to minimize response time
4169  *  while increasing bulk throughput.
4170  *  this functionality is controlled by the InterruptThrottleRate module
4171  *  parameter (see igb_param.c)
4172  *  NOTE:  These calculations are only valid when operating in a single-
4173  *         queue environment.
4174  **/
4175 static void igb_update_itr(struct igb_q_vector *q_vector,
4176                            struct igb_ring_container *ring_container)
4177 {
4178         unsigned int packets = ring_container->total_packets;
4179         unsigned int bytes = ring_container->total_bytes;
4180         u8 itrval = ring_container->itr;
4181
4182         /* no packets, exit with status unchanged */
4183         if (packets == 0)
4184                 return;
4185
4186         switch (itrval) {
4187         case lowest_latency:
4188                 /* handle TSO and jumbo frames */
4189                 if (bytes/packets > 8000)
4190                         itrval = bulk_latency;
4191                 else if ((packets < 5) && (bytes > 512))
4192                         itrval = low_latency;
4193                 break;
4194         case low_latency:  /* 50 usec aka 20000 ints/s */
4195                 if (bytes > 10000) {
4196                         /* this if handles the TSO accounting */
4197                         if (bytes/packets > 8000) {
4198                                 itrval = bulk_latency;
4199                         } else if ((packets < 10) || ((bytes/packets) > 1200)) {
4200                                 itrval = bulk_latency;
4201                         } else if ((packets > 35)) {
4202                                 itrval = lowest_latency;
4203                         }
4204                 } else if (bytes/packets > 2000) {
4205                         itrval = bulk_latency;
4206                 } else if (packets <= 2 && bytes < 512) {
4207                         itrval = lowest_latency;
4208                 }
4209                 break;
4210         case bulk_latency: /* 250 usec aka 4000 ints/s */
4211                 if (bytes > 25000) {
4212                         if (packets > 35)
4213                                 itrval = low_latency;
4214                 } else if (bytes < 1500) {
4215                         itrval = low_latency;
4216                 }
4217                 break;
4218         }
4219
4220         /* clear work counters since we have the values we need */
4221         ring_container->total_bytes = 0;
4222         ring_container->total_packets = 0;
4223
4224         /* write updated itr to ring container */
4225         ring_container->itr = itrval;
4226 }
4227
4228 static void igb_set_itr(struct igb_q_vector *q_vector)
4229 {
4230         struct igb_adapter *adapter = q_vector->adapter;
4231         u32 new_itr = q_vector->itr_val;
4232         u8 current_itr = 0;
4233
4234         /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4235         if (adapter->link_speed != SPEED_1000) {
4236                 current_itr = 0;
4237                 new_itr = IGB_4K_ITR;
4238                 goto set_itr_now;
4239         }
4240
4241         igb_update_itr(q_vector, &q_vector->tx);
4242         igb_update_itr(q_vector, &q_vector->rx);
4243
4244         current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
4245
4246         /* conservative mode (itr 3) eliminates the lowest_latency setting */
4247         if (current_itr == lowest_latency &&
4248             ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4249              (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4250                 current_itr = low_latency;
4251
4252         switch (current_itr) {
4253         /* counts and packets in update_itr are dependent on these numbers */
4254         case lowest_latency:
4255                 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
4256                 break;
4257         case low_latency:
4258                 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
4259                 break;
4260         case bulk_latency:
4261                 new_itr = IGB_4K_ITR;  /* 4,000 ints/sec */
4262                 break;
4263         default:
4264                 break;
4265         }
4266
4267 set_itr_now:
4268         if (new_itr != q_vector->itr_val) {
4269                 /* this attempts to bias the interrupt rate towards Bulk
4270                  * by adding intermediate steps when interrupt rate is
4271                  * increasing
4272                  */
4273                 new_itr = new_itr > q_vector->itr_val ?
4274                           max((new_itr * q_vector->itr_val) /
4275                           (new_itr + (q_vector->itr_val >> 2)),
4276                           new_itr) : new_itr;
4277                 /* Don't write the value here; it resets the adapter's
4278                  * internal timer, and causes us to delay far longer than
4279                  * we should between interrupts.  Instead, we write the ITR
4280                  * value at the beginning of the next interrupt so the timing
4281                  * ends up being correct.
4282                  */
4283                 q_vector->itr_val = new_itr;
4284                 q_vector->set_itr = 1;
4285         }
4286 }
4287
4288 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4289                             u32 type_tucmd, u32 mss_l4len_idx)
4290 {
4291         struct e1000_adv_tx_context_desc *context_desc;
4292         u16 i = tx_ring->next_to_use;
4293
4294         context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4295
4296         i++;
4297         tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4298
4299         /* set bits to identify this as an advanced context descriptor */
4300         type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4301
4302         /* For 82575, context index must be unique per ring. */
4303         if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4304                 mss_l4len_idx |= tx_ring->reg_idx << 4;
4305
4306         context_desc->vlan_macip_lens   = cpu_to_le32(vlan_macip_lens);
4307         context_desc->seqnum_seed       = 0;
4308         context_desc->type_tucmd_mlhl   = cpu_to_le32(type_tucmd);
4309         context_desc->mss_l4len_idx     = cpu_to_le32(mss_l4len_idx);
4310 }
4311
4312 static int igb_tso(struct igb_ring *tx_ring,
4313                    struct igb_tx_buffer *first,
4314                    u8 *hdr_len)
4315 {
4316         struct sk_buff *skb = first->skb;
4317         u32 vlan_macip_lens, type_tucmd;
4318         u32 mss_l4len_idx, l4len;
4319
4320         if (skb->ip_summed != CHECKSUM_PARTIAL)
4321                 return 0;
4322
4323         if (!skb_is_gso(skb))
4324                 return 0;
4325
4326         if (skb_header_cloned(skb)) {
4327                 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4328                 if (err)
4329                         return err;
4330         }
4331
4332         /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4333         type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
4334
4335         if (first->protocol == __constant_htons(ETH_P_IP)) {
4336                 struct iphdr *iph = ip_hdr(skb);
4337                 iph->tot_len = 0;
4338                 iph->check = 0;
4339                 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4340                                                          iph->daddr, 0,
4341                                                          IPPROTO_TCP,
4342                                                          0);
4343                 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4344                 first->tx_flags |= IGB_TX_FLAGS_TSO |
4345                                    IGB_TX_FLAGS_CSUM |
4346                                    IGB_TX_FLAGS_IPV4;
4347         } else if (skb_is_gso_v6(skb)) {
4348                 ipv6_hdr(skb)->payload_len = 0;
4349                 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4350                                                        &ipv6_hdr(skb)->daddr,
4351                                                        0, IPPROTO_TCP, 0);
4352                 first->tx_flags |= IGB_TX_FLAGS_TSO |
4353                                    IGB_TX_FLAGS_CSUM;
4354         }
4355
4356         /* compute header lengths */
4357         l4len = tcp_hdrlen(skb);
4358         *hdr_len = skb_transport_offset(skb) + l4len;
4359
4360         /* update gso size and bytecount with header size */
4361         first->gso_segs = skb_shinfo(skb)->gso_segs;
4362         first->bytecount += (first->gso_segs - 1) * *hdr_len;
4363
4364         /* MSS L4LEN IDX */
4365         mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4366         mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
4367
4368         /* VLAN MACLEN IPLEN */
4369         vlan_macip_lens = skb_network_header_len(skb);
4370         vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4371         vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4372
4373         igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4374
4375         return 1;
4376 }
4377
4378 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
4379 {
4380         struct sk_buff *skb = first->skb;
4381         u32 vlan_macip_lens = 0;
4382         u32 mss_l4len_idx = 0;
4383         u32 type_tucmd = 0;
4384
4385         if (skb->ip_summed != CHECKSUM_PARTIAL) {
4386                 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4387                         return;
4388         } else {
4389                 u8 l4_hdr = 0;
4390                 switch (first->protocol) {
4391                 case __constant_htons(ETH_P_IP):
4392                         vlan_macip_lens |= skb_network_header_len(skb);
4393                         type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4394                         l4_hdr = ip_hdr(skb)->protocol;
4395                         break;
4396                 case __constant_htons(ETH_P_IPV6):
4397                         vlan_macip_lens |= skb_network_header_len(skb);
4398                         l4_hdr = ipv6_hdr(skb)->nexthdr;
4399                         break;
4400                 default:
4401                         if (unlikely(net_ratelimit())) {
4402                                 dev_warn(tx_ring->dev,
4403                                          "partial checksum but proto=%x!\n",
4404                                          first->protocol);
4405                         }
4406                         break;
4407                 }
4408
4409                 switch (l4_hdr) {
4410                 case IPPROTO_TCP:
4411                         type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4412                         mss_l4len_idx = tcp_hdrlen(skb) <<
4413                                         E1000_ADVTXD_L4LEN_SHIFT;
4414                         break;
4415                 case IPPROTO_SCTP:
4416                         type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4417                         mss_l4len_idx = sizeof(struct sctphdr) <<
4418                                         E1000_ADVTXD_L4LEN_SHIFT;
4419                         break;
4420                 case IPPROTO_UDP:
4421                         mss_l4len_idx = sizeof(struct udphdr) <<
4422                                         E1000_ADVTXD_L4LEN_SHIFT;
4423                         break;
4424                 default:
4425                         if (unlikely(net_ratelimit())) {
4426                                 dev_warn(tx_ring->dev,
4427                                          "partial checksum but l4 proto=%x!\n",
4428                                          l4_hdr);
4429                         }
4430                         break;
4431                 }
4432
4433                 /* update TX checksum flag */
4434                 first->tx_flags |= IGB_TX_FLAGS_CSUM;
4435         }
4436
4437         vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4438         vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4439
4440         igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4441 }
4442
4443 #define IGB_SET_FLAG(_input, _flag, _result) \
4444         ((_flag <= _result) ? \
4445          ((u32)(_input & _flag) * (_result / _flag)) : \
4446          ((u32)(_input & _flag) / (_flag / _result)))
4447
4448 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
4449 {
4450         /* set type for advanced descriptor with frame checksum insertion */
4451         u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4452                        E1000_ADVTXD_DCMD_DEXT |
4453                        E1000_ADVTXD_DCMD_IFCS;
4454
4455         /* set HW vlan bit if vlan is present */
4456         cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4457                                  (E1000_ADVTXD_DCMD_VLE));
4458
4459         /* set segmentation bits for TSO */
4460         cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4461                                  (E1000_ADVTXD_DCMD_TSE));
4462
4463         /* set timestamp bit if present */
4464         cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4465                                  (E1000_ADVTXD_MAC_TSTAMP));
4466
4467         /* insert frame checksum */
4468         cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
4469
4470         return cmd_type;
4471 }
4472
4473 static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4474                                  union e1000_adv_tx_desc *tx_desc,
4475                                  u32 tx_flags, unsigned int paylen)
4476 {
4477         u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4478
4479         /* 82575 requires a unique index per ring */
4480         if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4481                 olinfo_status |= tx_ring->reg_idx << 4;
4482
4483         /* insert L4 checksum */
4484         olinfo_status |= IGB_SET_FLAG(tx_flags,
4485                                       IGB_TX_FLAGS_CSUM,
4486                                       (E1000_TXD_POPTS_TXSM << 8));
4487
4488         /* insert IPv4 checksum */
4489         olinfo_status |= IGB_SET_FLAG(tx_flags,
4490                                       IGB_TX_FLAGS_IPV4,
4491                                       (E1000_TXD_POPTS_IXSM << 8));
4492
4493         tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
4494 }
4495
4496 static void igb_tx_map(struct igb_ring *tx_ring,
4497                        struct igb_tx_buffer *first,
4498                        const u8 hdr_len)
4499 {
4500         struct sk_buff *skb = first->skb;
4501         struct igb_tx_buffer *tx_buffer;
4502         union e1000_adv_tx_desc *tx_desc;
4503         struct skb_frag_struct *frag;
4504         dma_addr_t dma;
4505         unsigned int data_len, size;
4506         u32 tx_flags = first->tx_flags;
4507         u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
4508         u16 i = tx_ring->next_to_use;
4509
4510         tx_desc = IGB_TX_DESC(tx_ring, i);
4511
4512         igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4513
4514         size = skb_headlen(skb);
4515         data_len = skb->data_len;
4516
4517         dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
4518
4519         tx_buffer = first;
4520
4521         for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4522                 if (dma_mapping_error(tx_ring->dev, dma))
4523                         goto dma_error;
4524
4525                 /* record length, and DMA address */
4526                 dma_unmap_len_set(tx_buffer, len, size);
4527                 dma_unmap_addr_set(tx_buffer, dma, dma);
4528
4529                 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4530
4531                 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4532                         tx_desc->read.cmd_type_len =
4533                                 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
4534
4535                         i++;
4536                         tx_desc++;
4537                         if (i == tx_ring->count) {
4538                                 tx_desc = IGB_TX_DESC(tx_ring, 0);
4539                                 i = 0;
4540                         }
4541                         tx_desc->read.olinfo_status = 0;
4542
4543                         dma += IGB_MAX_DATA_PER_TXD;
4544                         size -= IGB_MAX_DATA_PER_TXD;
4545
4546                         tx_desc->read.buffer_addr = cpu_to_le64(dma);
4547                 }
4548
4549                 if (likely(!data_len))
4550                         break;
4551
4552                 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
4553
4554                 i++;
4555                 tx_desc++;
4556                 if (i == tx_ring->count) {
4557                         tx_desc = IGB_TX_DESC(tx_ring, 0);
4558                         i = 0;
4559                 }
4560                 tx_desc->read.olinfo_status = 0;
4561
4562                 size = skb_frag_size(frag);
4563                 data_len -= size;
4564
4565                 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
4566                                        size, DMA_TO_DEVICE);
4567
4568                 tx_buffer = &tx_ring->tx_buffer_info[i];
4569         }
4570
4571         /* write last descriptor with RS and EOP bits */
4572         cmd_type |= size | IGB_TXD_DCMD;
4573         tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
4574
4575         netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4576
4577         /* set the timestamp */
4578         first->time_stamp = jiffies;
4579
4580         /* Force memory writes to complete before letting h/w know there
4581          * are new descriptors to fetch.  (Only applicable for weak-ordered
4582          * memory model archs, such as IA-64).
4583          *
4584          * We also need this memory barrier to make certain all of the
4585          * status bits have been updated before next_to_watch is written.
4586          */
4587         wmb();
4588
4589         /* set next_to_watch value indicating a packet is present */
4590         first->next_to_watch = tx_desc;
4591
4592         i++;
4593         if (i == tx_ring->count)
4594                 i = 0;
4595
4596         tx_ring->next_to_use = i;
4597
4598         writel(i, tx_ring->tail);
4599
4600         /* we need this if more than one processor can write to our tail
4601          * at a time, it synchronizes IO on IA64/Altix systems
4602          */
4603         mmiowb();
4604
4605         return;
4606
4607 dma_error:
4608         dev_err(tx_ring->dev, "TX DMA map failed\n");
4609
4610         /* clear dma mappings for failed tx_buffer_info map */
4611         for (;;) {
4612                 tx_buffer = &tx_ring->tx_buffer_info[i];
4613                 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4614                 if (tx_buffer == first)
4615                         break;
4616                 if (i == 0)
4617                         i = tx_ring->count;
4618                 i--;
4619         }
4620
4621         tx_ring->next_to_use = i;
4622 }
4623
4624 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4625 {
4626         struct net_device *netdev = tx_ring->netdev;
4627
4628         netif_stop_subqueue(netdev, tx_ring->queue_index);
4629
4630         /* Herbert's original patch had:
4631          *  smp_mb__after_netif_stop_queue();
4632          * but since that doesn't exist yet, just open code it.
4633          */
4634         smp_mb();
4635
4636         /* We need to check again in a case another CPU has just
4637          * made room available.
4638          */
4639         if (igb_desc_unused(tx_ring) < size)
4640                 return -EBUSY;
4641
4642         /* A reprieve! */
4643         netif_wake_subqueue(netdev, tx_ring->queue_index);
4644
4645         u64_stats_update_begin(&tx_ring->tx_syncp2);
4646         tx_ring->tx_stats.restart_queue2++;
4647         u64_stats_update_end(&tx_ring->tx_syncp2);
4648
4649         return 0;
4650 }
4651
4652 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4653 {
4654         if (igb_desc_unused(tx_ring) >= size)
4655                 return 0;
4656         return __igb_maybe_stop_tx(tx_ring, size);
4657 }
4658
4659 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4660                                 struct igb_ring *tx_ring)
4661 {
4662         struct igb_tx_buffer *first;
4663         int tso;
4664         u32 tx_flags = 0;
4665         u16 count = TXD_USE_COUNT(skb_headlen(skb));
4666         __be16 protocol = vlan_get_protocol(skb);
4667         u8 hdr_len = 0;
4668
4669         /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
4670          *       + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
4671          *       + 2 desc gap to keep tail from touching head,
4672          *       + 1 desc for context descriptor,
4673          * otherwise try next time
4674          */
4675         if (NETDEV_FRAG_PAGE_MAX_SIZE > IGB_MAX_DATA_PER_TXD) {
4676                 unsigned short f;
4677                 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
4678                         count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4679         } else {
4680                 count += skb_shinfo(skb)->nr_frags;
4681         }
4682
4683         if (igb_maybe_stop_tx(tx_ring, count + 3)) {
4684                 /* this is a hard error */
4685                 return NETDEV_TX_BUSY;
4686         }
4687
4688         /* record the location of the first descriptor for this packet */
4689         first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
4690         first->skb = skb;
4691         first->bytecount = skb->len;
4692         first->gso_segs = 1;
4693
4694         skb_tx_timestamp(skb);
4695
4696         if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
4697                 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
4698
4699                 if (!(adapter->ptp_tx_skb)) {
4700                         skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4701                         tx_flags |= IGB_TX_FLAGS_TSTAMP;
4702
4703                         adapter->ptp_tx_skb = skb_get(skb);
4704                         adapter->ptp_tx_start = jiffies;
4705                         if (adapter->hw.mac.type == e1000_82576)
4706                                 schedule_work(&adapter->ptp_tx_work);
4707                 }
4708         }
4709
4710         if (vlan_tx_tag_present(skb)) {
4711                 tx_flags |= IGB_TX_FLAGS_VLAN;
4712                 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
4713         }
4714
4715         /* record initial flags and protocol */
4716         first->tx_flags = tx_flags;
4717         first->protocol = protocol;
4718
4719         tso = igb_tso(tx_ring, first, &hdr_len);
4720         if (tso < 0)
4721                 goto out_drop;
4722         else if (!tso)
4723                 igb_tx_csum(tx_ring, first);
4724
4725         igb_tx_map(tx_ring, first, hdr_len);
4726
4727         /* Make sure there is space in the ring for the next send. */
4728         igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
4729
4730         return NETDEV_TX_OK;
4731
4732 out_drop:
4733         igb_unmap_and_free_tx_resource(tx_ring, first);
4734
4735         return NETDEV_TX_OK;
4736 }
4737
4738 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
4739                                                     struct sk_buff *skb)
4740 {
4741         unsigned int r_idx = skb->queue_mapping;
4742
4743         if (r_idx >= adapter->num_tx_queues)
4744                 r_idx = r_idx % adapter->num_tx_queues;
4745
4746         return adapter->tx_ring[r_idx];
4747 }
4748
4749 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
4750                                   struct net_device *netdev)
4751 {
4752         struct igb_adapter *adapter = netdev_priv(netdev);
4753
4754         if (test_bit(__IGB_DOWN, &adapter->state)) {
4755                 dev_kfree_skb_any(skb);
4756                 return NETDEV_TX_OK;
4757         }
4758
4759         if (skb->len <= 0) {
4760                 dev_kfree_skb_any(skb);
4761                 return NETDEV_TX_OK;
4762         }
4763
4764         /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
4765          * in order to meet this minimum size requirement.
4766          */
4767         if (unlikely(skb->len < 17)) {
4768                 if (skb_pad(skb, 17 - skb->len))
4769                         return NETDEV_TX_OK;
4770                 skb->len = 17;
4771                 skb_set_tail_pointer(skb, 17);
4772         }
4773
4774         return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
4775 }
4776
4777 /**
4778  *  igb_tx_timeout - Respond to a Tx Hang
4779  *  @netdev: network interface device structure
4780  **/
4781 static void igb_tx_timeout(struct net_device *netdev)
4782 {
4783         struct igb_adapter *adapter = netdev_priv(netdev);
4784         struct e1000_hw *hw = &adapter->hw;
4785
4786         /* Do the reset outside of interrupt context */
4787         adapter->tx_timeout_count++;
4788
4789         if (hw->mac.type >= e1000_82580)
4790                 hw->dev_spec._82575.global_device_reset = true;
4791
4792         schedule_work(&adapter->reset_task);
4793         wr32(E1000_EICS,
4794              (adapter->eims_enable_mask & ~adapter->eims_other));
4795 }
4796
4797 static void igb_reset_task(struct work_struct *work)
4798 {
4799         struct igb_adapter *adapter;
4800         adapter = container_of(work, struct igb_adapter, reset_task);
4801
4802         igb_dump(adapter);
4803         netdev_err(adapter->netdev, "Reset adapter\n");
4804         igb_reinit_locked(adapter);
4805 }
4806
4807 /**
4808  *  igb_get_stats64 - Get System Network Statistics
4809  *  @netdev: network interface device structure
4810  *  @stats: rtnl_link_stats64 pointer
4811  **/
4812 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
4813                                                 struct rtnl_link_stats64 *stats)
4814 {
4815         struct igb_adapter *adapter = netdev_priv(netdev);
4816
4817         spin_lock(&adapter->stats64_lock);
4818         igb_update_stats(adapter, &adapter->stats64);
4819         memcpy(stats, &adapter->stats64, sizeof(*stats));
4820         spin_unlock(&adapter->stats64_lock);
4821
4822         return stats;
4823 }
4824
4825 /**
4826  *  igb_change_mtu - Change the Maximum Transfer Unit
4827  *  @netdev: network interface device structure
4828  *  @new_mtu: new value for maximum frame size
4829  *
4830  *  Returns 0 on success, negative on failure
4831  **/
4832 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
4833 {
4834         struct igb_adapter *adapter = netdev_priv(netdev);
4835         struct pci_dev *pdev = adapter->pdev;
4836         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
4837
4838         if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
4839                 dev_err(&pdev->dev, "Invalid MTU setting\n");
4840                 return -EINVAL;
4841         }
4842
4843 #define MAX_STD_JUMBO_FRAME_SIZE 9238
4844         if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
4845                 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
4846                 return -EINVAL;
4847         }
4848
4849         /* adjust max frame to be at least the size of a standard frame */
4850         if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
4851                 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
4852
4853         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
4854                 msleep(1);
4855
4856         /* igb_down has a dependency on max_frame_size */
4857         adapter->max_frame_size = max_frame;
4858
4859         if (netif_running(netdev))
4860                 igb_down(adapter);
4861
4862         dev_info(&pdev->dev, "changing MTU from %d to %d\n",
4863                  netdev->mtu, new_mtu);
4864         netdev->mtu = new_mtu;
4865
4866         if (netif_running(netdev))
4867                 igb_up(adapter);
4868         else
4869                 igb_reset(adapter);
4870
4871         clear_bit(__IGB_RESETTING, &adapter->state);
4872
4873         return 0;
4874 }
4875
4876 /**
4877  *  igb_update_stats - Update the board statistics counters
4878  *  @adapter: board private structure
4879  **/
4880 void igb_update_stats(struct igb_adapter *adapter,
4881                       struct rtnl_link_stats64 *net_stats)
4882 {
4883         struct e1000_hw *hw = &adapter->hw;
4884         struct pci_dev *pdev = adapter->pdev;
4885         u32 reg, mpc;
4886         u16 phy_tmp;
4887         int i;
4888         u64 bytes, packets;
4889         unsigned int start;
4890         u64 _bytes, _packets;
4891
4892 #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
4893
4894         /* Prevent stats update while adapter is being reset, or if the pci
4895          * connection is down.
4896          */
4897         if (adapter->link_speed == 0)
4898                 return;
4899         if (pci_channel_offline(pdev))
4900                 return;
4901
4902         bytes = 0;
4903         packets = 0;
4904
4905         rcu_read_lock();
4906         for (i = 0; i < adapter->num_rx_queues; i++) {
4907                 u32 rqdpc = rd32(E1000_RQDPC(i));
4908                 struct igb_ring *ring = adapter->rx_ring[i];
4909
4910                 if (rqdpc) {
4911                         ring->rx_stats.drops += rqdpc;
4912                         net_stats->rx_fifo_errors += rqdpc;
4913                 }
4914
4915                 do {
4916                         start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
4917                         _bytes = ring->rx_stats.bytes;
4918                         _packets = ring->rx_stats.packets;
4919                 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
4920                 bytes += _bytes;
4921                 packets += _packets;
4922         }
4923
4924         net_stats->rx_bytes = bytes;
4925         net_stats->rx_packets = packets;
4926
4927         bytes = 0;
4928         packets = 0;
4929         for (i = 0; i < adapter->num_tx_queues; i++) {
4930                 struct igb_ring *ring = adapter->tx_ring[i];
4931                 do {
4932                         start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
4933                         _bytes = ring->tx_stats.bytes;
4934                         _packets = ring->tx_stats.packets;
4935                 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
4936                 bytes += _bytes;
4937                 packets += _packets;
4938         }
4939         net_stats->tx_bytes = bytes;
4940         net_stats->tx_packets = packets;
4941         rcu_read_unlock();
4942
4943         /* read stats registers */
4944         adapter->stats.crcerrs += rd32(E1000_CRCERRS);
4945         adapter->stats.gprc += rd32(E1000_GPRC);
4946         adapter->stats.gorc += rd32(E1000_GORCL);
4947         rd32(E1000_GORCH); /* clear GORCL */
4948         adapter->stats.bprc += rd32(E1000_BPRC);
4949         adapter->stats.mprc += rd32(E1000_MPRC);
4950         adapter->stats.roc += rd32(E1000_ROC);
4951
4952         adapter->stats.prc64 += rd32(E1000_PRC64);
4953         adapter->stats.prc127 += rd32(E1000_PRC127);
4954         adapter->stats.prc255 += rd32(E1000_PRC255);
4955         adapter->stats.prc511 += rd32(E1000_PRC511);
4956         adapter->stats.prc1023 += rd32(E1000_PRC1023);
4957         adapter->stats.prc1522 += rd32(E1000_PRC1522);
4958         adapter->stats.symerrs += rd32(E1000_SYMERRS);
4959         adapter->stats.sec += rd32(E1000_SEC);
4960
4961         mpc = rd32(E1000_MPC);
4962         adapter->stats.mpc += mpc;
4963         net_stats->rx_fifo_errors += mpc;
4964         adapter->stats.scc += rd32(E1000_SCC);
4965         adapter->stats.ecol += rd32(E1000_ECOL);
4966         adapter->stats.mcc += rd32(E1000_MCC);
4967         adapter->stats.latecol += rd32(E1000_LATECOL);
4968         adapter->stats.dc += rd32(E1000_DC);
4969         adapter->stats.rlec += rd32(E1000_RLEC);
4970         adapter->stats.xonrxc += rd32(E1000_XONRXC);
4971         adapter->stats.xontxc += rd32(E1000_XONTXC);
4972         adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
4973         adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
4974         adapter->stats.fcruc += rd32(E1000_FCRUC);
4975         adapter->stats.gptc += rd32(E1000_GPTC);
4976         adapter->stats.gotc += rd32(E1000_GOTCL);
4977         rd32(E1000_GOTCH); /* clear GOTCL */
4978         adapter->stats.rnbc += rd32(E1000_RNBC);
4979         adapter->stats.ruc += rd32(E1000_RUC);
4980         adapter->stats.rfc += rd32(E1000_RFC);
4981         adapter->stats.rjc += rd32(E1000_RJC);
4982         adapter->stats.tor += rd32(E1000_TORH);
4983         adapter->stats.tot += rd32(E1000_TOTH);
4984         adapter->stats.tpr += rd32(E1000_TPR);
4985
4986         adapter->stats.ptc64 += rd32(E1000_PTC64);
4987         adapter->stats.ptc127 += rd32(E1000_PTC127);
4988         adapter->stats.ptc255 += rd32(E1000_PTC255);
4989         adapter->stats.ptc511 += rd32(E1000_PTC511);
4990         adapter->stats.ptc1023 += rd32(E1000_PTC1023);
4991         adapter->stats.ptc1522 += rd32(E1000_PTC1522);
4992
4993         adapter->stats.mptc += rd32(E1000_MPTC);
4994         adapter->stats.bptc += rd32(E1000_BPTC);
4995
4996         adapter->stats.tpt += rd32(E1000_TPT);
4997         adapter->stats.colc += rd32(E1000_COLC);
4998
4999         adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
5000         /* read internal phy specific stats */
5001         reg = rd32(E1000_CTRL_EXT);
5002         if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
5003                 adapter->stats.rxerrc += rd32(E1000_RXERRC);
5004
5005                 /* this stat has invalid values on i210/i211 */
5006                 if ((hw->mac.type != e1000_i210) &&
5007                     (hw->mac.type != e1000_i211))
5008                         adapter->stats.tncrs += rd32(E1000_TNCRS);
5009         }
5010
5011         adapter->stats.tsctc += rd32(E1000_TSCTC);
5012         adapter->stats.tsctfc += rd32(E1000_TSCTFC);
5013
5014         adapter->stats.iac += rd32(E1000_IAC);
5015         adapter->stats.icrxoc += rd32(E1000_ICRXOC);
5016         adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
5017         adapter->stats.icrxatc += rd32(E1000_ICRXATC);
5018         adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
5019         adapter->stats.ictxatc += rd32(E1000_ICTXATC);
5020         adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
5021         adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5022         adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5023
5024         /* Fill out the OS statistics structure */
5025         net_stats->multicast = adapter->stats.mprc;
5026         net_stats->collisions = adapter->stats.colc;
5027
5028         /* Rx Errors */
5029
5030         /* RLEC on some newer hardware can be incorrect so build
5031          * our own version based on RUC and ROC
5032          */
5033         net_stats->rx_errors = adapter->stats.rxerrc +
5034                 adapter->stats.crcerrs + adapter->stats.algnerrc +
5035                 adapter->stats.ruc + adapter->stats.roc +
5036                 adapter->stats.cexterr;
5037         net_stats->rx_length_errors = adapter->stats.ruc +
5038                                       adapter->stats.roc;
5039         net_stats->rx_crc_errors = adapter->stats.crcerrs;
5040         net_stats->rx_frame_errors = adapter->stats.algnerrc;
5041         net_stats->rx_missed_errors = adapter->stats.mpc;
5042
5043         /* Tx Errors */
5044         net_stats->tx_errors = adapter->stats.ecol +
5045                                adapter->stats.latecol;
5046         net_stats->tx_aborted_errors = adapter->stats.ecol;
5047         net_stats->tx_window_errors = adapter->stats.latecol;
5048         net_stats->tx_carrier_errors = adapter->stats.tncrs;
5049
5050         /* Tx Dropped needs to be maintained elsewhere */
5051
5052         /* Phy Stats */
5053         if (hw->phy.media_type == e1000_media_type_copper) {
5054                 if ((adapter->link_speed == SPEED_1000) &&
5055                    (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
5056                         phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
5057                         adapter->phy_stats.idle_errors += phy_tmp;
5058                 }
5059         }
5060
5061         /* Management Stats */
5062         adapter->stats.mgptc += rd32(E1000_MGTPTC);
5063         adapter->stats.mgprc += rd32(E1000_MGTPRC);
5064         adapter->stats.mgpdc += rd32(E1000_MGTPDC);
5065
5066         /* OS2BMC Stats */
5067         reg = rd32(E1000_MANC);
5068         if (reg & E1000_MANC_EN_BMC2OS) {
5069                 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5070                 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5071                 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5072                 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5073         }
5074 }
5075
5076 static irqreturn_t igb_msix_other(int irq, void *data)
5077 {
5078         struct igb_adapter *adapter = data;
5079         struct e1000_hw *hw = &adapter->hw;
5080         u32 icr = rd32(E1000_ICR);
5081         /* reading ICR causes bit 31 of EICR to be cleared */
5082
5083         if (icr & E1000_ICR_DRSTA)
5084                 schedule_work(&adapter->reset_task);
5085
5086         if (icr & E1000_ICR_DOUTSYNC) {
5087                 /* HW is reporting DMA is out of sync */
5088                 adapter->stats.doosync++;
5089                 /* The DMA Out of Sync is also indication of a spoof event
5090                  * in IOV mode. Check the Wrong VM Behavior register to
5091                  * see if it is really a spoof event.
5092                  */
5093                 igb_check_wvbr(adapter);
5094         }
5095
5096         /* Check for a mailbox event */
5097         if (icr & E1000_ICR_VMMB)
5098                 igb_msg_task(adapter);
5099
5100         if (icr & E1000_ICR_LSC) {
5101                 hw->mac.get_link_status = 1;
5102                 /* guard against interrupt when we're going down */
5103                 if (!test_bit(__IGB_DOWN, &adapter->state))
5104                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
5105         }
5106
5107         if (icr & E1000_ICR_TS) {
5108                 u32 tsicr = rd32(E1000_TSICR);
5109
5110                 if (tsicr & E1000_TSICR_TXTS) {
5111                         /* acknowledge the interrupt */
5112                         wr32(E1000_TSICR, E1000_TSICR_TXTS);
5113                         /* retrieve hardware timestamp */
5114                         schedule_work(&adapter->ptp_tx_work);
5115                 }
5116         }
5117
5118         wr32(E1000_EIMS, adapter->eims_other);
5119
5120         return IRQ_HANDLED;
5121 }
5122
5123 static void igb_write_itr(struct igb_q_vector *q_vector)
5124 {
5125         struct igb_adapter *adapter = q_vector->adapter;
5126         u32 itr_val = q_vector->itr_val & 0x7FFC;
5127
5128         if (!q_vector->set_itr)
5129                 return;
5130
5131         if (!itr_val)
5132                 itr_val = 0x4;
5133
5134         if (adapter->hw.mac.type == e1000_82575)
5135                 itr_val |= itr_val << 16;
5136         else
5137                 itr_val |= E1000_EITR_CNT_IGNR;
5138
5139         writel(itr_val, q_vector->itr_register);
5140         q_vector->set_itr = 0;
5141 }
5142
5143 static irqreturn_t igb_msix_ring(int irq, void *data)
5144 {
5145         struct igb_q_vector *q_vector = data;
5146
5147         /* Write the ITR value calculated from the previous interrupt. */
5148         igb_write_itr(q_vector);
5149
5150         napi_schedule(&q_vector->napi);
5151
5152         return IRQ_HANDLED;
5153 }
5154
5155 #ifdef CONFIG_IGB_DCA
5156 static void igb_update_tx_dca(struct igb_adapter *adapter,
5157                               struct igb_ring *tx_ring,
5158                               int cpu)
5159 {
5160         struct e1000_hw *hw = &adapter->hw;
5161         u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5162
5163         if (hw->mac.type != e1000_82575)
5164                 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5165
5166         /* We can enable relaxed ordering for reads, but not writes when
5167          * DCA is enabled.  This is due to a known issue in some chipsets
5168          * which will cause the DCA tag to be cleared.
5169          */
5170         txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5171                   E1000_DCA_TXCTRL_DATA_RRO_EN |
5172                   E1000_DCA_TXCTRL_DESC_DCA_EN;
5173
5174         wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5175 }
5176
5177 static void igb_update_rx_dca(struct igb_adapter *adapter,
5178                               struct igb_ring *rx_ring,
5179                               int cpu)
5180 {
5181         struct e1000_hw *hw = &adapter->hw;
5182         u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5183
5184         if (hw->mac.type != e1000_82575)
5185                 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5186
5187         /* We can enable relaxed ordering for reads, but not writes when
5188          * DCA is enabled.  This is due to a known issue in some chipsets
5189          * which will cause the DCA tag to be cleared.
5190          */
5191         rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5192                   E1000_DCA_RXCTRL_DESC_DCA_EN;
5193
5194         wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5195 }
5196
5197 static void igb_update_dca(struct igb_q_vector *q_vector)
5198 {
5199         struct igb_adapter *adapter = q_vector->adapter;
5200         int cpu = get_cpu();
5201
5202         if (q_vector->cpu == cpu)
5203                 goto out_no_update;
5204
5205         if (q_vector->tx.ring)
5206                 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5207
5208         if (q_vector->rx.ring)
5209                 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5210
5211         q_vector->cpu = cpu;
5212 out_no_update:
5213         put_cpu();
5214 }
5215
5216 static void igb_setup_dca(struct igb_adapter *adapter)
5217 {
5218         struct e1000_hw *hw = &adapter->hw;
5219         int i;
5220
5221         if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
5222                 return;
5223
5224         /* Always use CB2 mode, difference is masked in the CB driver. */
5225         wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5226
5227         for (i = 0; i < adapter->num_q_vectors; i++) {
5228                 adapter->q_vector[i]->cpu = -1;
5229                 igb_update_dca(adapter->q_vector[i]);
5230         }
5231 }
5232
5233 static int __igb_notify_dca(struct device *dev, void *data)
5234 {
5235         struct net_device *netdev = dev_get_drvdata(dev);
5236         struct igb_adapter *adapter = netdev_priv(netdev);
5237         struct pci_dev *pdev = adapter->pdev;
5238         struct e1000_hw *hw = &adapter->hw;
5239         unsigned long event = *(unsigned long *)data;
5240
5241         switch (event) {
5242         case DCA_PROVIDER_ADD:
5243                 /* if already enabled, don't do it again */
5244                 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
5245                         break;
5246                 if (dca_add_requester(dev) == 0) {
5247                         adapter->flags |= IGB_FLAG_DCA_ENABLED;
5248                         dev_info(&pdev->dev, "DCA enabled\n");
5249                         igb_setup_dca(adapter);
5250                         break;
5251                 }
5252                 /* Fall Through since DCA is disabled. */
5253         case DCA_PROVIDER_REMOVE:
5254                 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
5255                         /* without this a class_device is left
5256                          * hanging around in the sysfs model
5257                          */
5258                         dca_remove_requester(dev);
5259                         dev_info(&pdev->dev, "DCA disabled\n");
5260                         adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
5261                         wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
5262                 }
5263                 break;
5264         }
5265
5266         return 0;
5267 }
5268
5269 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
5270                           void *p)
5271 {
5272         int ret_val;
5273
5274         ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
5275                                          __igb_notify_dca);
5276
5277         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5278 }
5279 #endif /* CONFIG_IGB_DCA */
5280
5281 #ifdef CONFIG_PCI_IOV
5282 static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5283 {
5284         unsigned char mac_addr[ETH_ALEN];
5285
5286         eth_zero_addr(mac_addr);
5287         igb_set_vf_mac(adapter, vf, mac_addr);
5288
5289         /* By default spoof check is enabled for all VFs */
5290         adapter->vf_data[vf].spoofchk_enabled = true;
5291
5292         return 0;
5293 }
5294
5295 #endif
5296 static void igb_ping_all_vfs(struct igb_adapter *adapter)
5297 {
5298         struct e1000_hw *hw = &adapter->hw;
5299         u32 ping;
5300         int i;
5301
5302         for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5303                 ping = E1000_PF_CONTROL_MSG;
5304                 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
5305                         ping |= E1000_VT_MSGTYPE_CTS;
5306                 igb_write_mbx(hw, &ping, 1, i);
5307         }
5308 }
5309
5310 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5311 {
5312         struct e1000_hw *hw = &adapter->hw;
5313         u32 vmolr = rd32(E1000_VMOLR(vf));
5314         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5315
5316         vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
5317                             IGB_VF_FLAG_MULTI_PROMISC);
5318         vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5319
5320         if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5321                 vmolr |= E1000_VMOLR_MPME;
5322                 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
5323                 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5324         } else {
5325                 /* if we have hashes and we are clearing a multicast promisc
5326                  * flag we need to write the hashes to the MTA as this step
5327                  * was previously skipped
5328                  */
5329                 if (vf_data->num_vf_mc_hashes > 30) {
5330                         vmolr |= E1000_VMOLR_MPME;
5331                 } else if (vf_data->num_vf_mc_hashes) {
5332                         int j;
5333                         vmolr |= E1000_VMOLR_ROMPE;
5334                         for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5335                                 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5336                 }
5337         }
5338
5339         wr32(E1000_VMOLR(vf), vmolr);
5340
5341         /* there are flags left unprocessed, likely not supported */
5342         if (*msgbuf & E1000_VT_MSGINFO_MASK)
5343                 return -EINVAL;
5344
5345         return 0;
5346 }
5347
5348 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5349                                   u32 *msgbuf, u32 vf)
5350 {
5351         int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5352         u16 *hash_list = (u16 *)&msgbuf[1];
5353         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5354         int i;
5355
5356         /* salt away the number of multicast addresses assigned
5357          * to this VF for later use to restore when the PF multi cast
5358          * list changes
5359          */
5360         vf_data->num_vf_mc_hashes = n;
5361
5362         /* only up to 30 hash values supported */
5363         if (n > 30)
5364                 n = 30;
5365
5366         /* store the hashes for later use */
5367         for (i = 0; i < n; i++)
5368                 vf_data->vf_mc_hashes[i] = hash_list[i];
5369
5370         /* Flush and reset the mta with the new values */
5371         igb_set_rx_mode(adapter->netdev);
5372
5373         return 0;
5374 }
5375
5376 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5377 {
5378         struct e1000_hw *hw = &adapter->hw;
5379         struct vf_data_storage *vf_data;
5380         int i, j;
5381
5382         for (i = 0; i < adapter->vfs_allocated_count; i++) {
5383                 u32 vmolr = rd32(E1000_VMOLR(i));
5384                 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5385
5386                 vf_data = &adapter->vf_data[i];
5387
5388                 if ((vf_data->num_vf_mc_hashes > 30) ||
5389                     (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5390                         vmolr |= E1000_VMOLR_MPME;
5391                 } else if (vf_data->num_vf_mc_hashes) {
5392                         vmolr |= E1000_VMOLR_ROMPE;
5393                         for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5394                                 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5395                 }
5396                 wr32(E1000_VMOLR(i), vmolr);
5397         }
5398 }
5399
5400 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5401 {
5402         struct e1000_hw *hw = &adapter->hw;
5403         u32 pool_mask, reg, vid;
5404         int i;
5405
5406         pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5407
5408         /* Find the vlan filter for this id */
5409         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5410                 reg = rd32(E1000_VLVF(i));
5411
5412                 /* remove the vf from the pool */
5413                 reg &= ~pool_mask;
5414
5415                 /* if pool is empty then remove entry from vfta */
5416                 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5417                     (reg & E1000_VLVF_VLANID_ENABLE)) {
5418                         reg = 0;
5419                         vid = reg & E1000_VLVF_VLANID_MASK;
5420                         igb_vfta_set(hw, vid, false);
5421                 }
5422
5423                 wr32(E1000_VLVF(i), reg);
5424         }
5425
5426         adapter->vf_data[vf].vlans_enabled = 0;
5427 }
5428
5429 static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5430 {
5431         struct e1000_hw *hw = &adapter->hw;
5432         u32 reg, i;
5433
5434         /* The vlvf table only exists on 82576 hardware and newer */
5435         if (hw->mac.type < e1000_82576)
5436                 return -1;
5437
5438         /* we only need to do this if VMDq is enabled */
5439         if (!adapter->vfs_allocated_count)
5440                 return -1;
5441
5442         /* Find the vlan filter for this id */
5443         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5444                 reg = rd32(E1000_VLVF(i));
5445                 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5446                     vid == (reg & E1000_VLVF_VLANID_MASK))
5447                         break;
5448         }
5449
5450         if (add) {
5451                 if (i == E1000_VLVF_ARRAY_SIZE) {
5452                         /* Did not find a matching VLAN ID entry that was
5453                          * enabled.  Search for a free filter entry, i.e.
5454                          * one without the enable bit set
5455                          */
5456                         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5457                                 reg = rd32(E1000_VLVF(i));
5458                                 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5459                                         break;
5460                         }
5461                 }
5462                 if (i < E1000_VLVF_ARRAY_SIZE) {
5463                         /* Found an enabled/available entry */
5464                         reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5465
5466                         /* if !enabled we need to set this up in vfta */
5467                         if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
5468                                 /* add VID to filter table */
5469                                 igb_vfta_set(hw, vid, true);
5470                                 reg |= E1000_VLVF_VLANID_ENABLE;
5471                         }
5472                         reg &= ~E1000_VLVF_VLANID_MASK;
5473                         reg |= vid;
5474                         wr32(E1000_VLVF(i), reg);
5475
5476                         /* do not modify RLPML for PF devices */
5477                         if (vf >= adapter->vfs_allocated_count)
5478                                 return 0;
5479
5480                         if (!adapter->vf_data[vf].vlans_enabled) {
5481                                 u32 size;
5482                                 reg = rd32(E1000_VMOLR(vf));
5483                                 size = reg & E1000_VMOLR_RLPML_MASK;
5484                                 size += 4;
5485                                 reg &= ~E1000_VMOLR_RLPML_MASK;
5486                                 reg |= size;
5487                                 wr32(E1000_VMOLR(vf), reg);
5488                         }
5489
5490                         adapter->vf_data[vf].vlans_enabled++;
5491                 }
5492         } else {
5493                 if (i < E1000_VLVF_ARRAY_SIZE) {
5494                         /* remove vf from the pool */
5495                         reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5496                         /* if pool is empty then remove entry from vfta */
5497                         if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5498                                 reg = 0;
5499                                 igb_vfta_set(hw, vid, false);
5500                         }
5501                         wr32(E1000_VLVF(i), reg);
5502
5503                         /* do not modify RLPML for PF devices */
5504                         if (vf >= adapter->vfs_allocated_count)
5505                                 return 0;
5506
5507                         adapter->vf_data[vf].vlans_enabled--;
5508                         if (!adapter->vf_data[vf].vlans_enabled) {
5509                                 u32 size;
5510                                 reg = rd32(E1000_VMOLR(vf));
5511                                 size = reg & E1000_VMOLR_RLPML_MASK;
5512                                 size -= 4;
5513                                 reg &= ~E1000_VMOLR_RLPML_MASK;
5514                                 reg |= size;
5515                                 wr32(E1000_VMOLR(vf), reg);
5516                         }
5517                 }
5518         }
5519         return 0;
5520 }
5521
5522 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5523 {
5524         struct e1000_hw *hw = &adapter->hw;
5525
5526         if (vid)
5527                 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5528         else
5529                 wr32(E1000_VMVIR(vf), 0);
5530 }
5531
5532 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5533                                int vf, u16 vlan, u8 qos)
5534 {
5535         int err = 0;
5536         struct igb_adapter *adapter = netdev_priv(netdev);
5537
5538         if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5539                 return -EINVAL;
5540         if (vlan || qos) {
5541                 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5542                 if (err)
5543                         goto out;
5544                 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5545                 igb_set_vmolr(adapter, vf, !vlan);
5546                 adapter->vf_data[vf].pf_vlan = vlan;
5547                 adapter->vf_data[vf].pf_qos = qos;
5548                 dev_info(&adapter->pdev->dev,
5549                          "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5550                 if (test_bit(__IGB_DOWN, &adapter->state)) {
5551                         dev_warn(&adapter->pdev->dev,
5552                                  "The VF VLAN has been set, but the PF device is not up.\n");
5553                         dev_warn(&adapter->pdev->dev,
5554                                  "Bring the PF device up before attempting to use the VF device.\n");
5555                 }
5556         } else {
5557                 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
5558                              false, vf);
5559                 igb_set_vmvir(adapter, vlan, vf);
5560                 igb_set_vmolr(adapter, vf, true);
5561                 adapter->vf_data[vf].pf_vlan = 0;
5562                 adapter->vf_data[vf].pf_qos = 0;
5563         }
5564 out:
5565         return err;
5566 }
5567
5568 static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid)
5569 {
5570         struct e1000_hw *hw = &adapter->hw;
5571         int i;
5572         u32 reg;
5573
5574         /* Find the vlan filter for this id */
5575         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5576                 reg = rd32(E1000_VLVF(i));
5577                 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5578                     vid == (reg & E1000_VLVF_VLANID_MASK))
5579                         break;
5580         }
5581
5582         if (i >= E1000_VLVF_ARRAY_SIZE)
5583                 i = -1;
5584
5585         return i;
5586 }
5587
5588 static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5589 {
5590         struct e1000_hw *hw = &adapter->hw;
5591         int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5592         int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
5593         int err = 0;
5594
5595         /* If in promiscuous mode we need to make sure the PF also has
5596          * the VLAN filter set.
5597          */
5598         if (add && (adapter->netdev->flags & IFF_PROMISC))
5599                 err = igb_vlvf_set(adapter, vid, add,
5600                                    adapter->vfs_allocated_count);
5601         if (err)
5602                 goto out;
5603
5604         err = igb_vlvf_set(adapter, vid, add, vf);
5605
5606         if (err)
5607                 goto out;
5608
5609         /* Go through all the checks to see if the VLAN filter should
5610          * be wiped completely.
5611          */
5612         if (!add && (adapter->netdev->flags & IFF_PROMISC)) {
5613                 u32 vlvf, bits;
5614
5615                 int regndx = igb_find_vlvf_entry(adapter, vid);
5616                 if (regndx < 0)
5617                         goto out;
5618                 /* See if any other pools are set for this VLAN filter
5619                  * entry other than the PF.
5620                  */
5621                 vlvf = bits = rd32(E1000_VLVF(regndx));
5622                 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT +
5623                               adapter->vfs_allocated_count);
5624                 /* If the filter was removed then ensure PF pool bit
5625                  * is cleared if the PF only added itself to the pool
5626                  * because the PF is in promiscuous mode.
5627                  */
5628                 if ((vlvf & VLAN_VID_MASK) == vid &&
5629                     !test_bit(vid, adapter->active_vlans) &&
5630                     !bits)
5631                         igb_vlvf_set(adapter, vid, add,
5632                                      adapter->vfs_allocated_count);
5633         }
5634
5635 out:
5636         return err;
5637 }
5638
5639 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
5640 {
5641         /* clear flags - except flag that indicates PF has set the MAC */
5642         adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
5643         adapter->vf_data[vf].last_nack = jiffies;
5644
5645         /* reset offloads to defaults */
5646         igb_set_vmolr(adapter, vf, true);
5647
5648         /* reset vlans for device */
5649         igb_clear_vf_vfta(adapter, vf);
5650         if (adapter->vf_data[vf].pf_vlan)
5651                 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5652                                     adapter->vf_data[vf].pf_vlan,
5653                                     adapter->vf_data[vf].pf_qos);
5654         else
5655                 igb_clear_vf_vfta(adapter, vf);
5656
5657         /* reset multicast table array for vf */
5658         adapter->vf_data[vf].num_vf_mc_hashes = 0;
5659
5660         /* Flush and reset the mta with the new values */
5661         igb_set_rx_mode(adapter->netdev);
5662 }
5663
5664 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5665 {
5666         unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5667
5668         /* clear mac address as we were hotplug removed/added */
5669         if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5670                 eth_zero_addr(vf_mac);
5671
5672         /* process remaining reset events */
5673         igb_vf_reset(adapter, vf);
5674 }
5675
5676 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
5677 {
5678         struct e1000_hw *hw = &adapter->hw;
5679         unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5680         int rar_entry = hw->mac.rar_entry_count - (vf + 1);
5681         u32 reg, msgbuf[3];
5682         u8 *addr = (u8 *)(&msgbuf[1]);
5683
5684         /* process all the same items cleared in a function level reset */
5685         igb_vf_reset(adapter, vf);
5686
5687         /* set vf mac address */
5688         igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
5689
5690         /* enable transmit and receive for vf */
5691         reg = rd32(E1000_VFTE);
5692         wr32(E1000_VFTE, reg | (1 << vf));
5693         reg = rd32(E1000_VFRE);
5694         wr32(E1000_VFRE, reg | (1 << vf));
5695
5696         adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
5697
5698         /* reply to reset with ack and vf mac address */
5699         msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
5700         memcpy(addr, vf_mac, ETH_ALEN);
5701         igb_write_mbx(hw, msgbuf, 3, vf);
5702 }
5703
5704 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
5705 {
5706         /* The VF MAC Address is stored in a packed array of bytes
5707          * starting at the second 32 bit word of the msg array
5708          */
5709         unsigned char *addr = (char *)&msg[1];
5710         int err = -1;
5711
5712         if (is_valid_ether_addr(addr))
5713                 err = igb_set_vf_mac(adapter, vf, addr);
5714
5715         return err;
5716 }
5717
5718 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
5719 {
5720         struct e1000_hw *hw = &adapter->hw;
5721         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5722         u32 msg = E1000_VT_MSGTYPE_NACK;
5723
5724         /* if device isn't clear to send it shouldn't be reading either */
5725         if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
5726             time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
5727                 igb_write_mbx(hw, &msg, 1, vf);
5728                 vf_data->last_nack = jiffies;
5729         }
5730 }
5731
5732 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
5733 {
5734         struct pci_dev *pdev = adapter->pdev;
5735         u32 msgbuf[E1000_VFMAILBOX_SIZE];
5736         struct e1000_hw *hw = &adapter->hw;
5737         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5738         s32 retval;
5739
5740         retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
5741
5742         if (retval) {
5743                 /* if receive failed revoke VF CTS stats and restart init */
5744                 dev_err(&pdev->dev, "Error receiving message from VF\n");
5745                 vf_data->flags &= ~IGB_VF_FLAG_CTS;
5746                 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5747                         return;
5748                 goto out;
5749         }
5750
5751         /* this is a message we already processed, do nothing */
5752         if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
5753                 return;
5754
5755         /* until the vf completes a reset it should not be
5756          * allowed to start any configuration.
5757          */
5758         if (msgbuf[0] == E1000_VF_RESET) {
5759                 igb_vf_reset_msg(adapter, vf);
5760                 return;
5761         }
5762
5763         if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
5764                 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5765                         return;
5766                 retval = -1;
5767                 goto out;
5768         }
5769
5770         switch ((msgbuf[0] & 0xFFFF)) {
5771         case E1000_VF_SET_MAC_ADDR:
5772                 retval = -EINVAL;
5773                 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
5774                         retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
5775                 else
5776                         dev_warn(&pdev->dev,
5777                                  "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
5778                                  vf);
5779                 break;
5780         case E1000_VF_SET_PROMISC:
5781                 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
5782                 break;
5783         case E1000_VF_SET_MULTICAST:
5784                 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
5785                 break;
5786         case E1000_VF_SET_LPE:
5787                 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
5788                 break;
5789         case E1000_VF_SET_VLAN:
5790                 retval = -1;
5791                 if (vf_data->pf_vlan)
5792                         dev_warn(&pdev->dev,
5793                                  "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
5794                                  vf);
5795                 else
5796                         retval = igb_set_vf_vlan(adapter, msgbuf, vf);
5797                 break;
5798         default:
5799                 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
5800                 retval = -1;
5801                 break;
5802         }
5803
5804         msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
5805 out:
5806         /* notify the VF of the results of what it sent us */
5807         if (retval)
5808                 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
5809         else
5810                 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
5811
5812         igb_write_mbx(hw, msgbuf, 1, vf);
5813 }
5814
5815 static void igb_msg_task(struct igb_adapter *adapter)
5816 {
5817         struct e1000_hw *hw = &adapter->hw;
5818         u32 vf;
5819
5820         for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
5821                 /* process any reset requests */
5822                 if (!igb_check_for_rst(hw, vf))
5823                         igb_vf_reset_event(adapter, vf);
5824
5825                 /* process any messages pending */
5826                 if (!igb_check_for_msg(hw, vf))
5827                         igb_rcv_msg_from_vf(adapter, vf);
5828
5829                 /* process any acks */
5830                 if (!igb_check_for_ack(hw, vf))
5831                         igb_rcv_ack_from_vf(adapter, vf);
5832         }
5833 }
5834
5835 /**
5836  *  igb_set_uta - Set unicast filter table address
5837  *  @adapter: board private structure
5838  *
5839  *  The unicast table address is a register array of 32-bit registers.
5840  *  The table is meant to be used in a way similar to how the MTA is used
5841  *  however due to certain limitations in the hardware it is necessary to
5842  *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
5843  *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
5844  **/
5845 static void igb_set_uta(struct igb_adapter *adapter)
5846 {
5847         struct e1000_hw *hw = &adapter->hw;
5848         int i;
5849
5850         /* The UTA table only exists on 82576 hardware and newer */
5851         if (hw->mac.type < e1000_82576)
5852                 return;
5853
5854         /* we only need to do this if VMDq is enabled */
5855         if (!adapter->vfs_allocated_count)
5856                 return;
5857
5858         for (i = 0; i < hw->mac.uta_reg_count; i++)
5859                 array_wr32(E1000_UTA, i, ~0);
5860 }
5861
5862 /**
5863  *  igb_intr_msi - Interrupt Handler
5864  *  @irq: interrupt number
5865  *  @data: pointer to a network interface device structure
5866  **/
5867 static irqreturn_t igb_intr_msi(int irq, void *data)
5868 {
5869         struct igb_adapter *adapter = data;
5870         struct igb_q_vector *q_vector = adapter->q_vector[0];
5871         struct e1000_hw *hw = &adapter->hw;
5872         /* read ICR disables interrupts using IAM */
5873         u32 icr = rd32(E1000_ICR);
5874
5875         igb_write_itr(q_vector);
5876
5877         if (icr & E1000_ICR_DRSTA)
5878                 schedule_work(&adapter->reset_task);
5879
5880         if (icr & E1000_ICR_DOUTSYNC) {
5881                 /* HW is reporting DMA is out of sync */
5882                 adapter->stats.doosync++;
5883         }
5884
5885         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5886                 hw->mac.get_link_status = 1;
5887                 if (!test_bit(__IGB_DOWN, &adapter->state))
5888                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
5889         }
5890
5891         if (icr & E1000_ICR_TS) {
5892                 u32 tsicr = rd32(E1000_TSICR);
5893
5894                 if (tsicr & E1000_TSICR_TXTS) {
5895                         /* acknowledge the interrupt */
5896                         wr32(E1000_TSICR, E1000_TSICR_TXTS);
5897                         /* retrieve hardware timestamp */
5898                         schedule_work(&adapter->ptp_tx_work);
5899                 }
5900         }
5901
5902         napi_schedule(&q_vector->napi);
5903
5904         return IRQ_HANDLED;
5905 }
5906
5907 /**
5908  *  igb_intr - Legacy Interrupt Handler
5909  *  @irq: interrupt number
5910  *  @data: pointer to a network interface device structure
5911  **/
5912 static irqreturn_t igb_intr(int irq, void *data)
5913 {
5914         struct igb_adapter *adapter = data;
5915         struct igb_q_vector *q_vector = adapter->q_vector[0];
5916         struct e1000_hw *hw = &adapter->hw;
5917         /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked.  No
5918          * need for the IMC write
5919          */
5920         u32 icr = rd32(E1000_ICR);
5921
5922         /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
5923          * not set, then the adapter didn't send an interrupt
5924          */
5925         if (!(icr & E1000_ICR_INT_ASSERTED))
5926                 return IRQ_NONE;
5927
5928         igb_write_itr(q_vector);
5929
5930         if (icr & E1000_ICR_DRSTA)
5931                 schedule_work(&adapter->reset_task);
5932
5933         if (icr & E1000_ICR_DOUTSYNC) {
5934                 /* HW is reporting DMA is out of sync */
5935                 adapter->stats.doosync++;
5936         }
5937
5938         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5939                 hw->mac.get_link_status = 1;
5940                 /* guard against interrupt when we're going down */
5941                 if (!test_bit(__IGB_DOWN, &adapter->state))
5942                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
5943         }
5944
5945         if (icr & E1000_ICR_TS) {
5946                 u32 tsicr = rd32(E1000_TSICR);
5947
5948                 if (tsicr & E1000_TSICR_TXTS) {
5949                         /* acknowledge the interrupt */
5950                         wr32(E1000_TSICR, E1000_TSICR_TXTS);
5951                         /* retrieve hardware timestamp */
5952                         schedule_work(&adapter->ptp_tx_work);
5953                 }
5954         }
5955
5956         napi_schedule(&q_vector->napi);
5957
5958         return IRQ_HANDLED;
5959 }
5960
5961 static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
5962 {
5963         struct igb_adapter *adapter = q_vector->adapter;
5964         struct e1000_hw *hw = &adapter->hw;
5965
5966         if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
5967             (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
5968                 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
5969                         igb_set_itr(q_vector);
5970                 else
5971                         igb_update_ring_itr(q_vector);
5972         }
5973
5974         if (!test_bit(__IGB_DOWN, &adapter->state)) {
5975                 if (adapter->msix_entries)
5976                         wr32(E1000_EIMS, q_vector->eims_value);
5977                 else
5978                         igb_irq_enable(adapter);
5979         }
5980 }
5981
5982 /**
5983  *  igb_poll - NAPI Rx polling callback
5984  *  @napi: napi polling structure
5985  *  @budget: count of how many packets we should handle
5986  **/
5987 static int igb_poll(struct napi_struct *napi, int budget)
5988 {
5989         struct igb_q_vector *q_vector = container_of(napi,
5990                                                      struct igb_q_vector,
5991                                                      napi);
5992         bool clean_complete = true;
5993
5994 #ifdef CONFIG_IGB_DCA
5995         if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
5996                 igb_update_dca(q_vector);
5997 #endif
5998         if (q_vector->tx.ring)
5999                 clean_complete = igb_clean_tx_irq(q_vector);
6000
6001         if (q_vector->rx.ring)
6002                 clean_complete &= igb_clean_rx_irq(q_vector, budget);
6003
6004         /* If all work not completed, return budget and keep polling */
6005         if (!clean_complete)
6006                 return budget;
6007
6008         /* If not enough Rx work done, exit the polling mode */
6009         napi_complete(napi);
6010         igb_ring_irq_enable(q_vector);
6011
6012         return 0;
6013 }
6014
6015 /**
6016  *  igb_clean_tx_irq - Reclaim resources after transmit completes
6017  *  @q_vector: pointer to q_vector containing needed info
6018  *
6019  *  returns true if ring is completely cleaned
6020  **/
6021 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
6022 {
6023         struct igb_adapter *adapter = q_vector->adapter;
6024         struct igb_ring *tx_ring = q_vector->tx.ring;
6025         struct igb_tx_buffer *tx_buffer;
6026         union e1000_adv_tx_desc *tx_desc;
6027         unsigned int total_bytes = 0, total_packets = 0;
6028         unsigned int budget = q_vector->tx.work_limit;
6029         unsigned int i = tx_ring->next_to_clean;
6030
6031         if (test_bit(__IGB_DOWN, &adapter->state))
6032                 return true;
6033
6034         tx_buffer = &tx_ring->tx_buffer_info[i];
6035         tx_desc = IGB_TX_DESC(tx_ring, i);
6036         i -= tx_ring->count;
6037
6038         do {
6039                 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
6040
6041                 /* if next_to_watch is not set then there is no work pending */
6042                 if (!eop_desc)
6043                         break;
6044
6045                 /* prevent any other reads prior to eop_desc */
6046                 read_barrier_depends();
6047
6048                 /* if DD is not set pending work has not been completed */
6049                 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6050                         break;
6051
6052                 /* clear next_to_watch to prevent false hangs */
6053                 tx_buffer->next_to_watch = NULL;
6054
6055                 /* update the statistics for this packet */
6056                 total_bytes += tx_buffer->bytecount;
6057                 total_packets += tx_buffer->gso_segs;
6058
6059                 /* free the skb */
6060                 dev_kfree_skb_any(tx_buffer->skb);
6061
6062                 /* unmap skb header data */
6063                 dma_unmap_single(tx_ring->dev,
6064                                  dma_unmap_addr(tx_buffer, dma),
6065                                  dma_unmap_len(tx_buffer, len),
6066                                  DMA_TO_DEVICE);
6067
6068                 /* clear tx_buffer data */
6069                 tx_buffer->skb = NULL;
6070                 dma_unmap_len_set(tx_buffer, len, 0);
6071
6072                 /* clear last DMA location and unmap remaining buffers */
6073                 while (tx_desc != eop_desc) {
6074                         tx_buffer++;
6075                         tx_desc++;
6076                         i++;
6077                         if (unlikely(!i)) {
6078                                 i -= tx_ring->count;
6079                                 tx_buffer = tx_ring->tx_buffer_info;
6080                                 tx_desc = IGB_TX_DESC(tx_ring, 0);
6081                         }
6082
6083                         /* unmap any remaining paged data */
6084                         if (dma_unmap_len(tx_buffer, len)) {
6085                                 dma_unmap_page(tx_ring->dev,
6086                                                dma_unmap_addr(tx_buffer, dma),
6087                                                dma_unmap_len(tx_buffer, len),
6088                                                DMA_TO_DEVICE);
6089                                 dma_unmap_len_set(tx_buffer, len, 0);
6090                         }
6091                 }
6092
6093                 /* move us one more past the eop_desc for start of next pkt */
6094                 tx_buffer++;
6095                 tx_desc++;
6096                 i++;
6097                 if (unlikely(!i)) {
6098                         i -= tx_ring->count;
6099                         tx_buffer = tx_ring->tx_buffer_info;
6100                         tx_desc = IGB_TX_DESC(tx_ring, 0);
6101                 }
6102
6103                 /* issue prefetch for next Tx descriptor */
6104                 prefetch(tx_desc);
6105
6106                 /* update budget accounting */
6107                 budget--;
6108         } while (likely(budget));
6109
6110         netdev_tx_completed_queue(txring_txq(tx_ring),
6111                                   total_packets, total_bytes);
6112         i += tx_ring->count;
6113         tx_ring->next_to_clean = i;
6114         u64_stats_update_begin(&tx_ring->tx_syncp);
6115         tx_ring->tx_stats.bytes += total_bytes;
6116         tx_ring->tx_stats.packets += total_packets;
6117         u64_stats_update_end(&tx_ring->tx_syncp);
6118         q_vector->tx.total_bytes += total_bytes;
6119         q_vector->tx.total_packets += total_packets;
6120
6121         if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
6122                 struct e1000_hw *hw = &adapter->hw;
6123
6124                 /* Detect a transmit hang in hardware, this serializes the
6125                  * check with the clearing of time_stamp and movement of i
6126                  */
6127                 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
6128                 if (tx_buffer->next_to_watch &&
6129                     time_after(jiffies, tx_buffer->time_stamp +
6130                                (adapter->tx_timeout_factor * HZ)) &&
6131                     !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
6132
6133                         /* detected Tx unit hang */
6134                         dev_err(tx_ring->dev,
6135                                 "Detected Tx Unit Hang\n"
6136                                 "  Tx Queue             <%d>\n"
6137                                 "  TDH                  <%x>\n"
6138                                 "  TDT                  <%x>\n"
6139                                 "  next_to_use          <%x>\n"
6140                                 "  next_to_clean        <%x>\n"
6141                                 "buffer_info[next_to_clean]\n"
6142                                 "  time_stamp           <%lx>\n"
6143                                 "  next_to_watch        <%p>\n"
6144                                 "  jiffies              <%lx>\n"
6145                                 "  desc.status          <%x>\n",
6146                                 tx_ring->queue_index,
6147                                 rd32(E1000_TDH(tx_ring->reg_idx)),
6148                                 readl(tx_ring->tail),
6149                                 tx_ring->next_to_use,
6150                                 tx_ring->next_to_clean,
6151                                 tx_buffer->time_stamp,
6152                                 tx_buffer->next_to_watch,
6153                                 jiffies,
6154                                 tx_buffer->next_to_watch->wb.status);
6155                         netif_stop_subqueue(tx_ring->netdev,
6156                                             tx_ring->queue_index);
6157
6158                         /* we are about to reset, no point in enabling stuff */
6159                         return true;
6160                 }
6161         }
6162
6163 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
6164         if (unlikely(total_packets &&
6165             netif_carrier_ok(tx_ring->netdev) &&
6166             igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
6167                 /* Make sure that anybody stopping the queue after this
6168                  * sees the new next_to_clean.
6169                  */
6170                 smp_mb();
6171                 if (__netif_subqueue_stopped(tx_ring->netdev,
6172                                              tx_ring->queue_index) &&
6173                     !(test_bit(__IGB_DOWN, &adapter->state))) {
6174                         netif_wake_subqueue(tx_ring->netdev,
6175                                             tx_ring->queue_index);
6176
6177                         u64_stats_update_begin(&tx_ring->tx_syncp);
6178                         tx_ring->tx_stats.restart_queue++;
6179                         u64_stats_update_end(&tx_ring->tx_syncp);
6180                 }
6181         }
6182
6183         return !!budget;
6184 }
6185
6186 /**
6187  *  igb_reuse_rx_page - page flip buffer and store it back on the ring
6188  *  @rx_ring: rx descriptor ring to store buffers on
6189  *  @old_buff: donor buffer to have page reused
6190  *
6191  *  Synchronizes page for reuse by the adapter
6192  **/
6193 static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6194                               struct igb_rx_buffer *old_buff)
6195 {
6196         struct igb_rx_buffer *new_buff;
6197         u16 nta = rx_ring->next_to_alloc;
6198
6199         new_buff = &rx_ring->rx_buffer_info[nta];
6200
6201         /* update, and store next to alloc */
6202         nta++;
6203         rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6204
6205         /* transfer page from old buffer to new buffer */
6206         memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer));
6207
6208         /* sync the buffer for use by the device */
6209         dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6210                                          old_buff->page_offset,
6211                                          IGB_RX_BUFSZ,
6212                                          DMA_FROM_DEVICE);
6213 }
6214
6215 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6216                                   struct page *page,
6217                                   unsigned int truesize)
6218 {
6219         /* avoid re-using remote pages */
6220         if (unlikely(page_to_nid(page) != numa_node_id()))
6221                 return false;
6222
6223 #if (PAGE_SIZE < 8192)
6224         /* if we are only owner of page we can reuse it */
6225         if (unlikely(page_count(page) != 1))
6226                 return false;
6227
6228         /* flip page offset to other buffer */
6229         rx_buffer->page_offset ^= IGB_RX_BUFSZ;
6230
6231         /* since we are the only owner of the page and we need to
6232          * increment it, just set the value to 2 in order to avoid
6233          * an unnecessary locked operation
6234          */
6235         atomic_set(&page->_count, 2);
6236 #else
6237         /* move offset up to the next cache line */
6238         rx_buffer->page_offset += truesize;
6239
6240         if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6241                 return false;
6242
6243         /* bump ref count on page before it is given to the stack */
6244         get_page(page);
6245 #endif
6246
6247         return true;
6248 }
6249
6250 /**
6251  *  igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6252  *  @rx_ring: rx descriptor ring to transact packets on
6253  *  @rx_buffer: buffer containing page to add
6254  *  @rx_desc: descriptor containing length of buffer written by hardware
6255  *  @skb: sk_buff to place the data into
6256  *
6257  *  This function will add the data contained in rx_buffer->page to the skb.
6258  *  This is done either through a direct copy if the data in the buffer is
6259  *  less than the skb header size, otherwise it will just attach the page as
6260  *  a frag to the skb.
6261  *
6262  *  The function will then update the page offset if necessary and return
6263  *  true if the buffer can be reused by the adapter.
6264  **/
6265 static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6266                             struct igb_rx_buffer *rx_buffer,
6267                             union e1000_adv_rx_desc *rx_desc,
6268                             struct sk_buff *skb)
6269 {
6270         struct page *page = rx_buffer->page;
6271         unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
6272 #if (PAGE_SIZE < 8192)
6273         unsigned int truesize = IGB_RX_BUFSZ;
6274 #else
6275         unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
6276 #endif
6277
6278         if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
6279                 unsigned char *va = page_address(page) + rx_buffer->page_offset;
6280
6281                 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6282                         igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6283                         va += IGB_TS_HDR_LEN;
6284                         size -= IGB_TS_HDR_LEN;
6285                 }
6286
6287                 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6288
6289                 /* we can reuse buffer as-is, just make sure it is local */
6290                 if (likely(page_to_nid(page) == numa_node_id()))
6291                         return true;
6292
6293                 /* this page cannot be reused so discard it */
6294                 put_page(page);
6295                 return false;
6296         }
6297
6298         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
6299                         rx_buffer->page_offset, size, truesize);
6300
6301         return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6302 }
6303
6304 static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6305                                            union e1000_adv_rx_desc *rx_desc,
6306                                            struct sk_buff *skb)
6307 {
6308         struct igb_rx_buffer *rx_buffer;
6309         struct page *page;
6310
6311         rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6312
6313         page = rx_buffer->page;
6314         prefetchw(page);
6315
6316         if (likely(!skb)) {
6317                 void *page_addr = page_address(page) +
6318                                   rx_buffer->page_offset;
6319
6320                 /* prefetch first cache line of first page */
6321                 prefetch(page_addr);
6322 #if L1_CACHE_BYTES < 128
6323                 prefetch(page_addr + L1_CACHE_BYTES);
6324 #endif
6325
6326                 /* allocate a skb to store the frags */
6327                 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
6328                                                 IGB_RX_HDR_LEN);
6329                 if (unlikely(!skb)) {
6330                         rx_ring->rx_stats.alloc_failed++;
6331                         return NULL;
6332                 }
6333
6334                 /* we will be copying header into skb->data in
6335                  * pskb_may_pull so it is in our interest to prefetch
6336                  * it now to avoid a possible cache miss
6337                  */
6338                 prefetchw(skb->data);
6339         }
6340
6341         /* we are reusing so sync this buffer for CPU use */
6342         dma_sync_single_range_for_cpu(rx_ring->dev,
6343                                       rx_buffer->dma,
6344                                       rx_buffer->page_offset,
6345                                       IGB_RX_BUFSZ,
6346                                       DMA_FROM_DEVICE);
6347
6348         /* pull page into skb */
6349         if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6350                 /* hand second half of page back to the ring */
6351                 igb_reuse_rx_page(rx_ring, rx_buffer);
6352         } else {
6353                 /* we are not reusing the buffer so unmap it */
6354                 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6355                                PAGE_SIZE, DMA_FROM_DEVICE);
6356         }
6357
6358         /* clear contents of rx_buffer */
6359         rx_buffer->page = NULL;
6360
6361         return skb;
6362 }
6363
6364 static inline void igb_rx_checksum(struct igb_ring *ring,
6365                                    union e1000_adv_rx_desc *rx_desc,
6366                                    struct sk_buff *skb)
6367 {
6368         skb_checksum_none_assert(skb);
6369
6370         /* Ignore Checksum bit is set */
6371         if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
6372                 return;
6373
6374         /* Rx checksum disabled via ethtool */
6375         if (!(ring->netdev->features & NETIF_F_RXCSUM))
6376                 return;
6377
6378         /* TCP/UDP checksum error bit is set */
6379         if (igb_test_staterr(rx_desc,
6380                              E1000_RXDEXT_STATERR_TCPE |
6381                              E1000_RXDEXT_STATERR_IPE)) {
6382                 /* work around errata with sctp packets where the TCPE aka
6383                  * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6384                  * packets, (aka let the stack check the crc32c)
6385                  */
6386                 if (!((skb->len == 60) &&
6387                       test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
6388                         u64_stats_update_begin(&ring->rx_syncp);
6389                         ring->rx_stats.csum_err++;
6390                         u64_stats_update_end(&ring->rx_syncp);
6391                 }
6392                 /* let the stack verify checksum errors */
6393                 return;
6394         }
6395         /* It must be a TCP or UDP packet with a valid checksum */
6396         if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6397                                       E1000_RXD_STAT_UDPCS))
6398                 skb->ip_summed = CHECKSUM_UNNECESSARY;
6399
6400         dev_dbg(ring->dev, "cksum success: bits %08X\n",
6401                 le32_to_cpu(rx_desc->wb.upper.status_error));
6402 }
6403
6404 static inline void igb_rx_hash(struct igb_ring *ring,
6405                                union e1000_adv_rx_desc *rx_desc,
6406                                struct sk_buff *skb)
6407 {
6408         if (ring->netdev->features & NETIF_F_RXHASH)
6409                 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
6410 }
6411
6412 /**
6413  *  igb_is_non_eop - process handling of non-EOP buffers
6414  *  @rx_ring: Rx ring being processed
6415  *  @rx_desc: Rx descriptor for current buffer
6416  *  @skb: current socket buffer containing buffer in progress
6417  *
6418  *  This function updates next to clean.  If the buffer is an EOP buffer
6419  *  this function exits returning false, otherwise it will place the
6420  *  sk_buff in the next buffer to be chained and return true indicating
6421  *  that this is in fact a non-EOP buffer.
6422  **/
6423 static bool igb_is_non_eop(struct igb_ring *rx_ring,
6424                            union e1000_adv_rx_desc *rx_desc)
6425 {
6426         u32 ntc = rx_ring->next_to_clean + 1;
6427
6428         /* fetch, update, and store next to clean */
6429         ntc = (ntc < rx_ring->count) ? ntc : 0;
6430         rx_ring->next_to_clean = ntc;
6431
6432         prefetch(IGB_RX_DESC(rx_ring, ntc));
6433
6434         if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6435                 return false;
6436
6437         return true;
6438 }
6439
6440 /**
6441  *  igb_get_headlen - determine size of header for LRO/GRO
6442  *  @data: pointer to the start of the headers
6443  *  @max_len: total length of section to find headers in
6444  *
6445  *  This function is meant to determine the length of headers that will
6446  *  be recognized by hardware for LRO, and GRO offloads.  The main
6447  *  motivation of doing this is to only perform one pull for IPv4 TCP
6448  *  packets so that we can do basic things like calculating the gso_size
6449  *  based on the average data per packet.
6450  **/
6451 static unsigned int igb_get_headlen(unsigned char *data,
6452                                     unsigned int max_len)
6453 {
6454         union {
6455                 unsigned char *network;
6456                 /* l2 headers */
6457                 struct ethhdr *eth;
6458                 struct vlan_hdr *vlan;
6459                 /* l3 headers */
6460                 struct iphdr *ipv4;
6461                 struct ipv6hdr *ipv6;
6462         } hdr;
6463         __be16 protocol;
6464         u8 nexthdr = 0; /* default to not TCP */
6465         u8 hlen;
6466
6467         /* this should never happen, but better safe than sorry */
6468         if (max_len < ETH_HLEN)
6469                 return max_len;
6470
6471         /* initialize network frame pointer */
6472         hdr.network = data;
6473
6474         /* set first protocol and move network header forward */
6475         protocol = hdr.eth->h_proto;
6476         hdr.network += ETH_HLEN;
6477
6478         /* handle any vlan tag if present */
6479         if (protocol == __constant_htons(ETH_P_8021Q)) {
6480                 if ((hdr.network - data) > (max_len - VLAN_HLEN))
6481                         return max_len;
6482
6483                 protocol = hdr.vlan->h_vlan_encapsulated_proto;
6484                 hdr.network += VLAN_HLEN;
6485         }
6486
6487         /* handle L3 protocols */
6488         if (protocol == __constant_htons(ETH_P_IP)) {
6489                 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
6490                         return max_len;
6491
6492                 /* access ihl as a u8 to avoid unaligned access on ia64 */
6493                 hlen = (hdr.network[0] & 0x0F) << 2;
6494
6495                 /* verify hlen meets minimum size requirements */
6496                 if (hlen < sizeof(struct iphdr))
6497                         return hdr.network - data;
6498
6499                 /* record next protocol if header is present */
6500                 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
6501                         nexthdr = hdr.ipv4->protocol;
6502         } else if (protocol == __constant_htons(ETH_P_IPV6)) {
6503                 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
6504                         return max_len;
6505
6506                 /* record next protocol */
6507                 nexthdr = hdr.ipv6->nexthdr;
6508                 hlen = sizeof(struct ipv6hdr);
6509         } else {
6510                 return hdr.network - data;
6511         }
6512
6513         /* relocate pointer to start of L4 header */
6514         hdr.network += hlen;
6515
6516         /* finally sort out TCP */
6517         if (nexthdr == IPPROTO_TCP) {
6518                 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
6519                         return max_len;
6520
6521                 /* access doff as a u8 to avoid unaligned access on ia64 */
6522                 hlen = (hdr.network[12] & 0xF0) >> 2;
6523
6524                 /* verify hlen meets minimum size requirements */
6525                 if (hlen < sizeof(struct tcphdr))
6526                         return hdr.network - data;
6527
6528                 hdr.network += hlen;
6529         } else if (nexthdr == IPPROTO_UDP) {
6530                 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
6531                         return max_len;
6532
6533                 hdr.network += sizeof(struct udphdr);
6534         }
6535
6536         /* If everything has gone correctly hdr.network should be the
6537          * data section of the packet and will be the end of the header.
6538          * If not then it probably represents the end of the last recognized
6539          * header.
6540          */
6541         if ((hdr.network - data) < max_len)
6542                 return hdr.network - data;
6543         else
6544                 return max_len;
6545 }
6546
6547 /**
6548  *  igb_pull_tail - igb specific version of skb_pull_tail
6549  *  @rx_ring: rx descriptor ring packet is being transacted on
6550  *  @rx_desc: pointer to the EOP Rx descriptor
6551  *  @skb: pointer to current skb being adjusted
6552  *
6553  *  This function is an igb specific version of __pskb_pull_tail.  The
6554  *  main difference between this version and the original function is that
6555  *  this function can make several assumptions about the state of things
6556  *  that allow for significant optimizations versus the standard function.
6557  *  As a result we can do things like drop a frag and maintain an accurate
6558  *  truesize for the skb.
6559  */
6560 static void igb_pull_tail(struct igb_ring *rx_ring,
6561                           union e1000_adv_rx_desc *rx_desc,
6562                           struct sk_buff *skb)
6563 {
6564         struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6565         unsigned char *va;
6566         unsigned int pull_len;
6567
6568         /* it is valid to use page_address instead of kmap since we are
6569          * working with pages allocated out of the lomem pool per
6570          * alloc_page(GFP_ATOMIC)
6571          */
6572         va = skb_frag_address(frag);
6573
6574         if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6575                 /* retrieve timestamp from buffer */
6576                 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6577
6578                 /* update pointers to remove timestamp header */
6579                 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6580                 frag->page_offset += IGB_TS_HDR_LEN;
6581                 skb->data_len -= IGB_TS_HDR_LEN;
6582                 skb->len -= IGB_TS_HDR_LEN;
6583
6584                 /* move va to start of packet data */
6585                 va += IGB_TS_HDR_LEN;
6586         }
6587
6588         /* we need the header to contain the greater of either ETH_HLEN or
6589          * 60 bytes if the skb->len is less than 60 for skb_pad.
6590          */
6591         pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN);
6592
6593         /* align pull length to size of long to optimize memcpy performance */
6594         skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6595
6596         /* update all of the pointers */
6597         skb_frag_size_sub(frag, pull_len);
6598         frag->page_offset += pull_len;
6599         skb->data_len -= pull_len;
6600         skb->tail += pull_len;
6601 }
6602
6603 /**
6604  *  igb_cleanup_headers - Correct corrupted or empty headers
6605  *  @rx_ring: rx descriptor ring packet is being transacted on
6606  *  @rx_desc: pointer to the EOP Rx descriptor
6607  *  @skb: pointer to current skb being fixed
6608  *
6609  *  Address the case where we are pulling data in on pages only
6610  *  and as such no data is present in the skb header.
6611  *
6612  *  In addition if skb is not at least 60 bytes we need to pad it so that
6613  *  it is large enough to qualify as a valid Ethernet frame.
6614  *
6615  *  Returns true if an error was encountered and skb was freed.
6616  **/
6617 static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6618                                 union e1000_adv_rx_desc *rx_desc,
6619                                 struct sk_buff *skb)
6620 {
6621         if (unlikely((igb_test_staterr(rx_desc,
6622                                        E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6623                 struct net_device *netdev = rx_ring->netdev;
6624                 if (!(netdev->features & NETIF_F_RXALL)) {
6625                         dev_kfree_skb_any(skb);
6626                         return true;
6627                 }
6628         }
6629
6630         /* place header in linear portion of buffer */
6631         if (skb_is_nonlinear(skb))
6632                 igb_pull_tail(rx_ring, rx_desc, skb);
6633
6634         /* if skb_pad returns an error the skb was freed */
6635         if (unlikely(skb->len < 60)) {
6636                 int pad_len = 60 - skb->len;
6637
6638                 if (skb_pad(skb, pad_len))
6639                         return true;
6640                 __skb_put(skb, pad_len);
6641         }
6642
6643         return false;
6644 }
6645
6646 /**
6647  *  igb_process_skb_fields - Populate skb header fields from Rx descriptor
6648  *  @rx_ring: rx descriptor ring packet is being transacted on
6649  *  @rx_desc: pointer to the EOP Rx descriptor
6650  *  @skb: pointer to current skb being populated
6651  *
6652  *  This function checks the ring, descriptor, and packet information in
6653  *  order to populate the hash, checksum, VLAN, timestamp, protocol, and
6654  *  other fields within the skb.
6655  **/
6656 static void igb_process_skb_fields(struct igb_ring *rx_ring,
6657                                    union e1000_adv_rx_desc *rx_desc,
6658                                    struct sk_buff *skb)
6659 {
6660         struct net_device *dev = rx_ring->netdev;
6661
6662         igb_rx_hash(rx_ring, rx_desc, skb);
6663
6664         igb_rx_checksum(rx_ring, rx_desc, skb);
6665
6666         igb_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
6667
6668         if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
6669             igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6670                 u16 vid;
6671                 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6672                     test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6673                         vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6674                 else
6675                         vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6676
6677                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
6678         }
6679
6680         skb_record_rx_queue(skb, rx_ring->queue_index);
6681
6682         skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6683 }
6684
6685 static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
6686 {
6687         struct igb_ring *rx_ring = q_vector->rx.ring;
6688         struct sk_buff *skb = rx_ring->skb;
6689         unsigned int total_bytes = 0, total_packets = 0;
6690         u16 cleaned_count = igb_desc_unused(rx_ring);
6691
6692         do {
6693                 union e1000_adv_rx_desc *rx_desc;
6694
6695                 /* return some buffers to hardware, one at a time is too slow */
6696                 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6697                         igb_alloc_rx_buffers(rx_ring, cleaned_count);
6698                         cleaned_count = 0;
6699                 }
6700
6701                 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
6702
6703                 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD))
6704                         break;
6705
6706                 /* This memory barrier is needed to keep us from reading
6707                  * any other fields out of the rx_desc until we know the
6708                  * RXD_STAT_DD bit is set
6709                  */
6710                 rmb();
6711
6712                 /* retrieve a buffer from the ring */
6713                 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
6714
6715                 /* exit if we failed to retrieve a buffer */
6716                 if (!skb)
6717                         break;
6718
6719                 cleaned_count++;
6720
6721                 /* fetch next buffer in frame if non-eop */
6722                 if (igb_is_non_eop(rx_ring, rx_desc))
6723                         continue;
6724
6725                 /* verify the packet layout is correct */
6726                 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6727                         skb = NULL;
6728                         continue;
6729                 }
6730
6731                 /* probably a little skewed due to removing CRC */
6732                 total_bytes += skb->len;
6733
6734                 /* populate checksum, timestamp, VLAN, and protocol */
6735                 igb_process_skb_fields(rx_ring, rx_desc, skb);
6736
6737                 napi_gro_receive(&q_vector->napi, skb);
6738
6739                 /* reset skb pointer */
6740                 skb = NULL;
6741
6742                 /* update budget accounting */
6743                 total_packets++;
6744         } while (likely(total_packets < budget));
6745
6746         /* place incomplete frames back on ring for completion */
6747         rx_ring->skb = skb;
6748
6749         u64_stats_update_begin(&rx_ring->rx_syncp);
6750         rx_ring->rx_stats.packets += total_packets;
6751         rx_ring->rx_stats.bytes += total_bytes;
6752         u64_stats_update_end(&rx_ring->rx_syncp);
6753         q_vector->rx.total_packets += total_packets;
6754         q_vector->rx.total_bytes += total_bytes;
6755
6756         if (cleaned_count)
6757                 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6758
6759         return (total_packets < budget);
6760 }
6761
6762 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
6763                                   struct igb_rx_buffer *bi)
6764 {
6765         struct page *page = bi->page;
6766         dma_addr_t dma;
6767
6768         /* since we are recycling buffers we should seldom need to alloc */
6769         if (likely(page))
6770                 return true;
6771
6772         /* alloc new page for storage */
6773         page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL);
6774         if (unlikely(!page)) {
6775                 rx_ring->rx_stats.alloc_failed++;
6776                 return false;
6777         }
6778
6779         /* map page for use */
6780         dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
6781
6782         /* if mapping failed free memory back to system since
6783          * there isn't much point in holding memory we can't use
6784          */
6785         if (dma_mapping_error(rx_ring->dev, dma)) {
6786                 __free_page(page);
6787
6788                 rx_ring->rx_stats.alloc_failed++;
6789                 return false;
6790         }
6791
6792         bi->dma = dma;
6793         bi->page = page;
6794         bi->page_offset = 0;
6795
6796         return true;
6797 }
6798
6799 /**
6800  *  igb_alloc_rx_buffers - Replace used receive buffers; packet split
6801  *  @adapter: address of board private structure
6802  **/
6803 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
6804 {
6805         union e1000_adv_rx_desc *rx_desc;
6806         struct igb_rx_buffer *bi;
6807         u16 i = rx_ring->next_to_use;
6808
6809         /* nothing to do */
6810         if (!cleaned_count)
6811                 return;
6812
6813         rx_desc = IGB_RX_DESC(rx_ring, i);
6814         bi = &rx_ring->rx_buffer_info[i];
6815         i -= rx_ring->count;
6816
6817         do {
6818                 if (!igb_alloc_mapped_page(rx_ring, bi))
6819                         break;
6820
6821                 /* Refresh the desc even if buffer_addrs didn't change
6822                  * because each write-back erases this info.
6823                  */
6824                 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
6825
6826                 rx_desc++;
6827                 bi++;
6828                 i++;
6829                 if (unlikely(!i)) {
6830                         rx_desc = IGB_RX_DESC(rx_ring, 0);
6831                         bi = rx_ring->rx_buffer_info;
6832                         i -= rx_ring->count;
6833                 }
6834
6835                 /* clear the hdr_addr for the next_to_use descriptor */
6836                 rx_desc->read.hdr_addr = 0;
6837
6838                 cleaned_count--;
6839         } while (cleaned_count);
6840
6841         i += rx_ring->count;
6842
6843         if (rx_ring->next_to_use != i) {
6844                 /* record the next descriptor to use */
6845                 rx_ring->next_to_use = i;
6846
6847                 /* update next to alloc since we have filled the ring */
6848                 rx_ring->next_to_alloc = i;
6849
6850                 /* Force memory writes to complete before letting h/w
6851                  * know there are new descriptors to fetch.  (Only
6852                  * applicable for weak-ordered memory model archs,
6853                  * such as IA-64).
6854                  */
6855                 wmb();
6856                 writel(i, rx_ring->tail);
6857         }
6858 }
6859
6860 /**
6861  * igb_mii_ioctl -
6862  * @netdev:
6863  * @ifreq:
6864  * @cmd:
6865  **/
6866 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6867 {
6868         struct igb_adapter *adapter = netdev_priv(netdev);
6869         struct mii_ioctl_data *data = if_mii(ifr);
6870
6871         if (adapter->hw.phy.media_type != e1000_media_type_copper)
6872                 return -EOPNOTSUPP;
6873
6874         switch (cmd) {
6875         case SIOCGMIIPHY:
6876                 data->phy_id = adapter->hw.phy.addr;
6877                 break;
6878         case SIOCGMIIREG:
6879                 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
6880                                      &data->val_out))
6881                         return -EIO;
6882                 break;
6883         case SIOCSMIIREG:
6884         default:
6885                 return -EOPNOTSUPP;
6886         }
6887         return 0;
6888 }
6889
6890 /**
6891  * igb_ioctl -
6892  * @netdev:
6893  * @ifreq:
6894  * @cmd:
6895  **/
6896 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6897 {
6898         switch (cmd) {
6899         case SIOCGMIIPHY:
6900         case SIOCGMIIREG:
6901         case SIOCSMIIREG:
6902                 return igb_mii_ioctl(netdev, ifr, cmd);
6903         case SIOCSHWTSTAMP:
6904                 return igb_ptp_hwtstamp_ioctl(netdev, ifr, cmd);
6905         default:
6906                 return -EOPNOTSUPP;
6907         }
6908 }
6909
6910 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6911 {
6912         struct igb_adapter *adapter = hw->back;
6913
6914         if (pcie_capability_read_word(adapter->pdev, reg, value))
6915                 return -E1000_ERR_CONFIG;
6916
6917         return 0;
6918 }
6919
6920 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6921 {
6922         struct igb_adapter *adapter = hw->back;
6923
6924         if (pcie_capability_write_word(adapter->pdev, reg, *value))
6925                 return -E1000_ERR_CONFIG;
6926
6927         return 0;
6928 }
6929
6930 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
6931 {
6932         struct igb_adapter *adapter = netdev_priv(netdev);
6933         struct e1000_hw *hw = &adapter->hw;
6934         u32 ctrl, rctl;
6935         bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
6936
6937         if (enable) {
6938                 /* enable VLAN tag insert/strip */
6939                 ctrl = rd32(E1000_CTRL);
6940                 ctrl |= E1000_CTRL_VME;
6941                 wr32(E1000_CTRL, ctrl);
6942
6943                 /* Disable CFI check */
6944                 rctl = rd32(E1000_RCTL);
6945                 rctl &= ~E1000_RCTL_CFIEN;
6946                 wr32(E1000_RCTL, rctl);
6947         } else {
6948                 /* disable VLAN tag insert/strip */
6949                 ctrl = rd32(E1000_CTRL);
6950                 ctrl &= ~E1000_CTRL_VME;
6951                 wr32(E1000_CTRL, ctrl);
6952         }
6953
6954         igb_rlpml_set(adapter);
6955 }
6956
6957 static int igb_vlan_rx_add_vid(struct net_device *netdev,
6958                                __be16 proto, u16 vid)
6959 {
6960         struct igb_adapter *adapter = netdev_priv(netdev);
6961         struct e1000_hw *hw = &adapter->hw;
6962         int pf_id = adapter->vfs_allocated_count;
6963
6964         /* attempt to add filter to vlvf array */
6965         igb_vlvf_set(adapter, vid, true, pf_id);
6966
6967         /* add the filter since PF can receive vlans w/o entry in vlvf */
6968         igb_vfta_set(hw, vid, true);
6969
6970         set_bit(vid, adapter->active_vlans);
6971
6972         return 0;
6973 }
6974
6975 static int igb_vlan_rx_kill_vid(struct net_device *netdev,
6976                                 __be16 proto, u16 vid)
6977 {
6978         struct igb_adapter *adapter = netdev_priv(netdev);
6979         struct e1000_hw *hw = &adapter->hw;
6980         int pf_id = adapter->vfs_allocated_count;
6981         s32 err;
6982
6983         /* remove vlan from VLVF table array */
6984         err = igb_vlvf_set(adapter, vid, false, pf_id);
6985
6986         /* if vid was not present in VLVF just remove it from table */
6987         if (err)
6988                 igb_vfta_set(hw, vid, false);
6989
6990         clear_bit(vid, adapter->active_vlans);
6991
6992         return 0;
6993 }
6994
6995 static void igb_restore_vlan(struct igb_adapter *adapter)
6996 {
6997         u16 vid;
6998
6999         igb_vlan_mode(adapter->netdev, adapter->netdev->features);
7000
7001         for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
7002                 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
7003 }
7004
7005 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
7006 {
7007         struct pci_dev *pdev = adapter->pdev;
7008         struct e1000_mac_info *mac = &adapter->hw.mac;
7009
7010         mac->autoneg = 0;
7011
7012         /* Make sure dplx is at most 1 bit and lsb of speed is not set
7013          * for the switch() below to work
7014          */
7015         if ((spd & 1) || (dplx & ~1))
7016                 goto err_inval;
7017
7018         /* Fiber NIC's only allow 1000 gbps Full duplex
7019          * and 100Mbps Full duplex for 100baseFx sfp
7020          */
7021         if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7022                 switch (spd + dplx) {
7023                 case SPEED_10 + DUPLEX_HALF:
7024                 case SPEED_10 + DUPLEX_FULL:
7025                 case SPEED_100 + DUPLEX_HALF:
7026                         goto err_inval;
7027                 default:
7028                         break;
7029                 }
7030         }
7031
7032         switch (spd + dplx) {
7033         case SPEED_10 + DUPLEX_HALF:
7034                 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7035                 break;
7036         case SPEED_10 + DUPLEX_FULL:
7037                 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7038                 break;
7039         case SPEED_100 + DUPLEX_HALF:
7040                 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7041                 break;
7042         case SPEED_100 + DUPLEX_FULL:
7043                 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7044                 break;
7045         case SPEED_1000 + DUPLEX_FULL:
7046                 mac->autoneg = 1;
7047                 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7048                 break;
7049         case SPEED_1000 + DUPLEX_HALF: /* not supported */
7050         default:
7051                 goto err_inval;
7052         }
7053
7054         /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7055         adapter->hw.phy.mdix = AUTO_ALL_MODES;
7056
7057         return 0;
7058
7059 err_inval:
7060         dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7061         return -EINVAL;
7062 }
7063
7064 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7065                           bool runtime)
7066 {
7067         struct net_device *netdev = pci_get_drvdata(pdev);
7068         struct igb_adapter *adapter = netdev_priv(netdev);
7069         struct e1000_hw *hw = &adapter->hw;
7070         u32 ctrl, rctl, status;
7071         u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
7072 #ifdef CONFIG_PM
7073         int retval = 0;
7074 #endif
7075
7076         netif_device_detach(netdev);
7077
7078         if (netif_running(netdev))
7079                 __igb_close(netdev, true);
7080
7081         igb_clear_interrupt_scheme(adapter);
7082
7083 #ifdef CONFIG_PM
7084         retval = pci_save_state(pdev);
7085         if (retval)
7086                 return retval;
7087 #endif
7088
7089         status = rd32(E1000_STATUS);
7090         if (status & E1000_STATUS_LU)
7091                 wufc &= ~E1000_WUFC_LNKC;
7092
7093         if (wufc) {
7094                 igb_setup_rctl(adapter);
7095                 igb_set_rx_mode(netdev);
7096
7097                 /* turn on all-multi mode if wake on multicast is enabled */
7098                 if (wufc & E1000_WUFC_MC) {
7099                         rctl = rd32(E1000_RCTL);
7100                         rctl |= E1000_RCTL_MPE;
7101                         wr32(E1000_RCTL, rctl);
7102                 }
7103
7104                 ctrl = rd32(E1000_CTRL);
7105                 /* advertise wake from D3Cold */
7106                 #define E1000_CTRL_ADVD3WUC 0x00100000
7107                 /* phy power management enable */
7108                 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7109                 ctrl |= E1000_CTRL_ADVD3WUC;
7110                 wr32(E1000_CTRL, ctrl);
7111
7112                 /* Allow time for pending master requests to run */
7113                 igb_disable_pcie_master(hw);
7114
7115                 wr32(E1000_WUC, E1000_WUC_PME_EN);
7116                 wr32(E1000_WUFC, wufc);
7117         } else {
7118                 wr32(E1000_WUC, 0);
7119                 wr32(E1000_WUFC, 0);
7120         }
7121
7122         *enable_wake = wufc || adapter->en_mng_pt;
7123         if (!*enable_wake)
7124                 igb_power_down_link(adapter);
7125         else
7126                 igb_power_up_link(adapter);
7127
7128         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
7129          * would have already happened in close and is redundant.
7130          */
7131         igb_release_hw_control(adapter);
7132
7133         pci_disable_device(pdev);
7134
7135         return 0;
7136 }
7137
7138 #ifdef CONFIG_PM
7139 #ifdef CONFIG_PM_SLEEP
7140 static int igb_suspend(struct device *dev)
7141 {
7142         int retval;
7143         bool wake;
7144         struct pci_dev *pdev = to_pci_dev(dev);
7145
7146         retval = __igb_shutdown(pdev, &wake, 0);
7147         if (retval)
7148                 return retval;
7149
7150         if (wake) {
7151                 pci_prepare_to_sleep(pdev);
7152         } else {
7153                 pci_wake_from_d3(pdev, false);
7154                 pci_set_power_state(pdev, PCI_D3hot);
7155         }
7156
7157         return 0;
7158 }
7159 #endif /* CONFIG_PM_SLEEP */
7160
7161 static int igb_resume(struct device *dev)
7162 {
7163         struct pci_dev *pdev = to_pci_dev(dev);
7164         struct net_device *netdev = pci_get_drvdata(pdev);
7165         struct igb_adapter *adapter = netdev_priv(netdev);
7166         struct e1000_hw *hw = &adapter->hw;
7167         u32 err;
7168
7169         pci_set_power_state(pdev, PCI_D0);
7170         pci_restore_state(pdev);
7171         pci_save_state(pdev);
7172
7173         err = pci_enable_device_mem(pdev);
7174         if (err) {
7175                 dev_err(&pdev->dev,
7176                         "igb: Cannot enable PCI device from suspend\n");
7177                 return err;
7178         }
7179         pci_set_master(pdev);
7180
7181         pci_enable_wake(pdev, PCI_D3hot, 0);
7182         pci_enable_wake(pdev, PCI_D3cold, 0);
7183
7184         if (igb_init_interrupt_scheme(adapter, true)) {
7185                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7186                 return -ENOMEM;
7187         }
7188
7189         igb_reset(adapter);
7190
7191         /* let the f/w know that the h/w is now under the control of the
7192          * driver.
7193          */
7194         igb_get_hw_control(adapter);
7195
7196         wr32(E1000_WUS, ~0);
7197
7198         if (netdev->flags & IFF_UP) {
7199                 rtnl_lock();
7200                 err = __igb_open(netdev, true);
7201                 rtnl_unlock();
7202                 if (err)
7203                         return err;
7204         }
7205
7206         netif_device_attach(netdev);
7207         return 0;
7208 }
7209
7210 #ifdef CONFIG_PM_RUNTIME
7211 static int igb_runtime_idle(struct device *dev)
7212 {
7213         struct pci_dev *pdev = to_pci_dev(dev);
7214         struct net_device *netdev = pci_get_drvdata(pdev);
7215         struct igb_adapter *adapter = netdev_priv(netdev);
7216
7217         if (!igb_has_link(adapter))
7218                 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7219
7220         return -EBUSY;
7221 }
7222
7223 static int igb_runtime_suspend(struct device *dev)
7224 {
7225         struct pci_dev *pdev = to_pci_dev(dev);
7226         int retval;
7227         bool wake;
7228
7229         retval = __igb_shutdown(pdev, &wake, 1);
7230         if (retval)
7231                 return retval;
7232
7233         if (wake) {
7234                 pci_prepare_to_sleep(pdev);
7235         } else {
7236                 pci_wake_from_d3(pdev, false);
7237                 pci_set_power_state(pdev, PCI_D3hot);
7238         }
7239
7240         return 0;
7241 }
7242
7243 static int igb_runtime_resume(struct device *dev)
7244 {
7245         return igb_resume(dev);
7246 }
7247 #endif /* CONFIG_PM_RUNTIME */
7248 #endif
7249
7250 static void igb_shutdown(struct pci_dev *pdev)
7251 {
7252         bool wake;
7253
7254         __igb_shutdown(pdev, &wake, 0);
7255
7256         if (system_state == SYSTEM_POWER_OFF) {
7257                 pci_wake_from_d3(pdev, wake);
7258                 pci_set_power_state(pdev, PCI_D3hot);
7259         }
7260 }
7261
7262 #ifdef CONFIG_PCI_IOV
7263 static int igb_sriov_reinit(struct pci_dev *dev)
7264 {
7265         struct net_device *netdev = pci_get_drvdata(dev);
7266         struct igb_adapter *adapter = netdev_priv(netdev);
7267         struct pci_dev *pdev = adapter->pdev;
7268
7269         rtnl_lock();
7270
7271         if (netif_running(netdev))
7272                 igb_close(netdev);
7273
7274         igb_clear_interrupt_scheme(adapter);
7275
7276         igb_init_queue_configuration(adapter);
7277
7278         if (igb_init_interrupt_scheme(adapter, true)) {
7279                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7280                 return -ENOMEM;
7281         }
7282
7283         if (netif_running(netdev))
7284                 igb_open(netdev);
7285
7286         rtnl_unlock();
7287
7288         return 0;
7289 }
7290
7291 static int igb_pci_disable_sriov(struct pci_dev *dev)
7292 {
7293         int err = igb_disable_sriov(dev);
7294
7295         if (!err)
7296                 err = igb_sriov_reinit(dev);
7297
7298         return err;
7299 }
7300
7301 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7302 {
7303         int err = igb_enable_sriov(dev, num_vfs);
7304
7305         if (err)
7306                 goto out;
7307
7308         err = igb_sriov_reinit(dev);
7309         if (!err)
7310                 return num_vfs;
7311
7312 out:
7313         return err;
7314 }
7315
7316 #endif
7317 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7318 {
7319 #ifdef CONFIG_PCI_IOV
7320         if (num_vfs == 0)
7321                 return igb_pci_disable_sriov(dev);
7322         else
7323                 return igb_pci_enable_sriov(dev, num_vfs);
7324 #endif
7325         return 0;
7326 }
7327
7328 #ifdef CONFIG_NET_POLL_CONTROLLER
7329 /* Polling 'interrupt' - used by things like netconsole to send skbs
7330  * without having to re-enable interrupts. It's not called while
7331  * the interrupt routine is executing.
7332  */
7333 static void igb_netpoll(struct net_device *netdev)
7334 {
7335         struct igb_adapter *adapter = netdev_priv(netdev);
7336         struct e1000_hw *hw = &adapter->hw;
7337         struct igb_q_vector *q_vector;
7338         int i;
7339
7340         for (i = 0; i < adapter->num_q_vectors; i++) {
7341                 q_vector = adapter->q_vector[i];
7342                 if (adapter->msix_entries)
7343                         wr32(E1000_EIMC, q_vector->eims_value);
7344                 else
7345                         igb_irq_disable(adapter);
7346                 napi_schedule(&q_vector->napi);
7347         }
7348 }
7349 #endif /* CONFIG_NET_POLL_CONTROLLER */
7350
7351 /**
7352  *  igb_io_error_detected - called when PCI error is detected
7353  *  @pdev: Pointer to PCI device
7354  *  @state: The current pci connection state
7355  *
7356  *  This function is called after a PCI bus error affecting
7357  *  this device has been detected.
7358  **/
7359 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7360                                               pci_channel_state_t state)
7361 {
7362         struct net_device *netdev = pci_get_drvdata(pdev);
7363         struct igb_adapter *adapter = netdev_priv(netdev);
7364
7365         netif_device_detach(netdev);
7366
7367         if (state == pci_channel_io_perm_failure)
7368                 return PCI_ERS_RESULT_DISCONNECT;
7369
7370         if (netif_running(netdev))
7371                 igb_down(adapter);
7372         pci_disable_device(pdev);
7373
7374         /* Request a slot slot reset. */
7375         return PCI_ERS_RESULT_NEED_RESET;
7376 }
7377
7378 /**
7379  *  igb_io_slot_reset - called after the pci bus has been reset.
7380  *  @pdev: Pointer to PCI device
7381  *
7382  *  Restart the card from scratch, as if from a cold-boot. Implementation
7383  *  resembles the first-half of the igb_resume routine.
7384  **/
7385 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7386 {
7387         struct net_device *netdev = pci_get_drvdata(pdev);
7388         struct igb_adapter *adapter = netdev_priv(netdev);
7389         struct e1000_hw *hw = &adapter->hw;
7390         pci_ers_result_t result;
7391         int err;
7392
7393         if (pci_enable_device_mem(pdev)) {
7394                 dev_err(&pdev->dev,
7395                         "Cannot re-enable PCI device after reset.\n");
7396                 result = PCI_ERS_RESULT_DISCONNECT;
7397         } else {
7398                 pci_set_master(pdev);
7399                 pci_restore_state(pdev);
7400                 pci_save_state(pdev);
7401
7402                 pci_enable_wake(pdev, PCI_D3hot, 0);
7403                 pci_enable_wake(pdev, PCI_D3cold, 0);
7404
7405                 igb_reset(adapter);
7406                 wr32(E1000_WUS, ~0);
7407                 result = PCI_ERS_RESULT_RECOVERED;
7408         }
7409
7410         err = pci_cleanup_aer_uncorrect_error_status(pdev);
7411         if (err) {
7412                 dev_err(&pdev->dev,
7413                         "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7414                         err);
7415                 /* non-fatal, continue */
7416         }
7417
7418         return result;
7419 }
7420
7421 /**
7422  *  igb_io_resume - called when traffic can start flowing again.
7423  *  @pdev: Pointer to PCI device
7424  *
7425  *  This callback is called when the error recovery driver tells us that
7426  *  its OK to resume normal operation. Implementation resembles the
7427  *  second-half of the igb_resume routine.
7428  */
7429 static void igb_io_resume(struct pci_dev *pdev)
7430 {
7431         struct net_device *netdev = pci_get_drvdata(pdev);
7432         struct igb_adapter *adapter = netdev_priv(netdev);
7433
7434         if (netif_running(netdev)) {
7435                 if (igb_up(adapter)) {
7436                         dev_err(&pdev->dev, "igb_up failed after reset\n");
7437                         return;
7438                 }
7439         }
7440
7441         netif_device_attach(netdev);
7442
7443         /* let the f/w know that the h/w is now under the control of the
7444          * driver.
7445          */
7446         igb_get_hw_control(adapter);
7447 }
7448
7449 static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
7450                              u8 qsel)
7451 {
7452         u32 rar_low, rar_high;
7453         struct e1000_hw *hw = &adapter->hw;
7454
7455         /* HW expects these in little endian so we reverse the byte order
7456          * from network order (big endian) to little endian
7457          */
7458         rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
7459                    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
7460         rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7461
7462         /* Indicate to hardware the Address is Valid. */
7463         rar_high |= E1000_RAH_AV;
7464
7465         if (hw->mac.type == e1000_82575)
7466                 rar_high |= E1000_RAH_POOL_1 * qsel;
7467         else
7468                 rar_high |= E1000_RAH_POOL_1 << qsel;
7469
7470         wr32(E1000_RAL(index), rar_low);
7471         wrfl();
7472         wr32(E1000_RAH(index), rar_high);
7473         wrfl();
7474 }
7475
7476 static int igb_set_vf_mac(struct igb_adapter *adapter,
7477                           int vf, unsigned char *mac_addr)
7478 {
7479         struct e1000_hw *hw = &adapter->hw;
7480         /* VF MAC addresses start at end of receive addresses and moves
7481          * towards the first, as a result a collision should not be possible
7482          */
7483         int rar_entry = hw->mac.rar_entry_count - (vf + 1);
7484
7485         memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
7486
7487         igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
7488
7489         return 0;
7490 }
7491
7492 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7493 {
7494         struct igb_adapter *adapter = netdev_priv(netdev);
7495         if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7496                 return -EINVAL;
7497         adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7498         dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
7499         dev_info(&adapter->pdev->dev,
7500                  "Reload the VF driver to make this change effective.");
7501         if (test_bit(__IGB_DOWN, &adapter->state)) {
7502                 dev_warn(&adapter->pdev->dev,
7503                          "The VF MAC address has been set, but the PF device is not up.\n");
7504                 dev_warn(&adapter->pdev->dev,
7505                          "Bring the PF device up before attempting to use the VF device.\n");
7506         }
7507         return igb_set_vf_mac(adapter, vf, mac);
7508 }
7509
7510 static int igb_link_mbps(int internal_link_speed)
7511 {
7512         switch (internal_link_speed) {
7513         case SPEED_100:
7514                 return 100;
7515         case SPEED_1000:
7516                 return 1000;
7517         default:
7518                 return 0;
7519         }
7520 }
7521
7522 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7523                                   int link_speed)
7524 {
7525         int rf_dec, rf_int;
7526         u32 bcnrc_val;
7527
7528         if (tx_rate != 0) {
7529                 /* Calculate the rate factor values to set */
7530                 rf_int = link_speed / tx_rate;
7531                 rf_dec = (link_speed - (rf_int * tx_rate));
7532                 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) /
7533                          tx_rate;
7534
7535                 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
7536                 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7537                               E1000_RTTBCNRC_RF_INT_MASK);
7538                 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7539         } else {
7540                 bcnrc_val = 0;
7541         }
7542
7543         wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
7544         /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
7545          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7546          */
7547         wr32(E1000_RTTBCNRM, 0x14);
7548         wr32(E1000_RTTBCNRC, bcnrc_val);
7549 }
7550
7551 static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7552 {
7553         int actual_link_speed, i;
7554         bool reset_rate = false;
7555
7556         /* VF TX rate limit was not set or not supported */
7557         if ((adapter->vf_rate_link_speed == 0) ||
7558             (adapter->hw.mac.type != e1000_82576))
7559                 return;
7560
7561         actual_link_speed = igb_link_mbps(adapter->link_speed);
7562         if (actual_link_speed != adapter->vf_rate_link_speed) {
7563                 reset_rate = true;
7564                 adapter->vf_rate_link_speed = 0;
7565                 dev_info(&adapter->pdev->dev,
7566                          "Link speed has been changed. VF Transmit rate is disabled\n");
7567         }
7568
7569         for (i = 0; i < adapter->vfs_allocated_count; i++) {
7570                 if (reset_rate)
7571                         adapter->vf_data[i].tx_rate = 0;
7572
7573                 igb_set_vf_rate_limit(&adapter->hw, i,
7574                                       adapter->vf_data[i].tx_rate,
7575                                       actual_link_speed);
7576         }
7577 }
7578
7579 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
7580 {
7581         struct igb_adapter *adapter = netdev_priv(netdev);
7582         struct e1000_hw *hw = &adapter->hw;
7583         int actual_link_speed;
7584
7585         if (hw->mac.type != e1000_82576)
7586                 return -EOPNOTSUPP;
7587
7588         actual_link_speed = igb_link_mbps(adapter->link_speed);
7589         if ((vf >= adapter->vfs_allocated_count) ||
7590             (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7591             (tx_rate < 0) || (tx_rate > actual_link_speed))
7592                 return -EINVAL;
7593
7594         adapter->vf_rate_link_speed = actual_link_speed;
7595         adapter->vf_data[vf].tx_rate = (u16)tx_rate;
7596         igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);
7597
7598         return 0;
7599 }
7600
7601 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
7602                                    bool setting)
7603 {
7604         struct igb_adapter *adapter = netdev_priv(netdev);
7605         struct e1000_hw *hw = &adapter->hw;
7606         u32 reg_val, reg_offset;
7607
7608         if (!adapter->vfs_allocated_count)
7609                 return -EOPNOTSUPP;
7610
7611         if (vf >= adapter->vfs_allocated_count)
7612                 return -EINVAL;
7613
7614         reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
7615         reg_val = rd32(reg_offset);
7616         if (setting)
7617                 reg_val |= ((1 << vf) |
7618                             (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7619         else
7620                 reg_val &= ~((1 << vf) |
7621                              (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7622         wr32(reg_offset, reg_val);
7623
7624         adapter->vf_data[vf].spoofchk_enabled = setting;
7625         return E1000_SUCCESS;
7626 }
7627
7628 static int igb_ndo_get_vf_config(struct net_device *netdev,
7629                                  int vf, struct ifla_vf_info *ivi)
7630 {
7631         struct igb_adapter *adapter = netdev_priv(netdev);
7632         if (vf >= adapter->vfs_allocated_count)
7633                 return -EINVAL;
7634         ivi->vf = vf;
7635         memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
7636         ivi->tx_rate = adapter->vf_data[vf].tx_rate;
7637         ivi->vlan = adapter->vf_data[vf].pf_vlan;
7638         ivi->qos = adapter->vf_data[vf].pf_qos;
7639         ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
7640         return 0;
7641 }
7642
7643 static void igb_vmm_control(struct igb_adapter *adapter)
7644 {
7645         struct e1000_hw *hw = &adapter->hw;
7646         u32 reg;
7647
7648         switch (hw->mac.type) {
7649         case e1000_82575:
7650         case e1000_i210:
7651         case e1000_i211:
7652         case e1000_i354:
7653         default:
7654                 /* replication is not supported for 82575 */
7655                 return;
7656         case e1000_82576:
7657                 /* notify HW that the MAC is adding vlan tags */
7658                 reg = rd32(E1000_DTXCTL);
7659                 reg |= E1000_DTXCTL_VLAN_ADDED;
7660                 wr32(E1000_DTXCTL, reg);
7661         case e1000_82580:
7662                 /* enable replication vlan tag stripping */
7663                 reg = rd32(E1000_RPLOLR);
7664                 reg |= E1000_RPLOLR_STRVLAN;
7665                 wr32(E1000_RPLOLR, reg);
7666         case e1000_i350:
7667                 /* none of the above registers are supported by i350 */
7668                 break;
7669         }
7670
7671         if (adapter->vfs_allocated_count) {
7672                 igb_vmdq_set_loopback_pf(hw, true);
7673                 igb_vmdq_set_replication_pf(hw, true);
7674                 igb_vmdq_set_anti_spoofing_pf(hw, true,
7675                                               adapter->vfs_allocated_count);
7676         } else {
7677                 igb_vmdq_set_loopback_pf(hw, false);
7678                 igb_vmdq_set_replication_pf(hw, false);
7679         }
7680 }
7681
7682 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7683 {
7684         struct e1000_hw *hw = &adapter->hw;
7685         u32 dmac_thr;
7686         u16 hwm;
7687
7688         if (hw->mac.type > e1000_82580) {
7689                 if (adapter->flags & IGB_FLAG_DMAC) {
7690                         u32 reg;
7691
7692                         /* force threshold to 0. */
7693                         wr32(E1000_DMCTXTH, 0);
7694
7695                         /* DMA Coalescing high water mark needs to be greater
7696                          * than the Rx threshold. Set hwm to PBA - max frame
7697                          * size in 16B units, capping it at PBA - 6KB.
7698                          */
7699                         hwm = 64 * pba - adapter->max_frame_size / 16;
7700                         if (hwm < 64 * (pba - 6))
7701                                 hwm = 64 * (pba - 6);
7702                         reg = rd32(E1000_FCRTC);
7703                         reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7704                         reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7705                                 & E1000_FCRTC_RTH_COAL_MASK);
7706                         wr32(E1000_FCRTC, reg);
7707
7708                         /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
7709                          * frame size, capping it at PBA - 10KB.
7710                          */
7711                         dmac_thr = pba - adapter->max_frame_size / 512;
7712                         if (dmac_thr < pba - 10)
7713                                 dmac_thr = pba - 10;
7714                         reg = rd32(E1000_DMACR);
7715                         reg &= ~E1000_DMACR_DMACTHR_MASK;
7716                         reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7717                                 & E1000_DMACR_DMACTHR_MASK);
7718
7719                         /* transition to L0x or L1 if available..*/
7720                         reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7721
7722                         /* watchdog timer= +-1000 usec in 32usec intervals */
7723                         reg |= (1000 >> 5);
7724
7725                         /* Disable BMC-to-OS Watchdog Enable */
7726                         if (hw->mac.type != e1000_i354)
7727                                 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
7728
7729                         wr32(E1000_DMACR, reg);
7730
7731                         /* no lower threshold to disable
7732                          * coalescing(smart fifb)-UTRESH=0
7733                          */
7734                         wr32(E1000_DMCRTRH, 0);
7735
7736                         reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7737
7738                         wr32(E1000_DMCTLX, reg);
7739
7740                         /* free space in tx packet buffer to wake from
7741                          * DMA coal
7742                          */
7743                         wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7744                              (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
7745
7746                         /* make low power state decision controlled
7747                          * by DMA coal
7748                          */
7749                         reg = rd32(E1000_PCIEMISC);
7750                         reg &= ~E1000_PCIEMISC_LX_DECISION;
7751                         wr32(E1000_PCIEMISC, reg);
7752                 } /* endif adapter->dmac is not disabled */
7753         } else if (hw->mac.type == e1000_82580) {
7754                 u32 reg = rd32(E1000_PCIEMISC);
7755                 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
7756                 wr32(E1000_DMACR, 0);
7757         }
7758 }
7759
7760 /**
7761  *  igb_read_i2c_byte - Reads 8 bit word over I2C
7762  *  @hw: pointer to hardware structure
7763  *  @byte_offset: byte offset to read
7764  *  @dev_addr: device address
7765  *  @data: value read
7766  *
7767  *  Performs byte read operation over I2C interface at
7768  *  a specified device address.
7769  **/
7770 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
7771                       u8 dev_addr, u8 *data)
7772 {
7773         struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
7774         struct i2c_client *this_client = adapter->i2c_client;
7775         s32 status;
7776         u16 swfw_mask = 0;
7777
7778         if (!this_client)
7779                 return E1000_ERR_I2C;
7780
7781         swfw_mask = E1000_SWFW_PHY0_SM;
7782
7783         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
7784             != E1000_SUCCESS)
7785                 return E1000_ERR_SWFW_SYNC;
7786
7787         status = i2c_smbus_read_byte_data(this_client, byte_offset);
7788         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
7789
7790         if (status < 0)
7791                 return E1000_ERR_I2C;
7792         else {
7793                 *data = status;
7794                 return E1000_SUCCESS;
7795         }
7796 }
7797
7798 /**
7799  *  igb_write_i2c_byte - Writes 8 bit word over I2C
7800  *  @hw: pointer to hardware structure
7801  *  @byte_offset: byte offset to write
7802  *  @dev_addr: device address
7803  *  @data: value to write
7804  *
7805  *  Performs byte write operation over I2C interface at
7806  *  a specified device address.
7807  **/
7808 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
7809                        u8 dev_addr, u8 data)
7810 {
7811         struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
7812         struct i2c_client *this_client = adapter->i2c_client;
7813         s32 status;
7814         u16 swfw_mask = E1000_SWFW_PHY0_SM;
7815
7816         if (!this_client)
7817                 return E1000_ERR_I2C;
7818
7819         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS)
7820                 return E1000_ERR_SWFW_SYNC;
7821         status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
7822         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
7823
7824         if (status)
7825                 return E1000_ERR_I2C;
7826         else
7827                 return E1000_SUCCESS;
7828
7829 }
7830
7831 int igb_reinit_queues(struct igb_adapter *adapter)
7832 {
7833         struct net_device *netdev = adapter->netdev;
7834         struct pci_dev *pdev = adapter->pdev;
7835         int err = 0;
7836
7837         if (netif_running(netdev))
7838                 igb_close(netdev);
7839
7840         igb_clear_interrupt_scheme(adapter);
7841
7842         if (igb_init_interrupt_scheme(adapter, true)) {
7843                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7844                 return -ENOMEM;
7845         }
7846
7847         if (netif_running(netdev))
7848                 err = igb_open(netdev);
7849
7850         return err;
7851 }
7852 /* igb_main.c */