drivers/net/ethernet/intel/igb/igb_ptp.c

   1 /* PTP Hardware Clock (PHC) driver for the Intel 82576 and 82580
   2  *
   3  * Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program; if not, see <http://www.gnu.org/licenses/>.
  17  */
  18 #include <linux/module.h>
  19 #include <linux/device.h>
  20 #include <linux/pci.h>
  21 #include <linux/ptp_classify.h>
  22
  23 #include "igb.h"
  24
  25 #define INCVALUE_MASK           0x7fffffff
  26 #define ISGN                    0x80000000
  27
  28 /* The 82580 timesync updates the system timer every 8ns by 8ns,
  29  * and this update value cannot be reprogrammed.
  30  *
  31  * Neither the 82576 nor the 82580 offer registers wide enough to hold
  32  * nanoseconds time values for very long. For the 82580, SYSTIM always
  33  * counts nanoseconds, but the upper 24 bits are not availible. The
  34  * frequency is adjusted by changing the 32 bit fractional nanoseconds
  35  * register, TIMINCA.
  36  *
  37  * For the 82576, the SYSTIM register time unit is affect by the
  38  * choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this
  39  * field are needed to provide the nominal 16 nanosecond period,
  40  * leaving 19 bits for fractional nanoseconds.
  41  *
  42  * We scale the NIC clock cycle by a large factor so that relatively
  43  * small clock corrections can be added or subtracted at each clock
  44  * tick. The drawbacks of a large factor are a) that the clock
  45  * register overflows more quickly (not such a big deal) and b) that
  46  * the increment per tick has to fit into 24 bits.  As a result we
  47  * need to use a shift of 19 so we can fit a value of 16 into the
  48  * TIMINCA register.
  49  *
  50  *
  51  *             SYSTIMH            SYSTIML
  52  *        +--------------+   +---+---+------+
  53  *  82576 |      32      |   | 8 | 5 |  19  |
  54  *        +--------------+   +---+---+------+
  55  *         \________ 45 bits _______/  fract
  56  *
  57  *        +----------+---+   +--------------+
  58  *  82580 |    24    | 8 |   |      32      |
  59  *        +----------+---+   +--------------+
  60  *          reserved  \______ 40 bits _____/
  61  *
  62  *
  63  * The 45 bit 82576 SYSTIM overflows every
  64  *   2^45 * 10^-9 / 3600 = 9.77 hours.
  65  *
  66  * The 40 bit 82580 SYSTIM overflows every
  67  *   2^40 * 10^-9 /  60  = 18.3 minutes.
  68  */
  69
  70 #define IGB_SYSTIM_OVERFLOW_PERIOD      (HZ * 60 * 9)
  71 #define IGB_PTP_TX_TIMEOUT              (HZ * 15)
  72 #define INCPERIOD_82576                 (1 << E1000_TIMINCA_16NS_SHIFT)
  73 #define INCVALUE_82576_MASK             ((1 << E1000_TIMINCA_16NS_SHIFT) - 1)
  74 #define INCVALUE_82576                  (16 << IGB_82576_TSYNC_SHIFT)
  75 #define IGB_NBITS_82580                 40
  76
  77 static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter);
  78
  79 /* SYSTIM read access for the 82576 */
  80 static cycle_t igb_ptp_read_82576(const struct cyclecounter *cc)
  81 {
  82         struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
  83         struct e1000_hw *hw = &igb->hw;
  84         u64 val;
  85         u32 lo, hi;
  86
  87         lo = rd32(E1000_SYSTIML);
  88         hi = rd32(E1000_SYSTIMH);
  89
  90         val = ((u64) hi) << 32;
  91         val |= lo;
  92
  93         return val;
  94 }
  95
  96 /* SYSTIM read access for the 82580 */
  97 static cycle_t igb_ptp_read_82580(const struct cyclecounter *cc)
  98 {
  99         struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
 100         struct e1000_hw *hw = &igb->hw;
 101         u32 lo, hi;
 102         u64 val;
 103
 104         /* The timestamp latches on lowest register read. For the 82580
 105          * the lowest register is SYSTIMR instead of SYSTIML.  However we only
 106          * need to provide nanosecond resolution, so we just ignore it.
 107          */
 108         rd32(E1000_SYSTIMR);
 109         lo = rd32(E1000_SYSTIML);
 110         hi = rd32(E1000_SYSTIMH);
 111
 112         val = ((u64) hi) << 32;
 113         val |= lo;
 114
 115         return val;
 116 }
 117
 118 /* SYSTIM read access for I210/I211 */
 119 static void igb_ptp_read_i210(struct igb_adapter *adapter, struct timespec *ts)
 120 {
 121         struct e1000_hw *hw = &adapter->hw;
 122         u32 sec, nsec;
 123
 124         /* The timestamp latches on lowest register read. For I210/I211, the
 125          * lowest register is SYSTIMR. Since we only need to provide nanosecond
 126          * resolution, we can ignore it.
 127          */
 128         rd32(E1000_SYSTIMR);
 129         nsec = rd32(E1000_SYSTIML);
 130         sec = rd32(E1000_SYSTIMH);
 131
 132         ts->tv_sec = sec;
 133         ts->tv_nsec = nsec;
 134 }
 135
 136 static void igb_ptp_write_i210(struct igb_adapter *adapter,
 137                                const struct timespec *ts)
 138 {
 139         struct e1000_hw *hw = &adapter->hw;
 140
 141         /* Writing the SYSTIMR register is not necessary as it only provides
 142          * sub-nanosecond resolution.
 143          */
 144         wr32(E1000_SYSTIML, ts->tv_nsec);
 145         wr32(E1000_SYSTIMH, ts->tv_sec);
 146 }
 147
 148 /**
 149  * igb_ptp_systim_to_hwtstamp - convert system time value to hw timestamp
 150  * @adapter: board private structure
 151  * @hwtstamps: timestamp structure to update
 152  * @systim: unsigned 64bit system time value.
 153  *
 154  * We need to convert the system time value stored in the RX/TXSTMP registers
 155  * into a hwtstamp which can be used by the upper level timestamping functions.
 156  *
 157  * The 'tmreg_lock' spinlock is used to protect the consistency of the
 158  * system time value. This is needed because reading the 64 bit time
 159  * value involves reading two (or three) 32 bit registers. The first
 160  * read latches the value. Ditto for writing.
 161  *
 162  * In addition, here have extended the system time with an overflow
 163  * counter in software.
 164  **/
 165 static void igb_ptp_systim_to_hwtstamp(struct igb_adapter *adapter,
 166                                        struct skb_shared_hwtstamps *hwtstamps,
 167                                        u64 systim)
 168 {
 169         unsigned long flags;
 170         u64 ns;
 171
 172         switch (adapter->hw.mac.type) {
 173         case e1000_82576:
 174         case e1000_82580:
 175         case e1000_i354:
 176         case e1000_i350:
 177                 spin_lock_irqsave(&adapter->tmreg_lock, flags);
 178
 179                 ns = timecounter_cyc2time(&adapter->tc, systim);
 180
 181                 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 182
 183                 memset(hwtstamps, 0, sizeof(*hwtstamps));
 184                 hwtstamps->hwtstamp = ns_to_ktime(ns);
 185                 break;
 186         case e1000_i210:
 187         case e1000_i211:
 188                 memset(hwtstamps, 0, sizeof(*hwtstamps));
 189                 /* Upper 32 bits contain s, lower 32 bits contain ns. */
 190                 hwtstamps->hwtstamp = ktime_set(systim >> 32,
 191                                                 systim & 0xFFFFFFFF);
 192                 break;
 193         default:
 194                 break;
 195         }
 196 }
 197
 198 /* PTP clock operations */
 199 static int igb_ptp_adjfreq_82576(struct ptp_clock_info *ptp, s32 ppb)
 200 {
 201         struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
 202                                                ptp_caps);
 203         struct e1000_hw *hw = &igb->hw;
 204         int neg_adj = 0;
 205         u64 rate;
 206         u32 incvalue;
 207
 208         if (ppb < 0) {
 209                 neg_adj = 1;
 210                 ppb = -ppb;
 211         }
 212         rate = ppb;
 213         rate <<= 14;
 214         rate = div_u64(rate, 1953125);
 215
 216         incvalue = 16 << IGB_82576_TSYNC_SHIFT;
 217
 218         if (neg_adj)
 219                 incvalue -= rate;
 220         else
 221                 incvalue += rate;
 222
 223         wr32(E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK));
 224
 225         return 0;
 226 }
 227
 228 static int igb_ptp_adjfreq_82580(struct ptp_clock_info *ptp, s32 ppb)
 229 {
 230         struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
 231                                                ptp_caps);
 232         struct e1000_hw *hw = &igb->hw;
 233         int neg_adj = 0;
 234         u64 rate;
 235         u32 inca;
 236
 237         if (ppb < 0) {
 238                 neg_adj = 1;
 239                 ppb = -ppb;
 240         }
 241         rate = ppb;
 242         rate <<= 26;
 243         rate = div_u64(rate, 1953125);
 244
 245         inca = rate & INCVALUE_MASK;
 246         if (neg_adj)
 247                 inca |= ISGN;
 248
 249         wr32(E1000_TIMINCA, inca);
 250
 251         return 0;
 252 }
 253
 254 static int igb_ptp_adjtime_82576(struct ptp_clock_info *ptp, s64 delta)
 255 {
 256         struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
 257                                                ptp_caps);
 258         unsigned long flags;
 259
 260         spin_lock_irqsave(&igb->tmreg_lock, flags);
 261         timecounter_adjtime(&igb->tc, delta);
 262         spin_unlock_irqrestore(&igb->tmreg_lock, flags);
 263
 264         return 0;
 265 }
 266
 267 static int igb_ptp_adjtime_i210(struct ptp_clock_info *ptp, s64 delta)
 268 {
 269         struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
 270                                                ptp_caps);
 271         unsigned long flags;
 272         struct timespec now, then = ns_to_timespec(delta);
 273
 274         spin_lock_irqsave(&igb->tmreg_lock, flags);
 275
 276         igb_ptp_read_i210(igb, &now);
 277         now = timespec_add(now, then);
 278         igb_ptp_write_i210(igb, (const struct timespec *)&now);
 279
 280         spin_unlock_irqrestore(&igb->tmreg_lock, flags);
 281
 282         return 0;
 283 }
 284
 285 static int igb_ptp_gettime_82576(struct ptp_clock_info *ptp,
 286                                  struct timespec *ts)
 287 {
 288         struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
 289                                                ptp_caps);
 290         unsigned long flags;
 291         u64 ns;
 292         u32 remainder;
 293
 294         spin_lock_irqsave(&igb->tmreg_lock, flags);
 295
 296         ns = timecounter_read(&igb->tc);
 297
 298         spin_unlock_irqrestore(&igb->tmreg_lock, flags);
 299
 300         ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
 301         ts->tv_nsec = remainder;
 302
 303         return 0;
 304 }
 305
 306 static int igb_ptp_gettime_i210(struct ptp_clock_info *ptp,
 307                                 struct timespec *ts)
 308 {
 309         struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
 310                                                ptp_caps);
 311         unsigned long flags;
 312
 313         spin_lock_irqsave(&igb->tmreg_lock, flags);
 314
 315         igb_ptp_read_i210(igb, ts);
 316
 317         spin_unlock_irqrestore(&igb->tmreg_lock, flags);
 318
 319         return 0;
 320 }
 321
 322 static int igb_ptp_settime_82576(struct ptp_clock_info *ptp,
 323                                  const struct timespec *ts)
 324 {
 325         struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
 326                                                ptp_caps);
 327         unsigned long flags;
 328         u64 ns;
 329
 330         ns = ts->tv_sec * 1000000000ULL;
 331         ns += ts->tv_nsec;
 332
 333         spin_lock_irqsave(&igb->tmreg_lock, flags);
 334
 335         timecounter_init(&igb->tc, &igb->cc, ns);
 336
 337         spin_unlock_irqrestore(&igb->tmreg_lock, flags);
 338
 339         return 0;
 340 }
 341
 342 static int igb_ptp_settime_i210(struct ptp_clock_info *ptp,
 343                                 const struct timespec *ts)
 344 {
 345         struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
 346                                                ptp_caps);
 347         unsigned long flags;
 348
 349         spin_lock_irqsave(&igb->tmreg_lock, flags);
 350
 351         igb_ptp_write_i210(igb, ts);
 352
 353         spin_unlock_irqrestore(&igb->tmreg_lock, flags);
 354
 355         return 0;
 356 }
 357
 358 static int igb_ptp_feature_enable(struct ptp_clock_info *ptp,
 359                                   struct ptp_clock_request *rq, int on)
 360 {
 361         return -EOPNOTSUPP;
 362 }
 363
 364 /**
 365  * igb_ptp_tx_work
 366  * @work: pointer to work struct
 367  *
 368  * This work function polls the TSYNCTXCTL valid bit to determine when a
 369  * timestamp has been taken for the current stored skb.
 370  **/
 371 static void igb_ptp_tx_work(struct work_struct *work)
 372 {
 373         struct igb_adapter *adapter = container_of(work, struct igb_adapter,
 374                                                    ptp_tx_work);
 375         struct e1000_hw *hw = &adapter->hw;
 376         u32 tsynctxctl;
 377
 378         if (!adapter->ptp_tx_skb)
 379                 return;
 380
 381         if (time_is_before_jiffies(adapter->ptp_tx_start +
 382                                    IGB_PTP_TX_TIMEOUT)) {
 383                 dev_kfree_skb_any(adapter->ptp_tx_skb);
 384                 adapter->ptp_tx_skb = NULL;
 385                 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
 386                 adapter->tx_hwtstamp_timeouts++;
 387                 dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n");
 388                 return;
 389         }
 390
 391         tsynctxctl = rd32(E1000_TSYNCTXCTL);
 392         if (tsynctxctl & E1000_TSYNCTXCTL_VALID)
 393                 igb_ptp_tx_hwtstamp(adapter);
 394         else
 395                 /* reschedule to check later */
 396                 schedule_work(&adapter->ptp_tx_work);
 397 }
 398
 399 static void igb_ptp_overflow_check(struct work_struct *work)
 400 {
 401         struct igb_adapter *igb =
 402                 container_of(work, struct igb_adapter, ptp_overflow_work.work);
 403         struct timespec ts;
 404
 405         igb->ptp_caps.gettime(&igb->ptp_caps, &ts);
 406
 407         pr_debug("igb overflow check at %ld.%09lu\n", ts.tv_sec, ts.tv_nsec);
 408
 409         schedule_delayed_work(&igb->ptp_overflow_work,
 410                               IGB_SYSTIM_OVERFLOW_PERIOD);
 411 }
 412
 413 /**
 414  * igb_ptp_rx_hang - detect error case when Rx timestamp registers latched
 415  * @adapter: private network adapter structure
 416  *
 417  * This watchdog task is scheduled to detect error case where hardware has
 418  * dropped an Rx packet that was timestamped when the ring is full. The
 419  * particular error is rare but leaves the device in a state unable to timestamp
 420  * any future packets.
 421  **/
 422 void igb_ptp_rx_hang(struct igb_adapter *adapter)
 423 {
 424         struct e1000_hw *hw = &adapter->hw;
 425         u32 tsyncrxctl = rd32(E1000_TSYNCRXCTL);
 426         unsigned long rx_event;
 427
 428         if (hw->mac.type != e1000_82576)
 429                 return;
 430
 431         /* If we don't have a valid timestamp in the registers, just update the
 432          * timeout counter and exit
 433          */
 434         if (!(tsyncrxctl & E1000_TSYNCRXCTL_VALID)) {
 435                 adapter->last_rx_ptp_check = jiffies;
 436                 return;
 437         }
 438
 439         /* Determine the most recent watchdog or rx_timestamp event */
 440         rx_event = adapter->last_rx_ptp_check;
 441         if (time_after(adapter->last_rx_timestamp, rx_event))
 442                 rx_event = adapter->last_rx_timestamp;
 443
 444         /* Only need to read the high RXSTMP register to clear the lock */
 445         if (time_is_before_jiffies(rx_event + 5 * HZ)) {
 446                 rd32(E1000_RXSTMPH);
 447                 adapter->last_rx_ptp_check = jiffies;
 448                 adapter->rx_hwtstamp_cleared++;
 449                 dev_warn(&adapter->pdev->dev, "clearing Rx timestamp hang\n");
 450         }
 451 }
 452
 453 /**
 454  * igb_ptp_tx_hwtstamp - utility function which checks for TX time stamp
 455  * @adapter: Board private structure.
 456  *
 457  * If we were asked to do hardware stamping and such a time stamp is
 458  * available, then it must have been for this skb here because we only
 459  * allow only one such packet into the queue.
 460  **/
 461 static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter)
 462 {
 463         struct e1000_hw *hw = &adapter->hw;
 464         struct skb_shared_hwtstamps shhwtstamps;
 465         u64 regval;
 466
 467         regval = rd32(E1000_TXSTMPL);
 468         regval |= (u64)rd32(E1000_TXSTMPH) << 32;
 469
 470         igb_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval);
 471         skb_tstamp_tx(adapter->ptp_tx_skb, &shhwtstamps);
 472         dev_kfree_skb_any(adapter->ptp_tx_skb);
 473         adapter->ptp_tx_skb = NULL;
 474         clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
 475 }
 476
 477 /**
 478  * igb_ptp_rx_pktstamp - retrieve Rx per packet timestamp
 479  * @q_vector: Pointer to interrupt specific structure
 480  * @va: Pointer to address containing Rx buffer
 481  * @skb: Buffer containing timestamp and packet
 482  *
 483  * This function is meant to retrieve a timestamp from the first buffer of an
 484  * incoming frame.  The value is stored in little endian format starting on
 485  * byte 8.
 486  **/
 487 void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector,
 488                          unsigned char *va,
 489                          struct sk_buff *skb)
 490 {
 491         __le64 *regval = (__le64 *)va;
 492
 493         /* The timestamp is recorded in little endian format.
 494          * DWORD: 0        1        2        3
 495          * Field: Reserved Reserved SYSTIML  SYSTIMH
 496          */
 497         igb_ptp_systim_to_hwtstamp(q_vector->adapter, skb_hwtstamps(skb),
 498                                    le64_to_cpu(regval[1]));
 499 }
 500
 501 /**
 502  * igb_ptp_rx_rgtstamp - retrieve Rx timestamp stored in register
 503  * @q_vector: Pointer to interrupt specific structure
 504  * @skb: Buffer containing timestamp and packet
 505  *
 506  * This function is meant to retrieve a timestamp from the internal registers
 507  * of the adapter and store it in the skb.
 508  **/
 509 void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector,
 510                          struct sk_buff *skb)
 511 {
 512         struct igb_adapter *adapter = q_vector->adapter;
 513         struct e1000_hw *hw = &adapter->hw;
 514         u64 regval;
 515
 516         /* If this bit is set, then the RX registers contain the time stamp. No
 517          * other packet will be time stamped until we read these registers, so
 518          * read the registers to make them available again. Because only one
 519          * packet can be time stamped at a time, we know that the register
 520          * values must belong to this one here and therefore we don't need to
 521          * compare any of the additional attributes stored for it.
 522          *
 523          * If nothing went wrong, then it should have a shared tx_flags that we
 524          * can turn into a skb_shared_hwtstamps.
 525          */
 526         if (!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
 527                 return;
 528
 529         regval = rd32(E1000_RXSTMPL);
 530         regval |= (u64)rd32(E1000_RXSTMPH) << 32;
 531
 532         igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
 533
 534         /* Update the last_rx_timestamp timer in order to enable watchdog check
 535          * for error case of latched timestamp on a dropped packet.
 536          */
 537         adapter->last_rx_timestamp = jiffies;
 538 }
 539
 540 /**
 541  * igb_ptp_get_ts_config - get hardware time stamping config
 542  * @netdev:
 543  * @ifreq:
 544  *
 545  * Get the hwtstamp_config settings to return to the user. Rather than attempt
 546  * to deconstruct the settings from the registers, just return a shadow copy
 547  * of the last known settings.
 548  **/
 549 int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr)
 550 {
 551         struct igb_adapter *adapter = netdev_priv(netdev);
 552         struct hwtstamp_config *config = &adapter->tstamp_config;
 553
 554         return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
 555                 -EFAULT : 0;
 556 }
 557
 558 /**
 559  * igb_ptp_set_timestamp_mode - setup hardware for timestamping
 560  * @adapter: networking device structure
 561  * @config: hwtstamp configuration
 562  *
 563  * Outgoing time stamping can be enabled and disabled. Play nice and
 564  * disable it when requested, although it shouldn't case any overhead
 565  * when no packet needs it. At most one packet in the queue may be
 566  * marked for time stamping, otherwise it would be impossible to tell
 567  * for sure to which packet the hardware time stamp belongs.
 568  *
 569  * Incoming time stamping has to be configured via the hardware
 570  * filters. Not all combinations are supported, in particular event
 571  * type has to be specified. Matching the kind of event packet is
 572  * not supported, with the exception of "all V2 events regardless of
 573  * level 2 or 4".
 574  */
 575 static int igb_ptp_set_timestamp_mode(struct igb_adapter *adapter,
 576                                       struct hwtstamp_config *config)
 577 {
 578         struct e1000_hw *hw = &adapter->hw;
 579         u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
 580         u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
 581         u32 tsync_rx_cfg = 0;
 582         bool is_l4 = false;
 583         bool is_l2 = false;
 584         u32 regval;
 585
 586         /* reserved for future extensions */
 587         if (config->flags)
 588                 return -EINVAL;
 589
 590         switch (config->tx_type) {
 591         case HWTSTAMP_TX_OFF:
 592                 tsync_tx_ctl = 0;
 593         case HWTSTAMP_TX_ON:
 594                 break;
 595         default:
 596                 return -ERANGE;
 597         }
 598
 599         switch (config->rx_filter) {
 600         case HWTSTAMP_FILTER_NONE:
 601                 tsync_rx_ctl = 0;
 602                 break;
 603         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 604                 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
 605                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
 606                 is_l4 = true;
 607                 break;
 608         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 609                 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
 610                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
 611                 is_l4 = true;
 612                 break;
 613         case HWTSTAMP_FILTER_PTP_V2_EVENT:
 614         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
 615         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 616         case HWTSTAMP_FILTER_PTP_V2_SYNC:
 617         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
 618         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 619         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 620         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
 621         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 622                 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
 623                 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
 624                 is_l2 = true;
 625                 is_l4 = true;
 626                 break;
 627         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 628         case HWTSTAMP_FILTER_ALL:
 629                 /* 82576 cannot timestamp all packets, which it needs to do to
 630                  * support both V1 Sync and Delay_Req messages
 631                  */
 632                 if (hw->mac.type != e1000_82576) {
 633                         tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
 634                         config->rx_filter = HWTSTAMP_FILTER_ALL;
 635                         break;
 636                 }
 637                 /* fall through */
 638         default:
 639                 config->rx_filter = HWTSTAMP_FILTER_NONE;
 640                 return -ERANGE;
 641         }
 642
 643         if (hw->mac.type == e1000_82575) {
 644                 if (tsync_rx_ctl | tsync_tx_ctl)
 645                         return -EINVAL;
 646                 return 0;
 647         }
 648
 649         /* Per-packet timestamping only works if all packets are
 650          * timestamped, so enable timestamping in all packets as
 651          * long as one Rx filter was configured.
 652          */
 653         if ((hw->mac.type >= e1000_82580) && tsync_rx_ctl) {
 654                 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
 655                 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
 656                 config->rx_filter = HWTSTAMP_FILTER_ALL;
 657                 is_l2 = true;
 658                 is_l4 = true;
 659
 660                 if ((hw->mac.type == e1000_i210) ||
 661                     (hw->mac.type == e1000_i211)) {
 662                         regval = rd32(E1000_RXPBS);
 663                         regval |= E1000_RXPBS_CFG_TS_EN;
 664                         wr32(E1000_RXPBS, regval);
 665                 }
 666         }
 667
 668         /* enable/disable TX */
 669         regval = rd32(E1000_TSYNCTXCTL);
 670         regval &= ~E1000_TSYNCTXCTL_ENABLED;
 671         regval |= tsync_tx_ctl;
 672         wr32(E1000_TSYNCTXCTL, regval);
 673
 674         /* enable/disable RX */
 675         regval = rd32(E1000_TSYNCRXCTL);
 676         regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
 677         regval |= tsync_rx_ctl;
 678         wr32(E1000_TSYNCRXCTL, regval);
 679
 680         /* define which PTP packets are time stamped */
 681         wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
 682
 683         /* define ethertype filter for timestamped packets */
 684         if (is_l2)
 685                 wr32(E1000_ETQF(3),
 686                      (E1000_ETQF_FILTER_ENABLE | /* enable filter */
 687                       E1000_ETQF_1588 | /* enable timestamping */
 688                       ETH_P_1588));     /* 1588 eth protocol type */
 689         else
 690                 wr32(E1000_ETQF(3), 0);
 691
 692         /* L4 Queue Filter[3]: filter by destination port and protocol */
 693         if (is_l4) {
 694                 u32 ftqf = (IPPROTO_UDP /* UDP */
 695                         | E1000_FTQF_VF_BP /* VF not compared */
 696                         | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */
 697                         | E1000_FTQF_MASK); /* mask all inputs */
 698                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */
 699
 700                 wr32(E1000_IMIR(3), htons(PTP_EV_PORT));
 701                 wr32(E1000_IMIREXT(3),
 702                      (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP));
 703                 if (hw->mac.type == e1000_82576) {
 704                         /* enable source port check */
 705                         wr32(E1000_SPQF(3), htons(PTP_EV_PORT));
 706                         ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
 707                 }
 708                 wr32(E1000_FTQF(3), ftqf);
 709         } else {
 710                 wr32(E1000_FTQF(3), E1000_FTQF_MASK);
 711         }
 712         wrfl();
 713
 714         /* clear TX/RX time stamp registers, just to be sure */
 715         regval = rd32(E1000_TXSTMPL);
 716         regval = rd32(E1000_TXSTMPH);
 717         regval = rd32(E1000_RXSTMPL);
 718         regval = rd32(E1000_RXSTMPH);
 719
 720         return 0;
 721 }
 722
 723 /**
 724  * igb_ptp_set_ts_config - set hardware time stamping config
 725  * @netdev:
 726  * @ifreq:
 727  *
 728  **/
 729 int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr)
 730 {
 731         struct igb_adapter *adapter = netdev_priv(netdev);
 732         struct hwtstamp_config config;
 733         int err;
 734
 735         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
 736                 return -EFAULT;
 737
 738         err = igb_ptp_set_timestamp_mode(adapter, &config);
 739         if (err)
 740                 return err;
 741
 742         /* save these settings for future reference */
 743         memcpy(&adapter->tstamp_config, &config,
 744                sizeof(adapter->tstamp_config));
 745
 746         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 747                 -EFAULT : 0;
 748 }
 749
 750 void igb_ptp_init(struct igb_adapter *adapter)
 751 {
 752         struct e1000_hw *hw = &adapter->hw;
 753         struct net_device *netdev = adapter->netdev;
 754
 755         switch (hw->mac.type) {
 756         case e1000_82576:
 757                 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
 758                 adapter->ptp_caps.owner = THIS_MODULE;
 759                 adapter->ptp_caps.max_adj = 999999881;
 760                 adapter->ptp_caps.n_ext_ts = 0;
 761                 adapter->ptp_caps.pps = 0;
 762                 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82576;
 763                 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576;
 764                 adapter->ptp_caps.gettime = igb_ptp_gettime_82576;
 765                 adapter->ptp_caps.settime = igb_ptp_settime_82576;
 766                 adapter->ptp_caps.enable = igb_ptp_feature_enable;
 767                 adapter->cc.read = igb_ptp_read_82576;
 768                 adapter->cc.mask = CYCLECOUNTER_MASK(64);
 769                 adapter->cc.mult = 1;
 770                 adapter->cc.shift = IGB_82576_TSYNC_SHIFT;
 771                 /* Dial the nominal frequency. */
 772                 wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576);
 773                 break;
 774         case e1000_82580:
 775         case e1000_i354:
 776         case e1000_i350:
 777                 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
 778                 adapter->ptp_caps.owner = THIS_MODULE;
 779                 adapter->ptp_caps.max_adj = 62499999;
 780                 adapter->ptp_caps.n_ext_ts = 0;
 781                 adapter->ptp_caps.pps = 0;
 782                 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580;
 783                 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576;
 784                 adapter->ptp_caps.gettime = igb_ptp_gettime_82576;
 785                 adapter->ptp_caps.settime = igb_ptp_settime_82576;
 786                 adapter->ptp_caps.enable = igb_ptp_feature_enable;
 787                 adapter->cc.read = igb_ptp_read_82580;
 788                 adapter->cc.mask = CYCLECOUNTER_MASK(IGB_NBITS_82580);
 789                 adapter->cc.mult = 1;
 790                 adapter->cc.shift = 0;
 791                 /* Enable the timer functions by clearing bit 31. */
 792                 wr32(E1000_TSAUXC, 0x0);
 793                 break;
 794         case e1000_i210:
 795         case e1000_i211:
 796                 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
 797                 adapter->ptp_caps.owner = THIS_MODULE;
 798                 adapter->ptp_caps.max_adj = 62499999;
 799                 adapter->ptp_caps.n_ext_ts = 0;
 800                 adapter->ptp_caps.pps = 0;
 801                 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580;
 802                 adapter->ptp_caps.adjtime = igb_ptp_adjtime_i210;
 803                 adapter->ptp_caps.gettime = igb_ptp_gettime_i210;
 804                 adapter->ptp_caps.settime = igb_ptp_settime_i210;
 805                 adapter->ptp_caps.enable = igb_ptp_feature_enable;
 806                 /* Enable the timer functions by clearing bit 31. */
 807                 wr32(E1000_TSAUXC, 0x0);
 808                 break;
 809         default:
 810                 adapter->ptp_clock = NULL;
 811                 return;
 812         }
 813
 814         wrfl();
 815
 816         spin_lock_init(&adapter->tmreg_lock);
 817         INIT_WORK(&adapter->ptp_tx_work, igb_ptp_tx_work);
 818
 819         /* Initialize the clock and overflow work for devices that need it. */
 820         if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) {
 821                 struct timespec ts = ktime_to_timespec(ktime_get_real());
 822
 823                 igb_ptp_settime_i210(&adapter->ptp_caps, &ts);
 824         } else {
 825                 timecounter_init(&adapter->tc, &adapter->cc,
 826                                  ktime_to_ns(ktime_get_real()));
 827
 828                 INIT_DELAYED_WORK(&adapter->ptp_overflow_work,
 829                                   igb_ptp_overflow_check);
 830
 831                 schedule_delayed_work(&adapter->ptp_overflow_work,
 832                                       IGB_SYSTIM_OVERFLOW_PERIOD);
 833         }
 834
 835         /* Initialize the time sync interrupts for devices that support it. */
 836         if (hw->mac.type >= e1000_82580) {
 837                 wr32(E1000_TSIM, TSYNC_INTERRUPTS);
 838                 wr32(E1000_IMS, E1000_IMS_TS);
 839         }
 840
 841         adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
 842         adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
 843
 844         adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
 845                                                 &adapter->pdev->dev);
 846         if (IS_ERR(adapter->ptp_clock)) {
 847                 adapter->ptp_clock = NULL;
 848                 dev_err(&adapter->pdev->dev, "ptp_clock_register failed\n");
 849         } else {
 850                 dev_info(&adapter->pdev->dev, "added PHC on %s\n",
 851                          adapter->netdev->name);
 852                 adapter->flags |= IGB_FLAG_PTP;
 853         }
 854 }
 855
 856 /**
 857  * igb_ptp_stop - Disable PTP device and stop the overflow check.
 858  * @adapter: Board private structure.
 859  *
 860  * This function stops the PTP support and cancels the delayed work.
 861  **/
 862 void igb_ptp_stop(struct igb_adapter *adapter)
 863 {
 864         switch (adapter->hw.mac.type) {
 865         case e1000_82576:
 866         case e1000_82580:
 867         case e1000_i354:
 868         case e1000_i350:
 869                 cancel_delayed_work_sync(&adapter->ptp_overflow_work);
 870                 break;
 871         case e1000_i210:
 872         case e1000_i211:
 873                 /* No delayed work to cancel. */
 874                 break;
 875         default:
 876                 return;
 877         }
 878
 879         cancel_work_sync(&adapter->ptp_tx_work);
 880         if (adapter->ptp_tx_skb) {
 881                 dev_kfree_skb_any(adapter->ptp_tx_skb);
 882                 adapter->ptp_tx_skb = NULL;
 883                 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
 884         }
 885
 886         if (adapter->ptp_clock) {
 887                 ptp_clock_unregister(adapter->ptp_clock);
 888                 dev_info(&adapter->pdev->dev, "removed PHC on %s\n",
 889                          adapter->netdev->name);
 890                 adapter->flags &= ~IGB_FLAG_PTP;
 891         }
 892 }
 893
 894 /**
 895  * igb_ptp_reset - Re-enable the adapter for PTP following a reset.
 896  * @adapter: Board private structure.
 897  *
 898  * This function handles the reset work required to re-enable the PTP device.
 899  **/
 900 void igb_ptp_reset(struct igb_adapter *adapter)
 901 {
 902         struct e1000_hw *hw = &adapter->hw;
 903
 904         if (!(adapter->flags & IGB_FLAG_PTP))
 905                 return;
 906
 907         /* reset the tstamp_config */
 908         igb_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config);
 909
 910         switch (adapter->hw.mac.type) {
 911         case e1000_82576:
 912                 /* Dial the nominal frequency. */
 913                 wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576);
 914                 break;
 915         case e1000_82580:
 916         case e1000_i354:
 917         case e1000_i350:
 918         case e1000_i210:
 919         case e1000_i211:
 920                 /* Enable the timer functions and interrupts. */
 921                 wr32(E1000_TSAUXC, 0x0);
 922                 wr32(E1000_TSIM, TSYNC_INTERRUPTS);
 923                 wr32(E1000_IMS, E1000_IMS_TS);
 924                 break;
 925         default:
 926                 /* No work to do. */
 927                 return;
 928         }
 929
 930         /* Re-initialize the timer. */
 931         if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) {
 932                 struct timespec ts = ktime_to_timespec(ktime_get_real());
 933
 934                 igb_ptp_settime_i210(&adapter->ptp_caps, &ts);
 935         } else {
 936                 timecounter_init(&adapter->tc, &adapter->cc,
 937                                  ktime_to_ns(ktime_get_real()));
 938         }
 939 }