drivers/net/ethernet/intel/igb/igb_ptp.c

   1 /* PTP Hardware Clock (PHC) driver for the Intel 82576 and 82580
   2  *
   3  * Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program; if not, see <http://www.gnu.org/licenses/>.
  17  */
  18 #include <linux/module.h>
  19 #include <linux/device.h>
  20 #include <linux/pci.h>
  21 #include <linux/ptp_classify.h>
  22
  23 #include "igb.h"
  24
  25 #define INCVALUE_MASK           0x7fffffff
  26 #define ISGN                    0x80000000
  27
  28 /* The 82580 timesync updates the system timer every 8ns by 8ns,
  29  * and this update value cannot be reprogrammed.
  30  *
  31  * Neither the 82576 nor the 82580 offer registers wide enough to hold
  32  * nanoseconds time values for very long. For the 82580, SYSTIM always
  33  * counts nanoseconds, but the upper 24 bits are not available. The
  34  * frequency is adjusted by changing the 32 bit fractional nanoseconds
  35  * register, TIMINCA.
  36  *
  37  * For the 82576, the SYSTIM register time unit is affect by the
  38  * choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this
  39  * field are needed to provide the nominal 16 nanosecond period,
  40  * leaving 19 bits for fractional nanoseconds.
  41  *
  42  * We scale the NIC clock cycle by a large factor so that relatively
  43  * small clock corrections can be added or subtracted at each clock
  44  * tick. The drawbacks of a large factor are a) that the clock
  45  * register overflows more quickly (not such a big deal) and b) that
  46  * the increment per tick has to fit into 24 bits.  As a result we
  47  * need to use a shift of 19 so we can fit a value of 16 into the
  48  * TIMINCA register.
  49  *
  50  *
  51  *             SYSTIMH            SYSTIML
  52  *        +--------------+   +---+---+------+
  53  *  82576 |      32      |   | 8 | 5 |  19  |
  54  *        +--------------+   +---+---+------+
  55  *         \________ 45 bits _______/  fract
  56  *
  57  *        +----------+---+   +--------------+
  58  *  82580 |    24    | 8 |   |      32      |
  59  *        +----------+---+   +--------------+
  60  *          reserved  \______ 40 bits _____/
  61  *
  62  *
  63  * The 45 bit 82576 SYSTIM overflows every
  64  *   2^45 * 10^-9 / 3600 = 9.77 hours.
  65  *
  66  * The 40 bit 82580 SYSTIM overflows every
  67  *   2^40 * 10^-9 /  60  = 18.3 minutes.
  68  */
  69
  70 #define IGB_SYSTIM_OVERFLOW_PERIOD      (HZ * 60 * 9)
  71 #define IGB_PTP_TX_TIMEOUT              (HZ * 15)
  72 #define INCPERIOD_82576                 BIT(E1000_TIMINCA_16NS_SHIFT)
  73 #define INCVALUE_82576_MASK             GENMASK(E1000_TIMINCA_16NS_SHIFT - 1, 0)
  74 #define INCVALUE_82576                  (16u << IGB_82576_TSYNC_SHIFT)
  75 #define IGB_NBITS_82580                 40
  76
  77 static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter);
  78
  79 /* SYSTIM read access for the 82576 */
  80 static cycle_t igb_ptp_read_82576(const struct cyclecounter *cc)
  81 {
  82         struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
  83         struct e1000_hw *hw = &igb->hw;
  84         u64 val;
  85         u32 lo, hi;
  86
  87         lo = rd32(E1000_SYSTIML);
  88         hi = rd32(E1000_SYSTIMH);
  89
  90         val = ((u64) hi) << 32;
  91         val |= lo;
  92
  93         return val;
  94 }
  95
  96 /* SYSTIM read access for the 82580 */
  97 static cycle_t igb_ptp_read_82580(const struct cyclecounter *cc)
  98 {
  99         struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
 100         struct e1000_hw *hw = &igb->hw;
 101         u32 lo, hi;
 102         u64 val;
 103
 104         /* The timestamp latches on lowest register read. For the 82580
 105          * the lowest register is SYSTIMR instead of SYSTIML.  However we only
 106          * need to provide nanosecond resolution, so we just ignore it.
 107          */
 108         rd32(E1000_SYSTIMR);
 109         lo = rd32(E1000_SYSTIML);
 110         hi = rd32(E1000_SYSTIMH);
 111
 112         val = ((u64) hi) << 32;
 113         val |= lo;
 114
 115         return val;
 116 }
 117
 118 /* SYSTIM read access for I210/I211 */
 119 static void igb_ptp_read_i210(struct igb_adapter *adapter,
 120                               struct timespec64 *ts)
 121 {
 122         struct e1000_hw *hw = &adapter->hw;
 123         u32 sec, nsec;
 124
 125         /* The timestamp latches on lowest register read. For I210/I211, the
 126          * lowest register is SYSTIMR. Since we only need to provide nanosecond
 127          * resolution, we can ignore it.
 128          */
 129         rd32(E1000_SYSTIMR);
 130         nsec = rd32(E1000_SYSTIML);
 131         sec = rd32(E1000_SYSTIMH);
 132
 133         ts->tv_sec = sec;
 134         ts->tv_nsec = nsec;
 135 }
 136
 137 static void igb_ptp_write_i210(struct igb_adapter *adapter,
 138                                const struct timespec64 *ts)
 139 {
 140         struct e1000_hw *hw = &adapter->hw;
 141
 142         /* Writing the SYSTIMR register is not necessary as it only provides
 143          * sub-nanosecond resolution.
 144          */
 145         wr32(E1000_SYSTIML, ts->tv_nsec);
 146         wr32(E1000_SYSTIMH, (u32)ts->tv_sec);
 147 }
 148
 149 /**
 150  * igb_ptp_systim_to_hwtstamp - convert system time value to hw timestamp
 151  * @adapter: board private structure
 152  * @hwtstamps: timestamp structure to update
 153  * @systim: unsigned 64bit system time value.
 154  *
 155  * We need to convert the system time value stored in the RX/TXSTMP registers
 156  * into a hwtstamp which can be used by the upper level timestamping functions.
 157  *
 158  * The 'tmreg_lock' spinlock is used to protect the consistency of the
 159  * system time value. This is needed because reading the 64 bit time
 160  * value involves reading two (or three) 32 bit registers. The first
 161  * read latches the value. Ditto for writing.
 162  *
 163  * In addition, here have extended the system time with an overflow
 164  * counter in software.
 165  **/
 166 static void igb_ptp_systim_to_hwtstamp(struct igb_adapter *adapter,
 167                                        struct skb_shared_hwtstamps *hwtstamps,
 168                                        u64 systim)
 169 {
 170         unsigned long flags;
 171         u64 ns;
 172
 173         switch (adapter->hw.mac.type) {
 174         case e1000_82576:
 175         case e1000_82580:
 176         case e1000_i354:
 177         case e1000_i350:
 178                 spin_lock_irqsave(&adapter->tmreg_lock, flags);
 179
 180                 ns = timecounter_cyc2time(&adapter->tc, systim);
 181
 182                 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 183
 184                 memset(hwtstamps, 0, sizeof(*hwtstamps));
 185                 hwtstamps->hwtstamp = ns_to_ktime(ns);
 186                 break;
 187         case e1000_i210:
 188         case e1000_i211:
 189                 memset(hwtstamps, 0, sizeof(*hwtstamps));
 190                 /* Upper 32 bits contain s, lower 32 bits contain ns. */
 191                 hwtstamps->hwtstamp = ktime_set(systim >> 32,
 192                                                 systim & 0xFFFFFFFF);
 193                 break;
 194         default:
 195                 break;
 196         }
 197 }
 198
 199 /* PTP clock operations */
 200 static int igb_ptp_adjfreq_82576(struct ptp_clock_info *ptp, s32 ppb)
 201 {
 202         struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
 203                                                ptp_caps);
 204         struct e1000_hw *hw = &igb->hw;
 205         int neg_adj = 0;
 206         u64 rate;
 207         u32 incvalue;
 208
 209         if (ppb < 0) {
 210                 neg_adj = 1;
 211                 ppb = -ppb;
 212         }
 213         rate = ppb;
 214         rate <<= 14;
 215         rate = div_u64(rate, 1953125);
 216
 217         incvalue = 16 << IGB_82576_TSYNC_SHIFT;
 218
 219         if (neg_adj)
 220                 incvalue -= rate;
 221         else
 222                 incvalue += rate;
 223
 224         wr32(E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK));
 225
 226         return 0;
 227 }
 228
 229 static int igb_ptp_adjfreq_82580(struct ptp_clock_info *ptp, s32 ppb)
 230 {
 231         struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
 232                                                ptp_caps);
 233         struct e1000_hw *hw = &igb->hw;
 234         int neg_adj = 0;
 235         u64 rate;
 236         u32 inca;
 237
 238         if (ppb < 0) {
 239                 neg_adj = 1;
 240                 ppb = -ppb;
 241         }
 242         rate = ppb;
 243         rate <<= 26;
 244         rate = div_u64(rate, 1953125);
 245
 246         inca = rate & INCVALUE_MASK;
 247         if (neg_adj)
 248                 inca |= ISGN;
 249
 250         wr32(E1000_TIMINCA, inca);
 251
 252         return 0;
 253 }
 254
 255 static int igb_ptp_adjtime_82576(struct ptp_clock_info *ptp, s64 delta)
 256 {
 257         struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
 258                                                ptp_caps);
 259         unsigned long flags;
 260
 261         spin_lock_irqsave(&igb->tmreg_lock, flags);
 262         timecounter_adjtime(&igb->tc, delta);
 263         spin_unlock_irqrestore(&igb->tmreg_lock, flags);
 264
 265         return 0;
 266 }
 267
 268 static int igb_ptp_adjtime_i210(struct ptp_clock_info *ptp, s64 delta)
 269 {
 270         struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
 271                                                ptp_caps);
 272         unsigned long flags;
 273         struct timespec64 now, then = ns_to_timespec64(delta);
 274
 275         spin_lock_irqsave(&igb->tmreg_lock, flags);
 276
 277         igb_ptp_read_i210(igb, &now);
 278         now = timespec64_add(now, then);
 279         igb_ptp_write_i210(igb, (const struct timespec64 *)&now);
 280
 281         spin_unlock_irqrestore(&igb->tmreg_lock, flags);
 282
 283         return 0;
 284 }
 285
 286 static int igb_ptp_gettime_82576(struct ptp_clock_info *ptp,
 287                                  struct timespec64 *ts)
 288 {
 289         struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
 290                                                ptp_caps);
 291         unsigned long flags;
 292         u64 ns;
 293
 294         spin_lock_irqsave(&igb->tmreg_lock, flags);
 295
 296         ns = timecounter_read(&igb->tc);
 297
 298         spin_unlock_irqrestore(&igb->tmreg_lock, flags);
 299
 300         *ts = ns_to_timespec64(ns);
 301
 302         return 0;
 303 }
 304
 305 static int igb_ptp_gettime_i210(struct ptp_clock_info *ptp,
 306                                 struct timespec64 *ts)
 307 {
 308         struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
 309                                                ptp_caps);
 310         unsigned long flags;
 311
 312         spin_lock_irqsave(&igb->tmreg_lock, flags);
 313
 314         igb_ptp_read_i210(igb, ts);
 315
 316         spin_unlock_irqrestore(&igb->tmreg_lock, flags);
 317
 318         return 0;
 319 }
 320
 321 static int igb_ptp_settime_82576(struct ptp_clock_info *ptp,
 322                                  const struct timespec64 *ts)
 323 {
 324         struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
 325                                                ptp_caps);
 326         unsigned long flags;
 327         u64 ns;
 328
 329         ns = timespec64_to_ns(ts);
 330
 331         spin_lock_irqsave(&igb->tmreg_lock, flags);
 332
 333         timecounter_init(&igb->tc, &igb->cc, ns);
 334
 335         spin_unlock_irqrestore(&igb->tmreg_lock, flags);
 336
 337         return 0;
 338 }
 339
 340 static int igb_ptp_settime_i210(struct ptp_clock_info *ptp,
 341                                 const struct timespec64 *ts)
 342 {
 343         struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
 344                                                ptp_caps);
 345         unsigned long flags;
 346
 347         spin_lock_irqsave(&igb->tmreg_lock, flags);
 348
 349         igb_ptp_write_i210(igb, ts);
 350
 351         spin_unlock_irqrestore(&igb->tmreg_lock, flags);
 352
 353         return 0;
 354 }
 355
 356 static void igb_pin_direction(int pin, int input, u32 *ctrl, u32 *ctrl_ext)
 357 {
 358         u32 *ptr = pin < 2 ? ctrl : ctrl_ext;
 359         static const u32 mask[IGB_N_SDP] = {
 360                 E1000_CTRL_SDP0_DIR,
 361                 E1000_CTRL_SDP1_DIR,
 362                 E1000_CTRL_EXT_SDP2_DIR,
 363                 E1000_CTRL_EXT_SDP3_DIR,
 364         };
 365
 366         if (input)
 367                 *ptr &= ~mask[pin];
 368         else
 369                 *ptr |= mask[pin];
 370 }
 371
 372 static void igb_pin_extts(struct igb_adapter *igb, int chan, int pin)
 373 {
 374         static const u32 aux0_sel_sdp[IGB_N_SDP] = {
 375                 AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3,
 376         };
 377         static const u32 aux1_sel_sdp[IGB_N_SDP] = {
 378                 AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3,
 379         };
 380         static const u32 ts_sdp_en[IGB_N_SDP] = {
 381                 TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN,
 382         };
 383         struct e1000_hw *hw = &igb->hw;
 384         u32 ctrl, ctrl_ext, tssdp = 0;
 385
 386         ctrl = rd32(E1000_CTRL);
 387         ctrl_ext = rd32(E1000_CTRL_EXT);
 388         tssdp = rd32(E1000_TSSDP);
 389
 390         igb_pin_direction(pin, 1, &ctrl, &ctrl_ext);
 391
 392         /* Make sure this pin is not enabled as an output. */
 393         tssdp &= ~ts_sdp_en[pin];
 394
 395         if (chan == 1) {
 396                 tssdp &= ~AUX1_SEL_SDP3;
 397                 tssdp |= aux1_sel_sdp[pin] | AUX1_TS_SDP_EN;
 398         } else {
 399                 tssdp &= ~AUX0_SEL_SDP3;
 400                 tssdp |= aux0_sel_sdp[pin] | AUX0_TS_SDP_EN;
 401         }
 402
 403         wr32(E1000_TSSDP, tssdp);
 404         wr32(E1000_CTRL, ctrl);
 405         wr32(E1000_CTRL_EXT, ctrl_ext);
 406 }
 407
 408 static void igb_pin_perout(struct igb_adapter *igb, int chan, int pin, int freq)
 409 {
 410         static const u32 aux0_sel_sdp[IGB_N_SDP] = {
 411                 AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3,
 412         };
 413         static const u32 aux1_sel_sdp[IGB_N_SDP] = {
 414                 AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3,
 415         };
 416         static const u32 ts_sdp_en[IGB_N_SDP] = {
 417                 TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN,
 418         };
 419         static const u32 ts_sdp_sel_tt0[IGB_N_SDP] = {
 420                 TS_SDP0_SEL_TT0, TS_SDP1_SEL_TT0,
 421                 TS_SDP2_SEL_TT0, TS_SDP3_SEL_TT0,
 422         };
 423         static const u32 ts_sdp_sel_tt1[IGB_N_SDP] = {
 424                 TS_SDP0_SEL_TT1, TS_SDP1_SEL_TT1,
 425                 TS_SDP2_SEL_TT1, TS_SDP3_SEL_TT1,
 426         };
 427         static const u32 ts_sdp_sel_fc0[IGB_N_SDP] = {
 428                 TS_SDP0_SEL_FC0, TS_SDP1_SEL_FC0,
 429                 TS_SDP2_SEL_FC0, TS_SDP3_SEL_FC0,
 430         };
 431         static const u32 ts_sdp_sel_fc1[IGB_N_SDP] = {
 432                 TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1,
 433                 TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1,
 434         };
 435         static const u32 ts_sdp_sel_clr[IGB_N_SDP] = {
 436                 TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1,
 437                 TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1,
 438         };
 439         struct e1000_hw *hw = &igb->hw;
 440         u32 ctrl, ctrl_ext, tssdp = 0;
 441
 442         ctrl = rd32(E1000_CTRL);
 443         ctrl_ext = rd32(E1000_CTRL_EXT);
 444         tssdp = rd32(E1000_TSSDP);
 445
 446         igb_pin_direction(pin, 0, &ctrl, &ctrl_ext);
 447
 448         /* Make sure this pin is not enabled as an input. */
 449         if ((tssdp & AUX0_SEL_SDP3) == aux0_sel_sdp[pin])
 450                 tssdp &= ~AUX0_TS_SDP_EN;
 451
 452         if ((tssdp & AUX1_SEL_SDP3) == aux1_sel_sdp[pin])
 453                 tssdp &= ~AUX1_TS_SDP_EN;
 454
 455         tssdp &= ~ts_sdp_sel_clr[pin];
 456         if (freq) {
 457                 if (chan == 1)
 458                         tssdp |= ts_sdp_sel_fc1[pin];
 459                 else
 460                         tssdp |= ts_sdp_sel_fc0[pin];
 461         } else {
 462                 if (chan == 1)
 463                         tssdp |= ts_sdp_sel_tt1[pin];
 464                 else
 465                         tssdp |= ts_sdp_sel_tt0[pin];
 466         }
 467         tssdp |= ts_sdp_en[pin];
 468
 469         wr32(E1000_TSSDP, tssdp);
 470         wr32(E1000_CTRL, ctrl);
 471         wr32(E1000_CTRL_EXT, ctrl_ext);
 472 }
 473
 474 static int igb_ptp_feature_enable_i210(struct ptp_clock_info *ptp,
 475                                        struct ptp_clock_request *rq, int on)
 476 {
 477         struct igb_adapter *igb =
 478                 container_of(ptp, struct igb_adapter, ptp_caps);
 479         struct e1000_hw *hw = &igb->hw;
 480         u32 tsauxc, tsim, tsauxc_mask, tsim_mask, trgttiml, trgttimh, freqout;
 481         unsigned long flags;
 482         struct timespec64 ts;
 483         int use_freq = 0, pin = -1;
 484         s64 ns;
 485
 486         switch (rq->type) {
 487         case PTP_CLK_REQ_EXTTS:
 488                 if (on) {
 489                         pin = ptp_find_pin(igb->ptp_clock, PTP_PF_EXTTS,
 490                                            rq->extts.index);
 491                         if (pin < 0)
 492                                 return -EBUSY;
 493                 }
 494                 if (rq->extts.index == 1) {
 495                         tsauxc_mask = TSAUXC_EN_TS1;
 496                         tsim_mask = TSINTR_AUTT1;
 497                 } else {
 498                         tsauxc_mask = TSAUXC_EN_TS0;
 499                         tsim_mask = TSINTR_AUTT0;
 500                 }
 501                 spin_lock_irqsave(&igb->tmreg_lock, flags);
 502                 tsauxc = rd32(E1000_TSAUXC);
 503                 tsim = rd32(E1000_TSIM);
 504                 if (on) {
 505                         igb_pin_extts(igb, rq->extts.index, pin);
 506                         tsauxc |= tsauxc_mask;
 507                         tsim |= tsim_mask;
 508                 } else {
 509                         tsauxc &= ~tsauxc_mask;
 510                         tsim &= ~tsim_mask;
 511                 }
 512                 wr32(E1000_TSAUXC, tsauxc);
 513                 wr32(E1000_TSIM, tsim);
 514                 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
 515                 return 0;
 516
 517         case PTP_CLK_REQ_PEROUT:
 518                 if (on) {
 519                         pin = ptp_find_pin(igb->ptp_clock, PTP_PF_PEROUT,
 520                                            rq->perout.index);
 521                         if (pin < 0)
 522                                 return -EBUSY;
 523                 }
 524                 ts.tv_sec = rq->perout.period.sec;
 525                 ts.tv_nsec = rq->perout.period.nsec;
 526                 ns = timespec64_to_ns(&ts);
 527                 ns = ns >> 1;
 528                 if (on && ((ns <= 70000000LL) || (ns == 125000000LL) ||
 529                            (ns == 250000000LL) || (ns == 500000000LL))) {
 530                         if (ns < 8LL)
 531                                 return -EINVAL;
 532                         use_freq = 1;
 533                 }
 534                 ts = ns_to_timespec64(ns);
 535                 if (rq->perout.index == 1) {
 536                         if (use_freq) {
 537                                 tsauxc_mask = TSAUXC_EN_CLK1 | TSAUXC_ST1;
 538                                 tsim_mask = 0;
 539                         } else {
 540                                 tsauxc_mask = TSAUXC_EN_TT1;
 541                                 tsim_mask = TSINTR_TT1;
 542                         }
 543                         trgttiml = E1000_TRGTTIML1;
 544                         trgttimh = E1000_TRGTTIMH1;
 545                         freqout = E1000_FREQOUT1;
 546                 } else {
 547                         if (use_freq) {
 548                                 tsauxc_mask = TSAUXC_EN_CLK0 | TSAUXC_ST0;
 549                                 tsim_mask = 0;
 550                         } else {
 551                                 tsauxc_mask = TSAUXC_EN_TT0;
 552                                 tsim_mask = TSINTR_TT0;
 553                         }
 554                         trgttiml = E1000_TRGTTIML0;
 555                         trgttimh = E1000_TRGTTIMH0;
 556                         freqout = E1000_FREQOUT0;
 557                 }
 558                 spin_lock_irqsave(&igb->tmreg_lock, flags);
 559                 tsauxc = rd32(E1000_TSAUXC);
 560                 tsim = rd32(E1000_TSIM);
 561                 if (rq->perout.index == 1) {
 562                         tsauxc &= ~(TSAUXC_EN_TT1 | TSAUXC_EN_CLK1 | TSAUXC_ST1);
 563                         tsim &= ~TSINTR_TT1;
 564                 } else {
 565                         tsauxc &= ~(TSAUXC_EN_TT0 | TSAUXC_EN_CLK0 | TSAUXC_ST0);
 566                         tsim &= ~TSINTR_TT0;
 567                 }
 568                 if (on) {
 569                         int i = rq->perout.index;
 570                         igb_pin_perout(igb, i, pin, use_freq);
 571                         igb->perout[i].start.tv_sec = rq->perout.start.sec;
 572                         igb->perout[i].start.tv_nsec = rq->perout.start.nsec;
 573                         igb->perout[i].period.tv_sec = ts.tv_sec;
 574                         igb->perout[i].period.tv_nsec = ts.tv_nsec;
 575                         wr32(trgttimh, rq->perout.start.sec);
 576                         wr32(trgttiml, rq->perout.start.nsec);
 577                         if (use_freq)
 578                                 wr32(freqout, ns);
 579                         tsauxc |= tsauxc_mask;
 580                         tsim |= tsim_mask;
 581                 }
 582                 wr32(E1000_TSAUXC, tsauxc);
 583                 wr32(E1000_TSIM, tsim);
 584                 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
 585                 return 0;
 586
 587         case PTP_CLK_REQ_PPS:
 588                 spin_lock_irqsave(&igb->tmreg_lock, flags);
 589                 tsim = rd32(E1000_TSIM);
 590                 if (on)
 591                         tsim |= TSINTR_SYS_WRAP;
 592                 else
 593                         tsim &= ~TSINTR_SYS_WRAP;
 594                 wr32(E1000_TSIM, tsim);
 595                 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
 596                 return 0;
 597         }
 598
 599         return -EOPNOTSUPP;
 600 }
 601
 602 static int igb_ptp_feature_enable(struct ptp_clock_info *ptp,
 603                                   struct ptp_clock_request *rq, int on)
 604 {
 605         return -EOPNOTSUPP;
 606 }
 607
 608 static int igb_ptp_verify_pin(struct ptp_clock_info *ptp, unsigned int pin,
 609                               enum ptp_pin_function func, unsigned int chan)
 610 {
 611         switch (func) {
 612         case PTP_PF_NONE:
 613         case PTP_PF_EXTTS:
 614         case PTP_PF_PEROUT:
 615                 break;
 616         case PTP_PF_PHYSYNC:
 617                 return -1;
 618         }
 619         return 0;
 620 }
 621
 622 /**
 623  * igb_ptp_tx_work
 624  * @work: pointer to work struct
 625  *
 626  * This work function polls the TSYNCTXCTL valid bit to determine when a
 627  * timestamp has been taken for the current stored skb.
 628  **/
 629 static void igb_ptp_tx_work(struct work_struct *work)
 630 {
 631         struct igb_adapter *adapter = container_of(work, struct igb_adapter,
 632                                                    ptp_tx_work);
 633         struct e1000_hw *hw = &adapter->hw;
 634         u32 tsynctxctl;
 635
 636         if (!adapter->ptp_tx_skb)
 637                 return;
 638
 639         if (time_is_before_jiffies(adapter->ptp_tx_start +
 640                                    IGB_PTP_TX_TIMEOUT)) {
 641                 dev_kfree_skb_any(adapter->ptp_tx_skb);
 642                 adapter->ptp_tx_skb = NULL;
 643                 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
 644                 adapter->tx_hwtstamp_timeouts++;
 645                 dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n");
 646                 return;
 647         }
 648
 649         tsynctxctl = rd32(E1000_TSYNCTXCTL);
 650         if (tsynctxctl & E1000_TSYNCTXCTL_VALID)
 651                 igb_ptp_tx_hwtstamp(adapter);
 652         else
 653                 /* reschedule to check later */
 654                 schedule_work(&adapter->ptp_tx_work);
 655 }
 656
 657 static void igb_ptp_overflow_check(struct work_struct *work)
 658 {
 659         struct igb_adapter *igb =
 660                 container_of(work, struct igb_adapter, ptp_overflow_work.work);
 661         struct timespec64 ts;
 662
 663         igb->ptp_caps.gettime64(&igb->ptp_caps, &ts);
 664
 665         pr_debug("igb overflow check at %lld.%09lu\n",
 666                  (long long) ts.tv_sec, ts.tv_nsec);
 667
 668         schedule_delayed_work(&igb->ptp_overflow_work,
 669                               IGB_SYSTIM_OVERFLOW_PERIOD);
 670 }
 671
 672 /**
 673  * igb_ptp_rx_hang - detect error case when Rx timestamp registers latched
 674  * @adapter: private network adapter structure
 675  *
 676  * This watchdog task is scheduled to detect error case where hardware has
 677  * dropped an Rx packet that was timestamped when the ring is full. The
 678  * particular error is rare but leaves the device in a state unable to timestamp
 679  * any future packets.
 680  **/
 681 void igb_ptp_rx_hang(struct igb_adapter *adapter)
 682 {
 683         struct e1000_hw *hw = &adapter->hw;
 684         u32 tsyncrxctl = rd32(E1000_TSYNCRXCTL);
 685         unsigned long rx_event;
 686
 687         /* Other hardware uses per-packet timestamps */
 688         if (hw->mac.type != e1000_82576)
 689                 return;
 690
 691         /* If we don't have a valid timestamp in the registers, just update the
 692          * timeout counter and exit
 693          */
 694         if (!(tsyncrxctl & E1000_TSYNCRXCTL_VALID)) {
 695                 adapter->last_rx_ptp_check = jiffies;
 696                 return;
 697         }
 698
 699         /* Determine the most recent watchdog or rx_timestamp event */
 700         rx_event = adapter->last_rx_ptp_check;
 701         if (time_after(adapter->last_rx_timestamp, rx_event))
 702                 rx_event = adapter->last_rx_timestamp;
 703
 704         /* Only need to read the high RXSTMP register to clear the lock */
 705         if (time_is_before_jiffies(rx_event + 5 * HZ)) {
 706                 rd32(E1000_RXSTMPH);
 707                 adapter->last_rx_ptp_check = jiffies;
 708                 adapter->rx_hwtstamp_cleared++;
 709                 dev_warn(&adapter->pdev->dev, "clearing Rx timestamp hang\n");
 710         }
 711 }
 712
 713 /**
 714  * igb_ptp_tx_hwtstamp - utility function which checks for TX time stamp
 715  * @adapter: Board private structure.
 716  *
 717  * If we were asked to do hardware stamping and such a time stamp is
 718  * available, then it must have been for this skb here because we only
 719  * allow only one such packet into the queue.
 720  **/
 721 static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter)
 722 {
 723         struct e1000_hw *hw = &adapter->hw;
 724         struct skb_shared_hwtstamps shhwtstamps;
 725         u64 regval;
 726         int adjust = 0;
 727
 728         regval = rd32(E1000_TXSTMPL);
 729         regval |= (u64)rd32(E1000_TXSTMPH) << 32;
 730
 731         igb_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval);
 732         /* adjust timestamp for the TX latency based on link speed */
 733         if (adapter->hw.mac.type == e1000_i210) {
 734                 switch (adapter->link_speed) {
 735                 case SPEED_10:
 736                         adjust = IGB_I210_TX_LATENCY_10;
 737                         break;
 738                 case SPEED_100:
 739                         adjust = IGB_I210_TX_LATENCY_100;
 740                         break;
 741                 case SPEED_1000:
 742                         adjust = IGB_I210_TX_LATENCY_1000;
 743                         break;
 744                 }
 745         }
 746
 747         shhwtstamps.hwtstamp = ktime_sub_ns(shhwtstamps.hwtstamp, adjust);
 748
 749         skb_tstamp_tx(adapter->ptp_tx_skb, &shhwtstamps);
 750         dev_kfree_skb_any(adapter->ptp_tx_skb);
 751         adapter->ptp_tx_skb = NULL;
 752         clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
 753 }
 754
 755 /**
 756  * igb_ptp_rx_pktstamp - retrieve Rx per packet timestamp
 757  * @q_vector: Pointer to interrupt specific structure
 758  * @va: Pointer to address containing Rx buffer
 759  * @skb: Buffer containing timestamp and packet
 760  *
 761  * This function is meant to retrieve a timestamp from the first buffer of an
 762  * incoming frame.  The value is stored in little endian format starting on
 763  * byte 8.
 764  **/
 765 void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector,
 766                          unsigned char *va,
 767                          struct sk_buff *skb)
 768 {
 769         __le64 *regval = (__le64 *)va;
 770
 771         /* The timestamp is recorded in little endian format.
 772          * DWORD: 0        1        2        3
 773          * Field: Reserved Reserved SYSTIML  SYSTIMH
 774          */
 775         igb_ptp_systim_to_hwtstamp(q_vector->adapter, skb_hwtstamps(skb),
 776                                    le64_to_cpu(regval[1]));
 777 }
 778
 779 /**
 780  * igb_ptp_rx_rgtstamp - retrieve Rx timestamp stored in register
 781  * @q_vector: Pointer to interrupt specific structure
 782  * @skb: Buffer containing timestamp and packet
 783  *
 784  * This function is meant to retrieve a timestamp from the internal registers
 785  * of the adapter and store it in the skb.
 786  **/
 787 void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector,
 788                          struct sk_buff *skb)
 789 {
 790         struct igb_adapter *adapter = q_vector->adapter;
 791         struct e1000_hw *hw = &adapter->hw;
 792         u64 regval;
 793         int adjust = 0;
 794
 795         /* If this bit is set, then the RX registers contain the time stamp. No
 796          * other packet will be time stamped until we read these registers, so
 797          * read the registers to make them available again. Because only one
 798          * packet can be time stamped at a time, we know that the register
 799          * values must belong to this one here and therefore we don't need to
 800          * compare any of the additional attributes stored for it.
 801          *
 802          * If nothing went wrong, then it should have a shared tx_flags that we
 803          * can turn into a skb_shared_hwtstamps.
 804          */
 805         if (!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
 806                 return;
 807
 808         regval = rd32(E1000_RXSTMPL);
 809         regval |= (u64)rd32(E1000_RXSTMPH) << 32;
 810
 811         igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
 812
 813         /* adjust timestamp for the RX latency based on link speed */
 814         if (adapter->hw.mac.type == e1000_i210) {
 815                 switch (adapter->link_speed) {
 816                 case SPEED_10:
 817                         adjust = IGB_I210_RX_LATENCY_10;
 818                         break;
 819                 case SPEED_100:
 820                         adjust = IGB_I210_RX_LATENCY_100;
 821                         break;
 822                 case SPEED_1000:
 823                         adjust = IGB_I210_RX_LATENCY_1000;
 824                         break;
 825                 }
 826         }
 827         skb_hwtstamps(skb)->hwtstamp =
 828                 ktime_add_ns(skb_hwtstamps(skb)->hwtstamp, adjust);
 829
 830         /* Update the last_rx_timestamp timer in order to enable watchdog check
 831          * for error case of latched timestamp on a dropped packet.
 832          */
 833         adapter->last_rx_timestamp = jiffies;
 834 }
 835
 836 /**
 837  * igb_ptp_get_ts_config - get hardware time stamping config
 838  * @netdev:
 839  * @ifreq:
 840  *
 841  * Get the hwtstamp_config settings to return to the user. Rather than attempt
 842  * to deconstruct the settings from the registers, just return a shadow copy
 843  * of the last known settings.
 844  **/
 845 int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr)
 846 {
 847         struct igb_adapter *adapter = netdev_priv(netdev);
 848         struct hwtstamp_config *config = &adapter->tstamp_config;
 849
 850         return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
 851                 -EFAULT : 0;
 852 }
 853
 854 /**
 855  * igb_ptp_set_timestamp_mode - setup hardware for timestamping
 856  * @adapter: networking device structure
 857  * @config: hwtstamp configuration
 858  *
 859  * Outgoing time stamping can be enabled and disabled. Play nice and
 860  * disable it when requested, although it shouldn't case any overhead
 861  * when no packet needs it. At most one packet in the queue may be
 862  * marked for time stamping, otherwise it would be impossible to tell
 863  * for sure to which packet the hardware time stamp belongs.
 864  *
 865  * Incoming time stamping has to be configured via the hardware
 866  * filters. Not all combinations are supported, in particular event
 867  * type has to be specified. Matching the kind of event packet is
 868  * not supported, with the exception of "all V2 events regardless of
 869  * level 2 or 4".
 870  */
 871 static int igb_ptp_set_timestamp_mode(struct igb_adapter *adapter,
 872                                       struct hwtstamp_config *config)
 873 {
 874         struct e1000_hw *hw = &adapter->hw;
 875         u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
 876         u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
 877         u32 tsync_rx_cfg = 0;
 878         bool is_l4 = false;
 879         bool is_l2 = false;
 880         u32 regval;
 881
 882         /* reserved for future extensions */
 883         if (config->flags)
 884                 return -EINVAL;
 885
 886         switch (config->tx_type) {
 887         case HWTSTAMP_TX_OFF:
 888                 tsync_tx_ctl = 0;
 889         case HWTSTAMP_TX_ON:
 890                 break;
 891         default:
 892                 return -ERANGE;
 893         }
 894
 895         switch (config->rx_filter) {
 896         case HWTSTAMP_FILTER_NONE:
 897                 tsync_rx_ctl = 0;
 898                 break;
 899         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 900                 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
 901                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
 902                 is_l4 = true;
 903                 break;
 904         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 905                 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
 906                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
 907                 is_l4 = true;
 908                 break;
 909         case HWTSTAMP_FILTER_PTP_V2_EVENT:
 910         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
 911         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 912         case HWTSTAMP_FILTER_PTP_V2_SYNC:
 913         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
 914         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 915         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 916         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
 917         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 918                 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
 919                 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
 920                 is_l2 = true;
 921                 is_l4 = true;
 922                 break;
 923         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 924         case HWTSTAMP_FILTER_ALL:
 925                 /* 82576 cannot timestamp all packets, which it needs to do to
 926                  * support both V1 Sync and Delay_Req messages
 927                  */
 928                 if (hw->mac.type != e1000_82576) {
 929                         tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
 930                         config->rx_filter = HWTSTAMP_FILTER_ALL;
 931                         break;
 932                 }
 933                 /* fall through */
 934         default:
 935                 config->rx_filter = HWTSTAMP_FILTER_NONE;
 936                 return -ERANGE;
 937         }
 938
 939         if (hw->mac.type == e1000_82575) {
 940                 if (tsync_rx_ctl | tsync_tx_ctl)
 941                         return -EINVAL;
 942                 return 0;
 943         }
 944
 945         /* Per-packet timestamping only works if all packets are
 946          * timestamped, so enable timestamping in all packets as
 947          * long as one Rx filter was configured.
 948          */
 949         if ((hw->mac.type >= e1000_82580) && tsync_rx_ctl) {
 950                 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
 951                 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
 952                 config->rx_filter = HWTSTAMP_FILTER_ALL;
 953                 is_l2 = true;
 954                 is_l4 = true;
 955
 956                 if ((hw->mac.type == e1000_i210) ||
 957                     (hw->mac.type == e1000_i211)) {
 958                         regval = rd32(E1000_RXPBS);
 959                         regval |= E1000_RXPBS_CFG_TS_EN;
 960                         wr32(E1000_RXPBS, regval);
 961                 }
 962         }
 963
 964         /* enable/disable TX */
 965         regval = rd32(E1000_TSYNCTXCTL);
 966         regval &= ~E1000_TSYNCTXCTL_ENABLED;
 967         regval |= tsync_tx_ctl;
 968         wr32(E1000_TSYNCTXCTL, regval);
 969
 970         /* enable/disable RX */
 971         regval = rd32(E1000_TSYNCRXCTL);
 972         regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
 973         regval |= tsync_rx_ctl;
 974         wr32(E1000_TSYNCRXCTL, regval);
 975
 976         /* define which PTP packets are time stamped */
 977         wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
 978
 979         /* define ethertype filter for timestamped packets */
 980         if (is_l2)
 981                 wr32(E1000_ETQF(3),
 982                      (E1000_ETQF_FILTER_ENABLE | /* enable filter */
 983                       E1000_ETQF_1588 | /* enable timestamping */
 984                       ETH_P_1588));     /* 1588 eth protocol type */
 985         else
 986                 wr32(E1000_ETQF(3), 0);
 987
 988         /* L4 Queue Filter[3]: filter by destination port and protocol */
 989         if (is_l4) {
 990                 u32 ftqf = (IPPROTO_UDP /* UDP */
 991                         | E1000_FTQF_VF_BP /* VF not compared */
 992                         | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */
 993                         | E1000_FTQF_MASK); /* mask all inputs */
 994                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */
 995
 996                 wr32(E1000_IMIR(3), htons(PTP_EV_PORT));
 997                 wr32(E1000_IMIREXT(3),
 998                      (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP));
 999                 if (hw->mac.type == e1000_82576) {
1000                         /* enable source port check */
1001                         wr32(E1000_SPQF(3), htons(PTP_EV_PORT));
1002                         ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
1003                 }
1004                 wr32(E1000_FTQF(3), ftqf);
1005         } else {
1006                 wr32(E1000_FTQF(3), E1000_FTQF_MASK);
1007         }
1008         wrfl();
1009
1010         /* clear TX/RX time stamp registers, just to be sure */
1011         regval = rd32(E1000_TXSTMPL);
1012         regval = rd32(E1000_TXSTMPH);
1013         regval = rd32(E1000_RXSTMPL);
1014         regval = rd32(E1000_RXSTMPH);
1015
1016         return 0;
1017 }
1018
1019 /**
1020  * igb_ptp_set_ts_config - set hardware time stamping config
1021  * @netdev:
1022  * @ifreq:
1023  *
1024  **/
1025 int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr)
1026 {
1027         struct igb_adapter *adapter = netdev_priv(netdev);
1028         struct hwtstamp_config config;
1029         int err;
1030
1031         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
1032                 return -EFAULT;
1033
1034         err = igb_ptp_set_timestamp_mode(adapter, &config);
1035         if (err)
1036                 return err;
1037
1038         /* save these settings for future reference */
1039         memcpy(&adapter->tstamp_config, &config,
1040                sizeof(adapter->tstamp_config));
1041
1042         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1043                 -EFAULT : 0;
1044 }
1045
1046 /**
1047  * igb_ptp_init - Initialize PTP functionality
1048  * @adapter: Board private structure
1049  *
1050  * This function is called at device probe to initialize the PTP
1051  * functionality.
1052  */
1053 void igb_ptp_init(struct igb_adapter *adapter)
1054 {
1055         struct e1000_hw *hw = &adapter->hw;
1056         struct net_device *netdev = adapter->netdev;
1057         int i;
1058
1059         switch (hw->mac.type) {
1060         case e1000_82576:
1061                 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1062                 adapter->ptp_caps.owner = THIS_MODULE;
1063                 adapter->ptp_caps.max_adj = 999999881;
1064                 adapter->ptp_caps.n_ext_ts = 0;
1065                 adapter->ptp_caps.pps = 0;
1066                 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82576;
1067                 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576;
1068                 adapter->ptp_caps.gettime64 = igb_ptp_gettime_82576;
1069                 adapter->ptp_caps.settime64 = igb_ptp_settime_82576;
1070                 adapter->ptp_caps.enable = igb_ptp_feature_enable;
1071                 adapter->cc.read = igb_ptp_read_82576;
1072                 adapter->cc.mask = CYCLECOUNTER_MASK(64);
1073                 adapter->cc.mult = 1;
1074                 adapter->cc.shift = IGB_82576_TSYNC_SHIFT;
1075                 adapter->ptp_flags |= IGB_PTP_OVERFLOW_CHECK;
1076                 break;
1077         case e1000_82580:
1078         case e1000_i354:
1079         case e1000_i350:
1080                 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1081                 adapter->ptp_caps.owner = THIS_MODULE;
1082                 adapter->ptp_caps.max_adj = 62499999;
1083                 adapter->ptp_caps.n_ext_ts = 0;
1084                 adapter->ptp_caps.pps = 0;
1085                 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580;
1086                 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576;
1087                 adapter->ptp_caps.gettime64 = igb_ptp_gettime_82576;
1088                 adapter->ptp_caps.settime64 = igb_ptp_settime_82576;
1089                 adapter->ptp_caps.enable = igb_ptp_feature_enable;
1090                 adapter->cc.read = igb_ptp_read_82580;
1091                 adapter->cc.mask = CYCLECOUNTER_MASK(IGB_NBITS_82580);
1092                 adapter->cc.mult = 1;
1093                 adapter->cc.shift = 0;
1094                 adapter->ptp_flags |= IGB_PTP_OVERFLOW_CHECK;
1095                 break;
1096         case e1000_i210:
1097         case e1000_i211:
1098                 for (i = 0; i < IGB_N_SDP; i++) {
1099                         struct ptp_pin_desc *ppd = &adapter->sdp_config[i];
1100
1101                         snprintf(ppd->name, sizeof(ppd->name), "SDP%d", i);
1102                         ppd->index = i;
1103                         ppd->func = PTP_PF_NONE;
1104                 }
1105                 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1106                 adapter->ptp_caps.owner = THIS_MODULE;
1107                 adapter->ptp_caps.max_adj = 62499999;
1108                 adapter->ptp_caps.n_ext_ts = IGB_N_EXTTS;
1109                 adapter->ptp_caps.n_per_out = IGB_N_PEROUT;
1110                 adapter->ptp_caps.n_pins = IGB_N_SDP;
1111                 adapter->ptp_caps.pps = 1;
1112                 adapter->ptp_caps.pin_config = adapter->sdp_config;
1113                 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580;
1114                 adapter->ptp_caps.adjtime = igb_ptp_adjtime_i210;
1115                 adapter->ptp_caps.gettime64 = igb_ptp_gettime_i210;
1116                 adapter->ptp_caps.settime64 = igb_ptp_settime_i210;
1117                 adapter->ptp_caps.enable = igb_ptp_feature_enable_i210;
1118                 adapter->ptp_caps.verify = igb_ptp_verify_pin;
1119                 break;
1120         default:
1121                 adapter->ptp_clock = NULL;
1122                 return;
1123         }
1124
1125         spin_lock_init(&adapter->tmreg_lock);
1126         INIT_WORK(&adapter->ptp_tx_work, igb_ptp_tx_work);
1127
1128         if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK)
1129                 INIT_DELAYED_WORK(&adapter->ptp_overflow_work,
1130                                   igb_ptp_overflow_check);
1131
1132         adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
1133         adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
1134
1135         igb_ptp_reset(adapter);
1136
1137         adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
1138                                                 &adapter->pdev->dev);
1139         if (IS_ERR(adapter->ptp_clock)) {
1140                 adapter->ptp_clock = NULL;
1141                 dev_err(&adapter->pdev->dev, "ptp_clock_register failed\n");
1142         } else {
1143                 dev_info(&adapter->pdev->dev, "added PHC on %s\n",
1144                          adapter->netdev->name);
1145                 adapter->ptp_flags |= IGB_PTP_ENABLED;
1146         }
1147 }
1148
1149 /**
1150  * igb_ptp_suspend - Disable PTP work items and prepare for suspend
1151  * @adapter: Board private structure
1152  *
1153  * This function stops the overflow check work and PTP Tx timestamp work, and
1154  * will prepare the device for OS suspend.
1155  */
1156 void igb_ptp_suspend(struct igb_adapter *adapter)
1157 {
1158         if (!(adapter->ptp_flags & IGB_PTP_ENABLED))
1159                 return;
1160
1161         if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK)
1162                 cancel_delayed_work_sync(&adapter->ptp_overflow_work);
1163
1164         cancel_work_sync(&adapter->ptp_tx_work);
1165         if (adapter->ptp_tx_skb) {
1166                 dev_kfree_skb_any(adapter->ptp_tx_skb);
1167                 adapter->ptp_tx_skb = NULL;
1168                 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
1169         }
1170 }
1171
1172 /**
1173  * igb_ptp_stop - Disable PTP device and stop the overflow check.
1174  * @adapter: Board private structure.
1175  *
1176  * This function stops the PTP support and cancels the delayed work.
1177  **/
1178 void igb_ptp_stop(struct igb_adapter *adapter)
1179 {
1180         igb_ptp_suspend(adapter);
1181
1182         if (adapter->ptp_clock) {
1183                 ptp_clock_unregister(adapter->ptp_clock);
1184                 dev_info(&adapter->pdev->dev, "removed PHC on %s\n",
1185                          adapter->netdev->name);
1186                 adapter->ptp_flags &= ~IGB_PTP_ENABLED;
1187         }
1188 }
1189
1190 /**
1191  * igb_ptp_reset - Re-enable the adapter for PTP following a reset.
1192  * @adapter: Board private structure.
1193  *
1194  * This function handles the reset work required to re-enable the PTP device.
1195  **/
1196 void igb_ptp_reset(struct igb_adapter *adapter)
1197 {
1198         struct e1000_hw *hw = &adapter->hw;
1199         unsigned long flags;
1200
1201         /* reset the tstamp_config */
1202         igb_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config);
1203
1204         spin_lock_irqsave(&adapter->tmreg_lock, flags);
1205
1206         switch (adapter->hw.mac.type) {
1207         case e1000_82576:
1208                 /* Dial the nominal frequency. */
1209                 wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576);
1210                 break;
1211         case e1000_82580:
1212         case e1000_i354:
1213         case e1000_i350:
1214         case e1000_i210:
1215         case e1000_i211:
1216                 wr32(E1000_TSAUXC, 0x0);
1217                 wr32(E1000_TSSDP, 0x0);
1218                 wr32(E1000_TSIM, TSYNC_INTERRUPTS);
1219                 wr32(E1000_IMS, E1000_IMS_TS);
1220                 break;
1221         default:
1222                 /* No work to do. */
1223                 goto out;
1224         }
1225
1226         /* Re-initialize the timer. */
1227         if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) {
1228                 struct timespec64 ts = ktime_to_timespec64(ktime_get_real());
1229
1230                 igb_ptp_write_i210(adapter, &ts);
1231         } else {
1232                 timecounter_init(&adapter->tc, &adapter->cc,
1233                                  ktime_to_ns(ktime_get_real()));
1234         }
1235 out:
1236         spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
1237
1238         wrfl();
1239
1240         if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK)
1241                 schedule_delayed_work(&adapter->ptp_overflow_work,
1242                                       IGB_SYSTIM_OVERFLOW_PERIOD);
1243 }