1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
35 #include <linux/interrupt.h>
37 #include <linux/tcp.h>
38 #include <linux/sctp.h>
39 #include <linux/pkt_sched.h>
40 #include <linux/ipv6.h>
41 #include <linux/slab.h>
42 #include <net/checksum.h>
43 #include <net/ip6_checksum.h>
44 #include <linux/ethtool.h>
46 #include <linux/if_vlan.h>
47 #include <linux/if_bridge.h>
48 #include <linux/prefetch.h>
49 #include <scsi/fc/fc_fcoe.h>
52 #include "ixgbe_common.h"
53 #include "ixgbe_dcb_82599.h"
54 #include "ixgbe_sriov.h"
56 char ixgbe_driver_name[] = "ixgbe";
57 static const char ixgbe_driver_string[] =
58 "Intel(R) 10 Gigabit PCI Express Network Driver";
60 char ixgbe_default_device_descr[] =
61 "Intel(R) 10 Gigabit Network Connection";
63 static char ixgbe_default_device_descr[] =
64 "Intel(R) 10 Gigabit Network Connection";
66 #define DRV_VERSION "3.15.1-k"
67 const char ixgbe_driver_version[] = DRV_VERSION;
68 static const char ixgbe_copyright[] =
69 "Copyright (c) 1999-2013 Intel Corporation.";
71 static const struct ixgbe_info *ixgbe_info_tbl[] = {
72 [board_82598] = &ixgbe_82598_info,
73 [board_82599] = &ixgbe_82599_info,
74 [board_X540] = &ixgbe_X540_info,
77 /* ixgbe_pci_tbl - PCI Device ID Table
79 * Wildcard entries (PCI_ANY_ID) should come last
80 * Last entry must be all 0s
82 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
83 * Class, Class Mask, private data (not used) }
85 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
116 /* required last entry */
119 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
121 #ifdef CONFIG_IXGBE_DCA
122 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
124 static struct notifier_block dca_notifier = {
125 .notifier_call = ixgbe_notify_dca,
131 #ifdef CONFIG_PCI_IOV
132 static unsigned int max_vfs;
133 module_param(max_vfs, uint, 0);
134 MODULE_PARM_DESC(max_vfs,
135 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63");
136 #endif /* CONFIG_PCI_IOV */
138 static unsigned int allow_unsupported_sfp;
139 module_param(allow_unsupported_sfp, uint, 0);
140 MODULE_PARM_DESC(allow_unsupported_sfp,
141 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
143 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
144 static int debug = -1;
145 module_param(debug, int, 0);
146 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
148 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
149 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
150 MODULE_LICENSE("GPL");
151 MODULE_VERSION(DRV_VERSION);
153 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
156 struct pci_dev *parent_dev;
157 struct pci_bus *parent_bus;
159 parent_bus = adapter->pdev->bus->parent;
163 parent_dev = parent_bus->self;
167 if (!pci_is_pcie(parent_dev))
170 pcie_capability_read_word(parent_dev, reg, value);
174 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
176 struct ixgbe_hw *hw = &adapter->hw;
180 hw->bus.type = ixgbe_bus_type_pci_express;
182 /* Get the negotiated link width and speed from PCI config space of the
183 * parent, as this device is behind a switch
185 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
187 /* assume caller will handle error case */
191 hw->bus.width = ixgbe_convert_bus_width(link_status);
192 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
198 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
199 * @hw: hw specific details
201 * This function is used by probe to determine whether a device's PCI-Express
202 * bandwidth details should be gathered from the parent bus instead of from the
203 * device. Used to ensure that various locations all have the correct device ID
206 static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
208 switch (hw->device_id) {
209 case IXGBE_DEV_ID_82599_SFP_SF_QP:
210 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
217 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
221 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
222 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
223 struct pci_dev *pdev;
225 /* determine whether to use the the parent device
227 if (ixgbe_pcie_from_parent(&adapter->hw))
228 pdev = adapter->pdev->bus->parent->self;
230 pdev = adapter->pdev;
232 if (pcie_get_minimum_link(pdev, &speed, &width) ||
233 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
234 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
239 case PCIE_SPEED_2_5GT:
240 /* 8b/10b encoding reduces max throughput by 20% */
243 case PCIE_SPEED_5_0GT:
244 /* 8b/10b encoding reduces max throughput by 20% */
247 case PCIE_SPEED_8_0GT:
248 /* 128b/130b encoding reduces throughput by less than 2% */
252 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
256 e_dev_info("PCI Express bandwidth of %dGT/s available\n",
258 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n",
259 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
260 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
261 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
264 (speed == PCIE_SPEED_2_5GT ? "20%" :
265 speed == PCIE_SPEED_5_0GT ? "20%" :
266 speed == PCIE_SPEED_8_0GT ? "<2%" :
269 if (max_gts < expected_gts) {
270 e_dev_warn("This is not sufficient for optimal performance of this card.\n");
271 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n",
273 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n");
277 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
279 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
280 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
281 schedule_work(&adapter->service_task);
284 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
286 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
288 /* flush memory to make sure state is correct before next watchdog */
289 smp_mb__before_clear_bit();
290 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
293 struct ixgbe_reg_info {
298 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
300 /* General Registers */
301 {IXGBE_CTRL, "CTRL"},
302 {IXGBE_STATUS, "STATUS"},
303 {IXGBE_CTRL_EXT, "CTRL_EXT"},
305 /* Interrupt Registers */
306 {IXGBE_EICR, "EICR"},
309 {IXGBE_SRRCTL(0), "SRRCTL"},
310 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
311 {IXGBE_RDLEN(0), "RDLEN"},
312 {IXGBE_RDH(0), "RDH"},
313 {IXGBE_RDT(0), "RDT"},
314 {IXGBE_RXDCTL(0), "RXDCTL"},
315 {IXGBE_RDBAL(0), "RDBAL"},
316 {IXGBE_RDBAH(0), "RDBAH"},
319 {IXGBE_TDBAL(0), "TDBAL"},
320 {IXGBE_TDBAH(0), "TDBAH"},
321 {IXGBE_TDLEN(0), "TDLEN"},
322 {IXGBE_TDH(0), "TDH"},
323 {IXGBE_TDT(0), "TDT"},
324 {IXGBE_TXDCTL(0), "TXDCTL"},
326 /* List Terminator */
332 * ixgbe_regdump - register printout routine
334 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
340 switch (reginfo->ofs) {
341 case IXGBE_SRRCTL(0):
342 for (i = 0; i < 64; i++)
343 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
345 case IXGBE_DCA_RXCTRL(0):
346 for (i = 0; i < 64; i++)
347 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
350 for (i = 0; i < 64; i++)
351 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
354 for (i = 0; i < 64; i++)
355 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
358 for (i = 0; i < 64; i++)
359 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
361 case IXGBE_RXDCTL(0):
362 for (i = 0; i < 64; i++)
363 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
366 for (i = 0; i < 64; i++)
367 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
370 for (i = 0; i < 64; i++)
371 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
374 for (i = 0; i < 64; i++)
375 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
378 for (i = 0; i < 64; i++)
379 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
382 for (i = 0; i < 64; i++)
383 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
386 for (i = 0; i < 64; i++)
387 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
390 for (i = 0; i < 64; i++)
391 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
393 case IXGBE_TXDCTL(0):
394 for (i = 0; i < 64; i++)
395 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
398 pr_info("%-15s %08x\n", reginfo->name,
399 IXGBE_READ_REG(hw, reginfo->ofs));
403 for (i = 0; i < 8; i++) {
404 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
405 pr_err("%-15s", rname);
406 for (j = 0; j < 8; j++)
407 pr_cont(" %08x", regs[i*8+j]);
414 * ixgbe_dump - Print registers, tx-rings and rx-rings
416 static void ixgbe_dump(struct ixgbe_adapter *adapter)
418 struct net_device *netdev = adapter->netdev;
419 struct ixgbe_hw *hw = &adapter->hw;
420 struct ixgbe_reg_info *reginfo;
422 struct ixgbe_ring *tx_ring;
423 struct ixgbe_tx_buffer *tx_buffer;
424 union ixgbe_adv_tx_desc *tx_desc;
425 struct my_u0 { u64 a; u64 b; } *u0;
426 struct ixgbe_ring *rx_ring;
427 union ixgbe_adv_rx_desc *rx_desc;
428 struct ixgbe_rx_buffer *rx_buffer_info;
432 if (!netif_msg_hw(adapter))
435 /* Print netdevice Info */
437 dev_info(&adapter->pdev->dev, "Net device Info\n");
438 pr_info("Device Name state "
439 "trans_start last_rx\n");
440 pr_info("%-15s %016lX %016lX %016lX\n",
447 /* Print Registers */
448 dev_info(&adapter->pdev->dev, "Register Dump\n");
449 pr_info(" Register Name Value\n");
450 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
451 reginfo->name; reginfo++) {
452 ixgbe_regdump(hw, reginfo);
455 /* Print TX Ring Summary */
456 if (!netdev || !netif_running(netdev))
459 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
460 pr_info(" %s %s %s %s\n",
461 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
462 "leng", "ntw", "timestamp");
463 for (n = 0; n < adapter->num_tx_queues; n++) {
464 tx_ring = adapter->tx_ring[n];
465 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
466 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
467 n, tx_ring->next_to_use, tx_ring->next_to_clean,
468 (u64)dma_unmap_addr(tx_buffer, dma),
469 dma_unmap_len(tx_buffer, len),
470 tx_buffer->next_to_watch,
471 (u64)tx_buffer->time_stamp);
475 if (!netif_msg_tx_done(adapter))
476 goto rx_ring_summary;
478 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
480 /* Transmit Descriptor Formats
482 * 82598 Advanced Transmit Descriptor
483 * +--------------------------------------------------------------+
484 * 0 | Buffer Address [63:0] |
485 * +--------------------------------------------------------------+
486 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
487 * +--------------------------------------------------------------+
488 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
490 * 82598 Advanced Transmit Descriptor (Write-Back Format)
491 * +--------------------------------------------------------------+
493 * +--------------------------------------------------------------+
494 * 8 | RSV | STA | NXTSEQ |
495 * +--------------------------------------------------------------+
498 * 82599+ Advanced Transmit Descriptor
499 * +--------------------------------------------------------------+
500 * 0 | Buffer Address [63:0] |
501 * +--------------------------------------------------------------+
502 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
503 * +--------------------------------------------------------------+
504 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
506 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
507 * +--------------------------------------------------------------+
509 * +--------------------------------------------------------------+
510 * 8 | RSV | STA | RSV |
511 * +--------------------------------------------------------------+
515 for (n = 0; n < adapter->num_tx_queues; n++) {
516 tx_ring = adapter->tx_ring[n];
517 pr_info("------------------------------------\n");
518 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
519 pr_info("------------------------------------\n");
520 pr_info("%s%s %s %s %s %s\n",
521 "T [desc] [address 63:0 ] ",
522 "[PlPOIdStDDt Ln] [bi->dma ] ",
523 "leng", "ntw", "timestamp", "bi->skb");
525 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
526 tx_desc = IXGBE_TX_DESC(tx_ring, i);
527 tx_buffer = &tx_ring->tx_buffer_info[i];
528 u0 = (struct my_u0 *)tx_desc;
529 if (dma_unmap_len(tx_buffer, len) > 0) {
530 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
534 (u64)dma_unmap_addr(tx_buffer, dma),
535 dma_unmap_len(tx_buffer, len),
536 tx_buffer->next_to_watch,
537 (u64)tx_buffer->time_stamp,
539 if (i == tx_ring->next_to_use &&
540 i == tx_ring->next_to_clean)
542 else if (i == tx_ring->next_to_use)
544 else if (i == tx_ring->next_to_clean)
549 if (netif_msg_pktdata(adapter) &&
551 print_hex_dump(KERN_INFO, "",
552 DUMP_PREFIX_ADDRESS, 16, 1,
553 tx_buffer->skb->data,
554 dma_unmap_len(tx_buffer, len),
560 /* Print RX Rings Summary */
562 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
563 pr_info("Queue [NTU] [NTC]\n");
564 for (n = 0; n < adapter->num_rx_queues; n++) {
565 rx_ring = adapter->rx_ring[n];
566 pr_info("%5d %5X %5X\n",
567 n, rx_ring->next_to_use, rx_ring->next_to_clean);
571 if (!netif_msg_rx_status(adapter))
574 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
576 /* Receive Descriptor Formats
578 * 82598 Advanced Receive Descriptor (Read) Format
580 * +-----------------------------------------------------+
581 * 0 | Packet Buffer Address [63:1] |A0/NSE|
582 * +----------------------------------------------+------+
583 * 8 | Header Buffer Address [63:1] | DD |
584 * +-----------------------------------------------------+
587 * 82598 Advanced Receive Descriptor (Write-Back) Format
589 * 63 48 47 32 31 30 21 20 16 15 4 3 0
590 * +------------------------------------------------------+
591 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
592 * | Packet | IP | | | | Type | Type |
593 * | Checksum | Ident | | | | | |
594 * +------------------------------------------------------+
595 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
596 * +------------------------------------------------------+
597 * 63 48 47 32 31 20 19 0
599 * 82599+ Advanced Receive Descriptor (Read) Format
601 * +-----------------------------------------------------+
602 * 0 | Packet Buffer Address [63:1] |A0/NSE|
603 * +----------------------------------------------+------+
604 * 8 | Header Buffer Address [63:1] | DD |
605 * +-----------------------------------------------------+
608 * 82599+ Advanced Receive Descriptor (Write-Back) Format
610 * 63 48 47 32 31 30 21 20 17 16 4 3 0
611 * +------------------------------------------------------+
612 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
613 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
614 * |/ Flow Dir Flt ID | | | | | |
615 * +------------------------------------------------------+
616 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
617 * +------------------------------------------------------+
618 * 63 48 47 32 31 20 19 0
621 for (n = 0; n < adapter->num_rx_queues; n++) {
622 rx_ring = adapter->rx_ring[n];
623 pr_info("------------------------------------\n");
624 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
625 pr_info("------------------------------------\n");
627 "R [desc] [ PktBuf A0] ",
628 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
629 "<-- Adv Rx Read format\n");
631 "RWB[desc] [PcsmIpSHl PtRs] ",
632 "[vl er S cks ln] ---------------- [bi->skb ] ",
633 "<-- Adv Rx Write-Back format\n");
635 for (i = 0; i < rx_ring->count; i++) {
636 rx_buffer_info = &rx_ring->rx_buffer_info[i];
637 rx_desc = IXGBE_RX_DESC(rx_ring, i);
638 u0 = (struct my_u0 *)rx_desc;
639 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
640 if (staterr & IXGBE_RXD_STAT_DD) {
641 /* Descriptor Done */
642 pr_info("RWB[0x%03X] %016llX "
643 "%016llX ---------------- %p", i,
646 rx_buffer_info->skb);
648 pr_info("R [0x%03X] %016llX "
649 "%016llX %016llX %p", i,
652 (u64)rx_buffer_info->dma,
653 rx_buffer_info->skb);
655 if (netif_msg_pktdata(adapter) &&
656 rx_buffer_info->dma) {
657 print_hex_dump(KERN_INFO, "",
658 DUMP_PREFIX_ADDRESS, 16, 1,
659 page_address(rx_buffer_info->page) +
660 rx_buffer_info->page_offset,
661 ixgbe_rx_bufsz(rx_ring), true);
665 if (i == rx_ring->next_to_use)
667 else if (i == rx_ring->next_to_clean)
679 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
683 /* Let firmware take over control of h/w */
684 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
685 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
686 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
689 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
693 /* Let firmware know the driver has taken over */
694 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
695 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
696 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
700 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
701 * @adapter: pointer to adapter struct
702 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
703 * @queue: queue to map the corresponding interrupt to
704 * @msix_vector: the vector to map to the corresponding queue
707 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
708 u8 queue, u8 msix_vector)
711 struct ixgbe_hw *hw = &adapter->hw;
712 switch (hw->mac.type) {
713 case ixgbe_mac_82598EB:
714 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
717 index = (((direction * 64) + queue) >> 2) & 0x1F;
718 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
719 ivar &= ~(0xFF << (8 * (queue & 0x3)));
720 ivar |= (msix_vector << (8 * (queue & 0x3)));
721 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
723 case ixgbe_mac_82599EB:
725 if (direction == -1) {
727 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
728 index = ((queue & 1) * 8);
729 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
730 ivar &= ~(0xFF << index);
731 ivar |= (msix_vector << index);
732 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
735 /* tx or rx causes */
736 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
737 index = ((16 * (queue & 1)) + (8 * direction));
738 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
739 ivar &= ~(0xFF << index);
740 ivar |= (msix_vector << index);
741 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
749 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
754 switch (adapter->hw.mac.type) {
755 case ixgbe_mac_82598EB:
756 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
757 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
759 case ixgbe_mac_82599EB:
761 mask = (qmask & 0xFFFFFFFF);
762 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
763 mask = (qmask >> 32);
764 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
771 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
772 struct ixgbe_tx_buffer *tx_buffer)
774 if (tx_buffer->skb) {
775 dev_kfree_skb_any(tx_buffer->skb);
776 if (dma_unmap_len(tx_buffer, len))
777 dma_unmap_single(ring->dev,
778 dma_unmap_addr(tx_buffer, dma),
779 dma_unmap_len(tx_buffer, len),
781 } else if (dma_unmap_len(tx_buffer, len)) {
782 dma_unmap_page(ring->dev,
783 dma_unmap_addr(tx_buffer, dma),
784 dma_unmap_len(tx_buffer, len),
787 tx_buffer->next_to_watch = NULL;
788 tx_buffer->skb = NULL;
789 dma_unmap_len_set(tx_buffer, len, 0);
790 /* tx_buffer must be completely set up in the transmit path */
793 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
795 struct ixgbe_hw *hw = &adapter->hw;
796 struct ixgbe_hw_stats *hwstats = &adapter->stats;
800 if ((hw->fc.current_mode != ixgbe_fc_full) &&
801 (hw->fc.current_mode != ixgbe_fc_rx_pause))
804 switch (hw->mac.type) {
805 case ixgbe_mac_82598EB:
806 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
809 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
811 hwstats->lxoffrxc += data;
813 /* refill credits (no tx hang) if we received xoff */
817 for (i = 0; i < adapter->num_tx_queues; i++)
818 clear_bit(__IXGBE_HANG_CHECK_ARMED,
819 &adapter->tx_ring[i]->state);
822 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
824 struct ixgbe_hw *hw = &adapter->hw;
825 struct ixgbe_hw_stats *hwstats = &adapter->stats;
829 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
831 if (adapter->ixgbe_ieee_pfc)
832 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
834 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
835 ixgbe_update_xoff_rx_lfc(adapter);
839 /* update stats for each tc, only valid with PFC enabled */
840 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
843 switch (hw->mac.type) {
844 case ixgbe_mac_82598EB:
845 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
848 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
850 hwstats->pxoffrxc[i] += pxoffrxc;
851 /* Get the TC for given UP */
852 tc = netdev_get_prio_tc_map(adapter->netdev, i);
853 xoff[tc] += pxoffrxc;
856 /* disarm tx queues that have received xoff frames */
857 for (i = 0; i < adapter->num_tx_queues; i++) {
858 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
860 tc = tx_ring->dcb_tc;
862 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
866 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
868 return ring->stats.packets;
871 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
873 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
874 struct ixgbe_hw *hw = &adapter->hw;
876 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
877 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
880 return (head < tail) ?
881 tail - head : (tail + ring->count - head);
886 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
888 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
889 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
890 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
893 clear_check_for_tx_hang(tx_ring);
896 * Check for a hung queue, but be thorough. This verifies
897 * that a transmit has been completed since the previous
898 * check AND there is at least one packet pending. The
899 * ARMED bit is set to indicate a potential hang. The
900 * bit is cleared if a pause frame is received to remove
901 * false hang detection due to PFC or 802.3x frames. By
902 * requiring this to fail twice we avoid races with
903 * pfc clearing the ARMED bit and conditions where we
904 * run the check_tx_hang logic with a transmit completion
905 * pending but without time to complete it yet.
907 if ((tx_done_old == tx_done) && tx_pending) {
908 /* make sure it is true for two checks in a row */
909 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
912 /* update completed stats and continue */
913 tx_ring->tx_stats.tx_done_old = tx_done;
914 /* reset the countdown */
915 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
922 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
923 * @adapter: driver private struct
925 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
928 /* Do the reset outside of interrupt context */
929 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
930 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
931 e_warn(drv, "initiating reset due to tx timeout\n");
932 ixgbe_service_event_schedule(adapter);
937 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
938 * @q_vector: structure containing interrupt and ring information
939 * @tx_ring: tx ring to clean
941 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
942 struct ixgbe_ring *tx_ring)
944 struct ixgbe_adapter *adapter = q_vector->adapter;
945 struct ixgbe_tx_buffer *tx_buffer;
946 union ixgbe_adv_tx_desc *tx_desc;
947 unsigned int total_bytes = 0, total_packets = 0;
948 unsigned int budget = q_vector->tx.work_limit;
949 unsigned int i = tx_ring->next_to_clean;
951 if (test_bit(__IXGBE_DOWN, &adapter->state))
954 tx_buffer = &tx_ring->tx_buffer_info[i];
955 tx_desc = IXGBE_TX_DESC(tx_ring, i);
959 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
961 /* if next_to_watch is not set then there is no work pending */
965 /* prevent any other reads prior to eop_desc */
966 read_barrier_depends();
968 /* if DD is not set pending work has not been completed */
969 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
972 /* clear next_to_watch to prevent false hangs */
973 tx_buffer->next_to_watch = NULL;
975 /* update the statistics for this packet */
976 total_bytes += tx_buffer->bytecount;
977 total_packets += tx_buffer->gso_segs;
980 dev_kfree_skb_any(tx_buffer->skb);
982 /* unmap skb header data */
983 dma_unmap_single(tx_ring->dev,
984 dma_unmap_addr(tx_buffer, dma),
985 dma_unmap_len(tx_buffer, len),
988 /* clear tx_buffer data */
989 tx_buffer->skb = NULL;
990 dma_unmap_len_set(tx_buffer, len, 0);
992 /* unmap remaining buffers */
993 while (tx_desc != eop_desc) {
999 tx_buffer = tx_ring->tx_buffer_info;
1000 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1003 /* unmap any remaining paged data */
1004 if (dma_unmap_len(tx_buffer, len)) {
1005 dma_unmap_page(tx_ring->dev,
1006 dma_unmap_addr(tx_buffer, dma),
1007 dma_unmap_len(tx_buffer, len),
1009 dma_unmap_len_set(tx_buffer, len, 0);
1013 /* move us one more past the eop_desc for start of next pkt */
1018 i -= tx_ring->count;
1019 tx_buffer = tx_ring->tx_buffer_info;
1020 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1023 /* issue prefetch for next Tx descriptor */
1026 /* update budget accounting */
1028 } while (likely(budget));
1030 i += tx_ring->count;
1031 tx_ring->next_to_clean = i;
1032 u64_stats_update_begin(&tx_ring->syncp);
1033 tx_ring->stats.bytes += total_bytes;
1034 tx_ring->stats.packets += total_packets;
1035 u64_stats_update_end(&tx_ring->syncp);
1036 q_vector->tx.total_bytes += total_bytes;
1037 q_vector->tx.total_packets += total_packets;
1039 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1040 /* schedule immediate reset if we believe we hung */
1041 struct ixgbe_hw *hw = &adapter->hw;
1042 e_err(drv, "Detected Tx Unit Hang\n"
1044 " TDH, TDT <%x>, <%x>\n"
1045 " next_to_use <%x>\n"
1046 " next_to_clean <%x>\n"
1047 "tx_buffer_info[next_to_clean]\n"
1048 " time_stamp <%lx>\n"
1050 tx_ring->queue_index,
1051 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1052 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
1053 tx_ring->next_to_use, i,
1054 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
1056 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1059 "tx hang %d detected on queue %d, resetting adapter\n",
1060 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1062 /* schedule immediate reset if we believe we hung */
1063 ixgbe_tx_timeout_reset(adapter);
1065 /* the adapter is about to reset, no point in enabling stuff */
1069 netdev_tx_completed_queue(txring_txq(tx_ring),
1070 total_packets, total_bytes);
1072 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
1073 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
1074 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
1075 /* Make sure that anybody stopping the queue after this
1076 * sees the new next_to_clean.
1079 if (__netif_subqueue_stopped(tx_ring->netdev,
1080 tx_ring->queue_index)
1081 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1082 netif_wake_subqueue(tx_ring->netdev,
1083 tx_ring->queue_index);
1084 ++tx_ring->tx_stats.restart_queue;
1091 #ifdef CONFIG_IXGBE_DCA
1092 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1093 struct ixgbe_ring *tx_ring,
1096 struct ixgbe_hw *hw = &adapter->hw;
1097 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1100 switch (hw->mac.type) {
1101 case ixgbe_mac_82598EB:
1102 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
1104 case ixgbe_mac_82599EB:
1105 case ixgbe_mac_X540:
1106 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1107 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
1110 /* for unknown hardware do not write register */
1115 * We can enable relaxed ordering for reads, but not writes when
1116 * DCA is enabled. This is due to a known issue in some chipsets
1117 * which will cause the DCA tag to be cleared.
1119 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1120 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1121 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1123 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
1126 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1127 struct ixgbe_ring *rx_ring,
1130 struct ixgbe_hw *hw = &adapter->hw;
1131 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1132 u8 reg_idx = rx_ring->reg_idx;
1135 switch (hw->mac.type) {
1136 case ixgbe_mac_82599EB:
1137 case ixgbe_mac_X540:
1138 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
1145 * We can enable relaxed ordering for reads, but not writes when
1146 * DCA is enabled. This is due to a known issue in some chipsets
1147 * which will cause the DCA tag to be cleared.
1149 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
1150 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1152 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
1155 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1157 struct ixgbe_adapter *adapter = q_vector->adapter;
1158 struct ixgbe_ring *ring;
1159 int cpu = get_cpu();
1161 if (q_vector->cpu == cpu)
1164 ixgbe_for_each_ring(ring, q_vector->tx)
1165 ixgbe_update_tx_dca(adapter, ring, cpu);
1167 ixgbe_for_each_ring(ring, q_vector->rx)
1168 ixgbe_update_rx_dca(adapter, ring, cpu);
1170 q_vector->cpu = cpu;
1175 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1179 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1182 /* always use CB2 mode, difference is masked in the CB driver */
1183 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1185 for (i = 0; i < adapter->num_q_vectors; i++) {
1186 adapter->q_vector[i]->cpu = -1;
1187 ixgbe_update_dca(adapter->q_vector[i]);
1191 static int __ixgbe_notify_dca(struct device *dev, void *data)
1193 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1194 unsigned long event = *(unsigned long *)data;
1196 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1200 case DCA_PROVIDER_ADD:
1201 /* if we're already enabled, don't do it again */
1202 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1204 if (dca_add_requester(dev) == 0) {
1205 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1206 ixgbe_setup_dca(adapter);
1209 /* Fall Through since DCA is disabled. */
1210 case DCA_PROVIDER_REMOVE:
1211 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1212 dca_remove_requester(dev);
1213 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1214 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1222 #endif /* CONFIG_IXGBE_DCA */
1223 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1224 union ixgbe_adv_rx_desc *rx_desc,
1225 struct sk_buff *skb)
1227 if (ring->netdev->features & NETIF_F_RXHASH)
1228 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1233 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1234 * @ring: structure containing ring specific data
1235 * @rx_desc: advanced rx descriptor
1237 * Returns : true if it is FCoE pkt
1239 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
1240 union ixgbe_adv_rx_desc *rx_desc)
1242 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1244 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
1245 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1246 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1247 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1250 #endif /* IXGBE_FCOE */
1252 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1253 * @ring: structure containing ring specific data
1254 * @rx_desc: current Rx descriptor being processed
1255 * @skb: skb currently being received and modified
1257 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
1258 union ixgbe_adv_rx_desc *rx_desc,
1259 struct sk_buff *skb)
1261 skb_checksum_none_assert(skb);
1263 /* Rx csum disabled */
1264 if (!(ring->netdev->features & NETIF_F_RXCSUM))
1267 /* if IP and error */
1268 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1269 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
1270 ring->rx_stats.csum_err++;
1274 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
1277 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
1278 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1281 * 82599 errata, UDP frames with a 0 checksum can be marked as
1284 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1285 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
1288 ring->rx_stats.csum_err++;
1292 /* It must be a TCP or UDP packet with a valid checksum */
1293 skb->ip_summed = CHECKSUM_UNNECESSARY;
1296 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1298 rx_ring->next_to_use = val;
1300 /* update next to alloc since we have filled the ring */
1301 rx_ring->next_to_alloc = val;
1303 * Force memory writes to complete before letting h/w
1304 * know there are new descriptors to fetch. (Only
1305 * applicable for weak-ordered memory model archs,
1309 writel(val, rx_ring->tail);
1312 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1313 struct ixgbe_rx_buffer *bi)
1315 struct page *page = bi->page;
1316 dma_addr_t dma = bi->dma;
1318 /* since we are recycling buffers we should seldom need to alloc */
1322 /* alloc new page for storage */
1323 if (likely(!page)) {
1324 page = __skb_alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP,
1325 bi->skb, ixgbe_rx_pg_order(rx_ring));
1326 if (unlikely(!page)) {
1327 rx_ring->rx_stats.alloc_rx_page_failed++;
1333 /* map page for use */
1334 dma = dma_map_page(rx_ring->dev, page, 0,
1335 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1338 * if mapping failed free memory back to system since
1339 * there isn't much point in holding memory we can't use
1341 if (dma_mapping_error(rx_ring->dev, dma)) {
1342 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
1345 rx_ring->rx_stats.alloc_rx_page_failed++;
1350 bi->page_offset = 0;
1356 * ixgbe_alloc_rx_buffers - Replace used receive buffers
1357 * @rx_ring: ring to place buffers on
1358 * @cleaned_count: number of buffers to replace
1360 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1362 union ixgbe_adv_rx_desc *rx_desc;
1363 struct ixgbe_rx_buffer *bi;
1364 u16 i = rx_ring->next_to_use;
1370 rx_desc = IXGBE_RX_DESC(rx_ring, i);
1371 bi = &rx_ring->rx_buffer_info[i];
1372 i -= rx_ring->count;
1375 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1379 * Refresh the desc even if buffer_addrs didn't change
1380 * because each write-back erases this info.
1382 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1388 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
1389 bi = rx_ring->rx_buffer_info;
1390 i -= rx_ring->count;
1393 /* clear the hdr_addr for the next_to_use descriptor */
1394 rx_desc->read.hdr_addr = 0;
1397 } while (cleaned_count);
1399 i += rx_ring->count;
1401 if (rx_ring->next_to_use != i)
1402 ixgbe_release_rx_desc(rx_ring, i);
1406 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1407 * @data: pointer to the start of the headers
1408 * @max_len: total length of section to find headers in
1410 * This function is meant to determine the length of headers that will
1411 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1412 * motivation of doing this is to only perform one pull for IPv4 TCP
1413 * packets so that we can do basic things like calculating the gso_size
1414 * based on the average data per packet.
1416 static unsigned int ixgbe_get_headlen(unsigned char *data,
1417 unsigned int max_len)
1420 unsigned char *network;
1423 struct vlan_hdr *vlan;
1426 struct ipv6hdr *ipv6;
1429 u8 nexthdr = 0; /* default to not TCP */
1432 /* this should never happen, but better safe than sorry */
1433 if (max_len < ETH_HLEN)
1436 /* initialize network frame pointer */
1439 /* set first protocol and move network header forward */
1440 protocol = hdr.eth->h_proto;
1441 hdr.network += ETH_HLEN;
1443 /* handle any vlan tag if present */
1444 if (protocol == __constant_htons(ETH_P_8021Q)) {
1445 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1448 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1449 hdr.network += VLAN_HLEN;
1452 /* handle L3 protocols */
1453 if (protocol == __constant_htons(ETH_P_IP)) {
1454 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1457 /* access ihl as a u8 to avoid unaligned access on ia64 */
1458 hlen = (hdr.network[0] & 0x0F) << 2;
1460 /* verify hlen meets minimum size requirements */
1461 if (hlen < sizeof(struct iphdr))
1462 return hdr.network - data;
1464 /* record next protocol if header is present */
1465 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
1466 nexthdr = hdr.ipv4->protocol;
1467 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
1468 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
1471 /* record next protocol */
1472 nexthdr = hdr.ipv6->nexthdr;
1473 hlen = sizeof(struct ipv6hdr);
1475 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1476 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1478 hlen = FCOE_HEADER_LEN;
1481 return hdr.network - data;
1484 /* relocate pointer to start of L4 header */
1485 hdr.network += hlen;
1487 /* finally sort out TCP/UDP */
1488 if (nexthdr == IPPROTO_TCP) {
1489 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1492 /* access doff as a u8 to avoid unaligned access on ia64 */
1493 hlen = (hdr.network[12] & 0xF0) >> 2;
1495 /* verify hlen meets minimum size requirements */
1496 if (hlen < sizeof(struct tcphdr))
1497 return hdr.network - data;
1499 hdr.network += hlen;
1500 } else if (nexthdr == IPPROTO_UDP) {
1501 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
1504 hdr.network += sizeof(struct udphdr);
1508 * If everything has gone correctly hdr.network should be the
1509 * data section of the packet and will be the end of the header.
1510 * If not then it probably represents the end of the last recognized
1513 if ((hdr.network - data) < max_len)
1514 return hdr.network - data;
1519 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1520 struct sk_buff *skb)
1522 u16 hdr_len = skb_headlen(skb);
1524 /* set gso_size to avoid messing up TCP MSS */
1525 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1526 IXGBE_CB(skb)->append_cnt);
1527 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1530 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1531 struct sk_buff *skb)
1533 /* if append_cnt is 0 then frame is not RSC */
1534 if (!IXGBE_CB(skb)->append_cnt)
1537 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1538 rx_ring->rx_stats.rsc_flush++;
1540 ixgbe_set_rsc_gso_size(rx_ring, skb);
1542 /* gso_size is computed using append_cnt so always clear it last */
1543 IXGBE_CB(skb)->append_cnt = 0;
1547 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1548 * @rx_ring: rx descriptor ring packet is being transacted on
1549 * @rx_desc: pointer to the EOP Rx descriptor
1550 * @skb: pointer to current skb being populated
1552 * This function checks the ring, descriptor, and packet information in
1553 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1554 * other fields within the skb.
1556 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1557 union ixgbe_adv_rx_desc *rx_desc,
1558 struct sk_buff *skb)
1560 struct net_device *dev = rx_ring->netdev;
1562 ixgbe_update_rsc_stats(rx_ring, skb);
1564 ixgbe_rx_hash(rx_ring, rx_desc, skb);
1566 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1568 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
1570 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1571 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1572 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1573 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
1576 skb_record_rx_queue(skb, rx_ring->queue_index);
1578 skb->protocol = eth_type_trans(skb, dev);
1581 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1582 struct sk_buff *skb)
1584 struct ixgbe_adapter *adapter = q_vector->adapter;
1586 if (ixgbe_qv_busy_polling(q_vector))
1587 netif_receive_skb(skb);
1588 else if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1589 napi_gro_receive(&q_vector->napi, skb);
1595 * ixgbe_is_non_eop - process handling of non-EOP buffers
1596 * @rx_ring: Rx ring being processed
1597 * @rx_desc: Rx descriptor for current buffer
1598 * @skb: Current socket buffer containing buffer in progress
1600 * This function updates next to clean. If the buffer is an EOP buffer
1601 * this function exits returning false, otherwise it will place the
1602 * sk_buff in the next buffer to be chained and return true indicating
1603 * that this is in fact a non-EOP buffer.
1605 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1606 union ixgbe_adv_rx_desc *rx_desc,
1607 struct sk_buff *skb)
1609 u32 ntc = rx_ring->next_to_clean + 1;
1611 /* fetch, update, and store next to clean */
1612 ntc = (ntc < rx_ring->count) ? ntc : 0;
1613 rx_ring->next_to_clean = ntc;
1615 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1617 /* update RSC append count if present */
1618 if (ring_is_rsc_enabled(rx_ring)) {
1619 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1620 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1622 if (unlikely(rsc_enabled)) {
1623 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1625 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1626 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
1628 /* update ntc based on RSC value */
1629 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1630 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1631 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1635 /* if we are the last buffer then there is nothing else to do */
1636 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1639 /* place skb in next buffer to be received */
1640 rx_ring->rx_buffer_info[ntc].skb = skb;
1641 rx_ring->rx_stats.non_eop_descs++;
1647 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1648 * @rx_ring: rx descriptor ring packet is being transacted on
1649 * @skb: pointer to current skb being adjusted
1651 * This function is an ixgbe specific version of __pskb_pull_tail. The
1652 * main difference between this version and the original function is that
1653 * this function can make several assumptions about the state of things
1654 * that allow for significant optimizations versus the standard function.
1655 * As a result we can do things like drop a frag and maintain an accurate
1656 * truesize for the skb.
1658 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1659 struct sk_buff *skb)
1661 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1663 unsigned int pull_len;
1666 * it is valid to use page_address instead of kmap since we are
1667 * working with pages allocated out of the lomem pool per
1668 * alloc_page(GFP_ATOMIC)
1670 va = skb_frag_address(frag);
1673 * we need the header to contain the greater of either ETH_HLEN or
1674 * 60 bytes if the skb->len is less than 60 for skb_pad.
1676 pull_len = ixgbe_get_headlen(va, IXGBE_RX_HDR_SIZE);
1678 /* align pull length to size of long to optimize memcpy performance */
1679 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1681 /* update all of the pointers */
1682 skb_frag_size_sub(frag, pull_len);
1683 frag->page_offset += pull_len;
1684 skb->data_len -= pull_len;
1685 skb->tail += pull_len;
1689 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1690 * @rx_ring: rx descriptor ring packet is being transacted on
1691 * @skb: pointer to current skb being updated
1693 * This function provides a basic DMA sync up for the first fragment of an
1694 * skb. The reason for doing this is that the first fragment cannot be
1695 * unmapped until we have reached the end of packet descriptor for a buffer
1698 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1699 struct sk_buff *skb)
1701 /* if the page was released unmap it, else just sync our portion */
1702 if (unlikely(IXGBE_CB(skb)->page_released)) {
1703 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1704 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1705 IXGBE_CB(skb)->page_released = false;
1707 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1709 dma_sync_single_range_for_cpu(rx_ring->dev,
1712 ixgbe_rx_bufsz(rx_ring),
1715 IXGBE_CB(skb)->dma = 0;
1719 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1720 * @rx_ring: rx descriptor ring packet is being transacted on
1721 * @rx_desc: pointer to the EOP Rx descriptor
1722 * @skb: pointer to current skb being fixed
1724 * Check for corrupted packet headers caused by senders on the local L2
1725 * embedded NIC switch not setting up their Tx Descriptors right. These
1726 * should be very rare.
1728 * Also address the case where we are pulling data in on pages only
1729 * and as such no data is present in the skb header.
1731 * In addition if skb is not at least 60 bytes we need to pad it so that
1732 * it is large enough to qualify as a valid Ethernet frame.
1734 * Returns true if an error was encountered and skb was freed.
1736 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1737 union ixgbe_adv_rx_desc *rx_desc,
1738 struct sk_buff *skb)
1740 struct net_device *netdev = rx_ring->netdev;
1742 /* verify that the packet does not have any known errors */
1743 if (unlikely(ixgbe_test_staterr(rx_desc,
1744 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1745 !(netdev->features & NETIF_F_RXALL))) {
1746 dev_kfree_skb_any(skb);
1750 /* place header in linear portion of buffer */
1751 if (skb_is_nonlinear(skb))
1752 ixgbe_pull_tail(rx_ring, skb);
1755 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1756 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1760 /* if skb_pad returns an error the skb was freed */
1761 if (unlikely(skb->len < 60)) {
1762 int pad_len = 60 - skb->len;
1764 if (skb_pad(skb, pad_len))
1766 __skb_put(skb, pad_len);
1773 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1774 * @rx_ring: rx descriptor ring to store buffers on
1775 * @old_buff: donor buffer to have page reused
1777 * Synchronizes page for reuse by the adapter
1779 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1780 struct ixgbe_rx_buffer *old_buff)
1782 struct ixgbe_rx_buffer *new_buff;
1783 u16 nta = rx_ring->next_to_alloc;
1785 new_buff = &rx_ring->rx_buffer_info[nta];
1787 /* update, and store next to alloc */
1789 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1791 /* transfer page from old buffer to new buffer */
1792 new_buff->page = old_buff->page;
1793 new_buff->dma = old_buff->dma;
1794 new_buff->page_offset = old_buff->page_offset;
1796 /* sync the buffer for use by the device */
1797 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
1798 new_buff->page_offset,
1799 ixgbe_rx_bufsz(rx_ring),
1804 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1805 * @rx_ring: rx descriptor ring to transact packets on
1806 * @rx_buffer: buffer containing page to add
1807 * @rx_desc: descriptor containing length of buffer written by hardware
1808 * @skb: sk_buff to place the data into
1810 * This function will add the data contained in rx_buffer->page to the skb.
1811 * This is done either through a direct copy if the data in the buffer is
1812 * less than the skb header size, otherwise it will just attach the page as
1813 * a frag to the skb.
1815 * The function will then update the page offset if necessary and return
1816 * true if the buffer can be reused by the adapter.
1818 static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
1819 struct ixgbe_rx_buffer *rx_buffer,
1820 union ixgbe_adv_rx_desc *rx_desc,
1821 struct sk_buff *skb)
1823 struct page *page = rx_buffer->page;
1824 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
1825 #if (PAGE_SIZE < 8192)
1826 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
1828 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1829 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1830 ixgbe_rx_bufsz(rx_ring);
1833 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1834 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1836 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1838 /* we can reuse buffer as-is, just make sure it is local */
1839 if (likely(page_to_nid(page) == numa_node_id()))
1842 /* this page cannot be reused so discard it */
1847 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1848 rx_buffer->page_offset, size, truesize);
1850 /* avoid re-using remote pages */
1851 if (unlikely(page_to_nid(page) != numa_node_id()))
1854 #if (PAGE_SIZE < 8192)
1855 /* if we are only owner of page we can reuse it */
1856 if (unlikely(page_count(page) != 1))
1859 /* flip page offset to other buffer */
1860 rx_buffer->page_offset ^= truesize;
1863 * since we are the only owner of the page and we need to
1864 * increment it, just set the value to 2 in order to avoid
1865 * an unecessary locked operation
1867 atomic_set(&page->_count, 2);
1869 /* move offset up to the next cache line */
1870 rx_buffer->page_offset += truesize;
1872 if (rx_buffer->page_offset > last_offset)
1875 /* bump ref count on page before it is given to the stack */
1882 static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1883 union ixgbe_adv_rx_desc *rx_desc)
1885 struct ixgbe_rx_buffer *rx_buffer;
1886 struct sk_buff *skb;
1889 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1890 page = rx_buffer->page;
1893 skb = rx_buffer->skb;
1896 void *page_addr = page_address(page) +
1897 rx_buffer->page_offset;
1899 /* prefetch first cache line of first page */
1900 prefetch(page_addr);
1901 #if L1_CACHE_BYTES < 128
1902 prefetch(page_addr + L1_CACHE_BYTES);
1905 /* allocate a skb to store the frags */
1906 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1908 if (unlikely(!skb)) {
1909 rx_ring->rx_stats.alloc_rx_buff_failed++;
1914 * we will be copying header into skb->data in
1915 * pskb_may_pull so it is in our interest to prefetch
1916 * it now to avoid a possible cache miss
1918 prefetchw(skb->data);
1921 * Delay unmapping of the first packet. It carries the
1922 * header information, HW may still access the header
1923 * after the writeback. Only unmap it when EOP is
1926 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1929 IXGBE_CB(skb)->dma = rx_buffer->dma;
1931 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
1932 ixgbe_dma_sync_frag(rx_ring, skb);
1935 /* we are reusing so sync this buffer for CPU use */
1936 dma_sync_single_range_for_cpu(rx_ring->dev,
1938 rx_buffer->page_offset,
1939 ixgbe_rx_bufsz(rx_ring),
1943 /* pull page into skb */
1944 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
1945 /* hand second half of page back to the ring */
1946 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1947 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1948 /* the page has been released from the ring */
1949 IXGBE_CB(skb)->page_released = true;
1951 /* we are not reusing the buffer so unmap it */
1952 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1953 ixgbe_rx_pg_size(rx_ring),
1957 /* clear contents of buffer_info */
1958 rx_buffer->skb = NULL;
1960 rx_buffer->page = NULL;
1966 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1967 * @q_vector: structure containing interrupt and ring information
1968 * @rx_ring: rx descriptor ring to transact packets on
1969 * @budget: Total limit on number of packets to process
1971 * This function provides a "bounce buffer" approach to Rx interrupt
1972 * processing. The advantage to this is that on systems that have
1973 * expensive overhead for IOMMU access this provides a means of avoiding
1974 * it by maintaining the mapping of the page to the syste.
1976 * Returns amount of work completed
1978 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1979 struct ixgbe_ring *rx_ring,
1982 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1984 struct ixgbe_adapter *adapter = q_vector->adapter;
1986 unsigned int mss = 0;
1987 #endif /* IXGBE_FCOE */
1988 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
1991 union ixgbe_adv_rx_desc *rx_desc;
1992 struct sk_buff *skb;
1994 /* return some buffers to hardware, one at a time is too slow */
1995 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1996 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2000 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
2002 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
2006 * This memory barrier is needed to keep us from reading
2007 * any other fields out of the rx_desc until we know the
2008 * RXD_STAT_DD bit is set
2012 /* retrieve a buffer from the ring */
2013 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
2015 /* exit if we failed to retrieve a buffer */
2021 /* place incomplete frames back on ring for completion */
2022 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2025 /* verify the packet layout is correct */
2026 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2029 /* probably a little skewed due to removing CRC */
2030 total_rx_bytes += skb->len;
2032 /* populate checksum, timestamp, VLAN, and protocol */
2033 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2036 /* if ddp, not passing to ULD unless for FCP_RSP or error */
2037 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
2038 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
2039 /* include DDPed FCoE data */
2040 if (ddp_bytes > 0) {
2042 mss = rx_ring->netdev->mtu -
2043 sizeof(struct fcoe_hdr) -
2044 sizeof(struct fc_frame_header) -
2045 sizeof(struct fcoe_crc_eof);
2049 total_rx_bytes += ddp_bytes;
2050 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2054 dev_kfree_skb_any(skb);
2059 #endif /* IXGBE_FCOE */
2060 skb_mark_napi_id(skb, &q_vector->napi);
2061 ixgbe_rx_skb(q_vector, skb);
2063 /* update budget accounting */
2065 } while (likely(total_rx_packets < budget));
2067 u64_stats_update_begin(&rx_ring->syncp);
2068 rx_ring->stats.packets += total_rx_packets;
2069 rx_ring->stats.bytes += total_rx_bytes;
2070 u64_stats_update_end(&rx_ring->syncp);
2071 q_vector->rx.total_packets += total_rx_packets;
2072 q_vector->rx.total_bytes += total_rx_bytes;
2075 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2077 return total_rx_packets;
2080 #ifdef CONFIG_NET_RX_BUSY_POLL
2081 /* must be called with local_bh_disable()d */
2082 static int ixgbe_low_latency_recv(struct napi_struct *napi)
2084 struct ixgbe_q_vector *q_vector =
2085 container_of(napi, struct ixgbe_q_vector, napi);
2086 struct ixgbe_adapter *adapter = q_vector->adapter;
2087 struct ixgbe_ring *ring;
2090 if (test_bit(__IXGBE_DOWN, &adapter->state))
2091 return LL_FLUSH_FAILED;
2093 if (!ixgbe_qv_lock_poll(q_vector))
2094 return LL_FLUSH_BUSY;
2096 ixgbe_for_each_ring(ring, q_vector->rx) {
2097 found = ixgbe_clean_rx_irq(q_vector, ring, 4);
2098 #ifdef BP_EXTENDED_STATS
2100 ring->stats.cleaned += found;
2102 ring->stats.misses++;
2108 ixgbe_qv_unlock_poll(q_vector);
2112 #endif /* CONFIG_NET_RX_BUSY_POLL */
2115 * ixgbe_configure_msix - Configure MSI-X hardware
2116 * @adapter: board private structure
2118 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2121 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2123 struct ixgbe_q_vector *q_vector;
2127 /* Populate MSIX to EITR Select */
2128 if (adapter->num_vfs > 32) {
2129 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2130 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2134 * Populate the IVAR table and set the ITR values to the
2135 * corresponding register.
2137 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
2138 struct ixgbe_ring *ring;
2139 q_vector = adapter->q_vector[v_idx];
2141 ixgbe_for_each_ring(ring, q_vector->rx)
2142 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2144 ixgbe_for_each_ring(ring, q_vector->tx)
2145 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2147 ixgbe_write_eitr(q_vector);
2150 switch (adapter->hw.mac.type) {
2151 case ixgbe_mac_82598EB:
2152 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
2155 case ixgbe_mac_82599EB:
2156 case ixgbe_mac_X540:
2157 ixgbe_set_ivar(adapter, -1, 1, v_idx);
2162 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2164 /* set up to autoclear timer, and the vectors */
2165 mask = IXGBE_EIMS_ENABLE_MASK;
2166 mask &= ~(IXGBE_EIMS_OTHER |
2167 IXGBE_EIMS_MAILBOX |
2170 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
2173 enum latency_range {
2177 latency_invalid = 255
2181 * ixgbe_update_itr - update the dynamic ITR value based on statistics
2182 * @q_vector: structure containing interrupt and ring information
2183 * @ring_container: structure containing ring performance data
2185 * Stores a new ITR value based on packets and byte
2186 * counts during the last interrupt. The advantage of per interrupt
2187 * computation is faster updates and more accurate ITR for the current
2188 * traffic pattern. Constants in this function were computed
2189 * based on theoretical maximum wire speed and thresholds were set based
2190 * on testing data as well as attempting to minimize response time
2191 * while increasing bulk throughput.
2192 * this functionality is controlled by the InterruptThrottleRate module
2193 * parameter (see ixgbe_param.c)
2195 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2196 struct ixgbe_ring_container *ring_container)
2198 int bytes = ring_container->total_bytes;
2199 int packets = ring_container->total_packets;
2202 u8 itr_setting = ring_container->itr;
2207 /* simple throttlerate management
2208 * 0-10MB/s lowest (100000 ints/s)
2209 * 10-20MB/s low (20000 ints/s)
2210 * 20-1249MB/s bulk (8000 ints/s)
2212 /* what was last interrupt timeslice? */
2213 timepassed_us = q_vector->itr >> 2;
2214 if (timepassed_us == 0)
2217 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2219 switch (itr_setting) {
2220 case lowest_latency:
2221 if (bytes_perint > 10)
2222 itr_setting = low_latency;
2225 if (bytes_perint > 20)
2226 itr_setting = bulk_latency;
2227 else if (bytes_perint <= 10)
2228 itr_setting = lowest_latency;
2231 if (bytes_perint <= 20)
2232 itr_setting = low_latency;
2236 /* clear work counters since we have the values we need */
2237 ring_container->total_bytes = 0;
2238 ring_container->total_packets = 0;
2240 /* write updated itr to ring container */
2241 ring_container->itr = itr_setting;
2245 * ixgbe_write_eitr - write EITR register in hardware specific way
2246 * @q_vector: structure containing interrupt and ring information
2248 * This function is made to be called by ethtool and by the driver
2249 * when it needs to update EITR registers at runtime. Hardware
2250 * specific quirks/differences are taken care of here.
2252 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
2254 struct ixgbe_adapter *adapter = q_vector->adapter;
2255 struct ixgbe_hw *hw = &adapter->hw;
2256 int v_idx = q_vector->v_idx;
2257 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
2259 switch (adapter->hw.mac.type) {
2260 case ixgbe_mac_82598EB:
2261 /* must write high and low 16 bits to reset counter */
2262 itr_reg |= (itr_reg << 16);
2264 case ixgbe_mac_82599EB:
2265 case ixgbe_mac_X540:
2267 * set the WDIS bit to not clear the timer bits and cause an
2268 * immediate assertion of the interrupt
2270 itr_reg |= IXGBE_EITR_CNT_WDIS;
2275 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2278 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
2280 u32 new_itr = q_vector->itr;
2283 ixgbe_update_itr(q_vector, &q_vector->tx);
2284 ixgbe_update_itr(q_vector, &q_vector->rx);
2286 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
2288 switch (current_itr) {
2289 /* counts and packets in update_itr are dependent on these numbers */
2290 case lowest_latency:
2291 new_itr = IXGBE_100K_ITR;
2294 new_itr = IXGBE_20K_ITR;
2297 new_itr = IXGBE_8K_ITR;
2303 if (new_itr != q_vector->itr) {
2304 /* do an exponential smoothing */
2305 new_itr = (10 * new_itr * q_vector->itr) /
2306 ((9 * new_itr) + q_vector->itr);
2308 /* save the algorithm value here */
2309 q_vector->itr = new_itr;
2311 ixgbe_write_eitr(q_vector);
2316 * ixgbe_check_overtemp_subtask - check for over temperature
2317 * @adapter: pointer to adapter
2319 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
2321 struct ixgbe_hw *hw = &adapter->hw;
2322 u32 eicr = adapter->interrupt_event;
2324 if (test_bit(__IXGBE_DOWN, &adapter->state))
2327 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2328 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2331 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2333 switch (hw->device_id) {
2334 case IXGBE_DEV_ID_82599_T3_LOM:
2336 * Since the warning interrupt is for both ports
2337 * we don't have to check if:
2338 * - This interrupt wasn't for our port.
2339 * - We may have missed the interrupt so always have to
2340 * check if we got a LSC
2342 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2343 !(eicr & IXGBE_EICR_LSC))
2346 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2348 bool link_up = false;
2350 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2356 /* Check if this is not due to overtemp */
2357 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2362 if (!(eicr & IXGBE_EICR_GPI_SDP0))
2367 "Network adapter has been stopped because it has over heated. "
2368 "Restart the computer. If the problem persists, "
2369 "power off the system and replace the adapter\n");
2371 adapter->interrupt_event = 0;
2374 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2376 struct ixgbe_hw *hw = &adapter->hw;
2378 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2379 (eicr & IXGBE_EICR_GPI_SDP1)) {
2380 e_crit(probe, "Fan has stopped, replace the adapter\n");
2381 /* write to clear the interrupt */
2382 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2386 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2388 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2391 switch (adapter->hw.mac.type) {
2392 case ixgbe_mac_82599EB:
2394 * Need to check link state so complete overtemp check
2397 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2398 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2399 adapter->interrupt_event = eicr;
2400 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2401 ixgbe_service_event_schedule(adapter);
2405 case ixgbe_mac_X540:
2406 if (!(eicr & IXGBE_EICR_TS))
2414 "Network adapter has been stopped because it has over heated. "
2415 "Restart the computer. If the problem persists, "
2416 "power off the system and replace the adapter\n");
2419 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2421 struct ixgbe_hw *hw = &adapter->hw;
2423 if (eicr & IXGBE_EICR_GPI_SDP2) {
2424 /* Clear the interrupt */
2425 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
2426 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2427 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2428 ixgbe_service_event_schedule(adapter);
2432 if (eicr & IXGBE_EICR_GPI_SDP1) {
2433 /* Clear the interrupt */
2434 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2435 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2436 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2437 ixgbe_service_event_schedule(adapter);
2442 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2444 struct ixgbe_hw *hw = &adapter->hw;
2447 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2448 adapter->link_check_timeout = jiffies;
2449 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2450 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
2451 IXGBE_WRITE_FLUSH(hw);
2452 ixgbe_service_event_schedule(adapter);
2456 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2460 struct ixgbe_hw *hw = &adapter->hw;
2462 switch (hw->mac.type) {
2463 case ixgbe_mac_82598EB:
2464 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2465 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2467 case ixgbe_mac_82599EB:
2468 case ixgbe_mac_X540:
2469 mask = (qmask & 0xFFFFFFFF);
2471 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
2472 mask = (qmask >> 32);
2474 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2479 /* skip the flush */
2482 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
2486 struct ixgbe_hw *hw = &adapter->hw;
2488 switch (hw->mac.type) {
2489 case ixgbe_mac_82598EB:
2490 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2491 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2493 case ixgbe_mac_82599EB:
2494 case ixgbe_mac_X540:
2495 mask = (qmask & 0xFFFFFFFF);
2497 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
2498 mask = (qmask >> 32);
2500 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2505 /* skip the flush */
2509 * ixgbe_irq_enable - Enable default interrupt generation settings
2510 * @adapter: board private structure
2512 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2515 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2517 /* don't reenable LSC while waiting for link */
2518 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2519 mask &= ~IXGBE_EIMS_LSC;
2521 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2522 switch (adapter->hw.mac.type) {
2523 case ixgbe_mac_82599EB:
2524 mask |= IXGBE_EIMS_GPI_SDP0;
2526 case ixgbe_mac_X540:
2527 mask |= IXGBE_EIMS_TS;
2532 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2533 mask |= IXGBE_EIMS_GPI_SDP1;
2534 switch (adapter->hw.mac.type) {
2535 case ixgbe_mac_82599EB:
2536 mask |= IXGBE_EIMS_GPI_SDP1;
2537 mask |= IXGBE_EIMS_GPI_SDP2;
2538 case ixgbe_mac_X540:
2539 mask |= IXGBE_EIMS_ECC;
2540 mask |= IXGBE_EIMS_MAILBOX;
2546 if (adapter->hw.mac.type == ixgbe_mac_X540)
2547 mask |= IXGBE_EIMS_TIMESYNC;
2549 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2550 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2551 mask |= IXGBE_EIMS_FLOW_DIR;
2553 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2555 ixgbe_irq_enable_queues(adapter, ~0);
2557 IXGBE_WRITE_FLUSH(&adapter->hw);
2560 static irqreturn_t ixgbe_msix_other(int irq, void *data)
2562 struct ixgbe_adapter *adapter = data;
2563 struct ixgbe_hw *hw = &adapter->hw;
2567 * Workaround for Silicon errata. Use clear-by-write instead
2568 * of clear-by-read. Reading with EICS will return the
2569 * interrupt causes without clearing, which later be done
2570 * with the write to EICR.
2572 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2574 /* The lower 16bits of the EICR register are for the queue interrupts
2575 * which should be masked here in order to not accidently clear them if
2576 * the bits are high when ixgbe_msix_other is called. There is a race
2577 * condition otherwise which results in possible performance loss
2578 * especially if the ixgbe_msix_other interrupt is triggering
2579 * consistently (as it would when PPS is turned on for the X540 device)
2583 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
2585 if (eicr & IXGBE_EICR_LSC)
2586 ixgbe_check_lsc(adapter);
2588 if (eicr & IXGBE_EICR_MAILBOX)
2589 ixgbe_msg_task(adapter);
2591 switch (hw->mac.type) {
2592 case ixgbe_mac_82599EB:
2593 case ixgbe_mac_X540:
2594 if (eicr & IXGBE_EICR_ECC)
2595 e_info(link, "Received unrecoverable ECC Err, please "
2597 /* Handle Flow Director Full threshold interrupt */
2598 if (eicr & IXGBE_EICR_FLOW_DIR) {
2599 int reinit_count = 0;
2601 for (i = 0; i < adapter->num_tx_queues; i++) {
2602 struct ixgbe_ring *ring = adapter->tx_ring[i];
2603 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
2608 /* no more flow director interrupts until after init */
2609 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
2610 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2611 ixgbe_service_event_schedule(adapter);
2614 ixgbe_check_sfp_event(adapter, eicr);
2615 ixgbe_check_overtemp_event(adapter, eicr);
2621 ixgbe_check_fan_failure(adapter, eicr);
2623 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2624 ixgbe_ptp_check_pps_event(adapter, eicr);
2626 /* re-enable the original interrupt state, no lsc, no queues */
2627 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2628 ixgbe_irq_enable(adapter, false, false);
2633 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
2635 struct ixgbe_q_vector *q_vector = data;
2637 /* EIAM disabled interrupts (on this vector) for us */
2639 if (q_vector->rx.ring || q_vector->tx.ring)
2640 napi_schedule(&q_vector->napi);
2646 * ixgbe_poll - NAPI Rx polling callback
2647 * @napi: structure for representing this polling device
2648 * @budget: how many packets driver is allowed to clean
2650 * This function is used for legacy and MSI, NAPI mode
2652 int ixgbe_poll(struct napi_struct *napi, int budget)
2654 struct ixgbe_q_vector *q_vector =
2655 container_of(napi, struct ixgbe_q_vector, napi);
2656 struct ixgbe_adapter *adapter = q_vector->adapter;
2657 struct ixgbe_ring *ring;
2658 int per_ring_budget;
2659 bool clean_complete = true;
2661 #ifdef CONFIG_IXGBE_DCA
2662 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2663 ixgbe_update_dca(q_vector);
2666 ixgbe_for_each_ring(ring, q_vector->tx)
2667 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2669 if (!ixgbe_qv_lock_napi(q_vector))
2672 /* attempt to distribute budget to each queue fairly, but don't allow
2673 * the budget to go below 1 because we'll exit polling */
2674 if (q_vector->rx.count > 1)
2675 per_ring_budget = max(budget/q_vector->rx.count, 1);
2677 per_ring_budget = budget;
2679 ixgbe_for_each_ring(ring, q_vector->rx)
2680 clean_complete &= (ixgbe_clean_rx_irq(q_vector, ring,
2681 per_ring_budget) < per_ring_budget);
2683 ixgbe_qv_unlock_napi(q_vector);
2684 /* If all work not completed, return budget and keep polling */
2685 if (!clean_complete)
2688 /* all work done, exit the polling mode */
2689 napi_complete(napi);
2690 if (adapter->rx_itr_setting & 1)
2691 ixgbe_set_itr(q_vector);
2692 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2693 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2699 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2700 * @adapter: board private structure
2702 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2703 * interrupts from the kernel.
2705 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2707 struct net_device *netdev = adapter->netdev;
2711 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2712 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2713 struct msix_entry *entry = &adapter->msix_entries[vector];
2715 if (q_vector->tx.ring && q_vector->rx.ring) {
2716 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2717 "%s-%s-%d", netdev->name, "TxRx", ri++);
2719 } else if (q_vector->rx.ring) {
2720 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2721 "%s-%s-%d", netdev->name, "rx", ri++);
2722 } else if (q_vector->tx.ring) {
2723 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2724 "%s-%s-%d", netdev->name, "tx", ti++);
2726 /* skip this unused q_vector */
2729 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2730 q_vector->name, q_vector);
2732 e_err(probe, "request_irq failed for MSIX interrupt "
2733 "Error: %d\n", err);
2734 goto free_queue_irqs;
2736 /* If Flow Director is enabled, set interrupt affinity */
2737 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2738 /* assign the mask for this irq */
2739 irq_set_affinity_hint(entry->vector,
2740 &q_vector->affinity_mask);
2744 err = request_irq(adapter->msix_entries[vector].vector,
2745 ixgbe_msix_other, 0, netdev->name, adapter);
2747 e_err(probe, "request_irq for msix_other failed: %d\n", err);
2748 goto free_queue_irqs;
2756 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2758 free_irq(adapter->msix_entries[vector].vector,
2759 adapter->q_vector[vector]);
2761 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2762 pci_disable_msix(adapter->pdev);
2763 kfree(adapter->msix_entries);
2764 adapter->msix_entries = NULL;
2769 * ixgbe_intr - legacy mode Interrupt Handler
2770 * @irq: interrupt number
2771 * @data: pointer to a network interface device structure
2773 static irqreturn_t ixgbe_intr(int irq, void *data)
2775 struct ixgbe_adapter *adapter = data;
2776 struct ixgbe_hw *hw = &adapter->hw;
2777 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2781 * Workaround for silicon errata #26 on 82598. Mask the interrupt
2782 * before the read of EICR.
2784 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2786 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2787 * therefore no explicit interrupt disable is necessary */
2788 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2791 * shared interrupt alert!
2792 * make sure interrupts are enabled because the read will
2793 * have disabled interrupts due to EIAM
2794 * finish the workaround of silicon errata on 82598. Unmask
2795 * the interrupt that we masked before the EICR read.
2797 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2798 ixgbe_irq_enable(adapter, true, true);
2799 return IRQ_NONE; /* Not our interrupt */
2802 if (eicr & IXGBE_EICR_LSC)
2803 ixgbe_check_lsc(adapter);
2805 switch (hw->mac.type) {
2806 case ixgbe_mac_82599EB:
2807 ixgbe_check_sfp_event(adapter, eicr);
2809 case ixgbe_mac_X540:
2810 if (eicr & IXGBE_EICR_ECC)
2811 e_info(link, "Received unrecoverable ECC err, please "
2813 ixgbe_check_overtemp_event(adapter, eicr);
2819 ixgbe_check_fan_failure(adapter, eicr);
2820 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2821 ixgbe_ptp_check_pps_event(adapter, eicr);
2823 /* would disable interrupts here but EIAM disabled it */
2824 napi_schedule(&q_vector->napi);
2827 * re-enable link(maybe) and non-queue interrupts, no flush.
2828 * ixgbe_poll will re-enable the queue interrupts
2830 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2831 ixgbe_irq_enable(adapter, false, false);
2837 * ixgbe_request_irq - initialize interrupts
2838 * @adapter: board private structure
2840 * Attempts to configure interrupts using the best available
2841 * capabilities of the hardware and kernel.
2843 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2845 struct net_device *netdev = adapter->netdev;
2848 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2849 err = ixgbe_request_msix_irqs(adapter);
2850 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
2851 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2852 netdev->name, adapter);
2854 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2855 netdev->name, adapter);
2858 e_err(probe, "request_irq failed, Error %d\n", err);
2863 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2867 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2868 free_irq(adapter->pdev->irq, adapter);
2872 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2873 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2874 struct msix_entry *entry = &adapter->msix_entries[vector];
2876 /* free only the irqs that were actually requested */
2877 if (!q_vector->rx.ring && !q_vector->tx.ring)
2880 /* clear the affinity_mask in the IRQ descriptor */
2881 irq_set_affinity_hint(entry->vector, NULL);
2883 free_irq(entry->vector, q_vector);
2886 free_irq(adapter->msix_entries[vector++].vector, adapter);
2890 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2891 * @adapter: board private structure
2893 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2895 switch (adapter->hw.mac.type) {
2896 case ixgbe_mac_82598EB:
2897 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2899 case ixgbe_mac_82599EB:
2900 case ixgbe_mac_X540:
2901 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2902 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2903 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2908 IXGBE_WRITE_FLUSH(&adapter->hw);
2909 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2912 for (vector = 0; vector < adapter->num_q_vectors; vector++)
2913 synchronize_irq(adapter->msix_entries[vector].vector);
2915 synchronize_irq(adapter->msix_entries[vector++].vector);
2917 synchronize_irq(adapter->pdev->irq);
2922 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2925 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2927 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2929 ixgbe_write_eitr(q_vector);
2931 ixgbe_set_ivar(adapter, 0, 0, 0);
2932 ixgbe_set_ivar(adapter, 1, 0, 0);
2934 e_info(hw, "Legacy interrupt IVAR setup done\n");
2938 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2939 * @adapter: board private structure
2940 * @ring: structure containing ring specific data
2942 * Configure the Tx descriptor ring after a reset.
2944 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2945 struct ixgbe_ring *ring)
2947 struct ixgbe_hw *hw = &adapter->hw;
2948 u64 tdba = ring->dma;
2950 u32 txdctl = IXGBE_TXDCTL_ENABLE;
2951 u8 reg_idx = ring->reg_idx;
2953 /* disable queue to avoid issues while updating state */
2954 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2955 IXGBE_WRITE_FLUSH(hw);
2957 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2958 (tdba & DMA_BIT_MASK(32)));
2959 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2960 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2961 ring->count * sizeof(union ixgbe_adv_tx_desc));
2962 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2963 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2964 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2967 * set WTHRESH to encourage burst writeback, it should not be set
2968 * higher than 1 when:
2969 * - ITR is 0 as it could cause false TX hangs
2970 * - ITR is set to > 100k int/sec and BQL is enabled
2972 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2973 * to or less than the number of on chip descriptors, which is
2976 #if IS_ENABLED(CONFIG_BQL)
2977 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
2979 if (!ring->q_vector || (ring->q_vector->itr < 8))
2981 txdctl |= (1 << 16); /* WTHRESH = 1 */
2983 txdctl |= (8 << 16); /* WTHRESH = 8 */
2986 * Setting PTHRESH to 32 both improves performance
2987 * and avoids a TX hang with DFP enabled
2989 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2990 32; /* PTHRESH = 32 */
2992 /* reinitialize flowdirector state */
2993 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2994 ring->atr_sample_rate = adapter->atr_sample_rate;
2995 ring->atr_count = 0;
2996 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2998 ring->atr_sample_rate = 0;
3001 /* initialize XPS */
3002 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3003 struct ixgbe_q_vector *q_vector = ring->q_vector;
3006 netif_set_xps_queue(adapter->netdev,
3007 &q_vector->affinity_mask,
3011 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3014 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3016 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3017 if (hw->mac.type == ixgbe_mac_82598EB &&
3018 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3021 /* poll to verify queue is enabled */
3023 usleep_range(1000, 2000);
3024 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3025 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3027 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
3030 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3032 struct ixgbe_hw *hw = &adapter->hw;
3034 u8 tcs = netdev_get_num_tc(adapter->netdev);
3036 if (hw->mac.type == ixgbe_mac_82598EB)
3039 /* disable the arbiter while setting MTQC */
3040 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3041 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3042 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3044 /* set transmit pool layout */
3045 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3046 mtqc = IXGBE_MTQC_VT_ENA;
3048 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3050 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3051 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3052 mtqc |= IXGBE_MTQC_32VF;
3054 mtqc |= IXGBE_MTQC_64VF;
3057 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3059 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3061 mtqc = IXGBE_MTQC_64Q_1PB;
3064 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3066 /* Enable Security TX Buffer IFG for multiple pb */
3068 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3069 sectx |= IXGBE_SECTX_DCB;
3070 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
3073 /* re-enable the arbiter */
3074 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3075 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3079 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
3080 * @adapter: board private structure
3082 * Configure the Tx unit of the MAC after a reset.
3084 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3086 struct ixgbe_hw *hw = &adapter->hw;
3090 ixgbe_setup_mtqc(adapter);
3092 if (hw->mac.type != ixgbe_mac_82598EB) {
3093 /* DMATXCTL.EN must be before Tx queues are enabled */
3094 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3095 dmatxctl |= IXGBE_DMATXCTL_TE;
3096 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3099 /* Setup the HW Tx Head and Tail descriptor pointers */
3100 for (i = 0; i < adapter->num_tx_queues; i++)
3101 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
3104 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3105 struct ixgbe_ring *ring)
3107 struct ixgbe_hw *hw = &adapter->hw;
3108 u8 reg_idx = ring->reg_idx;
3109 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3111 srrctl |= IXGBE_SRRCTL_DROP_EN;
3113 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3116 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3117 struct ixgbe_ring *ring)
3119 struct ixgbe_hw *hw = &adapter->hw;
3120 u8 reg_idx = ring->reg_idx;
3121 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3123 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3125 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3128 #ifdef CONFIG_IXGBE_DCB
3129 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3131 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3135 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3137 if (adapter->ixgbe_ieee_pfc)
3138 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3141 * We should set the drop enable bit if:
3144 * Number of Rx queues > 1 and flow control is disabled
3146 * This allows us to avoid head of line blocking for security
3147 * and performance reasons.
3149 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3150 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3151 for (i = 0; i < adapter->num_rx_queues; i++)
3152 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3154 for (i = 0; i < adapter->num_rx_queues; i++)
3155 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3159 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
3161 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
3162 struct ixgbe_ring *rx_ring)
3164 struct ixgbe_hw *hw = &adapter->hw;
3166 u8 reg_idx = rx_ring->reg_idx;
3168 if (hw->mac.type == ixgbe_mac_82598EB) {
3169 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
3172 * if VMDq is not active we must program one srrctl register
3173 * per RSS queue since we have enabled RDRXCTL.MVMEN
3178 /* configure header buffer length, needed for RSC */
3179 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
3181 /* configure the packet buffer length */
3182 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3184 /* configure descriptor type */
3185 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3187 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3190 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3192 struct ixgbe_hw *hw = &adapter->hw;
3193 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
3194 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
3195 0x6A3E67EA, 0x14364D17, 0x3BED200D};
3196 u32 mrqc = 0, reta = 0;
3199 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3202 * Program table for at least 2 queues w/ SR-IOV so that VFs can
3203 * make full use of any rings they may have. We will use the
3204 * PSRTYPE register to control how many rings we use within the PF.
3206 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3209 /* Fill out hash function seeds */
3210 for (i = 0; i < 10; i++)
3211 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
3213 /* Fill out redirection table */
3214 for (i = 0, j = 0; i < 128; i++, j++) {
3217 /* reta = 4-byte sliding window of
3218 * 0x00..(indices-1)(indices-1)00..etc. */
3219 reta = (reta << 8) | (j * 0x11);
3221 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3224 /* Disable indicating checksum in descriptor, enables RSS hash */
3225 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3226 rxcsum |= IXGBE_RXCSUM_PCSD;
3227 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3229 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3230 if (adapter->ring_feature[RING_F_RSS].mask)
3231 mrqc = IXGBE_MRQC_RSSEN;
3233 u8 tcs = netdev_get_num_tc(adapter->netdev);
3235 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3237 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3239 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3240 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3241 mrqc = IXGBE_MRQC_VMDQRSS32EN;
3243 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3246 mrqc = IXGBE_MRQC_RTRSS8TCEN;
3248 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3250 mrqc = IXGBE_MRQC_RSSEN;
3254 /* Perform hash on these packet types */
3255 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3256 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3257 IXGBE_MRQC_RSS_FIELD_IPV6 |
3258 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
3260 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3261 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3262 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3263 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3265 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3269 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3270 * @adapter: address of board private structure
3271 * @index: index of ring to set
3273 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
3274 struct ixgbe_ring *ring)
3276 struct ixgbe_hw *hw = &adapter->hw;
3278 u8 reg_idx = ring->reg_idx;
3280 if (!ring_is_rsc_enabled(ring))
3283 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
3284 rscctrl |= IXGBE_RSCCTL_RSCEN;
3286 * we must limit the number of descriptors so that the
3287 * total size of max desc * buf_len is not greater
3290 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
3291 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
3294 #define IXGBE_MAX_RX_DESC_POLL 10
3295 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3296 struct ixgbe_ring *ring)
3298 struct ixgbe_hw *hw = &adapter->hw;
3299 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3301 u8 reg_idx = ring->reg_idx;
3303 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3304 if (hw->mac.type == ixgbe_mac_82598EB &&
3305 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3309 usleep_range(1000, 2000);
3310 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3311 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3314 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3315 "the polling period\n", reg_idx);
3319 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3320 struct ixgbe_ring *ring)
3322 struct ixgbe_hw *hw = &adapter->hw;
3323 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3325 u8 reg_idx = ring->reg_idx;
3327 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3328 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3330 /* write value back with RXDCTL.ENABLE bit cleared */
3331 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3333 if (hw->mac.type == ixgbe_mac_82598EB &&
3334 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3337 /* the hardware may take up to 100us to really disable the rx queue */
3340 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3341 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3344 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3345 "the polling period\n", reg_idx);
3349 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3350 struct ixgbe_ring *ring)
3352 struct ixgbe_hw *hw = &adapter->hw;
3353 u64 rdba = ring->dma;
3355 u8 reg_idx = ring->reg_idx;
3357 /* disable queue to avoid issues while updating state */
3358 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3359 ixgbe_disable_rx_queue(adapter, ring);
3361 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3362 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3363 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3364 ring->count * sizeof(union ixgbe_adv_rx_desc));
3365 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3366 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3367 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
3369 ixgbe_configure_srrctl(adapter, ring);
3370 ixgbe_configure_rscctl(adapter, ring);
3372 if (hw->mac.type == ixgbe_mac_82598EB) {
3374 * enable cache line friendly hardware writes:
3375 * PTHRESH=32 descriptors (half the internal cache),
3376 * this also removes ugly rx_no_buffer_count increment
3377 * HTHRESH=4 descriptors (to minimize latency on fetch)
3378 * WTHRESH=8 burst writeback up to two cache lines
3380 rxdctl &= ~0x3FFFFF;
3384 /* enable receive descriptor ring */
3385 rxdctl |= IXGBE_RXDCTL_ENABLE;
3386 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3388 ixgbe_rx_desc_queue_enable(adapter, ring);
3389 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
3392 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3394 struct ixgbe_hw *hw = &adapter->hw;
3395 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
3398 /* PSRTYPE must be initialized in non 82598 adapters */
3399 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3400 IXGBE_PSRTYPE_UDPHDR |
3401 IXGBE_PSRTYPE_IPV4HDR |
3402 IXGBE_PSRTYPE_L2HDR |
3403 IXGBE_PSRTYPE_IPV6HDR;
3405 if (hw->mac.type == ixgbe_mac_82598EB)
3413 for (p = 0; p < adapter->num_rx_pools; p++)
3414 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(p)),
3418 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3420 struct ixgbe_hw *hw = &adapter->hw;
3421 u32 reg_offset, vf_shift;
3422 u32 gcr_ext, vmdctl;
3425 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3428 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3429 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3430 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
3431 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
3432 vmdctl |= IXGBE_VT_CTL_REPLEN;
3433 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
3435 vf_shift = VMDQ_P(0) % 32;
3436 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
3438 /* Enable only the PF's pool for Tx/Rx */
3439 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3440 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3441 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3442 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
3443 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
3444 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3446 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3447 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
3450 * Set up VF register offsets for selected VT Mode,
3451 * i.e. 32 or 64 VFs for SR-IOV
3453 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3454 case IXGBE_82599_VMDQ_8Q_MASK:
3455 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3457 case IXGBE_82599_VMDQ_4Q_MASK:
3458 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3461 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3465 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3468 /* Enable MAC Anti-Spoofing */
3469 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
3471 /* For VFs that have spoof checking turned off */
3472 for (i = 0; i < adapter->num_vfs; i++) {
3473 if (!adapter->vfinfo[i].spoofchk_enabled)
3474 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3478 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3480 struct ixgbe_hw *hw = &adapter->hw;
3481 struct net_device *netdev = adapter->netdev;
3482 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3483 struct ixgbe_ring *rx_ring;
3488 /* adjust max frame to be able to do baby jumbo for FCoE */
3489 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3490 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3491 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3493 #endif /* IXGBE_FCOE */
3495 /* adjust max frame to be at least the size of a standard frame */
3496 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3497 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3499 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3500 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3501 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3502 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3504 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3507 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3508 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3509 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3510 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3513 * Setup the HW Rx Head and Tail Descriptor Pointers and
3514 * the Base and Length of the Rx Descriptor Ring
3516 for (i = 0; i < adapter->num_rx_queues; i++) {
3517 rx_ring = adapter->rx_ring[i];
3518 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3519 set_ring_rsc_enabled(rx_ring);
3521 clear_ring_rsc_enabled(rx_ring);
3525 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3527 struct ixgbe_hw *hw = &adapter->hw;
3528 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3530 switch (hw->mac.type) {
3531 case ixgbe_mac_82598EB:
3533 * For VMDq support of different descriptor types or
3534 * buffer sizes through the use of multiple SRRCTL
3535 * registers, RDRXCTL.MVMEN must be set to 1
3537 * also, the manual doesn't mention it clearly but DCA hints
3538 * will only use queue 0's tags unless this bit is set. Side
3539 * effects of setting this bit are only that SRRCTL must be
3540 * fully programmed [0..15]
3542 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3544 case ixgbe_mac_82599EB:
3545 case ixgbe_mac_X540:
3546 /* Disable RSC for ACK packets */
3547 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3548 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3549 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3550 /* hardware requires some bits to be set by default */
3551 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3552 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3555 /* We should do nothing since we don't know this hardware */
3559 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3563 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3564 * @adapter: board private structure
3566 * Configure the Rx unit of the MAC after a reset.
3568 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3570 struct ixgbe_hw *hw = &adapter->hw;
3574 /* disable receives while setting up the descriptors */
3575 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3576 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3578 ixgbe_setup_psrtype(adapter);
3579 ixgbe_setup_rdrxctl(adapter);
3582 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
3583 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
3584 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
3585 rfctl |= IXGBE_RFCTL_RSC_DIS;
3586 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
3588 /* Program registers for the distribution of queues */
3589 ixgbe_setup_mrqc(adapter);
3591 /* set_rx_buffer_len must be called before ring initialization */
3592 ixgbe_set_rx_buffer_len(adapter);
3595 * Setup the HW Rx Head and Tail Descriptor Pointers and
3596 * the Base and Length of the Rx Descriptor Ring
3598 for (i = 0; i < adapter->num_rx_queues; i++)
3599 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3601 /* disable drop enable for 82598 parts */
3602 if (hw->mac.type == ixgbe_mac_82598EB)
3603 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3605 /* enable all receives */
3606 rxctrl |= IXGBE_RXCTRL_RXEN;
3607 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3610 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3611 __be16 proto, u16 vid)
3613 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3614 struct ixgbe_hw *hw = &adapter->hw;
3616 /* add VID to filter table */
3617 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
3618 set_bit(vid, adapter->active_vlans);
3623 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
3624 __be16 proto, u16 vid)
3626 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3627 struct ixgbe_hw *hw = &adapter->hw;
3629 /* remove VID from filter table */
3630 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
3631 clear_bit(vid, adapter->active_vlans);
3637 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3638 * @adapter: driver data
3640 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3642 struct ixgbe_hw *hw = &adapter->hw;
3645 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3646 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3647 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3651 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3652 * @adapter: driver data
3654 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3656 struct ixgbe_hw *hw = &adapter->hw;
3659 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3660 vlnctrl |= IXGBE_VLNCTRL_VFE;
3661 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3662 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3666 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3667 * @adapter: driver data
3669 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3671 struct ixgbe_hw *hw = &adapter->hw;
3675 switch (hw->mac.type) {
3676 case ixgbe_mac_82598EB:
3677 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3678 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3679 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3681 case ixgbe_mac_82599EB:
3682 case ixgbe_mac_X540:
3683 for (i = 0; i < adapter->num_rx_queues; i++) {
3684 j = adapter->rx_ring[i]->reg_idx;
3685 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3686 vlnctrl &= ~IXGBE_RXDCTL_VME;
3687 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3696 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3697 * @adapter: driver data
3699 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3701 struct ixgbe_hw *hw = &adapter->hw;
3705 switch (hw->mac.type) {
3706 case ixgbe_mac_82598EB:
3707 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3708 vlnctrl |= IXGBE_VLNCTRL_VME;
3709 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3711 case ixgbe_mac_82599EB:
3712 case ixgbe_mac_X540:
3713 for (i = 0; i < adapter->num_rx_queues; i++) {
3714 j = adapter->rx_ring[i]->reg_idx;
3715 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3716 vlnctrl |= IXGBE_RXDCTL_VME;
3717 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3725 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3729 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
3731 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3732 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
3736 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3737 * @netdev: network interface device structure
3739 * Writes unicast address list to the RAR table.
3740 * Returns: -ENOMEM on failure/insufficient address space
3741 * 0 on no addresses written
3742 * X on writing X addresses to the RAR table
3744 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3746 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3747 struct ixgbe_hw *hw = &adapter->hw;
3748 unsigned int rar_entries = hw->mac.num_rar_entries - 1;
3751 /* In SR-IOV mode significantly less RAR entries are available */
3752 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3753 rar_entries = IXGBE_MAX_PF_MACVLANS - 1;
3755 /* return ENOMEM indicating insufficient memory for addresses */
3756 if (netdev_uc_count(netdev) > rar_entries)
3759 if (!netdev_uc_empty(netdev)) {
3760 struct netdev_hw_addr *ha;
3761 /* return error if we do not support writing to RAR table */
3762 if (!hw->mac.ops.set_rar)
3765 netdev_for_each_uc_addr(ha, netdev) {
3768 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3769 VMDQ_P(0), IXGBE_RAH_AV);
3773 /* write the addresses in reverse order to avoid write combining */
3774 for (; rar_entries > 0 ; rar_entries--)
3775 hw->mac.ops.clear_rar(hw, rar_entries);
3781 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3782 * @netdev: network interface device structure
3784 * The set_rx_method entry point is called whenever the unicast/multicast
3785 * address list or the network interface flags are updated. This routine is
3786 * responsible for configuring the hardware for proper unicast, multicast and
3789 void ixgbe_set_rx_mode(struct net_device *netdev)
3791 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3792 struct ixgbe_hw *hw = &adapter->hw;
3793 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3796 /* Check for Promiscuous and All Multicast modes */
3798 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3800 /* set all bits that we expect to always be set */
3801 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
3802 fctrl |= IXGBE_FCTRL_BAM;
3803 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3804 fctrl |= IXGBE_FCTRL_PMCF;
3806 /* clear the bits we are changing the status of */
3807 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3809 if (netdev->flags & IFF_PROMISC) {
3810 hw->addr_ctrl.user_set_promisc = true;
3811 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3812 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3813 /* Only disable hardware filter vlans in promiscuous mode
3814 * if SR-IOV and VMDQ are disabled - otherwise ensure
3815 * that hardware VLAN filters remain enabled.
3817 if (!(adapter->flags & (IXGBE_FLAG_VMDQ_ENABLED |
3818 IXGBE_FLAG_SRIOV_ENABLED)))
3819 ixgbe_vlan_filter_disable(adapter);
3821 ixgbe_vlan_filter_enable(adapter);
3823 if (netdev->flags & IFF_ALLMULTI) {
3824 fctrl |= IXGBE_FCTRL_MPE;
3825 vmolr |= IXGBE_VMOLR_MPE;
3827 ixgbe_vlan_filter_enable(adapter);
3828 hw->addr_ctrl.user_set_promisc = false;
3832 * Write addresses to available RAR registers, if there is not
3833 * sufficient space to store all the addresses then enable
3834 * unicast promiscuous mode
3836 count = ixgbe_write_uc_addr_list(netdev);
3838 fctrl |= IXGBE_FCTRL_UPE;
3839 vmolr |= IXGBE_VMOLR_ROPE;
3842 /* Write addresses to the MTA, if the attempt fails
3843 * then we should just turn on promiscuous mode so
3844 * that we can at least receive multicast traffic
3846 hw->mac.ops.update_mc_addr_list(hw, netdev);
3847 vmolr |= IXGBE_VMOLR_ROMPE;
3849 if (adapter->num_vfs)
3850 ixgbe_restore_vf_multicasts(adapter);
3852 if (hw->mac.type != ixgbe_mac_82598EB) {
3853 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
3854 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3856 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
3859 /* This is useful for sniffing bad packets. */
3860 if (adapter->netdev->features & NETIF_F_RXALL) {
3861 /* UPE and MPE will be handled by normal PROMISC logic
3862 * in e1000e_set_rx_mode */
3863 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3864 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3865 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3867 fctrl &= ~(IXGBE_FCTRL_DPF);
3868 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3871 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3873 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
3874 ixgbe_vlan_strip_enable(adapter);
3876 ixgbe_vlan_strip_disable(adapter);
3879 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3883 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
3884 ixgbe_qv_init_lock(adapter->q_vector[q_idx]);
3885 napi_enable(&adapter->q_vector[q_idx]->napi);
3889 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3893 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
3894 napi_disable(&adapter->q_vector[q_idx]->napi);
3895 while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) {
3896 pr_info("QV %d locked\n", q_idx);
3897 usleep_range(1000, 20000);
3902 #ifdef CONFIG_IXGBE_DCB
3904 * ixgbe_configure_dcb - Configure DCB hardware
3905 * @adapter: ixgbe adapter struct
3907 * This is called by the driver on open to configure the DCB hardware.
3908 * This is also called by the gennetlink interface when reconfiguring
3911 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3913 struct ixgbe_hw *hw = &adapter->hw;
3914 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3916 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3917 if (hw->mac.type == ixgbe_mac_82598EB)
3918 netif_set_gso_max_size(adapter->netdev, 65536);
3922 if (hw->mac.type == ixgbe_mac_82598EB)
3923 netif_set_gso_max_size(adapter->netdev, 32768);
3926 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3927 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3930 /* reconfigure the hardware */
3931 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
3932 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3934 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3936 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3937 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3938 ixgbe_dcb_hw_ets(&adapter->hw,
3939 adapter->ixgbe_ieee_ets,
3941 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3942 adapter->ixgbe_ieee_pfc->pfc_en,
3943 adapter->ixgbe_ieee_ets->prio_tc);
3946 /* Enable RSS Hash per TC */
3947 if (hw->mac.type != ixgbe_mac_82598EB) {
3949 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
3956 /* write msb to all 8 TCs in one write */
3957 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
3962 /* Additional bittime to account for IXGBE framing */
3963 #define IXGBE_ETH_FRAMING 20
3966 * ixgbe_hpbthresh - calculate high water mark for flow control
3968 * @adapter: board private structure to calculate for
3969 * @pb: packet buffer to calculate
3971 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3973 struct ixgbe_hw *hw = &adapter->hw;
3974 struct net_device *dev = adapter->netdev;
3975 int link, tc, kb, marker;
3978 /* Calculate max LAN frame size */
3979 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3982 /* FCoE traffic class uses FCOE jumbo frames */
3983 if ((dev->features & NETIF_F_FCOE_MTU) &&
3984 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
3985 (pb == ixgbe_fcoe_get_tc(adapter)))
3986 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3989 /* Calculate delay value for device */
3990 switch (hw->mac.type) {
3991 case ixgbe_mac_X540:
3992 dv_id = IXGBE_DV_X540(link, tc);
3995 dv_id = IXGBE_DV(link, tc);
3999 /* Loopback switch introduces additional latency */
4000 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4001 dv_id += IXGBE_B2BT(tc);
4003 /* Delay value is calculated in bit times convert to KB */
4004 kb = IXGBE_BT2KB(dv_id);
4005 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
4007 marker = rx_pba - kb;
4009 /* It is possible that the packet buffer is not large enough
4010 * to provide required headroom. In this case throw an error
4011 * to user and a do the best we can.
4014 e_warn(drv, "Packet Buffer(%i) can not provide enough"
4015 "headroom to support flow control."
4016 "Decrease MTU or number of traffic classes\n", pb);
4024 * ixgbe_lpbthresh - calculate low water mark for for flow control
4026 * @adapter: board private structure to calculate for
4027 * @pb: packet buffer to calculate
4029 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
4031 struct ixgbe_hw *hw = &adapter->hw;
4032 struct net_device *dev = adapter->netdev;
4036 /* Calculate max LAN frame size */
4037 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4039 /* Calculate delay value for device */
4040 switch (hw->mac.type) {
4041 case ixgbe_mac_X540:
4042 dv_id = IXGBE_LOW_DV_X540(tc);
4045 dv_id = IXGBE_LOW_DV(tc);
4049 /* Delay value is calculated in bit times convert to KB */
4050 return IXGBE_BT2KB(dv_id);
4054 * ixgbe_pbthresh_setup - calculate and setup high low water marks
4056 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
4058 struct ixgbe_hw *hw = &adapter->hw;
4059 int num_tc = netdev_get_num_tc(adapter->netdev);
4065 hw->fc.low_water = ixgbe_lpbthresh(adapter);
4067 for (i = 0; i < num_tc; i++) {
4068 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
4070 /* Low water marks must not be larger than high water marks */
4071 if (hw->fc.low_water > hw->fc.high_water[i])
4072 hw->fc.low_water = 0;
4076 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
4078 struct ixgbe_hw *hw = &adapter->hw;
4080 u8 tc = netdev_get_num_tc(adapter->netdev);
4082 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4083 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
4084 hdrm = 32 << adapter->fdir_pballoc;
4088 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
4089 ixgbe_pbthresh_setup(adapter);
4092 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
4094 struct ixgbe_hw *hw = &adapter->hw;
4095 struct hlist_node *node2;
4096 struct ixgbe_fdir_filter *filter;
4098 spin_lock(&adapter->fdir_perfect_lock);
4100 if (!hlist_empty(&adapter->fdir_filter_list))
4101 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
4103 hlist_for_each_entry_safe(filter, node2,
4104 &adapter->fdir_filter_list, fdir_node) {
4105 ixgbe_fdir_write_perfect_filter_82599(hw,
4108 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
4109 IXGBE_FDIR_DROP_QUEUE :
4110 adapter->rx_ring[filter->action]->reg_idx);
4113 spin_unlock(&adapter->fdir_perfect_lock);
4116 static void ixgbe_configure(struct ixgbe_adapter *adapter)
4118 struct ixgbe_hw *hw = &adapter->hw;
4120 ixgbe_configure_pb(adapter);
4121 #ifdef CONFIG_IXGBE_DCB
4122 ixgbe_configure_dcb(adapter);
4125 * We must restore virtualization before VLANs or else
4126 * the VLVF registers will not be populated
4128 ixgbe_configure_virtualization(adapter);
4130 ixgbe_set_rx_mode(adapter->netdev);
4131 ixgbe_restore_vlan(adapter);
4133 switch (hw->mac.type) {
4134 case ixgbe_mac_82599EB:
4135 case ixgbe_mac_X540:
4136 hw->mac.ops.disable_rx_buff(hw);
4142 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4143 ixgbe_init_fdir_signature_82599(&adapter->hw,
4144 adapter->fdir_pballoc);
4145 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
4146 ixgbe_init_fdir_perfect_82599(&adapter->hw,
4147 adapter->fdir_pballoc);
4148 ixgbe_fdir_filter_restore(adapter);
4151 switch (hw->mac.type) {
4152 case ixgbe_mac_82599EB:
4153 case ixgbe_mac_X540:
4154 hw->mac.ops.enable_rx_buff(hw);
4161 /* configure FCoE L2 filters, redirection table, and Rx control */
4162 ixgbe_configure_fcoe(adapter);
4164 #endif /* IXGBE_FCOE */
4165 ixgbe_configure_tx(adapter);
4166 ixgbe_configure_rx(adapter);
4169 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
4171 switch (hw->phy.type) {
4172 case ixgbe_phy_sfp_avago:
4173 case ixgbe_phy_sfp_ftl:
4174 case ixgbe_phy_sfp_intel:
4175 case ixgbe_phy_sfp_unknown:
4176 case ixgbe_phy_sfp_passive_tyco:
4177 case ixgbe_phy_sfp_passive_unknown:
4178 case ixgbe_phy_sfp_active_unknown:
4179 case ixgbe_phy_sfp_ftl_active:
4180 case ixgbe_phy_qsfp_passive_unknown:
4181 case ixgbe_phy_qsfp_active_unknown:
4182 case ixgbe_phy_qsfp_intel:
4183 case ixgbe_phy_qsfp_unknown:
4186 if (hw->mac.type == ixgbe_mac_82598EB)
4194 * ixgbe_sfp_link_config - set up SFP+ link
4195 * @adapter: pointer to private adapter struct
4197 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
4200 * We are assuming the worst case scenario here, and that
4201 * is that an SFP was inserted/removed after the reset
4202 * but before SFP detection was enabled. As such the best
4203 * solution is to just start searching as soon as we start
4205 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
4206 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
4208 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
4212 * ixgbe_non_sfp_link_config - set up non-SFP+ link
4213 * @hw: pointer to private hardware struct
4215 * Returns 0 on success, negative on failure
4217 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
4220 bool autoneg, link_up = false;
4221 u32 ret = IXGBE_ERR_LINK_SETUP;
4223 if (hw->mac.ops.check_link)
4224 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
4229 speed = hw->phy.autoneg_advertised;
4230 if ((!speed) && (hw->mac.ops.get_link_capabilities))
4231 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
4236 if (hw->mac.ops.setup_link)
4237 ret = hw->mac.ops.setup_link(hw, speed, link_up);
4242 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
4244 struct ixgbe_hw *hw = &adapter->hw;
4247 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4248 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4250 gpie |= IXGBE_GPIE_EIAME;
4252 * use EIAM to auto-mask when MSI-X interrupt is asserted
4253 * this saves a register write for every interrupt
4255 switch (hw->mac.type) {
4256 case ixgbe_mac_82598EB:
4257 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4259 case ixgbe_mac_82599EB:
4260 case ixgbe_mac_X540:
4262 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4263 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4267 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4268 * specifically only auto mask tx and rx interrupts */
4269 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4272 /* XXX: to interrupt immediately for EICS writes, enable this */
4273 /* gpie |= IXGBE_GPIE_EIMEN; */
4275 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4276 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
4278 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4279 case IXGBE_82599_VMDQ_8Q_MASK:
4280 gpie |= IXGBE_GPIE_VTMODE_16;
4282 case IXGBE_82599_VMDQ_4Q_MASK:
4283 gpie |= IXGBE_GPIE_VTMODE_32;
4286 gpie |= IXGBE_GPIE_VTMODE_64;
4291 /* Enable Thermal over heat sensor interrupt */
4292 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4293 switch (adapter->hw.mac.type) {
4294 case ixgbe_mac_82599EB:
4295 gpie |= IXGBE_SDP0_GPIEN;
4297 case ixgbe_mac_X540:
4298 gpie |= IXGBE_EIMS_TS;
4305 /* Enable fan failure interrupt */
4306 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
4307 gpie |= IXGBE_SDP1_GPIEN;
4309 if (hw->mac.type == ixgbe_mac_82599EB) {
4310 gpie |= IXGBE_SDP1_GPIEN;
4311 gpie |= IXGBE_SDP2_GPIEN;
4314 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4317 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
4319 struct ixgbe_hw *hw = &adapter->hw;
4323 ixgbe_get_hw_control(adapter);
4324 ixgbe_setup_gpie(adapter);
4326 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4327 ixgbe_configure_msix(adapter);
4329 ixgbe_configure_msi_and_legacy(adapter);
4331 /* enable the optics for 82599 SFP+ fiber */
4332 if (hw->mac.ops.enable_tx_laser)
4333 hw->mac.ops.enable_tx_laser(hw);
4335 clear_bit(__IXGBE_DOWN, &adapter->state);
4336 ixgbe_napi_enable_all(adapter);
4338 if (ixgbe_is_sfp(hw)) {
4339 ixgbe_sfp_link_config(adapter);
4341 err = ixgbe_non_sfp_link_config(hw);
4343 e_err(probe, "link_config FAILED %d\n", err);
4346 /* clear any pending interrupts, may auto mask */
4347 IXGBE_READ_REG(hw, IXGBE_EICR);
4348 ixgbe_irq_enable(adapter, true, true);
4351 * If this adapter has a fan, check to see if we had a failure
4352 * before we enabled the interrupt.
4354 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4355 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4356 if (esdp & IXGBE_ESDP_SDP1)
4357 e_crit(drv, "Fan has stopped, replace the adapter\n");
4360 /* enable transmits */
4361 netif_tx_start_all_queues(adapter->netdev);
4363 /* bring the link up in the watchdog, this could race with our first
4364 * link up interrupt but shouldn't be a problem */
4365 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4366 adapter->link_check_timeout = jiffies;
4367 mod_timer(&adapter->service_timer, jiffies);
4369 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4370 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4371 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4372 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
4375 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4377 WARN_ON(in_interrupt());
4378 /* put off any impending NetWatchDogTimeout */
4379 adapter->netdev->trans_start = jiffies;
4381 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
4382 usleep_range(1000, 2000);
4383 ixgbe_down(adapter);
4385 * If SR-IOV enabled then wait a bit before bringing the adapter
4386 * back up to give the VFs time to respond to the reset. The
4387 * two second wait is based upon the watchdog timer cycle in
4390 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4393 clear_bit(__IXGBE_RESETTING, &adapter->state);
4396 void ixgbe_up(struct ixgbe_adapter *adapter)
4398 /* hardware has been reset, we need to reload some things */
4399 ixgbe_configure(adapter);
4401 ixgbe_up_complete(adapter);
4404 void ixgbe_reset(struct ixgbe_adapter *adapter)
4406 struct ixgbe_hw *hw = &adapter->hw;
4409 /* lock SFP init bit to prevent race conditions with the watchdog */
4410 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4411 usleep_range(1000, 2000);
4413 /* clear all SFP and link config related flags while holding SFP_INIT */
4414 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4415 IXGBE_FLAG2_SFP_NEEDS_RESET);
4416 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4418 err = hw->mac.ops.init_hw(hw);
4421 case IXGBE_ERR_SFP_NOT_PRESENT:
4422 case IXGBE_ERR_SFP_NOT_SUPPORTED:
4424 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
4425 e_dev_err("master disable timed out\n");
4427 case IXGBE_ERR_EEPROM_VERSION:
4428 /* We are running on a pre-production device, log a warning */
4429 e_dev_warn("This device is a pre-production adapter/LOM. "
4430 "Please be aware there may be issues associated with "
4431 "your hardware. If you are experiencing problems "
4432 "please contact your Intel or hardware "
4433 "representative who provided you with this "
4437 e_dev_err("Hardware Error: %d\n", err);
4440 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4442 /* reprogram the RAR[0] in case user changed it. */
4443 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
4445 /* update SAN MAC vmdq pool selection */
4446 if (hw->mac.san_mac_rar_index)
4447 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
4449 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
4450 ixgbe_ptp_reset(adapter);
4454 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4455 * @rx_ring: ring to free buffers from
4457 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4459 struct device *dev = rx_ring->dev;
4463 /* ring already cleared, nothing to do */
4464 if (!rx_ring->rx_buffer_info)
4467 /* Free all the Rx ring sk_buffs */
4468 for (i = 0; i < rx_ring->count; i++) {
4469 struct ixgbe_rx_buffer *rx_buffer;
4471 rx_buffer = &rx_ring->rx_buffer_info[i];
4472 if (rx_buffer->skb) {
4473 struct sk_buff *skb = rx_buffer->skb;
4474 if (IXGBE_CB(skb)->page_released) {
4477 ixgbe_rx_bufsz(rx_ring),
4479 IXGBE_CB(skb)->page_released = false;
4483 rx_buffer->skb = NULL;
4485 dma_unmap_page(dev, rx_buffer->dma,
4486 ixgbe_rx_pg_size(rx_ring),
4489 if (rx_buffer->page)
4490 __free_pages(rx_buffer->page,
4491 ixgbe_rx_pg_order(rx_ring));
4492 rx_buffer->page = NULL;
4495 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4496 memset(rx_ring->rx_buffer_info, 0, size);
4498 /* Zero out the descriptor ring */
4499 memset(rx_ring->desc, 0, rx_ring->size);
4501 rx_ring->next_to_alloc = 0;
4502 rx_ring->next_to_clean = 0;
4503 rx_ring->next_to_use = 0;
4507 * ixgbe_clean_tx_ring - Free Tx Buffers
4508 * @tx_ring: ring to be cleaned
4510 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4512 struct ixgbe_tx_buffer *tx_buffer_info;
4516 /* ring already cleared, nothing to do */
4517 if (!tx_ring->tx_buffer_info)
4520 /* Free all the Tx ring sk_buffs */
4521 for (i = 0; i < tx_ring->count; i++) {
4522 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4523 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4526 netdev_tx_reset_queue(txring_txq(tx_ring));
4528 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4529 memset(tx_ring->tx_buffer_info, 0, size);
4531 /* Zero out the descriptor ring */
4532 memset(tx_ring->desc, 0, tx_ring->size);
4534 tx_ring->next_to_use = 0;
4535 tx_ring->next_to_clean = 0;
4539 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4540 * @adapter: board private structure
4542 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4546 for (i = 0; i < adapter->num_rx_queues; i++)
4547 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4551 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4552 * @adapter: board private structure
4554 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4558 for (i = 0; i < adapter->num_tx_queues; i++)
4559 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4562 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4564 struct hlist_node *node2;
4565 struct ixgbe_fdir_filter *filter;
4567 spin_lock(&adapter->fdir_perfect_lock);
4569 hlist_for_each_entry_safe(filter, node2,
4570 &adapter->fdir_filter_list, fdir_node) {
4571 hlist_del(&filter->fdir_node);
4574 adapter->fdir_filter_count = 0;
4576 spin_unlock(&adapter->fdir_perfect_lock);
4579 void ixgbe_down(struct ixgbe_adapter *adapter)
4581 struct net_device *netdev = adapter->netdev;
4582 struct ixgbe_hw *hw = &adapter->hw;
4586 /* signal that we are down to the interrupt handler */
4587 set_bit(__IXGBE_DOWN, &adapter->state);
4589 /* disable receives */
4590 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4591 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4593 /* disable all enabled rx queues */
4594 for (i = 0; i < adapter->num_rx_queues; i++)
4595 /* this call also flushes the previous write */
4596 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4598 usleep_range(10000, 20000);
4600 netif_tx_stop_all_queues(netdev);
4602 /* call carrier off first to avoid false dev_watchdog timeouts */
4603 netif_carrier_off(netdev);
4604 netif_tx_disable(netdev);
4606 ixgbe_irq_disable(adapter);
4608 ixgbe_napi_disable_all(adapter);
4610 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4611 IXGBE_FLAG2_RESET_REQUESTED);
4612 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4614 del_timer_sync(&adapter->service_timer);
4616 if (adapter->num_vfs) {
4617 /* Clear EITR Select mapping */
4618 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
4620 /* Mark all the VFs as inactive */
4621 for (i = 0 ; i < adapter->num_vfs; i++)
4622 adapter->vfinfo[i].clear_to_send = false;
4624 /* ping all the active vfs to let them know we are going down */
4625 ixgbe_ping_all_vfs(adapter);
4627 /* Disable all VFTE/VFRE TX/RX */
4628 ixgbe_disable_tx_rx(adapter);
4631 /* disable transmits in the hardware now that interrupts are off */
4632 for (i = 0; i < adapter->num_tx_queues; i++) {
4633 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4634 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
4637 /* Disable the Tx DMA engine on 82599 and X540 */
4638 switch (hw->mac.type) {
4639 case ixgbe_mac_82599EB:
4640 case ixgbe_mac_X540:
4641 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4642 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4643 ~IXGBE_DMATXCTL_TE));
4649 if (!pci_channel_offline(adapter->pdev))
4650 ixgbe_reset(adapter);
4652 /* power down the optics for 82599 SFP+ fiber */
4653 if (hw->mac.ops.disable_tx_laser)
4654 hw->mac.ops.disable_tx_laser(hw);
4656 ixgbe_clean_all_tx_rings(adapter);
4657 ixgbe_clean_all_rx_rings(adapter);
4659 #ifdef CONFIG_IXGBE_DCA
4660 /* since we reset the hardware DCA settings were cleared */
4661 ixgbe_setup_dca(adapter);
4666 * ixgbe_tx_timeout - Respond to a Tx Hang
4667 * @netdev: network interface device structure
4669 static void ixgbe_tx_timeout(struct net_device *netdev)
4671 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4673 /* Do the reset outside of interrupt context */
4674 ixgbe_tx_timeout_reset(adapter);
4678 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4679 * @adapter: board private structure to initialize
4681 * ixgbe_sw_init initializes the Adapter private data structure.
4682 * Fields are initialized based on PCI device information and
4683 * OS network device settings (MTU size).
4685 static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
4687 struct ixgbe_hw *hw = &adapter->hw;
4688 struct pci_dev *pdev = adapter->pdev;
4689 unsigned int rss, fdir;
4691 #ifdef CONFIG_IXGBE_DCB
4693 struct tc_configuration *tc;
4696 /* PCI config space info */
4698 hw->vendor_id = pdev->vendor;
4699 hw->device_id = pdev->device;
4700 hw->revision_id = pdev->revision;
4701 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4702 hw->subsystem_device_id = pdev->subsystem_device;
4704 /* Set common capability flags and settings */
4705 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
4706 adapter->ring_feature[RING_F_RSS].limit = rss;
4707 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4708 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4709 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
4710 adapter->atr_sample_rate = 20;
4711 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
4712 adapter->ring_feature[RING_F_FDIR].limit = fdir;
4713 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
4714 #ifdef CONFIG_IXGBE_DCA
4715 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
4718 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4719 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4720 #ifdef CONFIG_IXGBE_DCB
4721 /* Default traffic class to use for FCoE */
4722 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4723 #endif /* CONFIG_IXGBE_DCB */
4724 #endif /* IXGBE_FCOE */
4726 /* Set MAC specific capability flags and exceptions */
4727 switch (hw->mac.type) {
4728 case ixgbe_mac_82598EB:
4729 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
4730 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
4732 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4733 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4735 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
4736 adapter->ring_feature[RING_F_FDIR].limit = 0;
4737 adapter->atr_sample_rate = 0;
4738 adapter->fdir_pballoc = 0;
4740 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
4741 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4742 #ifdef CONFIG_IXGBE_DCB
4743 adapter->fcoe.up = 0;
4744 #endif /* IXGBE_DCB */
4745 #endif /* IXGBE_FCOE */
4747 case ixgbe_mac_82599EB:
4748 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4749 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4751 case ixgbe_mac_X540:
4752 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
4753 if (fwsm & IXGBE_FWSM_TS_ENABLED)
4754 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4761 /* FCoE support exists, always init the FCoE lock */
4762 spin_lock_init(&adapter->fcoe.lock);
4765 /* n-tuple support exists, always init our spinlock */
4766 spin_lock_init(&adapter->fdir_perfect_lock);
4768 #ifdef CONFIG_IXGBE_DCB
4769 switch (hw->mac.type) {
4770 case ixgbe_mac_X540:
4771 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
4772 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
4775 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
4776 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
4780 /* Configure DCB traffic classes */
4781 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4782 tc = &adapter->dcb_cfg.tc_config[j];
4783 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4784 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4785 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4786 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4787 tc->dcb_pfc = pfc_disabled;
4790 /* Initialize default user to priority mapping, UPx->TC0 */
4791 tc = &adapter->dcb_cfg.tc_config[0];
4792 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
4793 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
4795 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4796 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4797 adapter->dcb_cfg.pfc_mode_enable = false;
4798 adapter->dcb_set_bitmap = 0x00;
4799 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
4800 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
4801 sizeof(adapter->temp_dcb_cfg));
4805 /* default flow control settings */
4806 hw->fc.requested_mode = ixgbe_fc_full;
4807 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
4808 ixgbe_pbthresh_setup(adapter);
4809 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4810 hw->fc.send_xon = true;
4811 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
4813 #ifdef CONFIG_PCI_IOV
4814 /* assign number of SR-IOV VFs */
4815 if (hw->mac.type != ixgbe_mac_82598EB)
4816 adapter->num_vfs = (max_vfs > 63) ? 0 : max_vfs;
4819 /* enable itr by default in dynamic mode */
4820 adapter->rx_itr_setting = 1;
4821 adapter->tx_itr_setting = 1;
4823 /* set default ring sizes */
4824 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4825 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4827 /* set default work limits */
4828 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
4830 /* initialize eeprom parameters */
4831 if (ixgbe_init_eeprom_params_generic(hw)) {
4832 e_dev_err("EEPROM initialization failed\n");
4836 set_bit(__IXGBE_DOWN, &adapter->state);
4842 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4843 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4845 * Return 0 on success, negative on failure
4847 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
4849 struct device *dev = tx_ring->dev;
4850 int orig_node = dev_to_node(dev);
4854 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4856 if (tx_ring->q_vector)
4857 numa_node = tx_ring->q_vector->numa_node;
4859 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
4860 if (!tx_ring->tx_buffer_info)
4861 tx_ring->tx_buffer_info = vzalloc(size);
4862 if (!tx_ring->tx_buffer_info)
4865 /* round up to nearest 4K */
4866 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4867 tx_ring->size = ALIGN(tx_ring->size, 4096);
4869 set_dev_node(dev, numa_node);
4870 tx_ring->desc = dma_alloc_coherent(dev,
4874 set_dev_node(dev, orig_node);
4876 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4877 &tx_ring->dma, GFP_KERNEL);
4881 tx_ring->next_to_use = 0;
4882 tx_ring->next_to_clean = 0;
4886 vfree(tx_ring->tx_buffer_info);
4887 tx_ring->tx_buffer_info = NULL;
4888 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
4893 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4894 * @adapter: board private structure
4896 * If this function returns with an error, then it's possible one or
4897 * more of the rings is populated (while the rest are not). It is the
4898 * callers duty to clean those orphaned rings.
4900 * Return 0 on success, negative on failure
4902 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4906 for (i = 0; i < adapter->num_tx_queues; i++) {
4907 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
4911 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
4917 /* rewind the index freeing the rings as we go */
4919 ixgbe_free_tx_resources(adapter->tx_ring[i]);
4924 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4925 * @rx_ring: rx descriptor ring (for a specific queue) to setup
4927 * Returns 0 on success, negative on failure
4929 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
4931 struct device *dev = rx_ring->dev;
4932 int orig_node = dev_to_node(dev);
4936 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4938 if (rx_ring->q_vector)
4939 numa_node = rx_ring->q_vector->numa_node;
4941 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
4942 if (!rx_ring->rx_buffer_info)
4943 rx_ring->rx_buffer_info = vzalloc(size);
4944 if (!rx_ring->rx_buffer_info)
4947 /* Round up to nearest 4K */
4948 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4949 rx_ring->size = ALIGN(rx_ring->size, 4096);
4951 set_dev_node(dev, numa_node);
4952 rx_ring->desc = dma_alloc_coherent(dev,
4956 set_dev_node(dev, orig_node);
4958 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4959 &rx_ring->dma, GFP_KERNEL);
4963 rx_ring->next_to_clean = 0;
4964 rx_ring->next_to_use = 0;
4968 vfree(rx_ring->rx_buffer_info);
4969 rx_ring->rx_buffer_info = NULL;
4970 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
4975 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4976 * @adapter: board private structure
4978 * If this function returns with an error, then it's possible one or
4979 * more of the rings is populated (while the rest are not). It is the
4980 * callers duty to clean those orphaned rings.
4982 * Return 0 on success, negative on failure
4984 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4988 for (i = 0; i < adapter->num_rx_queues; i++) {
4989 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
4993 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
4998 err = ixgbe_setup_fcoe_ddp_resources(adapter);
5003 /* rewind the index freeing the rings as we go */
5005 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5010 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5011 * @tx_ring: Tx descriptor ring for a specific queue
5013 * Free all transmit software resources
5015 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5017 ixgbe_clean_tx_ring(tx_ring);
5019 vfree(tx_ring->tx_buffer_info);
5020 tx_ring->tx_buffer_info = NULL;
5022 /* if not set, then don't free */
5026 dma_free_coherent(tx_ring->dev, tx_ring->size,
5027 tx_ring->desc, tx_ring->dma);
5029 tx_ring->desc = NULL;
5033 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5034 * @adapter: board private structure
5036 * Free all transmit software resources
5038 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5042 for (i = 0; i < adapter->num_tx_queues; i++)
5043 if (adapter->tx_ring[i]->desc)
5044 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5048 * ixgbe_free_rx_resources - Free Rx Resources
5049 * @rx_ring: ring to clean the resources from
5051 * Free all receive software resources
5053 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5055 ixgbe_clean_rx_ring(rx_ring);
5057 vfree(rx_ring->rx_buffer_info);
5058 rx_ring->rx_buffer_info = NULL;
5060 /* if not set, then don't free */
5064 dma_free_coherent(rx_ring->dev, rx_ring->size,
5065 rx_ring->desc, rx_ring->dma);
5067 rx_ring->desc = NULL;
5071 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5072 * @adapter: board private structure
5074 * Free all receive software resources
5076 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5081 ixgbe_free_fcoe_ddp_resources(adapter);
5084 for (i = 0; i < adapter->num_rx_queues; i++)
5085 if (adapter->rx_ring[i]->desc)
5086 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5090 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5091 * @netdev: network interface device structure
5092 * @new_mtu: new value for maximum frame size
5094 * Returns 0 on success, negative on failure
5096 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5098 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5099 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5101 /* MTU < 68 is an error and causes problems on some kernels */
5102 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5106 * For 82599EB we cannot allow legacy VFs to enable their receive
5107 * paths when MTU greater than 1500 is configured. So display a
5108 * warning that legacy VFs will be disabled.
5110 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
5111 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
5112 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
5113 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
5115 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5117 /* must set new MTU before calling down or up */
5118 netdev->mtu = new_mtu;
5120 if (netif_running(netdev))
5121 ixgbe_reinit_locked(adapter);
5127 * ixgbe_open - Called when a network interface is made active
5128 * @netdev: network interface device structure
5130 * Returns 0 on success, negative value on failure
5132 * The open entry point is called when a network interface is made
5133 * active by the system (IFF_UP). At this point all resources needed
5134 * for transmit and receive operations are allocated, the interrupt
5135 * handler is registered with the OS, the watchdog timer is started,
5136 * and the stack is notified that the interface is ready.
5138 static int ixgbe_open(struct net_device *netdev)
5140 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5143 /* disallow open during test */
5144 if (test_bit(__IXGBE_TESTING, &adapter->state))
5147 netif_carrier_off(netdev);
5149 /* allocate transmit descriptors */
5150 err = ixgbe_setup_all_tx_resources(adapter);
5154 /* allocate receive descriptors */
5155 err = ixgbe_setup_all_rx_resources(adapter);
5159 ixgbe_configure(adapter);
5161 err = ixgbe_request_irq(adapter);
5165 /* Notify the stack of the actual queue counts. */
5166 err = netif_set_real_num_tx_queues(netdev,
5167 adapter->num_rx_pools > 1 ? 1 :
5168 adapter->num_tx_queues);
5170 goto err_set_queues;
5173 err = netif_set_real_num_rx_queues(netdev,
5174 adapter->num_rx_pools > 1 ? 1 :
5175 adapter->num_rx_queues);
5177 goto err_set_queues;
5179 ixgbe_ptp_init(adapter);
5181 ixgbe_up_complete(adapter);
5186 ixgbe_free_irq(adapter);
5188 ixgbe_free_all_rx_resources(adapter);
5190 ixgbe_free_all_tx_resources(adapter);
5192 ixgbe_reset(adapter);
5198 * ixgbe_close - Disables a network interface
5199 * @netdev: network interface device structure
5201 * Returns 0, this is not allowed to fail
5203 * The close entry point is called when an interface is de-activated
5204 * by the OS. The hardware is still under the drivers control, but
5205 * needs to be disabled. A global MAC reset is issued to stop the
5206 * hardware, and all transmit and receive resources are freed.
5208 static int ixgbe_close(struct net_device *netdev)
5210 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5212 ixgbe_ptp_stop(adapter);
5214 ixgbe_down(adapter);
5215 ixgbe_free_irq(adapter);
5217 ixgbe_fdir_filter_exit(adapter);
5219 ixgbe_free_all_tx_resources(adapter);
5220 ixgbe_free_all_rx_resources(adapter);
5222 ixgbe_release_hw_control(adapter);
5228 static int ixgbe_resume(struct pci_dev *pdev)
5230 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5231 struct net_device *netdev = adapter->netdev;
5234 pci_set_power_state(pdev, PCI_D0);
5235 pci_restore_state(pdev);
5237 * pci_restore_state clears dev->state_saved so call
5238 * pci_save_state to restore it.
5240 pci_save_state(pdev);
5242 err = pci_enable_device_mem(pdev);
5244 e_dev_err("Cannot enable PCI device from suspend\n");
5247 pci_set_master(pdev);
5249 pci_wake_from_d3(pdev, false);
5251 ixgbe_reset(adapter);
5253 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5256 err = ixgbe_init_interrupt_scheme(adapter);
5257 if (!err && netif_running(netdev))
5258 err = ixgbe_open(netdev);
5265 netif_device_attach(netdev);
5269 #endif /* CONFIG_PM */
5271 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5273 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5274 struct net_device *netdev = adapter->netdev;
5275 struct ixgbe_hw *hw = &adapter->hw;
5277 u32 wufc = adapter->wol;
5282 netif_device_detach(netdev);
5285 if (netif_running(netdev)) {
5286 ixgbe_down(adapter);
5287 ixgbe_free_irq(adapter);
5288 ixgbe_free_all_tx_resources(adapter);
5289 ixgbe_free_all_rx_resources(adapter);
5293 ixgbe_clear_interrupt_scheme(adapter);
5296 retval = pci_save_state(pdev);
5301 if (hw->mac.ops.stop_link_on_d3)
5302 hw->mac.ops.stop_link_on_d3(hw);
5305 ixgbe_set_rx_mode(netdev);
5307 /* enable the optics for 82599 SFP+ fiber as we can WoL */
5308 if (hw->mac.ops.enable_tx_laser)
5309 hw->mac.ops.enable_tx_laser(hw);
5311 /* turn on all-multi mode if wake on multicast is enabled */
5312 if (wufc & IXGBE_WUFC_MC) {
5313 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5314 fctrl |= IXGBE_FCTRL_MPE;
5315 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5318 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5319 ctrl |= IXGBE_CTRL_GIO_DIS;
5320 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5322 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5324 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5325 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5328 switch (hw->mac.type) {
5329 case ixgbe_mac_82598EB:
5330 pci_wake_from_d3(pdev, false);
5332 case ixgbe_mac_82599EB:
5333 case ixgbe_mac_X540:
5334 pci_wake_from_d3(pdev, !!wufc);
5340 *enable_wake = !!wufc;
5342 ixgbe_release_hw_control(adapter);
5344 pci_disable_device(pdev);
5350 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5355 retval = __ixgbe_shutdown(pdev, &wake);
5360 pci_prepare_to_sleep(pdev);
5362 pci_wake_from_d3(pdev, false);
5363 pci_set_power_state(pdev, PCI_D3hot);
5368 #endif /* CONFIG_PM */
5370 static void ixgbe_shutdown(struct pci_dev *pdev)
5374 __ixgbe_shutdown(pdev, &wake);
5376 if (system_state == SYSTEM_POWER_OFF) {
5377 pci_wake_from_d3(pdev, wake);
5378 pci_set_power_state(pdev, PCI_D3hot);
5383 * ixgbe_update_stats - Update the board statistics counters.
5384 * @adapter: board private structure
5386 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5388 struct net_device *netdev = adapter->netdev;
5389 struct ixgbe_hw *hw = &adapter->hw;
5390 struct ixgbe_hw_stats *hwstats = &adapter->stats;
5392 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5393 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5394 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5395 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
5397 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5398 test_bit(__IXGBE_RESETTING, &adapter->state))
5401 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5404 for (i = 0; i < adapter->num_rx_queues; i++) {
5405 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5406 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5408 adapter->rsc_total_count = rsc_count;
5409 adapter->rsc_total_flush = rsc_flush;
5412 for (i = 0; i < adapter->num_rx_queues; i++) {
5413 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5414 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5415 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5416 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5417 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5418 bytes += rx_ring->stats.bytes;
5419 packets += rx_ring->stats.packets;
5421 adapter->non_eop_descs = non_eop_descs;
5422 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5423 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5424 adapter->hw_csum_rx_error = hw_csum_rx_error;
5425 netdev->stats.rx_bytes = bytes;
5426 netdev->stats.rx_packets = packets;
5430 /* gather some stats to the adapter struct that are per queue */
5431 for (i = 0; i < adapter->num_tx_queues; i++) {
5432 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5433 restart_queue += tx_ring->tx_stats.restart_queue;
5434 tx_busy += tx_ring->tx_stats.tx_busy;
5435 bytes += tx_ring->stats.bytes;
5436 packets += tx_ring->stats.packets;
5438 adapter->restart_queue = restart_queue;
5439 adapter->tx_busy = tx_busy;
5440 netdev->stats.tx_bytes = bytes;
5441 netdev->stats.tx_packets = packets;
5443 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5445 /* 8 register reads */
5446 for (i = 0; i < 8; i++) {
5447 /* for packet buffers not used, the register should read 0 */
5448 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5450 hwstats->mpc[i] += mpc;
5451 total_mpc += hwstats->mpc[i];
5452 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5453 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5454 switch (hw->mac.type) {
5455 case ixgbe_mac_82598EB:
5456 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5457 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5458 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5459 hwstats->pxonrxc[i] +=
5460 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5462 case ixgbe_mac_82599EB:
5463 case ixgbe_mac_X540:
5464 hwstats->pxonrxc[i] +=
5465 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5472 /*16 register reads */
5473 for (i = 0; i < 16; i++) {
5474 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5475 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5476 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5477 (hw->mac.type == ixgbe_mac_X540)) {
5478 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5479 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5480 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5481 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5485 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5486 /* work around hardware counting issue */
5487 hwstats->gprc -= missed_rx;
5489 ixgbe_update_xoff_received(adapter);
5491 /* 82598 hardware only has a 32 bit counter in the high register */
5492 switch (hw->mac.type) {
5493 case ixgbe_mac_82598EB:
5494 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5495 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5496 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5497 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5499 case ixgbe_mac_X540:
5500 /* OS2BMC stats are X540 only*/
5501 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5502 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5503 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5504 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5505 case ixgbe_mac_82599EB:
5506 for (i = 0; i < 16; i++)
5507 adapter->hw_rx_no_dma_resources +=
5508 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5509 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5510 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5511 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5512 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5513 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5514 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5515 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5516 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5517 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5519 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5520 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5521 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5522 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5523 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5524 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5525 /* Add up per cpu counters for total ddp aloc fail */
5526 if (adapter->fcoe.ddp_pool) {
5527 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5528 struct ixgbe_fcoe_ddp_pool *ddp_pool;
5530 u64 noddp = 0, noddp_ext_buff = 0;
5531 for_each_possible_cpu(cpu) {
5532 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
5533 noddp += ddp_pool->noddp;
5534 noddp_ext_buff += ddp_pool->noddp_ext_buff;
5536 hwstats->fcoe_noddp = noddp;
5537 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
5539 #endif /* IXGBE_FCOE */
5544 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5545 hwstats->bprc += bprc;
5546 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5547 if (hw->mac.type == ixgbe_mac_82598EB)
5548 hwstats->mprc -= bprc;
5549 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5550 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5551 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5552 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5553 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5554 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5555 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5556 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5557 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5558 hwstats->lxontxc += lxon;
5559 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5560 hwstats->lxofftxc += lxoff;
5561 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5562 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5564 * 82598 errata - tx of flow control packets is included in tx counters
5566 xon_off_tot = lxon + lxoff;
5567 hwstats->gptc -= xon_off_tot;
5568 hwstats->mptc -= xon_off_tot;
5569 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5570 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5571 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5572 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5573 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5574 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5575 hwstats->ptc64 -= xon_off_tot;
5576 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5577 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5578 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5579 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5580 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5581 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5583 /* Fill out the OS statistics structure */
5584 netdev->stats.multicast = hwstats->mprc;
5587 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5588 netdev->stats.rx_dropped = 0;
5589 netdev->stats.rx_length_errors = hwstats->rlec;
5590 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5591 netdev->stats.rx_missed_errors = total_mpc;
5595 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5596 * @adapter: pointer to the device adapter structure
5598 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5600 struct ixgbe_hw *hw = &adapter->hw;
5603 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5606 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5608 /* if interface is down do nothing */
5609 if (test_bit(__IXGBE_DOWN, &adapter->state))
5612 /* do nothing if we are not using signature filters */
5613 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5616 adapter->fdir_overflow++;
5618 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5619 for (i = 0; i < adapter->num_tx_queues; i++)
5620 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5621 &(adapter->tx_ring[i]->state));
5622 /* re-enable flow director interrupts */
5623 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5625 e_err(probe, "failed to finish FDIR re-initialization, "
5626 "ignored adding FDIR ATR filters\n");
5631 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5632 * @adapter: pointer to the device adapter structure
5634 * This function serves two purposes. First it strobes the interrupt lines
5635 * in order to make certain interrupts are occurring. Secondly it sets the
5636 * bits needed to check for TX hangs. As a result we should immediately
5637 * determine if a hang has occurred.
5639 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5641 struct ixgbe_hw *hw = &adapter->hw;
5645 /* If we're down or resetting, just bail */
5646 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5647 test_bit(__IXGBE_RESETTING, &adapter->state))
5650 /* Force detection of hung controller */
5651 if (netif_carrier_ok(adapter->netdev)) {
5652 for (i = 0; i < adapter->num_tx_queues; i++)
5653 set_check_for_tx_hang(adapter->tx_ring[i]);
5656 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5658 * for legacy and MSI interrupts don't set any bits
5659 * that are enabled for EIAM, because this operation
5660 * would set *both* EIMS and EICS for any bit in EIAM
5662 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5663 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5665 /* get one bit for every active tx/rx interrupt vector */
5666 for (i = 0; i < adapter->num_q_vectors; i++) {
5667 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5668 if (qv->rx.ring || qv->tx.ring)
5669 eics |= ((u64)1 << i);
5673 /* Cause software interrupt to ensure rings are cleaned */
5674 ixgbe_irq_rearm_queues(adapter, eics);
5679 * ixgbe_watchdog_update_link - update the link status
5680 * @adapter: pointer to the device adapter structure
5681 * @link_speed: pointer to a u32 to store the link_speed
5683 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
5685 struct ixgbe_hw *hw = &adapter->hw;
5686 u32 link_speed = adapter->link_speed;
5687 bool link_up = adapter->link_up;
5688 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
5690 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5693 if (hw->mac.ops.check_link) {
5694 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5696 /* always assume link is up, if no check link function */
5697 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5701 if (adapter->ixgbe_ieee_pfc)
5702 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
5704 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
5705 hw->mac.ops.fc_enable(hw);
5706 ixgbe_set_rx_drop_en(adapter);
5710 time_after(jiffies, (adapter->link_check_timeout +
5711 IXGBE_TRY_LINK_TIMEOUT))) {
5712 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5713 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5714 IXGBE_WRITE_FLUSH(hw);
5717 adapter->link_up = link_up;
5718 adapter->link_speed = link_speed;
5721 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
5723 #ifdef CONFIG_IXGBE_DCB
5724 struct net_device *netdev = adapter->netdev;
5725 struct dcb_app app = {
5726 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
5731 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
5732 up = dcb_ieee_getapp_mask(netdev, &app);
5734 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
5739 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5740 * print link up message
5741 * @adapter: pointer to the device adapter structure
5743 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
5745 struct net_device *netdev = adapter->netdev;
5746 struct ixgbe_hw *hw = &adapter->hw;
5747 u32 link_speed = adapter->link_speed;
5748 bool flow_rx, flow_tx;
5750 /* only continue if link was previously down */
5751 if (netif_carrier_ok(netdev))
5754 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
5756 switch (hw->mac.type) {
5757 case ixgbe_mac_82598EB: {
5758 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5759 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5760 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5761 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5764 case ixgbe_mac_X540:
5765 case ixgbe_mac_82599EB: {
5766 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5767 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5768 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5769 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5778 adapter->last_rx_ptp_check = jiffies;
5780 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
5781 ixgbe_ptp_start_cyclecounter(adapter);
5783 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5784 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5786 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5788 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5791 ((flow_rx && flow_tx) ? "RX/TX" :
5793 (flow_tx ? "TX" : "None"))));
5795 netif_carrier_on(netdev);
5796 ixgbe_check_vf_rate_limit(adapter);
5798 /* update the default user priority for VFs */
5799 ixgbe_update_default_up(adapter);
5801 /* ping all the active vfs to let them know link has changed */
5802 ixgbe_ping_all_vfs(adapter);
5806 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5807 * print link down message
5808 * @adapter: pointer to the adapter structure
5810 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
5812 struct net_device *netdev = adapter->netdev;
5813 struct ixgbe_hw *hw = &adapter->hw;
5815 adapter->link_up = false;
5816 adapter->link_speed = 0;
5818 /* only continue if link was up previously */
5819 if (!netif_carrier_ok(netdev))
5822 /* poll for SFP+ cable when link is down */
5823 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5824 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
5826 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
5827 ixgbe_ptp_start_cyclecounter(adapter);
5829 e_info(drv, "NIC Link is Down\n");
5830 netif_carrier_off(netdev);
5832 /* ping all the active vfs to let them know link has changed */
5833 ixgbe_ping_all_vfs(adapter);
5837 * ixgbe_watchdog_flush_tx - flush queues on link down
5838 * @adapter: pointer to the device adapter structure
5840 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5843 int some_tx_pending = 0;
5845 if (!netif_carrier_ok(adapter->netdev)) {
5846 for (i = 0; i < adapter->num_tx_queues; i++) {
5847 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5848 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5849 some_tx_pending = 1;
5854 if (some_tx_pending) {
5855 /* We've lost link, so the controller stops DMA,
5856 * but we've got queued Tx work that's never going
5857 * to get done, so reset controller to flush Tx.
5858 * (Do the reset outside of interrupt context).
5860 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
5861 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
5866 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5870 /* Do not perform spoof check for 82598 or if not in IOV mode */
5871 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
5872 adapter->num_vfs == 0)
5875 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5878 * ssvpc register is cleared on read, if zero then no
5879 * spoofed packets in the last interval.
5884 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
5888 * ixgbe_watchdog_subtask - check and bring link up
5889 * @adapter: pointer to the device adapter structure
5891 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5893 /* if interface is down do nothing */
5894 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5895 test_bit(__IXGBE_RESETTING, &adapter->state))
5898 ixgbe_watchdog_update_link(adapter);
5900 if (adapter->link_up)
5901 ixgbe_watchdog_link_is_up(adapter);
5903 ixgbe_watchdog_link_is_down(adapter);
5905 ixgbe_spoof_check(adapter);
5906 ixgbe_update_stats(adapter);
5908 ixgbe_watchdog_flush_tx(adapter);
5912 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
5913 * @adapter: the ixgbe adapter structure
5915 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
5917 struct ixgbe_hw *hw = &adapter->hw;
5920 /* not searching for SFP so there is nothing to do here */
5921 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
5922 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5925 /* someone else is in init, wait until next service event */
5926 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5929 err = hw->phy.ops.identify_sfp(hw);
5930 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5933 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5934 /* If no cable is present, then we need to reset
5935 * the next time we find a good cable. */
5936 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
5943 /* exit if reset not needed */
5944 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5947 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
5950 * A module may be identified correctly, but the EEPROM may not have
5951 * support for that module. setup_sfp() will fail in that case, so
5952 * we should not allow that module to load.
5954 if (hw->mac.type == ixgbe_mac_82598EB)
5955 err = hw->phy.ops.reset(hw);
5957 err = hw->mac.ops.setup_sfp(hw);
5959 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5962 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
5963 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5966 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5968 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
5969 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
5970 e_dev_err("failed to initialize because an unsupported "
5971 "SFP+ module type was detected.\n");
5972 e_dev_err("Reload the driver after installing a "
5973 "supported module.\n");
5974 unregister_netdev(adapter->netdev);
5979 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
5980 * @adapter: the ixgbe adapter structure
5982 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
5984 struct ixgbe_hw *hw = &adapter->hw;
5986 bool autoneg = false;
5988 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
5991 /* someone else is in init, wait until next service event */
5992 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5995 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5997 speed = hw->phy.autoneg_advertised;
5998 if ((!speed) && (hw->mac.ops.get_link_capabilities)) {
5999 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
6001 /* setup the highest link when no autoneg */
6003 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
6004 speed = IXGBE_LINK_SPEED_10GB_FULL;
6008 if (hw->mac.ops.setup_link)
6009 hw->mac.ops.setup_link(hw, speed, true);
6011 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6012 adapter->link_check_timeout = jiffies;
6013 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6016 #ifdef CONFIG_PCI_IOV
6017 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6020 struct ixgbe_hw *hw = &adapter->hw;
6021 struct net_device *netdev = adapter->netdev;
6025 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6026 if (gpc) /* If incrementing then no need for the check below */
6029 * Check to see if a bad DMA write target from an errant or
6030 * malicious VF has caused a PCIe error. If so then we can
6031 * issue a VFLR to the offending VF(s) and then resume without
6032 * requesting a full slot reset.
6035 for (vf = 0; vf < adapter->num_vfs; vf++) {
6036 ciaa = (vf << 16) | 0x80000000;
6037 /* 32 bit read so align, we really want status at offset 6 */
6038 ciaa |= PCI_COMMAND;
6039 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6040 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
6042 /* disable debug mode asap after reading data */
6043 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6044 /* Get the upper 16 bits which will be the PCI status reg */
6046 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
6047 netdev_err(netdev, "VF %d Hung DMA\n", vf);
6049 ciaa = (vf << 16) | 0x80000000;
6051 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6052 ciad = 0x00008000; /* VFLR */
6053 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
6055 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6062 * ixgbe_service_timer - Timer Call-back
6063 * @data: pointer to adapter cast into an unsigned long
6065 static void ixgbe_service_timer(unsigned long data)
6067 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6068 unsigned long next_event_offset;
6071 /* poll faster when waiting for link */
6072 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6073 next_event_offset = HZ / 10;
6075 next_event_offset = HZ * 2;
6077 #ifdef CONFIG_PCI_IOV
6079 * don't bother with SR-IOV VF DMA hang check if there are
6080 * no VFs or the link is down
6082 if (!adapter->num_vfs ||
6083 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6084 goto normal_timer_service;
6086 /* If we have VFs allocated then we must check for DMA hangs */
6087 ixgbe_check_for_bad_vf(adapter);
6088 next_event_offset = HZ / 50;
6089 adapter->timer_event_accumulator++;
6091 if (adapter->timer_event_accumulator >= 100)
6092 adapter->timer_event_accumulator = 0;
6096 normal_timer_service:
6098 /* Reset the timer */
6099 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6102 ixgbe_service_event_schedule(adapter);
6105 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6107 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6110 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6112 /* If we're already down or resetting, just bail */
6113 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6114 test_bit(__IXGBE_RESETTING, &adapter->state))
6117 ixgbe_dump(adapter);
6118 netdev_err(adapter->netdev, "Reset adapter\n");
6119 adapter->tx_timeout_count++;
6121 ixgbe_reinit_locked(adapter);
6125 * ixgbe_service_task - manages and runs subtasks
6126 * @work: pointer to work_struct containing our data
6128 static void ixgbe_service_task(struct work_struct *work)
6130 struct ixgbe_adapter *adapter = container_of(work,
6131 struct ixgbe_adapter,
6133 ixgbe_reset_subtask(adapter);
6134 ixgbe_sfp_detection_subtask(adapter);
6135 ixgbe_sfp_link_config_subtask(adapter);
6136 ixgbe_check_overtemp_subtask(adapter);
6137 ixgbe_watchdog_subtask(adapter);
6138 ixgbe_fdir_reinit_subtask(adapter);
6139 ixgbe_check_hang_subtask(adapter);
6141 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
6142 ixgbe_ptp_overflow_check(adapter);
6143 ixgbe_ptp_rx_hang(adapter);
6146 ixgbe_service_event_complete(adapter);
6149 static int ixgbe_tso(struct ixgbe_ring *tx_ring,
6150 struct ixgbe_tx_buffer *first,
6153 struct sk_buff *skb = first->skb;
6154 u32 vlan_macip_lens, type_tucmd;
6155 u32 mss_l4len_idx, l4len;
6157 if (skb->ip_summed != CHECKSUM_PARTIAL)
6160 if (!skb_is_gso(skb))
6163 if (skb_header_cloned(skb)) {
6164 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6169 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6170 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6172 if (first->protocol == __constant_htons(ETH_P_IP)) {
6173 struct iphdr *iph = ip_hdr(skb);
6176 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6180 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6181 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6182 IXGBE_TX_FLAGS_CSUM |
6183 IXGBE_TX_FLAGS_IPV4;
6184 } else if (skb_is_gso_v6(skb)) {
6185 ipv6_hdr(skb)->payload_len = 0;
6186 tcp_hdr(skb)->check =
6187 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6188 &ipv6_hdr(skb)->daddr,
6190 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6191 IXGBE_TX_FLAGS_CSUM;
6194 /* compute header lengths */
6195 l4len = tcp_hdrlen(skb);
6196 *hdr_len = skb_transport_offset(skb) + l4len;
6198 /* update gso size and bytecount with header size */
6199 first->gso_segs = skb_shinfo(skb)->gso_segs;
6200 first->bytecount += (first->gso_segs - 1) * *hdr_len;
6202 /* mss_l4len_id: use 0 as index for TSO */
6203 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6204 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6206 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6207 vlan_macip_lens = skb_network_header_len(skb);
6208 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6209 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6211 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6217 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6218 struct ixgbe_tx_buffer *first)
6220 struct sk_buff *skb = first->skb;
6221 u32 vlan_macip_lens = 0;
6222 u32 mss_l4len_idx = 0;
6225 if (skb->ip_summed != CHECKSUM_PARTIAL) {
6226 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6227 !(first->tx_flags & IXGBE_TX_FLAGS_CC))
6231 switch (first->protocol) {
6232 case __constant_htons(ETH_P_IP):
6233 vlan_macip_lens |= skb_network_header_len(skb);
6234 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6235 l4_hdr = ip_hdr(skb)->protocol;
6237 case __constant_htons(ETH_P_IPV6):
6238 vlan_macip_lens |= skb_network_header_len(skb);
6239 l4_hdr = ipv6_hdr(skb)->nexthdr;
6242 if (unlikely(net_ratelimit())) {
6243 dev_warn(tx_ring->dev,
6244 "partial checksum but proto=%x!\n",
6252 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6253 mss_l4len_idx = tcp_hdrlen(skb) <<
6254 IXGBE_ADVTXD_L4LEN_SHIFT;
6257 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6258 mss_l4len_idx = sizeof(struct sctphdr) <<
6259 IXGBE_ADVTXD_L4LEN_SHIFT;
6262 mss_l4len_idx = sizeof(struct udphdr) <<
6263 IXGBE_ADVTXD_L4LEN_SHIFT;
6266 if (unlikely(net_ratelimit())) {
6267 dev_warn(tx_ring->dev,
6268 "partial checksum but l4 proto=%x!\n",
6274 /* update TX checksum flag */
6275 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
6278 /* vlan_macip_lens: MACLEN, VLAN tag */
6279 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6280 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6282 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6283 type_tucmd, mss_l4len_idx);
6286 #define IXGBE_SET_FLAG(_input, _flag, _result) \
6287 ((_flag <= _result) ? \
6288 ((u32)(_input & _flag) * (_result / _flag)) : \
6289 ((u32)(_input & _flag) / (_flag / _result)))
6291 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
6293 /* set type for advanced descriptor with frame checksum insertion */
6294 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
6295 IXGBE_ADVTXD_DCMD_DEXT |
6296 IXGBE_ADVTXD_DCMD_IFCS;
6298 /* set HW vlan bit if vlan is present */
6299 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
6300 IXGBE_ADVTXD_DCMD_VLE);
6302 /* set segmentation enable bits for TSO/FSO */
6303 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
6304 IXGBE_ADVTXD_DCMD_TSE);
6306 /* set timestamp bit if present */
6307 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
6308 IXGBE_ADVTXD_MAC_TSTAMP);
6310 /* insert frame checksum */
6311 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
6316 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
6317 u32 tx_flags, unsigned int paylen)
6319 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
6321 /* enable L4 checksum for TSO and TX checksum offload */
6322 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6323 IXGBE_TX_FLAGS_CSUM,
6324 IXGBE_ADVTXD_POPTS_TXSM);
6326 /* enble IPv4 checksum for TSO */
6327 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6328 IXGBE_TX_FLAGS_IPV4,
6329 IXGBE_ADVTXD_POPTS_IXSM);
6332 * Check Context must be set if Tx switch is enabled, which it
6333 * always is for case where virtual functions are running
6335 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6339 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6342 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6345 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6346 struct ixgbe_tx_buffer *first,
6349 struct sk_buff *skb = first->skb;
6350 struct ixgbe_tx_buffer *tx_buffer;
6351 union ixgbe_adv_tx_desc *tx_desc;
6352 struct skb_frag_struct *frag;
6354 unsigned int data_len, size;
6355 u32 tx_flags = first->tx_flags;
6356 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
6357 u16 i = tx_ring->next_to_use;
6359 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6361 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
6363 size = skb_headlen(skb);
6364 data_len = skb->data_len;
6367 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6368 if (data_len < sizeof(struct fcoe_crc_eof)) {
6369 size -= sizeof(struct fcoe_crc_eof) - data_len;
6372 data_len -= sizeof(struct fcoe_crc_eof);
6377 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
6381 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
6382 if (dma_mapping_error(tx_ring->dev, dma))
6385 /* record length, and DMA address */
6386 dma_unmap_len_set(tx_buffer, len, size);
6387 dma_unmap_addr_set(tx_buffer, dma, dma);
6389 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6391 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
6392 tx_desc->read.cmd_type_len =
6393 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
6397 if (i == tx_ring->count) {
6398 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6401 tx_desc->read.olinfo_status = 0;
6403 dma += IXGBE_MAX_DATA_PER_TXD;
6404 size -= IXGBE_MAX_DATA_PER_TXD;
6406 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6409 if (likely(!data_len))
6412 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
6416 if (i == tx_ring->count) {
6417 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6420 tx_desc->read.olinfo_status = 0;
6423 size = min_t(unsigned int, data_len, skb_frag_size(frag));
6425 size = skb_frag_size(frag);
6429 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6432 tx_buffer = &tx_ring->tx_buffer_info[i];
6435 /* write last descriptor with RS and EOP bits */
6436 cmd_type |= size | IXGBE_TXD_CMD;
6437 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
6439 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
6441 /* set the timestamp */
6442 first->time_stamp = jiffies;
6445 * Force memory writes to complete before letting h/w know there
6446 * are new descriptors to fetch. (Only applicable for weak-ordered
6447 * memory model archs, such as IA-64).
6449 * We also need this memory barrier to make certain all of the
6450 * status bits have been updated before next_to_watch is written.
6454 /* set next_to_watch value indicating a packet is present */
6455 first->next_to_watch = tx_desc;
6458 if (i == tx_ring->count)
6461 tx_ring->next_to_use = i;
6463 /* notify HW of packet */
6464 writel(i, tx_ring->tail);
6468 dev_err(tx_ring->dev, "TX DMA map failed\n");
6470 /* clear dma mappings for failed tx_buffer_info map */
6472 tx_buffer = &tx_ring->tx_buffer_info[i];
6473 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6474 if (tx_buffer == first)
6481 tx_ring->next_to_use = i;
6484 static void ixgbe_atr(struct ixgbe_ring *ring,
6485 struct ixgbe_tx_buffer *first)
6487 struct ixgbe_q_vector *q_vector = ring->q_vector;
6488 union ixgbe_atr_hash_dword input = { .dword = 0 };
6489 union ixgbe_atr_hash_dword common = { .dword = 0 };
6491 unsigned char *network;
6493 struct ipv6hdr *ipv6;
6498 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6502 /* do nothing if sampling is disabled */
6503 if (!ring->atr_sample_rate)
6508 /* snag network header to get L4 type and address */
6509 hdr.network = skb_network_header(first->skb);
6511 /* Currently only IPv4/IPv6 with TCP is supported */
6512 if ((first->protocol != __constant_htons(ETH_P_IPV6) ||
6513 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6514 (first->protocol != __constant_htons(ETH_P_IP) ||
6515 hdr.ipv4->protocol != IPPROTO_TCP))
6518 th = tcp_hdr(first->skb);
6520 /* skip this packet since it is invalid or the socket is closing */
6524 /* sample on all syn packets or once every atr sample count */
6525 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6528 /* reset sample count */
6529 ring->atr_count = 0;
6531 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6534 * src and dst are inverted, think how the receiver sees them
6536 * The input is broken into two sections, a non-compressed section
6537 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6538 * is XORed together and stored in the compressed dword.
6540 input.formatted.vlan_id = vlan_id;
6543 * since src port and flex bytes occupy the same word XOR them together
6544 * and write the value to source port portion of compressed dword
6546 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
6547 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6549 common.port.src ^= th->dest ^ first->protocol;
6550 common.port.dst ^= th->source;
6552 if (first->protocol == __constant_htons(ETH_P_IP)) {
6553 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6554 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6556 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6557 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6558 hdr.ipv6->saddr.s6_addr32[1] ^
6559 hdr.ipv6->saddr.s6_addr32[2] ^
6560 hdr.ipv6->saddr.s6_addr32[3] ^
6561 hdr.ipv6->daddr.s6_addr32[0] ^
6562 hdr.ipv6->daddr.s6_addr32[1] ^
6563 hdr.ipv6->daddr.s6_addr32[2] ^
6564 hdr.ipv6->daddr.s6_addr32[3];
6567 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6568 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6569 input, common, ring->queue_index);
6572 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6574 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6575 /* Herbert's original patch had:
6576 * smp_mb__after_netif_stop_queue();
6577 * but since that doesn't exist yet, just open code it. */
6580 /* We need to check again in a case another CPU has just
6581 * made room available. */
6582 if (likely(ixgbe_desc_unused(tx_ring) < size))
6585 /* A reprieve! - use start_queue because it doesn't call schedule */
6586 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6587 ++tx_ring->tx_stats.restart_queue;
6591 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6593 if (likely(ixgbe_desc_unused(tx_ring) >= size))
6595 return __ixgbe_maybe_stop_tx(tx_ring, size);
6599 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6601 struct ixgbe_adapter *adapter;
6602 struct ixgbe_ring_feature *f;
6606 * only execute the code below if protocol is FCoE
6607 * or FIP and we have FCoE enabled on the adapter
6609 switch (vlan_get_protocol(skb)) {
6610 case __constant_htons(ETH_P_FCOE):
6611 case __constant_htons(ETH_P_FIP):
6612 adapter = netdev_priv(dev);
6614 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6617 return __netdev_pick_tx(dev, skb);
6620 f = &adapter->ring_feature[RING_F_FCOE];
6622 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6625 while (txq >= f->indices)
6628 return txq + f->offset;
6632 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6633 struct ixgbe_adapter *adapter,
6634 struct ixgbe_ring *tx_ring)
6636 struct ixgbe_tx_buffer *first;
6640 u16 count = TXD_USE_COUNT(skb_headlen(skb));
6641 __be16 protocol = skb->protocol;
6645 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6646 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
6647 * + 2 desc gap to keep tail from touching head,
6648 * + 1 desc for context descriptor,
6649 * otherwise try next time
6651 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6652 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6654 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6655 tx_ring->tx_stats.tx_busy++;
6656 return NETDEV_TX_BUSY;
6659 /* record the location of the first descriptor for this packet */
6660 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6662 first->bytecount = skb->len;
6663 first->gso_segs = 1;
6665 /* if we have a HW VLAN tag being added default to the HW one */
6666 if (vlan_tx_tag_present(skb)) {
6667 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6668 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6669 /* else if it is a SW VLAN check the next protocol and store the tag */
6670 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6671 struct vlan_hdr *vhdr, _vhdr;
6672 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6676 protocol = vhdr->h_vlan_encapsulated_proto;
6677 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
6678 IXGBE_TX_FLAGS_VLAN_SHIFT;
6679 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6682 skb_tx_timestamp(skb);
6684 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
6685 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
6686 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
6688 /* schedule check for Tx timestamp */
6689 adapter->ptp_tx_skb = skb_get(skb);
6690 adapter->ptp_tx_start = jiffies;
6691 schedule_work(&adapter->ptp_tx_work);
6694 #ifdef CONFIG_PCI_IOV
6696 * Use the l2switch_enable flag - would be false if the DMA
6697 * Tx switch had been disabled.
6699 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6700 tx_flags |= IXGBE_TX_FLAGS_CC;
6703 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
6704 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
6705 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6706 (skb->priority != TC_PRIO_CONTROL))) {
6707 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6708 tx_flags |= (skb->priority & 0x7) <<
6709 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
6710 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6711 struct vlan_ethhdr *vhdr;
6712 if (skb_header_cloned(skb) &&
6713 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6715 vhdr = (struct vlan_ethhdr *)skb->data;
6716 vhdr->h_vlan_TCI = htons(tx_flags >>
6717 IXGBE_TX_FLAGS_VLAN_SHIFT);
6719 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6723 /* record initial flags and protocol */
6724 first->tx_flags = tx_flags;
6725 first->protocol = protocol;
6728 /* setup tx offload for FCoE */
6729 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6730 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
6731 tso = ixgbe_fso(tx_ring, first, &hdr_len);
6738 #endif /* IXGBE_FCOE */
6739 tso = ixgbe_tso(tx_ring, first, &hdr_len);
6743 ixgbe_tx_csum(tx_ring, first);
6745 /* add the ATR filter if ATR is on */
6746 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6747 ixgbe_atr(tx_ring, first);
6751 #endif /* IXGBE_FCOE */
6752 ixgbe_tx_map(tx_ring, first, hdr_len);
6754 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6756 return NETDEV_TX_OK;
6759 dev_kfree_skb_any(first->skb);
6762 return NETDEV_TX_OK;
6765 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6766 struct net_device *netdev)
6768 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6769 struct ixgbe_ring *tx_ring;
6772 * The minimum packet size for olinfo paylen is 17 so pad the skb
6773 * in order to meet this minimum size requirement.
6775 if (unlikely(skb->len < 17)) {
6776 if (skb_pad(skb, 17 - skb->len))
6777 return NETDEV_TX_OK;
6779 skb_set_tail_pointer(skb, 17);
6782 tx_ring = adapter->tx_ring[skb->queue_mapping];
6783 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6787 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6788 * @netdev: network interface device structure
6789 * @p: pointer to an address structure
6791 * Returns 0 on success, negative on failure
6793 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6795 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6796 struct ixgbe_hw *hw = &adapter->hw;
6797 struct sockaddr *addr = p;
6799 if (!is_valid_ether_addr(addr->sa_data))
6800 return -EADDRNOTAVAIL;
6802 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6803 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6805 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
6811 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6813 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6814 struct ixgbe_hw *hw = &adapter->hw;
6818 if (prtad != hw->phy.mdio.prtad)
6820 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6826 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6827 u16 addr, u16 value)
6829 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6830 struct ixgbe_hw *hw = &adapter->hw;
6832 if (prtad != hw->phy.mdio.prtad)
6834 return hw->phy.ops.write_reg(hw, addr, devad, value);
6837 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6839 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6843 return ixgbe_ptp_hwtstamp_ioctl(adapter, req, cmd);
6845 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6850 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6852 * @netdev: network interface device structure
6854 * Returns non-zero on failure
6856 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6859 struct ixgbe_adapter *adapter = netdev_priv(dev);
6860 struct ixgbe_hw *hw = &adapter->hw;
6862 if (is_valid_ether_addr(hw->mac.san_addr)) {
6864 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
6867 /* update SAN MAC vmdq pool selection */
6868 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
6874 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6876 * @netdev: network interface device structure
6878 * Returns non-zero on failure
6880 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6883 struct ixgbe_adapter *adapter = netdev_priv(dev);
6884 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6886 if (is_valid_ether_addr(mac->san_addr)) {
6888 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6894 #ifdef CONFIG_NET_POLL_CONTROLLER
6896 * Polling 'interrupt' - used by things like netconsole to send skbs
6897 * without having to re-enable interrupts. It's not called while
6898 * the interrupt routine is executing.
6900 static void ixgbe_netpoll(struct net_device *netdev)
6902 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6905 /* if interface is down do nothing */
6906 if (test_bit(__IXGBE_DOWN, &adapter->state))
6909 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6910 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6911 for (i = 0; i < adapter->num_q_vectors; i++)
6912 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
6914 ixgbe_intr(adapter->pdev->irq, netdev);
6916 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6920 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6921 struct rtnl_link_stats64 *stats)
6923 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6927 for (i = 0; i < adapter->num_rx_queues; i++) {
6928 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6934 start = u64_stats_fetch_begin_bh(&ring->syncp);
6935 packets = ring->stats.packets;
6936 bytes = ring->stats.bytes;
6937 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6938 stats->rx_packets += packets;
6939 stats->rx_bytes += bytes;
6943 for (i = 0; i < adapter->num_tx_queues; i++) {
6944 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6950 start = u64_stats_fetch_begin_bh(&ring->syncp);
6951 packets = ring->stats.packets;
6952 bytes = ring->stats.bytes;
6953 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6954 stats->tx_packets += packets;
6955 stats->tx_bytes += bytes;
6959 /* following stats updated by ixgbe_watchdog_task() */
6960 stats->multicast = netdev->stats.multicast;
6961 stats->rx_errors = netdev->stats.rx_errors;
6962 stats->rx_length_errors = netdev->stats.rx_length_errors;
6963 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6964 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6968 #ifdef CONFIG_IXGBE_DCB
6970 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6971 * @adapter: pointer to ixgbe_adapter
6972 * @tc: number of traffic classes currently enabled
6974 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6975 * 802.1Q priority maps to a packet buffer that exists.
6977 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6979 struct ixgbe_hw *hw = &adapter->hw;
6983 /* 82598 have a static priority to TC mapping that can not
6984 * be changed so no validation is needed.
6986 if (hw->mac.type == ixgbe_mac_82598EB)
6989 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6992 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6993 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6995 /* If up2tc is out of bounds default to zero */
6997 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7001 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7007 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
7008 * @adapter: Pointer to adapter struct
7010 * Populate the netdev user priority to tc map
7012 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
7014 struct net_device *dev = adapter->netdev;
7015 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
7016 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
7019 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
7022 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
7023 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
7025 tc = ets->prio_tc[prio];
7027 netdev_set_prio_tc_map(dev, prio, tc);
7031 #endif /* CONFIG_IXGBE_DCB */
7033 * ixgbe_setup_tc - configure net_device for multiple traffic classes
7035 * @netdev: net device to configure
7036 * @tc: number of traffic classes to enable
7038 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7040 struct ixgbe_adapter *adapter = netdev_priv(dev);
7041 struct ixgbe_hw *hw = &adapter->hw;
7043 /* Hardware supports up to 8 traffic classes */
7044 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
7045 (hw->mac.type == ixgbe_mac_82598EB &&
7046 tc < MAX_TRAFFIC_CLASS))
7049 /* Hardware has to reinitialize queues and interrupts to
7050 * match packet buffer alignment. Unfortunately, the
7051 * hardware is not flexible enough to do this dynamically.
7053 if (netif_running(dev))
7055 ixgbe_clear_interrupt_scheme(adapter);
7057 #ifdef CONFIG_IXGBE_DCB
7059 netdev_set_num_tc(dev, tc);
7060 ixgbe_set_prio_tc_map(adapter);
7062 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
7064 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
7065 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
7066 adapter->hw.fc.requested_mode = ixgbe_fc_none;
7069 netdev_reset_tc(dev);
7071 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7072 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
7074 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
7076 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7077 adapter->dcb_cfg.pfc_mode_enable = false;
7080 ixgbe_validate_rtr(adapter, tc);
7082 #endif /* CONFIG_IXGBE_DCB */
7083 ixgbe_init_interrupt_scheme(adapter);
7085 if (netif_running(dev))
7086 return ixgbe_open(dev);
7091 #ifdef CONFIG_PCI_IOV
7092 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
7094 struct net_device *netdev = adapter->netdev;
7097 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
7102 void ixgbe_do_reset(struct net_device *netdev)
7104 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7106 if (netif_running(netdev))
7107 ixgbe_reinit_locked(adapter);
7109 ixgbe_reset(adapter);
7112 static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
7113 netdev_features_t features)
7115 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7117 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7118 if (!(features & NETIF_F_RXCSUM))
7119 features &= ~NETIF_F_LRO;
7121 /* Turn off LRO if not RSC capable */
7122 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
7123 features &= ~NETIF_F_LRO;
7128 static int ixgbe_set_features(struct net_device *netdev,
7129 netdev_features_t features)
7131 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7132 netdev_features_t changed = netdev->features ^ features;
7133 bool need_reset = false;
7135 /* Make sure RSC matches LRO, reset if change */
7136 if (!(features & NETIF_F_LRO)) {
7137 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7139 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
7140 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
7141 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7142 if (adapter->rx_itr_setting == 1 ||
7143 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
7144 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
7146 } else if ((changed ^ features) & NETIF_F_LRO) {
7147 e_info(probe, "rx-usecs set too low, "
7153 * Check if Flow Director n-tuple support was enabled or disabled. If
7154 * the state changed, we need to reset.
7156 switch (features & NETIF_F_NTUPLE) {
7157 case NETIF_F_NTUPLE:
7158 /* turn off ATR, enable perfect filters and reset */
7159 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
7162 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7163 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7166 /* turn off perfect filters, enable ATR and reset */
7167 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7170 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7172 /* We cannot enable ATR if SR-IOV is enabled */
7173 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7176 /* We cannot enable ATR if we have 2 or more traffic classes */
7177 if (netdev_get_num_tc(netdev) > 1)
7180 /* We cannot enable ATR if RSS is disabled */
7181 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
7184 /* A sample rate of 0 indicates ATR disabled */
7185 if (!adapter->atr_sample_rate)
7188 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7192 if (features & NETIF_F_HW_VLAN_CTAG_RX)
7193 ixgbe_vlan_strip_enable(adapter);
7195 ixgbe_vlan_strip_disable(adapter);
7197 if (changed & NETIF_F_RXALL)
7200 netdev->features = features;
7202 ixgbe_do_reset(netdev);
7207 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
7208 struct net_device *dev,
7209 const unsigned char *addr,
7212 struct ixgbe_adapter *adapter = netdev_priv(dev);
7215 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7216 return ndo_dflt_fdb_add(ndm, tb, dev, addr, flags);
7218 /* Hardware does not support aging addresses so if a
7219 * ndm_state is given only allow permanent addresses
7221 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
7222 pr_info("%s: FDB only supports static addresses\n",
7227 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
7228 u32 rar_uc_entries = IXGBE_MAX_PF_MACVLANS;
7230 if (netdev_uc_count(dev) < rar_uc_entries)
7231 err = dev_uc_add_excl(dev, addr);
7234 } else if (is_multicast_ether_addr(addr)) {
7235 err = dev_mc_add_excl(dev, addr);
7240 /* Only return duplicate errors if NLM_F_EXCL is set */
7241 if (err == -EEXIST && !(flags & NLM_F_EXCL))
7247 static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
7248 struct nlmsghdr *nlh)
7250 struct ixgbe_adapter *adapter = netdev_priv(dev);
7251 struct nlattr *attr, *br_spec;
7254 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7257 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
7259 nla_for_each_nested(attr, br_spec, rem) {
7263 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7266 mode = nla_get_u16(attr);
7267 if (mode == BRIDGE_MODE_VEPA) {
7269 adapter->flags2 &= ~IXGBE_FLAG2_BRIDGE_MODE_VEB;
7270 } else if (mode == BRIDGE_MODE_VEB) {
7271 reg = IXGBE_PFDTXGSWC_VT_LBEN;
7272 adapter->flags2 |= IXGBE_FLAG2_BRIDGE_MODE_VEB;
7276 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, reg);
7278 e_info(drv, "enabling bridge mode: %s\n",
7279 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
7285 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
7286 struct net_device *dev,
7289 struct ixgbe_adapter *adapter = netdev_priv(dev);
7292 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7295 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
7296 mode = BRIDGE_MODE_VEB;
7298 mode = BRIDGE_MODE_VEPA;
7300 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode);
7303 static const struct net_device_ops ixgbe_netdev_ops = {
7304 .ndo_open = ixgbe_open,
7305 .ndo_stop = ixgbe_close,
7306 .ndo_start_xmit = ixgbe_xmit_frame,
7308 .ndo_select_queue = ixgbe_select_queue,
7310 .ndo_set_rx_mode = ixgbe_set_rx_mode,
7311 .ndo_validate_addr = eth_validate_addr,
7312 .ndo_set_mac_address = ixgbe_set_mac,
7313 .ndo_change_mtu = ixgbe_change_mtu,
7314 .ndo_tx_timeout = ixgbe_tx_timeout,
7315 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7316 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
7317 .ndo_do_ioctl = ixgbe_ioctl,
7318 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7319 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7320 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7321 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7322 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
7323 .ndo_get_stats64 = ixgbe_get_stats64,
7324 #ifdef CONFIG_IXGBE_DCB
7325 .ndo_setup_tc = ixgbe_setup_tc,
7327 #ifdef CONFIG_NET_POLL_CONTROLLER
7328 .ndo_poll_controller = ixgbe_netpoll,
7330 #ifdef CONFIG_NET_RX_BUSY_POLL
7331 .ndo_busy_poll = ixgbe_low_latency_recv,
7334 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7335 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7336 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7337 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7338 .ndo_fcoe_disable = ixgbe_fcoe_disable,
7339 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7340 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
7341 #endif /* IXGBE_FCOE */
7342 .ndo_set_features = ixgbe_set_features,
7343 .ndo_fix_features = ixgbe_fix_features,
7344 .ndo_fdb_add = ixgbe_ndo_fdb_add,
7345 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
7346 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
7350 * ixgbe_enumerate_functions - Get the number of ports this device has
7351 * @adapter: adapter structure
7353 * This function enumerates the phsyical functions co-located on a single slot,
7354 * in order to determine how many ports a device has. This is most useful in
7355 * determining the required GT/s of PCIe bandwidth necessary for optimal
7358 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
7360 struct list_head *entry;
7363 /* Some cards can not use the generic count PCIe functions method,
7364 * because they are behind a parent switch, so we hardcode these with
7365 * the correct number of functions.
7367 if (ixgbe_pcie_from_parent(&adapter->hw)) {
7370 list_for_each(entry, &adapter->pdev->bus_list) {
7371 struct pci_dev *pdev =
7372 list_entry(entry, struct pci_dev, bus_list);
7373 /* don't count virtual functions */
7374 if (!pdev->is_virtfn)
7383 * ixgbe_wol_supported - Check whether device supports WoL
7384 * @hw: hw specific details
7385 * @device_id: the device ID
7386 * @subdev_id: the subsystem device ID
7388 * This function is used by probe and ethtool to determine
7389 * which devices have WoL support
7392 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
7395 struct ixgbe_hw *hw = &adapter->hw;
7396 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7397 int is_wol_supported = 0;
7399 switch (device_id) {
7400 case IXGBE_DEV_ID_82599_SFP:
7401 /* Only these subdevices could supports WOL */
7402 switch (subdevice_id) {
7403 case IXGBE_SUBDEV_ID_82599_560FLR:
7404 /* only support first port */
7405 if (hw->bus.func != 0)
7407 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
7408 case IXGBE_SUBDEV_ID_82599_SFP:
7409 case IXGBE_SUBDEV_ID_82599_RNDC:
7410 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
7411 case IXGBE_SUBDEV_ID_82599_LOM_SFP:
7412 is_wol_supported = 1;
7416 case IXGBE_DEV_ID_82599EN_SFP:
7417 /* Only this subdevice supports WOL */
7418 switch (subdevice_id) {
7419 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
7420 is_wol_supported = 1;
7424 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7425 /* All except this subdevice support WOL */
7426 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7427 is_wol_supported = 1;
7429 case IXGBE_DEV_ID_82599_KX4:
7430 is_wol_supported = 1;
7432 case IXGBE_DEV_ID_X540T:
7433 case IXGBE_DEV_ID_X540T1:
7434 /* check eeprom to see if enabled wol */
7435 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7436 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7437 (hw->bus.func == 0))) {
7438 is_wol_supported = 1;
7443 return is_wol_supported;
7447 * ixgbe_probe - Device Initialization Routine
7448 * @pdev: PCI device information struct
7449 * @ent: entry in ixgbe_pci_tbl
7451 * Returns 0 on success, negative on failure
7453 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7454 * The OS initialization, configuring of the adapter private structure,
7455 * and a hardware reset occur.
7457 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
7459 struct net_device *netdev;
7460 struct ixgbe_adapter *adapter = NULL;
7461 struct ixgbe_hw *hw;
7462 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7463 static int cards_found;
7464 int i, err, pci_using_dac, expected_gts;
7465 unsigned int indices = MAX_TX_QUEUES;
7466 u8 part_str[IXGBE_PBANUM_LENGTH];
7472 /* Catch broken hardware that put the wrong VF device ID in
7473 * the PCIe SR-IOV capability.
7475 if (pdev->is_virtfn) {
7476 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7477 pci_name(pdev), pdev->vendor, pdev->device);
7481 err = pci_enable_device_mem(pdev);
7485 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7486 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7489 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7491 err = dma_set_coherent_mask(&pdev->dev,
7495 "No usable DMA configuration, aborting\n");
7502 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7503 IORESOURCE_MEM), ixgbe_driver_name);
7506 "pci_request_selected_regions failed 0x%x\n", err);
7510 pci_enable_pcie_error_reporting(pdev);
7512 pci_set_master(pdev);
7513 pci_save_state(pdev);
7515 if (ii->mac == ixgbe_mac_82598EB) {
7516 #ifdef CONFIG_IXGBE_DCB
7517 /* 8 TC w/ 4 queues per TC */
7518 indices = 4 * MAX_TRAFFIC_CLASS;
7520 indices = IXGBE_MAX_RSS_INDICES;
7524 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7527 goto err_alloc_etherdev;
7530 SET_NETDEV_DEV(netdev, &pdev->dev);
7532 adapter = netdev_priv(netdev);
7533 pci_set_drvdata(pdev, adapter);
7535 adapter->netdev = netdev;
7536 adapter->pdev = pdev;
7539 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
7541 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7542 pci_resource_len(pdev, 0));
7548 netdev->netdev_ops = &ixgbe_netdev_ops;
7549 ixgbe_set_ethtool_ops(netdev);
7550 netdev->watchdog_timeo = 5 * HZ;
7551 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7553 adapter->bd_number = cards_found;
7556 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7557 hw->mac.type = ii->mac;
7560 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7561 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7562 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7563 if (!(eec & (1 << 8)))
7564 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7567 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7568 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7569 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7570 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7571 hw->phy.mdio.mmds = 0;
7572 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7573 hw->phy.mdio.dev = netdev;
7574 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7575 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7577 ii->get_invariants(hw);
7579 /* setup the private structure */
7580 err = ixgbe_sw_init(adapter);
7584 /* Cache if MNG FW is up so we don't have to read the REG later */
7585 if (hw->mac.ops.mng_fw_enabled)
7586 hw->mng_fw_enabled = hw->mac.ops.mng_fw_enabled(hw);
7588 /* Make it possible the adapter to be woken up via WOL */
7589 switch (adapter->hw.mac.type) {
7590 case ixgbe_mac_82599EB:
7591 case ixgbe_mac_X540:
7592 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7599 * If there is a fan on this device and it has failed log the
7602 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7603 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7604 if (esdp & IXGBE_ESDP_SDP1)
7605 e_crit(probe, "Fan has stopped, replace the adapter\n");
7608 if (allow_unsupported_sfp)
7609 hw->allow_unsupported_sfp = allow_unsupported_sfp;
7611 /* reset_hw fills in the perm_addr as well */
7612 hw->phy.reset_if_overtemp = true;
7613 err = hw->mac.ops.reset_hw(hw);
7614 hw->phy.reset_if_overtemp = false;
7615 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7616 hw->mac.type == ixgbe_mac_82598EB) {
7618 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7619 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
7620 e_dev_err("Reload the driver after installing a supported module.\n");
7623 e_dev_err("HW Init failed: %d\n", err);
7627 #ifdef CONFIG_PCI_IOV
7628 /* SR-IOV not supported on the 82598 */
7629 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7632 ixgbe_init_mbx_params_pf(hw);
7633 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops));
7634 ixgbe_enable_sriov(adapter);
7635 pci_sriov_set_totalvfs(pdev, 63);
7639 netdev->features = NETIF_F_SG |
7642 NETIF_F_HW_VLAN_CTAG_TX |
7643 NETIF_F_HW_VLAN_CTAG_RX |
7644 NETIF_F_HW_VLAN_CTAG_FILTER |
7650 netdev->hw_features = netdev->features;
7652 switch (adapter->hw.mac.type) {
7653 case ixgbe_mac_82599EB:
7654 case ixgbe_mac_X540:
7655 netdev->features |= NETIF_F_SCTP_CSUM;
7656 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7663 netdev->hw_features |= NETIF_F_RXALL;
7665 netdev->vlan_features |= NETIF_F_TSO;
7666 netdev->vlan_features |= NETIF_F_TSO6;
7667 netdev->vlan_features |= NETIF_F_IP_CSUM;
7668 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7669 netdev->vlan_features |= NETIF_F_SG;
7671 netdev->priv_flags |= IFF_UNICAST_FLT;
7672 netdev->priv_flags |= IFF_SUPP_NOFCS;
7674 #ifdef CONFIG_IXGBE_DCB
7675 netdev->dcbnl_ops = &dcbnl_ops;
7679 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7680 unsigned int fcoe_l;
7682 if (hw->mac.ops.get_device_caps) {
7683 hw->mac.ops.get_device_caps(hw, &device_caps);
7684 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7685 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7689 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
7690 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
7692 netdev->features |= NETIF_F_FSO |
7695 netdev->vlan_features |= NETIF_F_FSO |
7699 #endif /* IXGBE_FCOE */
7700 if (pci_using_dac) {
7701 netdev->features |= NETIF_F_HIGHDMA;
7702 netdev->vlan_features |= NETIF_F_HIGHDMA;
7705 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7706 netdev->hw_features |= NETIF_F_LRO;
7707 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7708 netdev->features |= NETIF_F_LRO;
7710 /* make sure the EEPROM is good */
7711 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7712 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7717 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7719 if (!is_valid_ether_addr(netdev->dev_addr)) {
7720 e_dev_err("invalid MAC address\n");
7725 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7726 (unsigned long) adapter);
7728 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7729 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7731 err = ixgbe_init_interrupt_scheme(adapter);
7735 /* WOL not supported for all devices */
7737 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7738 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
7739 pdev->subsystem_device);
7740 if (hw->wol_enabled)
7741 adapter->wol = IXGBE_WUFC_MAG;
7743 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7745 /* save off EEPROM version number */
7746 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7747 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7749 /* pick up the PCI bus settings for reporting later */
7750 hw->mac.ops.get_bus_info(hw);
7751 if (ixgbe_pcie_from_parent(hw))
7752 ixgbe_get_parent_bus_info(adapter);
7754 /* calculate the expected PCIe bandwidth required for optimal
7755 * performance. Note that some older parts will never have enough
7756 * bandwidth due to being older generation PCIe parts. We clamp these
7757 * parts to ensure no warning is displayed if it can't be fixed.
7759 switch (hw->mac.type) {
7760 case ixgbe_mac_82598EB:
7761 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
7764 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
7767 ixgbe_check_minimum_link(adapter, expected_gts);
7769 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7771 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7772 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7773 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7774 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7777 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7778 hw->mac.type, hw->phy.type, part_str);
7780 e_dev_info("%pM\n", netdev->dev_addr);
7782 /* reset the hardware with the new settings */
7783 err = hw->mac.ops.start_hw(hw);
7784 if (err == IXGBE_ERR_EEPROM_VERSION) {
7785 /* We are running on a pre-production device, log a warning */
7786 e_dev_warn("This device is a pre-production adapter/LOM. "
7787 "Please be aware there may be issues associated "
7788 "with your hardware. If you are experiencing "
7789 "problems please contact your Intel or hardware "
7790 "representative who provided you with this "
7793 strcpy(netdev->name, "eth%d");
7794 err = register_netdev(netdev);
7798 /* power down the optics for 82599 SFP+ fiber */
7799 if (hw->mac.ops.disable_tx_laser)
7800 hw->mac.ops.disable_tx_laser(hw);
7802 /* carrier off reporting is important to ethtool even BEFORE open */
7803 netif_carrier_off(netdev);
7805 #ifdef CONFIG_IXGBE_DCA
7806 if (dca_add_requester(&pdev->dev) == 0) {
7807 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7808 ixgbe_setup_dca(adapter);
7811 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7812 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7813 for (i = 0; i < adapter->num_vfs; i++)
7814 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7817 /* firmware requires driver version to be 0xFFFFFFFF
7818 * since os does not support feature
7820 if (hw->mac.ops.set_fw_drv_ver)
7821 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7824 /* add san mac addr to netdev */
7825 ixgbe_add_sanmac_netdev(netdev);
7827 e_dev_info("%s\n", ixgbe_default_device_descr);
7830 #ifdef CONFIG_IXGBE_HWMON
7831 if (ixgbe_sysfs_init(adapter))
7832 e_err(probe, "failed to allocate sysfs resources\n");
7833 #endif /* CONFIG_IXGBE_HWMON */
7835 ixgbe_dbg_adapter_init(adapter);
7837 /* Need link setup for MNG FW, else wait for IXGBE_UP */
7838 if (hw->mng_fw_enabled && hw->mac.ops.setup_link)
7839 hw->mac.ops.setup_link(hw,
7840 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
7846 ixgbe_release_hw_control(adapter);
7847 ixgbe_clear_interrupt_scheme(adapter);
7849 ixgbe_disable_sriov(adapter);
7850 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7851 iounmap(hw->hw_addr);
7853 free_netdev(netdev);
7855 pci_release_selected_regions(pdev,
7856 pci_select_bars(pdev, IORESOURCE_MEM));
7859 pci_disable_device(pdev);
7864 * ixgbe_remove - Device Removal Routine
7865 * @pdev: PCI device information struct
7867 * ixgbe_remove is called by the PCI subsystem to alert the driver
7868 * that it should release a PCI device. The could be caused by a
7869 * Hot-Plug event, or because the driver is going to be removed from
7872 static void ixgbe_remove(struct pci_dev *pdev)
7874 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7875 struct net_device *netdev = adapter->netdev;
7877 ixgbe_dbg_adapter_exit(adapter);
7879 set_bit(__IXGBE_DOWN, &adapter->state);
7880 cancel_work_sync(&adapter->service_task);
7883 #ifdef CONFIG_IXGBE_DCA
7884 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7885 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7886 dca_remove_requester(&pdev->dev);
7887 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7891 #ifdef CONFIG_IXGBE_HWMON
7892 ixgbe_sysfs_exit(adapter);
7893 #endif /* CONFIG_IXGBE_HWMON */
7895 /* remove the added san mac */
7896 ixgbe_del_sanmac_netdev(netdev);
7898 if (netdev->reg_state == NETREG_REGISTERED)
7899 unregister_netdev(netdev);
7901 #ifdef CONFIG_PCI_IOV
7903 * Only disable SR-IOV on unload if the user specified the now
7904 * deprecated max_vfs module parameter.
7907 ixgbe_disable_sriov(adapter);
7909 ixgbe_clear_interrupt_scheme(adapter);
7911 ixgbe_release_hw_control(adapter);
7914 kfree(adapter->ixgbe_ieee_pfc);
7915 kfree(adapter->ixgbe_ieee_ets);
7918 iounmap(adapter->hw.hw_addr);
7919 pci_release_selected_regions(pdev, pci_select_bars(pdev,
7922 e_dev_info("complete\n");
7924 free_netdev(netdev);
7926 pci_disable_pcie_error_reporting(pdev);
7928 pci_disable_device(pdev);
7932 * ixgbe_io_error_detected - called when PCI error is detected
7933 * @pdev: Pointer to PCI device
7934 * @state: The current pci connection state
7936 * This function is called after a PCI bus error affecting
7937 * this device has been detected.
7939 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7940 pci_channel_state_t state)
7942 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7943 struct net_device *netdev = adapter->netdev;
7945 #ifdef CONFIG_PCI_IOV
7946 struct pci_dev *bdev, *vfdev;
7947 u32 dw0, dw1, dw2, dw3;
7949 u16 req_id, pf_func;
7951 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7952 adapter->num_vfs == 0)
7953 goto skip_bad_vf_detection;
7955 bdev = pdev->bus->self;
7956 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
7957 bdev = bdev->bus->self;
7960 goto skip_bad_vf_detection;
7962 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
7964 goto skip_bad_vf_detection;
7966 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
7967 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
7968 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
7969 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
7972 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
7973 if (!(req_id & 0x0080))
7974 goto skip_bad_vf_detection;
7976 pf_func = req_id & 0x01;
7977 if ((pf_func & 1) == (pdev->devfn & 1)) {
7978 unsigned int device_id;
7980 vf = (req_id & 0x7F) >> 1;
7981 e_dev_err("VF %d has caused a PCIe error\n", vf);
7982 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
7983 "%8.8x\tdw3: %8.8x\n",
7984 dw0, dw1, dw2, dw3);
7985 switch (adapter->hw.mac.type) {
7986 case ixgbe_mac_82599EB:
7987 device_id = IXGBE_82599_VF_DEVICE_ID;
7989 case ixgbe_mac_X540:
7990 device_id = IXGBE_X540_VF_DEVICE_ID;
7997 /* Find the pci device of the offending VF */
7998 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
8000 if (vfdev->devfn == (req_id & 0xFF))
8002 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
8006 * There's a slim chance the VF could have been hot plugged,
8007 * so if it is no longer present we don't need to issue the
8008 * VFLR. Just clean up the AER in that case.
8011 e_dev_err("Issuing VFLR to VF %d\n", vf);
8012 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
8013 /* Free device reference count */
8017 pci_cleanup_aer_uncorrect_error_status(pdev);
8021 * Even though the error may have occurred on the other port
8022 * we still need to increment the vf error reference count for
8023 * both ports because the I/O resume function will be called
8026 adapter->vferr_refcount++;
8028 return PCI_ERS_RESULT_RECOVERED;
8030 skip_bad_vf_detection:
8031 #endif /* CONFIG_PCI_IOV */
8032 netif_device_detach(netdev);
8034 if (state == pci_channel_io_perm_failure)
8035 return PCI_ERS_RESULT_DISCONNECT;
8037 if (netif_running(netdev))
8038 ixgbe_down(adapter);
8039 pci_disable_device(pdev);
8041 /* Request a slot reset. */
8042 return PCI_ERS_RESULT_NEED_RESET;
8046 * ixgbe_io_slot_reset - called after the pci bus has been reset.
8047 * @pdev: Pointer to PCI device
8049 * Restart the card from scratch, as if from a cold-boot.
8051 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
8053 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8054 pci_ers_result_t result;
8057 if (pci_enable_device_mem(pdev)) {
8058 e_err(probe, "Cannot re-enable PCI device after reset.\n");
8059 result = PCI_ERS_RESULT_DISCONNECT;
8061 pci_set_master(pdev);
8062 pci_restore_state(pdev);
8063 pci_save_state(pdev);
8065 pci_wake_from_d3(pdev, false);
8067 ixgbe_reset(adapter);
8068 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
8069 result = PCI_ERS_RESULT_RECOVERED;
8072 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8074 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
8075 "failed 0x%0x\n", err);
8076 /* non-fatal, continue */
8083 * ixgbe_io_resume - called when traffic can start flowing again.
8084 * @pdev: Pointer to PCI device
8086 * This callback is called when the error recovery driver tells us that
8087 * its OK to resume normal operation.
8089 static void ixgbe_io_resume(struct pci_dev *pdev)
8091 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8092 struct net_device *netdev = adapter->netdev;
8094 #ifdef CONFIG_PCI_IOV
8095 if (adapter->vferr_refcount) {
8096 e_info(drv, "Resuming after VF err\n");
8097 adapter->vferr_refcount--;
8102 if (netif_running(netdev))
8105 netif_device_attach(netdev);
8108 static const struct pci_error_handlers ixgbe_err_handler = {
8109 .error_detected = ixgbe_io_error_detected,
8110 .slot_reset = ixgbe_io_slot_reset,
8111 .resume = ixgbe_io_resume,
8114 static struct pci_driver ixgbe_driver = {
8115 .name = ixgbe_driver_name,
8116 .id_table = ixgbe_pci_tbl,
8117 .probe = ixgbe_probe,
8118 .remove = ixgbe_remove,
8120 .suspend = ixgbe_suspend,
8121 .resume = ixgbe_resume,
8123 .shutdown = ixgbe_shutdown,
8124 .sriov_configure = ixgbe_pci_sriov_configure,
8125 .err_handler = &ixgbe_err_handler
8129 * ixgbe_init_module - Driver Registration Routine
8131 * ixgbe_init_module is the first routine called when the driver is
8132 * loaded. All it does is register with the PCI subsystem.
8134 static int __init ixgbe_init_module(void)
8137 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
8138 pr_info("%s\n", ixgbe_copyright);
8142 ret = pci_register_driver(&ixgbe_driver);
8148 #ifdef CONFIG_IXGBE_DCA
8149 dca_register_notify(&dca_notifier);
8155 module_init(ixgbe_init_module);
8158 * ixgbe_exit_module - Driver Exit Cleanup Routine
8160 * ixgbe_exit_module is called just before the driver is removed
8163 static void __exit ixgbe_exit_module(void)
8165 #ifdef CONFIG_IXGBE_DCA
8166 dca_unregister_notify(&dca_notifier);
8168 pci_unregister_driver(&ixgbe_driver);
8172 rcu_barrier(); /* Wait for completion of call_rcu()'s */
8175 #ifdef CONFIG_IXGBE_DCA
8176 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
8181 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
8182 __ixgbe_notify_dca);
8184 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
8187 #endif /* CONFIG_IXGBE_DCA */
8189 module_exit(ixgbe_exit_module);