drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2014 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 #include <linux/pci.h>
  30 #include <linux/delay.h>
  31 #include <linux/sched.h>
  32
  33 #include "ixgbe.h"
  34 #include "ixgbe_phy.h"
  35
  36 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
  37 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  38 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  39 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  40 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  41 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  42 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  43 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  44 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  45 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  46 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
  47 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
  48 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
  49 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
  50 static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw);
  51
  52 /**
  53  *  ixgbe_identify_phy_generic - Get physical layer module
  54  *  @hw: pointer to hardware structure
  55  *
  56  *  Determines the physical layer module found on the current adapter.
  57  **/
  58 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
  59 {
  60         u32 phy_addr;
  61         u16 ext_ability = 0;
  62
  63         if (hw->phy.type == ixgbe_phy_unknown) {
  64                 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
  65                         hw->phy.mdio.prtad = phy_addr;
  66                         if (mdio45_probe(&hw->phy.mdio, phy_addr) == 0) {
  67                                 ixgbe_get_phy_id(hw);
  68                                 hw->phy.type =
  69                                         ixgbe_get_phy_type_from_id(hw->phy.id);
  70
  71                                 if (hw->phy.type == ixgbe_phy_unknown) {
  72                                         hw->phy.ops.read_reg(hw,
  73                                                              MDIO_PMA_EXTABLE,
  74                                                              MDIO_MMD_PMAPMD,
  75                                                              &ext_ability);
  76                                         if (ext_ability &
  77                                             (MDIO_PMA_EXTABLE_10GBT |
  78                                              MDIO_PMA_EXTABLE_1000BT))
  79                                                 hw->phy.type =
  80                                                          ixgbe_phy_cu_unknown;
  81                                         else
  82                                                 hw->phy.type =
  83                                                          ixgbe_phy_generic;
  84                                 }
  85
  86                                 return 0;
  87                         }
  88                 }
  89                 /* clear value if nothing found */
  90                 hw->phy.mdio.prtad = 0;
  91                 return IXGBE_ERR_PHY_ADDR_INVALID;
  92         }
  93         return 0;
  94 }
  95
  96 /**
  97  * ixgbe_check_reset_blocked - check status of MNG FW veto bit
  98  * @hw: pointer to the hardware structure
  99  *
 100  * This function checks the MMNGC.MNG_VETO bit to see if there are
 101  * any constraints on link from manageability.  For MAC's that don't
 102  * have this bit just return false since the link can not be blocked
 103  * via this method.
 104  **/
 105 bool ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
 106 {
 107         u32 mmngc;
 108
 109         /* If we don't have this bit, it can't be blocking */
 110         if (hw->mac.type == ixgbe_mac_82598EB)
 111                 return false;
 112
 113         mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
 114         if (mmngc & IXGBE_MMNGC_MNG_VETO) {
 115                 hw_dbg(hw, "MNG_VETO bit detected.\n");
 116                 return true;
 117         }
 118
 119         return false;
 120 }
 121
 122 /**
 123  *  ixgbe_get_phy_id - Get the phy type
 124  *  @hw: pointer to hardware structure
 125  *
 126  **/
 127 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 128 {
 129         u32 status;
 130         u16 phy_id_high = 0;
 131         u16 phy_id_low = 0;
 132
 133         status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
 134                                       &phy_id_high);
 135
 136         if (status == 0) {
 137                 hw->phy.id = (u32)(phy_id_high << 16);
 138                 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
 139                                               &phy_id_low);
 140                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 141                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 142         }
 143         return status;
 144 }
 145
 146 /**
 147  *  ixgbe_get_phy_type_from_id - Get the phy type
 148  *  @hw: pointer to hardware structure
 149  *
 150  **/
 151 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 152 {
 153         enum ixgbe_phy_type phy_type;
 154
 155         switch (phy_id) {
 156         case TN1010_PHY_ID:
 157                 phy_type = ixgbe_phy_tn;
 158                 break;
 159         case X540_PHY_ID:
 160                 phy_type = ixgbe_phy_aq;
 161                 break;
 162         case QT2022_PHY_ID:
 163                 phy_type = ixgbe_phy_qt;
 164                 break;
 165         case ATH_PHY_ID:
 166                 phy_type = ixgbe_phy_nl;
 167                 break;
 168         default:
 169                 phy_type = ixgbe_phy_unknown;
 170                 break;
 171         }
 172
 173         return phy_type;
 174 }
 175
 176 /**
 177  *  ixgbe_reset_phy_generic - Performs a PHY reset
 178  *  @hw: pointer to hardware structure
 179  **/
 180 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 181 {
 182         u32 i;
 183         u16 ctrl = 0;
 184         s32 status = 0;
 185
 186         if (hw->phy.type == ixgbe_phy_unknown)
 187                 status = ixgbe_identify_phy_generic(hw);
 188
 189         if (status != 0 || hw->phy.type == ixgbe_phy_none)
 190                 return status;
 191
 192         /* Don't reset PHY if it's shut down due to overtemp. */
 193         if (!hw->phy.reset_if_overtemp &&
 194             (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 195                 return 0;
 196
 197         /* Blocked by MNG FW so bail */
 198         if (ixgbe_check_reset_blocked(hw))
 199                 return 0;
 200
 201         /*
 202          * Perform soft PHY reset to the PHY_XS.
 203          * This will cause a soft reset to the PHY
 204          */
 205         hw->phy.ops.write_reg(hw, MDIO_CTRL1,
 206                               MDIO_MMD_PHYXS,
 207                               MDIO_CTRL1_RESET);
 208
 209         /*
 210          * Poll for reset bit to self-clear indicating reset is complete.
 211          * Some PHYs could take up to 3 seconds to complete and need about
 212          * 1.7 usec delay after the reset is complete.
 213          */
 214         for (i = 0; i < 30; i++) {
 215                 msleep(100);
 216                 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
 217                                      MDIO_MMD_PHYXS, &ctrl);
 218                 if (!(ctrl & MDIO_CTRL1_RESET)) {
 219                         udelay(2);
 220                         break;
 221                 }
 222         }
 223
 224         if (ctrl & MDIO_CTRL1_RESET) {
 225                 hw_dbg(hw, "PHY reset polling failed to complete.\n");
 226                 return IXGBE_ERR_RESET_FAILED;
 227         }
 228
 229         return 0;
 230 }
 231
 232 /**
 233  *  ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
 234  *  the SWFW lock
 235  *  @hw: pointer to hardware structure
 236  *  @reg_addr: 32 bit address of PHY register to read
 237  *  @phy_data: Pointer to read data from PHY register
 238  **/
 239 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
 240                        u16 *phy_data)
 241 {
 242         u32 i, data, command;
 243
 244         /* Setup and write the address cycle command */
 245         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 246                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 247                    (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 248                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 249
 250         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 251
 252         /* Check every 10 usec to see if the address cycle completed.
 253          * The MDI Command bit will clear when the operation is
 254          * complete
 255          */
 256         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 257                 udelay(10);
 258
 259                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 260                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 261                                 break;
 262         }
 263
 264
 265         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 266                 hw_dbg(hw, "PHY address command did not complete.\n");
 267                 return IXGBE_ERR_PHY;
 268         }
 269
 270         /* Address cycle complete, setup and write the read
 271          * command
 272          */
 273         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 274                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 275                    (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 276                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 277
 278         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 279
 280         /* Check every 10 usec to see if the address cycle
 281          * completed. The MDI Command bit will clear when the
 282          * operation is complete
 283          */
 284         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 285                 udelay(10);
 286
 287                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 288                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 289                         break;
 290         }
 291
 292         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 293                 hw_dbg(hw, "PHY read command didn't complete\n");
 294                 return IXGBE_ERR_PHY;
 295         }
 296
 297         /* Read operation is complete.  Get the data
 298          * from MSRWD
 299          */
 300         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 301         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 302         *phy_data = (u16)(data);
 303
 304         return 0;
 305 }
 306
 307 /**
 308  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 309  *  using the SWFW lock - this function is needed in most cases
 310  *  @hw: pointer to hardware structure
 311  *  @reg_addr: 32 bit address of PHY register to read
 312  *  @phy_data: Pointer to read data from PHY register
 313  **/
 314 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 315                                u32 device_type, u16 *phy_data)
 316 {
 317         s32 status;
 318         u16 gssr;
 319
 320         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
 321                 gssr = IXGBE_GSSR_PHY1_SM;
 322         else
 323                 gssr = IXGBE_GSSR_PHY0_SM;
 324
 325         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
 326                 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
 327                                                 phy_data);
 328                 hw->mac.ops.release_swfw_sync(hw, gssr);
 329         } else {
 330                 return IXGBE_ERR_SWFW_SYNC;
 331         }
 332
 333         return status;
 334 }
 335
 336 /**
 337  *  ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
 338  *  without SWFW lock
 339  *  @hw: pointer to hardware structure
 340  *  @reg_addr: 32 bit PHY register to write
 341  *  @device_type: 5 bit device type
 342  *  @phy_data: Data to write to the PHY register
 343  **/
 344 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
 345                                 u32 device_type, u16 phy_data)
 346 {
 347         u32 i, command;
 348
 349         /* Put the data in the MDI single read and write data register*/
 350         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 351
 352         /* Setup and write the address cycle command */
 353         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 354                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 355                    (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 356                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 357
 358         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 359
 360         /*
 361          * Check every 10 usec to see if the address cycle completed.
 362          * The MDI Command bit will clear when the operation is
 363          * complete
 364          */
 365         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 366                 udelay(10);
 367
 368                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 369                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 370                         break;
 371         }
 372
 373         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 374                 hw_dbg(hw, "PHY address cmd didn't complete\n");
 375                 return IXGBE_ERR_PHY;
 376         }
 377
 378         /*
 379          * Address cycle complete, setup and write the write
 380          * command
 381          */
 382         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 383                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 384                    (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 385                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 386
 387         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 388
 389         /* Check every 10 usec to see if the address cycle
 390          * completed. The MDI Command bit will clear when the
 391          * operation is complete
 392          */
 393         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 394                 udelay(10);
 395
 396                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 397                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 398                         break;
 399         }
 400
 401         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 402                 hw_dbg(hw, "PHY write cmd didn't complete\n");
 403                 return IXGBE_ERR_PHY;
 404         }
 405
 406         return 0;
 407 }
 408
 409 /**
 410  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 411  *  using SWFW lock- this function is needed in most cases
 412  *  @hw: pointer to hardware structure
 413  *  @reg_addr: 32 bit PHY register to write
 414  *  @device_type: 5 bit device type
 415  *  @phy_data: Data to write to the PHY register
 416  **/
 417 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 418                                 u32 device_type, u16 phy_data)
 419 {
 420         s32 status;
 421         u16 gssr;
 422
 423         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
 424                 gssr = IXGBE_GSSR_PHY1_SM;
 425         else
 426                 gssr = IXGBE_GSSR_PHY0_SM;
 427
 428         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
 429                 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
 430                                                  phy_data);
 431                 hw->mac.ops.release_swfw_sync(hw, gssr);
 432         } else {
 433                 return IXGBE_ERR_SWFW_SYNC;
 434         }
 435
 436         return status;
 437 }
 438
 439 /**
 440  *  ixgbe_setup_phy_link_generic - Set and restart autoneg
 441  *  @hw: pointer to hardware structure
 442  *
 443  *  Restart autonegotiation and PHY and waits for completion.
 444  **/
 445 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 446 {
 447         s32 status = 0;
 448         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 449         bool autoneg = false;
 450         ixgbe_link_speed speed;
 451
 452         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 453
 454         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 455                 /* Set or unset auto-negotiation 10G advertisement */
 456                 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
 457                                      MDIO_MMD_AN,
 458                                      &autoneg_reg);
 459
 460                 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
 461                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 462                         autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
 463
 464                 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
 465                                       MDIO_MMD_AN,
 466                                       autoneg_reg);
 467         }
 468
 469         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 470                 /* Set or unset auto-negotiation 1G advertisement */
 471                 hw->phy.ops.read_reg(hw,
 472                                      IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 473                                      MDIO_MMD_AN,
 474                                      &autoneg_reg);
 475
 476                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
 477                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 478                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
 479
 480                 hw->phy.ops.write_reg(hw,
 481                                       IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 482                                       MDIO_MMD_AN,
 483                                       autoneg_reg);
 484         }
 485
 486         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 487                 /* Set or unset auto-negotiation 100M advertisement */
 488                 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
 489                                      MDIO_MMD_AN,
 490                                      &autoneg_reg);
 491
 492                 autoneg_reg &= ~(ADVERTISE_100FULL |
 493                                  ADVERTISE_100HALF);
 494                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 495                         autoneg_reg |= ADVERTISE_100FULL;
 496
 497                 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
 498                                       MDIO_MMD_AN,
 499                                       autoneg_reg);
 500         }
 501
 502         /* Blocked by MNG FW so don't reset PHY */
 503         if (ixgbe_check_reset_blocked(hw))
 504                 return 0;
 505
 506         /* Restart PHY autonegotiation and wait for completion */
 507         hw->phy.ops.read_reg(hw, MDIO_CTRL1,
 508                              MDIO_MMD_AN, &autoneg_reg);
 509
 510         autoneg_reg |= MDIO_AN_CTRL1_RESTART;
 511
 512         hw->phy.ops.write_reg(hw, MDIO_CTRL1,
 513                               MDIO_MMD_AN, autoneg_reg);
 514
 515         return status;
 516 }
 517
 518 /**
 519  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 520  *  @hw: pointer to hardware structure
 521  *  @speed: new link speed
 522  **/
 523 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 524                                        ixgbe_link_speed speed,
 525                                        bool autoneg_wait_to_complete)
 526 {
 527
 528         /*
 529          * Clear autoneg_advertised and set new values based on input link
 530          * speed.
 531          */
 532         hw->phy.autoneg_advertised = 0;
 533
 534         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 535                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 536
 537         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 538                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 539
 540         if (speed & IXGBE_LINK_SPEED_100_FULL)
 541                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
 542
 543         /* Setup link based on the new speed settings */
 544         hw->phy.ops.setup_link(hw);
 545
 546         return 0;
 547 }
 548
 549 /**
 550  * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
 551  * @hw: pointer to hardware structure
 552  * @speed: pointer to link speed
 553  * @autoneg: boolean auto-negotiation value
 554  *
 555  * Determines the link capabilities by reading the AUTOC register.
 556  */
 557 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 558                                                ixgbe_link_speed *speed,
 559                                                bool *autoneg)
 560 {
 561         s32 status;
 562         u16 speed_ability;
 563
 564         *speed = 0;
 565         *autoneg = true;
 566
 567         status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
 568                                       &speed_ability);
 569
 570         if (status == 0) {
 571                 if (speed_ability & MDIO_SPEED_10G)
 572                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 573                 if (speed_ability & MDIO_PMA_SPEED_1000)
 574                         *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 575                 if (speed_ability & MDIO_PMA_SPEED_100)
 576                         *speed |= IXGBE_LINK_SPEED_100_FULL;
 577         }
 578
 579         /* Internal PHY does not support 100 Mbps */
 580         if (hw->mac.type == ixgbe_mac_X550EM_x)
 581                 *speed &= ~IXGBE_LINK_SPEED_100_FULL;
 582
 583         return status;
 584 }
 585
 586 /**
 587  *  ixgbe_check_phy_link_tnx - Determine link and speed status
 588  *  @hw: pointer to hardware structure
 589  *
 590  *  Reads the VS1 register to determine if link is up and the current speed for
 591  *  the PHY.
 592  **/
 593 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
 594                              bool *link_up)
 595 {
 596         s32 status;
 597         u32 time_out;
 598         u32 max_time_out = 10;
 599         u16 phy_link = 0;
 600         u16 phy_speed = 0;
 601         u16 phy_data = 0;
 602
 603         /* Initialize speed and link to default case */
 604         *link_up = false;
 605         *speed = IXGBE_LINK_SPEED_10GB_FULL;
 606
 607         /*
 608          * Check current speed and link status of the PHY register.
 609          * This is a vendor specific register and may have to
 610          * be changed for other copper PHYs.
 611          */
 612         for (time_out = 0; time_out < max_time_out; time_out++) {
 613                 udelay(10);
 614                 status = hw->phy.ops.read_reg(hw,
 615                                               MDIO_STAT1,
 616                                               MDIO_MMD_VEND1,
 617                                               &phy_data);
 618                 phy_link = phy_data &
 619                             IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
 620                 phy_speed = phy_data &
 621                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
 622                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
 623                         *link_up = true;
 624                         if (phy_speed ==
 625                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
 626                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 627                         break;
 628                 }
 629         }
 630
 631         return status;
 632 }
 633
 634 /**
 635  *      ixgbe_setup_phy_link_tnx - Set and restart autoneg
 636  *      @hw: pointer to hardware structure
 637  *
 638  *      Restart autonegotiation and PHY and waits for completion.
 639  *      This function always returns success, this is nessary since
 640  *      it is called via a function pointer that could call other
 641  *      functions that could return an error.
 642  **/
 643 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
 644 {
 645         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 646         bool autoneg = false;
 647         ixgbe_link_speed speed;
 648
 649         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 650
 651         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 652                 /* Set or unset auto-negotiation 10G advertisement */
 653                 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
 654                                      MDIO_MMD_AN,
 655                                      &autoneg_reg);
 656
 657                 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
 658                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 659                         autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
 660
 661                 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
 662                                       MDIO_MMD_AN,
 663                                       autoneg_reg);
 664         }
 665
 666         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 667                 /* Set or unset auto-negotiation 1G advertisement */
 668                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
 669                                      MDIO_MMD_AN,
 670                                      &autoneg_reg);
 671
 672                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
 673                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 674                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
 675
 676                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
 677                                       MDIO_MMD_AN,
 678                                       autoneg_reg);
 679         }
 680
 681         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 682                 /* Set or unset auto-negotiation 100M advertisement */
 683                 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
 684                                      MDIO_MMD_AN,
 685                                      &autoneg_reg);
 686
 687                 autoneg_reg &= ~(ADVERTISE_100FULL |
 688                                  ADVERTISE_100HALF);
 689                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 690                         autoneg_reg |= ADVERTISE_100FULL;
 691
 692                 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
 693                                       MDIO_MMD_AN,
 694                                       autoneg_reg);
 695         }
 696
 697         /* Blocked by MNG FW so don't reset PHY */
 698         if (ixgbe_check_reset_blocked(hw))
 699                 return 0;
 700
 701         /* Restart PHY autonegotiation and wait for completion */
 702         hw->phy.ops.read_reg(hw, MDIO_CTRL1,
 703                              MDIO_MMD_AN, &autoneg_reg);
 704
 705         autoneg_reg |= MDIO_AN_CTRL1_RESTART;
 706
 707         hw->phy.ops.write_reg(hw, MDIO_CTRL1,
 708                               MDIO_MMD_AN, autoneg_reg);
 709         return 0;
 710 }
 711
 712 /**
 713  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
 714  *  @hw: pointer to hardware structure
 715  *  @firmware_version: pointer to the PHY Firmware Version
 716  **/
 717 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
 718                                        u16 *firmware_version)
 719 {
 720         s32 status;
 721
 722         status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
 723                                       MDIO_MMD_VEND1,
 724                                       firmware_version);
 725
 726         return status;
 727 }
 728
 729 /**
 730  *  ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
 731  *  @hw: pointer to hardware structure
 732  *  @firmware_version: pointer to the PHY Firmware Version
 733  **/
 734 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
 735                                            u16 *firmware_version)
 736 {
 737         s32 status;
 738
 739         status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
 740                                       MDIO_MMD_VEND1,
 741                                       firmware_version);
 742
 743         return status;
 744 }
 745
 746 /**
 747  *  ixgbe_reset_phy_nl - Performs a PHY reset
 748  *  @hw: pointer to hardware structure
 749  **/
 750 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
 751 {
 752         u16 phy_offset, control, eword, edata, block_crc;
 753         bool end_data = false;
 754         u16 list_offset, data_offset;
 755         u16 phy_data = 0;
 756         s32 ret_val;
 757         u32 i;
 758
 759         /* Blocked by MNG FW so bail */
 760         if (ixgbe_check_reset_blocked(hw))
 761                 return 0;
 762
 763         hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
 764
 765         /* reset the PHY and poll for completion */
 766         hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
 767                               (phy_data | MDIO_CTRL1_RESET));
 768
 769         for (i = 0; i < 100; i++) {
 770                 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
 771                                      &phy_data);
 772                 if ((phy_data & MDIO_CTRL1_RESET) == 0)
 773                         break;
 774                 usleep_range(10000, 20000);
 775         }
 776
 777         if ((phy_data & MDIO_CTRL1_RESET) != 0) {
 778                 hw_dbg(hw, "PHY reset did not complete.\n");
 779                 return IXGBE_ERR_PHY;
 780         }
 781
 782         /* Get init offsets */
 783         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
 784                                                       &data_offset);
 785         if (ret_val)
 786                 return ret_val;
 787
 788         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
 789         data_offset++;
 790         while (!end_data) {
 791                 /*
 792                  * Read control word from PHY init contents offset
 793                  */
 794                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
 795                 if (ret_val)
 796                         goto err_eeprom;
 797                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
 798                            IXGBE_CONTROL_SHIFT_NL;
 799                 edata = eword & IXGBE_DATA_MASK_NL;
 800                 switch (control) {
 801                 case IXGBE_DELAY_NL:
 802                         data_offset++;
 803                         hw_dbg(hw, "DELAY: %d MS\n", edata);
 804                         usleep_range(edata * 1000, edata * 2000);
 805                         break;
 806                 case IXGBE_DATA_NL:
 807                         hw_dbg(hw, "DATA:\n");
 808                         data_offset++;
 809                         ret_val = hw->eeprom.ops.read(hw, data_offset++,
 810                                                       &phy_offset);
 811                         if (ret_val)
 812                                 goto err_eeprom;
 813                         for (i = 0; i < edata; i++) {
 814                                 ret_val = hw->eeprom.ops.read(hw, data_offset,
 815                                                               &eword);
 816                                 if (ret_val)
 817                                         goto err_eeprom;
 818                                 hw->phy.ops.write_reg(hw, phy_offset,
 819                                                       MDIO_MMD_PMAPMD, eword);
 820                                 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
 821                                        phy_offset);
 822                                 data_offset++;
 823                                 phy_offset++;
 824                         }
 825                         break;
 826                 case IXGBE_CONTROL_NL:
 827                         data_offset++;
 828                         hw_dbg(hw, "CONTROL:\n");
 829                         if (edata == IXGBE_CONTROL_EOL_NL) {
 830                                 hw_dbg(hw, "EOL\n");
 831                                 end_data = true;
 832                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
 833                                 hw_dbg(hw, "SOL\n");
 834                         } else {
 835                                 hw_dbg(hw, "Bad control value\n");
 836                                 return IXGBE_ERR_PHY;
 837                         }
 838                         break;
 839                 default:
 840                         hw_dbg(hw, "Bad control type\n");
 841                         return IXGBE_ERR_PHY;
 842                 }
 843         }
 844
 845         return ret_val;
 846
 847 err_eeprom:
 848         hw_err(hw, "eeprom read at offset %d failed\n", data_offset);
 849         return IXGBE_ERR_PHY;
 850 }
 851
 852 /**
 853  *  ixgbe_identify_module_generic - Identifies module type
 854  *  @hw: pointer to hardware structure
 855  *
 856  *  Determines HW type and calls appropriate function.
 857  **/
 858 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
 859 {
 860         switch (hw->mac.ops.get_media_type(hw)) {
 861         case ixgbe_media_type_fiber:
 862                 return ixgbe_identify_sfp_module_generic(hw);
 863         case ixgbe_media_type_fiber_qsfp:
 864                 return ixgbe_identify_qsfp_module_generic(hw);
 865         default:
 866                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
 867                 return IXGBE_ERR_SFP_NOT_PRESENT;
 868         }
 869
 870         return IXGBE_ERR_SFP_NOT_PRESENT;
 871 }
 872
 873 /**
 874  *  ixgbe_identify_sfp_module_generic - Identifies SFP modules
 875  *  @hw: pointer to hardware structure
 876  *
 877  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
 878  **/
 879 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
 880 {
 881         struct ixgbe_adapter *adapter = hw->back;
 882         s32 status;
 883         u32 vendor_oui = 0;
 884         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
 885         u8 identifier = 0;
 886         u8 comp_codes_1g = 0;
 887         u8 comp_codes_10g = 0;
 888         u8 oui_bytes[3] = {0, 0, 0};
 889         u8 cable_tech = 0;
 890         u8 cable_spec = 0;
 891         u16 enforce_sfp = 0;
 892
 893         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
 894                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
 895                 return IXGBE_ERR_SFP_NOT_PRESENT;
 896         }
 897
 898         status = hw->phy.ops.read_i2c_eeprom(hw,
 899                                              IXGBE_SFF_IDENTIFIER,
 900                                              &identifier);
 901
 902         if (status)
 903                 goto err_read_i2c_eeprom;
 904
 905         /* LAN ID is needed for sfp_type determination */
 906         hw->mac.ops.set_lan_id(hw);
 907
 908         if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
 909                 hw->phy.type = ixgbe_phy_sfp_unsupported;
 910                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
 911         }
 912         status = hw->phy.ops.read_i2c_eeprom(hw,
 913                                              IXGBE_SFF_1GBE_COMP_CODES,
 914                                              &comp_codes_1g);
 915
 916         if (status)
 917                 goto err_read_i2c_eeprom;
 918
 919         status = hw->phy.ops.read_i2c_eeprom(hw,
 920                                              IXGBE_SFF_10GBE_COMP_CODES,
 921                                              &comp_codes_10g);
 922
 923         if (status)
 924                 goto err_read_i2c_eeprom;
 925         status = hw->phy.ops.read_i2c_eeprom(hw,
 926                                              IXGBE_SFF_CABLE_TECHNOLOGY,
 927                                              &cable_tech);
 928
 929         if (status)
 930                 goto err_read_i2c_eeprom;
 931
 932          /* ID Module
 933           * =========
 934           * 0   SFP_DA_CU
 935           * 1   SFP_SR
 936           * 2   SFP_LR
 937           * 3   SFP_DA_CORE0 - 82599-specific
 938           * 4   SFP_DA_CORE1 - 82599-specific
 939           * 5   SFP_SR/LR_CORE0 - 82599-specific
 940           * 6   SFP_SR/LR_CORE1 - 82599-specific
 941           * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
 942           * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
 943           * 9   SFP_1g_cu_CORE0 - 82599-specific
 944           * 10  SFP_1g_cu_CORE1 - 82599-specific
 945           * 11  SFP_1g_sx_CORE0 - 82599-specific
 946           * 12  SFP_1g_sx_CORE1 - 82599-specific
 947           */
 948         if (hw->mac.type == ixgbe_mac_82598EB) {
 949                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
 950                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
 951                 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
 952                         hw->phy.sfp_type = ixgbe_sfp_type_sr;
 953                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
 954                         hw->phy.sfp_type = ixgbe_sfp_type_lr;
 955                 else
 956                         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
 957         } else if (hw->mac.type == ixgbe_mac_82599EB) {
 958                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
 959                         if (hw->bus.lan_id == 0)
 960                                 hw->phy.sfp_type =
 961                                              ixgbe_sfp_type_da_cu_core0;
 962                         else
 963                                 hw->phy.sfp_type =
 964                                              ixgbe_sfp_type_da_cu_core1;
 965                 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
 966                         hw->phy.ops.read_i2c_eeprom(
 967                                         hw, IXGBE_SFF_CABLE_SPEC_COMP,
 968                                         &cable_spec);
 969                         if (cable_spec &
 970                             IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
 971                                 if (hw->bus.lan_id == 0)
 972                                         hw->phy.sfp_type =
 973                                         ixgbe_sfp_type_da_act_lmt_core0;
 974                                 else
 975                                         hw->phy.sfp_type =
 976                                         ixgbe_sfp_type_da_act_lmt_core1;
 977                         } else {
 978                                 hw->phy.sfp_type =
 979                                                 ixgbe_sfp_type_unknown;
 980                         }
 981                 } else if (comp_codes_10g &
 982                            (IXGBE_SFF_10GBASESR_CAPABLE |
 983                             IXGBE_SFF_10GBASELR_CAPABLE)) {
 984                         if (hw->bus.lan_id == 0)
 985                                 hw->phy.sfp_type =
 986                                               ixgbe_sfp_type_srlr_core0;
 987                         else
 988                                 hw->phy.sfp_type =
 989                                               ixgbe_sfp_type_srlr_core1;
 990                 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
 991                         if (hw->bus.lan_id == 0)
 992                                 hw->phy.sfp_type =
 993                                         ixgbe_sfp_type_1g_cu_core0;
 994                         else
 995                                 hw->phy.sfp_type =
 996                                         ixgbe_sfp_type_1g_cu_core1;
 997                 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
 998                         if (hw->bus.lan_id == 0)
 999                                 hw->phy.sfp_type =
1000                                         ixgbe_sfp_type_1g_sx_core0;
1001                         else
1002                                 hw->phy.sfp_type =
1003                                         ixgbe_sfp_type_1g_sx_core1;
1004                 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1005                         if (hw->bus.lan_id == 0)
1006                                 hw->phy.sfp_type =
1007                                         ixgbe_sfp_type_1g_lx_core0;
1008                         else
1009                                 hw->phy.sfp_type =
1010                                         ixgbe_sfp_type_1g_lx_core1;
1011                 } else {
1012                         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1013                 }
1014         }
1015
1016         if (hw->phy.sfp_type != stored_sfp_type)
1017                 hw->phy.sfp_setup_needed = true;
1018
1019         /* Determine if the SFP+ PHY is dual speed or not. */
1020         hw->phy.multispeed_fiber = false;
1021         if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1022              (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1023             ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1024              (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1025                 hw->phy.multispeed_fiber = true;
1026
1027         /* Determine PHY vendor */
1028         if (hw->phy.type != ixgbe_phy_nl) {
1029                 hw->phy.id = identifier;
1030                 status = hw->phy.ops.read_i2c_eeprom(hw,
1031                                             IXGBE_SFF_VENDOR_OUI_BYTE0,
1032                                             &oui_bytes[0]);
1033
1034                 if (status != 0)
1035                         goto err_read_i2c_eeprom;
1036
1037                 status = hw->phy.ops.read_i2c_eeprom(hw,
1038                                             IXGBE_SFF_VENDOR_OUI_BYTE1,
1039                                             &oui_bytes[1]);
1040
1041                 if (status != 0)
1042                         goto err_read_i2c_eeprom;
1043
1044                 status = hw->phy.ops.read_i2c_eeprom(hw,
1045                                             IXGBE_SFF_VENDOR_OUI_BYTE2,
1046                                             &oui_bytes[2]);
1047
1048                 if (status != 0)
1049                         goto err_read_i2c_eeprom;
1050
1051                 vendor_oui =
1052                   ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1053                    (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1054                    (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1055
1056                 switch (vendor_oui) {
1057                 case IXGBE_SFF_VENDOR_OUI_TYCO:
1058                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1059                                 hw->phy.type =
1060                                             ixgbe_phy_sfp_passive_tyco;
1061                         break;
1062                 case IXGBE_SFF_VENDOR_OUI_FTL:
1063                         if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1064                                 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1065                         else
1066                                 hw->phy.type = ixgbe_phy_sfp_ftl;
1067                         break;
1068                 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1069                         hw->phy.type = ixgbe_phy_sfp_avago;
1070                         break;
1071                 case IXGBE_SFF_VENDOR_OUI_INTEL:
1072                         hw->phy.type = ixgbe_phy_sfp_intel;
1073                         break;
1074                 default:
1075                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1076                                 hw->phy.type =
1077                                          ixgbe_phy_sfp_passive_unknown;
1078                         else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1079                                 hw->phy.type =
1080                                         ixgbe_phy_sfp_active_unknown;
1081                         else
1082                                 hw->phy.type = ixgbe_phy_sfp_unknown;
1083                         break;
1084                 }
1085         }
1086
1087         /* Allow any DA cable vendor */
1088         if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1089             IXGBE_SFF_DA_ACTIVE_CABLE))
1090                 return 0;
1091
1092         /* Verify supported 1G SFP modules */
1093         if (comp_codes_10g == 0 &&
1094             !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1095               hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1096               hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1097               hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1098               hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1099               hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1100                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1101                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1102         }
1103
1104         /* Anything else 82598-based is supported */
1105         if (hw->mac.type == ixgbe_mac_82598EB)
1106                 return 0;
1107
1108         hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1109         if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1110             !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1111               hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1112               hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1113               hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1114               hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1115               hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1116                 /* Make sure we're a supported PHY type */
1117                 if (hw->phy.type == ixgbe_phy_sfp_intel)
1118                         return 0;
1119                 if (hw->allow_unsupported_sfp) {
1120                         e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics.  Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter.  Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1121                         return 0;
1122                 }
1123                 hw_dbg(hw, "SFP+ module not supported\n");
1124                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1125                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1126         }
1127         return 0;
1128
1129 err_read_i2c_eeprom:
1130         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1131         if (hw->phy.type != ixgbe_phy_nl) {
1132                 hw->phy.id = 0;
1133                 hw->phy.type = ixgbe_phy_unknown;
1134         }
1135         return IXGBE_ERR_SFP_NOT_PRESENT;
1136 }
1137
1138 /**
1139  * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1140  * @hw: pointer to hardware structure
1141  *
1142  * Searches for and identifies the QSFP module and assigns appropriate PHY type
1143  **/
1144 static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1145 {
1146         struct ixgbe_adapter *adapter = hw->back;
1147         s32 status;
1148         u32 vendor_oui = 0;
1149         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1150         u8 identifier = 0;
1151         u8 comp_codes_1g = 0;
1152         u8 comp_codes_10g = 0;
1153         u8 oui_bytes[3] = {0, 0, 0};
1154         u16 enforce_sfp = 0;
1155         u8 connector = 0;
1156         u8 cable_length = 0;
1157         u8 device_tech = 0;
1158         bool active_cable = false;
1159
1160         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1161                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1162                 return IXGBE_ERR_SFP_NOT_PRESENT;
1163         }
1164
1165         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1166                                              &identifier);
1167
1168         if (status != 0)
1169                 goto err_read_i2c_eeprom;
1170
1171         if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1172                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1173                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1174         }
1175
1176         hw->phy.id = identifier;
1177
1178         /* LAN ID is needed for sfp_type determination */
1179         hw->mac.ops.set_lan_id(hw);
1180
1181         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1182                                              &comp_codes_10g);
1183
1184         if (status != 0)
1185                 goto err_read_i2c_eeprom;
1186
1187         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1188                                              &comp_codes_1g);
1189
1190         if (status != 0)
1191                 goto err_read_i2c_eeprom;
1192
1193         if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1194                 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1195                 if (hw->bus.lan_id == 0)
1196                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1197                 else
1198                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1199         } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1200                                      IXGBE_SFF_10GBASELR_CAPABLE)) {
1201                 if (hw->bus.lan_id == 0)
1202                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1203                 else
1204                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1205         } else {
1206                 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1207                         active_cable = true;
1208
1209                 if (!active_cable) {
1210                         /* check for active DA cables that pre-date
1211                          * SFF-8436 v3.6
1212                          */
1213                         hw->phy.ops.read_i2c_eeprom(hw,
1214                                         IXGBE_SFF_QSFP_CONNECTOR,
1215                                         &connector);
1216
1217                         hw->phy.ops.read_i2c_eeprom(hw,
1218                                         IXGBE_SFF_QSFP_CABLE_LENGTH,
1219                                         &cable_length);
1220
1221                         hw->phy.ops.read_i2c_eeprom(hw,
1222                                         IXGBE_SFF_QSFP_DEVICE_TECH,
1223                                         &device_tech);
1224
1225                         if ((connector ==
1226                                      IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1227                             (cable_length > 0) &&
1228                             ((device_tech >> 4) ==
1229                                      IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1230                                 active_cable = true;
1231                 }
1232
1233                 if (active_cable) {
1234                         hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1235                         if (hw->bus.lan_id == 0)
1236                                 hw->phy.sfp_type =
1237                                                 ixgbe_sfp_type_da_act_lmt_core0;
1238                         else
1239                                 hw->phy.sfp_type =
1240                                                 ixgbe_sfp_type_da_act_lmt_core1;
1241                 } else {
1242                         /* unsupported module type */
1243                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1244                         return IXGBE_ERR_SFP_NOT_SUPPORTED;
1245                 }
1246         }
1247
1248         if (hw->phy.sfp_type != stored_sfp_type)
1249                 hw->phy.sfp_setup_needed = true;
1250
1251         /* Determine if the QSFP+ PHY is dual speed or not. */
1252         hw->phy.multispeed_fiber = false;
1253         if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1254              (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1255             ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1256              (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1257                 hw->phy.multispeed_fiber = true;
1258
1259         /* Determine PHY vendor for optical modules */
1260         if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1261                               IXGBE_SFF_10GBASELR_CAPABLE)) {
1262                 status = hw->phy.ops.read_i2c_eeprom(hw,
1263                                         IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1264                                         &oui_bytes[0]);
1265
1266                 if (status != 0)
1267                         goto err_read_i2c_eeprom;
1268
1269                 status = hw->phy.ops.read_i2c_eeprom(hw,
1270                                         IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1271                                         &oui_bytes[1]);
1272
1273                 if (status != 0)
1274                         goto err_read_i2c_eeprom;
1275
1276                 status = hw->phy.ops.read_i2c_eeprom(hw,
1277                                         IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1278                                         &oui_bytes[2]);
1279
1280                 if (status != 0)
1281                         goto err_read_i2c_eeprom;
1282
1283                 vendor_oui =
1284                         ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1285                          (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1286                          (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1287
1288                 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1289                         hw->phy.type = ixgbe_phy_qsfp_intel;
1290                 else
1291                         hw->phy.type = ixgbe_phy_qsfp_unknown;
1292
1293                 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1294                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1295                         /* Make sure we're a supported PHY type */
1296                         if (hw->phy.type == ixgbe_phy_qsfp_intel)
1297                                 return 0;
1298                         if (hw->allow_unsupported_sfp) {
1299                                 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1300                                 return 0;
1301                         }
1302                         hw_dbg(hw, "QSFP module not supported\n");
1303                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1304                         return IXGBE_ERR_SFP_NOT_SUPPORTED;
1305                 }
1306                 return 0;
1307         }
1308         return 0;
1309
1310 err_read_i2c_eeprom:
1311         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1312         hw->phy.id = 0;
1313         hw->phy.type = ixgbe_phy_unknown;
1314
1315         return IXGBE_ERR_SFP_NOT_PRESENT;
1316 }
1317
1318 /**
1319  *  ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1320  *  @hw: pointer to hardware structure
1321  *  @list_offset: offset to the SFP ID list
1322  *  @data_offset: offset to the SFP data block
1323  *
1324  *  Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1325  *  so it returns the offsets to the phy init sequence block.
1326  **/
1327 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1328                                         u16 *list_offset,
1329                                         u16 *data_offset)
1330 {
1331         u16 sfp_id;
1332         u16 sfp_type = hw->phy.sfp_type;
1333
1334         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1335                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1336
1337         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1338                 return IXGBE_ERR_SFP_NOT_PRESENT;
1339
1340         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1341             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1342                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1343
1344         /*
1345          * Limiting active cables and 1G Phys must be initialized as
1346          * SR modules
1347          */
1348         if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1349             sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1350             sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1351             sfp_type == ixgbe_sfp_type_1g_sx_core0)
1352                 sfp_type = ixgbe_sfp_type_srlr_core0;
1353         else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1354                  sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1355                  sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1356                  sfp_type == ixgbe_sfp_type_1g_sx_core1)
1357                 sfp_type = ixgbe_sfp_type_srlr_core1;
1358
1359         /* Read offset to PHY init contents */
1360         if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1361                 hw_err(hw, "eeprom read at %d failed\n",
1362                        IXGBE_PHY_INIT_OFFSET_NL);
1363                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1364         }
1365
1366         if ((!*list_offset) || (*list_offset == 0xFFFF))
1367                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1368
1369         /* Shift offset to first ID word */
1370         (*list_offset)++;
1371
1372         /*
1373          * Find the matching SFP ID in the EEPROM
1374          * and program the init sequence
1375          */
1376         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1377                 goto err_phy;
1378
1379         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1380                 if (sfp_id == sfp_type) {
1381                         (*list_offset)++;
1382                         if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1383                                 goto err_phy;
1384                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1385                                 hw_dbg(hw, "SFP+ module not supported\n");
1386                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1387                         } else {
1388                                 break;
1389                         }
1390                 } else {
1391                         (*list_offset) += 2;
1392                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1393                                 goto err_phy;
1394                 }
1395         }
1396
1397         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1398                 hw_dbg(hw, "No matching SFP+ module found\n");
1399                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1400         }
1401
1402         return 0;
1403
1404 err_phy:
1405         hw_err(hw, "eeprom read at offset %d failed\n", *list_offset);
1406         return IXGBE_ERR_PHY;
1407 }
1408
1409 /**
1410  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1411  *  @hw: pointer to hardware structure
1412  *  @byte_offset: EEPROM byte offset to read
1413  *  @eeprom_data: value read
1414  *
1415  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1416  **/
1417 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1418                                   u8 *eeprom_data)
1419 {
1420         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1421                                          IXGBE_I2C_EEPROM_DEV_ADDR,
1422                                          eeprom_data);
1423 }
1424
1425 /**
1426  *  ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1427  *  @hw: pointer to hardware structure
1428  *  @byte_offset: byte offset at address 0xA2
1429  *  @eeprom_data: value read
1430  *
1431  *  Performs byte read operation to SFP module's SFF-8472 data over I2C
1432  **/
1433 s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1434                                    u8 *sff8472_data)
1435 {
1436         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1437                                          IXGBE_I2C_EEPROM_DEV_ADDR2,
1438                                          sff8472_data);
1439 }
1440
1441 /**
1442  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1443  *  @hw: pointer to hardware structure
1444  *  @byte_offset: EEPROM byte offset to write
1445  *  @eeprom_data: value to write
1446  *
1447  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
1448  **/
1449 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1450                                    u8 eeprom_data)
1451 {
1452         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1453                                           IXGBE_I2C_EEPROM_DEV_ADDR,
1454                                           eeprom_data);
1455 }
1456
1457 /**
1458  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1459  *  @hw: pointer to hardware structure
1460  *  @byte_offset: byte offset to read
1461  *  @data: value read
1462  *
1463  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
1464  *  a specified device address.
1465  **/
1466 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1467                                 u8 dev_addr, u8 *data)
1468 {
1469         s32 status;
1470         u32 max_retry = 10;
1471         u32 retry = 0;
1472         u16 swfw_mask = 0;
1473         bool nack = true;
1474         *data = 0;
1475
1476         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1477                 swfw_mask = IXGBE_GSSR_PHY1_SM;
1478         else
1479                 swfw_mask = IXGBE_GSSR_PHY0_SM;
1480
1481         do {
1482                 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
1483                         return IXGBE_ERR_SWFW_SYNC;
1484
1485                 ixgbe_i2c_start(hw);
1486
1487                 /* Device Address and write indication */
1488                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1489                 if (status != 0)
1490                         goto fail;
1491
1492                 status = ixgbe_get_i2c_ack(hw);
1493                 if (status != 0)
1494                         goto fail;
1495
1496                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1497                 if (status != 0)
1498                         goto fail;
1499
1500                 status = ixgbe_get_i2c_ack(hw);
1501                 if (status != 0)
1502                         goto fail;
1503
1504                 ixgbe_i2c_start(hw);
1505
1506                 /* Device Address and read indication */
1507                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1508                 if (status != 0)
1509                         goto fail;
1510
1511                 status = ixgbe_get_i2c_ack(hw);
1512                 if (status != 0)
1513                         goto fail;
1514
1515                 status = ixgbe_clock_in_i2c_byte(hw, data);
1516                 if (status != 0)
1517                         goto fail;
1518
1519                 status = ixgbe_clock_out_i2c_bit(hw, nack);
1520                 if (status != 0)
1521                         goto fail;
1522
1523                 ixgbe_i2c_stop(hw);
1524                 break;
1525
1526 fail:
1527                 ixgbe_i2c_bus_clear(hw);
1528                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1529                 msleep(100);
1530                 retry++;
1531                 if (retry < max_retry)
1532                         hw_dbg(hw, "I2C byte read error - Retrying.\n");
1533                 else
1534                         hw_dbg(hw, "I2C byte read error.\n");
1535
1536         } while (retry < max_retry);
1537
1538         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1539
1540         return status;
1541 }
1542
1543 /**
1544  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1545  *  @hw: pointer to hardware structure
1546  *  @byte_offset: byte offset to write
1547  *  @data: value to write
1548  *
1549  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
1550  *  a specified device address.
1551  **/
1552 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1553                                  u8 dev_addr, u8 data)
1554 {
1555         s32 status;
1556         u32 max_retry = 1;
1557         u32 retry = 0;
1558         u16 swfw_mask = 0;
1559
1560         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1561                 swfw_mask = IXGBE_GSSR_PHY1_SM;
1562         else
1563                 swfw_mask = IXGBE_GSSR_PHY0_SM;
1564
1565         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
1566                 return IXGBE_ERR_SWFW_SYNC;
1567
1568         do {
1569                 ixgbe_i2c_start(hw);
1570
1571                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1572                 if (status != 0)
1573                         goto fail;
1574
1575                 status = ixgbe_get_i2c_ack(hw);
1576                 if (status != 0)
1577                         goto fail;
1578
1579                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1580                 if (status != 0)
1581                         goto fail;
1582
1583                 status = ixgbe_get_i2c_ack(hw);
1584                 if (status != 0)
1585                         goto fail;
1586
1587                 status = ixgbe_clock_out_i2c_byte(hw, data);
1588                 if (status != 0)
1589                         goto fail;
1590
1591                 status = ixgbe_get_i2c_ack(hw);
1592                 if (status != 0)
1593                         goto fail;
1594
1595                 ixgbe_i2c_stop(hw);
1596                 break;
1597
1598 fail:
1599                 ixgbe_i2c_bus_clear(hw);
1600                 retry++;
1601                 if (retry < max_retry)
1602                         hw_dbg(hw, "I2C byte write error - Retrying.\n");
1603                 else
1604                         hw_dbg(hw, "I2C byte write error.\n");
1605         } while (retry < max_retry);
1606
1607         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1608
1609         return status;
1610 }
1611
1612 /**
1613  *  ixgbe_i2c_start - Sets I2C start condition
1614  *  @hw: pointer to hardware structure
1615  *
1616  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
1617  **/
1618 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
1619 {
1620         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
1621
1622         /* Start condition must begin with data and clock high */
1623         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1624         ixgbe_raise_i2c_clk(hw, &i2cctl);
1625
1626         /* Setup time for start condition (4.7us) */
1627         udelay(IXGBE_I2C_T_SU_STA);
1628
1629         ixgbe_set_i2c_data(hw, &i2cctl, 0);
1630
1631         /* Hold time for start condition (4us) */
1632         udelay(IXGBE_I2C_T_HD_STA);
1633
1634         ixgbe_lower_i2c_clk(hw, &i2cctl);
1635
1636         /* Minimum low period of clock is 4.7 us */
1637         udelay(IXGBE_I2C_T_LOW);
1638
1639 }
1640
1641 /**
1642  *  ixgbe_i2c_stop - Sets I2C stop condition
1643  *  @hw: pointer to hardware structure
1644  *
1645  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
1646  **/
1647 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1648 {
1649         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
1650
1651         /* Stop condition must begin with data low and clock high */
1652         ixgbe_set_i2c_data(hw, &i2cctl, 0);
1653         ixgbe_raise_i2c_clk(hw, &i2cctl);
1654
1655         /* Setup time for stop condition (4us) */
1656         udelay(IXGBE_I2C_T_SU_STO);
1657
1658         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1659
1660         /* bus free time between stop and start (4.7us)*/
1661         udelay(IXGBE_I2C_T_BUF);
1662 }
1663
1664 /**
1665  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1666  *  @hw: pointer to hardware structure
1667  *  @data: data byte to clock in
1668  *
1669  *  Clocks in one byte data via I2C data/clock
1670  **/
1671 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1672 {
1673         s32 i;
1674         bool bit = false;
1675
1676         for (i = 7; i >= 0; i--) {
1677                 ixgbe_clock_in_i2c_bit(hw, &bit);
1678                 *data |= bit << i;
1679         }
1680
1681         return 0;
1682 }
1683
1684 /**
1685  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1686  *  @hw: pointer to hardware structure
1687  *  @data: data byte clocked out
1688  *
1689  *  Clocks out one byte data via I2C data/clock
1690  **/
1691 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1692 {
1693         s32 status;
1694         s32 i;
1695         u32 i2cctl;
1696         bool bit = false;
1697
1698         for (i = 7; i >= 0; i--) {
1699                 bit = (data >> i) & 0x1;
1700                 status = ixgbe_clock_out_i2c_bit(hw, bit);
1701
1702                 if (status != 0)
1703                         break;
1704         }
1705
1706         /* Release SDA line (set high) */
1707         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
1708         i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
1709         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
1710         IXGBE_WRITE_FLUSH(hw);
1711
1712         return status;
1713 }
1714
1715 /**
1716  *  ixgbe_get_i2c_ack - Polls for I2C ACK
1717  *  @hw: pointer to hardware structure
1718  *
1719  *  Clocks in/out one bit via I2C data/clock
1720  **/
1721 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1722 {
1723         s32 status = 0;
1724         u32 i = 0;
1725         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
1726         u32 timeout = 10;
1727         bool ack = true;
1728
1729         ixgbe_raise_i2c_clk(hw, &i2cctl);
1730
1731
1732         /* Minimum high period of clock is 4us */
1733         udelay(IXGBE_I2C_T_HIGH);
1734
1735         /* Poll for ACK.  Note that ACK in I2C spec is
1736          * transition from 1 to 0 */
1737         for (i = 0; i < timeout; i++) {
1738                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
1739                 ack = ixgbe_get_i2c_data(hw, &i2cctl);
1740
1741                 udelay(1);
1742                 if (ack == 0)
1743                         break;
1744         }
1745
1746         if (ack == 1) {
1747                 hw_dbg(hw, "I2C ack was not received.\n");
1748                 status = IXGBE_ERR_I2C;
1749         }
1750
1751         ixgbe_lower_i2c_clk(hw, &i2cctl);
1752
1753         /* Minimum low period of clock is 4.7 us */
1754         udelay(IXGBE_I2C_T_LOW);
1755
1756         return status;
1757 }
1758
1759 /**
1760  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1761  *  @hw: pointer to hardware structure
1762  *  @data: read data value
1763  *
1764  *  Clocks in one bit via I2C data/clock
1765  **/
1766 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1767 {
1768         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
1769
1770         ixgbe_raise_i2c_clk(hw, &i2cctl);
1771
1772         /* Minimum high period of clock is 4us */
1773         udelay(IXGBE_I2C_T_HIGH);
1774
1775         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
1776         *data = ixgbe_get_i2c_data(hw, &i2cctl);
1777
1778         ixgbe_lower_i2c_clk(hw, &i2cctl);
1779
1780         /* Minimum low period of clock is 4.7 us */
1781         udelay(IXGBE_I2C_T_LOW);
1782
1783         return 0;
1784 }
1785
1786 /**
1787  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1788  *  @hw: pointer to hardware structure
1789  *  @data: data value to write
1790  *
1791  *  Clocks out one bit via I2C data/clock
1792  **/
1793 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1794 {
1795         s32 status;
1796         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
1797
1798         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1799         if (status == 0) {
1800                 ixgbe_raise_i2c_clk(hw, &i2cctl);
1801
1802                 /* Minimum high period of clock is 4us */
1803                 udelay(IXGBE_I2C_T_HIGH);
1804
1805                 ixgbe_lower_i2c_clk(hw, &i2cctl);
1806
1807                 /* Minimum low period of clock is 4.7 us.
1808                  * This also takes care of the data hold time.
1809                  */
1810                 udelay(IXGBE_I2C_T_LOW);
1811         } else {
1812                 hw_dbg(hw, "I2C data was not set to %X\n", data);
1813                 return IXGBE_ERR_I2C;
1814         }
1815
1816         return 0;
1817 }
1818 /**
1819  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1820  *  @hw: pointer to hardware structure
1821  *  @i2cctl: Current value of I2CCTL register
1822  *
1823  *  Raises the I2C clock line '0'->'1'
1824  **/
1825 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1826 {
1827         u32 i = 0;
1828         u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
1829         u32 i2cctl_r = 0;
1830
1831         for (i = 0; i < timeout; i++) {
1832                 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
1833                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
1834                 IXGBE_WRITE_FLUSH(hw);
1835                 /* SCL rise time (1000ns) */
1836                 udelay(IXGBE_I2C_T_RISE);
1837
1838                 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
1839                 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
1840                         break;
1841         }
1842 }
1843
1844 /**
1845  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1846  *  @hw: pointer to hardware structure
1847  *  @i2cctl: Current value of I2CCTL register
1848  *
1849  *  Lowers the I2C clock line '1'->'0'
1850  **/
1851 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1852 {
1853
1854         *i2cctl &= ~IXGBE_I2C_CLK_OUT_BY_MAC(hw);
1855
1856         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
1857         IXGBE_WRITE_FLUSH(hw);
1858
1859         /* SCL fall time (300ns) */
1860         udelay(IXGBE_I2C_T_FALL);
1861 }
1862
1863 /**
1864  *  ixgbe_set_i2c_data - Sets the I2C data bit
1865  *  @hw: pointer to hardware structure
1866  *  @i2cctl: Current value of I2CCTL register
1867  *  @data: I2C data value (0 or 1) to set
1868  *
1869  *  Sets the I2C data bit
1870  **/
1871 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1872 {
1873         if (data)
1874                 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
1875         else
1876                 *i2cctl &= ~IXGBE_I2C_DATA_OUT_BY_MAC(hw);
1877
1878         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
1879         IXGBE_WRITE_FLUSH(hw);
1880
1881         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1882         udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1883
1884         /* Verify data was set correctly */
1885         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
1886         if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
1887                 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
1888                 return IXGBE_ERR_I2C;
1889         }
1890
1891         return 0;
1892 }
1893
1894 /**
1895  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
1896  *  @hw: pointer to hardware structure
1897  *  @i2cctl: Current value of I2CCTL register
1898  *
1899  *  Returns the I2C data bit value
1900  **/
1901 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
1902 {
1903         if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
1904                 return true;
1905         return false;
1906 }
1907
1908 /**
1909  *  ixgbe_i2c_bus_clear - Clears the I2C bus
1910  *  @hw: pointer to hardware structure
1911  *
1912  *  Clears the I2C bus by sending nine clock pulses.
1913  *  Used when data line is stuck low.
1914  **/
1915 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1916 {
1917         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
1918         u32 i;
1919
1920         ixgbe_i2c_start(hw);
1921
1922         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1923
1924         for (i = 0; i < 9; i++) {
1925                 ixgbe_raise_i2c_clk(hw, &i2cctl);
1926
1927                 /* Min high period of clock is 4us */
1928                 udelay(IXGBE_I2C_T_HIGH);
1929
1930                 ixgbe_lower_i2c_clk(hw, &i2cctl);
1931
1932                 /* Min low period of clock is 4.7us*/
1933                 udelay(IXGBE_I2C_T_LOW);
1934         }
1935
1936         ixgbe_i2c_start(hw);
1937
1938         /* Put the i2c bus back to default state */
1939         ixgbe_i2c_stop(hw);
1940 }
1941
1942 /**
1943  *  ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
1944  *  @hw: pointer to hardware structure
1945  *
1946  *  Checks if the LASI temp alarm status was triggered due to overtemp
1947  **/
1948 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
1949 {
1950         u16 phy_data = 0;
1951
1952         if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
1953                 return 0;
1954
1955         /* Check that the LASI temp alarm status was triggered */
1956         hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
1957                              MDIO_MMD_PMAPMD, &phy_data);
1958
1959         if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
1960                 return 0;
1961
1962         return IXGBE_ERR_OVERTEMP;
1963 }