drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2014 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 #include <linux/pci.h>
  30 #include <linux/delay.h>
  31 #include <linux/sched.h>
  32
  33 #include "ixgbe.h"
  34 #include "ixgbe_phy.h"
  35
  36 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
  37 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  38 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  39 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  40 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  41 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  42 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  43 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  44 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  45 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  46 static bool ixgbe_get_i2c_data(u32 *i2cctl);
  47 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
  48 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
  49 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
  50 static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw);
  51
  52 /**
  53  *  ixgbe_identify_phy_generic - Get physical layer module
  54  *  @hw: pointer to hardware structure
  55  *
  56  *  Determines the physical layer module found on the current adapter.
  57  **/
  58 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
  59 {
  60         u32 phy_addr;
  61         u16 ext_ability = 0;
  62
  63         if (hw->phy.type == ixgbe_phy_unknown) {
  64                 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
  65                         hw->phy.mdio.prtad = phy_addr;
  66                         if (mdio45_probe(&hw->phy.mdio, phy_addr) == 0) {
  67                                 ixgbe_get_phy_id(hw);
  68                                 hw->phy.type =
  69                                         ixgbe_get_phy_type_from_id(hw->phy.id);
  70
  71                                 if (hw->phy.type == ixgbe_phy_unknown) {
  72                                         hw->phy.ops.read_reg(hw,
  73                                                              MDIO_PMA_EXTABLE,
  74                                                              MDIO_MMD_PMAPMD,
  75                                                              &ext_ability);
  76                                         if (ext_ability &
  77                                             (MDIO_PMA_EXTABLE_10GBT |
  78                                              MDIO_PMA_EXTABLE_1000BT))
  79                                                 hw->phy.type =
  80                                                          ixgbe_phy_cu_unknown;
  81                                         else
  82                                                 hw->phy.type =
  83                                                          ixgbe_phy_generic;
  84                                 }
  85
  86                                 return 0;
  87                         }
  88                 }
  89                 /* clear value if nothing found */
  90                 hw->phy.mdio.prtad = 0;
  91                 return IXGBE_ERR_PHY_ADDR_INVALID;
  92         }
  93         return 0;
  94 }
  95
  96 /**
  97  * ixgbe_check_reset_blocked - check status of MNG FW veto bit
  98  * @hw: pointer to the hardware structure
  99  *
 100  * This function checks the MMNGC.MNG_VETO bit to see if there are
 101  * any constraints on link from manageability.  For MAC's that don't
 102  * have this bit just return false since the link can not be blocked
 103  * via this method.
 104  **/
 105 bool ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
 106 {
 107         u32 mmngc;
 108
 109         /* If we don't have this bit, it can't be blocking */
 110         if (hw->mac.type == ixgbe_mac_82598EB)
 111                 return false;
 112
 113         mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
 114         if (mmngc & IXGBE_MMNGC_MNG_VETO) {
 115                 hw_dbg(hw, "MNG_VETO bit detected.\n");
 116                 return true;
 117         }
 118
 119         return false;
 120 }
 121
 122 /**
 123  *  ixgbe_get_phy_id - Get the phy type
 124  *  @hw: pointer to hardware structure
 125  *
 126  **/
 127 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 128 {
 129         u32 status;
 130         u16 phy_id_high = 0;
 131         u16 phy_id_low = 0;
 132
 133         status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
 134                                       &phy_id_high);
 135
 136         if (status == 0) {
 137                 hw->phy.id = (u32)(phy_id_high << 16);
 138                 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
 139                                               &phy_id_low);
 140                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 141                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 142         }
 143         return status;
 144 }
 145
 146 /**
 147  *  ixgbe_get_phy_type_from_id - Get the phy type
 148  *  @hw: pointer to hardware structure
 149  *
 150  **/
 151 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 152 {
 153         enum ixgbe_phy_type phy_type;
 154
 155         switch (phy_id) {
 156         case TN1010_PHY_ID:
 157                 phy_type = ixgbe_phy_tn;
 158                 break;
 159         case X540_PHY_ID:
 160                 phy_type = ixgbe_phy_aq;
 161                 break;
 162         case QT2022_PHY_ID:
 163                 phy_type = ixgbe_phy_qt;
 164                 break;
 165         case ATH_PHY_ID:
 166                 phy_type = ixgbe_phy_nl;
 167                 break;
 168         default:
 169                 phy_type = ixgbe_phy_unknown;
 170                 break;
 171         }
 172
 173         return phy_type;
 174 }
 175
 176 /**
 177  *  ixgbe_reset_phy_generic - Performs a PHY reset
 178  *  @hw: pointer to hardware structure
 179  **/
 180 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 181 {
 182         u32 i;
 183         u16 ctrl = 0;
 184         s32 status = 0;
 185
 186         if (hw->phy.type == ixgbe_phy_unknown)
 187                 status = ixgbe_identify_phy_generic(hw);
 188
 189         if (status != 0 || hw->phy.type == ixgbe_phy_none)
 190                 return status;
 191
 192         /* Don't reset PHY if it's shut down due to overtemp. */
 193         if (!hw->phy.reset_if_overtemp &&
 194             (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 195                 return 0;
 196
 197         /* Blocked by MNG FW so bail */
 198         if (ixgbe_check_reset_blocked(hw))
 199                 return 0;
 200
 201         /*
 202          * Perform soft PHY reset to the PHY_XS.
 203          * This will cause a soft reset to the PHY
 204          */
 205         hw->phy.ops.write_reg(hw, MDIO_CTRL1,
 206                               MDIO_MMD_PHYXS,
 207                               MDIO_CTRL1_RESET);
 208
 209         /*
 210          * Poll for reset bit to self-clear indicating reset is complete.
 211          * Some PHYs could take up to 3 seconds to complete and need about
 212          * 1.7 usec delay after the reset is complete.
 213          */
 214         for (i = 0; i < 30; i++) {
 215                 msleep(100);
 216                 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
 217                                      MDIO_MMD_PHYXS, &ctrl);
 218                 if (!(ctrl & MDIO_CTRL1_RESET)) {
 219                         udelay(2);
 220                         break;
 221                 }
 222         }
 223
 224         if (ctrl & MDIO_CTRL1_RESET) {
 225                 hw_dbg(hw, "PHY reset polling failed to complete.\n");
 226                 return IXGBE_ERR_RESET_FAILED;
 227         }
 228
 229         return 0;
 230 }
 231
 232 /**
 233  *  ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
 234  *  the SWFW lock
 235  *  @hw: pointer to hardware structure
 236  *  @reg_addr: 32 bit address of PHY register to read
 237  *  @phy_data: Pointer to read data from PHY register
 238  **/
 239 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
 240                        u16 *phy_data)
 241 {
 242         u32 i, data, command;
 243
 244         /* Setup and write the address cycle command */
 245         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 246                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 247                    (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 248                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 249
 250         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 251
 252         /* Check every 10 usec to see if the address cycle completed.
 253          * The MDI Command bit will clear when the operation is
 254          * complete
 255          */
 256         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 257                 udelay(10);
 258
 259                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 260                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 261                                 break;
 262         }
 263
 264
 265         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 266                 hw_dbg(hw, "PHY address command did not complete.\n");
 267                 return IXGBE_ERR_PHY;
 268         }
 269
 270         /* Address cycle complete, setup and write the read
 271          * command
 272          */
 273         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 274                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 275                    (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 276                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 277
 278         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 279
 280         /* Check every 10 usec to see if the address cycle
 281          * completed. The MDI Command bit will clear when the
 282          * operation is complete
 283          */
 284         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 285                 udelay(10);
 286
 287                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 288                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 289                         break;
 290         }
 291
 292         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 293                 hw_dbg(hw, "PHY read command didn't complete\n");
 294                 return IXGBE_ERR_PHY;
 295         }
 296
 297         /* Read operation is complete.  Get the data
 298          * from MSRWD
 299          */
 300         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 301         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 302         *phy_data = (u16)(data);
 303
 304         return 0;
 305 }
 306
 307 /**
 308  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 309  *  using the SWFW lock - this function is needed in most cases
 310  *  @hw: pointer to hardware structure
 311  *  @reg_addr: 32 bit address of PHY register to read
 312  *  @phy_data: Pointer to read data from PHY register
 313  **/
 314 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 315                                u32 device_type, u16 *phy_data)
 316 {
 317         s32 status;
 318         u16 gssr;
 319
 320         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
 321                 gssr = IXGBE_GSSR_PHY1_SM;
 322         else
 323                 gssr = IXGBE_GSSR_PHY0_SM;
 324
 325         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
 326                 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
 327                                                 phy_data);
 328                 hw->mac.ops.release_swfw_sync(hw, gssr);
 329         } else {
 330                 return IXGBE_ERR_SWFW_SYNC;
 331         }
 332
 333         return status;
 334 }
 335
 336 /**
 337  *  ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
 338  *  without SWFW lock
 339  *  @hw: pointer to hardware structure
 340  *  @reg_addr: 32 bit PHY register to write
 341  *  @device_type: 5 bit device type
 342  *  @phy_data: Data to write to the PHY register
 343  **/
 344 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
 345                                 u32 device_type, u16 phy_data)
 346 {
 347         u32 i, command;
 348
 349         /* Put the data in the MDI single read and write data register*/
 350         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 351
 352         /* Setup and write the address cycle command */
 353         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 354                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 355                    (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 356                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 357
 358         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 359
 360         /*
 361          * Check every 10 usec to see if the address cycle completed.
 362          * The MDI Command bit will clear when the operation is
 363          * complete
 364          */
 365         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 366                 udelay(10);
 367
 368                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 369                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 370                         break;
 371         }
 372
 373         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 374                 hw_dbg(hw, "PHY address cmd didn't complete\n");
 375                 return IXGBE_ERR_PHY;
 376         }
 377
 378         /*
 379          * Address cycle complete, setup and write the write
 380          * command
 381          */
 382         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 383                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 384                    (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 385                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 386
 387         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 388
 389         /* Check every 10 usec to see if the address cycle
 390          * completed. The MDI Command bit will clear when the
 391          * operation is complete
 392          */
 393         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 394                 udelay(10);
 395
 396                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 397                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 398                         break;
 399         }
 400
 401         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 402                 hw_dbg(hw, "PHY write cmd didn't complete\n");
 403                 return IXGBE_ERR_PHY;
 404         }
 405
 406         return 0;
 407 }
 408
 409 /**
 410  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 411  *  using SWFW lock- this function is needed in most cases
 412  *  @hw: pointer to hardware structure
 413  *  @reg_addr: 32 bit PHY register to write
 414  *  @device_type: 5 bit device type
 415  *  @phy_data: Data to write to the PHY register
 416  **/
 417 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 418                                 u32 device_type, u16 phy_data)
 419 {
 420         s32 status;
 421         u16 gssr;
 422
 423         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
 424                 gssr = IXGBE_GSSR_PHY1_SM;
 425         else
 426                 gssr = IXGBE_GSSR_PHY0_SM;
 427
 428         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
 429                 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
 430                                                  phy_data);
 431                 hw->mac.ops.release_swfw_sync(hw, gssr);
 432         } else {
 433                 return IXGBE_ERR_SWFW_SYNC;
 434         }
 435
 436         return status;
 437 }
 438
 439 /**
 440  *  ixgbe_setup_phy_link_generic - Set and restart autoneg
 441  *  @hw: pointer to hardware structure
 442  *
 443  *  Restart autonegotiation and PHY and waits for completion.
 444  **/
 445 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 446 {
 447         s32 status = 0;
 448         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 449         bool autoneg = false;
 450         ixgbe_link_speed speed;
 451
 452         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 453
 454         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 455                 /* Set or unset auto-negotiation 10G advertisement */
 456                 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
 457                                      MDIO_MMD_AN,
 458                                      &autoneg_reg);
 459
 460                 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
 461                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 462                         autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
 463
 464                 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
 465                                       MDIO_MMD_AN,
 466                                       autoneg_reg);
 467         }
 468
 469         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 470                 /* Set or unset auto-negotiation 1G advertisement */
 471                 hw->phy.ops.read_reg(hw,
 472                                      IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 473                                      MDIO_MMD_AN,
 474                                      &autoneg_reg);
 475
 476                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
 477                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 478                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
 479
 480                 hw->phy.ops.write_reg(hw,
 481                                       IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 482                                       MDIO_MMD_AN,
 483                                       autoneg_reg);
 484         }
 485
 486         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 487                 /* Set or unset auto-negotiation 100M advertisement */
 488                 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
 489                                      MDIO_MMD_AN,
 490                                      &autoneg_reg);
 491
 492                 autoneg_reg &= ~(ADVERTISE_100FULL |
 493                                  ADVERTISE_100HALF);
 494                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 495                         autoneg_reg |= ADVERTISE_100FULL;
 496
 497                 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
 498                                       MDIO_MMD_AN,
 499                                       autoneg_reg);
 500         }
 501
 502         /* Blocked by MNG FW so don't reset PHY */
 503         if (ixgbe_check_reset_blocked(hw))
 504                 return 0;
 505
 506         /* Restart PHY autonegotiation and wait for completion */
 507         hw->phy.ops.read_reg(hw, MDIO_CTRL1,
 508                              MDIO_MMD_AN, &autoneg_reg);
 509
 510         autoneg_reg |= MDIO_AN_CTRL1_RESTART;
 511
 512         hw->phy.ops.write_reg(hw, MDIO_CTRL1,
 513                               MDIO_MMD_AN, autoneg_reg);
 514
 515         return status;
 516 }
 517
 518 /**
 519  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 520  *  @hw: pointer to hardware structure
 521  *  @speed: new link speed
 522  **/
 523 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 524                                        ixgbe_link_speed speed,
 525                                        bool autoneg_wait_to_complete)
 526 {
 527
 528         /*
 529          * Clear autoneg_advertised and set new values based on input link
 530          * speed.
 531          */
 532         hw->phy.autoneg_advertised = 0;
 533
 534         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 535                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 536
 537         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 538                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 539
 540         if (speed & IXGBE_LINK_SPEED_100_FULL)
 541                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
 542
 543         /* Setup link based on the new speed settings */
 544         hw->phy.ops.setup_link(hw);
 545
 546         return 0;
 547 }
 548
 549 /**
 550  * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
 551  * @hw: pointer to hardware structure
 552  * @speed: pointer to link speed
 553  * @autoneg: boolean auto-negotiation value
 554  *
 555  * Determines the link capabilities by reading the AUTOC register.
 556  */
 557 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 558                                                ixgbe_link_speed *speed,
 559                                                bool *autoneg)
 560 {
 561         s32 status;
 562         u16 speed_ability;
 563
 564         *speed = 0;
 565         *autoneg = true;
 566
 567         status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
 568                                       &speed_ability);
 569
 570         if (status == 0) {
 571                 if (speed_ability & MDIO_SPEED_10G)
 572                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 573                 if (speed_ability & MDIO_PMA_SPEED_1000)
 574                         *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 575                 if (speed_ability & MDIO_PMA_SPEED_100)
 576                         *speed |= IXGBE_LINK_SPEED_100_FULL;
 577         }
 578
 579         return status;
 580 }
 581
 582 /**
 583  *  ixgbe_check_phy_link_tnx - Determine link and speed status
 584  *  @hw: pointer to hardware structure
 585  *
 586  *  Reads the VS1 register to determine if link is up and the current speed for
 587  *  the PHY.
 588  **/
 589 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
 590                              bool *link_up)
 591 {
 592         s32 status;
 593         u32 time_out;
 594         u32 max_time_out = 10;
 595         u16 phy_link = 0;
 596         u16 phy_speed = 0;
 597         u16 phy_data = 0;
 598
 599         /* Initialize speed and link to default case */
 600         *link_up = false;
 601         *speed = IXGBE_LINK_SPEED_10GB_FULL;
 602
 603         /*
 604          * Check current speed and link status of the PHY register.
 605          * This is a vendor specific register and may have to
 606          * be changed for other copper PHYs.
 607          */
 608         for (time_out = 0; time_out < max_time_out; time_out++) {
 609                 udelay(10);
 610                 status = hw->phy.ops.read_reg(hw,
 611                                               MDIO_STAT1,
 612                                               MDIO_MMD_VEND1,
 613                                               &phy_data);
 614                 phy_link = phy_data &
 615                             IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
 616                 phy_speed = phy_data &
 617                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
 618                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
 619                         *link_up = true;
 620                         if (phy_speed ==
 621                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
 622                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 623                         break;
 624                 }
 625         }
 626
 627         return status;
 628 }
 629
 630 /**
 631  *      ixgbe_setup_phy_link_tnx - Set and restart autoneg
 632  *      @hw: pointer to hardware structure
 633  *
 634  *      Restart autonegotiation and PHY and waits for completion.
 635  **/
 636 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
 637 {
 638         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 639         bool autoneg = false;
 640         ixgbe_link_speed speed;
 641
 642         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 643
 644         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 645                 /* Set or unset auto-negotiation 10G advertisement */
 646                 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
 647                                      MDIO_MMD_AN,
 648                                      &autoneg_reg);
 649
 650                 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
 651                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 652                         autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
 653
 654                 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
 655                                       MDIO_MMD_AN,
 656                                       autoneg_reg);
 657         }
 658
 659         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 660                 /* Set or unset auto-negotiation 1G advertisement */
 661                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
 662                                      MDIO_MMD_AN,
 663                                      &autoneg_reg);
 664
 665                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
 666                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 667                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
 668
 669                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
 670                                       MDIO_MMD_AN,
 671                                       autoneg_reg);
 672         }
 673
 674         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 675                 /* Set or unset auto-negotiation 100M advertisement */
 676                 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
 677                                      MDIO_MMD_AN,
 678                                      &autoneg_reg);
 679
 680                 autoneg_reg &= ~(ADVERTISE_100FULL |
 681                                  ADVERTISE_100HALF);
 682                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 683                         autoneg_reg |= ADVERTISE_100FULL;
 684
 685                 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
 686                                       MDIO_MMD_AN,
 687                                       autoneg_reg);
 688         }
 689
 690         /* Blocked by MNG FW so don't reset PHY */
 691         if (ixgbe_check_reset_blocked(hw))
 692                 return 0;
 693
 694         /* Restart PHY autonegotiation and wait for completion */
 695         hw->phy.ops.read_reg(hw, MDIO_CTRL1,
 696                              MDIO_MMD_AN, &autoneg_reg);
 697
 698         autoneg_reg |= MDIO_AN_CTRL1_RESTART;
 699
 700         hw->phy.ops.write_reg(hw, MDIO_CTRL1,
 701                               MDIO_MMD_AN, autoneg_reg);
 702         return 0;
 703 }
 704
 705 /**
 706  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
 707  *  @hw: pointer to hardware structure
 708  *  @firmware_version: pointer to the PHY Firmware Version
 709  **/
 710 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
 711                                        u16 *firmware_version)
 712 {
 713         s32 status;
 714
 715         status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
 716                                       MDIO_MMD_VEND1,
 717                                       firmware_version);
 718
 719         return status;
 720 }
 721
 722 /**
 723  *  ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
 724  *  @hw: pointer to hardware structure
 725  *  @firmware_version: pointer to the PHY Firmware Version
 726  **/
 727 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
 728                                            u16 *firmware_version)
 729 {
 730         s32 status;
 731
 732         status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
 733                                       MDIO_MMD_VEND1,
 734                                       firmware_version);
 735
 736         return status;
 737 }
 738
 739 /**
 740  *  ixgbe_reset_phy_nl - Performs a PHY reset
 741  *  @hw: pointer to hardware structure
 742  **/
 743 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
 744 {
 745         u16 phy_offset, control, eword, edata, block_crc;
 746         bool end_data = false;
 747         u16 list_offset, data_offset;
 748         u16 phy_data = 0;
 749         s32 ret_val;
 750         u32 i;
 751
 752         /* Blocked by MNG FW so bail */
 753         if (ixgbe_check_reset_blocked(hw))
 754                 return 0;
 755
 756         hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
 757
 758         /* reset the PHY and poll for completion */
 759         hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
 760                               (phy_data | MDIO_CTRL1_RESET));
 761
 762         for (i = 0; i < 100; i++) {
 763                 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
 764                                      &phy_data);
 765                 if ((phy_data & MDIO_CTRL1_RESET) == 0)
 766                         break;
 767                 usleep_range(10000, 20000);
 768         }
 769
 770         if ((phy_data & MDIO_CTRL1_RESET) != 0) {
 771                 hw_dbg(hw, "PHY reset did not complete.\n");
 772                 return IXGBE_ERR_PHY;
 773         }
 774
 775         /* Get init offsets */
 776         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
 777                                                       &data_offset);
 778         if (ret_val)
 779                 return ret_val;
 780
 781         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
 782         data_offset++;
 783         while (!end_data) {
 784                 /*
 785                  * Read control word from PHY init contents offset
 786                  */
 787                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
 788                 if (ret_val)
 789                         goto err_eeprom;
 790                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
 791                            IXGBE_CONTROL_SHIFT_NL;
 792                 edata = eword & IXGBE_DATA_MASK_NL;
 793                 switch (control) {
 794                 case IXGBE_DELAY_NL:
 795                         data_offset++;
 796                         hw_dbg(hw, "DELAY: %d MS\n", edata);
 797                         usleep_range(edata * 1000, edata * 2000);
 798                         break;
 799                 case IXGBE_DATA_NL:
 800                         hw_dbg(hw, "DATA:\n");
 801                         data_offset++;
 802                         ret_val = hw->eeprom.ops.read(hw, data_offset++,
 803                                                       &phy_offset);
 804                         if (ret_val)
 805                                 goto err_eeprom;
 806                         for (i = 0; i < edata; i++) {
 807                                 ret_val = hw->eeprom.ops.read(hw, data_offset,
 808                                                               &eword);
 809                                 if (ret_val)
 810                                         goto err_eeprom;
 811                                 hw->phy.ops.write_reg(hw, phy_offset,
 812                                                       MDIO_MMD_PMAPMD, eword);
 813                                 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
 814                                        phy_offset);
 815                                 data_offset++;
 816                                 phy_offset++;
 817                         }
 818                         break;
 819                 case IXGBE_CONTROL_NL:
 820                         data_offset++;
 821                         hw_dbg(hw, "CONTROL:\n");
 822                         if (edata == IXGBE_CONTROL_EOL_NL) {
 823                                 hw_dbg(hw, "EOL\n");
 824                                 end_data = true;
 825                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
 826                                 hw_dbg(hw, "SOL\n");
 827                         } else {
 828                                 hw_dbg(hw, "Bad control value\n");
 829                                 return IXGBE_ERR_PHY;
 830                         }
 831                         break;
 832                 default:
 833                         hw_dbg(hw, "Bad control type\n");
 834                         return IXGBE_ERR_PHY;
 835                 }
 836         }
 837
 838         return ret_val;
 839
 840 err_eeprom:
 841         hw_err(hw, "eeprom read at offset %d failed\n", data_offset);
 842         return IXGBE_ERR_PHY;
 843 }
 844
 845 /**
 846  *  ixgbe_identify_module_generic - Identifies module type
 847  *  @hw: pointer to hardware structure
 848  *
 849  *  Determines HW type and calls appropriate function.
 850  **/
 851 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
 852 {
 853         switch (hw->mac.ops.get_media_type(hw)) {
 854         case ixgbe_media_type_fiber:
 855                 return ixgbe_identify_sfp_module_generic(hw);
 856         case ixgbe_media_type_fiber_qsfp:
 857                 return ixgbe_identify_qsfp_module_generic(hw);
 858         default:
 859                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
 860                 return IXGBE_ERR_SFP_NOT_PRESENT;
 861         }
 862
 863         return IXGBE_ERR_SFP_NOT_PRESENT;
 864 }
 865
 866 /**
 867  *  ixgbe_identify_sfp_module_generic - Identifies SFP modules
 868  *  @hw: pointer to hardware structure
 869  *
 870  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
 871  **/
 872 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
 873 {
 874         struct ixgbe_adapter *adapter = hw->back;
 875         s32 status;
 876         u32 vendor_oui = 0;
 877         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
 878         u8 identifier = 0;
 879         u8 comp_codes_1g = 0;
 880         u8 comp_codes_10g = 0;
 881         u8 oui_bytes[3] = {0, 0, 0};
 882         u8 cable_tech = 0;
 883         u8 cable_spec = 0;
 884         u16 enforce_sfp = 0;
 885
 886         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
 887                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
 888                 return IXGBE_ERR_SFP_NOT_PRESENT;
 889         }
 890
 891         status = hw->phy.ops.read_i2c_eeprom(hw,
 892                                              IXGBE_SFF_IDENTIFIER,
 893                                              &identifier);
 894
 895         if (status)
 896                 goto err_read_i2c_eeprom;
 897
 898         /* LAN ID is needed for sfp_type determination */
 899         hw->mac.ops.set_lan_id(hw);
 900
 901         if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
 902                 hw->phy.type = ixgbe_phy_sfp_unsupported;
 903                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
 904         }
 905         status = hw->phy.ops.read_i2c_eeprom(hw,
 906                                              IXGBE_SFF_1GBE_COMP_CODES,
 907                                              &comp_codes_1g);
 908
 909         if (status)
 910                 goto err_read_i2c_eeprom;
 911
 912         status = hw->phy.ops.read_i2c_eeprom(hw,
 913                                              IXGBE_SFF_10GBE_COMP_CODES,
 914                                              &comp_codes_10g);
 915
 916         if (status)
 917                 goto err_read_i2c_eeprom;
 918         status = hw->phy.ops.read_i2c_eeprom(hw,
 919                                              IXGBE_SFF_CABLE_TECHNOLOGY,
 920                                              &cable_tech);
 921
 922         if (status)
 923                 goto err_read_i2c_eeprom;
 924
 925          /* ID Module
 926           * =========
 927           * 0   SFP_DA_CU
 928           * 1   SFP_SR
 929           * 2   SFP_LR
 930           * 3   SFP_DA_CORE0 - 82599-specific
 931           * 4   SFP_DA_CORE1 - 82599-specific
 932           * 5   SFP_SR/LR_CORE0 - 82599-specific
 933           * 6   SFP_SR/LR_CORE1 - 82599-specific
 934           * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
 935           * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
 936           * 9   SFP_1g_cu_CORE0 - 82599-specific
 937           * 10  SFP_1g_cu_CORE1 - 82599-specific
 938           * 11  SFP_1g_sx_CORE0 - 82599-specific
 939           * 12  SFP_1g_sx_CORE1 - 82599-specific
 940           */
 941         if (hw->mac.type == ixgbe_mac_82598EB) {
 942                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
 943                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
 944                 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
 945                         hw->phy.sfp_type = ixgbe_sfp_type_sr;
 946                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
 947                         hw->phy.sfp_type = ixgbe_sfp_type_lr;
 948                 else
 949                         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
 950         } else if (hw->mac.type == ixgbe_mac_82599EB) {
 951                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
 952                         if (hw->bus.lan_id == 0)
 953                                 hw->phy.sfp_type =
 954                                              ixgbe_sfp_type_da_cu_core0;
 955                         else
 956                                 hw->phy.sfp_type =
 957                                              ixgbe_sfp_type_da_cu_core1;
 958                 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
 959                         hw->phy.ops.read_i2c_eeprom(
 960                                         hw, IXGBE_SFF_CABLE_SPEC_COMP,
 961                                         &cable_spec);
 962                         if (cable_spec &
 963                             IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
 964                                 if (hw->bus.lan_id == 0)
 965                                         hw->phy.sfp_type =
 966                                         ixgbe_sfp_type_da_act_lmt_core0;
 967                                 else
 968                                         hw->phy.sfp_type =
 969                                         ixgbe_sfp_type_da_act_lmt_core1;
 970                         } else {
 971                                 hw->phy.sfp_type =
 972                                                 ixgbe_sfp_type_unknown;
 973                         }
 974                 } else if (comp_codes_10g &
 975                            (IXGBE_SFF_10GBASESR_CAPABLE |
 976                             IXGBE_SFF_10GBASELR_CAPABLE)) {
 977                         if (hw->bus.lan_id == 0)
 978                                 hw->phy.sfp_type =
 979                                               ixgbe_sfp_type_srlr_core0;
 980                         else
 981                                 hw->phy.sfp_type =
 982                                               ixgbe_sfp_type_srlr_core1;
 983                 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
 984                         if (hw->bus.lan_id == 0)
 985                                 hw->phy.sfp_type =
 986                                         ixgbe_sfp_type_1g_cu_core0;
 987                         else
 988                                 hw->phy.sfp_type =
 989                                         ixgbe_sfp_type_1g_cu_core1;
 990                 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
 991                         if (hw->bus.lan_id == 0)
 992                                 hw->phy.sfp_type =
 993                                         ixgbe_sfp_type_1g_sx_core0;
 994                         else
 995                                 hw->phy.sfp_type =
 996                                         ixgbe_sfp_type_1g_sx_core1;
 997                 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
 998                         if (hw->bus.lan_id == 0)
 999                                 hw->phy.sfp_type =
1000                                         ixgbe_sfp_type_1g_lx_core0;
1001                         else
1002                                 hw->phy.sfp_type =
1003                                         ixgbe_sfp_type_1g_lx_core1;
1004                 } else {
1005                         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1006                 }
1007         }
1008
1009         if (hw->phy.sfp_type != stored_sfp_type)
1010                 hw->phy.sfp_setup_needed = true;
1011
1012         /* Determine if the SFP+ PHY is dual speed or not. */
1013         hw->phy.multispeed_fiber = false;
1014         if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1015              (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1016             ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1017              (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1018                 hw->phy.multispeed_fiber = true;
1019
1020         /* Determine PHY vendor */
1021         if (hw->phy.type != ixgbe_phy_nl) {
1022                 hw->phy.id = identifier;
1023                 status = hw->phy.ops.read_i2c_eeprom(hw,
1024                                             IXGBE_SFF_VENDOR_OUI_BYTE0,
1025                                             &oui_bytes[0]);
1026
1027                 if (status != 0)
1028                         goto err_read_i2c_eeprom;
1029
1030                 status = hw->phy.ops.read_i2c_eeprom(hw,
1031                                             IXGBE_SFF_VENDOR_OUI_BYTE1,
1032                                             &oui_bytes[1]);
1033
1034                 if (status != 0)
1035                         goto err_read_i2c_eeprom;
1036
1037                 status = hw->phy.ops.read_i2c_eeprom(hw,
1038                                             IXGBE_SFF_VENDOR_OUI_BYTE2,
1039                                             &oui_bytes[2]);
1040
1041                 if (status != 0)
1042                         goto err_read_i2c_eeprom;
1043
1044                 vendor_oui =
1045                   ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1046                    (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1047                    (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1048
1049                 switch (vendor_oui) {
1050                 case IXGBE_SFF_VENDOR_OUI_TYCO:
1051                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1052                                 hw->phy.type =
1053                                             ixgbe_phy_sfp_passive_tyco;
1054                         break;
1055                 case IXGBE_SFF_VENDOR_OUI_FTL:
1056                         if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1057                                 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1058                         else
1059                                 hw->phy.type = ixgbe_phy_sfp_ftl;
1060                         break;
1061                 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1062                         hw->phy.type = ixgbe_phy_sfp_avago;
1063                         break;
1064                 case IXGBE_SFF_VENDOR_OUI_INTEL:
1065                         hw->phy.type = ixgbe_phy_sfp_intel;
1066                         break;
1067                 default:
1068                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1069                                 hw->phy.type =
1070                                          ixgbe_phy_sfp_passive_unknown;
1071                         else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1072                                 hw->phy.type =
1073                                         ixgbe_phy_sfp_active_unknown;
1074                         else
1075                                 hw->phy.type = ixgbe_phy_sfp_unknown;
1076                         break;
1077                 }
1078         }
1079
1080         /* Allow any DA cable vendor */
1081         if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1082             IXGBE_SFF_DA_ACTIVE_CABLE))
1083                 return 0;
1084
1085         /* Verify supported 1G SFP modules */
1086         if (comp_codes_10g == 0 &&
1087             !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1088               hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1089               hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1090               hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1091               hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1092               hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1093                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1094                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1095         }
1096
1097         /* Anything else 82598-based is supported */
1098         if (hw->mac.type == ixgbe_mac_82598EB)
1099                 return 0;
1100
1101         hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1102         if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1103             !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1104               hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1105               hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1106               hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1107               hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1108               hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1109                 /* Make sure we're a supported PHY type */
1110                 if (hw->phy.type == ixgbe_phy_sfp_intel)
1111                         return 0;
1112                 if (hw->allow_unsupported_sfp) {
1113                         e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics.  Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter.  Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1114                         return 0;
1115                 }
1116                 hw_dbg(hw, "SFP+ module not supported\n");
1117                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1118                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1119         }
1120         return 0;
1121
1122 err_read_i2c_eeprom:
1123         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1124         if (hw->phy.type != ixgbe_phy_nl) {
1125                 hw->phy.id = 0;
1126                 hw->phy.type = ixgbe_phy_unknown;
1127         }
1128         return IXGBE_ERR_SFP_NOT_PRESENT;
1129 }
1130
1131 /**
1132  * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1133  * @hw: pointer to hardware structure
1134  *
1135  * Searches for and identifies the QSFP module and assigns appropriate PHY type
1136  **/
1137 static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1138 {
1139         struct ixgbe_adapter *adapter = hw->back;
1140         s32 status;
1141         u32 vendor_oui = 0;
1142         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1143         u8 identifier = 0;
1144         u8 comp_codes_1g = 0;
1145         u8 comp_codes_10g = 0;
1146         u8 oui_bytes[3] = {0, 0, 0};
1147         u16 enforce_sfp = 0;
1148         u8 connector = 0;
1149         u8 cable_length = 0;
1150         u8 device_tech = 0;
1151         bool active_cable = false;
1152
1153         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1154                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1155                 return IXGBE_ERR_SFP_NOT_PRESENT;
1156         }
1157
1158         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1159                                              &identifier);
1160
1161         if (status != 0)
1162                 goto err_read_i2c_eeprom;
1163
1164         if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1165                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1166                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1167         }
1168
1169         hw->phy.id = identifier;
1170
1171         /* LAN ID is needed for sfp_type determination */
1172         hw->mac.ops.set_lan_id(hw);
1173
1174         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1175                                              &comp_codes_10g);
1176
1177         if (status != 0)
1178                 goto err_read_i2c_eeprom;
1179
1180         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1181                                              &comp_codes_1g);
1182
1183         if (status != 0)
1184                 goto err_read_i2c_eeprom;
1185
1186         if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1187                 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1188                 if (hw->bus.lan_id == 0)
1189                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1190                 else
1191                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1192         } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1193                                      IXGBE_SFF_10GBASELR_CAPABLE)) {
1194                 if (hw->bus.lan_id == 0)
1195                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1196                 else
1197                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1198         } else {
1199                 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1200                         active_cable = true;
1201
1202                 if (!active_cable) {
1203                         /* check for active DA cables that pre-date
1204                          * SFF-8436 v3.6
1205                          */
1206                         hw->phy.ops.read_i2c_eeprom(hw,
1207                                         IXGBE_SFF_QSFP_CONNECTOR,
1208                                         &connector);
1209
1210                         hw->phy.ops.read_i2c_eeprom(hw,
1211                                         IXGBE_SFF_QSFP_CABLE_LENGTH,
1212                                         &cable_length);
1213
1214                         hw->phy.ops.read_i2c_eeprom(hw,
1215                                         IXGBE_SFF_QSFP_DEVICE_TECH,
1216                                         &device_tech);
1217
1218                         if ((connector ==
1219                                      IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1220                             (cable_length > 0) &&
1221                             ((device_tech >> 4) ==
1222                                      IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1223                                 active_cable = true;
1224                 }
1225
1226                 if (active_cable) {
1227                         hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1228                         if (hw->bus.lan_id == 0)
1229                                 hw->phy.sfp_type =
1230                                                 ixgbe_sfp_type_da_act_lmt_core0;
1231                         else
1232                                 hw->phy.sfp_type =
1233                                                 ixgbe_sfp_type_da_act_lmt_core1;
1234                 } else {
1235                         /* unsupported module type */
1236                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1237                         return IXGBE_ERR_SFP_NOT_SUPPORTED;
1238                 }
1239         }
1240
1241         if (hw->phy.sfp_type != stored_sfp_type)
1242                 hw->phy.sfp_setup_needed = true;
1243
1244         /* Determine if the QSFP+ PHY is dual speed or not. */
1245         hw->phy.multispeed_fiber = false;
1246         if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1247              (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1248             ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1249              (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1250                 hw->phy.multispeed_fiber = true;
1251
1252         /* Determine PHY vendor for optical modules */
1253         if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1254                               IXGBE_SFF_10GBASELR_CAPABLE)) {
1255                 status = hw->phy.ops.read_i2c_eeprom(hw,
1256                                         IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1257                                         &oui_bytes[0]);
1258
1259                 if (status != 0)
1260                         goto err_read_i2c_eeprom;
1261
1262                 status = hw->phy.ops.read_i2c_eeprom(hw,
1263                                         IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1264                                         &oui_bytes[1]);
1265
1266                 if (status != 0)
1267                         goto err_read_i2c_eeprom;
1268
1269                 status = hw->phy.ops.read_i2c_eeprom(hw,
1270                                         IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1271                                         &oui_bytes[2]);
1272
1273                 if (status != 0)
1274                         goto err_read_i2c_eeprom;
1275
1276                 vendor_oui =
1277                         ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1278                          (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1279                          (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1280
1281                 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1282                         hw->phy.type = ixgbe_phy_qsfp_intel;
1283                 else
1284                         hw->phy.type = ixgbe_phy_qsfp_unknown;
1285
1286                 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1287                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1288                         /* Make sure we're a supported PHY type */
1289                         if (hw->phy.type == ixgbe_phy_qsfp_intel)
1290                                 return 0;
1291                         if (hw->allow_unsupported_sfp) {
1292                                 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1293                                 return 0;
1294                         }
1295                         hw_dbg(hw, "QSFP module not supported\n");
1296                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1297                         return IXGBE_ERR_SFP_NOT_SUPPORTED;
1298                 }
1299                 return 0;
1300         }
1301         return 0;
1302
1303 err_read_i2c_eeprom:
1304         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1305         hw->phy.id = 0;
1306         hw->phy.type = ixgbe_phy_unknown;
1307
1308         return IXGBE_ERR_SFP_NOT_PRESENT;
1309 }
1310
1311 /**
1312  *  ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1313  *  @hw: pointer to hardware structure
1314  *  @list_offset: offset to the SFP ID list
1315  *  @data_offset: offset to the SFP data block
1316  *
1317  *  Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1318  *  so it returns the offsets to the phy init sequence block.
1319  **/
1320 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1321                                         u16 *list_offset,
1322                                         u16 *data_offset)
1323 {
1324         u16 sfp_id;
1325         u16 sfp_type = hw->phy.sfp_type;
1326
1327         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1328                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1329
1330         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1331                 return IXGBE_ERR_SFP_NOT_PRESENT;
1332
1333         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1334             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1335                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1336
1337         /*
1338          * Limiting active cables and 1G Phys must be initialized as
1339          * SR modules
1340          */
1341         if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1342             sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1343             sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1344             sfp_type == ixgbe_sfp_type_1g_sx_core0)
1345                 sfp_type = ixgbe_sfp_type_srlr_core0;
1346         else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1347                  sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1348                  sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1349                  sfp_type == ixgbe_sfp_type_1g_sx_core1)
1350                 sfp_type = ixgbe_sfp_type_srlr_core1;
1351
1352         /* Read offset to PHY init contents */
1353         if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1354                 hw_err(hw, "eeprom read at %d failed\n",
1355                        IXGBE_PHY_INIT_OFFSET_NL);
1356                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1357         }
1358
1359         if ((!*list_offset) || (*list_offset == 0xFFFF))
1360                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1361
1362         /* Shift offset to first ID word */
1363         (*list_offset)++;
1364
1365         /*
1366          * Find the matching SFP ID in the EEPROM
1367          * and program the init sequence
1368          */
1369         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1370                 goto err_phy;
1371
1372         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1373                 if (sfp_id == sfp_type) {
1374                         (*list_offset)++;
1375                         if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1376                                 goto err_phy;
1377                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1378                                 hw_dbg(hw, "SFP+ module not supported\n");
1379                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1380                         } else {
1381                                 break;
1382                         }
1383                 } else {
1384                         (*list_offset) += 2;
1385                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1386                                 goto err_phy;
1387                 }
1388         }
1389
1390         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1391                 hw_dbg(hw, "No matching SFP+ module found\n");
1392                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1393         }
1394
1395         return 0;
1396
1397 err_phy:
1398         hw_err(hw, "eeprom read at offset %d failed\n", *list_offset);
1399         return IXGBE_ERR_PHY;
1400 }
1401
1402 /**
1403  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1404  *  @hw: pointer to hardware structure
1405  *  @byte_offset: EEPROM byte offset to read
1406  *  @eeprom_data: value read
1407  *
1408  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1409  **/
1410 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1411                                   u8 *eeprom_data)
1412 {
1413         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1414                                          IXGBE_I2C_EEPROM_DEV_ADDR,
1415                                          eeprom_data);
1416 }
1417
1418 /**
1419  *  ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1420  *  @hw: pointer to hardware structure
1421  *  @byte_offset: byte offset at address 0xA2
1422  *  @eeprom_data: value read
1423  *
1424  *  Performs byte read operation to SFP module's SFF-8472 data over I2C
1425  **/
1426 s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1427                                    u8 *sff8472_data)
1428 {
1429         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1430                                          IXGBE_I2C_EEPROM_DEV_ADDR2,
1431                                          sff8472_data);
1432 }
1433
1434 /**
1435  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1436  *  @hw: pointer to hardware structure
1437  *  @byte_offset: EEPROM byte offset to write
1438  *  @eeprom_data: value to write
1439  *
1440  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
1441  **/
1442 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1443                                    u8 eeprom_data)
1444 {
1445         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1446                                           IXGBE_I2C_EEPROM_DEV_ADDR,
1447                                           eeprom_data);
1448 }
1449
1450 /**
1451  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1452  *  @hw: pointer to hardware structure
1453  *  @byte_offset: byte offset to read
1454  *  @data: value read
1455  *
1456  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
1457  *  a specified device address.
1458  **/
1459 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1460                                 u8 dev_addr, u8 *data)
1461 {
1462         s32 status;
1463         u32 max_retry = 10;
1464         u32 retry = 0;
1465         u16 swfw_mask = 0;
1466         bool nack = true;
1467         *data = 0;
1468
1469         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1470                 swfw_mask = IXGBE_GSSR_PHY1_SM;
1471         else
1472                 swfw_mask = IXGBE_GSSR_PHY0_SM;
1473
1474         do {
1475                 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
1476                         return IXGBE_ERR_SWFW_SYNC;
1477
1478                 ixgbe_i2c_start(hw);
1479
1480                 /* Device Address and write indication */
1481                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1482                 if (status != 0)
1483                         goto fail;
1484
1485                 status = ixgbe_get_i2c_ack(hw);
1486                 if (status != 0)
1487                         goto fail;
1488
1489                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1490                 if (status != 0)
1491                         goto fail;
1492
1493                 status = ixgbe_get_i2c_ack(hw);
1494                 if (status != 0)
1495                         goto fail;
1496
1497                 ixgbe_i2c_start(hw);
1498
1499                 /* Device Address and read indication */
1500                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1501                 if (status != 0)
1502                         goto fail;
1503
1504                 status = ixgbe_get_i2c_ack(hw);
1505                 if (status != 0)
1506                         goto fail;
1507
1508                 status = ixgbe_clock_in_i2c_byte(hw, data);
1509                 if (status != 0)
1510                         goto fail;
1511
1512                 status = ixgbe_clock_out_i2c_bit(hw, nack);
1513                 if (status != 0)
1514                         goto fail;
1515
1516                 ixgbe_i2c_stop(hw);
1517                 break;
1518
1519 fail:
1520                 ixgbe_i2c_bus_clear(hw);
1521                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1522                 msleep(100);
1523                 retry++;
1524                 if (retry < max_retry)
1525                         hw_dbg(hw, "I2C byte read error - Retrying.\n");
1526                 else
1527                         hw_dbg(hw, "I2C byte read error.\n");
1528
1529         } while (retry < max_retry);
1530
1531         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1532
1533         return status;
1534 }
1535
1536 /**
1537  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1538  *  @hw: pointer to hardware structure
1539  *  @byte_offset: byte offset to write
1540  *  @data: value to write
1541  *
1542  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
1543  *  a specified device address.
1544  **/
1545 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1546                                  u8 dev_addr, u8 data)
1547 {
1548         s32 status;
1549         u32 max_retry = 1;
1550         u32 retry = 0;
1551         u16 swfw_mask = 0;
1552
1553         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1554                 swfw_mask = IXGBE_GSSR_PHY1_SM;
1555         else
1556                 swfw_mask = IXGBE_GSSR_PHY0_SM;
1557
1558         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
1559                 return IXGBE_ERR_SWFW_SYNC;
1560
1561         do {
1562                 ixgbe_i2c_start(hw);
1563
1564                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1565                 if (status != 0)
1566                         goto fail;
1567
1568                 status = ixgbe_get_i2c_ack(hw);
1569                 if (status != 0)
1570                         goto fail;
1571
1572                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1573                 if (status != 0)
1574                         goto fail;
1575
1576                 status = ixgbe_get_i2c_ack(hw);
1577                 if (status != 0)
1578                         goto fail;
1579
1580                 status = ixgbe_clock_out_i2c_byte(hw, data);
1581                 if (status != 0)
1582                         goto fail;
1583
1584                 status = ixgbe_get_i2c_ack(hw);
1585                 if (status != 0)
1586                         goto fail;
1587
1588                 ixgbe_i2c_stop(hw);
1589                 break;
1590
1591 fail:
1592                 ixgbe_i2c_bus_clear(hw);
1593                 retry++;
1594                 if (retry < max_retry)
1595                         hw_dbg(hw, "I2C byte write error - Retrying.\n");
1596                 else
1597                         hw_dbg(hw, "I2C byte write error.\n");
1598         } while (retry < max_retry);
1599
1600         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1601
1602         return status;
1603 }
1604
1605 /**
1606  *  ixgbe_i2c_start - Sets I2C start condition
1607  *  @hw: pointer to hardware structure
1608  *
1609  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
1610  **/
1611 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
1612 {
1613         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1614
1615         /* Start condition must begin with data and clock high */
1616         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1617         ixgbe_raise_i2c_clk(hw, &i2cctl);
1618
1619         /* Setup time for start condition (4.7us) */
1620         udelay(IXGBE_I2C_T_SU_STA);
1621
1622         ixgbe_set_i2c_data(hw, &i2cctl, 0);
1623
1624         /* Hold time for start condition (4us) */
1625         udelay(IXGBE_I2C_T_HD_STA);
1626
1627         ixgbe_lower_i2c_clk(hw, &i2cctl);
1628
1629         /* Minimum low period of clock is 4.7 us */
1630         udelay(IXGBE_I2C_T_LOW);
1631
1632 }
1633
1634 /**
1635  *  ixgbe_i2c_stop - Sets I2C stop condition
1636  *  @hw: pointer to hardware structure
1637  *
1638  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
1639  **/
1640 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1641 {
1642         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1643
1644         /* Stop condition must begin with data low and clock high */
1645         ixgbe_set_i2c_data(hw, &i2cctl, 0);
1646         ixgbe_raise_i2c_clk(hw, &i2cctl);
1647
1648         /* Setup time for stop condition (4us) */
1649         udelay(IXGBE_I2C_T_SU_STO);
1650
1651         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1652
1653         /* bus free time between stop and start (4.7us)*/
1654         udelay(IXGBE_I2C_T_BUF);
1655 }
1656
1657 /**
1658  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1659  *  @hw: pointer to hardware structure
1660  *  @data: data byte to clock in
1661  *
1662  *  Clocks in one byte data via I2C data/clock
1663  **/
1664 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1665 {
1666         s32 i;
1667         bool bit = false;
1668
1669         for (i = 7; i >= 0; i--) {
1670                 ixgbe_clock_in_i2c_bit(hw, &bit);
1671                 *data |= bit << i;
1672         }
1673
1674         return 0;
1675 }
1676
1677 /**
1678  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1679  *  @hw: pointer to hardware structure
1680  *  @data: data byte clocked out
1681  *
1682  *  Clocks out one byte data via I2C data/clock
1683  **/
1684 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1685 {
1686         s32 status;
1687         s32 i;
1688         u32 i2cctl;
1689         bool bit = false;
1690
1691         for (i = 7; i >= 0; i--) {
1692                 bit = (data >> i) & 0x1;
1693                 status = ixgbe_clock_out_i2c_bit(hw, bit);
1694
1695                 if (status != 0)
1696                         break;
1697         }
1698
1699         /* Release SDA line (set high) */
1700         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1701         i2cctl |= IXGBE_I2C_DATA_OUT;
1702         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1703         IXGBE_WRITE_FLUSH(hw);
1704
1705         return status;
1706 }
1707
1708 /**
1709  *  ixgbe_get_i2c_ack - Polls for I2C ACK
1710  *  @hw: pointer to hardware structure
1711  *
1712  *  Clocks in/out one bit via I2C data/clock
1713  **/
1714 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1715 {
1716         s32 status = 0;
1717         u32 i = 0;
1718         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1719         u32 timeout = 10;
1720         bool ack = true;
1721
1722         ixgbe_raise_i2c_clk(hw, &i2cctl);
1723
1724
1725         /* Minimum high period of clock is 4us */
1726         udelay(IXGBE_I2C_T_HIGH);
1727
1728         /* Poll for ACK.  Note that ACK in I2C spec is
1729          * transition from 1 to 0 */
1730         for (i = 0; i < timeout; i++) {
1731                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1732                 ack = ixgbe_get_i2c_data(&i2cctl);
1733
1734                 udelay(1);
1735                 if (ack == 0)
1736                         break;
1737         }
1738
1739         if (ack == 1) {
1740                 hw_dbg(hw, "I2C ack was not received.\n");
1741                 status = IXGBE_ERR_I2C;
1742         }
1743
1744         ixgbe_lower_i2c_clk(hw, &i2cctl);
1745
1746         /* Minimum low period of clock is 4.7 us */
1747         udelay(IXGBE_I2C_T_LOW);
1748
1749         return status;
1750 }
1751
1752 /**
1753  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1754  *  @hw: pointer to hardware structure
1755  *  @data: read data value
1756  *
1757  *  Clocks in one bit via I2C data/clock
1758  **/
1759 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1760 {
1761         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1762
1763         ixgbe_raise_i2c_clk(hw, &i2cctl);
1764
1765         /* Minimum high period of clock is 4us */
1766         udelay(IXGBE_I2C_T_HIGH);
1767
1768         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1769         *data = ixgbe_get_i2c_data(&i2cctl);
1770
1771         ixgbe_lower_i2c_clk(hw, &i2cctl);
1772
1773         /* Minimum low period of clock is 4.7 us */
1774         udelay(IXGBE_I2C_T_LOW);
1775
1776         return 0;
1777 }
1778
1779 /**
1780  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1781  *  @hw: pointer to hardware structure
1782  *  @data: data value to write
1783  *
1784  *  Clocks out one bit via I2C data/clock
1785  **/
1786 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1787 {
1788         s32 status;
1789         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1790
1791         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1792         if (status == 0) {
1793                 ixgbe_raise_i2c_clk(hw, &i2cctl);
1794
1795                 /* Minimum high period of clock is 4us */
1796                 udelay(IXGBE_I2C_T_HIGH);
1797
1798                 ixgbe_lower_i2c_clk(hw, &i2cctl);
1799
1800                 /* Minimum low period of clock is 4.7 us.
1801                  * This also takes care of the data hold time.
1802                  */
1803                 udelay(IXGBE_I2C_T_LOW);
1804         } else {
1805                 hw_dbg(hw, "I2C data was not set to %X\n", data);
1806                 return IXGBE_ERR_I2C;
1807         }
1808
1809         return 0;
1810 }
1811 /**
1812  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1813  *  @hw: pointer to hardware structure
1814  *  @i2cctl: Current value of I2CCTL register
1815  *
1816  *  Raises the I2C clock line '0'->'1'
1817  **/
1818 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1819 {
1820         u32 i = 0;
1821         u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
1822         u32 i2cctl_r = 0;
1823
1824         for (i = 0; i < timeout; i++) {
1825                 *i2cctl |= IXGBE_I2C_CLK_OUT;
1826                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1827                 IXGBE_WRITE_FLUSH(hw);
1828                 /* SCL rise time (1000ns) */
1829                 udelay(IXGBE_I2C_T_RISE);
1830
1831                 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1832                 if (i2cctl_r & IXGBE_I2C_CLK_IN)
1833                         break;
1834         }
1835 }
1836
1837 /**
1838  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1839  *  @hw: pointer to hardware structure
1840  *  @i2cctl: Current value of I2CCTL register
1841  *
1842  *  Lowers the I2C clock line '1'->'0'
1843  **/
1844 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1845 {
1846
1847         *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1848
1849         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1850         IXGBE_WRITE_FLUSH(hw);
1851
1852         /* SCL fall time (300ns) */
1853         udelay(IXGBE_I2C_T_FALL);
1854 }
1855
1856 /**
1857  *  ixgbe_set_i2c_data - Sets the I2C data bit
1858  *  @hw: pointer to hardware structure
1859  *  @i2cctl: Current value of I2CCTL register
1860  *  @data: I2C data value (0 or 1) to set
1861  *
1862  *  Sets the I2C data bit
1863  **/
1864 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1865 {
1866         if (data)
1867                 *i2cctl |= IXGBE_I2C_DATA_OUT;
1868         else
1869                 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1870
1871         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1872         IXGBE_WRITE_FLUSH(hw);
1873
1874         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1875         udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1876
1877         /* Verify data was set correctly */
1878         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1879         if (data != ixgbe_get_i2c_data(i2cctl)) {
1880                 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
1881                 return IXGBE_ERR_I2C;
1882         }
1883
1884         return 0;
1885 }
1886
1887 /**
1888  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
1889  *  @hw: pointer to hardware structure
1890  *  @i2cctl: Current value of I2CCTL register
1891  *
1892  *  Returns the I2C data bit value
1893  **/
1894 static bool ixgbe_get_i2c_data(u32 *i2cctl)
1895 {
1896         if (*i2cctl & IXGBE_I2C_DATA_IN)
1897                 return true;
1898         return false;
1899 }
1900
1901 /**
1902  *  ixgbe_i2c_bus_clear - Clears the I2C bus
1903  *  @hw: pointer to hardware structure
1904  *
1905  *  Clears the I2C bus by sending nine clock pulses.
1906  *  Used when data line is stuck low.
1907  **/
1908 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1909 {
1910         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1911         u32 i;
1912
1913         ixgbe_i2c_start(hw);
1914
1915         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1916
1917         for (i = 0; i < 9; i++) {
1918                 ixgbe_raise_i2c_clk(hw, &i2cctl);
1919
1920                 /* Min high period of clock is 4us */
1921                 udelay(IXGBE_I2C_T_HIGH);
1922
1923                 ixgbe_lower_i2c_clk(hw, &i2cctl);
1924
1925                 /* Min low period of clock is 4.7us*/
1926                 udelay(IXGBE_I2C_T_LOW);
1927         }
1928
1929         ixgbe_i2c_start(hw);
1930
1931         /* Put the i2c bus back to default state */
1932         ixgbe_i2c_stop(hw);
1933 }
1934
1935 /**
1936  *  ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
1937  *  @hw: pointer to hardware structure
1938  *
1939  *  Checks if the LASI temp alarm status was triggered due to overtemp
1940  **/
1941 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
1942 {
1943         u16 phy_data = 0;
1944
1945         if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
1946                 return 0;
1947
1948         /* Check that the LASI temp alarm status was triggered */
1949         hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
1950                              MDIO_MMD_PMAPMD, &phy_data);
1951
1952         if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
1953                 return 0;
1954
1955         return IXGBE_ERR_OVERTEMP;
1956 }