1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
15 #include <linux/of_device.h>
16 #include <linux/of_mdio.h>
17 #include <linux/of_net.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/regmap.h>
20 #include <linux/clk.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/if_vlan.h>
23 #include <linux/reset.h>
24 #include <linux/tcp.h>
26 #include "mtk_eth_soc.h"
28 static int mtk_msg_level = -1;
29 module_param_named(msg_level, mtk_msg_level, int, 0);
30 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
32 #define MTK_ETHTOOL_STAT(x) { #x, \
33 offsetof(struct mtk_hw_stats, x) / sizeof(u64) }
35 /* strings used by ethtool */
36 static const struct mtk_ethtool_stats {
37 char str[ETH_GSTRING_LEN];
39 } mtk_ethtool_stats[] = {
40 MTK_ETHTOOL_STAT(tx_bytes),
41 MTK_ETHTOOL_STAT(tx_packets),
42 MTK_ETHTOOL_STAT(tx_skip),
43 MTK_ETHTOOL_STAT(tx_collisions),
44 MTK_ETHTOOL_STAT(rx_bytes),
45 MTK_ETHTOOL_STAT(rx_packets),
46 MTK_ETHTOOL_STAT(rx_overflow),
47 MTK_ETHTOOL_STAT(rx_fcs_errors),
48 MTK_ETHTOOL_STAT(rx_short_errors),
49 MTK_ETHTOOL_STAT(rx_long_errors),
50 MTK_ETHTOOL_STAT(rx_checksum_errors),
51 MTK_ETHTOOL_STAT(rx_flow_control_packets),
54 static const char * const mtk_clks_source_name[] = {
55 "ethif", "esw", "gp1", "gp2", "trgpll"
58 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
60 __raw_writel(val, eth->base + reg);
63 u32 mtk_r32(struct mtk_eth *eth, unsigned reg)
65 return __raw_readl(eth->base + reg);
68 static int mtk_mdio_busy_wait(struct mtk_eth *eth)
70 unsigned long t_start = jiffies;
73 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS))
75 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT))
80 dev_err(eth->dev, "mdio: MDIO timeout\n");
84 static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr,
85 u32 phy_register, u32 write_data)
87 if (mtk_mdio_busy_wait(eth))
92 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
93 (phy_register << PHY_IAC_REG_SHIFT) |
94 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,
97 if (mtk_mdio_busy_wait(eth))
103 static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg)
107 if (mtk_mdio_busy_wait(eth))
110 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
111 (phy_reg << PHY_IAC_REG_SHIFT) |
112 (phy_addr << PHY_IAC_ADDR_SHIFT),
115 if (mtk_mdio_busy_wait(eth))
118 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff;
123 static int mtk_mdio_write(struct mii_bus *bus, int phy_addr,
124 int phy_reg, u16 val)
126 struct mtk_eth *eth = bus->priv;
128 return _mtk_mdio_write(eth, phy_addr, phy_reg, val);
131 static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
133 struct mtk_eth *eth = bus->priv;
135 return _mtk_mdio_read(eth, phy_addr, phy_reg);
138 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, int speed)
143 val = (speed == SPEED_1000) ?
144 INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100;
145 mtk_w32(eth, val, INTF_MODE);
147 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0,
148 ETHSYS_TRGMII_CLK_SEL362_5,
149 ETHSYS_TRGMII_CLK_SEL362_5);
151 val = (speed == SPEED_1000) ? 250000000 : 500000000;
152 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val);
154 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret);
156 val = (speed == SPEED_1000) ?
157 RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100;
158 mtk_w32(eth, val, TRGMII_RCK_CTRL);
160 val = (speed == SPEED_1000) ?
161 TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100;
162 mtk_w32(eth, val, TRGMII_TCK_CTRL);
165 static void mtk_phy_link_adjust(struct net_device *dev)
167 struct mtk_mac *mac = netdev_priv(dev);
168 u16 lcl_adv = 0, rmt_adv = 0;
170 u32 mcr = MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG |
171 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN |
172 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN |
175 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
178 switch (dev->phydev->speed) {
180 mcr |= MAC_MCR_SPEED_1000;
183 mcr |= MAC_MCR_SPEED_100;
187 if (mac->id == 0 && !mac->trgmii)
188 mtk_gmac0_rgmii_adjust(mac->hw, dev->phydev->speed);
190 if (dev->phydev->link)
191 mcr |= MAC_MCR_FORCE_LINK;
193 if (dev->phydev->duplex) {
194 mcr |= MAC_MCR_FORCE_DPX;
196 if (dev->phydev->pause)
197 rmt_adv = LPA_PAUSE_CAP;
198 if (dev->phydev->asym_pause)
199 rmt_adv |= LPA_PAUSE_ASYM;
201 if (dev->phydev->advertising & ADVERTISED_Pause)
202 lcl_adv |= ADVERTISE_PAUSE_CAP;
203 if (dev->phydev->advertising & ADVERTISED_Asym_Pause)
204 lcl_adv |= ADVERTISE_PAUSE_ASYM;
206 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
208 if (flowctrl & FLOW_CTRL_TX)
209 mcr |= MAC_MCR_FORCE_TX_FC;
210 if (flowctrl & FLOW_CTRL_RX)
211 mcr |= MAC_MCR_FORCE_RX_FC;
213 netif_dbg(mac->hw, link, dev, "rx pause %s, tx pause %s\n",
214 flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled",
215 flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled");
218 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
220 if (dev->phydev->link)
221 netif_carrier_on(dev);
223 netif_carrier_off(dev);
226 static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac,
227 struct device_node *phy_node)
229 struct phy_device *phydev;
232 phy_mode = of_get_phy_mode(phy_node);
234 dev_err(eth->dev, "incorrect phy-mode %d\n", phy_mode);
238 phydev = of_phy_connect(eth->netdev[mac->id], phy_node,
239 mtk_phy_link_adjust, 0, phy_mode);
241 dev_err(eth->dev, "could not connect to PHY\n");
246 "connected mac %d to PHY at %s [uid=%08x, driver=%s]\n",
247 mac->id, phydev_name(phydev), phydev->phy_id,
253 static int mtk_phy_connect(struct net_device *dev)
255 struct mtk_mac *mac = netdev_priv(dev);
257 struct device_node *np;
261 np = of_parse_phandle(mac->of_node, "phy-handle", 0);
262 if (!np && of_phy_is_fixed_link(mac->of_node))
263 if (!of_phy_register_fixed_link(mac->of_node))
264 np = of_node_get(mac->of_node);
268 switch (of_get_phy_mode(np)) {
269 case PHY_INTERFACE_MODE_TRGMII:
271 case PHY_INTERFACE_MODE_RGMII_TXID:
272 case PHY_INTERFACE_MODE_RGMII_RXID:
273 case PHY_INTERFACE_MODE_RGMII_ID:
274 case PHY_INTERFACE_MODE_RGMII:
277 case PHY_INTERFACE_MODE_MII:
280 case PHY_INTERFACE_MODE_REVMII:
283 case PHY_INTERFACE_MODE_RMII:
292 /* put the gmac into the right mode */
293 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
294 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
295 val |= SYSCFG0_GE_MODE(mac->ge_mode, mac->id);
296 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
298 /* couple phydev to net_device */
299 if (mtk_phy_connect_node(eth, mac, np))
302 dev->phydev->autoneg = AUTONEG_ENABLE;
303 dev->phydev->speed = 0;
304 dev->phydev->duplex = 0;
306 if (of_phy_is_fixed_link(mac->of_node))
307 dev->phydev->supported |=
308 SUPPORTED_Pause | SUPPORTED_Asym_Pause;
310 dev->phydev->supported &= PHY_GBIT_FEATURES | SUPPORTED_Pause |
311 SUPPORTED_Asym_Pause;
312 dev->phydev->advertising = dev->phydev->supported |
314 phy_start_aneg(dev->phydev);
322 dev_err(eth->dev, "%s: invalid phy\n", __func__);
326 static int mtk_mdio_init(struct mtk_eth *eth)
328 struct device_node *mii_np;
331 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
333 dev_err(eth->dev, "no %s child node found", "mdio-bus");
337 if (!of_device_is_available(mii_np)) {
342 eth->mii_bus = devm_mdiobus_alloc(eth->dev);
348 eth->mii_bus->name = "mdio";
349 eth->mii_bus->read = mtk_mdio_read;
350 eth->mii_bus->write = mtk_mdio_write;
351 eth->mii_bus->priv = eth;
352 eth->mii_bus->parent = eth->dev;
354 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
355 ret = of_mdiobus_register(eth->mii_bus, mii_np);
362 static void mtk_mdio_cleanup(struct mtk_eth *eth)
367 mdiobus_unregister(eth->mii_bus);
370 static inline void mtk_irq_disable(struct mtk_eth *eth,
371 unsigned reg, u32 mask)
376 spin_lock_irqsave(ð->irq_lock, flags);
377 val = mtk_r32(eth, reg);
378 mtk_w32(eth, val & ~mask, reg);
379 spin_unlock_irqrestore(ð->irq_lock, flags);
382 static inline void mtk_irq_enable(struct mtk_eth *eth,
383 unsigned reg, u32 mask)
388 spin_lock_irqsave(ð->irq_lock, flags);
389 val = mtk_r32(eth, reg);
390 mtk_w32(eth, val | mask, reg);
391 spin_unlock_irqrestore(ð->irq_lock, flags);
394 static int mtk_set_mac_address(struct net_device *dev, void *p)
396 int ret = eth_mac_addr(dev, p);
397 struct mtk_mac *mac = netdev_priv(dev);
398 const char *macaddr = dev->dev_addr;
403 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
406 spin_lock_bh(&mac->hw->page_lock);
407 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
408 MTK_GDMA_MAC_ADRH(mac->id));
409 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
410 (macaddr[4] << 8) | macaddr[5],
411 MTK_GDMA_MAC_ADRL(mac->id));
412 spin_unlock_bh(&mac->hw->page_lock);
417 void mtk_stats_update_mac(struct mtk_mac *mac)
419 struct mtk_hw_stats *hw_stats = mac->hw_stats;
420 unsigned int base = MTK_GDM1_TX_GBCNT;
423 base += hw_stats->reg_offset;
425 u64_stats_update_begin(&hw_stats->syncp);
427 hw_stats->rx_bytes += mtk_r32(mac->hw, base);
428 stats = mtk_r32(mac->hw, base + 0x04);
430 hw_stats->rx_bytes += (stats << 32);
431 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08);
432 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10);
433 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14);
434 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18);
435 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c);
436 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20);
437 hw_stats->rx_flow_control_packets +=
438 mtk_r32(mac->hw, base + 0x24);
439 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28);
440 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c);
441 hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30);
442 stats = mtk_r32(mac->hw, base + 0x34);
444 hw_stats->tx_bytes += (stats << 32);
445 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38);
446 u64_stats_update_end(&hw_stats->syncp);
449 static void mtk_stats_update(struct mtk_eth *eth)
453 for (i = 0; i < MTK_MAC_COUNT; i++) {
454 if (!eth->mac[i] || !eth->mac[i]->hw_stats)
456 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) {
457 mtk_stats_update_mac(eth->mac[i]);
458 spin_unlock(ð->mac[i]->hw_stats->stats_lock);
463 static struct rtnl_link_stats64 *mtk_get_stats64(struct net_device *dev,
464 struct rtnl_link_stats64 *storage)
466 struct mtk_mac *mac = netdev_priv(dev);
467 struct mtk_hw_stats *hw_stats = mac->hw_stats;
470 if (netif_running(dev) && netif_device_present(dev)) {
471 if (spin_trylock(&hw_stats->stats_lock)) {
472 mtk_stats_update_mac(mac);
473 spin_unlock(&hw_stats->stats_lock);
478 start = u64_stats_fetch_begin_irq(&hw_stats->syncp);
479 storage->rx_packets = hw_stats->rx_packets;
480 storage->tx_packets = hw_stats->tx_packets;
481 storage->rx_bytes = hw_stats->rx_bytes;
482 storage->tx_bytes = hw_stats->tx_bytes;
483 storage->collisions = hw_stats->tx_collisions;
484 storage->rx_length_errors = hw_stats->rx_short_errors +
485 hw_stats->rx_long_errors;
486 storage->rx_over_errors = hw_stats->rx_overflow;
487 storage->rx_crc_errors = hw_stats->rx_fcs_errors;
488 storage->rx_errors = hw_stats->rx_checksum_errors;
489 storage->tx_aborted_errors = hw_stats->tx_skip;
490 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start));
492 storage->tx_errors = dev->stats.tx_errors;
493 storage->rx_dropped = dev->stats.rx_dropped;
494 storage->tx_dropped = dev->stats.tx_dropped;
499 static inline int mtk_max_frag_size(int mtu)
501 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */
502 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH)
503 mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN;
505 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) +
506 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
509 static inline int mtk_max_buf_size(int frag_size)
511 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
512 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
514 WARN_ON(buf_size < MTK_MAX_RX_LENGTH);
519 static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd,
520 struct mtk_rx_dma *dma_rxd)
522 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
523 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2);
524 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
525 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
528 /* the qdma core needs scratch memory to be setup */
529 static int mtk_init_fq_dma(struct mtk_eth *eth)
531 dma_addr_t phy_ring_tail;
532 int cnt = MTK_DMA_SIZE;
536 eth->scratch_ring = dma_alloc_coherent(eth->dev,
537 cnt * sizeof(struct mtk_tx_dma),
538 ð->phy_scratch_ring,
539 GFP_ATOMIC | __GFP_ZERO);
540 if (unlikely(!eth->scratch_ring))
543 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE,
545 if (unlikely(!eth->scratch_head))
548 dma_addr = dma_map_single(eth->dev,
549 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE,
551 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
554 memset(eth->scratch_ring, 0x0, sizeof(struct mtk_tx_dma) * cnt);
555 phy_ring_tail = eth->phy_scratch_ring +
556 (sizeof(struct mtk_tx_dma) * (cnt - 1));
558 for (i = 0; i < cnt; i++) {
559 eth->scratch_ring[i].txd1 =
560 (dma_addr + (i * MTK_QDMA_PAGE_SIZE));
562 eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring +
563 ((i + 1) * sizeof(struct mtk_tx_dma)));
564 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE);
567 mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD);
568 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL);
569 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT);
570 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN);
575 static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc)
577 void *ret = ring->dma;
579 return ret + (desc - ring->phys);
582 static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring,
583 struct mtk_tx_dma *txd)
585 int idx = txd - ring->dma;
587 return &ring->buf[idx];
590 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf)
592 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) {
593 dma_unmap_single(eth->dev,
594 dma_unmap_addr(tx_buf, dma_addr0),
595 dma_unmap_len(tx_buf, dma_len0),
597 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) {
598 dma_unmap_page(eth->dev,
599 dma_unmap_addr(tx_buf, dma_addr0),
600 dma_unmap_len(tx_buf, dma_len0),
605 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC))
606 dev_kfree_skb_any(tx_buf->skb);
610 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
611 int tx_num, struct mtk_tx_ring *ring, bool gso)
613 struct mtk_mac *mac = netdev_priv(dev);
614 struct mtk_eth *eth = mac->hw;
615 struct mtk_tx_dma *itxd, *txd;
616 struct mtk_tx_buf *tx_buf;
617 dma_addr_t mapped_addr;
618 unsigned int nr_frags;
622 itxd = ring->next_free;
623 if (itxd == ring->last_free)
626 /* set the forward port */
627 fport = (mac->id + 1) << TX_DMA_FPORT_SHIFT;
630 tx_buf = mtk_desc_to_tx_buf(ring, itxd);
631 memset(tx_buf, 0, sizeof(*tx_buf));
636 /* TX Checksum offload */
637 if (skb->ip_summed == CHECKSUM_PARTIAL)
638 txd4 |= TX_DMA_CHKSUM;
640 /* VLAN header offload */
641 if (skb_vlan_tag_present(skb))
642 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb);
644 mapped_addr = dma_map_single(eth->dev, skb->data,
645 skb_headlen(skb), DMA_TO_DEVICE);
646 if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
649 WRITE_ONCE(itxd->txd1, mapped_addr);
650 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
651 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
652 dma_unmap_len_set(tx_buf, dma_len0, skb_headlen(skb));
656 nr_frags = skb_shinfo(skb)->nr_frags;
657 for (i = 0; i < nr_frags; i++) {
658 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
659 unsigned int offset = 0;
660 int frag_size = skb_frag_size(frag);
663 bool last_frag = false;
664 unsigned int frag_map_size;
666 txd = mtk_qdma_phys_to_virt(ring, txd->txd2);
667 if (txd == ring->last_free)
671 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN);
672 mapped_addr = skb_frag_dma_map(eth->dev, frag, offset,
675 if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
678 if (i == nr_frags - 1 &&
679 (frag_size - frag_map_size) == 0)
682 WRITE_ONCE(txd->txd1, mapped_addr);
683 WRITE_ONCE(txd->txd3, (TX_DMA_SWC |
684 TX_DMA_PLEN0(frag_map_size) |
685 last_frag * TX_DMA_LS0));
686 WRITE_ONCE(txd->txd4, fport);
688 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC;
689 tx_buf = mtk_desc_to_tx_buf(ring, txd);
690 memset(tx_buf, 0, sizeof(*tx_buf));
692 tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
693 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
694 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size);
695 frag_size -= frag_map_size;
696 offset += frag_map_size;
700 /* store skb to cleanup */
703 WRITE_ONCE(itxd->txd4, txd4);
704 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) |
705 (!nr_frags * TX_DMA_LS0)));
707 netdev_sent_queue(dev, skb->len);
708 skb_tx_timestamp(skb);
710 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
711 atomic_sub(n_desc, &ring->free_count);
713 /* make sure that all changes to the dma ring are flushed before we
718 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more)
719 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR);
725 tx_buf = mtk_desc_to_tx_buf(ring, itxd);
728 mtk_tx_unmap(eth, tx_buf);
730 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
731 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2);
732 } while (itxd != txd);
737 static inline int mtk_cal_txd_req(struct sk_buff *skb)
740 struct skb_frag_struct *frag;
743 if (skb_is_gso(skb)) {
744 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
745 frag = &skb_shinfo(skb)->frags[i];
746 nfrags += DIV_ROUND_UP(frag->size, MTK_TX_DMA_BUF_LEN);
749 nfrags += skb_shinfo(skb)->nr_frags;
755 static int mtk_queue_stopped(struct mtk_eth *eth)
759 for (i = 0; i < MTK_MAC_COUNT; i++) {
762 if (netif_queue_stopped(eth->netdev[i]))
769 static void mtk_wake_queue(struct mtk_eth *eth)
773 for (i = 0; i < MTK_MAC_COUNT; i++) {
776 netif_wake_queue(eth->netdev[i]);
780 static void mtk_stop_queue(struct mtk_eth *eth)
784 for (i = 0; i < MTK_MAC_COUNT; i++) {
787 netif_stop_queue(eth->netdev[i]);
791 static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
793 struct mtk_mac *mac = netdev_priv(dev);
794 struct mtk_eth *eth = mac->hw;
795 struct mtk_tx_ring *ring = ð->tx_ring;
796 struct net_device_stats *stats = &dev->stats;
800 /* normally we can rely on the stack not calling this more than once,
801 * however we have 2 queues running on the same ring so we need to lock
804 spin_lock(ð->page_lock);
806 if (unlikely(test_bit(MTK_RESETTING, ð->state)))
809 tx_num = mtk_cal_txd_req(skb);
810 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) {
812 netif_err(eth, tx_queued, dev,
813 "Tx Ring full when queue awake!\n");
814 spin_unlock(ð->page_lock);
815 return NETDEV_TX_BUSY;
818 /* TSO: fill MSS info in tcp checksum field */
819 if (skb_is_gso(skb)) {
820 if (skb_cow_head(skb, 0)) {
821 netif_warn(eth, tx_err, dev,
822 "GSO expand head fail.\n");
826 if (skb_shinfo(skb)->gso_type &
827 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
829 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
833 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0)
836 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh))
839 spin_unlock(ð->page_lock);
844 spin_unlock(ð->page_lock);
850 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth)
853 struct mtk_rx_ring *ring;
857 return ð->rx_ring[0];
859 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) {
860 ring = ð->rx_ring[i];
861 idx = NEXT_RX_DESP_IDX(ring->calc_idx, ring->dma_size);
862 if (ring->dma[idx].rxd2 & RX_DMA_DONE) {
863 ring->calc_idx_update = true;
871 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth)
873 struct mtk_rx_ring *ring;
877 ring = ð->rx_ring[0];
878 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
880 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) {
881 ring = ð->rx_ring[i];
882 if (ring->calc_idx_update) {
883 ring->calc_idx_update = false;
884 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
890 static int mtk_poll_rx(struct napi_struct *napi, int budget,
893 struct mtk_rx_ring *ring;
897 struct mtk_rx_dma *rxd, trxd;
900 while (done < budget) {
901 struct net_device *netdev;
906 ring = mtk_get_rx_ring(eth);
910 idx = NEXT_RX_DESP_IDX(ring->calc_idx, ring->dma_size);
911 rxd = &ring->dma[idx];
912 data = ring->data[idx];
914 mtk_rx_get_desc(&trxd, rxd);
915 if (!(trxd.rxd2 & RX_DMA_DONE))
918 /* find out which mac the packet come from. values start at 1 */
919 mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
923 netdev = eth->netdev[mac];
925 if (unlikely(test_bit(MTK_RESETTING, ð->state)))
928 /* alloc new buffer */
929 new_data = napi_alloc_frag(ring->frag_size);
930 if (unlikely(!new_data)) {
931 netdev->stats.rx_dropped++;
934 dma_addr = dma_map_single(eth->dev,
935 new_data + NET_SKB_PAD,
938 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) {
939 skb_free_frag(new_data);
940 netdev->stats.rx_dropped++;
945 skb = build_skb(data, ring->frag_size);
946 if (unlikely(!skb)) {
947 skb_free_frag(new_data);
948 netdev->stats.rx_dropped++;
951 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
953 dma_unmap_single(eth->dev, trxd.rxd1,
954 ring->buf_size, DMA_FROM_DEVICE);
955 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
957 skb_put(skb, pktlen);
958 if (trxd.rxd4 & RX_DMA_L4_VALID)
959 skb->ip_summed = CHECKSUM_UNNECESSARY;
961 skb_checksum_none_assert(skb);
962 skb->protocol = eth_type_trans(skb, netdev);
964 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&
965 RX_DMA_VID(trxd.rxd3))
966 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
967 RX_DMA_VID(trxd.rxd3));
968 napi_gro_receive(napi, skb);
970 ring->data[idx] = new_data;
971 rxd->rxd1 = (unsigned int)dma_addr;
974 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size);
976 ring->calc_idx = idx;
983 /* make sure that all changes to the dma ring are flushed before
987 mtk_update_rx_cpu_idx(eth);
993 static int mtk_poll_tx(struct mtk_eth *eth, int budget)
995 struct mtk_tx_ring *ring = ð->tx_ring;
996 struct mtk_tx_dma *desc;
998 struct mtk_tx_buf *tx_buf;
999 unsigned int done[MTK_MAX_DEVS];
1000 unsigned int bytes[MTK_MAX_DEVS];
1002 static int condition;
1005 memset(done, 0, sizeof(done));
1006 memset(bytes, 0, sizeof(bytes));
1008 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR);
1009 dma = mtk_r32(eth, MTK_QTX_DRX_PTR);
1011 desc = mtk_qdma_phys_to_virt(ring, cpu);
1013 while ((cpu != dma) && budget) {
1014 u32 next_cpu = desc->txd2;
1017 desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
1018 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
1021 mac = (desc->txd4 >> TX_DMA_FPORT_SHIFT) &
1025 tx_buf = mtk_desc_to_tx_buf(ring, desc);
1032 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) {
1033 bytes[mac] += skb->len;
1037 mtk_tx_unmap(eth, tx_buf);
1039 ring->last_free = desc;
1040 atomic_inc(&ring->free_count);
1045 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR);
1047 for (i = 0; i < MTK_MAC_COUNT; i++) {
1048 if (!eth->netdev[i] || !done[i])
1050 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]);
1054 if (mtk_queue_stopped(eth) &&
1055 (atomic_read(&ring->free_count) > ring->thresh))
1056 mtk_wake_queue(eth);
1061 static void mtk_handle_status_irq(struct mtk_eth *eth)
1063 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2);
1065 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) {
1066 mtk_stats_update(eth);
1067 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF),
1072 static int mtk_napi_tx(struct napi_struct *napi, int budget)
1074 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi);
1078 mtk_handle_status_irq(eth);
1079 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QMTK_INT_STATUS);
1080 tx_done = mtk_poll_tx(eth, budget);
1082 if (unlikely(netif_msg_intr(eth))) {
1083 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
1084 mask = mtk_r32(eth, MTK_QDMA_INT_MASK);
1086 "done tx %d, intr 0x%08x/0x%x\n",
1087 tx_done, status, mask);
1090 if (tx_done == budget)
1093 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
1094 if (status & MTK_TX_DONE_INT)
1097 napi_complete(napi);
1098 mtk_irq_enable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
1103 static int mtk_napi_rx(struct napi_struct *napi, int budget)
1105 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);
1108 int remain_budget = budget;
1110 mtk_handle_status_irq(eth);
1113 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS);
1114 rx_done = mtk_poll_rx(napi, remain_budget, eth);
1116 if (unlikely(netif_msg_intr(eth))) {
1117 status = mtk_r32(eth, MTK_PDMA_INT_STATUS);
1118 mask = mtk_r32(eth, MTK_PDMA_INT_MASK);
1120 "done rx %d, intr 0x%08x/0x%x\n",
1121 rx_done, status, mask);
1123 if (rx_done == remain_budget)
1126 status = mtk_r32(eth, MTK_PDMA_INT_STATUS);
1127 if (status & MTK_RX_DONE_INT) {
1128 remain_budget -= rx_done;
1131 napi_complete(napi);
1132 mtk_irq_enable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
1134 return rx_done + budget - remain_budget;
1137 static int mtk_tx_alloc(struct mtk_eth *eth)
1139 struct mtk_tx_ring *ring = ð->tx_ring;
1140 int i, sz = sizeof(*ring->dma);
1142 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf),
1147 ring->dma = dma_alloc_coherent(eth->dev,
1150 GFP_ATOMIC | __GFP_ZERO);
1154 memset(ring->dma, 0, MTK_DMA_SIZE * sz);
1155 for (i = 0; i < MTK_DMA_SIZE; i++) {
1156 int next = (i + 1) % MTK_DMA_SIZE;
1157 u32 next_ptr = ring->phys + next * sz;
1159 ring->dma[i].txd2 = next_ptr;
1160 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
1163 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2);
1164 ring->next_free = &ring->dma[0];
1165 ring->last_free = &ring->dma[MTK_DMA_SIZE - 1];
1166 ring->thresh = MAX_SKB_FRAGS;
1168 /* make sure that all changes to the dma ring are flushed before we
1173 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR);
1174 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR);
1176 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1179 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1181 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, MTK_QTX_CFG(0));
1189 static void mtk_tx_clean(struct mtk_eth *eth)
1191 struct mtk_tx_ring *ring = ð->tx_ring;
1195 for (i = 0; i < MTK_DMA_SIZE; i++)
1196 mtk_tx_unmap(eth, &ring->buf[i]);
1202 dma_free_coherent(eth->dev,
1203 MTK_DMA_SIZE * sizeof(*ring->dma),
1210 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag)
1212 struct mtk_rx_ring *ring = ð->rx_ring[ring_no];
1213 int rx_data_len, rx_dma_size;
1216 if (rx_flag == MTK_RX_FLAGS_HWLRO) {
1217 rx_data_len = MTK_MAX_LRO_RX_LENGTH;
1218 rx_dma_size = MTK_HW_LRO_DMA_SIZE;
1220 rx_data_len = ETH_DATA_LEN;
1221 rx_dma_size = MTK_DMA_SIZE;
1224 ring->frag_size = mtk_max_frag_size(rx_data_len);
1225 ring->buf_size = mtk_max_buf_size(ring->frag_size);
1226 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data),
1231 for (i = 0; i < rx_dma_size; i++) {
1232 ring->data[i] = netdev_alloc_frag(ring->frag_size);
1237 ring->dma = dma_alloc_coherent(eth->dev,
1238 rx_dma_size * sizeof(*ring->dma),
1240 GFP_ATOMIC | __GFP_ZERO);
1244 for (i = 0; i < rx_dma_size; i++) {
1245 dma_addr_t dma_addr = dma_map_single(eth->dev,
1246 ring->data[i] + NET_SKB_PAD,
1249 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
1251 ring->dma[i].rxd1 = (unsigned int)dma_addr;
1253 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size);
1255 ring->dma_size = rx_dma_size;
1256 ring->calc_idx_update = false;
1257 ring->calc_idx = rx_dma_size - 1;
1258 ring->crx_idx_reg = MTK_PRX_CRX_IDX_CFG(ring_no);
1259 /* make sure that all changes to the dma ring are flushed before we
1264 mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no));
1265 mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no));
1266 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
1267 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX);
1272 static void mtk_rx_clean(struct mtk_eth *eth, int ring_no)
1274 struct mtk_rx_ring *ring = ð->rx_ring[ring_no];
1277 if (ring->data && ring->dma) {
1278 for (i = 0; i < ring->dma_size; i++) {
1281 if (!ring->dma[i].rxd1)
1283 dma_unmap_single(eth->dev,
1287 skb_free_frag(ring->data[i]);
1294 dma_free_coherent(eth->dev,
1295 ring->dma_size * sizeof(*ring->dma),
1302 static int mtk_hwlro_rx_init(struct mtk_eth *eth)
1305 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0;
1306 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0;
1308 /* set LRO rings to auto-learn modes */
1309 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE;
1311 /* validate LRO ring */
1312 ring_ctrl_dw2 |= MTK_RING_VLD;
1314 /* set AGE timer (unit: 20us) */
1315 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H;
1316 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L;
1318 /* set max AGG timer (unit: 20us) */
1319 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME;
1321 /* set max LRO AGG count */
1322 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L;
1323 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H;
1325 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
1326 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i));
1327 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i));
1328 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i));
1331 /* IPv4 checksum update enable */
1332 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN;
1334 /* switch priority comparison to packet count mode */
1335 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE;
1337 /* bandwidth threshold setting */
1338 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2);
1340 /* auto-learn score delta setting */
1341 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA);
1343 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */
1344 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME,
1345 MTK_PDMA_LRO_ALT_REFRESH_TIMER);
1347 /* set HW LRO mode & the max aggregation count for rx packets */
1348 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff);
1350 /* the minimal remaining room of SDL0 in RXD for lro aggregation */
1351 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL;
1354 lro_ctrl_dw0 |= MTK_LRO_EN;
1356 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3);
1357 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0);
1362 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth)
1367 /* relinquish lro rings, flush aggregated packets */
1368 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0);
1370 /* wait for relinquishments done */
1371 for (i = 0; i < 10; i++) {
1372 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0);
1373 if (val & MTK_LRO_RING_RELINQUISH_DONE) {
1379 /* invalidate lro rings */
1380 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
1381 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i));
1383 /* disable HW LRO */
1384 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0);
1387 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip)
1391 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
1393 /* invalidate the IP setting */
1394 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1396 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx));
1398 /* validate the IP setting */
1399 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1402 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx)
1406 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
1408 /* invalidate the IP setting */
1409 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1411 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx));
1414 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac)
1419 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
1420 if (mac->hwlro_ip[i])
1427 static int mtk_hwlro_add_ipaddr(struct net_device *dev,
1428 struct ethtool_rxnfc *cmd)
1430 struct ethtool_rx_flow_spec *fsp =
1431 (struct ethtool_rx_flow_spec *)&cmd->fs;
1432 struct mtk_mac *mac = netdev_priv(dev);
1433 struct mtk_eth *eth = mac->hw;
1436 if ((fsp->flow_type != TCP_V4_FLOW) ||
1437 (!fsp->h_u.tcp_ip4_spec.ip4dst) ||
1438 (fsp->location > 1))
1441 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst);
1442 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
1444 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
1446 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]);
1451 static int mtk_hwlro_del_ipaddr(struct net_device *dev,
1452 struct ethtool_rxnfc *cmd)
1454 struct ethtool_rx_flow_spec *fsp =
1455 (struct ethtool_rx_flow_spec *)&cmd->fs;
1456 struct mtk_mac *mac = netdev_priv(dev);
1457 struct mtk_eth *eth = mac->hw;
1460 if (fsp->location > 1)
1463 mac->hwlro_ip[fsp->location] = 0;
1464 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
1466 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
1468 mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
1473 static void mtk_hwlro_netdev_disable(struct net_device *dev)
1475 struct mtk_mac *mac = netdev_priv(dev);
1476 struct mtk_eth *eth = mac->hw;
1479 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
1480 mac->hwlro_ip[i] = 0;
1481 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i;
1483 mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
1486 mac->hwlro_ip_cnt = 0;
1489 static int mtk_hwlro_get_fdir_entry(struct net_device *dev,
1490 struct ethtool_rxnfc *cmd)
1492 struct mtk_mac *mac = netdev_priv(dev);
1493 struct ethtool_rx_flow_spec *fsp =
1494 (struct ethtool_rx_flow_spec *)&cmd->fs;
1496 /* only tcp dst ipv4 is meaningful, others are meaningless */
1497 fsp->flow_type = TCP_V4_FLOW;
1498 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]);
1499 fsp->m_u.tcp_ip4_spec.ip4dst = 0;
1501 fsp->h_u.tcp_ip4_spec.ip4src = 0;
1502 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff;
1503 fsp->h_u.tcp_ip4_spec.psrc = 0;
1504 fsp->m_u.tcp_ip4_spec.psrc = 0xffff;
1505 fsp->h_u.tcp_ip4_spec.pdst = 0;
1506 fsp->m_u.tcp_ip4_spec.pdst = 0xffff;
1507 fsp->h_u.tcp_ip4_spec.tos = 0;
1508 fsp->m_u.tcp_ip4_spec.tos = 0xff;
1513 static int mtk_hwlro_get_fdir_all(struct net_device *dev,
1514 struct ethtool_rxnfc *cmd,
1517 struct mtk_mac *mac = netdev_priv(dev);
1521 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
1522 if (mac->hwlro_ip[i]) {
1528 cmd->rule_cnt = cnt;
1533 static netdev_features_t mtk_fix_features(struct net_device *dev,
1534 netdev_features_t features)
1536 if (!(features & NETIF_F_LRO)) {
1537 struct mtk_mac *mac = netdev_priv(dev);
1538 int ip_cnt = mtk_hwlro_get_ip_cnt(mac);
1541 netdev_info(dev, "RX flow is programmed, LRO should keep on\n");
1543 features |= NETIF_F_LRO;
1550 static int mtk_set_features(struct net_device *dev, netdev_features_t features)
1554 if (!((dev->features ^ features) & NETIF_F_LRO))
1557 if (!(features & NETIF_F_LRO))
1558 mtk_hwlro_netdev_disable(dev);
1563 /* wait for DMA to finish whatever it is doing before we start using it again */
1564 static int mtk_dma_busy_wait(struct mtk_eth *eth)
1566 unsigned long t_start = jiffies;
1569 if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) &
1570 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)))
1572 if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT))
1576 dev_err(eth->dev, "DMA init timeout\n");
1580 static int mtk_dma_init(struct mtk_eth *eth)
1585 if (mtk_dma_busy_wait(eth))
1588 /* QDMA needs scratch memory for internal reordering of the
1591 err = mtk_init_fq_dma(eth);
1595 err = mtk_tx_alloc(eth);
1599 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL);
1604 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
1605 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO);
1609 err = mtk_hwlro_rx_init(eth);
1614 /* Enable random early drop and set drop threshold automatically */
1615 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | FC_THRES_MIN,
1617 mtk_w32(eth, 0x0, MTK_QDMA_HRED2);
1622 static void mtk_dma_free(struct mtk_eth *eth)
1626 for (i = 0; i < MTK_MAC_COUNT; i++)
1628 netdev_reset_queue(eth->netdev[i]);
1629 if (eth->scratch_ring) {
1630 dma_free_coherent(eth->dev,
1631 MTK_DMA_SIZE * sizeof(struct mtk_tx_dma),
1633 eth->phy_scratch_ring);
1634 eth->scratch_ring = NULL;
1635 eth->phy_scratch_ring = 0;
1638 mtk_rx_clean(eth, 0);
1641 mtk_hwlro_rx_uninit(eth);
1642 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
1643 mtk_rx_clean(eth, i);
1646 kfree(eth->scratch_head);
1649 static void mtk_tx_timeout(struct net_device *dev)
1651 struct mtk_mac *mac = netdev_priv(dev);
1652 struct mtk_eth *eth = mac->hw;
1654 eth->netdev[mac->id]->stats.tx_errors++;
1655 netif_err(eth, tx_err, dev,
1656 "transmit timed out\n");
1657 schedule_work(ð->pending_work);
1660 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth)
1662 struct mtk_eth *eth = _eth;
1664 if (likely(napi_schedule_prep(ð->rx_napi))) {
1665 __napi_schedule(ð->rx_napi);
1666 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
1672 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth)
1674 struct mtk_eth *eth = _eth;
1676 if (likely(napi_schedule_prep(ð->tx_napi))) {
1677 __napi_schedule(ð->tx_napi);
1678 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
1684 #ifdef CONFIG_NET_POLL_CONTROLLER
1685 static void mtk_poll_controller(struct net_device *dev)
1687 struct mtk_mac *mac = netdev_priv(dev);
1688 struct mtk_eth *eth = mac->hw;
1690 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
1691 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
1692 mtk_handle_irq_rx(eth->irq[2], dev);
1693 mtk_irq_enable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
1694 mtk_irq_enable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
1698 static int mtk_start_dma(struct mtk_eth *eth)
1702 err = mtk_dma_init(eth);
1709 MTK_TX_WB_DDONE | MTK_TX_DMA_EN |
1710 MTK_DMA_SIZE_16DWORDS | MTK_NDP_CO_PRO,
1714 MTK_RX_DMA_EN | MTK_RX_2B_OFFSET |
1715 MTK_RX_BT_32DWORDS | MTK_MULTI_EN,
1721 static int mtk_open(struct net_device *dev)
1723 struct mtk_mac *mac = netdev_priv(dev);
1724 struct mtk_eth *eth = mac->hw;
1726 /* we run 2 netdevs on the same dma ring so we only bring it up once */
1727 if (!atomic_read(ð->dma_refcnt)) {
1728 int err = mtk_start_dma(eth);
1733 napi_enable(ð->tx_napi);
1734 napi_enable(ð->rx_napi);
1735 mtk_irq_enable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
1736 mtk_irq_enable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
1738 atomic_inc(ð->dma_refcnt);
1740 phy_start(dev->phydev);
1741 netif_start_queue(dev);
1746 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg)
1751 /* stop the dma engine */
1752 spin_lock_bh(ð->page_lock);
1753 val = mtk_r32(eth, glo_cfg);
1754 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN),
1756 spin_unlock_bh(ð->page_lock);
1758 /* wait for dma stop */
1759 for (i = 0; i < 10; i++) {
1760 val = mtk_r32(eth, glo_cfg);
1761 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) {
1769 static int mtk_stop(struct net_device *dev)
1771 struct mtk_mac *mac = netdev_priv(dev);
1772 struct mtk_eth *eth = mac->hw;
1774 netif_tx_disable(dev);
1775 phy_stop(dev->phydev);
1777 /* only shutdown DMA if this is the last user */
1778 if (!atomic_dec_and_test(ð->dma_refcnt))
1781 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
1782 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
1783 napi_disable(ð->tx_napi);
1784 napi_disable(ð->rx_napi);
1786 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG);
1793 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits)
1795 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
1799 usleep_range(1000, 1100);
1800 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
1806 static int mtk_hw_init(struct mtk_eth *eth)
1810 if (test_and_set_bit(MTK_HW_INIT, ð->state))
1813 pm_runtime_enable(eth->dev);
1814 pm_runtime_get_sync(eth->dev);
1816 clk_prepare_enable(eth->clks[MTK_CLK_ETHIF]);
1817 clk_prepare_enable(eth->clks[MTK_CLK_ESW]);
1818 clk_prepare_enable(eth->clks[MTK_CLK_GP1]);
1819 clk_prepare_enable(eth->clks[MTK_CLK_GP2]);
1820 ethsys_reset(eth, RSTCTRL_FE);
1821 ethsys_reset(eth, RSTCTRL_PPE);
1823 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
1824 for (i = 0; i < MTK_MAC_COUNT; i++) {
1827 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, eth->mac[i]->id);
1828 val |= SYSCFG0_GE_MODE(eth->mac[i]->ge_mode, eth->mac[i]->id);
1830 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
1832 /* Set GE2 driving and slew rate */
1833 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
1836 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
1839 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
1841 /* GE1, Force 1000M/FD, FC ON */
1842 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(0));
1844 /* GE2, Force 1000M/FD, FC ON */
1845 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(1));
1847 /* Enable RX VLan Offloading */
1848 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
1850 /* disable delay and normal interrupt */
1851 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
1852 mtk_w32(eth, 0, MTK_PDMA_DELAY_INT);
1853 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, ~0);
1854 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, ~0);
1855 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
1856 mtk_w32(eth, 0, MTK_RST_GL);
1858 /* FE int grouping */
1859 mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1);
1860 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2);
1861 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1);
1862 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2);
1863 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
1865 for (i = 0; i < 2; i++) {
1866 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
1868 /* setup the forward port to send frame to PDMA */
1871 /* Enable RX checksum */
1872 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
1874 /* setup the mac dma */
1875 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
1881 static int mtk_hw_deinit(struct mtk_eth *eth)
1883 if (!test_and_clear_bit(MTK_HW_INIT, ð->state))
1886 clk_disable_unprepare(eth->clks[MTK_CLK_GP2]);
1887 clk_disable_unprepare(eth->clks[MTK_CLK_GP1]);
1888 clk_disable_unprepare(eth->clks[MTK_CLK_ESW]);
1889 clk_disable_unprepare(eth->clks[MTK_CLK_ETHIF]);
1891 pm_runtime_put_sync(eth->dev);
1892 pm_runtime_disable(eth->dev);
1897 static int __init mtk_init(struct net_device *dev)
1899 struct mtk_mac *mac = netdev_priv(dev);
1900 struct mtk_eth *eth = mac->hw;
1901 const char *mac_addr;
1903 mac_addr = of_get_mac_address(mac->of_node);
1905 ether_addr_copy(dev->dev_addr, mac_addr);
1907 /* If the mac address is invalid, use random mac address */
1908 if (!is_valid_ether_addr(dev->dev_addr)) {
1909 random_ether_addr(dev->dev_addr);
1910 dev_err(eth->dev, "generated random MAC address %pM\n",
1912 dev->addr_assign_type = NET_ADDR_RANDOM;
1915 return mtk_phy_connect(dev);
1918 static void mtk_uninit(struct net_device *dev)
1920 struct mtk_mac *mac = netdev_priv(dev);
1921 struct mtk_eth *eth = mac->hw;
1923 phy_disconnect(dev->phydev);
1924 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, ~0);
1925 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, ~0);
1928 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1934 return phy_mii_ioctl(dev->phydev, ifr, cmd);
1942 static void mtk_pending_work(struct work_struct *work)
1944 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work);
1946 unsigned long restart = 0;
1950 dev_dbg(eth->dev, "[%s][%d] reset\n", __func__, __LINE__);
1952 while (test_and_set_bit_lock(MTK_RESETTING, ð->state))
1955 dev_dbg(eth->dev, "[%s][%d] mtk_stop starts\n", __func__, __LINE__);
1956 /* stop all devices to make sure that dma is properly shut down */
1957 for (i = 0; i < MTK_MAC_COUNT; i++) {
1958 if (!eth->netdev[i])
1960 mtk_stop(eth->netdev[i]);
1961 __set_bit(i, &restart);
1963 dev_dbg(eth->dev, "[%s][%d] mtk_stop ends\n", __func__, __LINE__);
1965 /* restart underlying hardware such as power, clock, pin mux
1966 * and the connected phy
1971 pinctrl_select_state(eth->dev->pins->p,
1972 eth->dev->pins->default_state);
1975 for (i = 0; i < MTK_MAC_COUNT; i++) {
1977 of_phy_is_fixed_link(eth->mac[i]->of_node))
1979 err = phy_init_hw(eth->netdev[i]->phydev);
1981 dev_err(eth->dev, "%s: PHY init failed.\n",
1982 eth->netdev[i]->name);
1985 /* restart DMA and enable IRQs */
1986 for (i = 0; i < MTK_MAC_COUNT; i++) {
1987 if (!test_bit(i, &restart))
1989 err = mtk_open(eth->netdev[i]);
1991 netif_alert(eth, ifup, eth->netdev[i],
1992 "Driver up/down cycle failed, closing device.\n");
1993 dev_close(eth->netdev[i]);
1997 dev_dbg(eth->dev, "[%s][%d] reset done\n", __func__, __LINE__);
1999 clear_bit_unlock(MTK_RESETTING, ð->state);
2004 static int mtk_free_dev(struct mtk_eth *eth)
2008 for (i = 0; i < MTK_MAC_COUNT; i++) {
2009 if (!eth->netdev[i])
2011 free_netdev(eth->netdev[i]);
2017 static int mtk_unreg_dev(struct mtk_eth *eth)
2021 for (i = 0; i < MTK_MAC_COUNT; i++) {
2022 if (!eth->netdev[i])
2024 unregister_netdev(eth->netdev[i]);
2030 static int mtk_cleanup(struct mtk_eth *eth)
2034 cancel_work_sync(ð->pending_work);
2039 int mtk_get_link_ksettings(struct net_device *ndev,
2040 struct ethtool_link_ksettings *cmd)
2042 struct mtk_mac *mac = netdev_priv(ndev);
2044 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2047 return phy_ethtool_ksettings_get(ndev->phydev, cmd);
2050 int mtk_set_link_ksettings(struct net_device *ndev,
2051 const struct ethtool_link_ksettings *cmd)
2053 struct mtk_mac *mac = netdev_priv(ndev);
2055 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2058 return phy_ethtool_ksettings_set(ndev->phydev, cmd);
2061 static void mtk_get_drvinfo(struct net_device *dev,
2062 struct ethtool_drvinfo *info)
2064 struct mtk_mac *mac = netdev_priv(dev);
2066 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver));
2067 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info));
2068 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats);
2071 static u32 mtk_get_msglevel(struct net_device *dev)
2073 struct mtk_mac *mac = netdev_priv(dev);
2075 return mac->hw->msg_enable;
2078 static void mtk_set_msglevel(struct net_device *dev, u32 value)
2080 struct mtk_mac *mac = netdev_priv(dev);
2082 mac->hw->msg_enable = value;
2085 static int mtk_nway_reset(struct net_device *dev)
2087 struct mtk_mac *mac = netdev_priv(dev);
2089 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2092 return genphy_restart_aneg(dev->phydev);
2095 static u32 mtk_get_link(struct net_device *dev)
2097 struct mtk_mac *mac = netdev_priv(dev);
2100 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2103 err = genphy_update_link(dev->phydev);
2105 return ethtool_op_get_link(dev);
2107 return dev->phydev->link;
2110 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2114 switch (stringset) {
2116 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) {
2117 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN);
2118 data += ETH_GSTRING_LEN;
2124 static int mtk_get_sset_count(struct net_device *dev, int sset)
2128 return ARRAY_SIZE(mtk_ethtool_stats);
2134 static void mtk_get_ethtool_stats(struct net_device *dev,
2135 struct ethtool_stats *stats, u64 *data)
2137 struct mtk_mac *mac = netdev_priv(dev);
2138 struct mtk_hw_stats *hwstats = mac->hw_stats;
2139 u64 *data_src, *data_dst;
2143 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2146 if (netif_running(dev) && netif_device_present(dev)) {
2147 if (spin_trylock(&hwstats->stats_lock)) {
2148 mtk_stats_update_mac(mac);
2149 spin_unlock(&hwstats->stats_lock);
2153 data_src = (u64 *)hwstats;
2157 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
2159 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++)
2160 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset);
2161 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
2164 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
2167 int ret = -EOPNOTSUPP;
2170 case ETHTOOL_GRXRINGS:
2171 if (dev->features & NETIF_F_LRO) {
2172 cmd->data = MTK_MAX_RX_RING_NUM;
2176 case ETHTOOL_GRXCLSRLCNT:
2177 if (dev->features & NETIF_F_LRO) {
2178 struct mtk_mac *mac = netdev_priv(dev);
2180 cmd->rule_cnt = mac->hwlro_ip_cnt;
2184 case ETHTOOL_GRXCLSRULE:
2185 if (dev->features & NETIF_F_LRO)
2186 ret = mtk_hwlro_get_fdir_entry(dev, cmd);
2188 case ETHTOOL_GRXCLSRLALL:
2189 if (dev->features & NETIF_F_LRO)
2190 ret = mtk_hwlro_get_fdir_all(dev, cmd,
2200 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2202 int ret = -EOPNOTSUPP;
2205 case ETHTOOL_SRXCLSRLINS:
2206 if (dev->features & NETIF_F_LRO)
2207 ret = mtk_hwlro_add_ipaddr(dev, cmd);
2209 case ETHTOOL_SRXCLSRLDEL:
2210 if (dev->features & NETIF_F_LRO)
2211 ret = mtk_hwlro_del_ipaddr(dev, cmd);
2220 static const struct ethtool_ops mtk_ethtool_ops = {
2221 .get_link_ksettings = mtk_get_link_ksettings,
2222 .set_link_ksettings = mtk_set_link_ksettings,
2223 .get_drvinfo = mtk_get_drvinfo,
2224 .get_msglevel = mtk_get_msglevel,
2225 .set_msglevel = mtk_set_msglevel,
2226 .nway_reset = mtk_nway_reset,
2227 .get_link = mtk_get_link,
2228 .get_strings = mtk_get_strings,
2229 .get_sset_count = mtk_get_sset_count,
2230 .get_ethtool_stats = mtk_get_ethtool_stats,
2231 .get_rxnfc = mtk_get_rxnfc,
2232 .set_rxnfc = mtk_set_rxnfc,
2235 static const struct net_device_ops mtk_netdev_ops = {
2236 .ndo_init = mtk_init,
2237 .ndo_uninit = mtk_uninit,
2238 .ndo_open = mtk_open,
2239 .ndo_stop = mtk_stop,
2240 .ndo_start_xmit = mtk_start_xmit,
2241 .ndo_set_mac_address = mtk_set_mac_address,
2242 .ndo_validate_addr = eth_validate_addr,
2243 .ndo_do_ioctl = mtk_do_ioctl,
2244 .ndo_change_mtu = eth_change_mtu,
2245 .ndo_tx_timeout = mtk_tx_timeout,
2246 .ndo_get_stats64 = mtk_get_stats64,
2247 .ndo_fix_features = mtk_fix_features,
2248 .ndo_set_features = mtk_set_features,
2249 #ifdef CONFIG_NET_POLL_CONTROLLER
2250 .ndo_poll_controller = mtk_poll_controller,
2254 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
2256 struct mtk_mac *mac;
2257 const __be32 *_id = of_get_property(np, "reg", NULL);
2261 dev_err(eth->dev, "missing mac id\n");
2265 id = be32_to_cpup(_id);
2266 if (id >= MTK_MAC_COUNT) {
2267 dev_err(eth->dev, "%d is not a valid mac id\n", id);
2271 if (eth->netdev[id]) {
2272 dev_err(eth->dev, "duplicate mac id found: %d\n", id);
2276 eth->netdev[id] = alloc_etherdev(sizeof(*mac));
2277 if (!eth->netdev[id]) {
2278 dev_err(eth->dev, "alloc_etherdev failed\n");
2281 mac = netdev_priv(eth->netdev[id]);
2287 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip));
2288 mac->hwlro_ip_cnt = 0;
2290 mac->hw_stats = devm_kzalloc(eth->dev,
2291 sizeof(*mac->hw_stats),
2293 if (!mac->hw_stats) {
2294 dev_err(eth->dev, "failed to allocate counter memory\n");
2298 spin_lock_init(&mac->hw_stats->stats_lock);
2299 u64_stats_init(&mac->hw_stats->syncp);
2300 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
2302 SET_NETDEV_DEV(eth->netdev[id], eth->dev);
2303 eth->netdev[id]->watchdog_timeo = 5 * HZ;
2304 eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
2305 eth->netdev[id]->base_addr = (unsigned long)eth->base;
2307 eth->netdev[id]->hw_features = MTK_HW_FEATURES;
2309 eth->netdev[id]->hw_features |= NETIF_F_LRO;
2311 eth->netdev[id]->vlan_features = MTK_HW_FEATURES &
2312 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
2313 eth->netdev[id]->features |= MTK_HW_FEATURES;
2314 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops;
2316 eth->netdev[id]->irq = eth->irq[0];
2320 free_netdev(eth->netdev[id]);
2324 static int mtk_probe(struct platform_device *pdev)
2326 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2327 struct device_node *mac_np;
2328 const struct of_device_id *match;
2329 struct mtk_soc_data *soc;
2330 struct mtk_eth *eth;
2334 match = of_match_device(of_mtk_match, &pdev->dev);
2335 soc = (struct mtk_soc_data *)match->data;
2337 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL);
2341 eth->dev = &pdev->dev;
2342 eth->base = devm_ioremap_resource(&pdev->dev, res);
2343 if (IS_ERR(eth->base))
2344 return PTR_ERR(eth->base);
2346 spin_lock_init(ð->page_lock);
2347 spin_lock_init(ð->irq_lock);
2349 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2351 if (IS_ERR(eth->ethsys)) {
2352 dev_err(&pdev->dev, "no ethsys regmap found\n");
2353 return PTR_ERR(eth->ethsys);
2356 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2358 if (IS_ERR(eth->pctl)) {
2359 dev_err(&pdev->dev, "no pctl regmap found\n");
2360 return PTR_ERR(eth->pctl);
2363 eth->hwlro = of_property_read_bool(pdev->dev.of_node, "mediatek,hwlro");
2365 for (i = 0; i < 3; i++) {
2366 eth->irq[i] = platform_get_irq(pdev, i);
2367 if (eth->irq[i] < 0) {
2368 dev_err(&pdev->dev, "no IRQ%d resource found\n", i);
2372 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) {
2373 eth->clks[i] = devm_clk_get(eth->dev,
2374 mtk_clks_source_name[i]);
2375 if (IS_ERR(eth->clks[i])) {
2376 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER)
2377 return -EPROBE_DEFER;
2382 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
2383 INIT_WORK(ð->pending_work, mtk_pending_work);
2385 err = mtk_hw_init(eth);
2389 for_each_child_of_node(pdev->dev.of_node, mac_np) {
2390 if (!of_device_is_compatible(mac_np,
2391 "mediatek,eth-mac"))
2394 if (!of_device_is_available(mac_np))
2397 err = mtk_add_mac(eth, mac_np);
2402 err = devm_request_irq(eth->dev, eth->irq[1], mtk_handle_irq_tx, 0,
2403 dev_name(eth->dev), eth);
2407 err = devm_request_irq(eth->dev, eth->irq[2], mtk_handle_irq_rx, 0,
2408 dev_name(eth->dev), eth);
2412 err = mtk_mdio_init(eth);
2416 for (i = 0; i < MTK_MAX_DEVS; i++) {
2417 if (!eth->netdev[i])
2420 err = register_netdev(eth->netdev[i]);
2422 dev_err(eth->dev, "error bringing up device\n");
2423 goto err_deinit_mdio;
2425 netif_info(eth, probe, eth->netdev[i],
2426 "mediatek frame engine at 0x%08lx, irq %d\n",
2427 eth->netdev[i]->base_addr, eth->irq[0]);
2430 /* we run 2 devices on the same DMA ring so we need a dummy device
2433 init_dummy_netdev(ð->dummy_dev);
2434 netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx,
2436 netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx,
2439 platform_set_drvdata(pdev, eth);
2444 mtk_mdio_cleanup(eth);
2453 static int mtk_remove(struct platform_device *pdev)
2455 struct mtk_eth *eth = platform_get_drvdata(pdev);
2458 /* stop all devices to make sure that dma is properly shut down */
2459 for (i = 0; i < MTK_MAC_COUNT; i++) {
2460 if (!eth->netdev[i])
2462 mtk_stop(eth->netdev[i]);
2467 netif_napi_del(ð->tx_napi);
2468 netif_napi_del(ð->rx_napi);
2470 mtk_mdio_cleanup(eth);
2475 const struct of_device_id of_mtk_match[] = {
2476 { .compatible = "mediatek,mt7623-eth" },
2479 MODULE_DEVICE_TABLE(of, of_mtk_match);
2481 static struct platform_driver mtk_driver = {
2483 .remove = mtk_remove,
2485 .name = "mtk_soc_eth",
2486 .of_match_table = of_mtk_match,
2490 module_platform_driver(mtk_driver);
2492 MODULE_LICENSE("GPL");
2493 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
2494 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");