1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
15 #include <linux/of_device.h>
16 #include <linux/of_mdio.h>
17 #include <linux/of_net.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/regmap.h>
20 #include <linux/clk.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/if_vlan.h>
23 #include <linux/reset.h>
24 #include <linux/tcp.h>
26 #include "mtk_eth_soc.h"
28 static int mtk_msg_level = -1;
29 module_param_named(msg_level, mtk_msg_level, int, 0);
30 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
32 #define MTK_ETHTOOL_STAT(x) { #x, \
33 offsetof(struct mtk_hw_stats, x) / sizeof(u64) }
35 /* strings used by ethtool */
36 static const struct mtk_ethtool_stats {
37 char str[ETH_GSTRING_LEN];
39 } mtk_ethtool_stats[] = {
40 MTK_ETHTOOL_STAT(tx_bytes),
41 MTK_ETHTOOL_STAT(tx_packets),
42 MTK_ETHTOOL_STAT(tx_skip),
43 MTK_ETHTOOL_STAT(tx_collisions),
44 MTK_ETHTOOL_STAT(rx_bytes),
45 MTK_ETHTOOL_STAT(rx_packets),
46 MTK_ETHTOOL_STAT(rx_overflow),
47 MTK_ETHTOOL_STAT(rx_fcs_errors),
48 MTK_ETHTOOL_STAT(rx_short_errors),
49 MTK_ETHTOOL_STAT(rx_long_errors),
50 MTK_ETHTOOL_STAT(rx_checksum_errors),
51 MTK_ETHTOOL_STAT(rx_flow_control_packets),
54 static const char * const mtk_clks_source_name[] = {
55 "ethif", "esw", "gp1", "gp2"
58 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
60 __raw_writel(val, eth->base + reg);
63 u32 mtk_r32(struct mtk_eth *eth, unsigned reg)
65 return __raw_readl(eth->base + reg);
68 static int mtk_mdio_busy_wait(struct mtk_eth *eth)
70 unsigned long t_start = jiffies;
73 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS))
75 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT))
80 dev_err(eth->dev, "mdio: MDIO timeout\n");
84 static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr,
85 u32 phy_register, u32 write_data)
87 if (mtk_mdio_busy_wait(eth))
92 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
93 (phy_register << PHY_IAC_REG_SHIFT) |
94 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,
97 if (mtk_mdio_busy_wait(eth))
103 static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg)
107 if (mtk_mdio_busy_wait(eth))
110 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
111 (phy_reg << PHY_IAC_REG_SHIFT) |
112 (phy_addr << PHY_IAC_ADDR_SHIFT),
115 if (mtk_mdio_busy_wait(eth))
118 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff;
123 static int mtk_mdio_write(struct mii_bus *bus, int phy_addr,
124 int phy_reg, u16 val)
126 struct mtk_eth *eth = bus->priv;
128 return _mtk_mdio_write(eth, phy_addr, phy_reg, val);
131 static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
133 struct mtk_eth *eth = bus->priv;
135 return _mtk_mdio_read(eth, phy_addr, phy_reg);
138 static void mtk_phy_link_adjust(struct net_device *dev)
140 struct mtk_mac *mac = netdev_priv(dev);
141 u16 lcl_adv = 0, rmt_adv = 0;
143 u32 mcr = MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG |
144 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN |
145 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN |
148 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
151 switch (mac->phy_dev->speed) {
153 mcr |= MAC_MCR_SPEED_1000;
156 mcr |= MAC_MCR_SPEED_100;
160 if (mac->phy_dev->link)
161 mcr |= MAC_MCR_FORCE_LINK;
163 if (mac->phy_dev->duplex) {
164 mcr |= MAC_MCR_FORCE_DPX;
166 if (mac->phy_dev->pause)
167 rmt_adv = LPA_PAUSE_CAP;
168 if (mac->phy_dev->asym_pause)
169 rmt_adv |= LPA_PAUSE_ASYM;
171 if (mac->phy_dev->advertising & ADVERTISED_Pause)
172 lcl_adv |= ADVERTISE_PAUSE_CAP;
173 if (mac->phy_dev->advertising & ADVERTISED_Asym_Pause)
174 lcl_adv |= ADVERTISE_PAUSE_ASYM;
176 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
178 if (flowctrl & FLOW_CTRL_TX)
179 mcr |= MAC_MCR_FORCE_TX_FC;
180 if (flowctrl & FLOW_CTRL_RX)
181 mcr |= MAC_MCR_FORCE_RX_FC;
183 netif_dbg(mac->hw, link, dev, "rx pause %s, tx pause %s\n",
184 flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled",
185 flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled");
188 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
190 if (mac->phy_dev->link)
191 netif_carrier_on(dev);
193 netif_carrier_off(dev);
196 static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac,
197 struct device_node *phy_node)
199 const __be32 *_addr = NULL;
200 struct phy_device *phydev;
203 _addr = of_get_property(phy_node, "reg", NULL);
205 if (!_addr || (be32_to_cpu(*_addr) >= 0x20)) {
206 pr_err("%s: invalid phy address\n", phy_node->name);
209 addr = be32_to_cpu(*_addr);
210 phy_mode = of_get_phy_mode(phy_node);
212 dev_err(eth->dev, "incorrect phy-mode %d\n", phy_mode);
216 phydev = of_phy_connect(eth->netdev[mac->id], phy_node,
217 mtk_phy_link_adjust, 0, phy_mode);
219 dev_err(eth->dev, "could not connect to PHY\n");
224 "connected mac %d to PHY at %s [uid=%08x, driver=%s]\n",
225 mac->id, phydev_name(phydev), phydev->phy_id,
228 mac->phy_dev = phydev;
233 static int mtk_phy_connect(struct mtk_mac *mac)
235 struct mtk_eth *eth = mac->hw;
236 struct device_node *np;
239 np = of_parse_phandle(mac->of_node, "phy-handle", 0);
240 if (!np && of_phy_is_fixed_link(mac->of_node))
241 if (!of_phy_register_fixed_link(mac->of_node))
242 np = of_node_get(mac->of_node);
246 switch (of_get_phy_mode(np)) {
247 case PHY_INTERFACE_MODE_RGMII_TXID:
248 case PHY_INTERFACE_MODE_RGMII_RXID:
249 case PHY_INTERFACE_MODE_RGMII_ID:
250 case PHY_INTERFACE_MODE_RGMII:
253 case PHY_INTERFACE_MODE_MII:
256 case PHY_INTERFACE_MODE_REVMII:
259 case PHY_INTERFACE_MODE_RMII:
268 /* put the gmac into the right mode */
269 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
270 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
271 val |= SYSCFG0_GE_MODE(mac->ge_mode, mac->id);
272 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
274 mtk_phy_connect_node(eth, mac, np);
275 mac->phy_dev->autoneg = AUTONEG_ENABLE;
276 mac->phy_dev->speed = 0;
277 mac->phy_dev->duplex = 0;
279 if (of_phy_is_fixed_link(mac->of_node))
280 mac->phy_dev->supported |=
281 SUPPORTED_Pause | SUPPORTED_Asym_Pause;
283 mac->phy_dev->supported &= PHY_GBIT_FEATURES | SUPPORTED_Pause |
284 SUPPORTED_Asym_Pause;
285 mac->phy_dev->advertising = mac->phy_dev->supported |
287 phy_start_aneg(mac->phy_dev);
295 dev_err(eth->dev, "invalid phy_mode\n");
299 static int mtk_mdio_init(struct mtk_eth *eth)
301 struct device_node *mii_np;
304 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
306 dev_err(eth->dev, "no %s child node found", "mdio-bus");
310 if (!of_device_is_available(mii_np)) {
315 eth->mii_bus = devm_mdiobus_alloc(eth->dev);
321 eth->mii_bus->name = "mdio";
322 eth->mii_bus->read = mtk_mdio_read;
323 eth->mii_bus->write = mtk_mdio_write;
324 eth->mii_bus->priv = eth;
325 eth->mii_bus->parent = eth->dev;
327 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
328 ret = of_mdiobus_register(eth->mii_bus, mii_np);
335 static void mtk_mdio_cleanup(struct mtk_eth *eth)
340 mdiobus_unregister(eth->mii_bus);
343 static inline void mtk_irq_disable(struct mtk_eth *eth,
344 unsigned reg, u32 mask)
349 spin_lock_irqsave(ð->irq_lock, flags);
350 val = mtk_r32(eth, reg);
351 mtk_w32(eth, val & ~mask, reg);
352 spin_unlock_irqrestore(ð->irq_lock, flags);
355 static inline void mtk_irq_enable(struct mtk_eth *eth,
356 unsigned reg, u32 mask)
361 spin_lock_irqsave(ð->irq_lock, flags);
362 val = mtk_r32(eth, reg);
363 mtk_w32(eth, val | mask, reg);
364 spin_unlock_irqrestore(ð->irq_lock, flags);
367 static int mtk_set_mac_address(struct net_device *dev, void *p)
369 int ret = eth_mac_addr(dev, p);
370 struct mtk_mac *mac = netdev_priv(dev);
371 const char *macaddr = dev->dev_addr;
376 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
379 spin_lock_bh(&mac->hw->page_lock);
380 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
381 MTK_GDMA_MAC_ADRH(mac->id));
382 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
383 (macaddr[4] << 8) | macaddr[5],
384 MTK_GDMA_MAC_ADRL(mac->id));
385 spin_unlock_bh(&mac->hw->page_lock);
390 void mtk_stats_update_mac(struct mtk_mac *mac)
392 struct mtk_hw_stats *hw_stats = mac->hw_stats;
393 unsigned int base = MTK_GDM1_TX_GBCNT;
396 base += hw_stats->reg_offset;
398 u64_stats_update_begin(&hw_stats->syncp);
400 hw_stats->rx_bytes += mtk_r32(mac->hw, base);
401 stats = mtk_r32(mac->hw, base + 0x04);
403 hw_stats->rx_bytes += (stats << 32);
404 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08);
405 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10);
406 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14);
407 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18);
408 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c);
409 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20);
410 hw_stats->rx_flow_control_packets +=
411 mtk_r32(mac->hw, base + 0x24);
412 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28);
413 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c);
414 hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30);
415 stats = mtk_r32(mac->hw, base + 0x34);
417 hw_stats->tx_bytes += (stats << 32);
418 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38);
419 u64_stats_update_end(&hw_stats->syncp);
422 static void mtk_stats_update(struct mtk_eth *eth)
426 for (i = 0; i < MTK_MAC_COUNT; i++) {
427 if (!eth->mac[i] || !eth->mac[i]->hw_stats)
429 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) {
430 mtk_stats_update_mac(eth->mac[i]);
431 spin_unlock(ð->mac[i]->hw_stats->stats_lock);
436 static struct rtnl_link_stats64 *mtk_get_stats64(struct net_device *dev,
437 struct rtnl_link_stats64 *storage)
439 struct mtk_mac *mac = netdev_priv(dev);
440 struct mtk_hw_stats *hw_stats = mac->hw_stats;
443 if (netif_running(dev) && netif_device_present(dev)) {
444 if (spin_trylock(&hw_stats->stats_lock)) {
445 mtk_stats_update_mac(mac);
446 spin_unlock(&hw_stats->stats_lock);
451 start = u64_stats_fetch_begin_irq(&hw_stats->syncp);
452 storage->rx_packets = hw_stats->rx_packets;
453 storage->tx_packets = hw_stats->tx_packets;
454 storage->rx_bytes = hw_stats->rx_bytes;
455 storage->tx_bytes = hw_stats->tx_bytes;
456 storage->collisions = hw_stats->tx_collisions;
457 storage->rx_length_errors = hw_stats->rx_short_errors +
458 hw_stats->rx_long_errors;
459 storage->rx_over_errors = hw_stats->rx_overflow;
460 storage->rx_crc_errors = hw_stats->rx_fcs_errors;
461 storage->rx_errors = hw_stats->rx_checksum_errors;
462 storage->tx_aborted_errors = hw_stats->tx_skip;
463 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start));
465 storage->tx_errors = dev->stats.tx_errors;
466 storage->rx_dropped = dev->stats.rx_dropped;
467 storage->tx_dropped = dev->stats.tx_dropped;
472 static inline int mtk_max_frag_size(int mtu)
474 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */
475 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH)
476 mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN;
478 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) +
479 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
482 static inline int mtk_max_buf_size(int frag_size)
484 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
485 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
487 WARN_ON(buf_size < MTK_MAX_RX_LENGTH);
492 static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd,
493 struct mtk_rx_dma *dma_rxd)
495 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
496 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2);
497 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
498 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
501 /* the qdma core needs scratch memory to be setup */
502 static int mtk_init_fq_dma(struct mtk_eth *eth)
504 dma_addr_t phy_ring_tail;
505 int cnt = MTK_DMA_SIZE;
509 eth->scratch_ring = dma_alloc_coherent(eth->dev,
510 cnt * sizeof(struct mtk_tx_dma),
511 ð->phy_scratch_ring,
512 GFP_ATOMIC | __GFP_ZERO);
513 if (unlikely(!eth->scratch_ring))
516 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE,
518 if (unlikely(!eth->scratch_head))
521 dma_addr = dma_map_single(eth->dev,
522 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE,
524 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
527 memset(eth->scratch_ring, 0x0, sizeof(struct mtk_tx_dma) * cnt);
528 phy_ring_tail = eth->phy_scratch_ring +
529 (sizeof(struct mtk_tx_dma) * (cnt - 1));
531 for (i = 0; i < cnt; i++) {
532 eth->scratch_ring[i].txd1 =
533 (dma_addr + (i * MTK_QDMA_PAGE_SIZE));
535 eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring +
536 ((i + 1) * sizeof(struct mtk_tx_dma)));
537 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE);
540 mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD);
541 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL);
542 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT);
543 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN);
548 static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc)
550 void *ret = ring->dma;
552 return ret + (desc - ring->phys);
555 static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring,
556 struct mtk_tx_dma *txd)
558 int idx = txd - ring->dma;
560 return &ring->buf[idx];
563 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf)
565 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) {
566 dma_unmap_single(eth->dev,
567 dma_unmap_addr(tx_buf, dma_addr0),
568 dma_unmap_len(tx_buf, dma_len0),
570 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) {
571 dma_unmap_page(eth->dev,
572 dma_unmap_addr(tx_buf, dma_addr0),
573 dma_unmap_len(tx_buf, dma_len0),
578 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC))
579 dev_kfree_skb_any(tx_buf->skb);
583 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
584 int tx_num, struct mtk_tx_ring *ring, bool gso)
586 struct mtk_mac *mac = netdev_priv(dev);
587 struct mtk_eth *eth = mac->hw;
588 struct mtk_tx_dma *itxd, *txd;
589 struct mtk_tx_buf *tx_buf;
590 dma_addr_t mapped_addr;
591 unsigned int nr_frags;
595 itxd = ring->next_free;
596 if (itxd == ring->last_free)
599 /* set the forward port */
600 fport = (mac->id + 1) << TX_DMA_FPORT_SHIFT;
603 tx_buf = mtk_desc_to_tx_buf(ring, itxd);
604 memset(tx_buf, 0, sizeof(*tx_buf));
609 /* TX Checksum offload */
610 if (skb->ip_summed == CHECKSUM_PARTIAL)
611 txd4 |= TX_DMA_CHKSUM;
613 /* VLAN header offload */
614 if (skb_vlan_tag_present(skb))
615 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb);
617 mapped_addr = dma_map_single(eth->dev, skb->data,
618 skb_headlen(skb), DMA_TO_DEVICE);
619 if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
622 WRITE_ONCE(itxd->txd1, mapped_addr);
623 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
624 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
625 dma_unmap_len_set(tx_buf, dma_len0, skb_headlen(skb));
629 nr_frags = skb_shinfo(skb)->nr_frags;
630 for (i = 0; i < nr_frags; i++) {
631 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
632 unsigned int offset = 0;
633 int frag_size = skb_frag_size(frag);
636 bool last_frag = false;
637 unsigned int frag_map_size;
639 txd = mtk_qdma_phys_to_virt(ring, txd->txd2);
640 if (txd == ring->last_free)
644 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN);
645 mapped_addr = skb_frag_dma_map(eth->dev, frag, offset,
648 if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
651 if (i == nr_frags - 1 &&
652 (frag_size - frag_map_size) == 0)
655 WRITE_ONCE(txd->txd1, mapped_addr);
656 WRITE_ONCE(txd->txd3, (TX_DMA_SWC |
657 TX_DMA_PLEN0(frag_map_size) |
658 last_frag * TX_DMA_LS0));
659 WRITE_ONCE(txd->txd4, fport);
661 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC;
662 tx_buf = mtk_desc_to_tx_buf(ring, txd);
663 memset(tx_buf, 0, sizeof(*tx_buf));
665 tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
666 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
667 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size);
668 frag_size -= frag_map_size;
669 offset += frag_map_size;
673 /* store skb to cleanup */
676 WRITE_ONCE(itxd->txd4, txd4);
677 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) |
678 (!nr_frags * TX_DMA_LS0)));
680 netdev_sent_queue(dev, skb->len);
681 skb_tx_timestamp(skb);
683 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
684 atomic_sub(n_desc, &ring->free_count);
686 /* make sure that all changes to the dma ring are flushed before we
691 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more)
692 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR);
698 tx_buf = mtk_desc_to_tx_buf(ring, itxd);
701 mtk_tx_unmap(eth, tx_buf);
703 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
704 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2);
705 } while (itxd != txd);
710 static inline int mtk_cal_txd_req(struct sk_buff *skb)
713 struct skb_frag_struct *frag;
716 if (skb_is_gso(skb)) {
717 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
718 frag = &skb_shinfo(skb)->frags[i];
719 nfrags += DIV_ROUND_UP(frag->size, MTK_TX_DMA_BUF_LEN);
722 nfrags += skb_shinfo(skb)->nr_frags;
728 static int mtk_queue_stopped(struct mtk_eth *eth)
732 for (i = 0; i < MTK_MAC_COUNT; i++) {
735 if (netif_queue_stopped(eth->netdev[i]))
742 static void mtk_wake_queue(struct mtk_eth *eth)
746 for (i = 0; i < MTK_MAC_COUNT; i++) {
749 netif_wake_queue(eth->netdev[i]);
753 static void mtk_stop_queue(struct mtk_eth *eth)
757 for (i = 0; i < MTK_MAC_COUNT; i++) {
760 netif_stop_queue(eth->netdev[i]);
764 static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
766 struct mtk_mac *mac = netdev_priv(dev);
767 struct mtk_eth *eth = mac->hw;
768 struct mtk_tx_ring *ring = ð->tx_ring;
769 struct net_device_stats *stats = &dev->stats;
773 /* normally we can rely on the stack not calling this more than once,
774 * however we have 2 queues running on the same ring so we need to lock
777 spin_lock(ð->page_lock);
779 if (unlikely(test_bit(MTK_RESETTING, ð->state)))
782 tx_num = mtk_cal_txd_req(skb);
783 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) {
785 netif_err(eth, tx_queued, dev,
786 "Tx Ring full when queue awake!\n");
787 spin_unlock(ð->page_lock);
788 return NETDEV_TX_BUSY;
791 /* TSO: fill MSS info in tcp checksum field */
792 if (skb_is_gso(skb)) {
793 if (skb_cow_head(skb, 0)) {
794 netif_warn(eth, tx_err, dev,
795 "GSO expand head fail.\n");
799 if (skb_shinfo(skb)->gso_type &
800 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
802 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
806 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0)
809 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh))
812 spin_unlock(ð->page_lock);
817 spin_unlock(ð->page_lock);
823 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth)
826 struct mtk_rx_ring *ring;
830 return ð->rx_ring[0];
832 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) {
833 ring = ð->rx_ring[i];
834 idx = NEXT_RX_DESP_IDX(ring->calc_idx, ring->dma_size);
835 if (ring->dma[idx].rxd2 & RX_DMA_DONE) {
836 ring->calc_idx_update = true;
844 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth)
846 struct mtk_rx_ring *ring;
850 ring = ð->rx_ring[0];
851 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
853 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) {
854 ring = ð->rx_ring[i];
855 if (ring->calc_idx_update) {
856 ring->calc_idx_update = false;
857 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
863 static int mtk_poll_rx(struct napi_struct *napi, int budget,
866 struct mtk_rx_ring *ring;
870 struct mtk_rx_dma *rxd, trxd;
873 while (done < budget) {
874 struct net_device *netdev;
879 ring = mtk_get_rx_ring(eth);
883 idx = NEXT_RX_DESP_IDX(ring->calc_idx, ring->dma_size);
884 rxd = &ring->dma[idx];
885 data = ring->data[idx];
887 mtk_rx_get_desc(&trxd, rxd);
888 if (!(trxd.rxd2 & RX_DMA_DONE))
891 /* find out which mac the packet come from. values start at 1 */
892 mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
896 netdev = eth->netdev[mac];
898 if (unlikely(test_bit(MTK_RESETTING, ð->state)))
901 /* alloc new buffer */
902 new_data = napi_alloc_frag(ring->frag_size);
903 if (unlikely(!new_data)) {
904 netdev->stats.rx_dropped++;
907 dma_addr = dma_map_single(eth->dev,
908 new_data + NET_SKB_PAD,
911 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) {
912 skb_free_frag(new_data);
913 netdev->stats.rx_dropped++;
918 skb = build_skb(data, ring->frag_size);
919 if (unlikely(!skb)) {
920 skb_free_frag(new_data);
921 netdev->stats.rx_dropped++;
924 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
926 dma_unmap_single(eth->dev, trxd.rxd1,
927 ring->buf_size, DMA_FROM_DEVICE);
928 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
930 skb_put(skb, pktlen);
931 if (trxd.rxd4 & RX_DMA_L4_VALID)
932 skb->ip_summed = CHECKSUM_UNNECESSARY;
934 skb_checksum_none_assert(skb);
935 skb->protocol = eth_type_trans(skb, netdev);
937 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&
938 RX_DMA_VID(trxd.rxd3))
939 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
940 RX_DMA_VID(trxd.rxd3));
941 napi_gro_receive(napi, skb);
943 ring->data[idx] = new_data;
944 rxd->rxd1 = (unsigned int)dma_addr;
947 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size);
949 ring->calc_idx = idx;
956 /* make sure that all changes to the dma ring are flushed before
960 mtk_update_rx_cpu_idx(eth);
966 static int mtk_poll_tx(struct mtk_eth *eth, int budget)
968 struct mtk_tx_ring *ring = ð->tx_ring;
969 struct mtk_tx_dma *desc;
971 struct mtk_tx_buf *tx_buf;
972 unsigned int done[MTK_MAX_DEVS];
973 unsigned int bytes[MTK_MAX_DEVS];
975 static int condition;
978 memset(done, 0, sizeof(done));
979 memset(bytes, 0, sizeof(bytes));
981 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR);
982 dma = mtk_r32(eth, MTK_QTX_DRX_PTR);
984 desc = mtk_qdma_phys_to_virt(ring, cpu);
986 while ((cpu != dma) && budget) {
987 u32 next_cpu = desc->txd2;
990 desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
991 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
994 mac = (desc->txd4 >> TX_DMA_FPORT_SHIFT) &
998 tx_buf = mtk_desc_to_tx_buf(ring, desc);
1005 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) {
1006 bytes[mac] += skb->len;
1010 mtk_tx_unmap(eth, tx_buf);
1012 ring->last_free = desc;
1013 atomic_inc(&ring->free_count);
1018 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR);
1020 for (i = 0; i < MTK_MAC_COUNT; i++) {
1021 if (!eth->netdev[i] || !done[i])
1023 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]);
1027 if (mtk_queue_stopped(eth) &&
1028 (atomic_read(&ring->free_count) > ring->thresh))
1029 mtk_wake_queue(eth);
1034 static void mtk_handle_status_irq(struct mtk_eth *eth)
1036 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2);
1038 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) {
1039 mtk_stats_update(eth);
1040 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF),
1045 static int mtk_napi_tx(struct napi_struct *napi, int budget)
1047 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi);
1051 mtk_handle_status_irq(eth);
1052 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QMTK_INT_STATUS);
1053 tx_done = mtk_poll_tx(eth, budget);
1055 if (unlikely(netif_msg_intr(eth))) {
1056 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
1057 mask = mtk_r32(eth, MTK_QDMA_INT_MASK);
1059 "done tx %d, intr 0x%08x/0x%x\n",
1060 tx_done, status, mask);
1063 if (tx_done == budget)
1066 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
1067 if (status & MTK_TX_DONE_INT)
1070 napi_complete(napi);
1071 mtk_irq_enable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
1076 static int mtk_napi_rx(struct napi_struct *napi, int budget)
1078 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);
1081 int remain_budget = budget;
1083 mtk_handle_status_irq(eth);
1086 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS);
1087 rx_done = mtk_poll_rx(napi, remain_budget, eth);
1089 if (unlikely(netif_msg_intr(eth))) {
1090 status = mtk_r32(eth, MTK_PDMA_INT_STATUS);
1091 mask = mtk_r32(eth, MTK_PDMA_INT_MASK);
1093 "done rx %d, intr 0x%08x/0x%x\n",
1094 rx_done, status, mask);
1096 if (rx_done == remain_budget)
1099 status = mtk_r32(eth, MTK_PDMA_INT_STATUS);
1100 if (status & MTK_RX_DONE_INT) {
1101 remain_budget -= rx_done;
1104 napi_complete(napi);
1105 mtk_irq_enable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
1107 return rx_done + budget - remain_budget;
1110 static int mtk_tx_alloc(struct mtk_eth *eth)
1112 struct mtk_tx_ring *ring = ð->tx_ring;
1113 int i, sz = sizeof(*ring->dma);
1115 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf),
1120 ring->dma = dma_alloc_coherent(eth->dev,
1123 GFP_ATOMIC | __GFP_ZERO);
1127 memset(ring->dma, 0, MTK_DMA_SIZE * sz);
1128 for (i = 0; i < MTK_DMA_SIZE; i++) {
1129 int next = (i + 1) % MTK_DMA_SIZE;
1130 u32 next_ptr = ring->phys + next * sz;
1132 ring->dma[i].txd2 = next_ptr;
1133 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
1136 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2);
1137 ring->next_free = &ring->dma[0];
1138 ring->last_free = &ring->dma[MTK_DMA_SIZE - 1];
1139 ring->thresh = MAX_SKB_FRAGS;
1141 /* make sure that all changes to the dma ring are flushed before we
1146 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR);
1147 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR);
1149 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1152 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1154 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, MTK_QTX_CFG(0));
1162 static void mtk_tx_clean(struct mtk_eth *eth)
1164 struct mtk_tx_ring *ring = ð->tx_ring;
1168 for (i = 0; i < MTK_DMA_SIZE; i++)
1169 mtk_tx_unmap(eth, &ring->buf[i]);
1175 dma_free_coherent(eth->dev,
1176 MTK_DMA_SIZE * sizeof(*ring->dma),
1183 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag)
1185 struct mtk_rx_ring *ring = ð->rx_ring[ring_no];
1186 int rx_data_len, rx_dma_size;
1189 if (rx_flag == MTK_RX_FLAGS_HWLRO) {
1190 rx_data_len = MTK_MAX_LRO_RX_LENGTH;
1191 rx_dma_size = MTK_HW_LRO_DMA_SIZE;
1193 rx_data_len = ETH_DATA_LEN;
1194 rx_dma_size = MTK_DMA_SIZE;
1197 ring->frag_size = mtk_max_frag_size(rx_data_len);
1198 ring->buf_size = mtk_max_buf_size(ring->frag_size);
1199 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data),
1204 for (i = 0; i < rx_dma_size; i++) {
1205 ring->data[i] = netdev_alloc_frag(ring->frag_size);
1210 ring->dma = dma_alloc_coherent(eth->dev,
1211 rx_dma_size * sizeof(*ring->dma),
1213 GFP_ATOMIC | __GFP_ZERO);
1217 for (i = 0; i < rx_dma_size; i++) {
1218 dma_addr_t dma_addr = dma_map_single(eth->dev,
1219 ring->data[i] + NET_SKB_PAD,
1222 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
1224 ring->dma[i].rxd1 = (unsigned int)dma_addr;
1226 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size);
1228 ring->dma_size = rx_dma_size;
1229 ring->calc_idx_update = false;
1230 ring->calc_idx = rx_dma_size - 1;
1231 ring->crx_idx_reg = MTK_PRX_CRX_IDX_CFG(ring_no);
1232 /* make sure that all changes to the dma ring are flushed before we
1237 mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no));
1238 mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no));
1239 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
1240 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX);
1245 static void mtk_rx_clean(struct mtk_eth *eth, int ring_no)
1247 struct mtk_rx_ring *ring = ð->rx_ring[ring_no];
1250 if (ring->data && ring->dma) {
1251 for (i = 0; i < ring->dma_size; i++) {
1254 if (!ring->dma[i].rxd1)
1256 dma_unmap_single(eth->dev,
1260 skb_free_frag(ring->data[i]);
1267 dma_free_coherent(eth->dev,
1268 ring->dma_size * sizeof(*ring->dma),
1275 static int mtk_hwlro_rx_init(struct mtk_eth *eth)
1278 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0;
1279 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0;
1281 /* set LRO rings to auto-learn modes */
1282 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE;
1284 /* validate LRO ring */
1285 ring_ctrl_dw2 |= MTK_RING_VLD;
1287 /* set AGE timer (unit: 20us) */
1288 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H;
1289 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L;
1291 /* set max AGG timer (unit: 20us) */
1292 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME;
1294 /* set max LRO AGG count */
1295 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L;
1296 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H;
1298 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
1299 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i));
1300 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i));
1301 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i));
1304 /* IPv4 checksum update enable */
1305 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN;
1307 /* switch priority comparison to packet count mode */
1308 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE;
1310 /* bandwidth threshold setting */
1311 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2);
1313 /* auto-learn score delta setting */
1314 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA);
1316 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */
1317 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME,
1318 MTK_PDMA_LRO_ALT_REFRESH_TIMER);
1320 /* set HW LRO mode & the max aggregation count for rx packets */
1321 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff);
1323 /* the minimal remaining room of SDL0 in RXD for lro aggregation */
1324 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL;
1327 lro_ctrl_dw0 |= MTK_LRO_EN;
1329 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3);
1330 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0);
1335 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth)
1340 /* relinquish lro rings, flush aggregated packets */
1341 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0);
1343 /* wait for relinquishments done */
1344 for (i = 0; i < 10; i++) {
1345 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0);
1346 if (val & MTK_LRO_RING_RELINQUISH_DONE) {
1352 /* invalidate lro rings */
1353 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
1354 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i));
1356 /* disable HW LRO */
1357 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0);
1360 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip)
1364 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
1366 /* invalidate the IP setting */
1367 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1369 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx));
1371 /* validate the IP setting */
1372 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1375 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx)
1379 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
1381 /* invalidate the IP setting */
1382 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1384 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx));
1387 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac)
1392 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
1393 if (mac->hwlro_ip[i])
1400 static int mtk_hwlro_add_ipaddr(struct net_device *dev,
1401 struct ethtool_rxnfc *cmd)
1403 struct ethtool_rx_flow_spec *fsp =
1404 (struct ethtool_rx_flow_spec *)&cmd->fs;
1405 struct mtk_mac *mac = netdev_priv(dev);
1406 struct mtk_eth *eth = mac->hw;
1409 if ((fsp->flow_type != TCP_V4_FLOW) ||
1410 (!fsp->h_u.tcp_ip4_spec.ip4dst) ||
1411 (fsp->location > 1))
1414 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst);
1415 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
1417 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
1419 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]);
1424 static int mtk_hwlro_del_ipaddr(struct net_device *dev,
1425 struct ethtool_rxnfc *cmd)
1427 struct ethtool_rx_flow_spec *fsp =
1428 (struct ethtool_rx_flow_spec *)&cmd->fs;
1429 struct mtk_mac *mac = netdev_priv(dev);
1430 struct mtk_eth *eth = mac->hw;
1433 if (fsp->location > 1)
1436 mac->hwlro_ip[fsp->location] = 0;
1437 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
1439 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
1441 mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
1446 static void mtk_hwlro_netdev_disable(struct net_device *dev)
1448 struct mtk_mac *mac = netdev_priv(dev);
1449 struct mtk_eth *eth = mac->hw;
1452 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
1453 mac->hwlro_ip[i] = 0;
1454 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i;
1456 mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
1459 mac->hwlro_ip_cnt = 0;
1462 static int mtk_hwlro_get_fdir_entry(struct net_device *dev,
1463 struct ethtool_rxnfc *cmd)
1465 struct mtk_mac *mac = netdev_priv(dev);
1466 struct ethtool_rx_flow_spec *fsp =
1467 (struct ethtool_rx_flow_spec *)&cmd->fs;
1469 /* only tcp dst ipv4 is meaningful, others are meaningless */
1470 fsp->flow_type = TCP_V4_FLOW;
1471 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]);
1472 fsp->m_u.tcp_ip4_spec.ip4dst = 0;
1474 fsp->h_u.tcp_ip4_spec.ip4src = 0;
1475 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff;
1476 fsp->h_u.tcp_ip4_spec.psrc = 0;
1477 fsp->m_u.tcp_ip4_spec.psrc = 0xffff;
1478 fsp->h_u.tcp_ip4_spec.pdst = 0;
1479 fsp->m_u.tcp_ip4_spec.pdst = 0xffff;
1480 fsp->h_u.tcp_ip4_spec.tos = 0;
1481 fsp->m_u.tcp_ip4_spec.tos = 0xff;
1486 static int mtk_hwlro_get_fdir_all(struct net_device *dev,
1487 struct ethtool_rxnfc *cmd,
1490 struct mtk_mac *mac = netdev_priv(dev);
1494 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
1495 if (mac->hwlro_ip[i]) {
1501 cmd->rule_cnt = cnt;
1506 static netdev_features_t mtk_fix_features(struct net_device *dev,
1507 netdev_features_t features)
1509 if (!(features & NETIF_F_LRO)) {
1510 struct mtk_mac *mac = netdev_priv(dev);
1511 int ip_cnt = mtk_hwlro_get_ip_cnt(mac);
1514 netdev_info(dev, "RX flow is programmed, LRO should keep on\n");
1516 features |= NETIF_F_LRO;
1523 static int mtk_set_features(struct net_device *dev, netdev_features_t features)
1527 if (!((dev->features ^ features) & NETIF_F_LRO))
1530 if (!(features & NETIF_F_LRO))
1531 mtk_hwlro_netdev_disable(dev);
1536 /* wait for DMA to finish whatever it is doing before we start using it again */
1537 static int mtk_dma_busy_wait(struct mtk_eth *eth)
1539 unsigned long t_start = jiffies;
1542 if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) &
1543 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)))
1545 if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT))
1549 dev_err(eth->dev, "DMA init timeout\n");
1553 static int mtk_dma_init(struct mtk_eth *eth)
1558 if (mtk_dma_busy_wait(eth))
1561 /* QDMA needs scratch memory for internal reordering of the
1564 err = mtk_init_fq_dma(eth);
1568 err = mtk_tx_alloc(eth);
1572 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL);
1577 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
1578 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO);
1582 err = mtk_hwlro_rx_init(eth);
1587 /* Enable random early drop and set drop threshold automatically */
1588 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | FC_THRES_MIN,
1590 mtk_w32(eth, 0x0, MTK_QDMA_HRED2);
1595 static void mtk_dma_free(struct mtk_eth *eth)
1599 for (i = 0; i < MTK_MAC_COUNT; i++)
1601 netdev_reset_queue(eth->netdev[i]);
1602 if (eth->scratch_ring) {
1603 dma_free_coherent(eth->dev,
1604 MTK_DMA_SIZE * sizeof(struct mtk_tx_dma),
1606 eth->phy_scratch_ring);
1607 eth->scratch_ring = NULL;
1608 eth->phy_scratch_ring = 0;
1611 mtk_rx_clean(eth, 0);
1614 mtk_hwlro_rx_uninit(eth);
1615 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
1616 mtk_rx_clean(eth, i);
1619 kfree(eth->scratch_head);
1622 static void mtk_tx_timeout(struct net_device *dev)
1624 struct mtk_mac *mac = netdev_priv(dev);
1625 struct mtk_eth *eth = mac->hw;
1627 eth->netdev[mac->id]->stats.tx_errors++;
1628 netif_err(eth, tx_err, dev,
1629 "transmit timed out\n");
1630 schedule_work(ð->pending_work);
1633 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth)
1635 struct mtk_eth *eth = _eth;
1637 if (likely(napi_schedule_prep(ð->rx_napi))) {
1638 __napi_schedule(ð->rx_napi);
1639 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
1645 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth)
1647 struct mtk_eth *eth = _eth;
1649 if (likely(napi_schedule_prep(ð->tx_napi))) {
1650 __napi_schedule(ð->tx_napi);
1651 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
1657 #ifdef CONFIG_NET_POLL_CONTROLLER
1658 static void mtk_poll_controller(struct net_device *dev)
1660 struct mtk_mac *mac = netdev_priv(dev);
1661 struct mtk_eth *eth = mac->hw;
1663 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
1664 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
1665 mtk_handle_irq_rx(eth->irq[2], dev);
1666 mtk_irq_enable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
1667 mtk_irq_enable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
1671 static int mtk_start_dma(struct mtk_eth *eth)
1675 err = mtk_dma_init(eth);
1682 MTK_TX_WB_DDONE | MTK_TX_DMA_EN |
1683 MTK_DMA_SIZE_16DWORDS | MTK_NDP_CO_PRO,
1687 MTK_RX_DMA_EN | MTK_RX_2B_OFFSET |
1688 MTK_RX_BT_32DWORDS | MTK_MULTI_EN,
1694 static int mtk_open(struct net_device *dev)
1696 struct mtk_mac *mac = netdev_priv(dev);
1697 struct mtk_eth *eth = mac->hw;
1699 /* we run 2 netdevs on the same dma ring so we only bring it up once */
1700 if (!atomic_read(ð->dma_refcnt)) {
1701 int err = mtk_start_dma(eth);
1706 napi_enable(ð->tx_napi);
1707 napi_enable(ð->rx_napi);
1708 mtk_irq_enable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
1709 mtk_irq_enable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
1711 atomic_inc(ð->dma_refcnt);
1713 phy_start(mac->phy_dev);
1714 netif_start_queue(dev);
1719 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg)
1724 /* stop the dma engine */
1725 spin_lock_bh(ð->page_lock);
1726 val = mtk_r32(eth, glo_cfg);
1727 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN),
1729 spin_unlock_bh(ð->page_lock);
1731 /* wait for dma stop */
1732 for (i = 0; i < 10; i++) {
1733 val = mtk_r32(eth, glo_cfg);
1734 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) {
1742 static int mtk_stop(struct net_device *dev)
1744 struct mtk_mac *mac = netdev_priv(dev);
1745 struct mtk_eth *eth = mac->hw;
1747 netif_tx_disable(dev);
1748 phy_stop(mac->phy_dev);
1750 /* only shutdown DMA if this is the last user */
1751 if (!atomic_dec_and_test(ð->dma_refcnt))
1754 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
1755 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
1756 napi_disable(ð->tx_napi);
1757 napi_disable(ð->rx_napi);
1759 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG);
1766 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits)
1768 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
1772 usleep_range(1000, 1100);
1773 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
1779 static int mtk_hw_init(struct mtk_eth *eth)
1783 if (test_and_set_bit(MTK_HW_INIT, ð->state))
1786 pm_runtime_enable(eth->dev);
1787 pm_runtime_get_sync(eth->dev);
1789 clk_prepare_enable(eth->clks[MTK_CLK_ETHIF]);
1790 clk_prepare_enable(eth->clks[MTK_CLK_ESW]);
1791 clk_prepare_enable(eth->clks[MTK_CLK_GP1]);
1792 clk_prepare_enable(eth->clks[MTK_CLK_GP2]);
1793 ethsys_reset(eth, RSTCTRL_FE);
1794 ethsys_reset(eth, RSTCTRL_PPE);
1796 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
1797 for (i = 0; i < MTK_MAC_COUNT; i++) {
1800 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, eth->mac[i]->id);
1801 val |= SYSCFG0_GE_MODE(eth->mac[i]->ge_mode, eth->mac[i]->id);
1803 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
1805 /* Set GE2 driving and slew rate */
1806 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
1809 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
1812 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
1814 /* GE1, Force 1000M/FD, FC ON */
1815 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(0));
1817 /* GE2, Force 1000M/FD, FC ON */
1818 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(1));
1820 /* Enable RX VLan Offloading */
1821 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
1823 /* disable delay and normal interrupt */
1824 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
1825 mtk_w32(eth, 0, MTK_PDMA_DELAY_INT);
1826 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, ~0);
1827 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, ~0);
1828 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
1829 mtk_w32(eth, 0, MTK_RST_GL);
1831 /* FE int grouping */
1832 mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1);
1833 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2);
1834 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1);
1835 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2);
1836 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
1838 for (i = 0; i < 2; i++) {
1839 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
1841 /* setup the forward port to send frame to PDMA */
1844 /* Enable RX checksum */
1845 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
1847 /* setup the mac dma */
1848 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
1854 static int mtk_hw_deinit(struct mtk_eth *eth)
1856 if (!test_and_clear_bit(MTK_HW_INIT, ð->state))
1859 clk_disable_unprepare(eth->clks[MTK_CLK_GP2]);
1860 clk_disable_unprepare(eth->clks[MTK_CLK_GP1]);
1861 clk_disable_unprepare(eth->clks[MTK_CLK_ESW]);
1862 clk_disable_unprepare(eth->clks[MTK_CLK_ETHIF]);
1864 pm_runtime_put_sync(eth->dev);
1865 pm_runtime_disable(eth->dev);
1870 static int __init mtk_init(struct net_device *dev)
1872 struct mtk_mac *mac = netdev_priv(dev);
1873 struct mtk_eth *eth = mac->hw;
1874 const char *mac_addr;
1876 mac_addr = of_get_mac_address(mac->of_node);
1878 ether_addr_copy(dev->dev_addr, mac_addr);
1880 /* If the mac address is invalid, use random mac address */
1881 if (!is_valid_ether_addr(dev->dev_addr)) {
1882 random_ether_addr(dev->dev_addr);
1883 dev_err(eth->dev, "generated random MAC address %pM\n",
1885 dev->addr_assign_type = NET_ADDR_RANDOM;
1888 return mtk_phy_connect(mac);
1891 static void mtk_uninit(struct net_device *dev)
1893 struct mtk_mac *mac = netdev_priv(dev);
1894 struct mtk_eth *eth = mac->hw;
1896 phy_disconnect(mac->phy_dev);
1897 mtk_mdio_cleanup(eth);
1898 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, ~0);
1899 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, ~0);
1900 free_irq(eth->irq[1], dev);
1901 free_irq(eth->irq[2], dev);
1904 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1906 struct mtk_mac *mac = netdev_priv(dev);
1912 return phy_mii_ioctl(mac->phy_dev, ifr, cmd);
1920 static void mtk_pending_work(struct work_struct *work)
1922 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work);
1924 unsigned long restart = 0;
1928 dev_dbg(eth->dev, "[%s][%d] reset\n", __func__, __LINE__);
1930 while (test_and_set_bit_lock(MTK_RESETTING, ð->state))
1933 dev_dbg(eth->dev, "[%s][%d] mtk_stop starts\n", __func__, __LINE__);
1934 /* stop all devices to make sure that dma is properly shut down */
1935 for (i = 0; i < MTK_MAC_COUNT; i++) {
1936 if (!eth->netdev[i])
1938 mtk_stop(eth->netdev[i]);
1939 __set_bit(i, &restart);
1941 dev_dbg(eth->dev, "[%s][%d] mtk_stop ends\n", __func__, __LINE__);
1943 /* restart underlying hardware such as power, clock, pin mux
1944 * and the connected phy
1949 pinctrl_select_state(eth->dev->pins->p,
1950 eth->dev->pins->default_state);
1953 for (i = 0; i < MTK_MAC_COUNT; i++) {
1955 of_phy_is_fixed_link(eth->mac[i]->of_node))
1957 err = phy_init_hw(eth->mac[i]->phy_dev);
1959 dev_err(eth->dev, "%s: PHY init failed.\n",
1960 eth->netdev[i]->name);
1963 /* restart DMA and enable IRQs */
1964 for (i = 0; i < MTK_MAC_COUNT; i++) {
1965 if (!test_bit(i, &restart))
1967 err = mtk_open(eth->netdev[i]);
1969 netif_alert(eth, ifup, eth->netdev[i],
1970 "Driver up/down cycle failed, closing device.\n");
1971 dev_close(eth->netdev[i]);
1975 dev_dbg(eth->dev, "[%s][%d] reset done\n", __func__, __LINE__);
1977 clear_bit_unlock(MTK_RESETTING, ð->state);
1982 static int mtk_free_dev(struct mtk_eth *eth)
1986 for (i = 0; i < MTK_MAC_COUNT; i++) {
1987 if (!eth->netdev[i])
1989 free_netdev(eth->netdev[i]);
1995 static int mtk_unreg_dev(struct mtk_eth *eth)
1999 for (i = 0; i < MTK_MAC_COUNT; i++) {
2000 if (!eth->netdev[i])
2002 unregister_netdev(eth->netdev[i]);
2008 static int mtk_cleanup(struct mtk_eth *eth)
2012 cancel_work_sync(ð->pending_work);
2017 static int mtk_get_settings(struct net_device *dev,
2018 struct ethtool_cmd *cmd)
2020 struct mtk_mac *mac = netdev_priv(dev);
2023 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2026 err = phy_read_status(mac->phy_dev);
2030 return phy_ethtool_gset(mac->phy_dev, cmd);
2033 static int mtk_set_settings(struct net_device *dev,
2034 struct ethtool_cmd *cmd)
2036 struct mtk_mac *mac = netdev_priv(dev);
2038 if (cmd->phy_address != mac->phy_dev->mdio.addr) {
2039 mac->phy_dev = mdiobus_get_phy(mac->hw->mii_bus,
2045 return phy_ethtool_sset(mac->phy_dev, cmd);
2048 static void mtk_get_drvinfo(struct net_device *dev,
2049 struct ethtool_drvinfo *info)
2051 struct mtk_mac *mac = netdev_priv(dev);
2053 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver));
2054 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info));
2055 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats);
2058 static u32 mtk_get_msglevel(struct net_device *dev)
2060 struct mtk_mac *mac = netdev_priv(dev);
2062 return mac->hw->msg_enable;
2065 static void mtk_set_msglevel(struct net_device *dev, u32 value)
2067 struct mtk_mac *mac = netdev_priv(dev);
2069 mac->hw->msg_enable = value;
2072 static int mtk_nway_reset(struct net_device *dev)
2074 struct mtk_mac *mac = netdev_priv(dev);
2076 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2079 return genphy_restart_aneg(mac->phy_dev);
2082 static u32 mtk_get_link(struct net_device *dev)
2084 struct mtk_mac *mac = netdev_priv(dev);
2087 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2090 err = genphy_update_link(mac->phy_dev);
2092 return ethtool_op_get_link(dev);
2094 return mac->phy_dev->link;
2097 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2101 switch (stringset) {
2103 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) {
2104 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN);
2105 data += ETH_GSTRING_LEN;
2111 static int mtk_get_sset_count(struct net_device *dev, int sset)
2115 return ARRAY_SIZE(mtk_ethtool_stats);
2121 static void mtk_get_ethtool_stats(struct net_device *dev,
2122 struct ethtool_stats *stats, u64 *data)
2124 struct mtk_mac *mac = netdev_priv(dev);
2125 struct mtk_hw_stats *hwstats = mac->hw_stats;
2126 u64 *data_src, *data_dst;
2130 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2133 if (netif_running(dev) && netif_device_present(dev)) {
2134 if (spin_trylock(&hwstats->stats_lock)) {
2135 mtk_stats_update_mac(mac);
2136 spin_unlock(&hwstats->stats_lock);
2141 data_src = (u64 *)hwstats;
2143 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
2145 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++)
2146 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset);
2147 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
2150 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
2153 int ret = -EOPNOTSUPP;
2156 case ETHTOOL_GRXRINGS:
2157 if (dev->features & NETIF_F_LRO) {
2158 cmd->data = MTK_MAX_RX_RING_NUM;
2162 case ETHTOOL_GRXCLSRLCNT:
2163 if (dev->features & NETIF_F_LRO) {
2164 struct mtk_mac *mac = netdev_priv(dev);
2166 cmd->rule_cnt = mac->hwlro_ip_cnt;
2170 case ETHTOOL_GRXCLSRULE:
2171 if (dev->features & NETIF_F_LRO)
2172 ret = mtk_hwlro_get_fdir_entry(dev, cmd);
2174 case ETHTOOL_GRXCLSRLALL:
2175 if (dev->features & NETIF_F_LRO)
2176 ret = mtk_hwlro_get_fdir_all(dev, cmd,
2186 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2188 int ret = -EOPNOTSUPP;
2191 case ETHTOOL_SRXCLSRLINS:
2192 if (dev->features & NETIF_F_LRO)
2193 ret = mtk_hwlro_add_ipaddr(dev, cmd);
2195 case ETHTOOL_SRXCLSRLDEL:
2196 if (dev->features & NETIF_F_LRO)
2197 ret = mtk_hwlro_del_ipaddr(dev, cmd);
2206 static const struct ethtool_ops mtk_ethtool_ops = {
2207 .get_settings = mtk_get_settings,
2208 .set_settings = mtk_set_settings,
2209 .get_drvinfo = mtk_get_drvinfo,
2210 .get_msglevel = mtk_get_msglevel,
2211 .set_msglevel = mtk_set_msglevel,
2212 .nway_reset = mtk_nway_reset,
2213 .get_link = mtk_get_link,
2214 .get_strings = mtk_get_strings,
2215 .get_sset_count = mtk_get_sset_count,
2216 .get_ethtool_stats = mtk_get_ethtool_stats,
2217 .get_rxnfc = mtk_get_rxnfc,
2218 .set_rxnfc = mtk_set_rxnfc,
2221 static const struct net_device_ops mtk_netdev_ops = {
2222 .ndo_init = mtk_init,
2223 .ndo_uninit = mtk_uninit,
2224 .ndo_open = mtk_open,
2225 .ndo_stop = mtk_stop,
2226 .ndo_start_xmit = mtk_start_xmit,
2227 .ndo_set_mac_address = mtk_set_mac_address,
2228 .ndo_validate_addr = eth_validate_addr,
2229 .ndo_do_ioctl = mtk_do_ioctl,
2230 .ndo_change_mtu = eth_change_mtu,
2231 .ndo_tx_timeout = mtk_tx_timeout,
2232 .ndo_get_stats64 = mtk_get_stats64,
2233 .ndo_fix_features = mtk_fix_features,
2234 .ndo_set_features = mtk_set_features,
2235 #ifdef CONFIG_NET_POLL_CONTROLLER
2236 .ndo_poll_controller = mtk_poll_controller,
2240 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
2242 struct mtk_mac *mac;
2243 const __be32 *_id = of_get_property(np, "reg", NULL);
2247 dev_err(eth->dev, "missing mac id\n");
2251 id = be32_to_cpup(_id);
2252 if (id >= MTK_MAC_COUNT) {
2253 dev_err(eth->dev, "%d is not a valid mac id\n", id);
2257 if (eth->netdev[id]) {
2258 dev_err(eth->dev, "duplicate mac id found: %d\n", id);
2262 eth->netdev[id] = alloc_etherdev(sizeof(*mac));
2263 if (!eth->netdev[id]) {
2264 dev_err(eth->dev, "alloc_etherdev failed\n");
2267 mac = netdev_priv(eth->netdev[id]);
2273 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip));
2274 mac->hwlro_ip_cnt = 0;
2276 mac->hw_stats = devm_kzalloc(eth->dev,
2277 sizeof(*mac->hw_stats),
2279 if (!mac->hw_stats) {
2280 dev_err(eth->dev, "failed to allocate counter memory\n");
2284 spin_lock_init(&mac->hw_stats->stats_lock);
2285 u64_stats_init(&mac->hw_stats->syncp);
2286 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
2288 SET_NETDEV_DEV(eth->netdev[id], eth->dev);
2289 eth->netdev[id]->watchdog_timeo = 5 * HZ;
2290 eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
2291 eth->netdev[id]->base_addr = (unsigned long)eth->base;
2293 eth->netdev[id]->hw_features = MTK_HW_FEATURES;
2295 eth->netdev[id]->hw_features |= NETIF_F_LRO;
2297 eth->netdev[id]->vlan_features = MTK_HW_FEATURES &
2298 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
2299 eth->netdev[id]->features |= MTK_HW_FEATURES;
2300 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops;
2302 eth->netdev[id]->irq = eth->irq[0];
2306 free_netdev(eth->netdev[id]);
2310 static int mtk_probe(struct platform_device *pdev)
2312 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2313 struct device_node *mac_np;
2314 const struct of_device_id *match;
2315 struct mtk_soc_data *soc;
2316 struct mtk_eth *eth;
2320 match = of_match_device(of_mtk_match, &pdev->dev);
2321 soc = (struct mtk_soc_data *)match->data;
2323 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL);
2327 eth->dev = &pdev->dev;
2328 eth->base = devm_ioremap_resource(&pdev->dev, res);
2329 if (IS_ERR(eth->base))
2330 return PTR_ERR(eth->base);
2332 spin_lock_init(ð->page_lock);
2333 spin_lock_init(ð->irq_lock);
2335 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2337 if (IS_ERR(eth->ethsys)) {
2338 dev_err(&pdev->dev, "no ethsys regmap found\n");
2339 return PTR_ERR(eth->ethsys);
2342 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2344 if (IS_ERR(eth->pctl)) {
2345 dev_err(&pdev->dev, "no pctl regmap found\n");
2346 return PTR_ERR(eth->pctl);
2349 eth->hwlro = of_property_read_bool(pdev->dev.of_node, "mediatek,hwlro");
2351 for (i = 0; i < 3; i++) {
2352 eth->irq[i] = platform_get_irq(pdev, i);
2353 if (eth->irq[i] < 0) {
2354 dev_err(&pdev->dev, "no IRQ%d resource found\n", i);
2358 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) {
2359 eth->clks[i] = devm_clk_get(eth->dev,
2360 mtk_clks_source_name[i]);
2361 if (IS_ERR(eth->clks[i])) {
2362 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER)
2363 return -EPROBE_DEFER;
2368 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
2369 INIT_WORK(ð->pending_work, mtk_pending_work);
2371 err = mtk_hw_init(eth);
2375 for_each_child_of_node(pdev->dev.of_node, mac_np) {
2376 if (!of_device_is_compatible(mac_np,
2377 "mediatek,eth-mac"))
2380 if (!of_device_is_available(mac_np))
2383 err = mtk_add_mac(eth, mac_np);
2388 err = devm_request_irq(eth->dev, eth->irq[1], mtk_handle_irq_tx, 0,
2389 dev_name(eth->dev), eth);
2393 err = devm_request_irq(eth->dev, eth->irq[2], mtk_handle_irq_rx, 0,
2394 dev_name(eth->dev), eth);
2398 err = mtk_mdio_init(eth);
2402 for (i = 0; i < MTK_MAX_DEVS; i++) {
2403 if (!eth->netdev[i])
2406 err = register_netdev(eth->netdev[i]);
2408 dev_err(eth->dev, "error bringing up device\n");
2409 goto err_deinit_mdio;
2411 netif_info(eth, probe, eth->netdev[i],
2412 "mediatek frame engine at 0x%08lx, irq %d\n",
2413 eth->netdev[i]->base_addr, eth->irq[0]);
2416 /* we run 2 devices on the same DMA ring so we need a dummy device
2419 init_dummy_netdev(ð->dummy_dev);
2420 netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx,
2422 netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx,
2425 platform_set_drvdata(pdev, eth);
2430 mtk_mdio_cleanup(eth);
2439 static int mtk_remove(struct platform_device *pdev)
2441 struct mtk_eth *eth = platform_get_drvdata(pdev);
2444 /* stop all devices to make sure that dma is properly shut down */
2445 for (i = 0; i < MTK_MAC_COUNT; i++) {
2446 if (!eth->netdev[i])
2448 mtk_stop(eth->netdev[i]);
2453 netif_napi_del(ð->tx_napi);
2454 netif_napi_del(ð->rx_napi);
2460 const struct of_device_id of_mtk_match[] = {
2461 { .compatible = "mediatek,mt7623-eth" },
2465 static struct platform_driver mtk_driver = {
2467 .remove = mtk_remove,
2469 .name = "mtk_soc_eth",
2470 .of_match_table = of_mtk_match,
2474 module_platform_driver(mtk_driver);
2476 MODULE_LICENSE("GPL");
2477 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
2478 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");