drivers/net/ethernet/mellanox/mlx4/main.c

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
   4  * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
   5  * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * OpenIB.org BSD license below:
  12  *
  13  *     Redistribution and use in source and binary forms, with or
  14  *     without modification, are permitted provided that the following
  15  *     conditions are met:
  16  *
  17  *      - Redistributions of source code must retain the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer.
  20  *
  21  *      - Redistributions in binary form must reproduce the above
  22  *        copyright notice, this list of conditions and the following
  23  *        disclaimer in the documentation and/or other materials
  24  *        provided with the distribution.
  25  *
  26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33  * SOFTWARE.
  34  */
  35
  36 #include <linux/module.h>
  37 #include <linux/init.h>
  38 #include <linux/errno.h>
  39 #include <linux/pci.h>
  40 #include <linux/dma-mapping.h>
  41 #include <linux/slab.h>
  42 #include <linux/io-mapping.h>
  43 #include <linux/delay.h>
  44 #include <linux/kmod.h>
  45 #include <net/devlink.h>
  46
  47 #include <linux/mlx4/device.h>
  48 #include <linux/mlx4/doorbell.h>
  49
  50 #include "mlx4.h"
  51 #include "fw.h"
  52 #include "icm.h"
  53
  54 MODULE_AUTHOR("Roland Dreier");
  55 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
  56 MODULE_LICENSE("Dual BSD/GPL");
  57 MODULE_VERSION(DRV_VERSION);
  58
  59 struct workqueue_struct *mlx4_wq;
  60
  61 #ifdef CONFIG_MLX4_DEBUG
  62
  63 int mlx4_debug_level = 0;
  64 module_param_named(debug_level, mlx4_debug_level, int, 0644);
  65 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
  66
  67 #endif /* CONFIG_MLX4_DEBUG */
  68
  69 #ifdef CONFIG_PCI_MSI
  70
  71 static int msi_x = 1;
  72 module_param(msi_x, int, 0444);
  73 MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
  74
  75 #else /* CONFIG_PCI_MSI */
  76
  77 #define msi_x (0)
  78
  79 #endif /* CONFIG_PCI_MSI */
  80
  81 static uint8_t num_vfs[3] = {0, 0, 0};
  82 static int num_vfs_argc;
  83 module_param_array(num_vfs, byte , &num_vfs_argc, 0444);
  84 MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0\n"
  85                           "num_vfs=port1,port2,port1+2");
  86
  87 static uint8_t probe_vf[3] = {0, 0, 0};
  88 static int probe_vfs_argc;
  89 module_param_array(probe_vf, byte, &probe_vfs_argc, 0444);
  90 MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)\n"
  91                            "probe_vf=port1,port2,port1+2");
  92
  93 int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
  94 module_param_named(log_num_mgm_entry_size,
  95                         mlx4_log_num_mgm_entry_size, int, 0444);
  96 MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
  97                                          " of qp per mcg, for example:"
  98                                          " 10 gives 248.range: 7 <="
  99                                          " log_num_mgm_entry_size <= 12."
 100                                          " To activate device managed"
 101                                          " flow steering when available, set to -1");
 102
 103 static bool enable_64b_cqe_eqe = true;
 104 module_param(enable_64b_cqe_eqe, bool, 0444);
 105 MODULE_PARM_DESC(enable_64b_cqe_eqe,
 106                  "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)");
 107
 108 static bool enable_4k_uar;
 109 module_param(enable_4k_uar, bool, 0444);
 110 MODULE_PARM_DESC(enable_4k_uar,
 111                  "Enable using 4K UAR. Should not be enabled if have VFs which do not support 4K UARs (default: false)");
 112
 113 #define PF_CONTEXT_BEHAVIOUR_MASK       (MLX4_FUNC_CAP_64B_EQE_CQE | \
 114                                          MLX4_FUNC_CAP_EQE_CQE_STRIDE | \
 115                                          MLX4_FUNC_CAP_DMFS_A0_STATIC)
 116
 117 #define RESET_PERSIST_MASK_FLAGS        (MLX4_FLAG_SRIOV)
 118
 119 static char mlx4_version[] =
 120         DRV_NAME ": Mellanox ConnectX core driver v"
 121         DRV_VERSION " (" DRV_RELDATE ")\n";
 122
 123 static struct mlx4_profile default_profile = {
 124         .num_qp         = 1 << 18,
 125         .num_srq        = 1 << 16,
 126         .rdmarc_per_qp  = 1 << 4,
 127         .num_cq         = 1 << 16,
 128         .num_mcg        = 1 << 13,
 129         .num_mpt        = 1 << 19,
 130         .num_mtt        = 1 << 20, /* It is really num mtt segements */
 131 };
 132
 133 static struct mlx4_profile low_mem_profile = {
 134         .num_qp         = 1 << 17,
 135         .num_srq        = 1 << 6,
 136         .rdmarc_per_qp  = 1 << 4,
 137         .num_cq         = 1 << 8,
 138         .num_mcg        = 1 << 8,
 139         .num_mpt        = 1 << 9,
 140         .num_mtt        = 1 << 7,
 141 };
 142
 143 static int log_num_mac = 7;
 144 module_param_named(log_num_mac, log_num_mac, int, 0444);
 145 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
 146
 147 static int log_num_vlan;
 148 module_param_named(log_num_vlan, log_num_vlan, int, 0444);
 149 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
 150 /* Log2 max number of VLANs per ETH port (0-7) */
 151 #define MLX4_LOG_NUM_VLANS 7
 152 #define MLX4_MIN_LOG_NUM_VLANS 0
 153 #define MLX4_MIN_LOG_NUM_MAC 1
 154
 155 static bool use_prio;
 156 module_param_named(use_prio, use_prio, bool, 0444);
 157 MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports (deprecated)");
 158
 159 int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
 160 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
 161 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
 162
 163 static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
 164 static int arr_argc = 2;
 165 module_param_array(port_type_array, int, &arr_argc, 0444);
 166 MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
 167                                 "1 for IB, 2 for Ethernet");
 168
 169 struct mlx4_port_config {
 170         struct list_head list;
 171         enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
 172         struct pci_dev *pdev;
 173 };
 174
 175 static atomic_t pf_loading = ATOMIC_INIT(0);
 176
 177 static inline void mlx4_set_num_reserved_uars(struct mlx4_dev *dev,
 178                                               struct mlx4_dev_cap *dev_cap)
 179 {
 180         /* The reserved_uars is calculated by system page size unit.
 181          * Therefore, adjustment is added when the uar page size is less
 182          * than the system page size
 183          */
 184         dev->caps.reserved_uars =
 185                 max_t(int,
 186                       mlx4_get_num_reserved_uar(dev),
 187                       dev_cap->reserved_uars /
 188                         (1 << (PAGE_SHIFT - dev->uar_page_shift)));
 189 }
 190
 191 int mlx4_check_port_params(struct mlx4_dev *dev,
 192                            enum mlx4_port_type *port_type)
 193 {
 194         int i;
 195
 196         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
 197                 for (i = 0; i < dev->caps.num_ports - 1; i++) {
 198                         if (port_type[i] != port_type[i + 1]) {
 199                                 mlx4_err(dev, "Only same port types supported on this HCA, aborting\n");
 200                                 return -EINVAL;
 201                         }
 202                 }
 203         }
 204
 205         for (i = 0; i < dev->caps.num_ports; i++) {
 206                 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
 207                         mlx4_err(dev, "Requested port type for port %d is not supported on this HCA\n",
 208                                  i + 1);
 209                         return -EINVAL;
 210                 }
 211         }
 212         return 0;
 213 }
 214
 215 static void mlx4_set_port_mask(struct mlx4_dev *dev)
 216 {
 217         int i;
 218
 219         for (i = 1; i <= dev->caps.num_ports; ++i)
 220                 dev->caps.port_mask[i] = dev->caps.port_type[i];
 221 }
 222
 223 enum {
 224         MLX4_QUERY_FUNC_NUM_SYS_EQS = 1 << 0,
 225 };
 226
 227 static int mlx4_query_func(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
 228 {
 229         int err = 0;
 230         struct mlx4_func func;
 231
 232         if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
 233                 err = mlx4_QUERY_FUNC(dev, &func, 0);
 234                 if (err) {
 235                         mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
 236                         return err;
 237                 }
 238                 dev_cap->max_eqs = func.max_eq;
 239                 dev_cap->reserved_eqs = func.rsvd_eqs;
 240                 dev_cap->reserved_uars = func.rsvd_uars;
 241                 err |= MLX4_QUERY_FUNC_NUM_SYS_EQS;
 242         }
 243         return err;
 244 }
 245
 246 static void mlx4_enable_cqe_eqe_stride(struct mlx4_dev *dev)
 247 {
 248         struct mlx4_caps *dev_cap = &dev->caps;
 249
 250         /* FW not supporting or cancelled by user */
 251         if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) ||
 252             !(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE))
 253                 return;
 254
 255         /* Must have 64B CQE_EQE enabled by FW to use bigger stride
 256          * When FW has NCSI it may decide not to report 64B CQE/EQEs
 257          */
 258         if (!(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_EQE) ||
 259             !(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_CQE)) {
 260                 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
 261                 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
 262                 return;
 263         }
 264
 265         if (cache_line_size() == 128 || cache_line_size() == 256) {
 266                 mlx4_dbg(dev, "Enabling CQE stride cacheLine supported\n");
 267                 /* Changing the real data inside CQE size to 32B */
 268                 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
 269                 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
 270
 271                 if (mlx4_is_master(dev))
 272                         dev_cap->function_caps |= MLX4_FUNC_CAP_EQE_CQE_STRIDE;
 273         } else {
 274                 if (cache_line_size() != 32  && cache_line_size() != 64)
 275                         mlx4_dbg(dev, "Disabling CQE stride, cacheLine size unsupported\n");
 276                 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
 277                 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
 278         }
 279 }
 280
 281 static int _mlx4_dev_port(struct mlx4_dev *dev, int port,
 282                           struct mlx4_port_cap *port_cap)
 283 {
 284         dev->caps.vl_cap[port]      = port_cap->max_vl;
 285         dev->caps.ib_mtu_cap[port]          = port_cap->ib_mtu;
 286         dev->phys_caps.gid_phys_table_len[port]  = port_cap->max_gids;
 287         dev->phys_caps.pkey_phys_table_len[port] = port_cap->max_pkeys;
 288         /* set gid and pkey table operating lengths by default
 289          * to non-sriov values
 290          */
 291         dev->caps.gid_table_len[port]  = port_cap->max_gids;
 292         dev->caps.pkey_table_len[port] = port_cap->max_pkeys;
 293         dev->caps.port_width_cap[port] = port_cap->max_port_width;
 294         dev->caps.eth_mtu_cap[port]    = port_cap->eth_mtu;
 295         dev->caps.max_tc_eth           = port_cap->max_tc_eth;
 296         dev->caps.def_mac[port]        = port_cap->def_mac;
 297         dev->caps.supported_type[port] = port_cap->supported_port_types;
 298         dev->caps.suggested_type[port] = port_cap->suggested_type;
 299         dev->caps.default_sense[port] = port_cap->default_sense;
 300         dev->caps.trans_type[port]          = port_cap->trans_type;
 301         dev->caps.vendor_oui[port]     = port_cap->vendor_oui;
 302         dev->caps.wavelength[port]     = port_cap->wavelength;
 303         dev->caps.trans_code[port]     = port_cap->trans_code;
 304
 305         return 0;
 306 }
 307
 308 static int mlx4_dev_port(struct mlx4_dev *dev, int port,
 309                          struct mlx4_port_cap *port_cap)
 310 {
 311         int err = 0;
 312
 313         err = mlx4_QUERY_PORT(dev, port, port_cap);
 314
 315         if (err)
 316                 mlx4_err(dev, "QUERY_PORT command failed.\n");
 317
 318         return err;
 319 }
 320
 321 static inline void mlx4_enable_ignore_fcs(struct mlx4_dev *dev)
 322 {
 323         if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_IGNORE_FCS))
 324                 return;
 325
 326         if (mlx4_is_mfunc(dev)) {
 327                 mlx4_dbg(dev, "SRIOV mode - Disabling Ignore FCS");
 328                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS;
 329                 return;
 330         }
 331
 332         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)) {
 333                 mlx4_dbg(dev,
 334                          "Keep FCS is not supported - Disabling Ignore FCS");
 335                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS;
 336                 return;
 337         }
 338 }
 339
 340 #define MLX4_A0_STEERING_TABLE_SIZE     256
 341 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
 342 {
 343         int err;
 344         int i;
 345
 346         err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
 347         if (err) {
 348                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
 349                 return err;
 350         }
 351         mlx4_dev_cap_dump(dev, dev_cap);
 352
 353         if (dev_cap->min_page_sz > PAGE_SIZE) {
 354                 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
 355                          dev_cap->min_page_sz, PAGE_SIZE);
 356                 return -ENODEV;
 357         }
 358         if (dev_cap->num_ports > MLX4_MAX_PORTS) {
 359                 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
 360                          dev_cap->num_ports, MLX4_MAX_PORTS);
 361                 return -ENODEV;
 362         }
 363
 364         if (dev_cap->uar_size > pci_resource_len(dev->persist->pdev, 2)) {
 365                 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
 366                          dev_cap->uar_size,
 367                          (unsigned long long)
 368                          pci_resource_len(dev->persist->pdev, 2));
 369                 return -ENODEV;
 370         }
 371
 372         dev->caps.num_ports          = dev_cap->num_ports;
 373         dev->caps.num_sys_eqs = dev_cap->num_sys_eqs;
 374         dev->phys_caps.num_phys_eqs = dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS ?
 375                                       dev->caps.num_sys_eqs :
 376                                       MLX4_MAX_EQ_NUM;
 377         for (i = 1; i <= dev->caps.num_ports; ++i) {
 378                 err = _mlx4_dev_port(dev, i, dev_cap->port_cap + i);
 379                 if (err) {
 380                         mlx4_err(dev, "QUERY_PORT command failed, aborting\n");
 381                         return err;
 382                 }
 383         }
 384
 385         dev->caps.uar_page_size      = PAGE_SIZE;
 386         dev->caps.num_uars           = dev_cap->uar_size / PAGE_SIZE;
 387         dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
 388         dev->caps.bf_reg_size        = dev_cap->bf_reg_size;
 389         dev->caps.bf_regs_per_page   = dev_cap->bf_regs_per_page;
 390         dev->caps.max_sq_sg          = dev_cap->max_sq_sg;
 391         dev->caps.max_rq_sg          = dev_cap->max_rq_sg;
 392         dev->caps.max_wqes           = dev_cap->max_qp_sz;
 393         dev->caps.max_qp_init_rdma   = dev_cap->max_requester_per_qp;
 394         dev->caps.max_srq_wqes       = dev_cap->max_srq_sz;
 395         dev->caps.max_srq_sge        = dev_cap->max_rq_sg - 1;
 396         dev->caps.reserved_srqs      = dev_cap->reserved_srqs;
 397         dev->caps.max_sq_desc_sz     = dev_cap->max_sq_desc_sz;
 398         dev->caps.max_rq_desc_sz     = dev_cap->max_rq_desc_sz;
 399         /*
 400          * Subtract 1 from the limit because we need to allocate a
 401          * spare CQE so the HCA HW can tell the difference between an
 402          * empty CQ and a full CQ.
 403          */
 404         dev->caps.max_cqes           = dev_cap->max_cq_sz - 1;
 405         dev->caps.reserved_cqs       = dev_cap->reserved_cqs;
 406         dev->caps.reserved_eqs       = dev_cap->reserved_eqs;
 407         dev->caps.reserved_mtts      = dev_cap->reserved_mtts;
 408         dev->caps.reserved_mrws      = dev_cap->reserved_mrws;
 409
 410         dev->caps.reserved_pds       = dev_cap->reserved_pds;
 411         dev->caps.reserved_xrcds     = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
 412                                         dev_cap->reserved_xrcds : 0;
 413         dev->caps.max_xrcds          = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
 414                                         dev_cap->max_xrcds : 0;
 415         dev->caps.mtt_entry_sz       = dev_cap->mtt_entry_sz;
 416
 417         dev->caps.max_msg_sz         = dev_cap->max_msg_sz;
 418         dev->caps.page_size_cap      = ~(u32) (dev_cap->min_page_sz - 1);
 419         dev->caps.flags              = dev_cap->flags;
 420         dev->caps.flags2             = dev_cap->flags2;
 421         dev->caps.bmme_flags         = dev_cap->bmme_flags;
 422         dev->caps.reserved_lkey      = dev_cap->reserved_lkey;
 423         dev->caps.stat_rate_support  = dev_cap->stat_rate_support;
 424         dev->caps.max_gso_sz         = dev_cap->max_gso_sz;
 425         dev->caps.max_rss_tbl_sz     = dev_cap->max_rss_tbl_sz;
 426
 427         /* Save uar page shift */
 428         if (!mlx4_is_slave(dev)) {
 429                 /* Virtual PCI function needs to determine UAR page size from
 430                  * firmware. Only master PCI function can set the uar page size
 431                  */
 432                 if (enable_4k_uar)
 433                         dev->uar_page_shift = DEFAULT_UAR_PAGE_SHIFT;
 434                 else
 435                         dev->uar_page_shift = PAGE_SHIFT;
 436
 437                 mlx4_set_num_reserved_uars(dev, dev_cap);
 438         }
 439
 440         if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN) {
 441                 struct mlx4_init_hca_param hca_param;
 442
 443                 memset(&hca_param, 0, sizeof(hca_param));
 444                 err = mlx4_QUERY_HCA(dev, &hca_param);
 445                 /* Turn off PHV_EN flag in case phv_check_en is set.
 446                  * phv_check_en is a HW check that parse the packet and verify
 447                  * phv bit was reported correctly in the wqe. To allow QinQ
 448                  * PHV_EN flag should be set and phv_check_en must be cleared
 449                  * otherwise QinQ packets will be drop by the HW.
 450                  */
 451                 if (err || hca_param.phv_check_en)
 452                         dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_PHV_EN;
 453         }
 454
 455         /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
 456         if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT)
 457                 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
 458         /* Don't do sense port on multifunction devices (for now at least) */
 459         if (mlx4_is_mfunc(dev))
 460                 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
 461
 462         if (mlx4_low_memory_profile()) {
 463                 dev->caps.log_num_macs  = MLX4_MIN_LOG_NUM_MAC;
 464                 dev->caps.log_num_vlans = MLX4_MIN_LOG_NUM_VLANS;
 465         } else {
 466                 dev->caps.log_num_macs  = log_num_mac;
 467                 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
 468         }
 469
 470         for (i = 1; i <= dev->caps.num_ports; ++i) {
 471                 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
 472                 if (dev->caps.supported_type[i]) {
 473                         /* if only ETH is supported - assign ETH */
 474                         if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
 475                                 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
 476                         /* if only IB is supported, assign IB */
 477                         else if (dev->caps.supported_type[i] ==
 478                                  MLX4_PORT_TYPE_IB)
 479                                 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
 480                         else {
 481                                 /* if IB and ETH are supported, we set the port
 482                                  * type according to user selection of port type;
 483                                  * if user selected none, take the FW hint */
 484                                 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE)
 485                                         dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
 486                                                 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
 487                                 else
 488                                         dev->caps.port_type[i] = port_type_array[i - 1];
 489                         }
 490                 }
 491                 /*
 492                  * Link sensing is allowed on the port if 3 conditions are true:
 493                  * 1. Both protocols are supported on the port.
 494                  * 2. Different types are supported on the port
 495                  * 3. FW declared that it supports link sensing
 496                  */
 497                 mlx4_priv(dev)->sense.sense_allowed[i] =
 498                         ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
 499                          (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
 500                          (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
 501
 502                 /*
 503                  * If "default_sense" bit is set, we move the port to "AUTO" mode
 504                  * and perform sense_port FW command to try and set the correct
 505                  * port type from beginning
 506                  */
 507                 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
 508                         enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
 509                         dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
 510                         mlx4_SENSE_PORT(dev, i, &sensed_port);
 511                         if (sensed_port != MLX4_PORT_TYPE_NONE)
 512                                 dev->caps.port_type[i] = sensed_port;
 513                 } else {
 514                         dev->caps.possible_type[i] = dev->caps.port_type[i];
 515                 }
 516
 517                 if (dev->caps.log_num_macs > dev_cap->port_cap[i].log_max_macs) {
 518                         dev->caps.log_num_macs = dev_cap->port_cap[i].log_max_macs;
 519                         mlx4_warn(dev, "Requested number of MACs is too much for port %d, reducing to %d\n",
 520                                   i, 1 << dev->caps.log_num_macs);
 521                 }
 522                 if (dev->caps.log_num_vlans > dev_cap->port_cap[i].log_max_vlans) {
 523                         dev->caps.log_num_vlans = dev_cap->port_cap[i].log_max_vlans;
 524                         mlx4_warn(dev, "Requested number of VLANs is too much for port %d, reducing to %d\n",
 525                                   i, 1 << dev->caps.log_num_vlans);
 526                 }
 527         }
 528
 529         if (mlx4_is_master(dev) && (dev->caps.num_ports == 2) &&
 530             (port_type_array[0] == MLX4_PORT_TYPE_IB) &&
 531             (port_type_array[1] == MLX4_PORT_TYPE_ETH)) {
 532                 mlx4_warn(dev,
 533                           "Granular QoS per VF not supported with IB/Eth configuration\n");
 534                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_QOS_VPP;
 535         }
 536
 537         dev->caps.max_counters = dev_cap->max_counters;
 538
 539         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
 540         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
 541                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
 542                 (1 << dev->caps.log_num_macs) *
 543                 (1 << dev->caps.log_num_vlans) *
 544                 dev->caps.num_ports;
 545         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
 546
 547         if (dev_cap->dmfs_high_rate_qpn_base > 0 &&
 548             dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN)
 549                 dev->caps.dmfs_high_rate_qpn_base = dev_cap->dmfs_high_rate_qpn_base;
 550         else
 551                 dev->caps.dmfs_high_rate_qpn_base =
 552                         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
 553
 554         if (dev_cap->dmfs_high_rate_qpn_range > 0 &&
 555             dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) {
 556                 dev->caps.dmfs_high_rate_qpn_range = dev_cap->dmfs_high_rate_qpn_range;
 557                 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DEFAULT;
 558                 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_FS_A0;
 559         } else {
 560                 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_NOT_SUPPORTED;
 561                 dev->caps.dmfs_high_rate_qpn_base =
 562                         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
 563                 dev->caps.dmfs_high_rate_qpn_range = MLX4_A0_STEERING_TABLE_SIZE;
 564         }
 565
 566         dev->caps.rl_caps = dev_cap->rl_caps;
 567
 568         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_RSS_RAW_ETH] =
 569                 dev->caps.dmfs_high_rate_qpn_range;
 570
 571         dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
 572                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
 573                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
 574                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
 575
 576         dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
 577
 578         if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) {
 579                 if (dev_cap->flags &
 580                     (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) {
 581                         mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n");
 582                         dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
 583                         dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
 584                 }
 585
 586                 if (dev_cap->flags2 &
 587                     (MLX4_DEV_CAP_FLAG2_CQE_STRIDE |
 588                      MLX4_DEV_CAP_FLAG2_EQE_STRIDE)) {
 589                         mlx4_warn(dev, "Disabling EQE/CQE stride per user request\n");
 590                         dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
 591                         dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
 592                 }
 593         }
 594
 595         if ((dev->caps.flags &
 596             (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) &&
 597             mlx4_is_master(dev))
 598                 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE;
 599
 600         if (!mlx4_is_slave(dev)) {
 601                 mlx4_enable_cqe_eqe_stride(dev);
 602                 dev->caps.alloc_res_qp_mask =
 603                         (dev->caps.bf_reg_size ? MLX4_RESERVE_ETH_BF_QP : 0) |
 604                         MLX4_RESERVE_A0_QP;
 605
 606                 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG) &&
 607                     dev->caps.flags & MLX4_DEV_CAP_FLAG_SET_ETH_SCHED) {
 608                         mlx4_warn(dev, "Old device ETS support detected\n");
 609                         mlx4_warn(dev, "Consider upgrading device FW.\n");
 610                         dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG;
 611                 }
 612
 613         } else {
 614                 dev->caps.alloc_res_qp_mask = 0;
 615         }
 616
 617         mlx4_enable_ignore_fcs(dev);
 618
 619         return 0;
 620 }
 621
 622 static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev *dev,
 623                                        enum pci_bus_speed *speed,
 624                                        enum pcie_link_width *width)
 625 {
 626         u32 lnkcap1, lnkcap2;
 627         int err1, err2;
 628
 629 #define  PCIE_MLW_CAP_SHIFT 4   /* start of MLW mask in link capabilities */
 630
 631         *speed = PCI_SPEED_UNKNOWN;
 632         *width = PCIE_LNK_WIDTH_UNKNOWN;
 633
 634         err1 = pcie_capability_read_dword(dev->persist->pdev, PCI_EXP_LNKCAP,
 635                                           &lnkcap1);
 636         err2 = pcie_capability_read_dword(dev->persist->pdev, PCI_EXP_LNKCAP2,
 637                                           &lnkcap2);
 638         if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */
 639                 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
 640                         *speed = PCIE_SPEED_8_0GT;
 641                 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
 642                         *speed = PCIE_SPEED_5_0GT;
 643                 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
 644                         *speed = PCIE_SPEED_2_5GT;
 645         }
 646         if (!err1) {
 647                 *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT;
 648                 if (!lnkcap2) { /* pre-r3.0 */
 649                         if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB)
 650                                 *speed = PCIE_SPEED_5_0GT;
 651                         else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB)
 652                                 *speed = PCIE_SPEED_2_5GT;
 653                 }
 654         }
 655
 656         if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) {
 657                 return err1 ? err1 :
 658                         err2 ? err2 : -EINVAL;
 659         }
 660         return 0;
 661 }
 662
 663 static void mlx4_check_pcie_caps(struct mlx4_dev *dev)
 664 {
 665         enum pcie_link_width width, width_cap;
 666         enum pci_bus_speed speed, speed_cap;
 667         int err;
 668
 669 #define PCIE_SPEED_STR(speed) \
 670         (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \
 671          speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \
 672          speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \
 673          "Unknown")
 674
 675         err = mlx4_get_pcie_dev_link_caps(dev, &speed_cap, &width_cap);
 676         if (err) {
 677                 mlx4_warn(dev,
 678                           "Unable to determine PCIe device BW capabilities\n");
 679                 return;
 680         }
 681
 682         err = pcie_get_minimum_link(dev->persist->pdev, &speed, &width);
 683         if (err || speed == PCI_SPEED_UNKNOWN ||
 684             width == PCIE_LNK_WIDTH_UNKNOWN) {
 685                 mlx4_warn(dev,
 686                           "Unable to determine PCI device chain minimum BW\n");
 687                 return;
 688         }
 689
 690         if (width != width_cap || speed != speed_cap)
 691                 mlx4_warn(dev,
 692                           "PCIe BW is different than device's capability\n");
 693
 694         mlx4_info(dev, "PCIe link speed is %s, device supports %s\n",
 695                   PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap));
 696         mlx4_info(dev, "PCIe link width is x%d, device supports x%d\n",
 697                   width, width_cap);
 698         return;
 699 }
 700
 701 /*The function checks if there are live vf, return the num of them*/
 702 static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
 703 {
 704         struct mlx4_priv *priv = mlx4_priv(dev);
 705         struct mlx4_slave_state *s_state;
 706         int i;
 707         int ret = 0;
 708
 709         for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
 710                 s_state = &priv->mfunc.master.slave_state[i];
 711                 if (s_state->active && s_state->last_cmd !=
 712                     MLX4_COMM_CMD_RESET) {
 713                         mlx4_warn(dev, "%s: slave: %d is still active\n",
 714                                   __func__, i);
 715                         ret++;
 716                 }
 717         }
 718         return ret;
 719 }
 720
 721 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey)
 722 {
 723         u32 qk = MLX4_RESERVED_QKEY_BASE;
 724
 725         if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX ||
 726             qpn < dev->phys_caps.base_proxy_sqpn)
 727                 return -EINVAL;
 728
 729         if (qpn >= dev->phys_caps.base_tunnel_sqpn)
 730                 /* tunnel qp */
 731                 qk += qpn - dev->phys_caps.base_tunnel_sqpn;
 732         else
 733                 qk += qpn - dev->phys_caps.base_proxy_sqpn;
 734         *qkey = qk;
 735         return 0;
 736 }
 737 EXPORT_SYMBOL(mlx4_get_parav_qkey);
 738
 739 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val)
 740 {
 741         struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
 742
 743         if (!mlx4_is_master(dev))
 744                 return;
 745
 746         priv->virt2phys_pkey[slave][port - 1][i] = val;
 747 }
 748 EXPORT_SYMBOL(mlx4_sync_pkey_table);
 749
 750 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid)
 751 {
 752         struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
 753
 754         if (!mlx4_is_master(dev))
 755                 return;
 756
 757         priv->slave_node_guids[slave] = guid;
 758 }
 759 EXPORT_SYMBOL(mlx4_put_slave_node_guid);
 760
 761 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave)
 762 {
 763         struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
 764
 765         if (!mlx4_is_master(dev))
 766                 return 0;
 767
 768         return priv->slave_node_guids[slave];
 769 }
 770 EXPORT_SYMBOL(mlx4_get_slave_node_guid);
 771
 772 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
 773 {
 774         struct mlx4_priv *priv = mlx4_priv(dev);
 775         struct mlx4_slave_state *s_slave;
 776
 777         if (!mlx4_is_master(dev))
 778                 return 0;
 779
 780         s_slave = &priv->mfunc.master.slave_state[slave];
 781         return !!s_slave->active;
 782 }
 783 EXPORT_SYMBOL(mlx4_is_slave_active);
 784
 785 static void slave_adjust_steering_mode(struct mlx4_dev *dev,
 786                                        struct mlx4_dev_cap *dev_cap,
 787                                        struct mlx4_init_hca_param *hca_param)
 788 {
 789         dev->caps.steering_mode = hca_param->steering_mode;
 790         if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
 791                 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
 792                 dev->caps.fs_log_max_ucast_qp_range_size =
 793                         dev_cap->fs_log_max_ucast_qp_range_size;
 794         } else
 795                 dev->caps.num_qp_per_mgm =
 796                         4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2);
 797
 798         mlx4_dbg(dev, "Steering mode is: %s\n",
 799                  mlx4_steering_mode_str(dev->caps.steering_mode));
 800 }
 801
 802 static int mlx4_slave_cap(struct mlx4_dev *dev)
 803 {
 804         int                        err;
 805         u32                        page_size;
 806         struct mlx4_dev_cap        dev_cap;
 807         struct mlx4_func_cap       func_cap;
 808         struct mlx4_init_hca_param hca_param;
 809         u8                         i;
 810
 811         memset(&hca_param, 0, sizeof(hca_param));
 812         err = mlx4_QUERY_HCA(dev, &hca_param);
 813         if (err) {
 814                 mlx4_err(dev, "QUERY_HCA command failed, aborting\n");
 815                 return err;
 816         }
 817
 818         /* fail if the hca has an unknown global capability
 819          * at this time global_caps should be always zeroed
 820          */
 821         if (hca_param.global_caps) {
 822                 mlx4_err(dev, "Unknown hca global capabilities\n");
 823                 return -ENOSYS;
 824         }
 825
 826         mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz;
 827
 828         dev->caps.hca_core_clock = hca_param.hca_core_clock;
 829
 830         memset(&dev_cap, 0, sizeof(dev_cap));
 831         dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp;
 832         err = mlx4_dev_cap(dev, &dev_cap);
 833         if (err) {
 834                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
 835                 return err;
 836         }
 837
 838         err = mlx4_QUERY_FW(dev);
 839         if (err)
 840                 mlx4_err(dev, "QUERY_FW command failed: could not get FW version\n");
 841
 842         page_size = ~dev->caps.page_size_cap + 1;
 843         mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
 844         if (page_size > PAGE_SIZE) {
 845                 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
 846                          page_size, PAGE_SIZE);
 847                 return -ENODEV;
 848         }
 849
 850         /* Set uar_page_shift for VF */
 851         dev->uar_page_shift = hca_param.uar_page_sz + 12;
 852
 853         /* Make sure the master uar page size is valid */
 854         if (dev->uar_page_shift > PAGE_SHIFT) {
 855                 mlx4_err(dev,
 856                          "Invalid configuration: uar page size is larger than system page size\n");
 857                 return  -ENODEV;
 858         }
 859
 860         /* Set reserved_uars based on the uar_page_shift */
 861         mlx4_set_num_reserved_uars(dev, &dev_cap);
 862
 863         /* Although uar page size in FW differs from system page size,
 864          * upper software layers (mlx4_ib, mlx4_en and part of mlx4_core)
 865          * still works with assumption that uar page size == system page size
 866          */
 867         dev->caps.uar_page_size = PAGE_SIZE;
 868
 869         memset(&func_cap, 0, sizeof(func_cap));
 870         err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap);
 871         if (err) {
 872                 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d)\n",
 873                          err);
 874                 return err;
 875         }
 876
 877         if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
 878             PF_CONTEXT_BEHAVIOUR_MASK) {
 879                 mlx4_err(dev, "Unknown pf context behaviour %x known flags %x\n",
 880                          func_cap.pf_context_behaviour, PF_CONTEXT_BEHAVIOUR_MASK);
 881                 return -ENOSYS;
 882         }
 883
 884         dev->caps.num_ports             = func_cap.num_ports;
 885         dev->quotas.qp                  = func_cap.qp_quota;
 886         dev->quotas.srq                 = func_cap.srq_quota;
 887         dev->quotas.cq                  = func_cap.cq_quota;
 888         dev->quotas.mpt                 = func_cap.mpt_quota;
 889         dev->quotas.mtt                 = func_cap.mtt_quota;
 890         dev->caps.num_qps               = 1 << hca_param.log_num_qps;
 891         dev->caps.num_srqs              = 1 << hca_param.log_num_srqs;
 892         dev->caps.num_cqs               = 1 << hca_param.log_num_cqs;
 893         dev->caps.num_mpts              = 1 << hca_param.log_mpt_sz;
 894         dev->caps.num_eqs               = func_cap.max_eq;
 895         dev->caps.reserved_eqs          = func_cap.reserved_eq;
 896         dev->caps.reserved_lkey         = func_cap.reserved_lkey;
 897         dev->caps.num_pds               = MLX4_NUM_PDS;
 898         dev->caps.num_mgms              = 0;
 899         dev->caps.num_amgms             = 0;
 900
 901         if (dev->caps.num_ports > MLX4_MAX_PORTS) {
 902                 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
 903                          dev->caps.num_ports, MLX4_MAX_PORTS);
 904                 return -ENODEV;
 905         }
 906
 907         mlx4_replace_zero_macs(dev);
 908
 909         dev->caps.qp0_qkey = kcalloc(dev->caps.num_ports, sizeof(u32), GFP_KERNEL);
 910         dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
 911         dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
 912         dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
 913         dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
 914
 915         if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy ||
 916             !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy ||
 917             !dev->caps.qp0_qkey) {
 918                 err = -ENOMEM;
 919                 goto err_mem;
 920         }
 921
 922         for (i = 1; i <= dev->caps.num_ports; ++i) {
 923                 err = mlx4_QUERY_FUNC_CAP(dev, i, &func_cap);
 924                 if (err) {
 925                         mlx4_err(dev, "QUERY_FUNC_CAP port command failed for port %d, aborting (%d)\n",
 926                                  i, err);
 927                         goto err_mem;
 928                 }
 929                 dev->caps.qp0_qkey[i - 1] = func_cap.qp0_qkey;
 930                 dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn;
 931                 dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn;
 932                 dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn;
 933                 dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn;
 934                 dev->caps.port_mask[i] = dev->caps.port_type[i];
 935                 dev->caps.phys_port_id[i] = func_cap.phys_port_id;
 936                 err = mlx4_get_slave_pkey_gid_tbl_len(dev, i,
 937                                                       &dev->caps.gid_table_len[i],
 938                                                       &dev->caps.pkey_table_len[i]);
 939                 if (err)
 940                         goto err_mem;
 941         }
 942
 943         if (dev->caps.uar_page_size * (dev->caps.num_uars -
 944                                        dev->caps.reserved_uars) >
 945                                        pci_resource_len(dev->persist->pdev,
 946                                                         2)) {
 947                 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
 948                          dev->caps.uar_page_size * dev->caps.num_uars,
 949                          (unsigned long long)
 950                          pci_resource_len(dev->persist->pdev, 2));
 951                 err = -ENOMEM;
 952                 goto err_mem;
 953         }
 954
 955         if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) {
 956                 dev->caps.eqe_size   = 64;
 957                 dev->caps.eqe_factor = 1;
 958         } else {
 959                 dev->caps.eqe_size   = 32;
 960                 dev->caps.eqe_factor = 0;
 961         }
 962
 963         if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) {
 964                 dev->caps.cqe_size   = 64;
 965                 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
 966         } else {
 967                 dev->caps.cqe_size   = 32;
 968         }
 969
 970         if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_EQE_STRIDE_ENABLED) {
 971                 dev->caps.eqe_size = hca_param.eqe_size;
 972                 dev->caps.eqe_factor = 0;
 973         }
 974
 975         if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_CQE_STRIDE_ENABLED) {
 976                 dev->caps.cqe_size = hca_param.cqe_size;
 977                 /* User still need to know when CQE > 32B */
 978                 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
 979         }
 980
 981         dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
 982         mlx4_warn(dev, "Timestamping is not supported in slave mode\n");
 983
 984         slave_adjust_steering_mode(dev, &dev_cap, &hca_param);
 985         mlx4_dbg(dev, "RSS support for IP fragments is %s\n",
 986                  hca_param.rss_ip_frags ? "on" : "off");
 987
 988         if (func_cap.extra_flags & MLX4_QUERY_FUNC_FLAGS_BF_RES_QP &&
 989             dev->caps.bf_reg_size)
 990                 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_ETH_BF_QP;
 991
 992         if (func_cap.extra_flags & MLX4_QUERY_FUNC_FLAGS_A0_RES_QP)
 993                 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_A0_QP;
 994
 995         return 0;
 996
 997 err_mem:
 998         kfree(dev->caps.qp0_qkey);
 999         kfree(dev->caps.qp0_tunnel);
1000         kfree(dev->caps.qp0_proxy);
1001         kfree(dev->caps.qp1_tunnel);
1002         kfree(dev->caps.qp1_proxy);
1003         dev->caps.qp0_qkey = NULL;
1004         dev->caps.qp0_tunnel = NULL;
1005         dev->caps.qp0_proxy = NULL;
1006         dev->caps.qp1_tunnel = NULL;
1007         dev->caps.qp1_proxy = NULL;
1008
1009         return err;
1010 }
1011
1012 static void mlx4_request_modules(struct mlx4_dev *dev)
1013 {
1014         int port;
1015         int has_ib_port = false;
1016         int has_eth_port = false;
1017 #define EN_DRV_NAME     "mlx4_en"
1018 #define IB_DRV_NAME     "mlx4_ib"
1019
1020         for (port = 1; port <= dev->caps.num_ports; port++) {
1021                 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB)
1022                         has_ib_port = true;
1023                 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
1024                         has_eth_port = true;
1025         }
1026
1027         if (has_eth_port)
1028                 request_module_nowait(EN_DRV_NAME);
1029         if (has_ib_port || (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
1030                 request_module_nowait(IB_DRV_NAME);
1031 }
1032
1033 /*
1034  * Change the port configuration of the device.
1035  * Every user of this function must hold the port mutex.
1036  */
1037 int mlx4_change_port_types(struct mlx4_dev *dev,
1038                            enum mlx4_port_type *port_types)
1039 {
1040         int err = 0;
1041         int change = 0;
1042         int port;
1043
1044         for (port = 0; port <  dev->caps.num_ports; port++) {
1045                 /* Change the port type only if the new type is different
1046                  * from the current, and not set to Auto */
1047                 if (port_types[port] != dev->caps.port_type[port + 1])
1048                         change = 1;
1049         }
1050         if (change) {
1051                 mlx4_unregister_device(dev);
1052                 for (port = 1; port <= dev->caps.num_ports; port++) {
1053                         mlx4_CLOSE_PORT(dev, port);
1054                         dev->caps.port_type[port] = port_types[port - 1];
1055                         err = mlx4_SET_PORT(dev, port, -1);
1056                         if (err) {
1057                                 mlx4_err(dev, "Failed to set port %d, aborting\n",
1058                                          port);
1059                                 goto out;
1060                         }
1061                 }
1062                 mlx4_set_port_mask(dev);
1063                 err = mlx4_register_device(dev);
1064                 if (err) {
1065                         mlx4_err(dev, "Failed to register device\n");
1066                         goto out;
1067                 }
1068                 mlx4_request_modules(dev);
1069         }
1070
1071 out:
1072         return err;
1073 }
1074
1075 static ssize_t show_port_type(struct device *dev,
1076                               struct device_attribute *attr,
1077                               char *buf)
1078 {
1079         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1080                                                    port_attr);
1081         struct mlx4_dev *mdev = info->dev;
1082         char type[8];
1083
1084         sprintf(type, "%s",
1085                 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
1086                 "ib" : "eth");
1087         if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
1088                 sprintf(buf, "auto (%s)\n", type);
1089         else
1090                 sprintf(buf, "%s\n", type);
1091
1092         return strlen(buf);
1093 }
1094
1095 static int __set_port_type(struct mlx4_port_info *info,
1096                            enum mlx4_port_type port_type)
1097 {
1098         struct mlx4_dev *mdev = info->dev;
1099         struct mlx4_priv *priv = mlx4_priv(mdev);
1100         enum mlx4_port_type types[MLX4_MAX_PORTS];
1101         enum mlx4_port_type new_types[MLX4_MAX_PORTS];
1102         int i;
1103         int err = 0;
1104
1105         if ((port_type & mdev->caps.supported_type[info->port]) != port_type) {
1106                 mlx4_err(mdev,
1107                          "Requested port type for port %d is not supported on this HCA\n",
1108                          info->port);
1109                 err = -EINVAL;
1110                 goto err_sup;
1111         }
1112
1113         mlx4_stop_sense(mdev);
1114         mutex_lock(&priv->port_mutex);
1115         info->tmp_type = port_type;
1116
1117         /* Possible type is always the one that was delivered */
1118         mdev->caps.possible_type[info->port] = info->tmp_type;
1119
1120         for (i = 0; i < mdev->caps.num_ports; i++) {
1121                 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
1122                                         mdev->caps.possible_type[i+1];
1123                 if (types[i] == MLX4_PORT_TYPE_AUTO)
1124                         types[i] = mdev->caps.port_type[i+1];
1125         }
1126
1127         if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
1128             !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
1129                 for (i = 1; i <= mdev->caps.num_ports; i++) {
1130                         if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
1131                                 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
1132                                 err = -EINVAL;
1133                         }
1134                 }
1135         }
1136         if (err) {
1137                 mlx4_err(mdev, "Auto sensing is not supported on this HCA. Set only 'eth' or 'ib' for both ports (should be the same)\n");
1138                 goto out;
1139         }
1140
1141         mlx4_do_sense_ports(mdev, new_types, types);
1142
1143         err = mlx4_check_port_params(mdev, new_types);
1144         if (err)
1145                 goto out;
1146
1147         /* We are about to apply the changes after the configuration
1148          * was verified, no need to remember the temporary types
1149          * any more */
1150         for (i = 0; i < mdev->caps.num_ports; i++)
1151                 priv->port[i + 1].tmp_type = 0;
1152
1153         err = mlx4_change_port_types(mdev, new_types);
1154
1155 out:
1156         mlx4_start_sense(mdev);
1157         mutex_unlock(&priv->port_mutex);
1158 err_sup:
1159         return err;
1160 }
1161
1162 static ssize_t set_port_type(struct device *dev,
1163                              struct device_attribute *attr,
1164                              const char *buf, size_t count)
1165 {
1166         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1167                                                    port_attr);
1168         struct mlx4_dev *mdev = info->dev;
1169         enum mlx4_port_type port_type;
1170         static DEFINE_MUTEX(set_port_type_mutex);
1171         int err;
1172
1173         mutex_lock(&set_port_type_mutex);
1174
1175         if (!strcmp(buf, "ib\n")) {
1176                 port_type = MLX4_PORT_TYPE_IB;
1177         } else if (!strcmp(buf, "eth\n")) {
1178                 port_type = MLX4_PORT_TYPE_ETH;
1179         } else if (!strcmp(buf, "auto\n")) {
1180                 port_type = MLX4_PORT_TYPE_AUTO;
1181         } else {
1182                 mlx4_err(mdev, "%s is not supported port type\n", buf);
1183                 err = -EINVAL;
1184                 goto err_out;
1185         }
1186
1187         err = __set_port_type(info, port_type);
1188
1189 err_out:
1190         mutex_unlock(&set_port_type_mutex);
1191
1192         return err ? err : count;
1193 }
1194
1195 enum ibta_mtu {
1196         IB_MTU_256  = 1,
1197         IB_MTU_512  = 2,
1198         IB_MTU_1024 = 3,
1199         IB_MTU_2048 = 4,
1200         IB_MTU_4096 = 5
1201 };
1202
1203 static inline int int_to_ibta_mtu(int mtu)
1204 {
1205         switch (mtu) {
1206         case 256:  return IB_MTU_256;
1207         case 512:  return IB_MTU_512;
1208         case 1024: return IB_MTU_1024;
1209         case 2048: return IB_MTU_2048;
1210         case 4096: return IB_MTU_4096;
1211         default: return -1;
1212         }
1213 }
1214
1215 static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
1216 {
1217         switch (mtu) {
1218         case IB_MTU_256:  return  256;
1219         case IB_MTU_512:  return  512;
1220         case IB_MTU_1024: return 1024;
1221         case IB_MTU_2048: return 2048;
1222         case IB_MTU_4096: return 4096;
1223         default: return -1;
1224         }
1225 }
1226
1227 static ssize_t show_port_ib_mtu(struct device *dev,
1228                              struct device_attribute *attr,
1229                              char *buf)
1230 {
1231         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1232                                                    port_mtu_attr);
1233         struct mlx4_dev *mdev = info->dev;
1234
1235         if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
1236                 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1237
1238         sprintf(buf, "%d\n",
1239                         ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
1240         return strlen(buf);
1241 }
1242
1243 static ssize_t set_port_ib_mtu(struct device *dev,
1244                              struct device_attribute *attr,
1245                              const char *buf, size_t count)
1246 {
1247         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1248                                                    port_mtu_attr);
1249         struct mlx4_dev *mdev = info->dev;
1250         struct mlx4_priv *priv = mlx4_priv(mdev);
1251         int err, port, mtu, ibta_mtu = -1;
1252
1253         if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
1254                 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1255                 return -EINVAL;
1256         }
1257
1258         err = kstrtoint(buf, 0, &mtu);
1259         if (!err)
1260                 ibta_mtu = int_to_ibta_mtu(mtu);
1261
1262         if (err || ibta_mtu < 0) {
1263                 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
1264                 return -EINVAL;
1265         }
1266
1267         mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
1268
1269         mlx4_stop_sense(mdev);
1270         mutex_lock(&priv->port_mutex);
1271         mlx4_unregister_device(mdev);
1272         for (port = 1; port <= mdev->caps.num_ports; port++) {
1273                 mlx4_CLOSE_PORT(mdev, port);
1274                 err = mlx4_SET_PORT(mdev, port, -1);
1275                 if (err) {
1276                         mlx4_err(mdev, "Failed to set port %d, aborting\n",
1277                                  port);
1278                         goto err_set_port;
1279                 }
1280         }
1281         err = mlx4_register_device(mdev);
1282 err_set_port:
1283         mutex_unlock(&priv->port_mutex);
1284         mlx4_start_sense(mdev);
1285         return err ? err : count;
1286 }
1287
1288 /* bond for multi-function device */
1289 #define MAX_MF_BOND_ALLOWED_SLAVES 63
1290 static int mlx4_mf_bond(struct mlx4_dev *dev)
1291 {
1292         int err = 0;
1293         int nvfs;
1294         struct mlx4_slaves_pport slaves_port1;
1295         struct mlx4_slaves_pport slaves_port2;
1296         DECLARE_BITMAP(slaves_port_1_2, MLX4_MFUNC_MAX);
1297
1298         slaves_port1 = mlx4_phys_to_slaves_pport(dev, 1);
1299         slaves_port2 = mlx4_phys_to_slaves_pport(dev, 2);
1300         bitmap_and(slaves_port_1_2,
1301                    slaves_port1.slaves, slaves_port2.slaves,
1302                    dev->persist->num_vfs + 1);
1303
1304         /* only single port vfs are allowed */
1305         if (bitmap_weight(slaves_port_1_2, dev->persist->num_vfs + 1) > 1) {
1306                 mlx4_warn(dev, "HA mode unsupported for dual ported VFs\n");
1307                 return -EINVAL;
1308         }
1309
1310         /* number of virtual functions is number of total functions minus one
1311          * physical function for each port.
1312          */
1313         nvfs = bitmap_weight(slaves_port1.slaves, dev->persist->num_vfs + 1) +
1314                 bitmap_weight(slaves_port2.slaves, dev->persist->num_vfs + 1) - 2;
1315
1316         /* limit on maximum allowed VFs */
1317         if (nvfs > MAX_MF_BOND_ALLOWED_SLAVES) {
1318                 mlx4_warn(dev, "HA mode is not supported for %d VFs (max %d are allowed)\n",
1319                           nvfs, MAX_MF_BOND_ALLOWED_SLAVES);
1320                 return -EINVAL;
1321         }
1322
1323         if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) {
1324                 mlx4_warn(dev, "HA mode unsupported for NON DMFS steering\n");
1325                 return -EINVAL;
1326         }
1327
1328         err = mlx4_bond_mac_table(dev);
1329         if (err)
1330                 return err;
1331         err = mlx4_bond_vlan_table(dev);
1332         if (err)
1333                 goto err1;
1334         err = mlx4_bond_fs_rules(dev);
1335         if (err)
1336                 goto err2;
1337
1338         return 0;
1339 err2:
1340         (void)mlx4_unbond_vlan_table(dev);
1341 err1:
1342         (void)mlx4_unbond_mac_table(dev);
1343         return err;
1344 }
1345
1346 static int mlx4_mf_unbond(struct mlx4_dev *dev)
1347 {
1348         int ret, ret1;
1349
1350         ret = mlx4_unbond_fs_rules(dev);
1351         if (ret)
1352                 mlx4_warn(dev, "multifunction unbond for flow rules failedi (%d)\n", ret);
1353         ret1 = mlx4_unbond_mac_table(dev);
1354         if (ret1) {
1355                 mlx4_warn(dev, "multifunction unbond for MAC table failed (%d)\n", ret1);
1356                 ret = ret1;
1357         }
1358         ret1 = mlx4_unbond_vlan_table(dev);
1359         if (ret1) {
1360                 mlx4_warn(dev, "multifunction unbond for VLAN table failed (%d)\n", ret1);
1361                 ret = ret1;
1362         }
1363         return ret;
1364 }
1365
1366 int mlx4_bond(struct mlx4_dev *dev)
1367 {
1368         int ret = 0;
1369         struct mlx4_priv *priv = mlx4_priv(dev);
1370
1371         mutex_lock(&priv->bond_mutex);
1372
1373         if (!mlx4_is_bonded(dev)) {
1374                 ret = mlx4_do_bond(dev, true);
1375                 if (ret)
1376                         mlx4_err(dev, "Failed to bond device: %d\n", ret);
1377                 if (!ret && mlx4_is_master(dev)) {
1378                         ret = mlx4_mf_bond(dev);
1379                         if (ret) {
1380                                 mlx4_err(dev, "bond for multifunction failed\n");
1381                                 mlx4_do_bond(dev, false);
1382                         }
1383                 }
1384         }
1385
1386         mutex_unlock(&priv->bond_mutex);
1387         if (!ret)
1388                 mlx4_dbg(dev, "Device is bonded\n");
1389
1390         return ret;
1391 }
1392 EXPORT_SYMBOL_GPL(mlx4_bond);
1393
1394 int mlx4_unbond(struct mlx4_dev *dev)
1395 {
1396         int ret = 0;
1397         struct mlx4_priv *priv = mlx4_priv(dev);
1398
1399         mutex_lock(&priv->bond_mutex);
1400
1401         if (mlx4_is_bonded(dev)) {
1402                 int ret2 = 0;
1403
1404                 ret = mlx4_do_bond(dev, false);
1405                 if (ret)
1406                         mlx4_err(dev, "Failed to unbond device: %d\n", ret);
1407                 if (mlx4_is_master(dev))
1408                         ret2 = mlx4_mf_unbond(dev);
1409                 if (ret2) {
1410                         mlx4_warn(dev, "Failed to unbond device for multifunction (%d)\n", ret2);
1411                         ret = ret2;
1412                 }
1413         }
1414
1415         mutex_unlock(&priv->bond_mutex);
1416         if (!ret)
1417                 mlx4_dbg(dev, "Device is unbonded\n");
1418
1419         return ret;
1420 }
1421 EXPORT_SYMBOL_GPL(mlx4_unbond);
1422
1423
1424 int mlx4_port_map_set(struct mlx4_dev *dev, struct mlx4_port_map *v2p)
1425 {
1426         u8 port1 = v2p->port1;
1427         u8 port2 = v2p->port2;
1428         struct mlx4_priv *priv = mlx4_priv(dev);
1429         int err;
1430
1431         if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_REMAP))
1432                 return -ENOTSUPP;
1433
1434         mutex_lock(&priv->bond_mutex);
1435
1436         /* zero means keep current mapping for this port */
1437         if (port1 == 0)
1438                 port1 = priv->v2p.port1;
1439         if (port2 == 0)
1440                 port2 = priv->v2p.port2;
1441
1442         if ((port1 < 1) || (port1 > MLX4_MAX_PORTS) ||
1443             (port2 < 1) || (port2 > MLX4_MAX_PORTS) ||
1444             (port1 == 2 && port2 == 1)) {
1445                 /* besides boundary checks cross mapping makes
1446                  * no sense and therefore not allowed */
1447                 err = -EINVAL;
1448         } else if ((port1 == priv->v2p.port1) &&
1449                  (port2 == priv->v2p.port2)) {
1450                 err = 0;
1451         } else {
1452                 err = mlx4_virt2phy_port_map(dev, port1, port2);
1453                 if (!err) {
1454                         mlx4_dbg(dev, "port map changed: [%d][%d]\n",
1455                                  port1, port2);
1456                         priv->v2p.port1 = port1;
1457                         priv->v2p.port2 = port2;
1458                 } else {
1459                         mlx4_err(dev, "Failed to change port mape: %d\n", err);
1460                 }
1461         }
1462
1463         mutex_unlock(&priv->bond_mutex);
1464         return err;
1465 }
1466 EXPORT_SYMBOL_GPL(mlx4_port_map_set);
1467
1468 static int mlx4_load_fw(struct mlx4_dev *dev)
1469 {
1470         struct mlx4_priv *priv = mlx4_priv(dev);
1471         int err;
1472
1473         priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
1474                                          GFP_HIGHUSER | __GFP_NOWARN, 0);
1475         if (!priv->fw.fw_icm) {
1476                 mlx4_err(dev, "Couldn't allocate FW area, aborting\n");
1477                 return -ENOMEM;
1478         }
1479
1480         err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
1481         if (err) {
1482                 mlx4_err(dev, "MAP_FA command failed, aborting\n");
1483                 goto err_free;
1484         }
1485
1486         err = mlx4_RUN_FW(dev);
1487         if (err) {
1488                 mlx4_err(dev, "RUN_FW command failed, aborting\n");
1489                 goto err_unmap_fa;
1490         }
1491
1492         return 0;
1493
1494 err_unmap_fa:
1495         mlx4_UNMAP_FA(dev);
1496
1497 err_free:
1498         mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1499         return err;
1500 }
1501
1502 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
1503                                 int cmpt_entry_sz)
1504 {
1505         struct mlx4_priv *priv = mlx4_priv(dev);
1506         int err;
1507         int num_eqs;
1508
1509         err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
1510                                   cmpt_base +
1511                                   ((u64) (MLX4_CMPT_TYPE_QP *
1512                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1513                                   cmpt_entry_sz, dev->caps.num_qps,
1514                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1515                                   0, 0);
1516         if (err)
1517                 goto err;
1518
1519         err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
1520                                   cmpt_base +
1521                                   ((u64) (MLX4_CMPT_TYPE_SRQ *
1522                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1523                                   cmpt_entry_sz, dev->caps.num_srqs,
1524                                   dev->caps.reserved_srqs, 0, 0);
1525         if (err)
1526                 goto err_qp;
1527
1528         err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
1529                                   cmpt_base +
1530                                   ((u64) (MLX4_CMPT_TYPE_CQ *
1531                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1532                                   cmpt_entry_sz, dev->caps.num_cqs,
1533                                   dev->caps.reserved_cqs, 0, 0);
1534         if (err)
1535                 goto err_srq;
1536
1537         num_eqs = dev->phys_caps.num_phys_eqs;
1538         err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
1539                                   cmpt_base +
1540                                   ((u64) (MLX4_CMPT_TYPE_EQ *
1541                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1542                                   cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
1543         if (err)
1544                 goto err_cq;
1545
1546         return 0;
1547
1548 err_cq:
1549         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1550
1551 err_srq:
1552         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1553
1554 err_qp:
1555         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1556
1557 err:
1558         return err;
1559 }
1560
1561 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
1562                          struct mlx4_init_hca_param *init_hca, u64 icm_size)
1563 {
1564         struct mlx4_priv *priv = mlx4_priv(dev);
1565         u64 aux_pages;
1566         int num_eqs;
1567         int err;
1568
1569         err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
1570         if (err) {
1571                 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting\n");
1572                 return err;
1573         }
1574
1575         mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory\n",
1576                  (unsigned long long) icm_size >> 10,
1577                  (unsigned long long) aux_pages << 2);
1578
1579         priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
1580                                           GFP_HIGHUSER | __GFP_NOWARN, 0);
1581         if (!priv->fw.aux_icm) {
1582                 mlx4_err(dev, "Couldn't allocate aux memory, aborting\n");
1583                 return -ENOMEM;
1584         }
1585
1586         err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
1587         if (err) {
1588                 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting\n");
1589                 goto err_free_aux;
1590         }
1591
1592         err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
1593         if (err) {
1594                 mlx4_err(dev, "Failed to map cMPT context memory, aborting\n");
1595                 goto err_unmap_aux;
1596         }
1597
1598
1599         num_eqs = dev->phys_caps.num_phys_eqs;
1600         err = mlx4_init_icm_table(dev, &priv->eq_table.table,
1601                                   init_hca->eqc_base, dev_cap->eqc_entry_sz,
1602                                   num_eqs, num_eqs, 0, 0);
1603         if (err) {
1604                 mlx4_err(dev, "Failed to map EQ context memory, aborting\n");
1605                 goto err_unmap_cmpt;
1606         }
1607
1608         /*
1609          * Reserved MTT entries must be aligned up to a cacheline
1610          * boundary, since the FW will write to them, while the driver
1611          * writes to all other MTT entries. (The variable
1612          * dev->caps.mtt_entry_sz below is really the MTT segment
1613          * size, not the raw entry size)
1614          */
1615         dev->caps.reserved_mtts =
1616                 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
1617                       dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
1618
1619         err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
1620                                   init_hca->mtt_base,
1621                                   dev->caps.mtt_entry_sz,
1622                                   dev->caps.num_mtts,
1623                                   dev->caps.reserved_mtts, 1, 0);
1624         if (err) {
1625                 mlx4_err(dev, "Failed to map MTT context memory, aborting\n");
1626                 goto err_unmap_eq;
1627         }
1628
1629         err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
1630                                   init_hca->dmpt_base,
1631                                   dev_cap->dmpt_entry_sz,
1632                                   dev->caps.num_mpts,
1633                                   dev->caps.reserved_mrws, 1, 1);
1634         if (err) {
1635                 mlx4_err(dev, "Failed to map dMPT context memory, aborting\n");
1636                 goto err_unmap_mtt;
1637         }
1638
1639         err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
1640                                   init_hca->qpc_base,
1641                                   dev_cap->qpc_entry_sz,
1642                                   dev->caps.num_qps,
1643                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1644                                   0, 0);
1645         if (err) {
1646                 mlx4_err(dev, "Failed to map QP context memory, aborting\n");
1647                 goto err_unmap_dmpt;
1648         }
1649
1650         err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
1651                                   init_hca->auxc_base,
1652                                   dev_cap->aux_entry_sz,
1653                                   dev->caps.num_qps,
1654                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1655                                   0, 0);
1656         if (err) {
1657                 mlx4_err(dev, "Failed to map AUXC context memory, aborting\n");
1658                 goto err_unmap_qp;
1659         }
1660
1661         err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
1662                                   init_hca->altc_base,
1663                                   dev_cap->altc_entry_sz,
1664                                   dev->caps.num_qps,
1665                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1666                                   0, 0);
1667         if (err) {
1668                 mlx4_err(dev, "Failed to map ALTC context memory, aborting\n");
1669                 goto err_unmap_auxc;
1670         }
1671
1672         err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
1673                                   init_hca->rdmarc_base,
1674                                   dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
1675                                   dev->caps.num_qps,
1676                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1677                                   0, 0);
1678         if (err) {
1679                 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
1680                 goto err_unmap_altc;
1681         }
1682
1683         err = mlx4_init_icm_table(dev, &priv->cq_table.table,
1684                                   init_hca->cqc_base,
1685                                   dev_cap->cqc_entry_sz,
1686                                   dev->caps.num_cqs,
1687                                   dev->caps.reserved_cqs, 0, 0);
1688         if (err) {
1689                 mlx4_err(dev, "Failed to map CQ context memory, aborting\n");
1690                 goto err_unmap_rdmarc;
1691         }
1692
1693         err = mlx4_init_icm_table(dev, &priv->srq_table.table,
1694                                   init_hca->srqc_base,
1695                                   dev_cap->srq_entry_sz,
1696                                   dev->caps.num_srqs,
1697                                   dev->caps.reserved_srqs, 0, 0);
1698         if (err) {
1699                 mlx4_err(dev, "Failed to map SRQ context memory, aborting\n");
1700                 goto err_unmap_cq;
1701         }
1702
1703         /*
1704          * For flow steering device managed mode it is required to use
1705          * mlx4_init_icm_table. For B0 steering mode it's not strictly
1706          * required, but for simplicity just map the whole multicast
1707          * group table now.  The table isn't very big and it's a lot
1708          * easier than trying to track ref counts.
1709          */
1710         err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
1711                                   init_hca->mc_base,
1712                                   mlx4_get_mgm_entry_size(dev),
1713                                   dev->caps.num_mgms + dev->caps.num_amgms,
1714                                   dev->caps.num_mgms + dev->caps.num_amgms,
1715                                   0, 0);
1716         if (err) {
1717                 mlx4_err(dev, "Failed to map MCG context memory, aborting\n");
1718                 goto err_unmap_srq;
1719         }
1720
1721         return 0;
1722
1723 err_unmap_srq:
1724         mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1725
1726 err_unmap_cq:
1727         mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1728
1729 err_unmap_rdmarc:
1730         mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1731
1732 err_unmap_altc:
1733         mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1734
1735 err_unmap_auxc:
1736         mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1737
1738 err_unmap_qp:
1739         mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1740
1741 err_unmap_dmpt:
1742         mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1743
1744 err_unmap_mtt:
1745         mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1746
1747 err_unmap_eq:
1748         mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1749
1750 err_unmap_cmpt:
1751         mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1752         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1753         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1754         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1755
1756 err_unmap_aux:
1757         mlx4_UNMAP_ICM_AUX(dev);
1758
1759 err_free_aux:
1760         mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1761
1762         return err;
1763 }
1764
1765 static void mlx4_free_icms(struct mlx4_dev *dev)
1766 {
1767         struct mlx4_priv *priv = mlx4_priv(dev);
1768
1769         mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1770         mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1771         mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1772         mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1773         mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1774         mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1775         mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1776         mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1777         mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1778         mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1779         mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1780         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1781         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1782         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1783
1784         mlx4_UNMAP_ICM_AUX(dev);
1785         mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1786 }
1787
1788 static void mlx4_slave_exit(struct mlx4_dev *dev)
1789 {
1790         struct mlx4_priv *priv = mlx4_priv(dev);
1791
1792         mutex_lock(&priv->cmd.slave_cmd_mutex);
1793         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP,
1794                           MLX4_COMM_TIME))
1795                 mlx4_warn(dev, "Failed to close slave function\n");
1796         mutex_unlock(&priv->cmd.slave_cmd_mutex);
1797 }
1798
1799 static int map_bf_area(struct mlx4_dev *dev)
1800 {
1801         struct mlx4_priv *priv = mlx4_priv(dev);
1802         resource_size_t bf_start;
1803         resource_size_t bf_len;
1804         int err = 0;
1805
1806         if (!dev->caps.bf_reg_size)
1807                 return -ENXIO;
1808
1809         bf_start = pci_resource_start(dev->persist->pdev, 2) +
1810                         (dev->caps.num_uars << PAGE_SHIFT);
1811         bf_len = pci_resource_len(dev->persist->pdev, 2) -
1812                         (dev->caps.num_uars << PAGE_SHIFT);
1813         priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1814         if (!priv->bf_mapping)
1815                 err = -ENOMEM;
1816
1817         return err;
1818 }
1819
1820 static void unmap_bf_area(struct mlx4_dev *dev)
1821 {
1822         if (mlx4_priv(dev)->bf_mapping)
1823                 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1824 }
1825
1826 cycle_t mlx4_read_clock(struct mlx4_dev *dev)
1827 {
1828         u32 clockhi, clocklo, clockhi1;
1829         cycle_t cycles;
1830         int i;
1831         struct mlx4_priv *priv = mlx4_priv(dev);
1832
1833         for (i = 0; i < 10; i++) {
1834                 clockhi = swab32(readl(priv->clock_mapping));
1835                 clocklo = swab32(readl(priv->clock_mapping + 4));
1836                 clockhi1 = swab32(readl(priv->clock_mapping));
1837                 if (clockhi == clockhi1)
1838                         break;
1839         }
1840
1841         cycles = (u64) clockhi << 32 | (u64) clocklo;
1842
1843         return cycles;
1844 }
1845 EXPORT_SYMBOL_GPL(mlx4_read_clock);
1846
1847
1848 static int map_internal_clock(struct mlx4_dev *dev)
1849 {
1850         struct mlx4_priv *priv = mlx4_priv(dev);
1851
1852         priv->clock_mapping =
1853                 ioremap(pci_resource_start(dev->persist->pdev,
1854                                            priv->fw.clock_bar) +
1855                         priv->fw.clock_offset, MLX4_CLOCK_SIZE);
1856
1857         if (!priv->clock_mapping)
1858                 return -ENOMEM;
1859
1860         return 0;
1861 }
1862
1863 int mlx4_get_internal_clock_params(struct mlx4_dev *dev,
1864                                    struct mlx4_clock_params *params)
1865 {
1866         struct mlx4_priv *priv = mlx4_priv(dev);
1867
1868         if (mlx4_is_slave(dev))
1869                 return -ENOTSUPP;
1870
1871         if (!params)
1872                 return -EINVAL;
1873
1874         params->bar = priv->fw.clock_bar;
1875         params->offset = priv->fw.clock_offset;
1876         params->size = MLX4_CLOCK_SIZE;
1877
1878         return 0;
1879 }
1880 EXPORT_SYMBOL_GPL(mlx4_get_internal_clock_params);
1881
1882 static void unmap_internal_clock(struct mlx4_dev *dev)
1883 {
1884         struct mlx4_priv *priv = mlx4_priv(dev);
1885
1886         if (priv->clock_mapping)
1887                 iounmap(priv->clock_mapping);
1888 }
1889
1890 static void mlx4_close_hca(struct mlx4_dev *dev)
1891 {
1892         unmap_internal_clock(dev);
1893         unmap_bf_area(dev);
1894         if (mlx4_is_slave(dev))
1895                 mlx4_slave_exit(dev);
1896         else {
1897                 mlx4_CLOSE_HCA(dev, 0);
1898                 mlx4_free_icms(dev);
1899         }
1900 }
1901
1902 static void mlx4_close_fw(struct mlx4_dev *dev)
1903 {
1904         if (!mlx4_is_slave(dev)) {
1905                 mlx4_UNMAP_FA(dev);
1906                 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1907         }
1908 }
1909
1910 static int mlx4_comm_check_offline(struct mlx4_dev *dev)
1911 {
1912 #define COMM_CHAN_OFFLINE_OFFSET 0x09
1913
1914         u32 comm_flags;
1915         u32 offline_bit;
1916         unsigned long end;
1917         struct mlx4_priv *priv = mlx4_priv(dev);
1918
1919         end = msecs_to_jiffies(MLX4_COMM_OFFLINE_TIME_OUT) + jiffies;
1920         while (time_before(jiffies, end)) {
1921                 comm_flags = swab32(readl((__iomem char *)priv->mfunc.comm +
1922                                           MLX4_COMM_CHAN_FLAGS));
1923                 offline_bit = (comm_flags &
1924                                (u32)(1 << COMM_CHAN_OFFLINE_OFFSET));
1925                 if (!offline_bit)
1926                         return 0;
1927                 /* There are cases as part of AER/Reset flow that PF needs
1928                  * around 100 msec to load. We therefore sleep for 100 msec
1929                  * to allow other tasks to make use of that CPU during this
1930                  * time interval.
1931                  */
1932                 msleep(100);
1933         }
1934         mlx4_err(dev, "Communication channel is offline.\n");
1935         return -EIO;
1936 }
1937
1938 static void mlx4_reset_vf_support(struct mlx4_dev *dev)
1939 {
1940 #define COMM_CHAN_RST_OFFSET 0x1e
1941
1942         struct mlx4_priv *priv = mlx4_priv(dev);
1943         u32 comm_rst;
1944         u32 comm_caps;
1945
1946         comm_caps = swab32(readl((__iomem char *)priv->mfunc.comm +
1947                                  MLX4_COMM_CHAN_CAPS));
1948         comm_rst = (comm_caps & (u32)(1 << COMM_CHAN_RST_OFFSET));
1949
1950         if (comm_rst)
1951                 dev->caps.vf_caps |= MLX4_VF_CAP_FLAG_RESET;
1952 }
1953
1954 static int mlx4_init_slave(struct mlx4_dev *dev)
1955 {
1956         struct mlx4_priv *priv = mlx4_priv(dev);
1957         u64 dma = (u64) priv->mfunc.vhcr_dma;
1958         int ret_from_reset = 0;
1959         u32 slave_read;
1960         u32 cmd_channel_ver;
1961
1962         if (atomic_read(&pf_loading)) {
1963                 mlx4_warn(dev, "PF is not ready - Deferring probe\n");
1964                 return -EPROBE_DEFER;
1965         }
1966
1967         mutex_lock(&priv->cmd.slave_cmd_mutex);
1968         priv->cmd.max_cmds = 1;
1969         if (mlx4_comm_check_offline(dev)) {
1970                 mlx4_err(dev, "PF is not responsive, skipping initialization\n");
1971                 goto err_offline;
1972         }
1973
1974         mlx4_reset_vf_support(dev);
1975         mlx4_warn(dev, "Sending reset\n");
1976         ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
1977                                        MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME);
1978         /* if we are in the middle of flr the slave will try
1979          * NUM_OF_RESET_RETRIES times before leaving.*/
1980         if (ret_from_reset) {
1981                 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
1982                         mlx4_warn(dev, "slave is currently in the middle of FLR - Deferring probe\n");
1983                         mutex_unlock(&priv->cmd.slave_cmd_mutex);
1984                         return -EPROBE_DEFER;
1985                 } else
1986                         goto err;
1987         }
1988
1989         /* check the driver version - the slave I/F revision
1990          * must match the master's */
1991         slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
1992         cmd_channel_ver = mlx4_comm_get_version();
1993
1994         if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
1995                 MLX4_COMM_GET_IF_REV(slave_read)) {
1996                 mlx4_err(dev, "slave driver version is not supported by the master\n");
1997                 goto err;
1998         }
1999
2000         mlx4_warn(dev, "Sending vhcr0\n");
2001         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
2002                              MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
2003                 goto err;
2004         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
2005                              MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
2006                 goto err;
2007         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
2008                              MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
2009                 goto err;
2010         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma,
2011                           MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
2012                 goto err;
2013
2014         mutex_unlock(&priv->cmd.slave_cmd_mutex);
2015         return 0;
2016
2017 err:
2018         mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP, 0);
2019 err_offline:
2020         mutex_unlock(&priv->cmd.slave_cmd_mutex);
2021         return -EIO;
2022 }
2023
2024 static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev)
2025 {
2026         int i;
2027
2028         for (i = 1; i <= dev->caps.num_ports; i++) {
2029                 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
2030                         dev->caps.gid_table_len[i] =
2031                                 mlx4_get_slave_num_gids(dev, 0, i);
2032                 else
2033                         dev->caps.gid_table_len[i] = 1;
2034                 dev->caps.pkey_table_len[i] =
2035                         dev->phys_caps.pkey_phys_table_len[i] - 1;
2036         }
2037 }
2038
2039 static int choose_log_fs_mgm_entry_size(int qp_per_entry)
2040 {
2041         int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE;
2042
2043         for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE;
2044               i++) {
2045                 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2))
2046                         break;
2047         }
2048
2049         return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1;
2050 }
2051
2052 static const char *dmfs_high_rate_steering_mode_str(int dmfs_high_steer_mode)
2053 {
2054         switch (dmfs_high_steer_mode) {
2055         case MLX4_STEERING_DMFS_A0_DEFAULT:
2056                 return "default performance";
2057
2058         case MLX4_STEERING_DMFS_A0_DYNAMIC:
2059                 return "dynamic hybrid mode";
2060
2061         case MLX4_STEERING_DMFS_A0_STATIC:
2062                 return "performance optimized for limited rule configuration (static)";
2063
2064         case MLX4_STEERING_DMFS_A0_DISABLE:
2065                 return "disabled performance optimized steering";
2066
2067         case MLX4_STEERING_DMFS_A0_NOT_SUPPORTED:
2068                 return "performance optimized steering not supported";
2069
2070         default:
2071                 return "Unrecognized mode";
2072         }
2073 }
2074
2075 #define MLX4_DMFS_A0_STEERING                   (1UL << 2)
2076
2077 static void choose_steering_mode(struct mlx4_dev *dev,
2078                                  struct mlx4_dev_cap *dev_cap)
2079 {
2080         if (mlx4_log_num_mgm_entry_size <= 0) {
2081                 if ((-mlx4_log_num_mgm_entry_size) & MLX4_DMFS_A0_STEERING) {
2082                         if (dev->caps.dmfs_high_steer_mode ==
2083                             MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
2084                                 mlx4_err(dev, "DMFS high rate mode not supported\n");
2085                         else
2086                                 dev->caps.dmfs_high_steer_mode =
2087                                         MLX4_STEERING_DMFS_A0_STATIC;
2088                 }
2089         }
2090
2091         if (mlx4_log_num_mgm_entry_size <= 0 &&
2092             dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN &&
2093             (!mlx4_is_mfunc(dev) ||
2094              (dev_cap->fs_max_num_qp_per_entry >=
2095              (dev->persist->num_vfs + 1))) &&
2096             choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >=
2097                 MLX4_MIN_MGM_LOG_ENTRY_SIZE) {
2098                 dev->oper_log_mgm_entry_size =
2099                         choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry);
2100                 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
2101                 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
2102                 dev->caps.fs_log_max_ucast_qp_range_size =
2103                         dev_cap->fs_log_max_ucast_qp_range_size;
2104         } else {
2105                 if (dev->caps.dmfs_high_steer_mode !=
2106                     MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
2107                         dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DISABLE;
2108                 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
2109                     dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
2110                         dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
2111                 else {
2112                         dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
2113
2114                         if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
2115                             dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
2116                                 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back to A0 steering mode\n");
2117                 }
2118                 dev->oper_log_mgm_entry_size =
2119                         mlx4_log_num_mgm_entry_size > 0 ?
2120                         mlx4_log_num_mgm_entry_size :
2121                         MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
2122                 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
2123         }
2124         mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, modparam log_num_mgm_entry_size = %d\n",
2125                  mlx4_steering_mode_str(dev->caps.steering_mode),
2126                  dev->oper_log_mgm_entry_size,
2127                  mlx4_log_num_mgm_entry_size);
2128 }
2129
2130 static void choose_tunnel_offload_mode(struct mlx4_dev *dev,
2131                                        struct mlx4_dev_cap *dev_cap)
2132 {
2133         if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED &&
2134             dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS)
2135                 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN;
2136         else
2137                 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE;
2138
2139         mlx4_dbg(dev, "Tunneling offload mode is: %s\n",  (dev->caps.tunnel_offload_mode
2140                  == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none");
2141 }
2142
2143 static int mlx4_validate_optimized_steering(struct mlx4_dev *dev)
2144 {
2145         int i;
2146         struct mlx4_port_cap port_cap;
2147
2148         if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
2149                 return -EINVAL;
2150
2151         for (i = 1; i <= dev->caps.num_ports; i++) {
2152                 if (mlx4_dev_port(dev, i, &port_cap)) {
2153                         mlx4_err(dev,
2154                                  "QUERY_DEV_CAP command failed, can't veify DMFS high rate steering.\n");
2155                 } else if ((dev->caps.dmfs_high_steer_mode !=
2156                             MLX4_STEERING_DMFS_A0_DEFAULT) &&
2157                            (port_cap.dmfs_optimized_state ==
2158                             !!(dev->caps.dmfs_high_steer_mode ==
2159                             MLX4_STEERING_DMFS_A0_DISABLE))) {
2160                         mlx4_err(dev,
2161                                  "DMFS high rate steer mode differ, driver requested %s but %s in FW.\n",
2162                                  dmfs_high_rate_steering_mode_str(
2163                                         dev->caps.dmfs_high_steer_mode),
2164                                  (port_cap.dmfs_optimized_state ?
2165                                         "enabled" : "disabled"));
2166                 }
2167         }
2168
2169         return 0;
2170 }
2171
2172 static int mlx4_init_fw(struct mlx4_dev *dev)
2173 {
2174         struct mlx4_mod_stat_cfg   mlx4_cfg;
2175         int err = 0;
2176
2177         if (!mlx4_is_slave(dev)) {
2178                 err = mlx4_QUERY_FW(dev);
2179                 if (err) {
2180                         if (err == -EACCES)
2181                                 mlx4_info(dev, "non-primary physical function, skipping\n");
2182                         else
2183                                 mlx4_err(dev, "QUERY_FW command failed, aborting\n");
2184                         return err;
2185                 }
2186
2187                 err = mlx4_load_fw(dev);
2188                 if (err) {
2189                         mlx4_err(dev, "Failed to start FW, aborting\n");
2190                         return err;
2191                 }
2192
2193                 mlx4_cfg.log_pg_sz_m = 1;
2194                 mlx4_cfg.log_pg_sz = 0;
2195                 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
2196                 if (err)
2197                         mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
2198         }
2199
2200         return err;
2201 }
2202
2203 static int mlx4_init_hca(struct mlx4_dev *dev)
2204 {
2205         struct mlx4_priv          *priv = mlx4_priv(dev);
2206         struct mlx4_adapter        adapter;
2207         struct mlx4_dev_cap        dev_cap;
2208         struct mlx4_profile        profile;
2209         struct mlx4_init_hca_param init_hca;
2210         u64 icm_size;
2211         struct mlx4_config_dev_params params;
2212         int err;
2213
2214         if (!mlx4_is_slave(dev)) {
2215                 err = mlx4_dev_cap(dev, &dev_cap);
2216                 if (err) {
2217                         mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
2218                         return err;
2219                 }
2220
2221                 choose_steering_mode(dev, &dev_cap);
2222                 choose_tunnel_offload_mode(dev, &dev_cap);
2223
2224                 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC &&
2225                     mlx4_is_master(dev))
2226                         dev->caps.function_caps |= MLX4_FUNC_CAP_DMFS_A0_STATIC;
2227
2228                 err = mlx4_get_phys_port_id(dev);
2229                 if (err)
2230                         mlx4_err(dev, "Fail to get physical port id\n");
2231
2232                 if (mlx4_is_master(dev))
2233                         mlx4_parav_master_pf_caps(dev);
2234
2235                 if (mlx4_low_memory_profile()) {
2236                         mlx4_info(dev, "Running from within kdump kernel. Using low memory profile\n");
2237                         profile = low_mem_profile;
2238                 } else {
2239                         profile = default_profile;
2240                 }
2241                 if (dev->caps.steering_mode ==
2242                     MLX4_STEERING_MODE_DEVICE_MANAGED)
2243                         profile.num_mcg = MLX4_FS_NUM_MCG;
2244
2245                 icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
2246                                              &init_hca);
2247                 if ((long long) icm_size < 0) {
2248                         err = icm_size;
2249                         return err;
2250                 }
2251
2252                 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1;
2253
2254                 if (enable_4k_uar) {
2255                         init_hca.log_uar_sz = ilog2(dev->caps.num_uars) +
2256                                                     PAGE_SHIFT - DEFAULT_UAR_PAGE_SHIFT;
2257                         init_hca.uar_page_sz = DEFAULT_UAR_PAGE_SHIFT - 12;
2258                 } else {
2259                         init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
2260                         init_hca.uar_page_sz = PAGE_SHIFT - 12;
2261                 }
2262
2263                 init_hca.mw_enabled = 0;
2264                 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
2265                     dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN)
2266                         init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE;
2267
2268                 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
2269                 if (err)
2270                         return err;
2271
2272                 err = mlx4_INIT_HCA(dev, &init_hca);
2273                 if (err) {
2274                         mlx4_err(dev, "INIT_HCA command failed, aborting\n");
2275                         goto err_free_icm;
2276                 }
2277
2278                 if (dev_cap.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
2279                         err = mlx4_query_func(dev, &dev_cap);
2280                         if (err < 0) {
2281                                 mlx4_err(dev, "QUERY_FUNC command failed, aborting.\n");
2282                                 goto err_close;
2283                         } else if (err & MLX4_QUERY_FUNC_NUM_SYS_EQS) {
2284                                 dev->caps.num_eqs = dev_cap.max_eqs;
2285                                 dev->caps.reserved_eqs = dev_cap.reserved_eqs;
2286                                 dev->caps.reserved_uars = dev_cap.reserved_uars;
2287                         }
2288                 }
2289
2290                 /*
2291                  * If TS is supported by FW
2292                  * read HCA frequency by QUERY_HCA command
2293                  */
2294                 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
2295                         memset(&init_hca, 0, sizeof(init_hca));
2296                         err = mlx4_QUERY_HCA(dev, &init_hca);
2297                         if (err) {
2298                                 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp\n");
2299                                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2300                         } else {
2301                                 dev->caps.hca_core_clock =
2302                                         init_hca.hca_core_clock;
2303                         }
2304
2305                         /* In case we got HCA frequency 0 - disable timestamping
2306                          * to avoid dividing by zero
2307                          */
2308                         if (!dev->caps.hca_core_clock) {
2309                                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2310                                 mlx4_err(dev,
2311                                          "HCA frequency is 0 - timestamping is not supported\n");
2312                         } else if (map_internal_clock(dev)) {
2313                                 /*
2314                                  * Map internal clock,
2315                                  * in case of failure disable timestamping
2316                                  */
2317                                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2318                                 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported\n");
2319                         }
2320                 }
2321
2322                 if (dev->caps.dmfs_high_steer_mode !=
2323                     MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) {
2324                         if (mlx4_validate_optimized_steering(dev))
2325                                 mlx4_warn(dev, "Optimized steering validation failed\n");
2326
2327                         if (dev->caps.dmfs_high_steer_mode ==
2328                             MLX4_STEERING_DMFS_A0_DISABLE) {
2329                                 dev->caps.dmfs_high_rate_qpn_base =
2330                                         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
2331                                 dev->caps.dmfs_high_rate_qpn_range =
2332                                         MLX4_A0_STEERING_TABLE_SIZE;
2333                         }
2334
2335                         mlx4_dbg(dev, "DMFS high rate steer mode is: %s\n",
2336                                  dmfs_high_rate_steering_mode_str(
2337                                         dev->caps.dmfs_high_steer_mode));
2338                 }
2339         } else {
2340                 err = mlx4_init_slave(dev);
2341                 if (err) {
2342                         if (err != -EPROBE_DEFER)
2343                                 mlx4_err(dev, "Failed to initialize slave\n");
2344                         return err;
2345                 }
2346
2347                 err = mlx4_slave_cap(dev);
2348                 if (err) {
2349                         mlx4_err(dev, "Failed to obtain slave caps\n");
2350                         goto err_close;
2351                 }
2352         }
2353
2354         if (map_bf_area(dev))
2355                 mlx4_dbg(dev, "Failed to map blue flame area\n");
2356
2357         /*Only the master set the ports, all the rest got it from it.*/
2358         if (!mlx4_is_slave(dev))
2359                 mlx4_set_port_mask(dev);
2360
2361         err = mlx4_QUERY_ADAPTER(dev, &adapter);
2362         if (err) {
2363                 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting\n");
2364                 goto unmap_bf;
2365         }
2366
2367         /* Query CONFIG_DEV parameters */
2368         err = mlx4_config_dev_retrieval(dev, &params);
2369         if (err && err != -ENOTSUPP) {
2370                 mlx4_err(dev, "Failed to query CONFIG_DEV parameters\n");
2371         } else if (!err) {
2372                 dev->caps.rx_checksum_flags_port[1] = params.rx_csum_flags_port_1;
2373                 dev->caps.rx_checksum_flags_port[2] = params.rx_csum_flags_port_2;
2374         }
2375         priv->eq_table.inta_pin = adapter.inta_pin;
2376         memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
2377
2378         return 0;
2379
2380 unmap_bf:
2381         unmap_internal_clock(dev);
2382         unmap_bf_area(dev);
2383
2384         if (mlx4_is_slave(dev)) {
2385                 kfree(dev->caps.qp0_qkey);
2386                 kfree(dev->caps.qp0_tunnel);
2387                 kfree(dev->caps.qp0_proxy);
2388                 kfree(dev->caps.qp1_tunnel);
2389                 kfree(dev->caps.qp1_proxy);
2390         }
2391
2392 err_close:
2393         if (mlx4_is_slave(dev))
2394                 mlx4_slave_exit(dev);
2395         else
2396                 mlx4_CLOSE_HCA(dev, 0);
2397
2398 err_free_icm:
2399         if (!mlx4_is_slave(dev))
2400                 mlx4_free_icms(dev);
2401
2402         return err;
2403 }
2404
2405 static int mlx4_init_counters_table(struct mlx4_dev *dev)
2406 {
2407         struct mlx4_priv *priv = mlx4_priv(dev);
2408         int nent_pow2;
2409
2410         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2411                 return -ENOENT;
2412
2413         if (!dev->caps.max_counters)
2414                 return -ENOSPC;
2415
2416         nent_pow2 = roundup_pow_of_two(dev->caps.max_counters);
2417         /* reserve last counter index for sink counter */
2418         return mlx4_bitmap_init(&priv->counters_bitmap, nent_pow2,
2419                                 nent_pow2 - 1, 0,
2420                                 nent_pow2 - dev->caps.max_counters + 1);
2421 }
2422
2423 static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
2424 {
2425         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2426                 return;
2427
2428         if (!dev->caps.max_counters)
2429                 return;
2430
2431         mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
2432 }
2433
2434 static void mlx4_cleanup_default_counters(struct mlx4_dev *dev)
2435 {
2436         struct mlx4_priv *priv = mlx4_priv(dev);
2437         int port;
2438
2439         for (port = 0; port < dev->caps.num_ports; port++)
2440                 if (priv->def_counter[port] != -1)
2441                         mlx4_counter_free(dev,  priv->def_counter[port]);
2442 }
2443
2444 static int mlx4_allocate_default_counters(struct mlx4_dev *dev)
2445 {
2446         struct mlx4_priv *priv = mlx4_priv(dev);
2447         int port, err = 0;
2448         u32 idx;
2449
2450         for (port = 0; port < dev->caps.num_ports; port++)
2451                 priv->def_counter[port] = -1;
2452
2453         for (port = 0; port < dev->caps.num_ports; port++) {
2454                 err = mlx4_counter_alloc(dev, &idx);
2455
2456                 if (!err || err == -ENOSPC) {
2457                         priv->def_counter[port] = idx;
2458                 } else if (err == -ENOENT) {
2459                         err = 0;
2460                         continue;
2461                 } else if (mlx4_is_slave(dev) && err == -EINVAL) {
2462                         priv->def_counter[port] = MLX4_SINK_COUNTER_INDEX(dev);
2463                         mlx4_warn(dev, "can't allocate counter from old PF driver, using index %d\n",
2464                                   MLX4_SINK_COUNTER_INDEX(dev));
2465                         err = 0;
2466                 } else {
2467                         mlx4_err(dev, "%s: failed to allocate default counter port %d err %d\n",
2468                                  __func__, port + 1, err);
2469                         mlx4_cleanup_default_counters(dev);
2470                         return err;
2471                 }
2472
2473                 mlx4_dbg(dev, "%s: default counter index %d for port %d\n",
2474                          __func__, priv->def_counter[port], port + 1);
2475         }
2476
2477         return err;
2478 }
2479
2480 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
2481 {
2482         struct mlx4_priv *priv = mlx4_priv(dev);
2483
2484         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2485                 return -ENOENT;
2486
2487         *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
2488         if (*idx == -1) {
2489                 *idx = MLX4_SINK_COUNTER_INDEX(dev);
2490                 return -ENOSPC;
2491         }
2492
2493         return 0;
2494 }
2495
2496 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
2497 {
2498         u64 out_param;
2499         int err;
2500
2501         if (mlx4_is_mfunc(dev)) {
2502                 err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER,
2503                                    RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
2504                                    MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
2505                 if (!err)
2506                         *idx = get_param_l(&out_param);
2507
2508                 return err;
2509         }
2510         return __mlx4_counter_alloc(dev, idx);
2511 }
2512 EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
2513
2514 static int __mlx4_clear_if_stat(struct mlx4_dev *dev,
2515                                 u8 counter_index)
2516 {
2517         struct mlx4_cmd_mailbox *if_stat_mailbox;
2518         int err;
2519         u32 if_stat_in_mod = (counter_index & 0xff) | MLX4_QUERY_IF_STAT_RESET;
2520
2521         if_stat_mailbox = mlx4_alloc_cmd_mailbox(dev);
2522         if (IS_ERR(if_stat_mailbox))
2523                 return PTR_ERR(if_stat_mailbox);
2524
2525         err = mlx4_cmd_box(dev, 0, if_stat_mailbox->dma, if_stat_in_mod, 0,
2526                            MLX4_CMD_QUERY_IF_STAT, MLX4_CMD_TIME_CLASS_C,
2527                            MLX4_CMD_NATIVE);
2528
2529         mlx4_free_cmd_mailbox(dev, if_stat_mailbox);
2530         return err;
2531 }
2532
2533 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
2534 {
2535         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2536                 return;
2537
2538         if (idx == MLX4_SINK_COUNTER_INDEX(dev))
2539                 return;
2540
2541         __mlx4_clear_if_stat(dev, idx);
2542
2543         mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR);
2544         return;
2545 }
2546
2547 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
2548 {
2549         u64 in_param = 0;
2550
2551         if (mlx4_is_mfunc(dev)) {
2552                 set_param_l(&in_param, idx);
2553                 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
2554                          MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
2555                          MLX4_CMD_WRAPPED);
2556                 return;
2557         }
2558         __mlx4_counter_free(dev, idx);
2559 }
2560 EXPORT_SYMBOL_GPL(mlx4_counter_free);
2561
2562 int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port)
2563 {
2564         struct mlx4_priv *priv = mlx4_priv(dev);
2565
2566         return priv->def_counter[port - 1];
2567 }
2568 EXPORT_SYMBOL_GPL(mlx4_get_default_counter_index);
2569
2570 void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry, int port)
2571 {
2572         struct mlx4_priv *priv = mlx4_priv(dev);
2573
2574         priv->mfunc.master.vf_admin[entry].vport[port].guid = guid;
2575 }
2576 EXPORT_SYMBOL_GPL(mlx4_set_admin_guid);
2577
2578 __be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port)
2579 {
2580         struct mlx4_priv *priv = mlx4_priv(dev);
2581
2582         return priv->mfunc.master.vf_admin[entry].vport[port].guid;
2583 }
2584 EXPORT_SYMBOL_GPL(mlx4_get_admin_guid);
2585
2586 void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port)
2587 {
2588         struct mlx4_priv *priv = mlx4_priv(dev);
2589         __be64 guid;
2590
2591         /* hw GUID */
2592         if (entry == 0)
2593                 return;
2594
2595         get_random_bytes((char *)&guid, sizeof(guid));
2596         guid &= ~(cpu_to_be64(1ULL << 56));
2597         guid |= cpu_to_be64(1ULL << 57);
2598         priv->mfunc.master.vf_admin[entry].vport[port].guid = guid;
2599 }
2600
2601 static int mlx4_setup_hca(struct mlx4_dev *dev)
2602 {
2603         struct mlx4_priv *priv = mlx4_priv(dev);
2604         int err;
2605         int port;
2606         __be32 ib_port_default_caps;
2607
2608         err = mlx4_init_uar_table(dev);
2609         if (err) {
2610                 mlx4_err(dev, "Failed to initialize user access region table, aborting\n");
2611                 return err;
2612         }
2613
2614         err = mlx4_uar_alloc(dev, &priv->driver_uar);
2615         if (err) {
2616                 mlx4_err(dev, "Failed to allocate driver access region, aborting\n");
2617                 goto err_uar_table_free;
2618         }
2619
2620         priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
2621         if (!priv->kar) {
2622                 mlx4_err(dev, "Couldn't map kernel access region, aborting\n");
2623                 err = -ENOMEM;
2624                 goto err_uar_free;
2625         }
2626
2627         err = mlx4_init_pd_table(dev);
2628         if (err) {
2629                 mlx4_err(dev, "Failed to initialize protection domain table, aborting\n");
2630                 goto err_kar_unmap;
2631         }
2632
2633         err = mlx4_init_xrcd_table(dev);
2634         if (err) {
2635                 mlx4_err(dev, "Failed to initialize reliable connection domain table, aborting\n");
2636                 goto err_pd_table_free;
2637         }
2638
2639         err = mlx4_init_mr_table(dev);
2640         if (err) {
2641                 mlx4_err(dev, "Failed to initialize memory region table, aborting\n");
2642                 goto err_xrcd_table_free;
2643         }
2644
2645         if (!mlx4_is_slave(dev)) {
2646                 err = mlx4_init_mcg_table(dev);
2647                 if (err) {
2648                         mlx4_err(dev, "Failed to initialize multicast group table, aborting\n");
2649                         goto err_mr_table_free;
2650                 }
2651                 err = mlx4_config_mad_demux(dev);
2652                 if (err) {
2653                         mlx4_err(dev, "Failed in config_mad_demux, aborting\n");
2654                         goto err_mcg_table_free;
2655                 }
2656         }
2657
2658         err = mlx4_init_eq_table(dev);
2659         if (err) {
2660                 mlx4_err(dev, "Failed to initialize event queue table, aborting\n");
2661                 goto err_mcg_table_free;
2662         }
2663
2664         err = mlx4_cmd_use_events(dev);
2665         if (err) {
2666                 mlx4_err(dev, "Failed to switch to event-driven firmware commands, aborting\n");
2667                 goto err_eq_table_free;
2668         }
2669
2670         err = mlx4_NOP(dev);
2671         if (err) {
2672                 if (dev->flags & MLX4_FLAG_MSI_X) {
2673                         mlx4_warn(dev, "NOP command failed to generate MSI-X interrupt IRQ %d)\n",
2674                                   priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
2675                         mlx4_warn(dev, "Trying again without MSI-X\n");
2676                 } else {
2677                         mlx4_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting\n",
2678                                  priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
2679                         mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
2680                 }
2681
2682                 goto err_cmd_poll;
2683         }
2684
2685         mlx4_dbg(dev, "NOP command IRQ test passed\n");
2686
2687         err = mlx4_init_cq_table(dev);
2688         if (err) {
2689                 mlx4_err(dev, "Failed to initialize completion queue table, aborting\n");
2690                 goto err_cmd_poll;
2691         }
2692
2693         err = mlx4_init_srq_table(dev);
2694         if (err) {
2695                 mlx4_err(dev, "Failed to initialize shared receive queue table, aborting\n");
2696                 goto err_cq_table_free;
2697         }
2698
2699         err = mlx4_init_qp_table(dev);
2700         if (err) {
2701                 mlx4_err(dev, "Failed to initialize queue pair table, aborting\n");
2702                 goto err_srq_table_free;
2703         }
2704
2705         if (!mlx4_is_slave(dev)) {
2706                 err = mlx4_init_counters_table(dev);
2707                 if (err && err != -ENOENT) {
2708                         mlx4_err(dev, "Failed to initialize counters table, aborting\n");
2709                         goto err_qp_table_free;
2710                 }
2711         }
2712
2713         err = mlx4_allocate_default_counters(dev);
2714         if (err) {
2715                 mlx4_err(dev, "Failed to allocate default counters, aborting\n");
2716                 goto err_counters_table_free;
2717         }
2718
2719         if (!mlx4_is_slave(dev)) {
2720                 for (port = 1; port <= dev->caps.num_ports; port++) {
2721                         ib_port_default_caps = 0;
2722                         err = mlx4_get_port_ib_caps(dev, port,
2723                                                     &ib_port_default_caps);
2724                         if (err)
2725                                 mlx4_warn(dev, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n",
2726                                           port, err);
2727                         dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
2728
2729                         /* initialize per-slave default ib port capabilities */
2730                         if (mlx4_is_master(dev)) {
2731                                 int i;
2732                                 for (i = 0; i < dev->num_slaves; i++) {
2733                                         if (i == mlx4_master_func_num(dev))
2734                                                 continue;
2735                                         priv->mfunc.master.slave_state[i].ib_cap_mask[port] =
2736                                                 ib_port_default_caps;
2737                                 }
2738                         }
2739
2740                         if (mlx4_is_mfunc(dev))
2741                                 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
2742                         else
2743                                 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
2744
2745                         err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ?
2746                                             dev->caps.pkey_table_len[port] : -1);
2747                         if (err) {
2748                                 mlx4_err(dev, "Failed to set port %d, aborting\n",
2749                                          port);
2750                                 goto err_default_countes_free;
2751                         }
2752                 }
2753         }
2754
2755         return 0;
2756
2757 err_default_countes_free:
2758         mlx4_cleanup_default_counters(dev);
2759
2760 err_counters_table_free:
2761         if (!mlx4_is_slave(dev))
2762                 mlx4_cleanup_counters_table(dev);
2763
2764 err_qp_table_free:
2765         mlx4_cleanup_qp_table(dev);
2766
2767 err_srq_table_free:
2768         mlx4_cleanup_srq_table(dev);
2769
2770 err_cq_table_free:
2771         mlx4_cleanup_cq_table(dev);
2772
2773 err_cmd_poll:
2774         mlx4_cmd_use_polling(dev);
2775
2776 err_eq_table_free:
2777         mlx4_cleanup_eq_table(dev);
2778
2779 err_mcg_table_free:
2780         if (!mlx4_is_slave(dev))
2781                 mlx4_cleanup_mcg_table(dev);
2782
2783 err_mr_table_free:
2784         mlx4_cleanup_mr_table(dev);
2785
2786 err_xrcd_table_free:
2787         mlx4_cleanup_xrcd_table(dev);
2788
2789 err_pd_table_free:
2790         mlx4_cleanup_pd_table(dev);
2791
2792 err_kar_unmap:
2793         iounmap(priv->kar);
2794
2795 err_uar_free:
2796         mlx4_uar_free(dev, &priv->driver_uar);
2797
2798 err_uar_table_free:
2799         mlx4_cleanup_uar_table(dev);
2800         return err;
2801 }
2802
2803 static int mlx4_init_affinity_hint(struct mlx4_dev *dev, int port, int eqn)
2804 {
2805         int requested_cpu = 0;
2806         struct mlx4_priv *priv = mlx4_priv(dev);
2807         struct mlx4_eq *eq;
2808         int off = 0;
2809         int i;
2810
2811         if (eqn > dev->caps.num_comp_vectors)
2812                 return -EINVAL;
2813
2814         for (i = 1; i < port; i++)
2815                 off += mlx4_get_eqs_per_port(dev, i);
2816
2817         requested_cpu = eqn - off - !!(eqn > MLX4_EQ_ASYNC);
2818
2819         /* Meaning EQs are shared, and this call comes from the second port */
2820         if (requested_cpu < 0)
2821                 return 0;
2822
2823         eq = &priv->eq_table.eq[eqn];
2824
2825         if (!zalloc_cpumask_var(&eq->affinity_mask, GFP_KERNEL))
2826                 return -ENOMEM;
2827
2828         cpumask_set_cpu(requested_cpu, eq->affinity_mask);
2829
2830         return 0;
2831 }
2832
2833 static void mlx4_enable_msi_x(struct mlx4_dev *dev)
2834 {
2835         struct mlx4_priv *priv = mlx4_priv(dev);
2836         struct msix_entry *entries;
2837         int i;
2838         int port = 0;
2839
2840         if (msi_x) {
2841                 int nreq = dev->caps.num_ports * num_online_cpus() + 1;
2842
2843                 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
2844                              nreq);
2845                 if (nreq > MAX_MSIX)
2846                         nreq = MAX_MSIX;
2847
2848                 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
2849                 if (!entries)
2850                         goto no_msi;
2851
2852                 for (i = 0; i < nreq; ++i)
2853                         entries[i].entry = i;
2854
2855                 nreq = pci_enable_msix_range(dev->persist->pdev, entries, 2,
2856                                              nreq);
2857
2858                 if (nreq < 0 || nreq < MLX4_EQ_ASYNC) {
2859                         kfree(entries);
2860                         goto no_msi;
2861                 }
2862                 /* 1 is reserved for events (asyncrounous EQ) */
2863                 dev->caps.num_comp_vectors = nreq - 1;
2864
2865                 priv->eq_table.eq[MLX4_EQ_ASYNC].irq = entries[0].vector;
2866                 bitmap_zero(priv->eq_table.eq[MLX4_EQ_ASYNC].actv_ports.ports,
2867                             dev->caps.num_ports);
2868
2869                 for (i = 0; i < dev->caps.num_comp_vectors + 1; i++) {
2870                         if (i == MLX4_EQ_ASYNC)
2871                                 continue;
2872
2873                         priv->eq_table.eq[i].irq =
2874                                 entries[i + 1 - !!(i > MLX4_EQ_ASYNC)].vector;
2875
2876                         if (MLX4_IS_LEGACY_EQ_MODE(dev->caps)) {
2877                                 bitmap_fill(priv->eq_table.eq[i].actv_ports.ports,
2878                                             dev->caps.num_ports);
2879                                 /* We don't set affinity hint when there
2880                                  * aren't enough EQs
2881                                  */
2882                         } else {
2883                                 set_bit(port,
2884                                         priv->eq_table.eq[i].actv_ports.ports);
2885                                 if (mlx4_init_affinity_hint(dev, port + 1, i))
2886                                         mlx4_warn(dev, "Couldn't init hint cpumask for EQ %d\n",
2887                                                   i);
2888                         }
2889                         /* We divide the Eqs evenly between the two ports.
2890                          * (dev->caps.num_comp_vectors / dev->caps.num_ports)
2891                          * refers to the number of Eqs per port
2892                          * (i.e eqs_per_port). Theoretically, we would like to
2893                          * write something like (i + 1) % eqs_per_port == 0.
2894                          * However, since there's an asynchronous Eq, we have
2895                          * to skip over it by comparing this condition to
2896                          * !!((i + 1) > MLX4_EQ_ASYNC).
2897                          */
2898                         if ((dev->caps.num_comp_vectors > dev->caps.num_ports) &&
2899                             ((i + 1) %
2900                              (dev->caps.num_comp_vectors / dev->caps.num_ports)) ==
2901                             !!((i + 1) > MLX4_EQ_ASYNC))
2902                                 /* If dev->caps.num_comp_vectors < dev->caps.num_ports,
2903                                  * everything is shared anyway.
2904                                  */
2905                                 port++;
2906                 }
2907
2908                 dev->flags |= MLX4_FLAG_MSI_X;
2909
2910                 kfree(entries);
2911                 return;
2912         }
2913
2914 no_msi:
2915         dev->caps.num_comp_vectors = 1;
2916
2917         BUG_ON(MLX4_EQ_ASYNC >= 2);
2918         for (i = 0; i < 2; ++i) {
2919                 priv->eq_table.eq[i].irq = dev->persist->pdev->irq;
2920                 if (i != MLX4_EQ_ASYNC) {
2921                         bitmap_fill(priv->eq_table.eq[i].actv_ports.ports,
2922                                     dev->caps.num_ports);
2923                 }
2924         }
2925 }
2926
2927 static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
2928 {
2929         struct devlink *devlink = priv_to_devlink(mlx4_priv(dev));
2930         struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
2931         int err;
2932
2933         err = devlink_port_register(devlink, &info->devlink_port, port);
2934         if (err)
2935                 return err;
2936
2937         info->dev = dev;
2938         info->port = port;
2939         if (!mlx4_is_slave(dev)) {
2940                 mlx4_init_mac_table(dev, &info->mac_table);
2941                 mlx4_init_vlan_table(dev, &info->vlan_table);
2942                 mlx4_init_roce_gid_table(dev, &info->gid_table);
2943                 info->base_qpn = mlx4_get_base_qpn(dev, port);
2944         }
2945
2946         sprintf(info->dev_name, "mlx4_port%d", port);
2947         info->port_attr.attr.name = info->dev_name;
2948         if (mlx4_is_mfunc(dev))
2949                 info->port_attr.attr.mode = S_IRUGO;
2950         else {
2951                 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
2952                 info->port_attr.store     = set_port_type;
2953         }
2954         info->port_attr.show      = show_port_type;
2955         sysfs_attr_init(&info->port_attr.attr);
2956
2957         err = device_create_file(&dev->persist->pdev->dev, &info->port_attr);
2958         if (err) {
2959                 mlx4_err(dev, "Failed to create file for port %d\n", port);
2960                 devlink_port_unregister(&info->devlink_port);
2961                 info->port = -1;
2962         }
2963
2964         sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
2965         info->port_mtu_attr.attr.name = info->dev_mtu_name;
2966         if (mlx4_is_mfunc(dev))
2967                 info->port_mtu_attr.attr.mode = S_IRUGO;
2968         else {
2969                 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR;
2970                 info->port_mtu_attr.store     = set_port_ib_mtu;
2971         }
2972         info->port_mtu_attr.show      = show_port_ib_mtu;
2973         sysfs_attr_init(&info->port_mtu_attr.attr);
2974
2975         err = device_create_file(&dev->persist->pdev->dev,
2976                                  &info->port_mtu_attr);
2977         if (err) {
2978                 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
2979                 device_remove_file(&info->dev->persist->pdev->dev,
2980                                    &info->port_attr);
2981                 devlink_port_unregister(&info->devlink_port);
2982                 info->port = -1;
2983         }
2984
2985         return err;
2986 }
2987
2988 static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
2989 {
2990         if (info->port < 0)
2991                 return;
2992
2993         device_remove_file(&info->dev->persist->pdev->dev, &info->port_attr);
2994         device_remove_file(&info->dev->persist->pdev->dev,
2995                            &info->port_mtu_attr);
2996         devlink_port_unregister(&info->devlink_port);
2997
2998 #ifdef CONFIG_RFS_ACCEL
2999         free_irq_cpu_rmap(info->rmap);
3000         info->rmap = NULL;
3001 #endif
3002 }
3003
3004 static int mlx4_init_steering(struct mlx4_dev *dev)
3005 {
3006         struct mlx4_priv *priv = mlx4_priv(dev);
3007         int num_entries = dev->caps.num_ports;
3008         int i, j;
3009
3010         priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
3011         if (!priv->steer)
3012                 return -ENOMEM;
3013
3014         for (i = 0; i < num_entries; i++)
3015                 for (j = 0; j < MLX4_NUM_STEERS; j++) {
3016                         INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
3017                         INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
3018                 }
3019         return 0;
3020 }
3021
3022 static void mlx4_clear_steering(struct mlx4_dev *dev)
3023 {
3024         struct mlx4_priv *priv = mlx4_priv(dev);
3025         struct mlx4_steer_index *entry, *tmp_entry;
3026         struct mlx4_promisc_qp *pqp, *tmp_pqp;
3027         int num_entries = dev->caps.num_ports;
3028         int i, j;
3029
3030         for (i = 0; i < num_entries; i++) {
3031                 for (j = 0; j < MLX4_NUM_STEERS; j++) {
3032                         list_for_each_entry_safe(pqp, tmp_pqp,
3033                                                  &priv->steer[i].promisc_qps[j],
3034                                                  list) {
3035                                 list_del(&pqp->list);
3036                                 kfree(pqp);
3037                         }
3038                         list_for_each_entry_safe(entry, tmp_entry,
3039                                                  &priv->steer[i].steer_entries[j],
3040                                                  list) {
3041                                 list_del(&entry->list);
3042                                 list_for_each_entry_safe(pqp, tmp_pqp,
3043                                                          &entry->duplicates,
3044                                                          list) {
3045                                         list_del(&pqp->list);
3046                                         kfree(pqp);
3047                                 }
3048                                 kfree(entry);
3049                         }
3050                 }
3051         }
3052         kfree(priv->steer);
3053 }
3054
3055 static int extended_func_num(struct pci_dev *pdev)
3056 {
3057         return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
3058 }
3059
3060 #define MLX4_OWNER_BASE 0x8069c
3061 #define MLX4_OWNER_SIZE 4
3062
3063 static int mlx4_get_ownership(struct mlx4_dev *dev)
3064 {
3065         void __iomem *owner;
3066         u32 ret;
3067
3068         if (pci_channel_offline(dev->persist->pdev))
3069                 return -EIO;
3070
3071         owner = ioremap(pci_resource_start(dev->persist->pdev, 0) +
3072                         MLX4_OWNER_BASE,
3073                         MLX4_OWNER_SIZE);
3074         if (!owner) {
3075                 mlx4_err(dev, "Failed to obtain ownership bit\n");
3076                 return -ENOMEM;
3077         }
3078
3079         ret = readl(owner);
3080         iounmap(owner);
3081         return (int) !!ret;
3082 }
3083
3084 static void mlx4_free_ownership(struct mlx4_dev *dev)
3085 {
3086         void __iomem *owner;
3087
3088         if (pci_channel_offline(dev->persist->pdev))
3089                 return;
3090
3091         owner = ioremap(pci_resource_start(dev->persist->pdev, 0) +
3092                         MLX4_OWNER_BASE,
3093                         MLX4_OWNER_SIZE);
3094         if (!owner) {
3095                 mlx4_err(dev, "Failed to obtain ownership bit\n");
3096                 return;
3097         }
3098         writel(0, owner);
3099         msleep(1000);
3100         iounmap(owner);
3101 }
3102
3103 #define SRIOV_VALID_STATE(flags) (!!((flags) & MLX4_FLAG_SRIOV) ==\
3104                                   !!((flags) & MLX4_FLAG_MASTER))
3105
3106 static u64 mlx4_enable_sriov(struct mlx4_dev *dev, struct pci_dev *pdev,
3107                              u8 total_vfs, int existing_vfs, int reset_flow)
3108 {
3109         u64 dev_flags = dev->flags;
3110         int err = 0;
3111         int fw_enabled_sriov_vfs = min(pci_sriov_get_totalvfs(pdev),
3112                                         MLX4_MAX_NUM_VF);
3113
3114         if (reset_flow) {
3115                 dev->dev_vfs = kcalloc(total_vfs, sizeof(*dev->dev_vfs),
3116                                        GFP_KERNEL);
3117                 if (!dev->dev_vfs)
3118                         goto free_mem;
3119                 return dev_flags;
3120         }
3121
3122         atomic_inc(&pf_loading);
3123         if (dev->flags &  MLX4_FLAG_SRIOV) {
3124                 if (existing_vfs != total_vfs) {
3125                         mlx4_err(dev, "SR-IOV was already enabled, but with num_vfs (%d) different than requested (%d)\n",
3126                                  existing_vfs, total_vfs);
3127                         total_vfs = existing_vfs;
3128                 }
3129         }
3130
3131         dev->dev_vfs = kzalloc(total_vfs * sizeof(*dev->dev_vfs), GFP_KERNEL);
3132         if (NULL == dev->dev_vfs) {
3133                 mlx4_err(dev, "Failed to allocate memory for VFs\n");
3134                 goto disable_sriov;
3135         }
3136
3137         if (!(dev->flags &  MLX4_FLAG_SRIOV)) {
3138                 if (total_vfs > fw_enabled_sriov_vfs) {
3139                         mlx4_err(dev, "requested vfs (%d) > available vfs (%d). Continuing without SR_IOV\n",
3140                                  total_vfs, fw_enabled_sriov_vfs);
3141                         err = -ENOMEM;
3142                         goto disable_sriov;
3143                 }
3144                 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", total_vfs);
3145                 err = pci_enable_sriov(pdev, total_vfs);
3146         }
3147         if (err) {
3148                 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n",
3149                          err);
3150                 goto disable_sriov;
3151         } else {
3152                 mlx4_warn(dev, "Running in master mode\n");
3153                 dev_flags |= MLX4_FLAG_SRIOV |
3154                         MLX4_FLAG_MASTER;
3155                 dev_flags &= ~MLX4_FLAG_SLAVE;
3156                 dev->persist->num_vfs = total_vfs;
3157         }
3158         return dev_flags;
3159
3160 disable_sriov:
3161         atomic_dec(&pf_loading);
3162 free_mem:
3163         dev->persist->num_vfs = 0;
3164         kfree(dev->dev_vfs);
3165         dev->dev_vfs = NULL;
3166         return dev_flags & ~MLX4_FLAG_MASTER;
3167 }
3168
3169 enum {
3170         MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64 = -1,
3171 };
3172
3173 static int mlx4_check_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
3174                               int *nvfs)
3175 {
3176         int requested_vfs = nvfs[0] + nvfs[1] + nvfs[2];
3177         /* Checking for 64 VFs as a limitation of CX2 */
3178         if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_80_VFS) &&
3179             requested_vfs >= 64) {
3180                 mlx4_err(dev, "Requested %d VFs, but FW does not support more than 64\n",
3181                          requested_vfs);
3182                 return MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64;
3183         }
3184         return 0;
3185 }
3186
3187 static int mlx4_pci_enable_device(struct mlx4_dev *dev)
3188 {
3189         struct pci_dev *pdev = dev->persist->pdev;
3190         int err = 0;
3191
3192         mutex_lock(&dev->persist->pci_status_mutex);
3193         if (dev->persist->pci_status == MLX4_PCI_STATUS_DISABLED) {
3194                 err = pci_enable_device(pdev);
3195                 if (!err)
3196                         dev->persist->pci_status = MLX4_PCI_STATUS_ENABLED;
3197         }
3198         mutex_unlock(&dev->persist->pci_status_mutex);
3199
3200         return err;
3201 }
3202
3203 static void mlx4_pci_disable_device(struct mlx4_dev *dev)
3204 {
3205         struct pci_dev *pdev = dev->persist->pdev;
3206
3207         mutex_lock(&dev->persist->pci_status_mutex);
3208         if (dev->persist->pci_status == MLX4_PCI_STATUS_ENABLED) {
3209                 pci_disable_device(pdev);
3210                 dev->persist->pci_status = MLX4_PCI_STATUS_DISABLED;
3211         }
3212         mutex_unlock(&dev->persist->pci_status_mutex);
3213 }
3214
3215 static int mlx4_load_one(struct pci_dev *pdev, int pci_dev_data,
3216                          int total_vfs, int *nvfs, struct mlx4_priv *priv,
3217                          int reset_flow)
3218 {
3219         struct mlx4_dev *dev;
3220         unsigned sum = 0;
3221         int err;
3222         int port;
3223         int i;
3224         struct mlx4_dev_cap *dev_cap = NULL;
3225         int existing_vfs = 0;
3226
3227         dev = &priv->dev;
3228
3229         INIT_LIST_HEAD(&priv->ctx_list);
3230         spin_lock_init(&priv->ctx_lock);
3231
3232         mutex_init(&priv->port_mutex);
3233         mutex_init(&priv->bond_mutex);
3234
3235         INIT_LIST_HEAD(&priv->pgdir_list);
3236         mutex_init(&priv->pgdir_mutex);
3237         spin_lock_init(&priv->cmd.context_lock);
3238
3239         INIT_LIST_HEAD(&priv->bf_list);
3240         mutex_init(&priv->bf_mutex);
3241
3242         dev->rev_id = pdev->revision;
3243         dev->numa_node = dev_to_node(&pdev->dev);
3244
3245         /* Detect if this device is a virtual function */
3246         if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
3247                 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
3248                 dev->flags |= MLX4_FLAG_SLAVE;
3249         } else {
3250                 /* We reset the device and enable SRIOV only for physical
3251                  * devices.  Try to claim ownership on the device;
3252                  * if already taken, skip -- do not allow multiple PFs */
3253                 err = mlx4_get_ownership(dev);
3254                 if (err) {
3255                         if (err < 0)
3256                                 return err;
3257                         else {
3258                                 mlx4_warn(dev, "Multiple PFs not yet supported - Skipping PF\n");
3259                                 return -EINVAL;
3260                         }
3261                 }
3262
3263                 atomic_set(&priv->opreq_count, 0);
3264                 INIT_WORK(&priv->opreq_task, mlx4_opreq_action);
3265
3266                 /*
3267                  * Now reset the HCA before we touch the PCI capabilities or
3268                  * attempt a firmware command, since a boot ROM may have left
3269                  * the HCA in an undefined state.
3270                  */
3271                 err = mlx4_reset(dev);
3272                 if (err) {
3273                         mlx4_err(dev, "Failed to reset HCA, aborting\n");
3274                         goto err_sriov;
3275                 }
3276
3277                 if (total_vfs) {
3278                         dev->flags = MLX4_FLAG_MASTER;
3279                         existing_vfs = pci_num_vf(pdev);
3280                         if (existing_vfs)
3281                                 dev->flags |= MLX4_FLAG_SRIOV;
3282                         dev->persist->num_vfs = total_vfs;
3283                 }
3284         }
3285
3286         /* on load remove any previous indication of internal error,
3287          * device is up.
3288          */
3289         dev->persist->state = MLX4_DEVICE_STATE_UP;
3290
3291 slave_start:
3292         err = mlx4_cmd_init(dev);
3293         if (err) {
3294                 mlx4_err(dev, "Failed to init command interface, aborting\n");
3295                 goto err_sriov;
3296         }
3297
3298         /* In slave functions, the communication channel must be initialized
3299          * before posting commands. Also, init num_slaves before calling
3300          * mlx4_init_hca */
3301         if (mlx4_is_mfunc(dev)) {
3302                 if (mlx4_is_master(dev)) {
3303                         dev->num_slaves = MLX4_MAX_NUM_SLAVES;
3304
3305                 } else {
3306                         dev->num_slaves = 0;
3307                         err = mlx4_multi_func_init(dev);
3308                         if (err) {
3309                                 mlx4_err(dev, "Failed to init slave mfunc interface, aborting\n");
3310                                 goto err_cmd;
3311                         }
3312                 }
3313         }
3314
3315         err = mlx4_init_fw(dev);
3316         if (err) {
3317                 mlx4_err(dev, "Failed to init fw, aborting.\n");
3318                 goto err_mfunc;
3319         }
3320
3321         if (mlx4_is_master(dev)) {
3322                 /* when we hit the goto slave_start below, dev_cap already initialized */
3323                 if (!dev_cap) {
3324                         dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL);
3325
3326                         if (!dev_cap) {
3327                                 err = -ENOMEM;
3328                                 goto err_fw;
3329                         }
3330
3331                         err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
3332                         if (err) {
3333                                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
3334                                 goto err_fw;
3335                         }
3336
3337                         if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
3338                                 goto err_fw;
3339
3340                         if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) {
3341                                 u64 dev_flags = mlx4_enable_sriov(dev, pdev,
3342                                                                   total_vfs,
3343                                                                   existing_vfs,
3344                                                                   reset_flow);
3345
3346                                 mlx4_close_fw(dev);
3347                                 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
3348                                 dev->flags = dev_flags;
3349                                 if (!SRIOV_VALID_STATE(dev->flags)) {
3350                                         mlx4_err(dev, "Invalid SRIOV state\n");
3351                                         goto err_sriov;
3352                                 }
3353                                 err = mlx4_reset(dev);
3354                                 if (err) {
3355                                         mlx4_err(dev, "Failed to reset HCA, aborting.\n");
3356                                         goto err_sriov;
3357                                 }
3358                                 goto slave_start;
3359                         }
3360                 } else {
3361                         /* Legacy mode FW requires SRIOV to be enabled before
3362                          * doing QUERY_DEV_CAP, since max_eq's value is different if
3363                          * SRIOV is enabled.
3364                          */
3365                         memset(dev_cap, 0, sizeof(*dev_cap));
3366                         err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
3367                         if (err) {
3368                                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
3369                                 goto err_fw;
3370                         }
3371
3372                         if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
3373                                 goto err_fw;
3374                 }
3375         }
3376
3377         err = mlx4_init_hca(dev);
3378         if (err) {
3379                 if (err == -EACCES) {
3380                         /* Not primary Physical function
3381                          * Running in slave mode */
3382                         mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
3383                         /* We're not a PF */
3384                         if (dev->flags & MLX4_FLAG_SRIOV) {
3385                                 if (!existing_vfs)
3386                                         pci_disable_sriov(pdev);
3387                                 if (mlx4_is_master(dev) && !reset_flow)
3388                                         atomic_dec(&pf_loading);
3389                                 dev->flags &= ~MLX4_FLAG_SRIOV;
3390                         }
3391                         if (!mlx4_is_slave(dev))
3392                                 mlx4_free_ownership(dev);
3393                         dev->flags |= MLX4_FLAG_SLAVE;
3394                         dev->flags &= ~MLX4_FLAG_MASTER;
3395                         goto slave_start;
3396                 } else
3397                         goto err_fw;
3398         }
3399
3400         if (mlx4_is_master(dev) && (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) {
3401                 u64 dev_flags = mlx4_enable_sriov(dev, pdev, total_vfs,
3402                                                   existing_vfs, reset_flow);
3403
3404                 if ((dev->flags ^ dev_flags) & (MLX4_FLAG_MASTER | MLX4_FLAG_SLAVE)) {
3405                         mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_VHCR);
3406                         dev->flags = dev_flags;
3407                         err = mlx4_cmd_init(dev);
3408                         if (err) {
3409                                 /* Only VHCR is cleaned up, so could still
3410                                  * send FW commands
3411                                  */
3412                                 mlx4_err(dev, "Failed to init VHCR command interface, aborting\n");
3413                                 goto err_close;
3414                         }
3415                 } else {
3416                         dev->flags = dev_flags;
3417                 }
3418
3419                 if (!SRIOV_VALID_STATE(dev->flags)) {
3420                         mlx4_err(dev, "Invalid SRIOV state\n");
3421                         goto err_close;
3422                 }
3423         }
3424
3425         /* check if the device is functioning at its maximum possible speed.
3426          * No return code for this call, just warn the user in case of PCI
3427          * express device capabilities are under-satisfied by the bus.
3428          */
3429         if (!mlx4_is_slave(dev))
3430                 mlx4_check_pcie_caps(dev);
3431
3432         /* In master functions, the communication channel must be initialized
3433          * after obtaining its address from fw */
3434         if (mlx4_is_master(dev)) {
3435                 if (dev->caps.num_ports < 2 &&
3436                     num_vfs_argc > 1) {
3437                         err = -EINVAL;
3438                         mlx4_err(dev,
3439                                  "Error: Trying to configure VFs on port 2, but HCA has only %d physical ports\n",
3440                                  dev->caps.num_ports);
3441                         goto err_close;
3442                 }
3443                 memcpy(dev->persist->nvfs, nvfs, sizeof(dev->persist->nvfs));
3444
3445                 for (i = 0;
3446                      i < sizeof(dev->persist->nvfs)/
3447                      sizeof(dev->persist->nvfs[0]); i++) {
3448                         unsigned j;
3449
3450                         for (j = 0; j < dev->persist->nvfs[i]; ++sum, ++j) {
3451                                 dev->dev_vfs[sum].min_port = i < 2 ? i + 1 : 1;
3452                                 dev->dev_vfs[sum].n_ports = i < 2 ? 1 :
3453                                         dev->caps.num_ports;
3454                         }
3455                 }
3456
3457                 /* In master functions, the communication channel
3458                  * must be initialized after obtaining its address from fw
3459                  */
3460                 err = mlx4_multi_func_init(dev);
3461                 if (err) {
3462                         mlx4_err(dev, "Failed to init master mfunc interface, aborting.\n");
3463                         goto err_close;
3464                 }
3465         }
3466
3467         err = mlx4_alloc_eq_table(dev);
3468         if (err)
3469                 goto err_master_mfunc;
3470
3471         bitmap_zero(priv->msix_ctl.pool_bm, MAX_MSIX);
3472         mutex_init(&priv->msix_ctl.pool_lock);
3473
3474         mlx4_enable_msi_x(dev);
3475         if ((mlx4_is_mfunc(dev)) &&
3476             !(dev->flags & MLX4_FLAG_MSI_X)) {
3477                 err = -ENOSYS;
3478                 mlx4_err(dev, "INTx is not supported in multi-function mode, aborting\n");
3479                 goto err_free_eq;
3480         }
3481
3482         if (!mlx4_is_slave(dev)) {
3483                 err = mlx4_init_steering(dev);
3484                 if (err)
3485                         goto err_disable_msix;
3486         }
3487
3488         err = mlx4_setup_hca(dev);
3489         if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
3490             !mlx4_is_mfunc(dev)) {
3491                 dev->flags &= ~MLX4_FLAG_MSI_X;
3492                 dev->caps.num_comp_vectors = 1;
3493                 pci_disable_msix(pdev);
3494                 err = mlx4_setup_hca(dev);
3495         }
3496
3497         if (err)
3498                 goto err_steer;
3499
3500         mlx4_init_quotas(dev);
3501         /* When PF resources are ready arm its comm channel to enable
3502          * getting commands
3503          */
3504         if (mlx4_is_master(dev)) {
3505                 err = mlx4_ARM_COMM_CHANNEL(dev);
3506                 if (err) {
3507                         mlx4_err(dev, " Failed to arm comm channel eq: %x\n",
3508                                  err);
3509                         goto err_steer;
3510                 }
3511         }
3512
3513         for (port = 1; port <= dev->caps.num_ports; port++) {
3514                 err = mlx4_init_port_info(dev, port);
3515                 if (err)
3516                         goto err_port;
3517         }
3518
3519         priv->v2p.port1 = 1;
3520         priv->v2p.port2 = 2;
3521
3522         err = mlx4_register_device(dev);
3523         if (err)
3524                 goto err_port;
3525
3526         mlx4_request_modules(dev);
3527
3528         mlx4_sense_init(dev);
3529         mlx4_start_sense(dev);
3530
3531         priv->removed = 0;
3532
3533         if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow)
3534                 atomic_dec(&pf_loading);
3535
3536         kfree(dev_cap);
3537         return 0;
3538
3539 err_port:
3540         for (--port; port >= 1; --port)
3541                 mlx4_cleanup_port_info(&priv->port[port]);
3542
3543         mlx4_cleanup_default_counters(dev);
3544         if (!mlx4_is_slave(dev))
3545                 mlx4_cleanup_counters_table(dev);
3546         mlx4_cleanup_qp_table(dev);
3547         mlx4_cleanup_srq_table(dev);
3548         mlx4_cleanup_cq_table(dev);
3549         mlx4_cmd_use_polling(dev);
3550         mlx4_cleanup_eq_table(dev);
3551         mlx4_cleanup_mcg_table(dev);
3552         mlx4_cleanup_mr_table(dev);
3553         mlx4_cleanup_xrcd_table(dev);
3554         mlx4_cleanup_pd_table(dev);
3555         mlx4_cleanup_uar_table(dev);
3556
3557 err_steer:
3558         if (!mlx4_is_slave(dev))
3559                 mlx4_clear_steering(dev);
3560
3561 err_disable_msix:
3562         if (dev->flags & MLX4_FLAG_MSI_X)
3563                 pci_disable_msix(pdev);
3564
3565 err_free_eq:
3566         mlx4_free_eq_table(dev);
3567
3568 err_master_mfunc:
3569         if (mlx4_is_master(dev)) {
3570                 mlx4_free_resource_tracker(dev, RES_TR_FREE_STRUCTS_ONLY);
3571                 mlx4_multi_func_cleanup(dev);
3572         }
3573
3574         if (mlx4_is_slave(dev)) {
3575                 kfree(dev->caps.qp0_qkey);
3576                 kfree(dev->caps.qp0_tunnel);
3577                 kfree(dev->caps.qp0_proxy);
3578                 kfree(dev->caps.qp1_tunnel);
3579                 kfree(dev->caps.qp1_proxy);
3580         }
3581
3582 err_close:
3583         mlx4_close_hca(dev);
3584
3585 err_fw:
3586         mlx4_close_fw(dev);
3587
3588 err_mfunc:
3589         if (mlx4_is_slave(dev))
3590                 mlx4_multi_func_cleanup(dev);
3591
3592 err_cmd:
3593         mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
3594
3595 err_sriov:
3596         if (dev->flags & MLX4_FLAG_SRIOV && !existing_vfs) {
3597                 pci_disable_sriov(pdev);
3598                 dev->flags &= ~MLX4_FLAG_SRIOV;
3599         }
3600
3601         if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow)
3602                 atomic_dec(&pf_loading);
3603
3604         kfree(priv->dev.dev_vfs);
3605
3606         if (!mlx4_is_slave(dev))
3607                 mlx4_free_ownership(dev);
3608
3609         kfree(dev_cap);
3610         return err;
3611 }
3612
3613 static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data,
3614                            struct mlx4_priv *priv)
3615 {
3616         int err;
3617         int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3618         int prb_vf[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3619         const int param_map[MLX4_MAX_PORTS + 1][MLX4_MAX_PORTS + 1] = {
3620                 {2, 0, 0}, {0, 1, 2}, {0, 1, 2} };
3621         unsigned total_vfs = 0;
3622         unsigned int i;
3623
3624         pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
3625
3626         err = mlx4_pci_enable_device(&priv->dev);
3627         if (err) {
3628                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
3629                 return err;
3630         }
3631
3632         /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS
3633          * per port, we must limit the number of VFs to 63 (since their are
3634          * 128 MACs)
3635          */
3636         for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) && i < num_vfs_argc;
3637              total_vfs += nvfs[param_map[num_vfs_argc - 1][i]], i++) {
3638                 nvfs[param_map[num_vfs_argc - 1][i]] = num_vfs[i];
3639                 if (nvfs[i] < 0) {
3640                         dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n");
3641                         err = -EINVAL;
3642                         goto err_disable_pdev;
3643                 }
3644         }
3645         for (i = 0; i < sizeof(prb_vf)/sizeof(prb_vf[0]) && i < probe_vfs_argc;
3646              i++) {
3647                 prb_vf[param_map[probe_vfs_argc - 1][i]] = probe_vf[i];
3648                 if (prb_vf[i] < 0 || prb_vf[i] > nvfs[i]) {
3649                         dev_err(&pdev->dev, "probe_vf module parameter cannot be negative or greater than num_vfs\n");
3650                         err = -EINVAL;
3651                         goto err_disable_pdev;
3652                 }
3653         }
3654         if (total_vfs > MLX4_MAX_NUM_VF) {
3655                 dev_err(&pdev->dev,
3656                         "Requested more VF's (%d) than allowed by hw (%d)\n",
3657                         total_vfs, MLX4_MAX_NUM_VF);
3658                 err = -EINVAL;
3659                 goto err_disable_pdev;
3660         }
3661
3662         for (i = 0; i < MLX4_MAX_PORTS; i++) {
3663                 if (nvfs[i] + nvfs[2] > MLX4_MAX_NUM_VF_P_PORT) {
3664                         dev_err(&pdev->dev,
3665                                 "Requested more VF's (%d) for port (%d) than allowed by driver (%d)\n",
3666                                 nvfs[i] + nvfs[2], i + 1,
3667                                 MLX4_MAX_NUM_VF_P_PORT);
3668                         err = -EINVAL;
3669                         goto err_disable_pdev;
3670                 }
3671         }
3672
3673         /* Check for BARs. */
3674         if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) &&
3675             !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
3676                 dev_err(&pdev->dev, "Missing DCS, aborting (driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
3677                         pci_dev_data, pci_resource_flags(pdev, 0));
3678                 err = -ENODEV;
3679                 goto err_disable_pdev;
3680         }
3681         if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
3682                 dev_err(&pdev->dev, "Missing UAR, aborting\n");
3683                 err = -ENODEV;
3684                 goto err_disable_pdev;
3685         }
3686
3687         err = pci_request_regions(pdev, DRV_NAME);
3688         if (err) {
3689                 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
3690                 goto err_disable_pdev;
3691         }
3692
3693         pci_set_master(pdev);
3694
3695         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
3696         if (err) {
3697                 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
3698                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3699                 if (err) {
3700                         dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
3701                         goto err_release_regions;
3702                 }
3703         }
3704         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3705         if (err) {
3706                 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
3707                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3708                 if (err) {
3709                         dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, aborting\n");
3710                         goto err_release_regions;
3711                 }
3712         }
3713
3714         /* Allow large DMA segments, up to the firmware limit of 1 GB */
3715         dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
3716         /* Detect if this device is a virtual function */
3717         if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
3718                 /* When acting as pf, we normally skip vfs unless explicitly
3719                  * requested to probe them.
3720                  */
3721                 if (total_vfs) {
3722                         unsigned vfs_offset = 0;
3723
3724                         for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) &&
3725                              vfs_offset + nvfs[i] < extended_func_num(pdev);
3726                              vfs_offset += nvfs[i], i++)
3727                                 ;
3728                         if (i == sizeof(nvfs)/sizeof(nvfs[0])) {
3729                                 err = -ENODEV;
3730                                 goto err_release_regions;
3731                         }
3732                         if ((extended_func_num(pdev) - vfs_offset)
3733                             > prb_vf[i]) {
3734                                 dev_warn(&pdev->dev, "Skipping virtual function:%d\n",
3735                                          extended_func_num(pdev));
3736                                 err = -ENODEV;
3737                                 goto err_release_regions;
3738                         }
3739                 }
3740         }
3741
3742         err = mlx4_catas_init(&priv->dev);
3743         if (err)
3744                 goto err_release_regions;
3745
3746         err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 0);
3747         if (err)
3748                 goto err_catas;
3749
3750         return 0;
3751
3752 err_catas:
3753         mlx4_catas_end(&priv->dev);
3754
3755 err_release_regions:
3756         pci_release_regions(pdev);
3757
3758 err_disable_pdev:
3759         mlx4_pci_disable_device(&priv->dev);
3760         pci_set_drvdata(pdev, NULL);
3761         return err;
3762 }
3763
3764 static int mlx4_devlink_port_type_set(struct devlink_port *devlink_port,
3765                                       enum devlink_port_type port_type)
3766 {
3767         struct mlx4_port_info *info = container_of(devlink_port,
3768                                                    struct mlx4_port_info,
3769                                                    devlink_port);
3770         enum mlx4_port_type mlx4_port_type;
3771
3772         switch (port_type) {
3773         case DEVLINK_PORT_TYPE_AUTO:
3774                 mlx4_port_type = MLX4_PORT_TYPE_AUTO;
3775                 break;
3776         case DEVLINK_PORT_TYPE_ETH:
3777                 mlx4_port_type = MLX4_PORT_TYPE_ETH;
3778                 break;
3779         case DEVLINK_PORT_TYPE_IB:
3780                 mlx4_port_type = MLX4_PORT_TYPE_IB;
3781                 break;
3782         default:
3783                 return -EOPNOTSUPP;
3784         }
3785
3786         return __set_port_type(info, mlx4_port_type);
3787 }
3788
3789 static const struct devlink_ops mlx4_devlink_ops = {
3790         .port_type_set  = mlx4_devlink_port_type_set,
3791 };
3792
3793 static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
3794 {
3795         struct devlink *devlink;
3796         struct mlx4_priv *priv;
3797         struct mlx4_dev *dev;
3798         int ret;
3799
3800         printk_once(KERN_INFO "%s", mlx4_version);
3801
3802         devlink = devlink_alloc(&mlx4_devlink_ops, sizeof(*priv));
3803         if (!devlink)
3804                 return -ENOMEM;
3805         priv = devlink_priv(devlink);
3806
3807         dev       = &priv->dev;
3808         dev->persist = kzalloc(sizeof(*dev->persist), GFP_KERNEL);
3809         if (!dev->persist) {
3810                 ret = -ENOMEM;
3811                 goto err_devlink_free;
3812         }
3813         dev->persist->pdev = pdev;
3814         dev->persist->dev = dev;
3815         pci_set_drvdata(pdev, dev->persist);
3816         priv->pci_dev_data = id->driver_data;
3817         mutex_init(&dev->persist->device_state_mutex);
3818         mutex_init(&dev->persist->interface_state_mutex);
3819         mutex_init(&dev->persist->pci_status_mutex);
3820
3821         ret = devlink_register(devlink, &pdev->dev);
3822         if (ret)
3823                 goto err_persist_free;
3824
3825         ret =  __mlx4_init_one(pdev, id->driver_data, priv);
3826         if (ret)
3827                 goto err_devlink_unregister;
3828
3829         pci_save_state(pdev);
3830         return 0;
3831
3832 err_devlink_unregister:
3833         devlink_unregister(devlink);
3834 err_persist_free:
3835         kfree(dev->persist);
3836 err_devlink_free:
3837         devlink_free(devlink);
3838         return ret;
3839 }
3840
3841 static void mlx4_clean_dev(struct mlx4_dev *dev)
3842 {
3843         struct mlx4_dev_persistent *persist = dev->persist;
3844         struct mlx4_priv *priv = mlx4_priv(dev);
3845         unsigned long   flags = (dev->flags & RESET_PERSIST_MASK_FLAGS);
3846
3847         memset(priv, 0, sizeof(*priv));
3848         priv->dev.persist = persist;
3849         priv->dev.flags = flags;
3850 }
3851
3852 static void mlx4_unload_one(struct pci_dev *pdev)
3853 {
3854         struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3855         struct mlx4_dev  *dev  = persist->dev;
3856         struct mlx4_priv *priv = mlx4_priv(dev);
3857         int               pci_dev_data;
3858         int p, i;
3859
3860         if (priv->removed)
3861                 return;
3862
3863         /* saving current ports type for further use */
3864         for (i = 0; i < dev->caps.num_ports; i++) {
3865                 dev->persist->curr_port_type[i] = dev->caps.port_type[i + 1];
3866                 dev->persist->curr_port_poss_type[i] = dev->caps.
3867                                                        possible_type[i + 1];
3868         }
3869
3870         pci_dev_data = priv->pci_dev_data;
3871
3872         mlx4_stop_sense(dev);
3873         mlx4_unregister_device(dev);
3874
3875         for (p = 1; p <= dev->caps.num_ports; p++) {
3876                 mlx4_cleanup_port_info(&priv->port[p]);
3877                 mlx4_CLOSE_PORT(dev, p);
3878         }
3879
3880         if (mlx4_is_master(dev))
3881                 mlx4_free_resource_tracker(dev,
3882                                            RES_TR_FREE_SLAVES_ONLY);
3883
3884         mlx4_cleanup_default_counters(dev);
3885         if (!mlx4_is_slave(dev))
3886                 mlx4_cleanup_counters_table(dev);
3887         mlx4_cleanup_qp_table(dev);
3888         mlx4_cleanup_srq_table(dev);
3889         mlx4_cleanup_cq_table(dev);
3890         mlx4_cmd_use_polling(dev);
3891         mlx4_cleanup_eq_table(dev);
3892         mlx4_cleanup_mcg_table(dev);
3893         mlx4_cleanup_mr_table(dev);
3894         mlx4_cleanup_xrcd_table(dev);
3895         mlx4_cleanup_pd_table(dev);
3896
3897         if (mlx4_is_master(dev))
3898                 mlx4_free_resource_tracker(dev,
3899                                            RES_TR_FREE_STRUCTS_ONLY);
3900
3901         iounmap(priv->kar);
3902         mlx4_uar_free(dev, &priv->driver_uar);
3903         mlx4_cleanup_uar_table(dev);
3904         if (!mlx4_is_slave(dev))
3905                 mlx4_clear_steering(dev);
3906         mlx4_free_eq_table(dev);
3907         if (mlx4_is_master(dev))
3908                 mlx4_multi_func_cleanup(dev);
3909         mlx4_close_hca(dev);
3910         mlx4_close_fw(dev);
3911         if (mlx4_is_slave(dev))
3912                 mlx4_multi_func_cleanup(dev);
3913         mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
3914
3915         if (dev->flags & MLX4_FLAG_MSI_X)
3916                 pci_disable_msix(pdev);
3917
3918         if (!mlx4_is_slave(dev))
3919                 mlx4_free_ownership(dev);
3920
3921         kfree(dev->caps.qp0_qkey);
3922         kfree(dev->caps.qp0_tunnel);
3923         kfree(dev->caps.qp0_proxy);
3924         kfree(dev->caps.qp1_tunnel);
3925         kfree(dev->caps.qp1_proxy);
3926         kfree(dev->dev_vfs);
3927
3928         mlx4_clean_dev(dev);
3929         priv->pci_dev_data = pci_dev_data;
3930         priv->removed = 1;
3931 }
3932
3933 static void mlx4_remove_one(struct pci_dev *pdev)
3934 {
3935         struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3936         struct mlx4_dev  *dev  = persist->dev;
3937         struct mlx4_priv *priv = mlx4_priv(dev);
3938         struct devlink *devlink = priv_to_devlink(priv);
3939         int active_vfs = 0;
3940
3941         mutex_lock(&persist->interface_state_mutex);
3942         persist->interface_state |= MLX4_INTERFACE_STATE_DELETION;
3943         mutex_unlock(&persist->interface_state_mutex);
3944
3945         /* Disabling SR-IOV is not allowed while there are active vf's */
3946         if (mlx4_is_master(dev) && dev->flags & MLX4_FLAG_SRIOV) {
3947                 active_vfs = mlx4_how_many_lives_vf(dev);
3948                 if (active_vfs) {
3949                         pr_warn("Removing PF when there are active VF's !!\n");
3950                         pr_warn("Will not disable SR-IOV.\n");
3951                 }
3952         }
3953
3954         /* device marked to be under deletion running now without the lock
3955          * letting other tasks to be terminated
3956          */
3957         if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
3958                 mlx4_unload_one(pdev);
3959         else
3960                 mlx4_info(dev, "%s: interface is down\n", __func__);
3961         mlx4_catas_end(dev);
3962         if (dev->flags & MLX4_FLAG_SRIOV && !active_vfs) {
3963                 mlx4_warn(dev, "Disabling SR-IOV\n");
3964                 pci_disable_sriov(pdev);
3965         }
3966
3967         pci_release_regions(pdev);
3968         mlx4_pci_disable_device(dev);
3969         devlink_unregister(devlink);
3970         kfree(dev->persist);
3971         devlink_free(devlink);
3972         pci_set_drvdata(pdev, NULL);
3973 }
3974
3975 static int restore_current_port_types(struct mlx4_dev *dev,
3976                                       enum mlx4_port_type *types,
3977                                       enum mlx4_port_type *poss_types)
3978 {
3979         struct mlx4_priv *priv = mlx4_priv(dev);
3980         int err, i;
3981
3982         mlx4_stop_sense(dev);
3983
3984         mutex_lock(&priv->port_mutex);
3985         for (i = 0; i < dev->caps.num_ports; i++)
3986                 dev->caps.possible_type[i + 1] = poss_types[i];
3987         err = mlx4_change_port_types(dev, types);
3988         mlx4_start_sense(dev);
3989         mutex_unlock(&priv->port_mutex);
3990
3991         return err;
3992 }
3993
3994 int mlx4_restart_one(struct pci_dev *pdev)
3995 {
3996         struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3997         struct mlx4_dev  *dev  = persist->dev;
3998         struct mlx4_priv *priv = mlx4_priv(dev);
3999         int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
4000         int pci_dev_data, err, total_vfs;
4001
4002         pci_dev_data = priv->pci_dev_data;
4003         total_vfs = dev->persist->num_vfs;
4004         memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs));
4005
4006         mlx4_unload_one(pdev);
4007         err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 1);
4008         if (err) {
4009                 mlx4_err(dev, "%s: ERROR: mlx4_load_one failed, pci_name=%s, err=%d\n",
4010                          __func__, pci_name(pdev), err);
4011                 return err;
4012         }
4013
4014         err = restore_current_port_types(dev, dev->persist->curr_port_type,
4015                                          dev->persist->curr_port_poss_type);
4016         if (err)
4017                 mlx4_err(dev, "could not restore original port types (%d)\n",
4018                          err);
4019
4020         return err;
4021 }
4022
4023 static const struct pci_device_id mlx4_pci_table[] = {
4024         /* MT25408 "Hermon" SDR */
4025         { PCI_VDEVICE(MELLANOX, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT },
4026         /* MT25408 "Hermon" DDR */
4027         { PCI_VDEVICE(MELLANOX, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
4028         /* MT25408 "Hermon" QDR */
4029         { PCI_VDEVICE(MELLANOX, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT },
4030         /* MT25408 "Hermon" DDR PCIe gen2 */
4031         { PCI_VDEVICE(MELLANOX, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT },
4032         /* MT25408 "Hermon" QDR PCIe gen2 */
4033         { PCI_VDEVICE(MELLANOX, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT },
4034         /* MT25408 "Hermon" EN 10GigE */
4035         { PCI_VDEVICE(MELLANOX, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT },
4036         /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
4037         { PCI_VDEVICE(MELLANOX, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT },
4038         /* MT25458 ConnectX EN 10GBASE-T 10GigE */
4039         { PCI_VDEVICE(MELLANOX, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT },
4040         /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
4041         { PCI_VDEVICE(MELLANOX, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
4042         /* MT26468 ConnectX EN 10GigE PCIe gen2*/
4043         { PCI_VDEVICE(MELLANOX, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT },
4044         /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
4045         { PCI_VDEVICE(MELLANOX, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT },
4046         /* MT26478 ConnectX2 40GigE PCIe gen2 */
4047         { PCI_VDEVICE(MELLANOX, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT },
4048         /* MT25400 Family [ConnectX-2 Virtual Function] */
4049         { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF },
4050         /* MT27500 Family [ConnectX-3] */
4051         { PCI_VDEVICE(MELLANOX, 0x1003), 0 },
4052         /* MT27500 Family [ConnectX-3 Virtual Function] */
4053         { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF },
4054         { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */
4055         { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */
4056         { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */
4057         { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */
4058         { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */
4059         { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */
4060         { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */
4061         { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */
4062         { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */
4063         { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */
4064         { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */
4065         { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */
4066         { 0, }
4067 };
4068
4069 MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
4070
4071 static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev,
4072                                               pci_channel_state_t state)
4073 {
4074         struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4075
4076         mlx4_err(persist->dev, "mlx4_pci_err_detected was called\n");
4077         mlx4_enter_error_state(persist);
4078
4079         mutex_lock(&persist->interface_state_mutex);
4080         if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
4081                 mlx4_unload_one(pdev);
4082
4083         mutex_unlock(&persist->interface_state_mutex);
4084         if (state == pci_channel_io_perm_failure)
4085                 return PCI_ERS_RESULT_DISCONNECT;
4086
4087         mlx4_pci_disable_device(persist->dev);
4088         return PCI_ERS_RESULT_NEED_RESET;
4089 }
4090
4091 static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev)
4092 {
4093         struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4094         struct mlx4_dev  *dev  = persist->dev;
4095         int err;
4096
4097         mlx4_err(dev, "mlx4_pci_slot_reset was called\n");
4098         err = mlx4_pci_enable_device(dev);
4099         if (err) {
4100                 mlx4_err(dev, "Can not re-enable device, err=%d\n", err);
4101                 return PCI_ERS_RESULT_DISCONNECT;
4102         }
4103
4104         pci_set_master(pdev);
4105         pci_restore_state(pdev);
4106         pci_save_state(pdev);
4107         return PCI_ERS_RESULT_RECOVERED;
4108 }
4109
4110 static void mlx4_pci_resume(struct pci_dev *pdev)
4111 {
4112         struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4113         struct mlx4_dev  *dev  = persist->dev;
4114         struct mlx4_priv *priv = mlx4_priv(dev);
4115         int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
4116         int total_vfs;
4117         int err;
4118
4119         mlx4_err(dev, "%s was called\n", __func__);
4120         total_vfs = dev->persist->num_vfs;
4121         memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs));
4122
4123         mutex_lock(&persist->interface_state_mutex);
4124         if (!(persist->interface_state & MLX4_INTERFACE_STATE_UP)) {
4125                 err = mlx4_load_one(pdev, priv->pci_dev_data, total_vfs, nvfs,
4126                                     priv, 1);
4127                 if (err) {
4128                         mlx4_err(dev, "%s: mlx4_load_one failed, err=%d\n",
4129                                  __func__,  err);
4130                         goto end;
4131                 }
4132
4133                 err = restore_current_port_types(dev, dev->persist->
4134                                                  curr_port_type, dev->persist->
4135                                                  curr_port_poss_type);
4136                 if (err)
4137                         mlx4_err(dev, "could not restore original port types (%d)\n", err);
4138         }
4139 end:
4140         mutex_unlock(&persist->interface_state_mutex);
4141
4142 }
4143
4144 static void mlx4_shutdown(struct pci_dev *pdev)
4145 {
4146         struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4147
4148         mlx4_info(persist->dev, "mlx4_shutdown was called\n");
4149         mutex_lock(&persist->interface_state_mutex);
4150         if (persist->interface_state & MLX4_INTERFACE_STATE_UP) {
4151                 /* Notify mlx4 clients that the kernel is being shut down */
4152                 persist->interface_state |= MLX4_INTERFACE_STATE_SHUTDOWN;
4153                 mlx4_unload_one(pdev);
4154         }
4155         mutex_unlock(&persist->interface_state_mutex);
4156 }
4157
4158 static const struct pci_error_handlers mlx4_err_handler = {
4159         .error_detected = mlx4_pci_err_detected,
4160         .slot_reset     = mlx4_pci_slot_reset,
4161         .resume         = mlx4_pci_resume,
4162 };
4163
4164 static struct pci_driver mlx4_driver = {
4165         .name           = DRV_NAME,
4166         .id_table       = mlx4_pci_table,
4167         .probe          = mlx4_init_one,
4168         .shutdown       = mlx4_shutdown,
4169         .remove         = mlx4_remove_one,
4170         .err_handler    = &mlx4_err_handler,
4171 };
4172
4173 static int __init mlx4_verify_params(void)
4174 {
4175         if ((log_num_mac < 0) || (log_num_mac > 7)) {
4176                 pr_warn("mlx4_core: bad num_mac: %d\n", log_num_mac);
4177                 return -1;
4178         }
4179
4180         if (log_num_vlan != 0)
4181                 pr_warn("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
4182                         MLX4_LOG_NUM_VLANS);
4183
4184         if (use_prio != 0)
4185                 pr_warn("mlx4_core: use_prio - obsolete module param, ignored\n");
4186
4187         if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
4188                 pr_warn("mlx4_core: bad log_mtts_per_seg: %d\n",
4189                         log_mtts_per_seg);
4190                 return -1;
4191         }
4192
4193         /* Check if module param for ports type has legal combination */
4194         if (port_type_array[0] == false && port_type_array[1] == true) {
4195                 pr_warn("Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
4196                 port_type_array[0] = true;
4197         }
4198
4199         if (mlx4_log_num_mgm_entry_size < -7 ||
4200             (mlx4_log_num_mgm_entry_size > 0 &&
4201              (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE ||
4202               mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE))) {
4203                 pr_warn("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not in legal range (-7..0 or %d..%d)\n",
4204                         mlx4_log_num_mgm_entry_size,
4205                         MLX4_MIN_MGM_LOG_ENTRY_SIZE,
4206                         MLX4_MAX_MGM_LOG_ENTRY_SIZE);
4207                 return -1;
4208         }
4209
4210         return 0;
4211 }
4212
4213 static int __init mlx4_init(void)
4214 {
4215         int ret;
4216
4217         if (mlx4_verify_params())
4218                 return -EINVAL;
4219
4220
4221         mlx4_wq = create_singlethread_workqueue("mlx4");
4222         if (!mlx4_wq)
4223                 return -ENOMEM;
4224
4225         ret = pci_register_driver(&mlx4_driver);
4226         if (ret < 0)
4227                 destroy_workqueue(mlx4_wq);
4228         return ret < 0 ? ret : 0;
4229 }
4230
4231 static void __exit mlx4_cleanup(void)
4232 {
4233         pci_unregister_driver(&mlx4_driver);
4234         destroy_workqueue(mlx4_wq);
4235 }
4236
4237 module_init(mlx4_init);
4238 module_exit(mlx4_cleanup);