2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/ptp_clock_kernel.h>
40 #include <linux/mlx5/driver.h>
41 #include <linux/mlx5/qp.h>
42 #include <linux/mlx5/cq.h>
43 #include <linux/mlx5/port.h>
44 #include <linux/mlx5/vport.h>
45 #include <linux/mlx5/transobj.h>
46 #include <linux/rhashtable.h>
48 #include "mlx5_core.h"
51 #define MLX5E_MAX_NUM_TC 8
53 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
54 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
55 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
57 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1
58 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
59 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd
61 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x1
62 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW 0x4
63 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW 0x6
65 #define MLX5_MPWRQ_LOG_NUM_STRIDES 11 /* >= 9, HW restriction */
66 #define MLX5_MPWRQ_LOG_STRIDE_SIZE 6 /* >= 6, HW restriction */
67 #define MLX5_MPWRQ_NUM_STRIDES BIT(MLX5_MPWRQ_LOG_NUM_STRIDES)
68 #define MLX5_MPWRQ_STRIDE_SIZE BIT(MLX5_MPWRQ_LOG_STRIDE_SIZE)
69 #define MLX5_MPWRQ_LOG_WQE_SZ (MLX5_MPWRQ_LOG_NUM_STRIDES +\
70 MLX5_MPWRQ_LOG_STRIDE_SIZE)
71 #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
72 MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
73 #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
74 #define MLX5_MPWRQ_STRIDES_PER_PAGE (MLX5_MPWRQ_NUM_STRIDES >> \
75 MLX5_MPWRQ_WQE_PAGE_ORDER)
76 #define MLX5_CHANNEL_MAX_NUM_MTTS (ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8) * \
77 BIT(MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW))
78 #define MLX5_UMR_ALIGN (2048)
79 #define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD (128)
81 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
82 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
83 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
84 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
85 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
86 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
87 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
89 #define MLX5E_LOG_INDIR_RQT_SIZE 0x7
90 #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE)
91 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1)
92 #define MLX5E_TX_CQ_POLL_BUDGET 128
93 #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */
94 #define MLX5E_SQ_BF_BUDGET 16
96 #define MLX5E_NUM_MAIN_GROUPS 9
98 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
101 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
102 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
105 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
110 static inline int mlx5_min_log_rq_size(int wq_type)
113 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
114 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
116 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE;
120 static inline int mlx5_max_log_rq_size(int wq_type)
123 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
124 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW;
126 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE;
130 struct mlx5e_tx_wqe {
131 struct mlx5_wqe_ctrl_seg ctrl;
132 struct mlx5_wqe_eth_seg eth;
135 struct mlx5e_rx_wqe {
136 struct mlx5_wqe_srq_next_seg next;
137 struct mlx5_wqe_data_seg data;
140 struct mlx5e_umr_wqe {
141 struct mlx5_wqe_ctrl_seg ctrl;
142 struct mlx5_wqe_umr_ctrl_seg uctrl;
143 struct mlx5_mkey_seg mkc;
144 struct mlx5_wqe_data_seg data;
147 #ifdef CONFIG_MLX5_CORE_EN_DCB
148 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
149 #define MLX5E_MIN_BW_ALLOC 1 /* Min percentage of BW allocation */
152 struct mlx5e_params {
158 u16 rx_cq_moderation_usec;
159 u16 rx_cq_moderation_pkts;
160 u16 tx_cq_moderation_usec;
161 u16 tx_cq_moderation_pkts;
167 u8 toeplitz_hash_key[40];
168 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
169 bool vlan_strip_disable;
170 #ifdef CONFIG_MLX5_CORE_EN_DCB
175 struct mlx5e_tstamp {
177 struct cyclecounter cycles;
178 struct timecounter clock;
179 struct hwtstamp_config hwtstamp_config;
181 unsigned long overflow_period;
182 struct delayed_work overflow_work;
183 struct mlx5_core_dev *mdev;
184 struct ptp_clock *ptp;
185 struct ptp_clock_info ptp_info;
189 MLX5E_RQ_STATE_POST_WQES_ENABLE,
190 MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS,
194 /* data path - accessed per cqe */
197 /* data path - accessed per napi poll */
198 struct napi_struct *napi;
199 struct mlx5_core_cq mcq;
200 struct mlx5e_channel *channel;
201 struct mlx5e_priv *priv;
204 struct mlx5_wq_ctrl wq_ctrl;
205 } ____cacheline_aligned_in_smp;
208 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq *rq,
209 struct mlx5_cqe64 *cqe);
210 typedef int (*mlx5e_fp_alloc_wqe)(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe,
213 struct mlx5e_dma_info {
220 struct mlx5_wq_ll wq;
222 struct sk_buff **skb;
223 struct mlx5e_mpw_info *wqe_info;
228 struct net_device *netdev;
229 struct mlx5e_tstamp *tstamp;
230 struct mlx5e_rq_stats stats;
232 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
233 mlx5e_fp_alloc_wqe alloc_wqe;
239 struct mlx5_wq_ctrl wq_ctrl;
242 struct mlx5e_channel *channel;
243 struct mlx5e_priv *priv;
244 } ____cacheline_aligned_in_smp;
246 struct mlx5e_umr_dma_info {
248 __be64 *mtt_no_align;
250 struct mlx5e_dma_info *dma_info;
253 struct mlx5e_mpw_info {
255 struct mlx5e_dma_info dma_info;
256 struct mlx5e_umr_dma_info umr;
258 u16 consumed_strides;
259 u16 skbs_frags[MLX5_MPWRQ_PAGES_PER_WQE];
261 void (*dma_pre_sync)(struct device *pdev,
262 struct mlx5e_mpw_info *wi,
263 u32 wqe_offset, u32 len);
264 void (*add_skb_frag)(struct device *pdev,
266 struct mlx5e_mpw_info *wi,
267 u32 page_idx, u32 frag_offset, u32 len);
268 void (*copy_skb_header)(struct device *pdev,
270 struct mlx5e_mpw_info *wi,
271 u32 page_idx, u32 offset,
273 void (*free_wqe)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi);
276 struct mlx5e_tx_wqe_info {
282 enum mlx5e_dma_map_type {
283 MLX5E_DMA_MAP_SINGLE,
287 struct mlx5e_sq_dma {
290 enum mlx5e_dma_map_type type;
294 MLX5E_SQ_STATE_WAKE_TXQ_ENABLE,
295 MLX5E_SQ_STATE_BF_ENABLE,
298 struct mlx5e_ico_wqe_info {
306 /* dirtied @completion */
311 u16 pc ____cacheline_aligned_in_smp;
316 struct mlx5e_sq_stats stats;
320 /* pointers to per packet info: write@xmit, read@completion */
321 struct sk_buff **skb;
322 struct mlx5e_sq_dma *dma_fifo;
323 struct mlx5e_tx_wqe_info *wqe_info;
326 struct mlx5_wq_cyc wq;
328 void __iomem *uar_map;
329 struct netdev_queue *txq;
335 struct mlx5e_tstamp *tstamp;
340 struct mlx5_wq_ctrl wq_ctrl;
342 struct mlx5e_channel *channel;
344 struct mlx5e_ico_wqe_info *ico_wqe_info;
345 } ____cacheline_aligned_in_smp;
347 static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n)
349 return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) ||
354 MLX5E_CHANNEL_NAPI_SCHED = 1,
357 struct mlx5e_channel {
360 struct mlx5e_sq sq[MLX5E_MAX_NUM_TC];
361 struct mlx5e_sq icosq; /* internal control operations */
362 struct napi_struct napi;
364 struct net_device *netdev;
370 struct mlx5e_priv *priv;
375 enum mlx5e_traffic_types {
380 MLX5E_TT_IPV4_IPSEC_AH,
381 MLX5E_TT_IPV6_IPSEC_AH,
382 MLX5E_TT_IPV4_IPSEC_ESP,
383 MLX5E_TT_IPV6_IPSEC_ESP,
388 MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY,
392 MLX5E_STATE_ASYNC_EVENTS_ENABLE,
394 MLX5E_STATE_DESTROYING,
397 struct mlx5e_vxlan_db {
398 spinlock_t lock; /* protect vxlan table */
399 struct radix_tree_root tree;
402 struct mlx5e_l2_rule {
403 u8 addr[ETH_ALEN + 2];
404 struct mlx5_flow_rule *rule;
407 struct mlx5e_flow_table {
409 struct mlx5_flow_table *t;
410 struct mlx5_flow_group **g;
413 #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE)
415 struct mlx5e_tc_table {
416 struct mlx5_flow_table *t;
418 struct rhashtable_params ht_params;
419 struct rhashtable ht;
422 struct mlx5e_vlan_table {
423 struct mlx5e_flow_table ft;
424 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
425 struct mlx5_flow_rule *active_vlans_rule[VLAN_N_VID];
426 struct mlx5_flow_rule *untagged_rule;
427 struct mlx5_flow_rule *any_vlan_rule;
428 bool filter_disabled;
431 struct mlx5e_l2_table {
432 struct mlx5e_flow_table ft;
433 struct hlist_head netdev_uc[MLX5E_L2_ADDR_HASH_SIZE];
434 struct hlist_head netdev_mc[MLX5E_L2_ADDR_HASH_SIZE];
435 struct mlx5e_l2_rule broadcast;
436 struct mlx5e_l2_rule allmulti;
437 struct mlx5e_l2_rule promisc;
438 bool broadcast_enabled;
439 bool allmulti_enabled;
440 bool promisc_enabled;
443 /* L3/L4 traffic type classifier */
444 struct mlx5e_ttc_table {
445 struct mlx5e_flow_table ft;
446 struct mlx5_flow_rule *rules[MLX5E_NUM_TT];
449 struct mlx5e_flow_steering {
450 struct mlx5_flow_namespace *ns;
451 struct mlx5e_tc_table tc;
452 struct mlx5e_vlan_table vlan;
453 struct mlx5e_l2_table l2;
454 struct mlx5e_ttc_table ttc;
457 struct mlx5e_direct_tir {
468 /* priv data path fields - start */
469 struct mlx5e_sq **txq_to_sq_map;
470 int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
471 /* priv data path fields - end */
474 struct mutex state_lock; /* Protects Interface state */
475 struct mlx5_uar cq_uar;
478 struct mlx5_core_mkey mkey;
479 struct mlx5_core_mkey umr_mkey;
480 struct mlx5e_rq drop_rq;
482 struct mlx5e_channel **channel;
483 u32 tisn[MLX5E_MAX_NUM_TC];
485 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
486 struct mlx5e_direct_tir direct_tir[MLX5E_MAX_NUM_CHANNELS];
488 struct mlx5e_flow_steering fs;
489 struct mlx5e_vxlan_db vxlan;
491 struct mlx5e_params params;
492 struct work_struct update_carrier_work;
493 struct work_struct set_rx_mode_work;
494 struct delayed_work update_stats_work;
496 struct mlx5_core_dev *mdev;
497 struct net_device *netdev;
498 struct mlx5e_stats stats;
499 struct mlx5e_tstamp tstamp;
503 enum mlx5e_link_mode {
504 MLX5E_1000BASE_CX_SGMII = 0,
505 MLX5E_1000BASE_KX = 1,
506 MLX5E_10GBASE_CX4 = 2,
507 MLX5E_10GBASE_KX4 = 3,
508 MLX5E_10GBASE_KR = 4,
509 MLX5E_20GBASE_KR2 = 5,
510 MLX5E_40GBASE_CR4 = 6,
511 MLX5E_40GBASE_KR4 = 7,
512 MLX5E_56GBASE_R4 = 8,
513 MLX5E_10GBASE_CR = 12,
514 MLX5E_10GBASE_SR = 13,
515 MLX5E_10GBASE_ER = 14,
516 MLX5E_40GBASE_SR4 = 15,
517 MLX5E_40GBASE_LR4 = 16,
518 MLX5E_100GBASE_CR4 = 20,
519 MLX5E_100GBASE_SR4 = 21,
520 MLX5E_100GBASE_KR4 = 22,
521 MLX5E_100GBASE_LR4 = 23,
522 MLX5E_100BASE_TX = 24,
523 MLX5E_1000BASE_T = 25,
524 MLX5E_10GBASE_T = 26,
525 MLX5E_25GBASE_CR = 27,
526 MLX5E_25GBASE_KR = 28,
527 MLX5E_25GBASE_SR = 29,
528 MLX5E_50GBASE_CR2 = 30,
529 MLX5E_50GBASE_KR2 = 31,
530 MLX5E_LINK_MODES_NUMBER,
533 #define MLX5E_PROT_MASK(link_mode) (1 << link_mode)
535 void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw);
536 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
537 void *accel_priv, select_queue_fallback_t fallback);
538 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);
540 void mlx5e_completion_event(struct mlx5_core_cq *mcq);
541 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
542 int mlx5e_napi_poll(struct napi_struct *napi, int budget);
543 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget);
544 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
546 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
547 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
548 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
549 int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
550 int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
551 void mlx5e_post_rx_fragmented_mpwqe(struct mlx5e_rq *rq);
552 void mlx5e_complete_rx_linear_mpwqe(struct mlx5e_rq *rq,
553 struct mlx5_cqe64 *cqe,
555 struct mlx5e_mpw_info *wi,
556 struct sk_buff *skb);
557 void mlx5e_complete_rx_fragmented_mpwqe(struct mlx5e_rq *rq,
558 struct mlx5_cqe64 *cqe,
560 struct mlx5e_mpw_info *wi,
561 struct sk_buff *skb);
562 void mlx5e_free_rx_linear_mpwqe(struct mlx5e_rq *rq,
563 struct mlx5e_mpw_info *wi);
564 void mlx5e_free_rx_fragmented_mpwqe(struct mlx5e_rq *rq,
565 struct mlx5e_mpw_info *wi);
566 struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq);
568 void mlx5e_update_stats(struct mlx5e_priv *priv);
570 int mlx5e_create_flow_steering(struct mlx5e_priv *priv);
571 void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv);
572 void mlx5e_init_l2_addr(struct mlx5e_priv *priv);
573 void mlx5e_set_rx_mode_work(struct work_struct *work);
575 void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp,
576 struct skb_shared_hwtstamps *hwts);
577 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
578 void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv);
579 int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr);
580 int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr);
582 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
584 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
586 void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv);
587 void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv);
589 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd);
591 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix);
592 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv);
594 int mlx5e_open_locked(struct net_device *netdev);
595 int mlx5e_close_locked(struct net_device *netdev);
596 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
597 u32 *indirection_rqt, int len,
600 static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq,
601 struct mlx5_wqe_ctrl_seg *ctrl, int bf_sz)
603 u16 ofst = MLX5_BF_OFFSET + sq->bf_offset;
605 /* ensure wqe is visible to device before updating doorbell record */
608 *sq->wq.db = cpu_to_be32(sq->pc);
610 /* ensure doorbell record is visible to device before ringing the
615 __iowrite64_copy(sq->uar_map + ofst, ctrl, bf_sz);
617 mlx5_write64((__be32 *)ctrl, sq->uar_map + ofst, NULL);
618 /* flush the write-combining mapped buffer */
621 sq->bf_offset ^= sq->bf_buf_size;
624 static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
626 struct mlx5_core_cq *mcq;
629 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc);
632 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
634 return min_t(int, mdev->priv.eq_table.num_comp_vectors,
635 MLX5E_MAX_NUM_CHANNELS);
638 static inline int mlx5e_get_mtt_octw(int npages)
640 return ALIGN(npages, 8) / 2;
643 extern const struct ethtool_ops mlx5e_ethtool_ops;
644 #ifdef CONFIG_MLX5_CORE_EN_DCB
645 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
646 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets);
649 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev);
651 #endif /* __MLX5_EN_H__ */