2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/ptp_clock_kernel.h>
40 #include <linux/mlx5/driver.h>
41 #include <linux/mlx5/qp.h>
42 #include <linux/mlx5/cq.h>
43 #include <linux/mlx5/port.h>
44 #include <linux/mlx5/vport.h>
45 #include <linux/mlx5/transobj.h>
46 #include <linux/rhashtable.h>
47 #include <net/switchdev.h>
49 #include "mlx5_core.h"
52 #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
54 #define MLX5E_MAX_NUM_TC 8
56 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
57 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
58 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
60 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1
61 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
62 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd
64 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x1
65 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW 0x4
66 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW 0x6
68 #define MLX5_MPWRQ_LOG_STRIDE_SIZE 6 /* >= 6, HW restriction */
69 #define MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS 8 /* >= 6, HW restriction */
70 #define MLX5_MPWRQ_LOG_WQE_SZ 17
71 #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
72 MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
73 #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
74 #define MLX5_MPWRQ_STRIDES_PER_PAGE (MLX5_MPWRQ_NUM_STRIDES >> \
75 MLX5_MPWRQ_WQE_PAGE_ORDER)
76 #define MLX5_CHANNEL_MAX_NUM_MTTS (ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8) * \
77 BIT(MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW))
78 #define MLX5_UMR_ALIGN (2048)
79 #define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD (128)
81 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
82 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
83 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
84 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
85 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
86 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
87 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
88 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
90 #define MLX5E_LOG_INDIR_RQT_SIZE 0x7
91 #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE)
92 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1)
93 #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC)
94 #define MLX5E_TX_CQ_POLL_BUDGET 128
95 #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */
96 #define MLX5E_SQ_BF_BUDGET 16
98 #define MLX5E_NUM_MAIN_GROUPS 9
100 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
103 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
104 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
107 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
112 static inline int mlx5_min_log_rq_size(int wq_type)
115 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
116 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
118 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE;
122 static inline int mlx5_max_log_rq_size(int wq_type)
125 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
126 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW;
128 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE;
132 struct mlx5e_tx_wqe {
133 struct mlx5_wqe_ctrl_seg ctrl;
134 struct mlx5_wqe_eth_seg eth;
137 struct mlx5e_rx_wqe {
138 struct mlx5_wqe_srq_next_seg next;
139 struct mlx5_wqe_data_seg data;
142 struct mlx5e_umr_wqe {
143 struct mlx5_wqe_ctrl_seg ctrl;
144 struct mlx5_wqe_umr_ctrl_seg uctrl;
145 struct mlx5_mkey_seg mkc;
146 struct mlx5_wqe_data_seg data;
149 static const char mlx5e_priv_flags[][ETH_GSTRING_LEN] = {
153 enum mlx5e_priv_flag {
154 MLX5E_PFLAG_RX_CQE_BASED_MODER = (1 << 0),
157 #define MLX5E_SET_PRIV_FLAG(priv, pflag, enable) \
160 priv->pflags |= pflag; \
162 priv->pflags &= ~pflag; \
165 #ifdef CONFIG_MLX5_CORE_EN_DCB
166 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
167 #define MLX5E_MIN_BW_ALLOC 1 /* Min percentage of BW allocation */
170 struct mlx5e_cq_moder {
175 struct mlx5e_params {
178 u8 mpwqe_log_stride_sz;
179 u8 mpwqe_log_num_strides;
183 u8 rx_cq_period_mode;
184 bool rx_cqe_compress_admin;
185 bool rx_cqe_compress;
186 struct mlx5e_cq_moder rx_cq_moderation;
187 struct mlx5e_cq_moder tx_cq_moderation;
193 u8 toeplitz_hash_key[40];
194 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
195 bool vlan_strip_disable;
196 #ifdef CONFIG_MLX5_CORE_EN_DCB
202 struct mlx5e_tstamp {
204 struct cyclecounter cycles;
205 struct timecounter clock;
206 struct hwtstamp_config hwtstamp_config;
208 unsigned long overflow_period;
209 struct delayed_work overflow_work;
210 struct mlx5_core_dev *mdev;
211 struct ptp_clock *ptp;
212 struct ptp_clock_info ptp_info;
216 MLX5E_RQ_STATE_POST_WQES_ENABLE,
217 MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS,
222 /* data path - accessed per cqe */
225 /* data path - accessed per napi poll */
227 struct napi_struct *napi;
228 struct mlx5_core_cq mcq;
229 struct mlx5e_channel *channel;
230 struct mlx5e_priv *priv;
232 /* cqe decompression */
233 struct mlx5_cqe64 title;
234 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
237 u16 decmprs_wqe_counter;
240 struct mlx5_wq_ctrl wq_ctrl;
241 } ____cacheline_aligned_in_smp;
244 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq *rq,
245 struct mlx5_cqe64 *cqe);
246 typedef int (*mlx5e_fp_alloc_wqe)(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe,
249 struct mlx5e_dma_info {
254 struct mlx5e_rx_am_stats {
255 int ppms; /* packets per msec */
256 int epms; /* events per msec */
259 struct mlx5e_rx_am_sample {
261 unsigned int pkt_ctr;
265 struct mlx5e_rx_am { /* Adaptive Moderation */
267 struct mlx5e_rx_am_stats prev_stats;
268 struct mlx5e_rx_am_sample start_sample;
269 struct work_struct work;
280 struct mlx5_wq_ll wq;
282 struct sk_buff **skb;
283 struct mlx5e_mpw_info *wqe_info;
288 struct net_device *netdev;
289 struct mlx5e_tstamp *tstamp;
290 struct mlx5e_rq_stats stats;
292 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
293 mlx5e_fp_alloc_wqe alloc_wqe;
298 struct mlx5e_rx_am am; /* Adaptive Moderation */
301 struct mlx5_wq_ctrl wq_ctrl;
304 u32 mpwqe_num_strides;
306 struct mlx5e_channel *channel;
307 struct mlx5e_priv *priv;
308 } ____cacheline_aligned_in_smp;
310 struct mlx5e_umr_dma_info {
312 __be64 *mtt_no_align;
314 struct mlx5e_dma_info *dma_info;
317 struct mlx5e_mpw_info {
319 struct mlx5e_dma_info dma_info;
320 struct mlx5e_umr_dma_info umr;
322 u16 consumed_strides;
323 u16 skbs_frags[MLX5_MPWRQ_PAGES_PER_WQE];
325 void (*dma_pre_sync)(struct device *pdev,
326 struct mlx5e_mpw_info *wi,
327 u32 wqe_offset, u32 len);
328 void (*add_skb_frag)(struct mlx5e_rq *rq,
330 struct mlx5e_mpw_info *wi,
331 u32 page_idx, u32 frag_offset, u32 len);
332 void (*copy_skb_header)(struct device *pdev,
334 struct mlx5e_mpw_info *wi,
335 u32 page_idx, u32 offset,
337 void (*free_wqe)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi);
340 struct mlx5e_tx_wqe_info {
346 enum mlx5e_dma_map_type {
347 MLX5E_DMA_MAP_SINGLE,
351 struct mlx5e_sq_dma {
354 enum mlx5e_dma_map_type type;
358 MLX5E_SQ_STATE_WAKE_TXQ_ENABLE,
359 MLX5E_SQ_STATE_BF_ENABLE,
362 struct mlx5e_ico_wqe_info {
370 /* dirtied @completion */
375 u16 pc ____cacheline_aligned_in_smp;
380 struct mlx5e_sq_stats stats;
384 /* pointers to per packet info: write@xmit, read@completion */
385 struct sk_buff **skb;
386 struct mlx5e_sq_dma *dma_fifo;
387 struct mlx5e_tx_wqe_info *wqe_info;
390 struct mlx5_wq_cyc wq;
392 void __iomem *uar_map;
393 struct netdev_queue *txq;
399 struct mlx5e_tstamp *tstamp;
404 struct mlx5_wq_ctrl wq_ctrl;
406 struct mlx5e_channel *channel;
408 struct mlx5e_ico_wqe_info *ico_wqe_info;
410 } ____cacheline_aligned_in_smp;
412 static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n)
414 return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) ||
419 MLX5E_CHANNEL_NAPI_SCHED = 1,
422 struct mlx5e_channel {
425 struct mlx5e_sq sq[MLX5E_MAX_NUM_TC];
426 struct mlx5e_sq icosq; /* internal control operations */
427 struct napi_struct napi;
429 struct net_device *netdev;
435 struct mlx5e_priv *priv;
440 enum mlx5e_traffic_types {
445 MLX5E_TT_IPV4_IPSEC_AH,
446 MLX5E_TT_IPV6_IPSEC_AH,
447 MLX5E_TT_IPV4_IPSEC_ESP,
448 MLX5E_TT_IPV6_IPSEC_ESP,
453 MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY,
457 MLX5E_STATE_ASYNC_EVENTS_ENABLED,
459 MLX5E_STATE_DESTROYING,
462 struct mlx5e_vxlan_db {
463 spinlock_t lock; /* protect vxlan table */
464 struct radix_tree_root tree;
467 struct mlx5e_l2_rule {
468 u8 addr[ETH_ALEN + 2];
469 struct mlx5_flow_rule *rule;
472 struct mlx5e_flow_table {
474 struct mlx5_flow_table *t;
475 struct mlx5_flow_group **g;
478 #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE)
480 struct mlx5e_tc_table {
481 struct mlx5_flow_table *t;
483 struct rhashtable_params ht_params;
484 struct rhashtable ht;
487 struct mlx5e_vlan_table {
488 struct mlx5e_flow_table ft;
489 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
490 struct mlx5_flow_rule *active_vlans_rule[VLAN_N_VID];
491 struct mlx5_flow_rule *untagged_rule;
492 struct mlx5_flow_rule *any_vlan_rule;
493 bool filter_disabled;
496 struct mlx5e_l2_table {
497 struct mlx5e_flow_table ft;
498 struct hlist_head netdev_uc[MLX5E_L2_ADDR_HASH_SIZE];
499 struct hlist_head netdev_mc[MLX5E_L2_ADDR_HASH_SIZE];
500 struct mlx5e_l2_rule broadcast;
501 struct mlx5e_l2_rule allmulti;
502 struct mlx5e_l2_rule promisc;
503 bool broadcast_enabled;
504 bool allmulti_enabled;
505 bool promisc_enabled;
508 /* L3/L4 traffic type classifier */
509 struct mlx5e_ttc_table {
510 struct mlx5e_flow_table ft;
511 struct mlx5_flow_rule *rules[MLX5E_NUM_TT];
514 #define ARFS_HASH_SHIFT BITS_PER_BYTE
515 #define ARFS_HASH_SIZE BIT(BITS_PER_BYTE)
517 struct mlx5e_flow_table ft;
518 struct mlx5_flow_rule *default_rule;
519 struct hlist_head rules_hash[ARFS_HASH_SIZE];
530 struct mlx5e_arfs_tables {
531 struct arfs_table arfs_tables[ARFS_NUM_TYPES];
532 /* Protect aRFS rules list */
533 spinlock_t arfs_lock;
534 struct list_head rules;
536 struct workqueue_struct *wq;
541 MLX5E_VLAN_FT_LEVEL = 0,
547 struct mlx5e_ethtool_table {
548 struct mlx5_flow_table *ft;
552 #define ETHTOOL_NUM_L3_L4_FTS 7
553 #define ETHTOOL_NUM_L2_FTS 4
555 struct mlx5e_ethtool_steering {
556 struct mlx5e_ethtool_table l3_l4_ft[ETHTOOL_NUM_L3_L4_FTS];
557 struct mlx5e_ethtool_table l2_ft[ETHTOOL_NUM_L2_FTS];
558 struct list_head rules;
562 struct mlx5e_flow_steering {
563 struct mlx5_flow_namespace *ns;
564 struct mlx5e_ethtool_steering ethtool;
565 struct mlx5e_tc_table tc;
566 struct mlx5e_vlan_table vlan;
567 struct mlx5e_l2_table l2;
568 struct mlx5e_ttc_table ttc;
569 struct mlx5e_arfs_tables arfs;
579 struct mlx5e_rqt rqt;
580 struct list_head list;
588 struct mlx5e_profile {
589 void (*init)(struct mlx5_core_dev *mdev,
590 struct net_device *netdev,
591 const struct mlx5e_profile *profile, void *ppriv);
592 void (*cleanup)(struct mlx5e_priv *priv);
593 int (*init_rx)(struct mlx5e_priv *priv);
594 void (*cleanup_rx)(struct mlx5e_priv *priv);
595 int (*init_tx)(struct mlx5e_priv *priv);
596 void (*cleanup_tx)(struct mlx5e_priv *priv);
597 void (*enable)(struct mlx5e_priv *priv);
598 void (*disable)(struct mlx5e_priv *priv);
599 void (*update_stats)(struct mlx5e_priv *priv);
600 int (*max_nch)(struct mlx5_core_dev *mdev);
605 /* priv data path fields - start */
606 struct mlx5e_sq **txq_to_sq_map;
607 int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
608 /* priv data path fields - end */
611 struct mutex state_lock; /* Protects Interface state */
612 struct mlx5_core_mkey umr_mkey;
613 struct mlx5e_rq drop_rq;
615 struct mlx5e_channel **channel;
616 u32 tisn[MLX5E_MAX_NUM_TC];
617 struct mlx5e_rqt indir_rqt;
618 struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS];
619 struct mlx5e_tir direct_tir[MLX5E_MAX_NUM_CHANNELS];
620 u32 tx_rates[MLX5E_MAX_NUM_SQS];
622 struct mlx5e_flow_steering fs;
623 struct mlx5e_vxlan_db vxlan;
625 struct mlx5e_params params;
626 struct workqueue_struct *wq;
627 struct work_struct update_carrier_work;
628 struct work_struct set_rx_mode_work;
629 struct delayed_work update_stats_work;
632 struct mlx5_core_dev *mdev;
633 struct net_device *netdev;
634 struct mlx5e_stats stats;
635 struct mlx5e_tstamp tstamp;
637 const struct mlx5e_profile *profile;
641 enum mlx5e_link_mode {
642 MLX5E_1000BASE_CX_SGMII = 0,
643 MLX5E_1000BASE_KX = 1,
644 MLX5E_10GBASE_CX4 = 2,
645 MLX5E_10GBASE_KX4 = 3,
646 MLX5E_10GBASE_KR = 4,
647 MLX5E_20GBASE_KR2 = 5,
648 MLX5E_40GBASE_CR4 = 6,
649 MLX5E_40GBASE_KR4 = 7,
650 MLX5E_56GBASE_R4 = 8,
651 MLX5E_10GBASE_CR = 12,
652 MLX5E_10GBASE_SR = 13,
653 MLX5E_10GBASE_ER = 14,
654 MLX5E_40GBASE_SR4 = 15,
655 MLX5E_40GBASE_LR4 = 16,
656 MLX5E_50GBASE_SR2 = 18,
657 MLX5E_100GBASE_CR4 = 20,
658 MLX5E_100GBASE_SR4 = 21,
659 MLX5E_100GBASE_KR4 = 22,
660 MLX5E_100GBASE_LR4 = 23,
661 MLX5E_100BASE_TX = 24,
662 MLX5E_1000BASE_T = 25,
663 MLX5E_10GBASE_T = 26,
664 MLX5E_25GBASE_CR = 27,
665 MLX5E_25GBASE_KR = 28,
666 MLX5E_25GBASE_SR = 29,
667 MLX5E_50GBASE_CR2 = 30,
668 MLX5E_50GBASE_KR2 = 31,
669 MLX5E_LINK_MODES_NUMBER,
672 #define MLX5E_PROT_MASK(link_mode) (1 << link_mode)
675 void mlx5e_build_ptys2ethtool_map(void);
677 void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw);
678 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
679 void *accel_priv, select_queue_fallback_t fallback);
680 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);
682 void mlx5e_completion_event(struct mlx5_core_cq *mcq);
683 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
684 int mlx5e_napi_poll(struct napi_struct *napi, int budget);
685 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget);
686 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
688 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
689 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
690 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
691 int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
692 int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
693 void mlx5e_post_rx_fragmented_mpwqe(struct mlx5e_rq *rq);
694 void mlx5e_complete_rx_linear_mpwqe(struct mlx5e_rq *rq,
695 struct mlx5_cqe64 *cqe,
697 struct mlx5e_mpw_info *wi,
698 struct sk_buff *skb);
699 void mlx5e_complete_rx_fragmented_mpwqe(struct mlx5e_rq *rq,
700 struct mlx5_cqe64 *cqe,
702 struct mlx5e_mpw_info *wi,
703 struct sk_buff *skb);
704 void mlx5e_free_rx_linear_mpwqe(struct mlx5e_rq *rq,
705 struct mlx5e_mpw_info *wi);
706 void mlx5e_free_rx_fragmented_mpwqe(struct mlx5e_rq *rq,
707 struct mlx5e_mpw_info *wi);
708 struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq);
710 void mlx5e_rx_am(struct mlx5e_rq *rq);
711 void mlx5e_rx_am_work(struct work_struct *work);
712 struct mlx5e_cq_moder mlx5e_am_get_def_profile(u8 rx_cq_period_mode);
714 void mlx5e_update_stats(struct mlx5e_priv *priv);
716 int mlx5e_create_flow_steering(struct mlx5e_priv *priv);
717 void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv);
718 void mlx5e_init_l2_addr(struct mlx5e_priv *priv);
719 void mlx5e_destroy_flow_table(struct mlx5e_flow_table *ft);
720 int mlx5e_ethtool_flow_replace(struct mlx5e_priv *priv,
721 struct ethtool_rx_flow_spec *fs);
722 int mlx5e_ethtool_flow_remove(struct mlx5e_priv *priv,
724 void mlx5e_ethtool_init_steering(struct mlx5e_priv *priv);
725 void mlx5e_ethtool_cleanup_steering(struct mlx5e_priv *priv);
726 void mlx5e_set_rx_mode_work(struct work_struct *work);
728 void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp,
729 struct skb_shared_hwtstamps *hwts);
730 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
731 void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv);
732 int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr);
733 int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr);
734 void mlx5e_modify_rx_cqe_compression(struct mlx5e_priv *priv, bool val);
736 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
738 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
740 void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv);
741 void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv);
743 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd);
745 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix);
746 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv);
748 int mlx5e_open_locked(struct net_device *netdev);
749 int mlx5e_close_locked(struct net_device *netdev);
750 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
751 u32 *indirection_rqt, int len,
753 int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed);
755 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params,
758 static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq,
759 struct mlx5_wqe_ctrl_seg *ctrl, int bf_sz)
761 u16 ofst = MLX5_BF_OFFSET + sq->bf_offset;
763 /* ensure wqe is visible to device before updating doorbell record */
766 *sq->wq.db = cpu_to_be32(sq->pc);
768 /* ensure doorbell record is visible to device before ringing the
773 __iowrite64_copy(sq->uar_map + ofst, ctrl, bf_sz);
775 mlx5_write64((__be32 *)ctrl, sq->uar_map + ofst, NULL);
776 /* flush the write-combining mapped buffer */
779 sq->bf_offset ^= sq->bf_buf_size;
782 static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
784 struct mlx5_core_cq *mcq;
787 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc);
790 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
792 return min_t(int, mdev->priv.eq_table.num_comp_vectors,
793 MLX5E_MAX_NUM_CHANNELS);
796 static inline int mlx5e_get_mtt_octw(int npages)
798 return ALIGN(npages, 8) / 2;
801 extern const struct ethtool_ops mlx5e_ethtool_ops;
802 #ifdef CONFIG_MLX5_CORE_EN_DCB
803 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
804 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets);
807 #ifndef CONFIG_RFS_ACCEL
808 static inline int mlx5e_arfs_create_tables(struct mlx5e_priv *priv)
813 static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv) {}
815 static inline int mlx5e_arfs_enable(struct mlx5e_priv *priv)
820 static inline int mlx5e_arfs_disable(struct mlx5e_priv *priv)
825 int mlx5e_arfs_create_tables(struct mlx5e_priv *priv);
826 void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv);
827 int mlx5e_arfs_enable(struct mlx5e_priv *priv);
828 int mlx5e_arfs_disable(struct mlx5e_priv *priv);
829 int mlx5e_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
830 u16 rxq_index, u32 flow_id);
833 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev);
834 int mlx5e_create_tir(struct mlx5_core_dev *mdev,
835 struct mlx5e_tir *tir, u32 *in, int inlen);
836 void mlx5e_destroy_tir(struct mlx5_core_dev *mdev,
837 struct mlx5e_tir *tir);
838 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev);
839 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev);
840 int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5_core_dev *mdev);
842 struct mlx5_eswitch_rep;
843 int mlx5e_vport_rep_load(struct mlx5_eswitch *esw,
844 struct mlx5_eswitch_rep *rep);
845 void mlx5e_vport_rep_unload(struct mlx5_eswitch *esw,
846 struct mlx5_eswitch_rep *rep);
847 int mlx5e_nic_rep_load(struct mlx5_eswitch *esw, struct mlx5_eswitch_rep *rep);
848 void mlx5e_nic_rep_unload(struct mlx5_eswitch *esw,
849 struct mlx5_eswitch_rep *rep);
850 int mlx5e_add_sqs_fwd_rules(struct mlx5e_priv *priv);
851 void mlx5e_remove_sqs_fwd_rules(struct mlx5e_priv *priv);
852 int mlx5e_attr_get(struct net_device *dev, struct switchdev_attr *attr);
854 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv);
855 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt);
856 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv);
857 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv);
858 int mlx5e_create_tises(struct mlx5e_priv *priv);
859 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv);
860 int mlx5e_close(struct net_device *netdev);
861 int mlx5e_open(struct net_device *netdev);
862 void mlx5e_update_stats_work(struct work_struct *work);
863 void *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
864 const struct mlx5e_profile *profile, void *ppriv);
865 void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv);
866 struct rtnl_link_stats64 *
867 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats);
869 #endif /* __MLX5_EN_H__ */