2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/ptp_clock_kernel.h>
40 #include <linux/mlx5/driver.h>
41 #include <linux/mlx5/qp.h>
42 #include <linux/mlx5/cq.h>
43 #include <linux/mlx5/port.h>
44 #include <linux/mlx5/vport.h>
45 #include <linux/mlx5/transobj.h>
46 #include <linux/rhashtable.h>
48 #include "mlx5_core.h"
51 #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
53 #define MLX5E_MAX_NUM_TC 8
55 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
56 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
57 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
59 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1
60 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
61 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd
63 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x1
64 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW 0x4
65 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW 0x6
67 #define MLX5_MPWRQ_LOG_NUM_STRIDES 11 /* >= 9, HW restriction */
68 #define MLX5_MPWRQ_LOG_STRIDE_SIZE 6 /* >= 6, HW restriction */
69 #define MLX5_MPWRQ_NUM_STRIDES BIT(MLX5_MPWRQ_LOG_NUM_STRIDES)
70 #define MLX5_MPWRQ_STRIDE_SIZE BIT(MLX5_MPWRQ_LOG_STRIDE_SIZE)
71 #define MLX5_MPWRQ_LOG_WQE_SZ (MLX5_MPWRQ_LOG_NUM_STRIDES +\
72 MLX5_MPWRQ_LOG_STRIDE_SIZE)
73 #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
74 MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
75 #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
76 #define MLX5_MPWRQ_STRIDES_PER_PAGE (MLX5_MPWRQ_NUM_STRIDES >> \
77 MLX5_MPWRQ_WQE_PAGE_ORDER)
78 #define MLX5_CHANNEL_MAX_NUM_MTTS (ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8) * \
79 BIT(MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW))
80 #define MLX5_UMR_ALIGN (2048)
81 #define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD (128)
83 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
84 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
85 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
86 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
87 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
88 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
89 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
91 #define MLX5E_LOG_INDIR_RQT_SIZE 0x7
92 #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE)
93 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1)
94 #define MLX5E_TX_CQ_POLL_BUDGET 128
95 #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */
96 #define MLX5E_SQ_BF_BUDGET 16
98 #define MLX5E_NUM_MAIN_GROUPS 9
100 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
103 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
104 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
107 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
112 static inline int mlx5_min_log_rq_size(int wq_type)
115 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
116 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
118 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE;
122 static inline int mlx5_max_log_rq_size(int wq_type)
125 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
126 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW;
128 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE;
132 struct mlx5e_tx_wqe {
133 struct mlx5_wqe_ctrl_seg ctrl;
134 struct mlx5_wqe_eth_seg eth;
137 struct mlx5e_rx_wqe {
138 struct mlx5_wqe_srq_next_seg next;
139 struct mlx5_wqe_data_seg data;
142 struct mlx5e_umr_wqe {
143 struct mlx5_wqe_ctrl_seg ctrl;
144 struct mlx5_wqe_umr_ctrl_seg uctrl;
145 struct mlx5_mkey_seg mkc;
146 struct mlx5_wqe_data_seg data;
149 #ifdef CONFIG_MLX5_CORE_EN_DCB
150 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
151 #define MLX5E_MIN_BW_ALLOC 1 /* Min percentage of BW allocation */
154 struct mlx5e_params {
160 u16 rx_cq_moderation_usec;
161 u16 rx_cq_moderation_pkts;
162 u16 tx_cq_moderation_usec;
163 u16 tx_cq_moderation_pkts;
169 u8 toeplitz_hash_key[40];
170 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
171 bool vlan_strip_disable;
172 #ifdef CONFIG_MLX5_CORE_EN_DCB
177 struct mlx5e_tstamp {
179 struct cyclecounter cycles;
180 struct timecounter clock;
181 struct hwtstamp_config hwtstamp_config;
183 unsigned long overflow_period;
184 struct delayed_work overflow_work;
185 struct mlx5_core_dev *mdev;
186 struct ptp_clock *ptp;
187 struct ptp_clock_info ptp_info;
191 MLX5E_RQ_STATE_POST_WQES_ENABLE,
192 MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS,
196 /* data path - accessed per cqe */
199 /* data path - accessed per napi poll */
200 struct napi_struct *napi;
201 struct mlx5_core_cq mcq;
202 struct mlx5e_channel *channel;
203 struct mlx5e_priv *priv;
206 struct mlx5_wq_ctrl wq_ctrl;
207 } ____cacheline_aligned_in_smp;
210 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq *rq,
211 struct mlx5_cqe64 *cqe);
212 typedef int (*mlx5e_fp_alloc_wqe)(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe,
215 struct mlx5e_dma_info {
222 struct mlx5_wq_ll wq;
224 struct sk_buff **skb;
225 struct mlx5e_mpw_info *wqe_info;
230 struct net_device *netdev;
231 struct mlx5e_tstamp *tstamp;
232 struct mlx5e_rq_stats stats;
234 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
235 mlx5e_fp_alloc_wqe alloc_wqe;
241 struct mlx5_wq_ctrl wq_ctrl;
244 struct mlx5e_channel *channel;
245 struct mlx5e_priv *priv;
246 } ____cacheline_aligned_in_smp;
248 struct mlx5e_umr_dma_info {
250 __be64 *mtt_no_align;
252 struct mlx5e_dma_info *dma_info;
255 struct mlx5e_mpw_info {
257 struct mlx5e_dma_info dma_info;
258 struct mlx5e_umr_dma_info umr;
260 u16 consumed_strides;
261 u16 skbs_frags[MLX5_MPWRQ_PAGES_PER_WQE];
263 void (*dma_pre_sync)(struct device *pdev,
264 struct mlx5e_mpw_info *wi,
265 u32 wqe_offset, u32 len);
266 void (*add_skb_frag)(struct device *pdev,
268 struct mlx5e_mpw_info *wi,
269 u32 page_idx, u32 frag_offset, u32 len);
270 void (*copy_skb_header)(struct device *pdev,
272 struct mlx5e_mpw_info *wi,
273 u32 page_idx, u32 offset,
275 void (*free_wqe)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi);
278 struct mlx5e_tx_wqe_info {
284 enum mlx5e_dma_map_type {
285 MLX5E_DMA_MAP_SINGLE,
289 struct mlx5e_sq_dma {
292 enum mlx5e_dma_map_type type;
296 MLX5E_SQ_STATE_WAKE_TXQ_ENABLE,
297 MLX5E_SQ_STATE_BF_ENABLE,
300 struct mlx5e_ico_wqe_info {
308 /* dirtied @completion */
313 u16 pc ____cacheline_aligned_in_smp;
318 struct mlx5e_sq_stats stats;
322 /* pointers to per packet info: write@xmit, read@completion */
323 struct sk_buff **skb;
324 struct mlx5e_sq_dma *dma_fifo;
325 struct mlx5e_tx_wqe_info *wqe_info;
328 struct mlx5_wq_cyc wq;
330 void __iomem *uar_map;
331 struct netdev_queue *txq;
337 struct mlx5e_tstamp *tstamp;
342 struct mlx5_wq_ctrl wq_ctrl;
344 struct mlx5e_channel *channel;
346 struct mlx5e_ico_wqe_info *ico_wqe_info;
347 } ____cacheline_aligned_in_smp;
349 static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n)
351 return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) ||
356 MLX5E_CHANNEL_NAPI_SCHED = 1,
359 struct mlx5e_channel {
362 struct mlx5e_sq sq[MLX5E_MAX_NUM_TC];
363 struct mlx5e_sq icosq; /* internal control operations */
364 struct napi_struct napi;
366 struct net_device *netdev;
372 struct mlx5e_priv *priv;
377 enum mlx5e_traffic_types {
382 MLX5E_TT_IPV4_IPSEC_AH,
383 MLX5E_TT_IPV6_IPSEC_AH,
384 MLX5E_TT_IPV4_IPSEC_ESP,
385 MLX5E_TT_IPV6_IPSEC_ESP,
390 MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY,
394 MLX5E_STATE_ASYNC_EVENTS_ENABLE,
396 MLX5E_STATE_DESTROYING,
399 struct mlx5e_vxlan_db {
400 spinlock_t lock; /* protect vxlan table */
401 struct radix_tree_root tree;
404 struct mlx5e_l2_rule {
405 u8 addr[ETH_ALEN + 2];
406 struct mlx5_flow_rule *rule;
409 struct mlx5e_flow_table {
411 struct mlx5_flow_table *t;
412 struct mlx5_flow_group **g;
415 #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE)
417 struct mlx5e_tc_table {
418 struct mlx5_flow_table *t;
420 struct rhashtable_params ht_params;
421 struct rhashtable ht;
424 struct mlx5e_vlan_table {
425 struct mlx5e_flow_table ft;
426 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
427 struct mlx5_flow_rule *active_vlans_rule[VLAN_N_VID];
428 struct mlx5_flow_rule *untagged_rule;
429 struct mlx5_flow_rule *any_vlan_rule;
430 bool filter_disabled;
433 struct mlx5e_l2_table {
434 struct mlx5e_flow_table ft;
435 struct hlist_head netdev_uc[MLX5E_L2_ADDR_HASH_SIZE];
436 struct hlist_head netdev_mc[MLX5E_L2_ADDR_HASH_SIZE];
437 struct mlx5e_l2_rule broadcast;
438 struct mlx5e_l2_rule allmulti;
439 struct mlx5e_l2_rule promisc;
440 bool broadcast_enabled;
441 bool allmulti_enabled;
442 bool promisc_enabled;
445 /* L3/L4 traffic type classifier */
446 struct mlx5e_ttc_table {
447 struct mlx5e_flow_table ft;
448 struct mlx5_flow_rule *rules[MLX5E_NUM_TT];
452 struct mlx5e_flow_table ft;
453 struct mlx5_flow_rule *default_rule;
464 struct mlx5e_arfs_tables {
465 struct arfs_table arfs_tables[ARFS_NUM_TYPES];
470 MLX5E_VLAN_FT_LEVEL = 0,
476 struct mlx5e_flow_steering {
477 struct mlx5_flow_namespace *ns;
478 struct mlx5e_tc_table tc;
479 struct mlx5e_vlan_table vlan;
480 struct mlx5e_l2_table l2;
481 struct mlx5e_ttc_table ttc;
482 struct mlx5e_arfs_tables arfs;
485 struct mlx5e_direct_tir {
496 /* priv data path fields - start */
497 struct mlx5e_sq **txq_to_sq_map;
498 int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
499 /* priv data path fields - end */
502 struct mutex state_lock; /* Protects Interface state */
503 struct mlx5_uar cq_uar;
506 struct mlx5_core_mkey mkey;
507 struct mlx5_core_mkey umr_mkey;
508 struct mlx5e_rq drop_rq;
510 struct mlx5e_channel **channel;
511 u32 tisn[MLX5E_MAX_NUM_TC];
513 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
514 struct mlx5e_direct_tir direct_tir[MLX5E_MAX_NUM_CHANNELS];
516 struct mlx5e_flow_steering fs;
517 struct mlx5e_vxlan_db vxlan;
519 struct mlx5e_params params;
520 struct work_struct update_carrier_work;
521 struct work_struct set_rx_mode_work;
522 struct delayed_work update_stats_work;
524 struct mlx5_core_dev *mdev;
525 struct net_device *netdev;
526 struct mlx5e_stats stats;
527 struct mlx5e_tstamp tstamp;
531 enum mlx5e_link_mode {
532 MLX5E_1000BASE_CX_SGMII = 0,
533 MLX5E_1000BASE_KX = 1,
534 MLX5E_10GBASE_CX4 = 2,
535 MLX5E_10GBASE_KX4 = 3,
536 MLX5E_10GBASE_KR = 4,
537 MLX5E_20GBASE_KR2 = 5,
538 MLX5E_40GBASE_CR4 = 6,
539 MLX5E_40GBASE_KR4 = 7,
540 MLX5E_56GBASE_R4 = 8,
541 MLX5E_10GBASE_CR = 12,
542 MLX5E_10GBASE_SR = 13,
543 MLX5E_10GBASE_ER = 14,
544 MLX5E_40GBASE_SR4 = 15,
545 MLX5E_40GBASE_LR4 = 16,
546 MLX5E_100GBASE_CR4 = 20,
547 MLX5E_100GBASE_SR4 = 21,
548 MLX5E_100GBASE_KR4 = 22,
549 MLX5E_100GBASE_LR4 = 23,
550 MLX5E_100BASE_TX = 24,
551 MLX5E_1000BASE_T = 25,
552 MLX5E_10GBASE_T = 26,
553 MLX5E_25GBASE_CR = 27,
554 MLX5E_25GBASE_KR = 28,
555 MLX5E_25GBASE_SR = 29,
556 MLX5E_50GBASE_CR2 = 30,
557 MLX5E_50GBASE_KR2 = 31,
558 MLX5E_LINK_MODES_NUMBER,
561 #define MLX5E_PROT_MASK(link_mode) (1 << link_mode)
563 void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw);
564 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
565 void *accel_priv, select_queue_fallback_t fallback);
566 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);
568 void mlx5e_completion_event(struct mlx5_core_cq *mcq);
569 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
570 int mlx5e_napi_poll(struct napi_struct *napi, int budget);
571 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget);
572 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
574 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
575 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
576 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
577 int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
578 int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
579 void mlx5e_post_rx_fragmented_mpwqe(struct mlx5e_rq *rq);
580 void mlx5e_complete_rx_linear_mpwqe(struct mlx5e_rq *rq,
581 struct mlx5_cqe64 *cqe,
583 struct mlx5e_mpw_info *wi,
584 struct sk_buff *skb);
585 void mlx5e_complete_rx_fragmented_mpwqe(struct mlx5e_rq *rq,
586 struct mlx5_cqe64 *cqe,
588 struct mlx5e_mpw_info *wi,
589 struct sk_buff *skb);
590 void mlx5e_free_rx_linear_mpwqe(struct mlx5e_rq *rq,
591 struct mlx5e_mpw_info *wi);
592 void mlx5e_free_rx_fragmented_mpwqe(struct mlx5e_rq *rq,
593 struct mlx5e_mpw_info *wi);
594 struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq);
596 void mlx5e_update_stats(struct mlx5e_priv *priv);
598 int mlx5e_create_flow_steering(struct mlx5e_priv *priv);
599 void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv);
600 void mlx5e_init_l2_addr(struct mlx5e_priv *priv);
601 void mlx5e_destroy_flow_table(struct mlx5e_flow_table *ft);
602 void mlx5e_set_rx_mode_work(struct work_struct *work);
604 void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp,
605 struct skb_shared_hwtstamps *hwts);
606 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
607 void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv);
608 int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr);
609 int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr);
611 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
613 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
615 void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv);
616 void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv);
618 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd);
620 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix);
621 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv);
623 int mlx5e_open_locked(struct net_device *netdev);
624 int mlx5e_close_locked(struct net_device *netdev);
625 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
626 u32 *indirection_rqt, int len,
629 static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq,
630 struct mlx5_wqe_ctrl_seg *ctrl, int bf_sz)
632 u16 ofst = MLX5_BF_OFFSET + sq->bf_offset;
634 /* ensure wqe is visible to device before updating doorbell record */
637 *sq->wq.db = cpu_to_be32(sq->pc);
639 /* ensure doorbell record is visible to device before ringing the
644 __iowrite64_copy(sq->uar_map + ofst, ctrl, bf_sz);
646 mlx5_write64((__be32 *)ctrl, sq->uar_map + ofst, NULL);
647 /* flush the write-combining mapped buffer */
650 sq->bf_offset ^= sq->bf_buf_size;
653 static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
655 struct mlx5_core_cq *mcq;
658 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc);
661 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
663 return min_t(int, mdev->priv.eq_table.num_comp_vectors,
664 MLX5E_MAX_NUM_CHANNELS);
667 static inline int mlx5e_get_mtt_octw(int npages)
669 return ALIGN(npages, 8) / 2;
672 extern const struct ethtool_ops mlx5e_ethtool_ops;
673 #ifdef CONFIG_MLX5_CORE_EN_DCB
674 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
675 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets);
678 #ifndef CONFIG_RFS_ACCEL
679 static inline int mlx5e_arfs_create_tables(struct mlx5e_priv *priv)
684 static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv) {}
686 int mlx5e_arfs_create_tables(struct mlx5e_priv *priv);
687 void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv);
690 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev);
692 #endif /* __MLX5_EN_H__ */