2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/ptp_clock_kernel.h>
40 #include <linux/mlx5/driver.h>
41 #include <linux/mlx5/qp.h>
42 #include <linux/mlx5/cq.h>
43 #include <linux/mlx5/port.h>
44 #include <linux/mlx5/vport.h>
45 #include <linux/mlx5/transobj.h>
46 #include <linux/rhashtable.h>
48 #include "mlx5_core.h"
50 #define MLX5E_MAX_NUM_TC 8
52 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
53 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
54 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
56 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1
57 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
58 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd
60 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x1
61 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW 0x4
62 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW 0x6
64 #define MLX5_MPWRQ_LOG_NUM_STRIDES 11 /* >= 9, HW restriction */
65 #define MLX5_MPWRQ_LOG_STRIDE_SIZE 6 /* >= 6, HW restriction */
66 #define MLX5_MPWRQ_NUM_STRIDES BIT(MLX5_MPWRQ_LOG_NUM_STRIDES)
67 #define MLX5_MPWRQ_STRIDE_SIZE BIT(MLX5_MPWRQ_LOG_STRIDE_SIZE)
68 #define MLX5_MPWRQ_LOG_WQE_SZ (MLX5_MPWRQ_LOG_NUM_STRIDES +\
69 MLX5_MPWRQ_LOG_STRIDE_SIZE)
70 #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
71 MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
72 #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
73 #define MLX5_MPWRQ_STRIDES_PER_PAGE (MLX5_MPWRQ_NUM_STRIDES >> \
74 MLX5_MPWRQ_WQE_PAGE_ORDER)
75 #define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD (128)
77 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
78 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
79 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
80 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
81 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
82 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
83 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
85 #define MLX5E_LOG_INDIR_RQT_SIZE 0x7
86 #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE)
87 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1)
88 #define MLX5E_TX_CQ_POLL_BUDGET 128
89 #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */
90 #define MLX5E_SQ_BF_BUDGET 16
92 #define MLX5E_NUM_MAIN_GROUPS 9
93 #define MLX5E_NET_IP_ALIGN 2
95 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
98 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
99 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
102 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
107 static inline int mlx5_min_log_rq_size(int wq_type)
110 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
111 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
113 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE;
117 static inline int mlx5_max_log_rq_size(int wq_type)
120 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
121 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW;
123 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE;
127 struct mlx5e_tx_wqe {
128 struct mlx5_wqe_ctrl_seg ctrl;
129 struct mlx5_wqe_eth_seg eth;
132 struct mlx5e_rx_wqe {
133 struct mlx5_wqe_srq_next_seg next;
134 struct mlx5_wqe_data_seg data;
137 #ifdef CONFIG_MLX5_CORE_EN_DCB
138 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
139 #define MLX5E_MIN_BW_ALLOC 1 /* Min percentage of BW allocation */
142 static const char vport_strings[][ETH_GSTRING_LEN] = {
143 /* vport statistics */
152 "rx_unicast_packets",
154 "tx_unicast_packets",
156 "rx_multicast_packets",
157 "rx_multicast_bytes",
158 "tx_multicast_packets",
159 "tx_multicast_bytes",
160 "rx_broadcast_packets",
161 "rx_broadcast_bytes",
162 "tx_broadcast_packets",
163 "tx_broadcast_bytes",
184 struct mlx5e_vport_stats {
190 u64 rx_error_packets;
192 u64 tx_error_packets;
194 u64 rx_unicast_packets;
195 u64 rx_unicast_bytes;
196 u64 tx_unicast_packets;
197 u64 tx_unicast_bytes;
198 u64 rx_multicast_packets;
199 u64 rx_multicast_bytes;
200 u64 tx_multicast_packets;
201 u64 tx_multicast_bytes;
202 u64 rx_broadcast_packets;
203 u64 rx_broadcast_bytes;
204 u64 tx_broadcast_packets;
205 u64 tx_broadcast_bytes;
210 u64 tso_inner_packets;
219 u64 tx_queue_stopped;
221 u64 tx_queue_dropped;
225 #define NUM_VPORT_COUNTERS 36
228 static const char pport_strings[][ETH_GSTRING_LEN] = {
229 /* IEEE802.3 counters */
240 "in_range_len_errors",
250 /* RFC2863 counters */
262 "out_multicast_pkts",
263 "out_broadcast_pkts",
265 /* RFC2819 counters */
286 "p8192to10239octets",
289 #define NUM_IEEE_802_3_COUNTERS 19
290 #define NUM_RFC_2863_COUNTERS 13
291 #define NUM_RFC_2819_COUNTERS 21
292 #define NUM_PPORT_COUNTERS (NUM_IEEE_802_3_COUNTERS + \
293 NUM_RFC_2863_COUNTERS + \
294 NUM_RFC_2819_COUNTERS)
296 struct mlx5e_pport_stats {
297 __be64 IEEE_802_3_counters[NUM_IEEE_802_3_COUNTERS];
298 __be64 RFC_2863_counters[NUM_RFC_2863_COUNTERS];
299 __be64 RFC_2819_counters[NUM_RFC_2819_COUNTERS];
302 static const char qcounter_stats_strings[][ETH_GSTRING_LEN] = {
306 struct mlx5e_qcounter_stats {
307 u32 rx_out_of_buffer;
308 #define NUM_Q_COUNTERS 1
311 static const char rq_stats_strings[][ETH_GSTRING_LEN] = {
322 struct mlx5e_rq_stats {
331 #define NUM_RQ_STATS 8
334 static const char sq_stats_strings[][ETH_GSTRING_LEN] = {
341 "csum_offload_inner",
349 struct mlx5e_sq_stats {
350 /* commonly accessed in data path */
355 u64 tso_inner_packets;
357 u64 csum_offload_inner;
359 /* less likely accessed in data path */
360 u64 csum_offload_none;
364 #define NUM_SQ_STATS 12
368 struct mlx5e_vport_stats vport;
369 struct mlx5e_pport_stats pport;
370 struct mlx5e_qcounter_stats qcnt;
373 struct mlx5e_params {
379 u16 rx_cq_moderation_usec;
380 u16 rx_cq_moderation_pkts;
381 u16 tx_cq_moderation_usec;
382 u16 tx_cq_moderation_pkts;
388 u8 toeplitz_hash_key[40];
389 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
390 #ifdef CONFIG_MLX5_CORE_EN_DCB
395 struct mlx5e_tstamp {
397 struct cyclecounter cycles;
398 struct timecounter clock;
399 struct hwtstamp_config hwtstamp_config;
401 unsigned long overflow_period;
402 struct delayed_work overflow_work;
403 struct mlx5_core_dev *mdev;
404 struct ptp_clock *ptp;
405 struct ptp_clock_info ptp_info;
409 MLX5E_RQ_STATE_POST_WQES_ENABLE,
413 /* data path - accessed per cqe */
416 /* data path - accessed per napi poll */
417 struct napi_struct *napi;
418 struct mlx5_core_cq mcq;
419 struct mlx5e_channel *channel;
420 struct mlx5e_priv *priv;
423 struct mlx5_wq_ctrl wq_ctrl;
424 } ____cacheline_aligned_in_smp;
427 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq *rq,
428 struct mlx5_cqe64 *cqe);
429 typedef int (*mlx5e_fp_alloc_wqe)(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe,
432 struct mlx5e_dma_info {
437 struct mlx5e_mpw_info {
438 struct mlx5e_dma_info dma_info;
439 u16 consumed_strides;
440 u16 skbs_frags[MLX5_MPWRQ_PAGES_PER_WQE];
445 struct mlx5_wq_ll wq;
447 struct sk_buff **skb;
448 struct mlx5e_mpw_info *wqe_info;
451 struct net_device *netdev;
452 struct mlx5e_tstamp *tstamp;
453 struct mlx5e_rq_stats stats;
455 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
456 mlx5e_fp_alloc_wqe alloc_wqe;
462 struct mlx5_wq_ctrl wq_ctrl;
465 struct mlx5e_channel *channel;
466 struct mlx5e_priv *priv;
467 } ____cacheline_aligned_in_smp;
469 struct mlx5e_tx_wqe_info {
475 enum mlx5e_dma_map_type {
476 MLX5E_DMA_MAP_SINGLE,
480 struct mlx5e_sq_dma {
483 enum mlx5e_dma_map_type type;
487 MLX5E_SQ_STATE_WAKE_TXQ_ENABLE,
488 MLX5E_SQ_STATE_BF_ENABLE,
494 /* dirtied @completion */
499 u16 pc ____cacheline_aligned_in_smp;
504 struct mlx5e_sq_stats stats;
508 /* pointers to per packet info: write@xmit, read@completion */
509 struct sk_buff **skb;
510 struct mlx5e_sq_dma *dma_fifo;
511 struct mlx5e_tx_wqe_info *wqe_info;
514 struct mlx5_wq_cyc wq;
516 void __iomem *uar_map;
517 struct netdev_queue *txq;
523 struct mlx5e_tstamp *tstamp;
528 struct mlx5_wq_ctrl wq_ctrl;
530 struct mlx5e_channel *channel;
532 } ____cacheline_aligned_in_smp;
534 static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n)
536 return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) ||
541 MLX5E_CHANNEL_NAPI_SCHED = 1,
544 struct mlx5e_channel {
547 struct mlx5e_sq sq[MLX5E_MAX_NUM_TC];
548 struct napi_struct napi;
550 struct net_device *netdev;
556 struct mlx5e_priv *priv;
561 enum mlx5e_traffic_types {
566 MLX5E_TT_IPV4_IPSEC_AH,
567 MLX5E_TT_IPV6_IPSEC_AH,
568 MLX5E_TT_IPV4_IPSEC_ESP,
569 MLX5E_TT_IPV6_IPSEC_ESP,
576 #define IS_HASHING_TT(tt) (tt != MLX5E_TT_ANY)
579 MLX5E_INDIRECTION_RQT,
584 struct mlx5e_eth_addr_info {
585 u8 addr[ETH_ALEN + 2];
587 struct mlx5_flow_rule *ft_rule[MLX5E_NUM_TT];
590 #define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE)
592 struct mlx5e_eth_addr_db {
593 struct hlist_head netdev_uc[MLX5E_ETH_ADDR_HASH_SIZE];
594 struct hlist_head netdev_mc[MLX5E_ETH_ADDR_HASH_SIZE];
595 struct mlx5e_eth_addr_info broadcast;
596 struct mlx5e_eth_addr_info allmulti;
597 struct mlx5e_eth_addr_info promisc;
598 bool broadcast_enabled;
599 bool allmulti_enabled;
600 bool promisc_enabled;
604 MLX5E_STATE_ASYNC_EVENTS_ENABLE,
606 MLX5E_STATE_DESTROYING,
609 struct mlx5e_vlan_db {
610 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
611 struct mlx5_flow_rule *active_vlans_rule[VLAN_N_VID];
612 struct mlx5_flow_rule *untagged_rule;
613 struct mlx5_flow_rule *any_vlan_rule;
614 bool filter_disabled;
617 struct mlx5e_vxlan_db {
618 spinlock_t lock; /* protect vxlan table */
619 struct radix_tree_root tree;
622 struct mlx5e_flow_table {
624 struct mlx5_flow_table *t;
625 struct mlx5_flow_group **g;
628 struct mlx5e_tc_flow_table {
629 struct mlx5_flow_table *t;
631 struct rhashtable_params ht_params;
632 struct rhashtable ht;
635 struct mlx5e_flow_tables {
636 struct mlx5_flow_namespace *ns;
637 struct mlx5e_tc_flow_table tc;
638 struct mlx5e_flow_table vlan;
639 struct mlx5e_flow_table main;
643 /* priv data path fields - start */
644 struct mlx5e_sq **txq_to_sq_map;
645 int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
646 /* priv data path fields - end */
649 struct mutex state_lock; /* Protects Interface state */
650 struct mlx5_uar cq_uar;
653 struct mlx5_core_mkey mkey;
654 struct mlx5e_rq drop_rq;
656 struct mlx5e_channel **channel;
657 u32 tisn[MLX5E_MAX_NUM_TC];
658 u32 rqtn[MLX5E_NUM_RQT];
659 u32 tirn[MLX5E_NUM_TT];
661 struct mlx5e_flow_tables fts;
662 struct mlx5e_eth_addr_db eth_addr;
663 struct mlx5e_vlan_db vlan;
664 struct mlx5e_vxlan_db vxlan;
666 struct mlx5e_params params;
667 struct work_struct update_carrier_work;
668 struct work_struct set_rx_mode_work;
669 struct delayed_work update_stats_work;
671 struct mlx5_core_dev *mdev;
672 struct net_device *netdev;
673 struct mlx5e_stats stats;
674 struct mlx5e_tstamp tstamp;
678 enum mlx5e_link_mode {
679 MLX5E_1000BASE_CX_SGMII = 0,
680 MLX5E_1000BASE_KX = 1,
681 MLX5E_10GBASE_CX4 = 2,
682 MLX5E_10GBASE_KX4 = 3,
683 MLX5E_10GBASE_KR = 4,
684 MLX5E_20GBASE_KR2 = 5,
685 MLX5E_40GBASE_CR4 = 6,
686 MLX5E_40GBASE_KR4 = 7,
687 MLX5E_56GBASE_R4 = 8,
688 MLX5E_10GBASE_CR = 12,
689 MLX5E_10GBASE_SR = 13,
690 MLX5E_10GBASE_ER = 14,
691 MLX5E_40GBASE_SR4 = 15,
692 MLX5E_40GBASE_LR4 = 16,
693 MLX5E_100GBASE_CR4 = 20,
694 MLX5E_100GBASE_SR4 = 21,
695 MLX5E_100GBASE_KR4 = 22,
696 MLX5E_100GBASE_LR4 = 23,
697 MLX5E_100BASE_TX = 24,
698 MLX5E_100BASE_T = 25,
699 MLX5E_10GBASE_T = 26,
700 MLX5E_25GBASE_CR = 27,
701 MLX5E_25GBASE_KR = 28,
702 MLX5E_25GBASE_SR = 29,
703 MLX5E_50GBASE_CR2 = 30,
704 MLX5E_50GBASE_KR2 = 31,
705 MLX5E_LINK_MODES_NUMBER,
708 #define MLX5E_PROT_MASK(link_mode) (1 << link_mode)
710 void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw);
711 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
712 void *accel_priv, select_queue_fallback_t fallback);
713 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);
715 void mlx5e_completion_event(struct mlx5_core_cq *mcq);
716 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
717 int mlx5e_napi_poll(struct napi_struct *napi, int budget);
718 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget);
719 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
721 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
722 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
723 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
724 int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
725 int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
726 struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq);
728 void mlx5e_update_stats(struct mlx5e_priv *priv);
730 int mlx5e_create_flow_tables(struct mlx5e_priv *priv);
731 void mlx5e_destroy_flow_tables(struct mlx5e_priv *priv);
732 void mlx5e_init_eth_addr(struct mlx5e_priv *priv);
733 void mlx5e_set_rx_mode_work(struct work_struct *work);
735 void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp,
736 struct skb_shared_hwtstamps *hwts);
737 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
738 void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv);
739 int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr);
740 int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr);
742 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
744 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
746 void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv);
747 void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv);
749 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix);
750 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv);
752 int mlx5e_open_locked(struct net_device *netdev);
753 int mlx5e_close_locked(struct net_device *netdev);
754 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
755 u32 *indirection_rqt, int len,
758 static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq,
759 struct mlx5e_tx_wqe *wqe, int bf_sz)
761 u16 ofst = MLX5_BF_OFFSET + sq->bf_offset;
763 /* ensure wqe is visible to device before updating doorbell record */
766 *sq->wq.db = cpu_to_be32(sq->pc);
768 /* ensure doorbell record is visible to device before ringing the
773 __iowrite64_copy(sq->uar_map + ofst, &wqe->ctrl, bf_sz);
775 mlx5_write64((__be32 *)&wqe->ctrl, sq->uar_map + ofst, NULL);
776 /* flush the write-combining mapped buffer */
779 sq->bf_offset ^= sq->bf_buf_size;
782 static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
784 struct mlx5_core_cq *mcq;
787 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc);
790 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
792 return min_t(int, mdev->priv.eq_table.num_comp_vectors,
793 MLX5E_MAX_NUM_CHANNELS);
796 extern const struct ethtool_ops mlx5e_ethtool_ops;
797 #ifdef CONFIG_MLX5_CORE_EN_DCB
798 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
799 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets);
802 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev);
804 #endif /* __MLX5_EN_H__ */