drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/mlx5/flow_table.h>
  34 #include "en.h"
  35
  36 struct mlx5e_rq_param {
  37         u32                        rqc[MLX5_ST_SZ_DW(rqc)];
  38         struct mlx5_wq_param       wq;
  39 };
  40
  41 struct mlx5e_sq_param {
  42         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  43         struct mlx5_wq_param       wq;
  44         u16                        max_inline;
  45 };
  46
  47 struct mlx5e_cq_param {
  48         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  49         struct mlx5_wq_param       wq;
  50         u16                        eq_ix;
  51 };
  52
  53 struct mlx5e_channel_param {
  54         struct mlx5e_rq_param      rq;
  55         struct mlx5e_sq_param      sq;
  56         struct mlx5e_cq_param      rx_cq;
  57         struct mlx5e_cq_param      tx_cq;
  58 };
  59
  60 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
  61 {
  62         struct mlx5_core_dev *mdev = priv->mdev;
  63         u8 port_state;
  64
  65         port_state = mlx5_query_vport_state(mdev,
  66                 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT);
  67
  68         if (port_state == VPORT_STATE_UP)
  69                 netif_carrier_on(priv->netdev);
  70         else
  71                 netif_carrier_off(priv->netdev);
  72 }
  73
  74 static void mlx5e_update_carrier_work(struct work_struct *work)
  75 {
  76         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
  77                                                update_carrier_work);
  78
  79         mutex_lock(&priv->state_lock);
  80         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
  81                 mlx5e_update_carrier(priv);
  82         mutex_unlock(&priv->state_lock);
  83 }
  84
  85 void mlx5e_update_stats(struct mlx5e_priv *priv)
  86 {
  87         struct mlx5_core_dev *mdev = priv->mdev;
  88         struct mlx5e_vport_stats *s = &priv->stats.vport;
  89         struct mlx5e_rq_stats *rq_stats;
  90         struct mlx5e_sq_stats *sq_stats;
  91         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
  92         u32 *out;
  93         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
  94         u64 tx_offload_none;
  95         int i, j;
  96
  97         out = mlx5_vzalloc(outlen);
  98         if (!out)
  99                 return;
 100
 101         /* Collect firts the SW counters and then HW for consistency */
 102         s->tso_packets          = 0;
 103         s->tso_bytes            = 0;
 104         s->tx_queue_stopped     = 0;
 105         s->tx_queue_wake        = 0;
 106         s->tx_queue_dropped     = 0;
 107         tx_offload_none         = 0;
 108         s->lro_packets          = 0;
 109         s->lro_bytes            = 0;
 110         s->rx_csum_none         = 0;
 111         s->rx_wqe_err           = 0;
 112         for (i = 0; i < priv->params.num_channels; i++) {
 113                 rq_stats = &priv->channel[i]->rq.stats;
 114
 115                 s->lro_packets  += rq_stats->lro_packets;
 116                 s->lro_bytes    += rq_stats->lro_bytes;
 117                 s->rx_csum_none += rq_stats->csum_none;
 118                 s->rx_wqe_err   += rq_stats->wqe_err;
 119
 120                 for (j = 0; j < priv->params.num_tc; j++) {
 121                         sq_stats = &priv->channel[i]->sq[j].stats;
 122
 123                         s->tso_packets          += sq_stats->tso_packets;
 124                         s->tso_bytes            += sq_stats->tso_bytes;
 125                         s->tx_queue_stopped     += sq_stats->stopped;
 126                         s->tx_queue_wake        += sq_stats->wake;
 127                         s->tx_queue_dropped     += sq_stats->dropped;
 128                         tx_offload_none         += sq_stats->csum_offload_none;
 129                 }
 130         }
 131
 132         /* HW counters */
 133         memset(in, 0, sizeof(in));
 134
 135         MLX5_SET(query_vport_counter_in, in, opcode,
 136                  MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 137         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 138         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 139
 140         memset(out, 0, outlen);
 141
 142         if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
 143                 goto free_out;
 144
 145 #define MLX5_GET_CTR(p, x) \
 146         MLX5_GET64(query_vport_counter_out, p, x)
 147
 148         s->rx_error_packets     =
 149                 MLX5_GET_CTR(out, received_errors.packets);
 150         s->rx_error_bytes       =
 151                 MLX5_GET_CTR(out, received_errors.octets);
 152         s->tx_error_packets     =
 153                 MLX5_GET_CTR(out, transmit_errors.packets);
 154         s->tx_error_bytes       =
 155                 MLX5_GET_CTR(out, transmit_errors.octets);
 156
 157         s->rx_unicast_packets   =
 158                 MLX5_GET_CTR(out, received_eth_unicast.packets);
 159         s->rx_unicast_bytes     =
 160                 MLX5_GET_CTR(out, received_eth_unicast.octets);
 161         s->tx_unicast_packets   =
 162                 MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
 163         s->tx_unicast_bytes     =
 164                 MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
 165
 166         s->rx_multicast_packets =
 167                 MLX5_GET_CTR(out, received_eth_multicast.packets);
 168         s->rx_multicast_bytes   =
 169                 MLX5_GET_CTR(out, received_eth_multicast.octets);
 170         s->tx_multicast_packets =
 171                 MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
 172         s->tx_multicast_bytes   =
 173                 MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
 174
 175         s->rx_broadcast_packets =
 176                 MLX5_GET_CTR(out, received_eth_broadcast.packets);
 177         s->rx_broadcast_bytes   =
 178                 MLX5_GET_CTR(out, received_eth_broadcast.octets);
 179         s->tx_broadcast_packets =
 180                 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
 181         s->tx_broadcast_bytes   =
 182                 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
 183
 184         s->rx_packets =
 185                 s->rx_unicast_packets +
 186                 s->rx_multicast_packets +
 187                 s->rx_broadcast_packets;
 188         s->rx_bytes =
 189                 s->rx_unicast_bytes +
 190                 s->rx_multicast_bytes +
 191                 s->rx_broadcast_bytes;
 192         s->tx_packets =
 193                 s->tx_unicast_packets +
 194                 s->tx_multicast_packets +
 195                 s->tx_broadcast_packets;
 196         s->tx_bytes =
 197                 s->tx_unicast_bytes +
 198                 s->tx_multicast_bytes +
 199                 s->tx_broadcast_bytes;
 200
 201         /* Update calculated offload counters */
 202         s->tx_csum_offload = s->tx_packets - tx_offload_none;
 203         s->rx_csum_good    = s->rx_packets - s->rx_csum_none;
 204
 205 free_out:
 206         kvfree(out);
 207 }
 208
 209 static void mlx5e_update_stats_work(struct work_struct *work)
 210 {
 211         struct delayed_work *dwork = to_delayed_work(work);
 212         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 213                                                update_stats_work);
 214         mutex_lock(&priv->state_lock);
 215         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 216                 mlx5e_update_stats(priv);
 217                 schedule_delayed_work(dwork,
 218                                       msecs_to_jiffies(
 219                                               MLX5E_UPDATE_STATS_INTERVAL));
 220         }
 221         mutex_unlock(&priv->state_lock);
 222 }
 223
 224 static void __mlx5e_async_event(struct mlx5e_priv *priv,
 225                                 enum mlx5_dev_event event)
 226 {
 227         switch (event) {
 228         case MLX5_DEV_EVENT_PORT_UP:
 229         case MLX5_DEV_EVENT_PORT_DOWN:
 230                 schedule_work(&priv->update_carrier_work);
 231                 break;
 232
 233         default:
 234                 break;
 235         }
 236 }
 237
 238 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 239                               enum mlx5_dev_event event, unsigned long param)
 240 {
 241         struct mlx5e_priv *priv = vpriv;
 242
 243         spin_lock(&priv->async_events_spinlock);
 244         if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
 245                 __mlx5e_async_event(priv, event);
 246         spin_unlock(&priv->async_events_spinlock);
 247 }
 248
 249 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 250 {
 251         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 252 }
 253
 254 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 255 {
 256         spin_lock_irq(&priv->async_events_spinlock);
 257         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 258         spin_unlock_irq(&priv->async_events_spinlock);
 259 }
 260
 261 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 262 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 263
 264 static int mlx5e_create_rq(struct mlx5e_channel *c,
 265                            struct mlx5e_rq_param *param,
 266                            struct mlx5e_rq *rq)
 267 {
 268         struct mlx5e_priv *priv = c->priv;
 269         struct mlx5_core_dev *mdev = priv->mdev;
 270         void *rqc = param->rqc;
 271         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 272         int wq_sz;
 273         int err;
 274         int i;
 275
 276         param->wq.db_numa_node = cpu_to_node(c->cpu);
 277
 278         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 279                                 &rq->wq_ctrl);
 280         if (err)
 281                 return err;
 282
 283         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 284
 285         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 286         rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
 287                                cpu_to_node(c->cpu));
 288         if (!rq->skb) {
 289                 err = -ENOMEM;
 290                 goto err_rq_wq_destroy;
 291         }
 292
 293         rq->wqe_sz = (priv->params.lro_en) ? priv->params.lro_wqe_sz :
 294                                              MLX5E_SW2HW_MTU(priv->netdev->mtu);
 295         rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz + MLX5E_NET_IP_ALIGN);
 296
 297         for (i = 0; i < wq_sz; i++) {
 298                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 299                 u32 byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
 300
 301                 wqe->data.lkey       = c->mkey_be;
 302                 wqe->data.byte_count =
 303                         cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
 304         }
 305
 306         rq->pdev    = c->pdev;
 307         rq->netdev  = c->netdev;
 308         rq->channel = c;
 309         rq->ix      = c->ix;
 310         rq->priv    = c->priv;
 311
 312         return 0;
 313
 314 err_rq_wq_destroy:
 315         mlx5_wq_destroy(&rq->wq_ctrl);
 316
 317         return err;
 318 }
 319
 320 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 321 {
 322         kfree(rq->skb);
 323         mlx5_wq_destroy(&rq->wq_ctrl);
 324 }
 325
 326 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 327 {
 328         struct mlx5e_priv *priv = rq->priv;
 329         struct mlx5_core_dev *mdev = priv->mdev;
 330
 331         void *in;
 332         void *rqc;
 333         void *wq;
 334         int inlen;
 335         int err;
 336
 337         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 338                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 339         in = mlx5_vzalloc(inlen);
 340         if (!in)
 341                 return -ENOMEM;
 342
 343         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 344         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 345
 346         memcpy(rqc, param->rqc, sizeof(param->rqc));
 347
 348         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 349         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 350         MLX5_SET(rqc,  rqc, flush_in_error_en,  1);
 351         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 352                                                 MLX5_ADAPTER_PAGE_SHIFT);
 353         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 354
 355         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 356                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 357
 358         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 359
 360         kvfree(in);
 361
 362         return err;
 363 }
 364
 365 static int mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
 366 {
 367         struct mlx5e_channel *c = rq->channel;
 368         struct mlx5e_priv *priv = c->priv;
 369         struct mlx5_core_dev *mdev = priv->mdev;
 370
 371         void *in;
 372         void *rqc;
 373         int inlen;
 374         int err;
 375
 376         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 377         in = mlx5_vzalloc(inlen);
 378         if (!in)
 379                 return -ENOMEM;
 380
 381         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 382
 383         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 384         MLX5_SET(rqc, rqc, state, next_state);
 385
 386         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 387
 388         kvfree(in);
 389
 390         return err;
 391 }
 392
 393 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
 394 {
 395         mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
 396 }
 397
 398 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 399 {
 400         struct mlx5e_channel *c = rq->channel;
 401         struct mlx5e_priv *priv = c->priv;
 402         struct mlx5_wq_ll *wq = &rq->wq;
 403         int i;
 404
 405         for (i = 0; i < 1000; i++) {
 406                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 407                         return 0;
 408
 409                 msleep(20);
 410         }
 411
 412         return -ETIMEDOUT;
 413 }
 414
 415 static int mlx5e_open_rq(struct mlx5e_channel *c,
 416                          struct mlx5e_rq_param *param,
 417                          struct mlx5e_rq *rq)
 418 {
 419         int err;
 420
 421         err = mlx5e_create_rq(c, param, rq);
 422         if (err)
 423                 return err;
 424
 425         err = mlx5e_enable_rq(rq, param);
 426         if (err)
 427                 goto err_destroy_rq;
 428
 429         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 430         if (err)
 431                 goto err_disable_rq;
 432
 433         set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 434         mlx5e_send_nop(&c->sq[0], true); /* trigger mlx5e_post_rx_wqes() */
 435
 436         return 0;
 437
 438 err_disable_rq:
 439         mlx5e_disable_rq(rq);
 440 err_destroy_rq:
 441         mlx5e_destroy_rq(rq);
 442
 443         return err;
 444 }
 445
 446 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 447 {
 448         clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 449         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 450
 451         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
 452         while (!mlx5_wq_ll_is_empty(&rq->wq))
 453                 msleep(20);
 454
 455         /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
 456         napi_synchronize(&rq->channel->napi);
 457
 458         mlx5e_disable_rq(rq);
 459         mlx5e_destroy_rq(rq);
 460 }
 461
 462 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
 463 {
 464         kfree(sq->dma_fifo);
 465         kfree(sq->skb);
 466 }
 467
 468 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
 469 {
 470         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 471         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 472
 473         sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
 474         sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
 475                                     numa);
 476
 477         if (!sq->skb || !sq->dma_fifo) {
 478                 mlx5e_free_sq_db(sq);
 479                 return -ENOMEM;
 480         }
 481
 482         sq->dma_fifo_mask = df_sz - 1;
 483
 484         return 0;
 485 }
 486
 487 static int mlx5e_create_sq(struct mlx5e_channel *c,
 488                            int tc,
 489                            struct mlx5e_sq_param *param,
 490                            struct mlx5e_sq *sq)
 491 {
 492         struct mlx5e_priv *priv = c->priv;
 493         struct mlx5_core_dev *mdev = priv->mdev;
 494
 495         void *sqc = param->sqc;
 496         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
 497         int txq_ix;
 498         int err;
 499
 500         err = mlx5_alloc_map_uar(mdev, &sq->uar);
 501         if (err)
 502                 return err;
 503
 504         param->wq.db_numa_node = cpu_to_node(c->cpu);
 505
 506         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
 507                                  &sq->wq_ctrl);
 508         if (err)
 509                 goto err_unmap_free_uar;
 510
 511         sq->wq.db       = &sq->wq.db[MLX5_SND_DBR];
 512         sq->uar_map     = sq->uar.map;
 513         sq->uar_bf_map  = sq->uar.bf_map;
 514         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
 515         sq->max_inline  = param->max_inline;
 516
 517         err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
 518         if (err)
 519                 goto err_sq_wq_destroy;
 520
 521         txq_ix = c->ix + tc * priv->params.num_channels;
 522         sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
 523
 524         sq->pdev      = c->pdev;
 525         sq->mkey_be   = c->mkey_be;
 526         sq->channel   = c;
 527         sq->tc        = tc;
 528         sq->edge      = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
 529         sq->bf_budget = MLX5E_SQ_BF_BUDGET;
 530         priv->txq_to_sq_map[txq_ix] = sq;
 531
 532         return 0;
 533
 534 err_sq_wq_destroy:
 535         mlx5_wq_destroy(&sq->wq_ctrl);
 536
 537 err_unmap_free_uar:
 538         mlx5_unmap_free_uar(mdev, &sq->uar);
 539
 540         return err;
 541 }
 542
 543 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
 544 {
 545         struct mlx5e_channel *c = sq->channel;
 546         struct mlx5e_priv *priv = c->priv;
 547
 548         mlx5e_free_sq_db(sq);
 549         mlx5_wq_destroy(&sq->wq_ctrl);
 550         mlx5_unmap_free_uar(priv->mdev, &sq->uar);
 551 }
 552
 553 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
 554 {
 555         struct mlx5e_channel *c = sq->channel;
 556         struct mlx5e_priv *priv = c->priv;
 557         struct mlx5_core_dev *mdev = priv->mdev;
 558
 559         void *in;
 560         void *sqc;
 561         void *wq;
 562         int inlen;
 563         int err;
 564
 565         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
 566                 sizeof(u64) * sq->wq_ctrl.buf.npages;
 567         in = mlx5_vzalloc(inlen);
 568         if (!in)
 569                 return -ENOMEM;
 570
 571         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
 572         wq = MLX5_ADDR_OF(sqc, sqc, wq);
 573
 574         memcpy(sqc, param->sqc, sizeof(param->sqc));
 575
 576         MLX5_SET(sqc,  sqc, tis_num_0,          priv->tisn[sq->tc]);
 577         MLX5_SET(sqc,  sqc, cqn,                c->sq[sq->tc].cq.mcq.cqn);
 578         MLX5_SET(sqc,  sqc, state,              MLX5_SQC_STATE_RST);
 579         MLX5_SET(sqc,  sqc, tis_lst_sz,         1);
 580         MLX5_SET(sqc,  sqc, flush_in_error_en,  1);
 581
 582         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
 583         MLX5_SET(wq,   wq, uar_page,      sq->uar.index);
 584         MLX5_SET(wq,   wq, log_wq_pg_sz,  sq->wq_ctrl.buf.page_shift -
 585                                           MLX5_ADAPTER_PAGE_SHIFT);
 586         MLX5_SET64(wq, wq, dbr_addr,      sq->wq_ctrl.db.dma);
 587
 588         mlx5_fill_page_array(&sq->wq_ctrl.buf,
 589                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 590
 591         err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
 592
 593         kvfree(in);
 594
 595         return err;
 596 }
 597
 598 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
 599 {
 600         struct mlx5e_channel *c = sq->channel;
 601         struct mlx5e_priv *priv = c->priv;
 602         struct mlx5_core_dev *mdev = priv->mdev;
 603
 604         void *in;
 605         void *sqc;
 606         int inlen;
 607         int err;
 608
 609         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
 610         in = mlx5_vzalloc(inlen);
 611         if (!in)
 612                 return -ENOMEM;
 613
 614         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
 615
 616         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
 617         MLX5_SET(sqc, sqc, state, next_state);
 618
 619         err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
 620
 621         kvfree(in);
 622
 623         return err;
 624 }
 625
 626 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
 627 {
 628         struct mlx5e_channel *c = sq->channel;
 629         struct mlx5e_priv *priv = c->priv;
 630         struct mlx5_core_dev *mdev = priv->mdev;
 631
 632         mlx5_core_destroy_sq(mdev, sq->sqn);
 633 }
 634
 635 static int mlx5e_open_sq(struct mlx5e_channel *c,
 636                          int tc,
 637                          struct mlx5e_sq_param *param,
 638                          struct mlx5e_sq *sq)
 639 {
 640         int err;
 641
 642         err = mlx5e_create_sq(c, tc, param, sq);
 643         if (err)
 644                 return err;
 645
 646         err = mlx5e_enable_sq(sq, param);
 647         if (err)
 648                 goto err_destroy_sq;
 649
 650         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
 651         if (err)
 652                 goto err_disable_sq;
 653
 654         set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 655         netdev_tx_reset_queue(sq->txq);
 656         netif_tx_start_queue(sq->txq);
 657
 658         return 0;
 659
 660 err_disable_sq:
 661         mlx5e_disable_sq(sq);
 662 err_destroy_sq:
 663         mlx5e_destroy_sq(sq);
 664
 665         return err;
 666 }
 667
 668 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
 669 {
 670         __netif_tx_lock_bh(txq);
 671         netif_tx_stop_queue(txq);
 672         __netif_tx_unlock_bh(txq);
 673 }
 674
 675 static void mlx5e_close_sq(struct mlx5e_sq *sq)
 676 {
 677         clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 678         napi_synchronize(&sq->channel->napi); /* prevent netif_tx_wake_queue */
 679         netif_tx_disable_queue(sq->txq);
 680
 681         /* ensure hw is notified of all pending wqes */
 682         if (mlx5e_sq_has_room_for(sq, 1))
 683                 mlx5e_send_nop(sq, true);
 684
 685         mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
 686         while (sq->cc != sq->pc) /* wait till sq is empty */
 687                 msleep(20);
 688
 689         /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
 690         napi_synchronize(&sq->channel->napi);
 691
 692         mlx5e_disable_sq(sq);
 693         mlx5e_destroy_sq(sq);
 694 }
 695
 696 static int mlx5e_create_cq(struct mlx5e_channel *c,
 697                            struct mlx5e_cq_param *param,
 698                            struct mlx5e_cq *cq)
 699 {
 700         struct mlx5e_priv *priv = c->priv;
 701         struct mlx5_core_dev *mdev = priv->mdev;
 702         struct mlx5_core_cq *mcq = &cq->mcq;
 703         int eqn_not_used;
 704         int irqn;
 705         int err;
 706         u32 i;
 707
 708         param->wq.buf_numa_node = cpu_to_node(c->cpu);
 709         param->wq.db_numa_node  = cpu_to_node(c->cpu);
 710         param->eq_ix   = c->ix;
 711
 712         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
 713                                &cq->wq_ctrl);
 714         if (err)
 715                 return err;
 716
 717         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
 718
 719         cq->napi        = &c->napi;
 720
 721         mcq->cqe_sz     = 64;
 722         mcq->set_ci_db  = cq->wq_ctrl.db.db;
 723         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
 724         *mcq->set_ci_db = 0;
 725         *mcq->arm_db    = 0;
 726         mcq->vector     = param->eq_ix;
 727         mcq->comp       = mlx5e_completion_event;
 728         mcq->event      = mlx5e_cq_error_event;
 729         mcq->irqn       = irqn;
 730         mcq->uar        = &priv->cq_uar;
 731
 732         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
 733                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
 734
 735                 cqe->op_own = 0xf1;
 736         }
 737
 738         cq->channel = c;
 739         cq->priv = priv;
 740
 741         return 0;
 742 }
 743
 744 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
 745 {
 746         mlx5_wq_destroy(&cq->wq_ctrl);
 747 }
 748
 749 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
 750 {
 751         struct mlx5e_priv *priv = cq->priv;
 752         struct mlx5_core_dev *mdev = priv->mdev;
 753         struct mlx5_core_cq *mcq = &cq->mcq;
 754
 755         void *in;
 756         void *cqc;
 757         int inlen;
 758         int irqn_not_used;
 759         int eqn;
 760         int err;
 761
 762         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
 763                 sizeof(u64) * cq->wq_ctrl.buf.npages;
 764         in = mlx5_vzalloc(inlen);
 765         if (!in)
 766                 return -ENOMEM;
 767
 768         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
 769
 770         memcpy(cqc, param->cqc, sizeof(param->cqc));
 771
 772         mlx5_fill_page_array(&cq->wq_ctrl.buf,
 773                              (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
 774
 775         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
 776
 777         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
 778         MLX5_SET(cqc,   cqc, uar_page,      mcq->uar->index);
 779         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
 780                                             MLX5_ADAPTER_PAGE_SHIFT);
 781         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
 782
 783         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
 784
 785         kvfree(in);
 786
 787         if (err)
 788                 return err;
 789
 790         mlx5e_cq_arm(cq);
 791
 792         return 0;
 793 }
 794
 795 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
 796 {
 797         struct mlx5e_priv *priv = cq->priv;
 798         struct mlx5_core_dev *mdev = priv->mdev;
 799
 800         mlx5_core_destroy_cq(mdev, &cq->mcq);
 801 }
 802
 803 static int mlx5e_open_cq(struct mlx5e_channel *c,
 804                          struct mlx5e_cq_param *param,
 805                          struct mlx5e_cq *cq,
 806                          u16 moderation_usecs,
 807                          u16 moderation_frames)
 808 {
 809         int err;
 810         struct mlx5e_priv *priv = c->priv;
 811         struct mlx5_core_dev *mdev = priv->mdev;
 812
 813         err = mlx5e_create_cq(c, param, cq);
 814         if (err)
 815                 return err;
 816
 817         err = mlx5e_enable_cq(cq, param);
 818         if (err)
 819                 goto err_destroy_cq;
 820
 821         err = mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
 822                                              moderation_usecs,
 823                                              moderation_frames);
 824         if (err)
 825                 goto err_destroy_cq;
 826
 827         return 0;
 828
 829 err_destroy_cq:
 830         mlx5e_destroy_cq(cq);
 831
 832         return err;
 833 }
 834
 835 static void mlx5e_close_cq(struct mlx5e_cq *cq)
 836 {
 837         mlx5e_disable_cq(cq);
 838         mlx5e_destroy_cq(cq);
 839 }
 840
 841 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
 842 {
 843         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
 844 }
 845
 846 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
 847                              struct mlx5e_channel_param *cparam)
 848 {
 849         struct mlx5e_priv *priv = c->priv;
 850         int err;
 851         int tc;
 852
 853         for (tc = 0; tc < c->num_tc; tc++) {
 854                 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
 855                                     priv->params.tx_cq_moderation_usec,
 856                                     priv->params.tx_cq_moderation_pkts);
 857                 if (err)
 858                         goto err_close_tx_cqs;
 859         }
 860
 861         return 0;
 862
 863 err_close_tx_cqs:
 864         for (tc--; tc >= 0; tc--)
 865                 mlx5e_close_cq(&c->sq[tc].cq);
 866
 867         return err;
 868 }
 869
 870 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
 871 {
 872         int tc;
 873
 874         for (tc = 0; tc < c->num_tc; tc++)
 875                 mlx5e_close_cq(&c->sq[tc].cq);
 876 }
 877
 878 static int mlx5e_open_sqs(struct mlx5e_channel *c,
 879                           struct mlx5e_channel_param *cparam)
 880 {
 881         int err;
 882         int tc;
 883
 884         for (tc = 0; tc < c->num_tc; tc++) {
 885                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
 886                 if (err)
 887                         goto err_close_sqs;
 888         }
 889
 890         return 0;
 891
 892 err_close_sqs:
 893         for (tc--; tc >= 0; tc--)
 894                 mlx5e_close_sq(&c->sq[tc]);
 895
 896         return err;
 897 }
 898
 899 static void mlx5e_close_sqs(struct mlx5e_channel *c)
 900 {
 901         int tc;
 902
 903         for (tc = 0; tc < c->num_tc; tc++)
 904                 mlx5e_close_sq(&c->sq[tc]);
 905 }
 906
 907 static void mlx5e_build_tc_to_txq_map(struct mlx5e_channel *c,
 908                                       int num_channels)
 909 {
 910         int i;
 911
 912         for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
 913                 c->tc_to_txq_map[i] = c->ix + i * num_channels;
 914 }
 915
 916 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
 917                               struct mlx5e_channel_param *cparam,
 918                               struct mlx5e_channel **cp)
 919 {
 920         struct net_device *netdev = priv->netdev;
 921         int cpu = mlx5e_get_cpu(priv, ix);
 922         struct mlx5e_channel *c;
 923         int err;
 924
 925         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
 926         if (!c)
 927                 return -ENOMEM;
 928
 929         c->priv     = priv;
 930         c->ix       = ix;
 931         c->cpu      = cpu;
 932         c->pdev     = &priv->mdev->pdev->dev;
 933         c->netdev   = priv->netdev;
 934         c->mkey_be  = cpu_to_be32(priv->mr.key);
 935         c->num_tc   = priv->params.num_tc;
 936
 937         mlx5e_build_tc_to_txq_map(c, priv->params.num_channels);
 938
 939         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
 940
 941         err = mlx5e_open_tx_cqs(c, cparam);
 942         if (err)
 943                 goto err_napi_del;
 944
 945         err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
 946                             priv->params.rx_cq_moderation_usec,
 947                             priv->params.rx_cq_moderation_pkts);
 948         if (err)
 949                 goto err_close_tx_cqs;
 950
 951         napi_enable(&c->napi);
 952
 953         err = mlx5e_open_sqs(c, cparam);
 954         if (err)
 955                 goto err_disable_napi;
 956
 957         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
 958         if (err)
 959                 goto err_close_sqs;
 960
 961         netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
 962         *cp = c;
 963
 964         return 0;
 965
 966 err_close_sqs:
 967         mlx5e_close_sqs(c);
 968
 969 err_disable_napi:
 970         napi_disable(&c->napi);
 971         mlx5e_close_cq(&c->rq.cq);
 972
 973 err_close_tx_cqs:
 974         mlx5e_close_tx_cqs(c);
 975
 976 err_napi_del:
 977         netif_napi_del(&c->napi);
 978         kfree(c);
 979
 980         return err;
 981 }
 982
 983 static void mlx5e_close_channel(struct mlx5e_channel *c)
 984 {
 985         mlx5e_close_rq(&c->rq);
 986         mlx5e_close_sqs(c);
 987         napi_disable(&c->napi);
 988         mlx5e_close_cq(&c->rq.cq);
 989         mlx5e_close_tx_cqs(c);
 990         netif_napi_del(&c->napi);
 991         kfree(c);
 992 }
 993
 994 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
 995                                  struct mlx5e_rq_param *param)
 996 {
 997         void *rqc = param->rqc;
 998         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
 999
1000         MLX5_SET(wq, wq, wq_type,          MLX5_WQ_TYPE_LINKED_LIST);
1001         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1002         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1003         MLX5_SET(wq, wq, log_wq_sz,        priv->params.log_rq_size);
1004         MLX5_SET(wq, wq, pd,               priv->pdn);
1005
1006         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1007         param->wq.linear = 1;
1008 }
1009
1010 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1011                                  struct mlx5e_sq_param *param)
1012 {
1013         void *sqc = param->sqc;
1014         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1015
1016         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1017         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1018         MLX5_SET(wq, wq, pd,            priv->pdn);
1019
1020         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1021         param->max_inline = priv->params.tx_max_inline;
1022 }
1023
1024 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1025                                         struct mlx5e_cq_param *param)
1026 {
1027         void *cqc = param->cqc;
1028
1029         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1030 }
1031
1032 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1033                                     struct mlx5e_cq_param *param)
1034 {
1035         void *cqc = param->cqc;
1036
1037         MLX5_SET(cqc, cqc, log_cq_size,  priv->params.log_rq_size);
1038
1039         mlx5e_build_common_cq_param(priv, param);
1040 }
1041
1042 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1043                                     struct mlx5e_cq_param *param)
1044 {
1045         void *cqc = param->cqc;
1046
1047         MLX5_SET(cqc, cqc, log_cq_size,  priv->params.log_sq_size);
1048
1049         mlx5e_build_common_cq_param(priv, param);
1050 }
1051
1052 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
1053                                       struct mlx5e_channel_param *cparam)
1054 {
1055         memset(cparam, 0, sizeof(*cparam));
1056
1057         mlx5e_build_rq_param(priv, &cparam->rq);
1058         mlx5e_build_sq_param(priv, &cparam->sq);
1059         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1060         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1061 }
1062
1063 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1064 {
1065         struct mlx5e_channel_param cparam;
1066         int nch = priv->params.num_channels;
1067         int err = -ENOMEM;
1068         int i;
1069         int j;
1070
1071         priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1072                                 GFP_KERNEL);
1073
1074         priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1075                                       sizeof(struct mlx5e_sq *), GFP_KERNEL);
1076
1077         if (!priv->channel || !priv->txq_to_sq_map)
1078                 goto err_free_txq_to_sq_map;
1079
1080         mlx5e_build_channel_param(priv, &cparam);
1081         for (i = 0; i < nch; i++) {
1082                 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1083                 if (err)
1084                         goto err_close_channels;
1085         }
1086
1087         for (j = 0; j < nch; j++) {
1088                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1089                 if (err)
1090                         goto err_close_channels;
1091         }
1092
1093         return 0;
1094
1095 err_close_channels:
1096         for (i--; i >= 0; i--)
1097                 mlx5e_close_channel(priv->channel[i]);
1098
1099 err_free_txq_to_sq_map:
1100         kfree(priv->txq_to_sq_map);
1101         kfree(priv->channel);
1102
1103         return err;
1104 }
1105
1106 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1107 {
1108         int i;
1109
1110         for (i = 0; i < priv->params.num_channels; i++)
1111                 mlx5e_close_channel(priv->channel[i]);
1112
1113         kfree(priv->txq_to_sq_map);
1114         kfree(priv->channel);
1115 }
1116
1117 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1118                                 struct mlx5e_rq *rq,
1119                                 struct mlx5e_rq_param *param)
1120 {
1121         struct mlx5_core_dev *mdev = priv->mdev;
1122         void *rqc = param->rqc;
1123         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1124         int err;
1125
1126         param->wq.db_numa_node = param->wq.buf_numa_node;
1127
1128         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1129                                 &rq->wq_ctrl);
1130         if (err)
1131                 return err;
1132
1133         rq->priv = priv;
1134
1135         return 0;
1136 }
1137
1138 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1139                                 struct mlx5e_cq *cq,
1140                                 struct mlx5e_cq_param *param)
1141 {
1142         struct mlx5_core_dev *mdev = priv->mdev;
1143         struct mlx5_core_cq *mcq = &cq->mcq;
1144         int eqn_not_used;
1145         int irqn;
1146         int err;
1147
1148         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1149                                &cq->wq_ctrl);
1150         if (err)
1151                 return err;
1152
1153         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1154
1155         mcq->cqe_sz     = 64;
1156         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1157         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1158         *mcq->set_ci_db = 0;
1159         *mcq->arm_db    = 0;
1160         mcq->vector     = param->eq_ix;
1161         mcq->comp       = mlx5e_completion_event;
1162         mcq->event      = mlx5e_cq_error_event;
1163         mcq->irqn       = irqn;
1164         mcq->uar        = &priv->cq_uar;
1165
1166         cq->priv = priv;
1167
1168         return 0;
1169 }
1170
1171 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1172 {
1173         struct mlx5e_cq_param cq_param;
1174         struct mlx5e_rq_param rq_param;
1175         struct mlx5e_rq *rq = &priv->drop_rq;
1176         struct mlx5e_cq *cq = &priv->drop_rq.cq;
1177         int err;
1178
1179         memset(&cq_param, 0, sizeof(cq_param));
1180         memset(&rq_param, 0, sizeof(rq_param));
1181         mlx5e_build_rx_cq_param(priv, &cq_param);
1182         mlx5e_build_rq_param(priv, &rq_param);
1183
1184         err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1185         if (err)
1186                 return err;
1187
1188         err = mlx5e_enable_cq(cq, &cq_param);
1189         if (err)
1190                 goto err_destroy_cq;
1191
1192         err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1193         if (err)
1194                 goto err_disable_cq;
1195
1196         err = mlx5e_enable_rq(rq, &rq_param);
1197         if (err)
1198                 goto err_destroy_rq;
1199
1200         return 0;
1201
1202 err_destroy_rq:
1203         mlx5e_destroy_rq(&priv->drop_rq);
1204
1205 err_disable_cq:
1206         mlx5e_disable_cq(&priv->drop_rq.cq);
1207
1208 err_destroy_cq:
1209         mlx5e_destroy_cq(&priv->drop_rq.cq);
1210
1211         return err;
1212 }
1213
1214 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
1215 {
1216         mlx5e_disable_rq(&priv->drop_rq);
1217         mlx5e_destroy_rq(&priv->drop_rq);
1218         mlx5e_disable_cq(&priv->drop_rq.cq);
1219         mlx5e_destroy_cq(&priv->drop_rq.cq);
1220 }
1221
1222 static int mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
1223 {
1224         struct mlx5_core_dev *mdev = priv->mdev;
1225         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1226         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1227
1228         memset(in, 0, sizeof(in));
1229
1230         MLX5_SET(tisc, tisc, prio,  tc);
1231         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1232
1233         return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1234 }
1235
1236 static void mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
1237 {
1238         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1239 }
1240
1241 static int mlx5e_open_tises(struct mlx5e_priv *priv)
1242 {
1243         int err;
1244         int tc;
1245
1246         for (tc = 0; tc < priv->params.num_tc; tc++) {
1247                 err = mlx5e_open_tis(priv, tc);
1248                 if (err)
1249                         goto err_close_tises;
1250         }
1251
1252         return 0;
1253
1254 err_close_tises:
1255         for (tc--; tc >= 0; tc--)
1256                 mlx5e_close_tis(priv, tc);
1257
1258         return err;
1259 }
1260
1261 static void mlx5e_close_tises(struct mlx5e_priv *priv)
1262 {
1263         int tc;
1264
1265         for (tc = 0; tc < priv->params.num_tc; tc++)
1266                 mlx5e_close_tis(priv, tc);
1267 }
1268
1269 static int mlx5e_rx_hash_fn(int hfunc)
1270 {
1271         return (hfunc == ETH_RSS_HASH_TOP) ?
1272                MLX5_RX_HASH_FN_TOEPLITZ :
1273                MLX5_RX_HASH_FN_INVERTED_XOR8;
1274 }
1275
1276 static int mlx5e_bits_invert(unsigned long a, int size)
1277 {
1278         int inv = 0;
1279         int i;
1280
1281         for (i = 0; i < size; i++)
1282                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1283
1284         return inv;
1285 }
1286
1287 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, void *rqtc,
1288                                 enum mlx5e_rqt_ix rqt_ix)
1289 {
1290         int i;
1291         int log_sz;
1292
1293         switch (rqt_ix) {
1294         case MLX5E_INDIRECTION_RQT:
1295                 log_sz = priv->params.rx_hash_log_tbl_sz;
1296                 for (i = 0; i < (1 << log_sz); i++) {
1297                         int ix = i;
1298
1299                         if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1300                                 ix = mlx5e_bits_invert(i, log_sz);
1301
1302                         ix = ix % priv->params.num_channels;
1303                         MLX5_SET(rqtc, rqtc, rq_num[i],
1304                                  test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1305                                  priv->channel[ix]->rq.rqn :
1306                                  priv->drop_rq.rqn);
1307                 }
1308
1309                 break;
1310
1311         default: /* MLX5E_SINGLE_RQ_RQT */
1312                 MLX5_SET(rqtc, rqtc, rq_num[0],
1313                          test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1314                          priv->channel[0]->rq.rqn :
1315                          priv->drop_rq.rqn);
1316
1317                 break;
1318         }
1319 }
1320
1321 static int mlx5e_open_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1322 {
1323         struct mlx5_core_dev *mdev = priv->mdev;
1324         u32 *in;
1325         void *rqtc;
1326         int inlen;
1327         int log_sz;
1328         int sz;
1329         int err;
1330
1331         log_sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 0 :
1332                   priv->params.rx_hash_log_tbl_sz;
1333         sz = 1 << log_sz;
1334
1335         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1336         in = mlx5_vzalloc(inlen);
1337         if (!in)
1338                 return -ENOMEM;
1339
1340         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1341
1342         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1343         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1344
1345         mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
1346
1347         err = mlx5_core_create_rqt(mdev, in, inlen, &priv->rqtn[rqt_ix]);
1348
1349         kvfree(in);
1350
1351         return err;
1352 }
1353
1354 static int mlx5e_redirect_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1355 {
1356         struct mlx5_core_dev *mdev = priv->mdev;
1357         u32 *in;
1358         void *rqtc;
1359         int inlen;
1360         int log_sz;
1361         int sz;
1362         int err;
1363
1364         log_sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 0 :
1365                   priv->params.rx_hash_log_tbl_sz;
1366         sz = 1 << log_sz;
1367
1368         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1369         in = mlx5_vzalloc(inlen);
1370         if (!in)
1371                 return -ENOMEM;
1372
1373         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1374
1375         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1376
1377         mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
1378
1379         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1380
1381         err = mlx5_core_modify_rqt(mdev, priv->rqtn[rqt_ix], in, inlen);
1382
1383         kvfree(in);
1384
1385         return err;
1386 }
1387
1388 static void mlx5e_close_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1389 {
1390         mlx5_core_destroy_rqt(priv->mdev, priv->rqtn[rqt_ix]);
1391 }
1392
1393 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1394 {
1395         if (!priv->params.lro_en)
1396                 return;
1397
1398 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1399
1400         MLX5_SET(tirc, tirc, lro_enable_mask,
1401                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1402                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1403         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1404                  (priv->params.lro_wqe_sz -
1405                   ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1406         MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1407                  MLX5_CAP_ETH(priv->mdev,
1408                               lro_timer_supported_periods[3]));
1409 }
1410
1411 static int mlx5e_modify_tir_lro(struct mlx5e_priv *priv, int tt)
1412 {
1413         struct mlx5_core_dev *mdev = priv->mdev;
1414
1415         void *in;
1416         void *tirc;
1417         int inlen;
1418         int err;
1419
1420         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1421         in = mlx5_vzalloc(inlen);
1422         if (!in)
1423                 return -ENOMEM;
1424
1425         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1426         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1427
1428         mlx5e_build_tir_ctx_lro(tirc, priv);
1429
1430         err = mlx5_core_modify_tir(mdev, priv->tirn[tt], in, inlen);
1431
1432         kvfree(in);
1433
1434         return err;
1435 }
1436
1437 static void mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, int tt)
1438 {
1439         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1440
1441         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1442
1443 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1444                                  MLX5_HASH_FIELD_SEL_DST_IP)
1445
1446 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1447                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1448                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
1449                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
1450
1451 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1452                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1453                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1454
1455         mlx5e_build_tir_ctx_lro(tirc, priv);
1456
1457         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
1458
1459         switch (tt) {
1460         case MLX5E_TT_ANY:
1461                 MLX5_SET(tirc, tirc, indirect_table,
1462                          priv->rqtn[MLX5E_SINGLE_RQ_RQT]);
1463                 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
1464                 break;
1465         default:
1466                 MLX5_SET(tirc, tirc, indirect_table,
1467                          priv->rqtn[MLX5E_INDIRECTION_RQT]);
1468                 MLX5_SET(tirc, tirc, rx_hash_fn,
1469                          mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1470                 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1471                         void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1472                                                      rx_hash_toeplitz_key);
1473                         size_t len = MLX5_FLD_SZ_BYTES(tirc,
1474                                                        rx_hash_toeplitz_key);
1475
1476                         MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1477                         netdev_rss_key_fill(rss_key, len);
1478                 }
1479                 break;
1480         }
1481
1482         switch (tt) {
1483         case MLX5E_TT_IPV4_TCP:
1484                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1485                          MLX5_L3_PROT_TYPE_IPV4);
1486                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1487                          MLX5_L4_PROT_TYPE_TCP);
1488                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1489                          MLX5_HASH_IP_L4PORTS);
1490                 break;
1491
1492         case MLX5E_TT_IPV6_TCP:
1493                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1494                          MLX5_L3_PROT_TYPE_IPV6);
1495                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1496                          MLX5_L4_PROT_TYPE_TCP);
1497                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1498                          MLX5_HASH_IP_L4PORTS);
1499                 break;
1500
1501         case MLX5E_TT_IPV4_UDP:
1502                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1503                          MLX5_L3_PROT_TYPE_IPV4);
1504                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1505                          MLX5_L4_PROT_TYPE_UDP);
1506                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1507                          MLX5_HASH_IP_L4PORTS);
1508                 break;
1509
1510         case MLX5E_TT_IPV6_UDP:
1511                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1512                          MLX5_L3_PROT_TYPE_IPV6);
1513                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1514                          MLX5_L4_PROT_TYPE_UDP);
1515                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1516                          MLX5_HASH_IP_L4PORTS);
1517                 break;
1518
1519         case MLX5E_TT_IPV4_IPSEC_AH:
1520                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1521                          MLX5_L3_PROT_TYPE_IPV4);
1522                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1523                          MLX5_HASH_IP_IPSEC_SPI);
1524                 break;
1525
1526         case MLX5E_TT_IPV6_IPSEC_AH:
1527                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1528                          MLX5_L3_PROT_TYPE_IPV6);
1529                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1530                          MLX5_HASH_IP_IPSEC_SPI);
1531                 break;
1532
1533         case MLX5E_TT_IPV4_IPSEC_ESP:
1534                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1535                          MLX5_L3_PROT_TYPE_IPV4);
1536                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1537                          MLX5_HASH_IP_IPSEC_SPI);
1538                 break;
1539
1540         case MLX5E_TT_IPV6_IPSEC_ESP:
1541                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1542                          MLX5_L3_PROT_TYPE_IPV6);
1543                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1544                          MLX5_HASH_IP_IPSEC_SPI);
1545                 break;
1546
1547         case MLX5E_TT_IPV4:
1548                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1549                          MLX5_L3_PROT_TYPE_IPV4);
1550                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1551                          MLX5_HASH_IP);
1552                 break;
1553
1554         case MLX5E_TT_IPV6:
1555                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1556                          MLX5_L3_PROT_TYPE_IPV6);
1557                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1558                          MLX5_HASH_IP);
1559                 break;
1560         }
1561 }
1562
1563 static int mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
1564 {
1565         struct mlx5_core_dev *mdev = priv->mdev;
1566         u32 *in;
1567         void *tirc;
1568         int inlen;
1569         int err;
1570
1571         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1572         in = mlx5_vzalloc(inlen);
1573         if (!in)
1574                 return -ENOMEM;
1575
1576         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1577
1578         mlx5e_build_tir_ctx(priv, tirc, tt);
1579
1580         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
1581
1582         kvfree(in);
1583
1584         return err;
1585 }
1586
1587 static void mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
1588 {
1589         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
1590 }
1591
1592 static int mlx5e_open_tirs(struct mlx5e_priv *priv)
1593 {
1594         int err;
1595         int i;
1596
1597         for (i = 0; i < MLX5E_NUM_TT; i++) {
1598                 err = mlx5e_open_tir(priv, i);
1599                 if (err)
1600                         goto err_close_tirs;
1601         }
1602
1603         return 0;
1604
1605 err_close_tirs:
1606         for (i--; i >= 0; i--)
1607                 mlx5e_close_tir(priv, i);
1608
1609         return err;
1610 }
1611
1612 static void mlx5e_close_tirs(struct mlx5e_priv *priv)
1613 {
1614         int i;
1615
1616         for (i = 0; i < MLX5E_NUM_TT; i++)
1617                 mlx5e_close_tir(priv, i);
1618 }
1619
1620 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1621 {
1622         struct mlx5e_priv *priv = netdev_priv(netdev);
1623         struct mlx5_core_dev *mdev = priv->mdev;
1624         int hw_mtu;
1625         int err;
1626
1627         err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(netdev->mtu), 1);
1628         if (err)
1629                 return err;
1630
1631         mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1632
1633         if (MLX5E_HW2SW_MTU(hw_mtu) != netdev->mtu)
1634                 netdev_warn(netdev, "%s: Port MTU %d is different than netdev mtu %d\n",
1635                             __func__, MLX5E_HW2SW_MTU(hw_mtu), netdev->mtu);
1636
1637         netdev->mtu = MLX5E_HW2SW_MTU(hw_mtu);
1638         return 0;
1639 }
1640
1641 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1642 {
1643         mlx5e_redirect_rqt(priv, MLX5E_INDIRECTION_RQT);
1644         mlx5e_redirect_rqt(priv, MLX5E_SINGLE_RQ_RQT);
1645 }
1646
1647 int mlx5e_open_locked(struct net_device *netdev)
1648 {
1649         struct mlx5e_priv *priv = netdev_priv(netdev);
1650         int num_txqs;
1651         int err;
1652
1653         set_bit(MLX5E_STATE_OPENED, &priv->state);
1654
1655         num_txqs = priv->params.num_channels * priv->params.num_tc;
1656         netif_set_real_num_tx_queues(netdev, num_txqs);
1657         netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1658
1659         err = mlx5e_set_dev_port_mtu(netdev);
1660         if (err)
1661                 return err;
1662
1663         err = mlx5e_open_channels(priv);
1664         if (err) {
1665                 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1666                            __func__, err);
1667                 return err;
1668         }
1669
1670         err = mlx5e_add_all_vlan_rules(priv);
1671         if (err) {
1672                 netdev_err(netdev, "%s: mlx5e_add_all_vlan_rules failed, %d\n",
1673                            __func__, err);
1674                 goto err_close_channels;
1675         }
1676
1677         mlx5e_init_eth_addr(priv);
1678
1679         mlx5e_update_carrier(priv);
1680         mlx5e_redirect_rqts(priv);
1681         mlx5e_set_rx_mode_core(priv);
1682
1683         schedule_delayed_work(&priv->update_stats_work, 0);
1684         return 0;
1685
1686 err_close_channels:
1687         mlx5e_close_channels(priv);
1688
1689         return err;
1690 }
1691
1692 static int mlx5e_open(struct net_device *netdev)
1693 {
1694         struct mlx5e_priv *priv = netdev_priv(netdev);
1695         int err;
1696
1697         mutex_lock(&priv->state_lock);
1698         err = mlx5e_open_locked(netdev);
1699         mutex_unlock(&priv->state_lock);
1700
1701         return err;
1702 }
1703
1704 int mlx5e_close_locked(struct net_device *netdev)
1705 {
1706         struct mlx5e_priv *priv = netdev_priv(netdev);
1707
1708         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1709
1710         mlx5e_set_rx_mode_core(priv);
1711         mlx5e_del_all_vlan_rules(priv);
1712         mlx5e_redirect_rqts(priv);
1713         netif_carrier_off(priv->netdev);
1714         mlx5e_close_channels(priv);
1715
1716         return 0;
1717 }
1718
1719 static int mlx5e_close(struct net_device *netdev)
1720 {
1721         struct mlx5e_priv *priv = netdev_priv(netdev);
1722         int err;
1723
1724         mutex_lock(&priv->state_lock);
1725         err = mlx5e_close_locked(netdev);
1726         mutex_unlock(&priv->state_lock);
1727
1728         return err;
1729 }
1730
1731 static struct rtnl_link_stats64 *
1732 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
1733 {
1734         struct mlx5e_priv *priv = netdev_priv(dev);
1735         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
1736
1737         stats->rx_packets = vstats->rx_packets;
1738         stats->rx_bytes   = vstats->rx_bytes;
1739         stats->tx_packets = vstats->tx_packets;
1740         stats->tx_bytes   = vstats->tx_bytes;
1741         stats->multicast  = vstats->rx_multicast_packets +
1742                             vstats->tx_multicast_packets;
1743         stats->tx_errors  = vstats->tx_error_packets;
1744         stats->rx_errors  = vstats->rx_error_packets;
1745         stats->tx_dropped = vstats->tx_queue_dropped;
1746         stats->rx_crc_errors = 0;
1747         stats->rx_length_errors = 0;
1748
1749         return stats;
1750 }
1751
1752 static void mlx5e_set_rx_mode(struct net_device *dev)
1753 {
1754         struct mlx5e_priv *priv = netdev_priv(dev);
1755
1756         schedule_work(&priv->set_rx_mode_work);
1757 }
1758
1759 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
1760 {
1761         struct mlx5e_priv *priv = netdev_priv(netdev);
1762         struct sockaddr *saddr = addr;
1763
1764         if (!is_valid_ether_addr(saddr->sa_data))
1765                 return -EADDRNOTAVAIL;
1766
1767         netif_addr_lock_bh(netdev);
1768         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
1769         netif_addr_unlock_bh(netdev);
1770
1771         schedule_work(&priv->set_rx_mode_work);
1772
1773         return 0;
1774 }
1775
1776 static int mlx5e_set_features(struct net_device *netdev,
1777                               netdev_features_t features)
1778 {
1779         struct mlx5e_priv *priv = netdev_priv(netdev);
1780         int err = 0;
1781         netdev_features_t changes = features ^ netdev->features;
1782
1783         mutex_lock(&priv->state_lock);
1784
1785         if (changes & NETIF_F_LRO) {
1786                 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1787
1788                 if (was_opened)
1789                         mlx5e_close_locked(priv->netdev);
1790
1791                 priv->params.lro_en = !!(features & NETIF_F_LRO);
1792                 mlx5e_modify_tir_lro(priv, MLX5E_TT_IPV4_TCP);
1793                 mlx5e_modify_tir_lro(priv, MLX5E_TT_IPV6_TCP);
1794
1795                 if (was_opened)
1796                         err = mlx5e_open_locked(priv->netdev);
1797         }
1798
1799         if (changes & NETIF_F_HW_VLAN_CTAG_FILTER) {
1800                 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
1801                         mlx5e_enable_vlan_filter(priv);
1802                 else
1803                         mlx5e_disable_vlan_filter(priv);
1804         }
1805
1806         mutex_unlock(&priv->state_lock);
1807
1808         return 0;
1809 }
1810
1811 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
1812 {
1813         struct mlx5e_priv *priv = netdev_priv(netdev);
1814         struct mlx5_core_dev *mdev = priv->mdev;
1815         bool was_opened;
1816         int max_mtu;
1817         int err = 0;
1818
1819         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
1820
1821         if (new_mtu > max_mtu) {
1822                 netdev_err(netdev,
1823                            "%s: Bad MTU (%d) > (%d) Max\n",
1824                            __func__, new_mtu, max_mtu);
1825                 return -EINVAL;
1826         }
1827
1828         mutex_lock(&priv->state_lock);
1829
1830         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1831         if (was_opened)
1832                 mlx5e_close_locked(netdev);
1833
1834         netdev->mtu = new_mtu;
1835
1836         if (was_opened)
1837                 err = mlx5e_open_locked(netdev);
1838
1839         mutex_unlock(&priv->state_lock);
1840
1841         return err;
1842 }
1843
1844 static struct net_device_ops mlx5e_netdev_ops = {
1845         .ndo_open                = mlx5e_open,
1846         .ndo_stop                = mlx5e_close,
1847         .ndo_start_xmit          = mlx5e_xmit,
1848         .ndo_get_stats64         = mlx5e_get_stats,
1849         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
1850         .ndo_set_mac_address     = mlx5e_set_mac,
1851         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
1852         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
1853         .ndo_set_features        = mlx5e_set_features,
1854         .ndo_change_mtu          = mlx5e_change_mtu,
1855 };
1856
1857 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
1858 {
1859         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
1860                 return -ENOTSUPP;
1861         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
1862             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
1863             !MLX5_CAP_ETH(mdev, csum_cap) ||
1864             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
1865             !MLX5_CAP_ETH(mdev, vlan_cap) ||
1866             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
1867             MLX5_CAP_FLOWTABLE(mdev,
1868                                flow_table_properties_nic_receive.max_ft_level)
1869                                < 3) {
1870                 mlx5_core_warn(mdev,
1871                                "Not creating net device, some required device capabilities are missing\n");
1872                 return -ENOTSUPP;
1873         }
1874         return 0;
1875 }
1876
1877 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
1878 {
1879         int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
1880
1881         return bf_buf_size -
1882                sizeof(struct mlx5e_tx_wqe) +
1883                2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
1884 }
1885
1886 static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
1887                                     struct net_device *netdev,
1888                                     int num_comp_vectors)
1889 {
1890         struct mlx5e_priv *priv = netdev_priv(netdev);
1891
1892         priv->params.log_sq_size           =
1893                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
1894         priv->params.log_rq_size           =
1895                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
1896         priv->params.rx_cq_moderation_usec =
1897                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
1898         priv->params.rx_cq_moderation_pkts =
1899                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
1900         priv->params.tx_cq_moderation_usec =
1901                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
1902         priv->params.tx_cq_moderation_pkts =
1903                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
1904         priv->params.tx_max_inline         = mlx5e_get_max_inline_cap(mdev);
1905         priv->params.min_rx_wqes           =
1906                 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
1907         priv->params.rx_hash_log_tbl_sz    =
1908                 (order_base_2(num_comp_vectors) >
1909                  MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
1910                 order_base_2(num_comp_vectors)           :
1911                 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
1912         priv->params.num_tc                = 1;
1913         priv->params.default_vlan_prio     = 0;
1914         priv->params.rss_hfunc             = ETH_RSS_HASH_XOR;
1915
1916         priv->params.lro_en = false && !!MLX5_CAP_ETH(priv->mdev, lro_cap);
1917         priv->params.lro_wqe_sz            =
1918                 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
1919
1920         priv->mdev                         = mdev;
1921         priv->netdev                       = netdev;
1922         priv->params.num_channels          = num_comp_vectors;
1923         priv->default_vlan_prio            = priv->params.default_vlan_prio;
1924
1925         spin_lock_init(&priv->async_events_spinlock);
1926         mutex_init(&priv->state_lock);
1927
1928         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
1929         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
1930         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
1931 }
1932
1933 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
1934 {
1935         struct mlx5e_priv *priv = netdev_priv(netdev);
1936
1937         mlx5_query_nic_vport_mac_address(priv->mdev, netdev->dev_addr);
1938 }
1939
1940 static void mlx5e_build_netdev(struct net_device *netdev)
1941 {
1942         struct mlx5e_priv *priv = netdev_priv(netdev);
1943         struct mlx5_core_dev *mdev = priv->mdev;
1944
1945         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
1946
1947         if (priv->params.num_tc > 1)
1948                 mlx5e_netdev_ops.ndo_select_queue = mlx5e_select_queue;
1949
1950         netdev->netdev_ops        = &mlx5e_netdev_ops;
1951         netdev->watchdog_timeo    = 15 * HZ;
1952
1953         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
1954
1955         netdev->vlan_features    |= NETIF_F_SG;
1956         netdev->vlan_features    |= NETIF_F_IP_CSUM;
1957         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
1958         netdev->vlan_features    |= NETIF_F_GRO;
1959         netdev->vlan_features    |= NETIF_F_TSO;
1960         netdev->vlan_features    |= NETIF_F_TSO6;
1961         netdev->vlan_features    |= NETIF_F_RXCSUM;
1962         netdev->vlan_features    |= NETIF_F_RXHASH;
1963
1964         if (!!MLX5_CAP_ETH(mdev, lro_cap))
1965                 netdev->vlan_features    |= NETIF_F_LRO;
1966
1967         netdev->hw_features       = netdev->vlan_features;
1968         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
1969         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
1970
1971         netdev->features          = netdev->hw_features;
1972         if (!priv->params.lro_en)
1973                 netdev->features  &= ~NETIF_F_LRO;
1974
1975         netdev->features         |= NETIF_F_HIGHDMA;
1976
1977         netdev->priv_flags       |= IFF_UNICAST_FLT;
1978
1979         mlx5e_set_netdev_dev_addr(netdev);
1980 }
1981
1982 static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
1983                              struct mlx5_core_mr *mr)
1984 {
1985         struct mlx5_core_dev *mdev = priv->mdev;
1986         struct mlx5_create_mkey_mbox_in *in;
1987         int err;
1988
1989         in = mlx5_vzalloc(sizeof(*in));
1990         if (!in)
1991                 return -ENOMEM;
1992
1993         in->seg.flags = MLX5_PERM_LOCAL_WRITE |
1994                         MLX5_PERM_LOCAL_READ  |
1995                         MLX5_ACCESS_MODE_PA;
1996         in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
1997         in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
1998
1999         err = mlx5_core_create_mkey(mdev, mr, in, sizeof(*in), NULL, NULL,
2000                                     NULL);
2001
2002         kvfree(in);
2003
2004         return err;
2005 }
2006
2007 static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
2008 {
2009         struct net_device *netdev;
2010         struct mlx5e_priv *priv;
2011         int ncv = mdev->priv.eq_table.num_comp_vectors;
2012         int err;
2013
2014         if (mlx5e_check_required_hca_cap(mdev))
2015                 return NULL;
2016
2017         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), ncv, ncv);
2018         if (!netdev) {
2019                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
2020                 return NULL;
2021         }
2022
2023         mlx5e_build_netdev_priv(mdev, netdev, ncv);
2024         mlx5e_build_netdev(netdev);
2025
2026         netif_carrier_off(netdev);
2027
2028         priv = netdev_priv(netdev);
2029
2030         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
2031         if (err) {
2032                 mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err);
2033                 goto err_free_netdev;
2034         }
2035
2036         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
2037         if (err) {
2038                 mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
2039                 goto err_unmap_free_uar;
2040         }
2041
2042         err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
2043         if (err) {
2044                 mlx5_core_err(mdev, "alloc td failed, %d\n", err);
2045                 goto err_dealloc_pd;
2046         }
2047
2048         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
2049         if (err) {
2050                 mlx5_core_err(mdev, "create mkey failed, %d\n", err);
2051                 goto err_dealloc_transport_domain;
2052         }
2053
2054         err = mlx5e_open_tises(priv);
2055         if (err) {
2056                 mlx5_core_warn(mdev, "open tises failed, %d\n", err);
2057                 goto err_destroy_mkey;
2058         }
2059
2060         err = mlx5e_open_drop_rq(priv);
2061         if (err) {
2062                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
2063                 goto err_close_tises;
2064         }
2065
2066         err = mlx5e_open_rqt(priv, MLX5E_INDIRECTION_RQT);
2067         if (err) {
2068                 mlx5_core_warn(mdev, "open rqt(INDIR) failed, %d\n", err);
2069                 goto err_close_drop_rq;
2070         }
2071
2072         err = mlx5e_open_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2073         if (err) {
2074                 mlx5_core_warn(mdev, "open rqt(SINGLE) failed, %d\n", err);
2075                 goto err_close_rqt_indir;
2076         }
2077
2078         err = mlx5e_open_tirs(priv);
2079         if (err) {
2080                 mlx5_core_warn(mdev, "open tirs failed, %d\n", err);
2081                 goto err_close_rqt_single;
2082         }
2083
2084         err = mlx5e_open_flow_table(priv);
2085         if (err) {
2086                 mlx5_core_warn(mdev, "open flow table failed, %d\n", err);
2087                 goto err_close_tirs;
2088         }
2089
2090         mlx5e_init_eth_addr(priv);
2091
2092         err = register_netdev(netdev);
2093         if (err) {
2094                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
2095                 goto err_close_flow_table;
2096         }
2097
2098         mlx5e_enable_async_events(priv);
2099
2100         return priv;
2101
2102 err_close_flow_table:
2103         mlx5e_close_flow_table(priv);
2104
2105 err_close_tirs:
2106         mlx5e_close_tirs(priv);
2107
2108 err_close_rqt_single:
2109         mlx5e_close_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2110
2111 err_close_rqt_indir:
2112         mlx5e_close_rqt(priv, MLX5E_INDIRECTION_RQT);
2113
2114 err_close_drop_rq:
2115         mlx5e_close_drop_rq(priv);
2116
2117 err_close_tises:
2118         mlx5e_close_tises(priv);
2119
2120 err_destroy_mkey:
2121         mlx5_core_destroy_mkey(mdev, &priv->mr);
2122
2123 err_dealloc_transport_domain:
2124         mlx5_dealloc_transport_domain(mdev, priv->tdn);
2125
2126 err_dealloc_pd:
2127         mlx5_core_dealloc_pd(mdev, priv->pdn);
2128
2129 err_unmap_free_uar:
2130         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
2131
2132 err_free_netdev:
2133         free_netdev(netdev);
2134
2135         return NULL;
2136 }
2137
2138 static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
2139 {
2140         struct mlx5e_priv *priv = vpriv;
2141         struct net_device *netdev = priv->netdev;
2142
2143         unregister_netdev(netdev);
2144         mlx5e_close_flow_table(priv);
2145         mlx5e_close_tirs(priv);
2146         mlx5e_close_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2147         mlx5e_close_rqt(priv, MLX5E_INDIRECTION_RQT);
2148         mlx5e_close_drop_rq(priv);
2149         mlx5e_close_tises(priv);
2150         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
2151         mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
2152         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
2153         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
2154         mlx5e_disable_async_events(priv);
2155         flush_scheduled_work();
2156         free_netdev(netdev);
2157 }
2158
2159 static void *mlx5e_get_netdev(void *vpriv)
2160 {
2161         struct mlx5e_priv *priv = vpriv;
2162
2163         return priv->netdev;
2164 }
2165
2166 static struct mlx5_interface mlx5e_interface = {
2167         .add       = mlx5e_create_netdev,
2168         .remove    = mlx5e_destroy_netdev,
2169         .event     = mlx5e_async_event,
2170         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
2171         .get_dev   = mlx5e_get_netdev,
2172 };
2173
2174 void mlx5e_init(void)
2175 {
2176         mlx5_register_interface(&mlx5e_interface);
2177 }
2178
2179 void mlx5e_cleanup(void)
2180 {
2181         mlx5_unregister_interface(&mlx5e_interface);
2182 }