2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
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8 * OpenIB.org BSD license below:
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11 * without modification, are permitted provided that the following
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15 * copyright notice, this list of conditions and the following
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21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
42 struct mlx5e_rq_param {
43 u32 rqc[MLX5_ST_SZ_DW(rqc)];
44 struct mlx5_wq_param wq;
47 struct mlx5e_sq_param {
48 u32 sqc[MLX5_ST_SZ_DW(sqc)];
49 struct mlx5_wq_param wq;
54 struct mlx5e_cq_param {
55 u32 cqc[MLX5_ST_SZ_DW(cqc)];
56 struct mlx5_wq_param wq;
60 struct mlx5e_channel_param {
61 struct mlx5e_rq_param rq;
62 struct mlx5e_sq_param sq;
63 struct mlx5e_sq_param icosq;
64 struct mlx5e_cq_param rx_cq;
65 struct mlx5e_cq_param tx_cq;
66 struct mlx5e_cq_param icosq_cq;
69 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
71 struct mlx5_core_dev *mdev = priv->mdev;
74 port_state = mlx5_query_vport_state(mdev,
75 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
77 if (port_state == VPORT_STATE_UP)
78 netif_carrier_on(priv->netdev);
80 netif_carrier_off(priv->netdev);
83 static void mlx5e_update_carrier_work(struct work_struct *work)
85 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
88 mutex_lock(&priv->state_lock);
89 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
90 mlx5e_update_carrier(priv);
91 mutex_unlock(&priv->state_lock);
94 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
96 struct mlx5e_sw_stats *s = &priv->stats.sw;
97 struct mlx5e_rq_stats *rq_stats;
98 struct mlx5e_sq_stats *sq_stats;
99 u64 tx_offload_none = 0;
102 memset(s, 0, sizeof(*s));
103 for (i = 0; i < priv->params.num_channels; i++) {
104 rq_stats = &priv->channel[i]->rq.stats;
106 s->rx_packets += rq_stats->packets;
107 s->rx_bytes += rq_stats->bytes;
108 s->lro_packets += rq_stats->lro_packets;
109 s->lro_bytes += rq_stats->lro_bytes;
110 s->rx_csum_none += rq_stats->csum_none;
111 s->rx_csum_sw += rq_stats->csum_sw;
112 s->rx_csum_inner += rq_stats->csum_inner;
113 s->rx_wqe_err += rq_stats->wqe_err;
114 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
115 s->rx_mpwqe_frag += rq_stats->mpwqe_frag;
116 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
118 for (j = 0; j < priv->params.num_tc; j++) {
119 sq_stats = &priv->channel[i]->sq[j].stats;
121 s->tx_packets += sq_stats->packets;
122 s->tx_bytes += sq_stats->bytes;
123 s->tso_packets += sq_stats->tso_packets;
124 s->tso_bytes += sq_stats->tso_bytes;
125 s->tso_inner_packets += sq_stats->tso_inner_packets;
126 s->tso_inner_bytes += sq_stats->tso_inner_bytes;
127 s->tx_queue_stopped += sq_stats->stopped;
128 s->tx_queue_wake += sq_stats->wake;
129 s->tx_queue_dropped += sq_stats->dropped;
130 s->tx_csum_inner += sq_stats->csum_offload_inner;
131 tx_offload_none += sq_stats->csum_offload_none;
135 /* Update calculated offload counters */
136 s->tx_csum_offload = s->tx_packets - tx_offload_none - s->tx_csum_inner;
137 s->rx_csum_good = s->rx_packets - s->rx_csum_none -
140 s->link_down_events = MLX5_GET(ppcnt_reg,
141 priv->stats.pport.phy_counters,
142 counter_set.phys_layer_cntrs.link_down_events);
145 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
147 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
148 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
149 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
150 struct mlx5_core_dev *mdev = priv->mdev;
152 memset(in, 0, sizeof(in));
154 MLX5_SET(query_vport_counter_in, in, opcode,
155 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
156 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
157 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
159 memset(out, 0, outlen);
161 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
164 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
166 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
167 struct mlx5_core_dev *mdev = priv->mdev;
168 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
173 in = mlx5_vzalloc(sz);
177 MLX5_SET(ppcnt_reg, in, local_port, 1);
179 out = pstats->IEEE_802_3_counters;
180 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
181 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
183 out = pstats->RFC_2863_counters;
184 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
185 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
187 out = pstats->RFC_2819_counters;
188 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
189 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
191 out = pstats->phy_counters;
192 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
193 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
195 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
196 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
197 out = pstats->per_prio_counters[prio];
198 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
199 mlx5_core_access_reg(mdev, in, sz, out, sz,
200 MLX5_REG_PPCNT, 0, 0);
207 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
209 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
211 if (!priv->q_counter)
214 mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
215 &qcnt->rx_out_of_buffer);
218 void mlx5e_update_stats(struct mlx5e_priv *priv)
220 mlx5e_update_q_counter(priv);
221 mlx5e_update_vport_counters(priv);
222 mlx5e_update_pport_counters(priv);
223 mlx5e_update_sw_counters(priv);
226 static void mlx5e_update_stats_work(struct work_struct *work)
228 struct delayed_work *dwork = to_delayed_work(work);
229 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
231 mutex_lock(&priv->state_lock);
232 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
233 mlx5e_update_stats(priv);
234 schedule_delayed_work(dwork,
236 MLX5E_UPDATE_STATS_INTERVAL));
238 mutex_unlock(&priv->state_lock);
241 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
242 enum mlx5_dev_event event, unsigned long param)
244 struct mlx5e_priv *priv = vpriv;
246 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
250 case MLX5_DEV_EVENT_PORT_UP:
251 case MLX5_DEV_EVENT_PORT_DOWN:
252 schedule_work(&priv->update_carrier_work);
260 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
262 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
265 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
267 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
268 synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
271 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
272 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
274 static int mlx5e_create_rq(struct mlx5e_channel *c,
275 struct mlx5e_rq_param *param,
278 struct mlx5e_priv *priv = c->priv;
279 struct mlx5_core_dev *mdev = priv->mdev;
280 void *rqc = param->rqc;
281 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
287 param->wq.db_numa_node = cpu_to_node(c->cpu);
289 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq,
294 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
296 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
298 switch (priv->params.rq_wq_type) {
299 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
300 rq->wqe_info = kzalloc_node(wq_sz * sizeof(*rq->wqe_info),
301 GFP_KERNEL, cpu_to_node(c->cpu));
304 goto err_rq_wq_destroy;
306 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
307 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
309 rq->wqe_sz = MLX5_MPWRQ_NUM_STRIDES * MLX5_MPWRQ_STRIDE_SIZE;
310 byte_count = rq->wqe_sz;
312 default: /* MLX5_WQ_TYPE_LINKED_LIST */
313 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
314 cpu_to_node(c->cpu));
317 goto err_rq_wq_destroy;
319 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
320 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
322 rq->wqe_sz = (priv->params.lro_en) ?
323 priv->params.lro_wqe_sz :
324 MLX5E_SW2HW_MTU(priv->netdev->mtu);
325 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz);
326 byte_count = rq->wqe_sz;
327 byte_count |= MLX5_HW_START_PADDING;
330 for (i = 0; i < wq_sz; i++) {
331 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
333 wqe->data.byte_count = cpu_to_be32(byte_count);
336 rq->wq_type = priv->params.rq_wq_type;
338 rq->netdev = c->netdev;
339 rq->tstamp = &priv->tstamp;
343 rq->mkey_be = c->mkey_be;
344 rq->umr_mkey_be = cpu_to_be32(c->priv->umr_mkey.key);
349 mlx5_wq_destroy(&rq->wq_ctrl);
354 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
356 switch (rq->wq_type) {
357 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
360 default: /* MLX5_WQ_TYPE_LINKED_LIST */
364 mlx5_wq_destroy(&rq->wq_ctrl);
367 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
369 struct mlx5e_priv *priv = rq->priv;
370 struct mlx5_core_dev *mdev = priv->mdev;
378 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
379 sizeof(u64) * rq->wq_ctrl.buf.npages;
380 in = mlx5_vzalloc(inlen);
384 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
385 wq = MLX5_ADDR_OF(rqc, rqc, wq);
387 memcpy(rqc, param->rqc, sizeof(param->rqc));
389 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
390 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
391 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
392 MLX5_SET(rqc, rqc, vsd, priv->params.vlan_strip_disable);
393 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
394 MLX5_ADAPTER_PAGE_SHIFT);
395 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
397 mlx5_fill_page_array(&rq->wq_ctrl.buf,
398 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
400 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
407 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
410 struct mlx5e_channel *c = rq->channel;
411 struct mlx5e_priv *priv = c->priv;
412 struct mlx5_core_dev *mdev = priv->mdev;
419 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
420 in = mlx5_vzalloc(inlen);
424 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
426 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
427 MLX5_SET(rqc, rqc, state, next_state);
429 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
436 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
438 struct mlx5e_channel *c = rq->channel;
439 struct mlx5e_priv *priv = c->priv;
440 struct mlx5_core_dev *mdev = priv->mdev;
447 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
448 in = mlx5_vzalloc(inlen);
452 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
454 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
455 MLX5_SET64(modify_rq_in, in, modify_bitmask, MLX5_RQ_BITMASK_VSD);
456 MLX5_SET(rqc, rqc, vsd, vsd);
457 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
459 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
466 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
468 mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
471 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
473 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
474 struct mlx5e_channel *c = rq->channel;
475 struct mlx5e_priv *priv = c->priv;
476 struct mlx5_wq_ll *wq = &rq->wq;
478 while (time_before(jiffies, exp_time)) {
479 if (wq->cur_sz >= priv->params.min_rx_wqes)
488 static int mlx5e_open_rq(struct mlx5e_channel *c,
489 struct mlx5e_rq_param *param,
492 struct mlx5e_sq *sq = &c->icosq;
493 u16 pi = sq->pc & sq->wq.sz_m1;
496 err = mlx5e_create_rq(c, param, rq);
500 err = mlx5e_enable_rq(rq, param);
504 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
508 set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
510 sq->ico_wqe_info[pi].opcode = MLX5_OPCODE_NOP;
511 sq->ico_wqe_info[pi].num_wqebbs = 1;
512 mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
517 mlx5e_disable_rq(rq);
519 mlx5e_destroy_rq(rq);
524 static void mlx5e_close_rq(struct mlx5e_rq *rq)
526 clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
527 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
529 mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
530 while (!mlx5_wq_ll_is_empty(&rq->wq))
533 /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
534 napi_synchronize(&rq->channel->napi);
536 mlx5e_disable_rq(rq);
537 mlx5e_destroy_rq(rq);
540 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
547 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
549 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
550 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
552 sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
553 sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
555 sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
558 if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
559 mlx5e_free_sq_db(sq);
563 sq->dma_fifo_mask = df_sz - 1;
568 static int mlx5e_create_sq(struct mlx5e_channel *c,
570 struct mlx5e_sq_param *param,
573 struct mlx5e_priv *priv = c->priv;
574 struct mlx5_core_dev *mdev = priv->mdev;
576 void *sqc = param->sqc;
577 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
580 err = mlx5_alloc_map_uar(mdev, &sq->uar, true);
584 param->wq.db_numa_node = cpu_to_node(c->cpu);
586 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq,
589 goto err_unmap_free_uar;
591 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
592 if (sq->uar.bf_map) {
593 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
594 sq->uar_map = sq->uar.bf_map;
596 sq->uar_map = sq->uar.map;
598 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
599 sq->max_inline = param->max_inline;
601 err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
603 goto err_sq_wq_destroy;
606 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
608 sq->ico_wqe_info = kzalloc_node(sizeof(*sq->ico_wqe_info) *
611 cpu_to_node(c->cpu));
612 if (!sq->ico_wqe_info) {
619 txq_ix = c->ix + tc * priv->params.num_channels;
620 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
621 priv->txq_to_sq_map[txq_ix] = sq;
625 sq->tstamp = &priv->tstamp;
626 sq->mkey_be = c->mkey_be;
629 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
630 sq->bf_budget = MLX5E_SQ_BF_BUDGET;
635 mlx5e_free_sq_db(sq);
638 mlx5_wq_destroy(&sq->wq_ctrl);
641 mlx5_unmap_free_uar(mdev, &sq->uar);
646 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
648 struct mlx5e_channel *c = sq->channel;
649 struct mlx5e_priv *priv = c->priv;
651 kfree(sq->ico_wqe_info);
652 mlx5e_free_sq_db(sq);
653 mlx5_wq_destroy(&sq->wq_ctrl);
654 mlx5_unmap_free_uar(priv->mdev, &sq->uar);
657 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
659 struct mlx5e_channel *c = sq->channel;
660 struct mlx5e_priv *priv = c->priv;
661 struct mlx5_core_dev *mdev = priv->mdev;
669 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
670 sizeof(u64) * sq->wq_ctrl.buf.npages;
671 in = mlx5_vzalloc(inlen);
675 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
676 wq = MLX5_ADDR_OF(sqc, sqc, wq);
678 memcpy(sqc, param->sqc, sizeof(param->sqc));
680 MLX5_SET(sqc, sqc, tis_num_0, param->icosq ? 0 : priv->tisn[sq->tc]);
681 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
682 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
683 MLX5_SET(sqc, sqc, tis_lst_sz, param->icosq ? 0 : 1);
684 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
686 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
687 MLX5_SET(wq, wq, uar_page, sq->uar.index);
688 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
689 MLX5_ADAPTER_PAGE_SHIFT);
690 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
692 mlx5_fill_page_array(&sq->wq_ctrl.buf,
693 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
695 err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
702 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
704 struct mlx5e_channel *c = sq->channel;
705 struct mlx5e_priv *priv = c->priv;
706 struct mlx5_core_dev *mdev = priv->mdev;
713 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
714 in = mlx5_vzalloc(inlen);
718 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
720 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
721 MLX5_SET(sqc, sqc, state, next_state);
723 err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
730 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
732 struct mlx5e_channel *c = sq->channel;
733 struct mlx5e_priv *priv = c->priv;
734 struct mlx5_core_dev *mdev = priv->mdev;
736 mlx5_core_destroy_sq(mdev, sq->sqn);
739 static int mlx5e_open_sq(struct mlx5e_channel *c,
741 struct mlx5e_sq_param *param,
746 err = mlx5e_create_sq(c, tc, param, sq);
750 err = mlx5e_enable_sq(sq, param);
754 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
759 set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
760 netdev_tx_reset_queue(sq->txq);
761 netif_tx_start_queue(sq->txq);
767 mlx5e_disable_sq(sq);
769 mlx5e_destroy_sq(sq);
774 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
776 __netif_tx_lock_bh(txq);
777 netif_tx_stop_queue(txq);
778 __netif_tx_unlock_bh(txq);
781 static void mlx5e_close_sq(struct mlx5e_sq *sq)
784 clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
785 /* prevent netif_tx_wake_queue */
786 napi_synchronize(&sq->channel->napi);
787 netif_tx_disable_queue(sq->txq);
789 /* ensure hw is notified of all pending wqes */
790 if (mlx5e_sq_has_room_for(sq, 1))
791 mlx5e_send_nop(sq, true);
793 mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
796 while (sq->cc != sq->pc) /* wait till sq is empty */
799 /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
800 napi_synchronize(&sq->channel->napi);
802 mlx5e_disable_sq(sq);
803 mlx5e_destroy_sq(sq);
806 static int mlx5e_create_cq(struct mlx5e_channel *c,
807 struct mlx5e_cq_param *param,
810 struct mlx5e_priv *priv = c->priv;
811 struct mlx5_core_dev *mdev = priv->mdev;
812 struct mlx5_core_cq *mcq = &cq->mcq;
818 param->wq.buf_numa_node = cpu_to_node(c->cpu);
819 param->wq.db_numa_node = cpu_to_node(c->cpu);
820 param->eq_ix = c->ix;
822 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
827 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
832 mcq->set_ci_db = cq->wq_ctrl.db.db;
833 mcq->arm_db = cq->wq_ctrl.db.db + 1;
836 mcq->vector = param->eq_ix;
837 mcq->comp = mlx5e_completion_event;
838 mcq->event = mlx5e_cq_error_event;
840 mcq->uar = &priv->cq_uar;
842 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
843 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
854 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
856 mlx5_wq_destroy(&cq->wq_ctrl);
859 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
861 struct mlx5e_priv *priv = cq->priv;
862 struct mlx5_core_dev *mdev = priv->mdev;
863 struct mlx5_core_cq *mcq = &cq->mcq;
868 unsigned int irqn_not_used;
872 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
873 sizeof(u64) * cq->wq_ctrl.buf.npages;
874 in = mlx5_vzalloc(inlen);
878 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
880 memcpy(cqc, param->cqc, sizeof(param->cqc));
882 mlx5_fill_page_array(&cq->wq_ctrl.buf,
883 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
885 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
887 MLX5_SET(cqc, cqc, c_eqn, eqn);
888 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
889 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
890 MLX5_ADAPTER_PAGE_SHIFT);
891 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
893 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
905 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
907 struct mlx5e_priv *priv = cq->priv;
908 struct mlx5_core_dev *mdev = priv->mdev;
910 mlx5_core_destroy_cq(mdev, &cq->mcq);
913 static int mlx5e_open_cq(struct mlx5e_channel *c,
914 struct mlx5e_cq_param *param,
916 u16 moderation_usecs,
917 u16 moderation_frames)
920 struct mlx5e_priv *priv = c->priv;
921 struct mlx5_core_dev *mdev = priv->mdev;
923 err = mlx5e_create_cq(c, param, cq);
927 err = mlx5e_enable_cq(cq, param);
931 if (MLX5_CAP_GEN(mdev, cq_moderation))
932 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
938 mlx5e_destroy_cq(cq);
943 static void mlx5e_close_cq(struct mlx5e_cq *cq)
945 mlx5e_disable_cq(cq);
946 mlx5e_destroy_cq(cq);
949 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
951 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
954 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
955 struct mlx5e_channel_param *cparam)
957 struct mlx5e_priv *priv = c->priv;
961 for (tc = 0; tc < c->num_tc; tc++) {
962 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
963 priv->params.tx_cq_moderation_usec,
964 priv->params.tx_cq_moderation_pkts);
966 goto err_close_tx_cqs;
972 for (tc--; tc >= 0; tc--)
973 mlx5e_close_cq(&c->sq[tc].cq);
978 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
982 for (tc = 0; tc < c->num_tc; tc++)
983 mlx5e_close_cq(&c->sq[tc].cq);
986 static int mlx5e_open_sqs(struct mlx5e_channel *c,
987 struct mlx5e_channel_param *cparam)
992 for (tc = 0; tc < c->num_tc; tc++) {
993 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1001 for (tc--; tc >= 0; tc--)
1002 mlx5e_close_sq(&c->sq[tc]);
1007 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1011 for (tc = 0; tc < c->num_tc; tc++)
1012 mlx5e_close_sq(&c->sq[tc]);
1015 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
1019 for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
1020 priv->channeltc_to_txq_map[ix][i] =
1021 ix + i * priv->params.num_channels;
1024 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1025 struct mlx5e_channel_param *cparam,
1026 struct mlx5e_channel **cp)
1028 struct net_device *netdev = priv->netdev;
1029 int cpu = mlx5e_get_cpu(priv, ix);
1030 struct mlx5e_channel *c;
1033 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1040 c->pdev = &priv->mdev->pdev->dev;
1041 c->netdev = priv->netdev;
1042 c->mkey_be = cpu_to_be32(priv->mkey.key);
1043 c->num_tc = priv->params.num_tc;
1045 mlx5e_build_channeltc_to_txq_map(priv, ix);
1047 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1049 err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, 0, 0);
1053 err = mlx5e_open_tx_cqs(c, cparam);
1055 goto err_close_icosq_cq;
1057 err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1058 priv->params.rx_cq_moderation_usec,
1059 priv->params.rx_cq_moderation_pkts);
1061 goto err_close_tx_cqs;
1063 napi_enable(&c->napi);
1065 err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
1067 goto err_disable_napi;
1069 err = mlx5e_open_sqs(c, cparam);
1071 goto err_close_icosq;
1073 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1077 netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1086 mlx5e_close_sq(&c->icosq);
1089 napi_disable(&c->napi);
1090 mlx5e_close_cq(&c->rq.cq);
1093 mlx5e_close_tx_cqs(c);
1096 mlx5e_close_cq(&c->icosq.cq);
1099 netif_napi_del(&c->napi);
1100 napi_hash_del(&c->napi);
1106 static void mlx5e_close_channel(struct mlx5e_channel *c)
1108 mlx5e_close_rq(&c->rq);
1110 mlx5e_close_sq(&c->icosq);
1111 napi_disable(&c->napi);
1112 mlx5e_close_cq(&c->rq.cq);
1113 mlx5e_close_tx_cqs(c);
1114 mlx5e_close_cq(&c->icosq.cq);
1115 netif_napi_del(&c->napi);
1117 napi_hash_del(&c->napi);
1123 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1124 struct mlx5e_rq_param *param)
1126 void *rqc = param->rqc;
1127 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1129 switch (priv->params.rq_wq_type) {
1130 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1131 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1132 MLX5_MPWRQ_LOG_NUM_STRIDES - 9);
1133 MLX5_SET(wq, wq, log_wqe_stride_size,
1134 MLX5_MPWRQ_LOG_STRIDE_SIZE - 6);
1135 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1137 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1138 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1141 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1142 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1143 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1144 MLX5_SET(wq, wq, pd, priv->pdn);
1145 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1147 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1148 param->wq.linear = 1;
1151 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1153 void *rqc = param->rqc;
1154 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1156 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1157 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1160 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1161 struct mlx5e_sq_param *param)
1163 void *sqc = param->sqc;
1164 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1166 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1167 MLX5_SET(wq, wq, pd, priv->pdn);
1169 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1172 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1173 struct mlx5e_sq_param *param)
1175 void *sqc = param->sqc;
1176 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1178 mlx5e_build_sq_param_common(priv, param);
1179 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1181 param->max_inline = priv->params.tx_max_inline;
1184 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1185 struct mlx5e_cq_param *param)
1187 void *cqc = param->cqc;
1189 MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1192 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1193 struct mlx5e_cq_param *param)
1195 void *cqc = param->cqc;
1198 switch (priv->params.rq_wq_type) {
1199 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1200 log_cq_size = priv->params.log_rq_size +
1201 MLX5_MPWRQ_LOG_NUM_STRIDES;
1203 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1204 log_cq_size = priv->params.log_rq_size;
1207 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1209 mlx5e_build_common_cq_param(priv, param);
1212 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1213 struct mlx5e_cq_param *param)
1215 void *cqc = param->cqc;
1217 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1219 mlx5e_build_common_cq_param(priv, param);
1222 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1223 struct mlx5e_cq_param *param,
1226 void *cqc = param->cqc;
1228 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1230 mlx5e_build_common_cq_param(priv, param);
1233 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1234 struct mlx5e_sq_param *param,
1237 void *sqc = param->sqc;
1238 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1240 mlx5e_build_sq_param_common(priv, param);
1242 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
1243 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
1245 param->icosq = true;
1248 static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
1250 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
1252 mlx5e_build_rq_param(priv, &cparam->rq);
1253 mlx5e_build_sq_param(priv, &cparam->sq);
1254 mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
1255 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1256 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1257 mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
1260 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1262 struct mlx5e_channel_param *cparam;
1263 int nch = priv->params.num_channels;
1268 priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1271 priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1272 sizeof(struct mlx5e_sq *), GFP_KERNEL);
1274 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1276 if (!priv->channel || !priv->txq_to_sq_map || !cparam)
1277 goto err_free_txq_to_sq_map;
1279 mlx5e_build_channel_param(priv, cparam);
1281 for (i = 0; i < nch; i++) {
1282 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
1284 goto err_close_channels;
1287 for (j = 0; j < nch; j++) {
1288 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1290 goto err_close_channels;
1297 for (i--; i >= 0; i--)
1298 mlx5e_close_channel(priv->channel[i]);
1300 err_free_txq_to_sq_map:
1301 kfree(priv->txq_to_sq_map);
1302 kfree(priv->channel);
1308 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1312 for (i = 0; i < priv->params.num_channels; i++)
1313 mlx5e_close_channel(priv->channel[i]);
1315 kfree(priv->txq_to_sq_map);
1316 kfree(priv->channel);
1319 static int mlx5e_rx_hash_fn(int hfunc)
1321 return (hfunc == ETH_RSS_HASH_TOP) ?
1322 MLX5_RX_HASH_FN_TOEPLITZ :
1323 MLX5_RX_HASH_FN_INVERTED_XOR8;
1326 static int mlx5e_bits_invert(unsigned long a, int size)
1331 for (i = 0; i < size; i++)
1332 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1337 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1341 for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1345 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1346 ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1348 ix = priv->params.indirection_rqt[ix];
1349 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1350 priv->channel[ix]->rq.rqn :
1352 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
1356 static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1359 u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1360 priv->channel[ix]->rq.rqn :
1363 MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
1366 static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, int ix, u32 *rqtn)
1368 struct mlx5_core_dev *mdev = priv->mdev;
1374 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1375 in = mlx5_vzalloc(inlen);
1379 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1381 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1382 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1384 if (sz > 1) /* RSS */
1385 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1387 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1389 err = mlx5_core_create_rqt(mdev, in, inlen, rqtn);
1395 static void mlx5e_destroy_rqt(struct mlx5e_priv *priv, u32 rqtn)
1397 mlx5_core_destroy_rqt(priv->mdev, rqtn);
1400 static int mlx5e_create_rqts(struct mlx5e_priv *priv)
1402 int nch = mlx5e_get_max_num_channels(priv->mdev);
1408 rqtn = &priv->indir_rqtn;
1409 err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqtn);
1414 for (ix = 0; ix < nch; ix++) {
1415 rqtn = &priv->direct_tir[ix].rqtn;
1416 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqtn);
1418 goto err_destroy_rqts;
1424 for (ix--; ix >= 0; ix--)
1425 mlx5e_destroy_rqt(priv, priv->direct_tir[ix].rqtn);
1427 mlx5e_destroy_rqt(priv, priv->indir_rqtn);
1432 static void mlx5e_destroy_rqts(struct mlx5e_priv *priv)
1434 int nch = mlx5e_get_max_num_channels(priv->mdev);
1437 for (i = 0; i < nch; i++)
1438 mlx5e_destroy_rqt(priv, priv->direct_tir[i].rqtn);
1440 mlx5e_destroy_rqt(priv, priv->indir_rqtn);
1443 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
1445 struct mlx5_core_dev *mdev = priv->mdev;
1451 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1452 in = mlx5_vzalloc(inlen);
1456 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1458 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1459 if (sz > 1) /* RSS */
1460 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1462 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1464 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1466 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
1473 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1478 rqtn = priv->indir_rqtn;
1479 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
1480 for (ix = 0; ix < priv->params.num_channels; ix++) {
1481 rqtn = priv->direct_tir[ix].rqtn;
1482 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
1486 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1488 if (!priv->params.lro_en)
1491 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1493 MLX5_SET(tirc, tirc, lro_enable_mask,
1494 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1495 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1496 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1497 (priv->params.lro_wqe_sz -
1498 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1499 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1500 MLX5_CAP_ETH(priv->mdev,
1501 lro_timer_supported_periods[2]));
1504 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1506 MLX5_SET(tirc, tirc, rx_hash_fn,
1507 mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1508 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1509 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1510 rx_hash_toeplitz_key);
1511 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1512 rx_hash_toeplitz_key);
1514 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1515 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1519 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
1521 struct mlx5_core_dev *mdev = priv->mdev;
1530 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1531 in = mlx5_vzalloc(inlen);
1535 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1536 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1538 mlx5e_build_tir_ctx_lro(tirc, priv);
1540 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
1541 err = mlx5_core_modify_tir(mdev, priv->indir_tirn[tt], in,
1547 for (ix = 0; ix < mlx5e_get_max_num_channels(mdev); ix++) {
1548 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
1560 static int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5e_priv *priv)
1567 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1568 in = mlx5_vzalloc(inlen);
1572 MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);
1574 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
1575 err = mlx5_core_modify_tir(priv->mdev, priv->indir_tirn[i], in,
1581 for (i = 0; i < priv->params.num_channels; i++) {
1582 err = mlx5_core_modify_tir(priv->mdev,
1583 priv->direct_tir[i].tirn, in,
1594 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
1596 struct mlx5_core_dev *mdev = priv->mdev;
1597 u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
1600 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
1604 /* Update vport context MTU */
1605 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
1609 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
1611 struct mlx5_core_dev *mdev = priv->mdev;
1615 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
1616 if (err || !hw_mtu) /* fallback to port oper mtu */
1617 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1619 *mtu = MLX5E_HW2SW_MTU(hw_mtu);
1622 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1624 struct mlx5e_priv *priv = netdev_priv(netdev);
1628 err = mlx5e_set_mtu(priv, netdev->mtu);
1632 mlx5e_query_mtu(priv, &mtu);
1633 if (mtu != netdev->mtu)
1634 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
1635 __func__, mtu, netdev->mtu);
1641 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1643 struct mlx5e_priv *priv = netdev_priv(netdev);
1644 int nch = priv->params.num_channels;
1645 int ntc = priv->params.num_tc;
1648 netdev_reset_tc(netdev);
1653 netdev_set_num_tc(netdev, ntc);
1655 for (tc = 0; tc < ntc; tc++)
1656 netdev_set_tc_queue(netdev, tc, nch, tc * nch);
1659 int mlx5e_open_locked(struct net_device *netdev)
1661 struct mlx5e_priv *priv = netdev_priv(netdev);
1665 set_bit(MLX5E_STATE_OPENED, &priv->state);
1667 mlx5e_netdev_set_tcs(netdev);
1669 num_txqs = priv->params.num_channels * priv->params.num_tc;
1670 netif_set_real_num_tx_queues(netdev, num_txqs);
1671 netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1673 err = mlx5e_set_dev_port_mtu(netdev);
1675 goto err_clear_state_opened_flag;
1677 err = mlx5e_open_channels(priv);
1679 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1681 goto err_clear_state_opened_flag;
1684 err = mlx5e_refresh_tirs_self_loopback_enable(priv);
1686 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1688 goto err_close_channels;
1691 mlx5e_redirect_rqts(priv);
1692 mlx5e_update_carrier(priv);
1693 mlx5e_timestamp_init(priv);
1695 schedule_delayed_work(&priv->update_stats_work, 0);
1700 mlx5e_close_channels(priv);
1701 err_clear_state_opened_flag:
1702 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1706 static int mlx5e_open(struct net_device *netdev)
1708 struct mlx5e_priv *priv = netdev_priv(netdev);
1711 mutex_lock(&priv->state_lock);
1712 err = mlx5e_open_locked(netdev);
1713 mutex_unlock(&priv->state_lock);
1718 int mlx5e_close_locked(struct net_device *netdev)
1720 struct mlx5e_priv *priv = netdev_priv(netdev);
1722 /* May already be CLOSED in case a previous configuration operation
1723 * (e.g RX/TX queue size change) that involves close&open failed.
1725 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1728 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1730 mlx5e_timestamp_cleanup(priv);
1731 netif_carrier_off(priv->netdev);
1732 mlx5e_redirect_rqts(priv);
1733 mlx5e_close_channels(priv);
1738 static int mlx5e_close(struct net_device *netdev)
1740 struct mlx5e_priv *priv = netdev_priv(netdev);
1743 mutex_lock(&priv->state_lock);
1744 err = mlx5e_close_locked(netdev);
1745 mutex_unlock(&priv->state_lock);
1750 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1751 struct mlx5e_rq *rq,
1752 struct mlx5e_rq_param *param)
1754 struct mlx5_core_dev *mdev = priv->mdev;
1755 void *rqc = param->rqc;
1756 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1759 param->wq.db_numa_node = param->wq.buf_numa_node;
1761 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq,
1771 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1772 struct mlx5e_cq *cq,
1773 struct mlx5e_cq_param *param)
1775 struct mlx5_core_dev *mdev = priv->mdev;
1776 struct mlx5_core_cq *mcq = &cq->mcq;
1781 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
1786 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1789 mcq->set_ci_db = cq->wq_ctrl.db.db;
1790 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1791 *mcq->set_ci_db = 0;
1793 mcq->vector = param->eq_ix;
1794 mcq->comp = mlx5e_completion_event;
1795 mcq->event = mlx5e_cq_error_event;
1797 mcq->uar = &priv->cq_uar;
1804 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1806 struct mlx5e_cq_param cq_param;
1807 struct mlx5e_rq_param rq_param;
1808 struct mlx5e_rq *rq = &priv->drop_rq;
1809 struct mlx5e_cq *cq = &priv->drop_rq.cq;
1812 memset(&cq_param, 0, sizeof(cq_param));
1813 memset(&rq_param, 0, sizeof(rq_param));
1814 mlx5e_build_drop_rq_param(&rq_param);
1816 err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1820 err = mlx5e_enable_cq(cq, &cq_param);
1822 goto err_destroy_cq;
1824 err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1826 goto err_disable_cq;
1828 err = mlx5e_enable_rq(rq, &rq_param);
1830 goto err_destroy_rq;
1835 mlx5e_destroy_rq(&priv->drop_rq);
1838 mlx5e_disable_cq(&priv->drop_rq.cq);
1841 mlx5e_destroy_cq(&priv->drop_rq.cq);
1846 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
1848 mlx5e_disable_rq(&priv->drop_rq);
1849 mlx5e_destroy_rq(&priv->drop_rq);
1850 mlx5e_disable_cq(&priv->drop_rq.cq);
1851 mlx5e_destroy_cq(&priv->drop_rq.cq);
1854 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
1856 struct mlx5_core_dev *mdev = priv->mdev;
1857 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1858 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1860 memset(in, 0, sizeof(in));
1862 MLX5_SET(tisc, tisc, prio, tc << 1);
1863 MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1865 return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1868 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
1870 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1873 static int mlx5e_create_tises(struct mlx5e_priv *priv)
1878 for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++) {
1879 err = mlx5e_create_tis(priv, tc);
1881 goto err_close_tises;
1887 for (tc--; tc >= 0; tc--)
1888 mlx5e_destroy_tis(priv, tc);
1893 static void mlx5e_destroy_tises(struct mlx5e_priv *priv)
1897 for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++)
1898 mlx5e_destroy_tis(priv, tc);
1901 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
1902 enum mlx5e_traffic_types tt)
1904 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1906 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1908 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
1909 MLX5_HASH_FIELD_SEL_DST_IP)
1911 #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
1912 MLX5_HASH_FIELD_SEL_DST_IP |\
1913 MLX5_HASH_FIELD_SEL_L4_SPORT |\
1914 MLX5_HASH_FIELD_SEL_L4_DPORT)
1916 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
1917 MLX5_HASH_FIELD_SEL_DST_IP |\
1918 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1920 mlx5e_build_tir_ctx_lro(tirc, priv);
1922 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
1923 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqtn);
1924 mlx5e_build_tir_ctx_hash(tirc, priv);
1927 case MLX5E_TT_IPV4_TCP:
1928 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1929 MLX5_L3_PROT_TYPE_IPV4);
1930 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1931 MLX5_L4_PROT_TYPE_TCP);
1932 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1933 MLX5_HASH_IP_L4PORTS);
1936 case MLX5E_TT_IPV6_TCP:
1937 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1938 MLX5_L3_PROT_TYPE_IPV6);
1939 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1940 MLX5_L4_PROT_TYPE_TCP);
1941 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1942 MLX5_HASH_IP_L4PORTS);
1945 case MLX5E_TT_IPV4_UDP:
1946 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1947 MLX5_L3_PROT_TYPE_IPV4);
1948 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1949 MLX5_L4_PROT_TYPE_UDP);
1950 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1951 MLX5_HASH_IP_L4PORTS);
1954 case MLX5E_TT_IPV6_UDP:
1955 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1956 MLX5_L3_PROT_TYPE_IPV6);
1957 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1958 MLX5_L4_PROT_TYPE_UDP);
1959 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1960 MLX5_HASH_IP_L4PORTS);
1963 case MLX5E_TT_IPV4_IPSEC_AH:
1964 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1965 MLX5_L3_PROT_TYPE_IPV4);
1966 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1967 MLX5_HASH_IP_IPSEC_SPI);
1970 case MLX5E_TT_IPV6_IPSEC_AH:
1971 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1972 MLX5_L3_PROT_TYPE_IPV6);
1973 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1974 MLX5_HASH_IP_IPSEC_SPI);
1977 case MLX5E_TT_IPV4_IPSEC_ESP:
1978 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1979 MLX5_L3_PROT_TYPE_IPV4);
1980 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1981 MLX5_HASH_IP_IPSEC_SPI);
1984 case MLX5E_TT_IPV6_IPSEC_ESP:
1985 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1986 MLX5_L3_PROT_TYPE_IPV6);
1987 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1988 MLX5_HASH_IP_IPSEC_SPI);
1992 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1993 MLX5_L3_PROT_TYPE_IPV4);
1994 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1999 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2000 MLX5_L3_PROT_TYPE_IPV6);
2001 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2006 "mlx5e_build_indir_tir_ctx: bad traffic type!\n");
2010 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2013 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2015 mlx5e_build_tir_ctx_lro(tirc, priv);
2017 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2018 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2019 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2022 static int mlx5e_create_tirs(struct mlx5e_priv *priv)
2024 int nch = mlx5e_get_max_num_channels(priv->mdev);
2033 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2034 in = mlx5_vzalloc(inlen);
2039 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2040 memset(in, 0, inlen);
2041 tirn = &priv->indir_tirn[tt];
2042 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2043 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
2044 err = mlx5_core_create_tir(priv->mdev, in, inlen, tirn);
2046 goto err_destroy_tirs;
2050 for (ix = 0; ix < nch; ix++) {
2051 memset(in, 0, inlen);
2052 tirn = &priv->direct_tir[ix].tirn;
2053 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2054 mlx5e_build_direct_tir_ctx(priv, tirc,
2055 priv->direct_tir[ix].rqtn);
2056 err = mlx5_core_create_tir(priv->mdev, in, inlen, tirn);
2058 goto err_destroy_ch_tirs;
2065 err_destroy_ch_tirs:
2066 for (ix--; ix >= 0; ix--)
2067 mlx5_core_destroy_tir(priv->mdev, priv->direct_tir[ix].tirn);
2070 for (tt--; tt >= 0; tt--)
2071 mlx5_core_destroy_tir(priv->mdev, priv->indir_tirn[tt]);
2078 static void mlx5e_destroy_tirs(struct mlx5e_priv *priv)
2080 int nch = mlx5e_get_max_num_channels(priv->mdev);
2083 for (i = 0; i < nch; i++)
2084 mlx5_core_destroy_tir(priv->mdev, priv->direct_tir[i].tirn);
2086 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2087 mlx5_core_destroy_tir(priv->mdev, priv->indir_tirn[i]);
2090 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2095 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2098 for (i = 0; i < priv->params.num_channels; i++) {
2099 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2107 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2109 struct mlx5e_priv *priv = netdev_priv(netdev);
2113 if (tc && tc != MLX5E_MAX_NUM_TC)
2116 mutex_lock(&priv->state_lock);
2118 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2120 mlx5e_close_locked(priv->netdev);
2122 priv->params.num_tc = tc ? tc : 1;
2125 err = mlx5e_open_locked(priv->netdev);
2127 mutex_unlock(&priv->state_lock);
2132 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2133 __be16 proto, struct tc_to_netdev *tc)
2135 struct mlx5e_priv *priv = netdev_priv(dev);
2137 if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2141 case TC_SETUP_CLSFLOWER:
2142 switch (tc->cls_flower->command) {
2143 case TC_CLSFLOWER_REPLACE:
2144 return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2145 case TC_CLSFLOWER_DESTROY:
2146 return mlx5e_delete_flower(priv, tc->cls_flower);
2153 if (tc->type != TC_SETUP_MQPRIO)
2156 return mlx5e_setup_tc(dev, tc->tc);
2159 static struct rtnl_link_stats64 *
2160 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2162 struct mlx5e_priv *priv = netdev_priv(dev);
2163 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
2164 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
2165 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
2167 stats->rx_packets = sstats->rx_packets;
2168 stats->rx_bytes = sstats->rx_bytes;
2169 stats->tx_packets = sstats->tx_packets;
2170 stats->tx_bytes = sstats->tx_bytes;
2172 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
2173 stats->tx_dropped = sstats->tx_queue_dropped;
2175 stats->rx_length_errors =
2176 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2177 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2178 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
2179 stats->rx_crc_errors =
2180 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2181 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2182 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
2183 stats->tx_carrier_errors =
2184 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
2185 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2186 stats->rx_frame_errors;
2187 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2189 /* vport multicast also counts packets that are dropped due to steering
2190 * or rx out of buffer
2193 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
2198 static void mlx5e_set_rx_mode(struct net_device *dev)
2200 struct mlx5e_priv *priv = netdev_priv(dev);
2202 schedule_work(&priv->set_rx_mode_work);
2205 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2207 struct mlx5e_priv *priv = netdev_priv(netdev);
2208 struct sockaddr *saddr = addr;
2210 if (!is_valid_ether_addr(saddr->sa_data))
2211 return -EADDRNOTAVAIL;
2213 netif_addr_lock_bh(netdev);
2214 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2215 netif_addr_unlock_bh(netdev);
2217 schedule_work(&priv->set_rx_mode_work);
2222 #define MLX5E_SET_FEATURE(netdev, feature, enable) \
2225 netdev->features |= feature; \
2227 netdev->features &= ~feature; \
2230 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2232 static int set_feature_lro(struct net_device *netdev, bool enable)
2234 struct mlx5e_priv *priv = netdev_priv(netdev);
2235 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2238 mutex_lock(&priv->state_lock);
2240 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2241 mlx5e_close_locked(priv->netdev);
2243 priv->params.lro_en = enable;
2244 err = mlx5e_modify_tirs_lro(priv);
2246 netdev_err(netdev, "lro modify failed, %d\n", err);
2247 priv->params.lro_en = !enable;
2250 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2251 mlx5e_open_locked(priv->netdev);
2253 mutex_unlock(&priv->state_lock);
2258 static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2260 struct mlx5e_priv *priv = netdev_priv(netdev);
2263 mlx5e_enable_vlan_filter(priv);
2265 mlx5e_disable_vlan_filter(priv);
2270 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2272 struct mlx5e_priv *priv = netdev_priv(netdev);
2274 if (!enable && mlx5e_tc_num_filters(priv)) {
2276 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2283 static int set_feature_rx_all(struct net_device *netdev, bool enable)
2285 struct mlx5e_priv *priv = netdev_priv(netdev);
2286 struct mlx5_core_dev *mdev = priv->mdev;
2288 return mlx5_set_port_fcs(mdev, !enable);
2291 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2293 struct mlx5e_priv *priv = netdev_priv(netdev);
2296 mutex_lock(&priv->state_lock);
2298 priv->params.vlan_strip_disable = !enable;
2299 err = mlx5e_modify_rqs_vsd(priv, !enable);
2301 priv->params.vlan_strip_disable = enable;
2303 mutex_unlock(&priv->state_lock);
2308 static int mlx5e_handle_feature(struct net_device *netdev,
2309 netdev_features_t wanted_features,
2310 netdev_features_t feature,
2311 mlx5e_feature_handler feature_handler)
2313 netdev_features_t changes = wanted_features ^ netdev->features;
2314 bool enable = !!(wanted_features & feature);
2317 if (!(changes & feature))
2320 err = feature_handler(netdev, enable);
2322 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2323 enable ? "Enable" : "Disable", feature, err);
2327 MLX5E_SET_FEATURE(netdev, feature, enable);
2331 static int mlx5e_set_features(struct net_device *netdev,
2332 netdev_features_t features)
2336 err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2338 err |= mlx5e_handle_feature(netdev, features,
2339 NETIF_F_HW_VLAN_CTAG_FILTER,
2340 set_feature_vlan_filter);
2341 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2342 set_feature_tc_num_filters);
2343 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2344 set_feature_rx_all);
2345 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2346 set_feature_rx_vlan);
2348 return err ? -EINVAL : 0;
2351 #define MXL5_HW_MIN_MTU 64
2352 #define MXL5E_MIN_MTU (MXL5_HW_MIN_MTU + ETH_FCS_LEN)
2354 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2356 struct mlx5e_priv *priv = netdev_priv(netdev);
2357 struct mlx5_core_dev *mdev = priv->mdev;
2363 mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2365 max_mtu = MLX5E_HW2SW_MTU(max_mtu);
2366 min_mtu = MLX5E_HW2SW_MTU(MXL5E_MIN_MTU);
2368 if (new_mtu > max_mtu || new_mtu < min_mtu) {
2370 "%s: Bad MTU (%d), valid range is: [%d..%d]\n",
2371 __func__, new_mtu, min_mtu, max_mtu);
2375 mutex_lock(&priv->state_lock);
2377 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2379 mlx5e_close_locked(netdev);
2381 netdev->mtu = new_mtu;
2384 err = mlx5e_open_locked(netdev);
2386 mutex_unlock(&priv->state_lock);
2391 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2395 return mlx5e_hwstamp_set(dev, ifr);
2397 return mlx5e_hwstamp_get(dev, ifr);
2403 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2405 struct mlx5e_priv *priv = netdev_priv(dev);
2406 struct mlx5_core_dev *mdev = priv->mdev;
2408 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2411 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2413 struct mlx5e_priv *priv = netdev_priv(dev);
2414 struct mlx5_core_dev *mdev = priv->mdev;
2416 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2420 static int mlx5_vport_link2ifla(u8 esw_link)
2423 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2424 return IFLA_VF_LINK_STATE_DISABLE;
2425 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2426 return IFLA_VF_LINK_STATE_ENABLE;
2428 return IFLA_VF_LINK_STATE_AUTO;
2431 static int mlx5_ifla_link2vport(u8 ifla_link)
2433 switch (ifla_link) {
2434 case IFLA_VF_LINK_STATE_DISABLE:
2435 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2436 case IFLA_VF_LINK_STATE_ENABLE:
2437 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2439 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2442 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2445 struct mlx5e_priv *priv = netdev_priv(dev);
2446 struct mlx5_core_dev *mdev = priv->mdev;
2448 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2449 mlx5_ifla_link2vport(link_state));
2452 static int mlx5e_get_vf_config(struct net_device *dev,
2453 int vf, struct ifla_vf_info *ivi)
2455 struct mlx5e_priv *priv = netdev_priv(dev);
2456 struct mlx5_core_dev *mdev = priv->mdev;
2459 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2462 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2466 static int mlx5e_get_vf_stats(struct net_device *dev,
2467 int vf, struct ifla_vf_stats *vf_stats)
2469 struct mlx5e_priv *priv = netdev_priv(dev);
2470 struct mlx5_core_dev *mdev = priv->mdev;
2472 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2476 static void mlx5e_add_vxlan_port(struct net_device *netdev,
2477 sa_family_t sa_family, __be16 port)
2479 struct mlx5e_priv *priv = netdev_priv(netdev);
2481 if (!mlx5e_vxlan_allowed(priv->mdev))
2484 mlx5e_vxlan_add_port(priv, be16_to_cpu(port));
2487 static void mlx5e_del_vxlan_port(struct net_device *netdev,
2488 sa_family_t sa_family, __be16 port)
2490 struct mlx5e_priv *priv = netdev_priv(netdev);
2492 if (!mlx5e_vxlan_allowed(priv->mdev))
2495 mlx5e_vxlan_del_port(priv, be16_to_cpu(port));
2498 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
2499 struct sk_buff *skb,
2500 netdev_features_t features)
2502 struct udphdr *udph;
2506 switch (vlan_get_protocol(skb)) {
2507 case htons(ETH_P_IP):
2508 proto = ip_hdr(skb)->protocol;
2510 case htons(ETH_P_IPV6):
2511 proto = ipv6_hdr(skb)->nexthdr;
2517 if (proto == IPPROTO_UDP) {
2518 udph = udp_hdr(skb);
2519 port = be16_to_cpu(udph->dest);
2522 /* Verify if UDP port is being offloaded by HW */
2523 if (port && mlx5e_vxlan_lookup_port(priv, port))
2527 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2528 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2531 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
2532 struct net_device *netdev,
2533 netdev_features_t features)
2535 struct mlx5e_priv *priv = netdev_priv(netdev);
2537 features = vlan_features_check(skb, features);
2538 features = vxlan_features_check(skb, features);
2540 /* Validate if the tunneled packet is being offloaded by HW */
2541 if (skb->encapsulation &&
2542 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
2543 return mlx5e_vxlan_features_check(priv, skb, features);
2548 static const struct net_device_ops mlx5e_netdev_ops_basic = {
2549 .ndo_open = mlx5e_open,
2550 .ndo_stop = mlx5e_close,
2551 .ndo_start_xmit = mlx5e_xmit,
2552 .ndo_setup_tc = mlx5e_ndo_setup_tc,
2553 .ndo_select_queue = mlx5e_select_queue,
2554 .ndo_get_stats64 = mlx5e_get_stats,
2555 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2556 .ndo_set_mac_address = mlx5e_set_mac,
2557 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2558 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
2559 .ndo_set_features = mlx5e_set_features,
2560 .ndo_change_mtu = mlx5e_change_mtu,
2561 .ndo_do_ioctl = mlx5e_ioctl,
2564 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2565 .ndo_open = mlx5e_open,
2566 .ndo_stop = mlx5e_close,
2567 .ndo_start_xmit = mlx5e_xmit,
2568 .ndo_setup_tc = mlx5e_ndo_setup_tc,
2569 .ndo_select_queue = mlx5e_select_queue,
2570 .ndo_get_stats64 = mlx5e_get_stats,
2571 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2572 .ndo_set_mac_address = mlx5e_set_mac,
2573 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2574 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
2575 .ndo_set_features = mlx5e_set_features,
2576 .ndo_change_mtu = mlx5e_change_mtu,
2577 .ndo_do_ioctl = mlx5e_ioctl,
2578 .ndo_add_vxlan_port = mlx5e_add_vxlan_port,
2579 .ndo_del_vxlan_port = mlx5e_del_vxlan_port,
2580 .ndo_features_check = mlx5e_features_check,
2581 .ndo_set_vf_mac = mlx5e_set_vf_mac,
2582 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
2583 .ndo_get_vf_config = mlx5e_get_vf_config,
2584 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
2585 .ndo_get_vf_stats = mlx5e_get_vf_stats,
2588 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2590 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2592 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2593 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2594 !MLX5_CAP_ETH(mdev, csum_cap) ||
2595 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2596 !MLX5_CAP_ETH(mdev, vlan_cap) ||
2597 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2598 MLX5_CAP_FLOWTABLE(mdev,
2599 flow_table_properties_nic_receive.max_ft_level)
2601 mlx5_core_warn(mdev,
2602 "Not creating net device, some required device capabilities are missing\n");
2605 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2606 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
2607 if (!MLX5_CAP_GEN(mdev, cq_moderation))
2608 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
2613 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2615 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2617 return bf_buf_size -
2618 sizeof(struct mlx5e_tx_wqe) +
2619 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2622 #ifdef CONFIG_MLX5_CORE_EN_DCB
2623 static void mlx5e_ets_init(struct mlx5e_priv *priv)
2627 priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
2628 for (i = 0; i < priv->params.ets.ets_cap; i++) {
2629 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
2630 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
2631 priv->params.ets.prio_tc[i] = i;
2634 /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2635 priv->params.ets.prio_tc[0] = 1;
2636 priv->params.ets.prio_tc[1] = 0;
2640 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
2641 u32 *indirection_rqt, int len,
2644 int node = mdev->priv.numa_node;
2645 int node_num_of_cores;
2649 node = first_online_node;
2651 node_num_of_cores = cpumask_weight(cpumask_of_node(node));
2653 if (node_num_of_cores)
2654 num_channels = min_t(int, num_channels, node_num_of_cores);
2656 for (i = 0; i < len; i++)
2657 indirection_rqt[i] = i % num_channels;
2660 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
2662 return MLX5_CAP_GEN(mdev, striding_rq) &&
2663 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
2664 MLX5_CAP_ETH(mdev, reg_umr_sq);
2667 static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
2668 struct net_device *netdev,
2671 struct mlx5e_priv *priv = netdev_priv(netdev);
2673 priv->params.log_sq_size =
2674 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2675 priv->params.rq_wq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) ?
2676 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
2677 MLX5_WQ_TYPE_LINKED_LIST;
2679 switch (priv->params.rq_wq_type) {
2680 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2681 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
2682 priv->params.lro_en = true;
2684 default: /* MLX5_WQ_TYPE_LINKED_LIST */
2685 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2688 priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
2689 BIT(priv->params.log_rq_size));
2690 priv->params.rx_cq_moderation_usec =
2691 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2692 priv->params.rx_cq_moderation_pkts =
2693 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2694 priv->params.tx_cq_moderation_usec =
2695 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2696 priv->params.tx_cq_moderation_pkts =
2697 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
2698 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
2699 priv->params.num_tc = 1;
2700 priv->params.rss_hfunc = ETH_RSS_HASH_XOR;
2702 netdev_rss_key_fill(priv->params.toeplitz_hash_key,
2703 sizeof(priv->params.toeplitz_hash_key));
2705 mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
2706 MLX5E_INDIR_RQT_SIZE, num_channels);
2708 priv->params.lro_wqe_sz =
2709 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2712 priv->netdev = netdev;
2713 priv->params.num_channels = num_channels;
2715 #ifdef CONFIG_MLX5_CORE_EN_DCB
2716 mlx5e_ets_init(priv);
2719 mutex_init(&priv->state_lock);
2721 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2722 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2723 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2726 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
2728 struct mlx5e_priv *priv = netdev_priv(netdev);
2730 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
2731 if (is_zero_ether_addr(netdev->dev_addr) &&
2732 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
2733 eth_hw_addr_random(netdev);
2734 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
2738 static void mlx5e_build_netdev(struct net_device *netdev)
2740 struct mlx5e_priv *priv = netdev_priv(netdev);
2741 struct mlx5_core_dev *mdev = priv->mdev;
2745 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
2747 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
2748 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
2749 #ifdef CONFIG_MLX5_CORE_EN_DCB
2750 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
2753 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
2756 netdev->watchdog_timeo = 15 * HZ;
2758 netdev->ethtool_ops = &mlx5e_ethtool_ops;
2760 netdev->vlan_features |= NETIF_F_SG;
2761 netdev->vlan_features |= NETIF_F_IP_CSUM;
2762 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
2763 netdev->vlan_features |= NETIF_F_GRO;
2764 netdev->vlan_features |= NETIF_F_TSO;
2765 netdev->vlan_features |= NETIF_F_TSO6;
2766 netdev->vlan_features |= NETIF_F_RXCSUM;
2767 netdev->vlan_features |= NETIF_F_RXHASH;
2769 if (!!MLX5_CAP_ETH(mdev, lro_cap))
2770 netdev->vlan_features |= NETIF_F_LRO;
2772 netdev->hw_features = netdev->vlan_features;
2773 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
2774 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
2775 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2777 if (mlx5e_vxlan_allowed(mdev)) {
2778 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL;
2779 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
2780 netdev->hw_enc_features |= NETIF_F_RXCSUM;
2781 netdev->hw_enc_features |= NETIF_F_TSO;
2782 netdev->hw_enc_features |= NETIF_F_TSO6;
2783 netdev->hw_enc_features |= NETIF_F_RXHASH;
2784 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
2787 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
2790 netdev->hw_features |= NETIF_F_RXALL;
2792 netdev->features = netdev->hw_features;
2793 if (!priv->params.lro_en)
2794 netdev->features &= ~NETIF_F_LRO;
2797 netdev->features &= ~NETIF_F_RXALL;
2799 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
2800 if (FT_CAP(flow_modify_en) &&
2801 FT_CAP(modify_root) &&
2802 FT_CAP(identified_miss_table_mode) &&
2803 FT_CAP(flow_table_modify))
2804 priv->netdev->hw_features |= NETIF_F_HW_TC;
2806 netdev->features |= NETIF_F_HIGHDMA;
2808 netdev->priv_flags |= IFF_UNICAST_FLT;
2810 mlx5e_set_netdev_dev_addr(netdev);
2813 static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
2814 struct mlx5_core_mkey *mkey)
2816 struct mlx5_core_dev *mdev = priv->mdev;
2817 struct mlx5_create_mkey_mbox_in *in;
2820 in = mlx5_vzalloc(sizeof(*in));
2824 in->seg.flags = MLX5_PERM_LOCAL_WRITE |
2825 MLX5_PERM_LOCAL_READ |
2826 MLX5_ACCESS_MODE_PA;
2827 in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
2828 in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2830 err = mlx5_core_create_mkey(mdev, mkey, in, sizeof(*in), NULL, NULL,
2838 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
2840 struct mlx5_core_dev *mdev = priv->mdev;
2843 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
2845 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
2846 priv->q_counter = 0;
2850 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
2852 if (!priv->q_counter)
2855 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
2858 static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv)
2860 struct mlx5_core_dev *mdev = priv->mdev;
2861 struct mlx5_create_mkey_mbox_in *in;
2862 struct mlx5_mkey_seg *mkc;
2863 int inlen = sizeof(*in);
2865 mlx5e_get_max_num_channels(mdev) * MLX5_CHANNEL_MAX_NUM_MTTS;
2868 in = mlx5_vzalloc(inlen);
2873 mkc->status = MLX5_MKEY_STATUS_FREE;
2874 mkc->flags = MLX5_PERM_UMR_EN |
2875 MLX5_PERM_LOCAL_READ |
2876 MLX5_PERM_LOCAL_WRITE |
2877 MLX5_ACCESS_MODE_MTT;
2879 mkc->qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2880 mkc->flags_pd = cpu_to_be32(priv->pdn);
2881 mkc->len = cpu_to_be64(npages << PAGE_SHIFT);
2882 mkc->xlt_oct_size = cpu_to_be32(mlx5e_get_mtt_octw(npages));
2883 mkc->log2_page_size = PAGE_SHIFT;
2885 err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen, NULL,
2893 static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
2895 struct net_device *netdev;
2896 struct mlx5e_priv *priv;
2897 int nch = mlx5e_get_max_num_channels(mdev);
2900 if (mlx5e_check_required_hca_cap(mdev))
2903 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
2904 nch * MLX5E_MAX_NUM_TC,
2907 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
2911 mlx5e_build_netdev_priv(mdev, netdev, nch);
2912 mlx5e_build_netdev(netdev);
2914 netif_carrier_off(netdev);
2916 priv = netdev_priv(netdev);
2918 err = mlx5_alloc_map_uar(mdev, &priv->cq_uar, false);
2920 mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err);
2921 goto err_free_netdev;
2924 err = mlx5_core_alloc_pd(mdev, &priv->pdn);
2926 mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
2927 goto err_unmap_free_uar;
2930 err = mlx5_core_alloc_transport_domain(mdev, &priv->tdn);
2932 mlx5_core_err(mdev, "alloc td failed, %d\n", err);
2933 goto err_dealloc_pd;
2936 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mkey);
2938 mlx5_core_err(mdev, "create mkey failed, %d\n", err);
2939 goto err_dealloc_transport_domain;
2942 err = mlx5e_create_umr_mkey(priv);
2944 mlx5_core_err(mdev, "create umr mkey failed, %d\n", err);
2945 goto err_destroy_mkey;
2948 err = mlx5e_create_tises(priv);
2950 mlx5_core_warn(mdev, "create tises failed, %d\n", err);
2951 goto err_destroy_umr_mkey;
2954 err = mlx5e_open_drop_rq(priv);
2956 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
2957 goto err_destroy_tises;
2960 err = mlx5e_create_rqts(priv);
2962 mlx5_core_warn(mdev, "create rqts failed, %d\n", err);
2963 goto err_close_drop_rq;
2966 err = mlx5e_create_tirs(priv);
2968 mlx5_core_warn(mdev, "create tirs failed, %d\n", err);
2969 goto err_destroy_rqts;
2972 err = mlx5e_create_flow_steering(priv);
2974 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
2975 goto err_destroy_tirs;
2978 mlx5e_create_q_counter(priv);
2980 mlx5e_init_l2_addr(priv);
2982 mlx5e_vxlan_init(priv);
2984 err = mlx5e_tc_init(priv);
2986 goto err_dealloc_q_counters;
2988 #ifdef CONFIG_MLX5_CORE_EN_DCB
2989 mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
2992 err = register_netdev(netdev);
2994 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
2995 goto err_tc_cleanup;
2998 if (mlx5e_vxlan_allowed(mdev)) {
3000 vxlan_get_rx_port(netdev);
3004 mlx5e_enable_async_events(priv);
3005 schedule_work(&priv->set_rx_mode_work);
3010 mlx5e_tc_cleanup(priv);
3012 err_dealloc_q_counters:
3013 mlx5e_destroy_q_counter(priv);
3014 mlx5e_destroy_flow_steering(priv);
3017 mlx5e_destroy_tirs(priv);
3020 mlx5e_destroy_rqts(priv);
3023 mlx5e_close_drop_rq(priv);
3026 mlx5e_destroy_tises(priv);
3028 err_destroy_umr_mkey:
3029 mlx5_core_destroy_mkey(mdev, &priv->umr_mkey);
3032 mlx5_core_destroy_mkey(mdev, &priv->mkey);
3034 err_dealloc_transport_domain:
3035 mlx5_core_dealloc_transport_domain(mdev, priv->tdn);
3038 mlx5_core_dealloc_pd(mdev, priv->pdn);
3041 mlx5_unmap_free_uar(mdev, &priv->cq_uar);
3044 free_netdev(netdev);
3049 static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
3051 struct mlx5e_priv *priv = vpriv;
3052 struct net_device *netdev = priv->netdev;
3054 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
3056 schedule_work(&priv->set_rx_mode_work);
3057 mlx5e_disable_async_events(priv);
3058 flush_scheduled_work();
3059 if (test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state)) {
3060 netif_device_detach(netdev);
3061 mutex_lock(&priv->state_lock);
3062 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
3063 mlx5e_close_locked(netdev);
3064 mutex_unlock(&priv->state_lock);
3066 unregister_netdev(netdev);
3069 mlx5e_tc_cleanup(priv);
3070 mlx5e_vxlan_cleanup(priv);
3071 mlx5e_destroy_q_counter(priv);
3072 mlx5e_destroy_flow_steering(priv);
3073 mlx5e_destroy_tirs(priv);
3074 mlx5e_destroy_rqts(priv);
3075 mlx5e_close_drop_rq(priv);
3076 mlx5e_destroy_tises(priv);
3077 mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey);
3078 mlx5_core_destroy_mkey(priv->mdev, &priv->mkey);
3079 mlx5_core_dealloc_transport_domain(priv->mdev, priv->tdn);
3080 mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
3081 mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
3083 if (!test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state))
3084 free_netdev(netdev);
3087 static void *mlx5e_get_netdev(void *vpriv)
3089 struct mlx5e_priv *priv = vpriv;
3091 return priv->netdev;
3094 static struct mlx5_interface mlx5e_interface = {
3095 .add = mlx5e_create_netdev,
3096 .remove = mlx5e_destroy_netdev,
3097 .event = mlx5e_async_event,
3098 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
3099 .get_dev = mlx5e_get_netdev,
3102 void mlx5e_init(void)
3104 mlx5_register_interface(&mlx5e_interface);
3107 void mlx5e_cleanup(void)
3109 mlx5_unregister_interface(&mlx5e_interface);