drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include "en.h"
  38 #include "en_tc.h"
  39 #include "eswitch.h"
  40 #include "vxlan.h"
  41
  42 struct mlx5e_rq_param {
  43         u32                        rqc[MLX5_ST_SZ_DW(rqc)];
  44         struct mlx5_wq_param       wq;
  45 };
  46
  47 struct mlx5e_sq_param {
  48         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  49         struct mlx5_wq_param       wq;
  50         u16                        max_inline;
  51         bool                       icosq;
  52 };
  53
  54 struct mlx5e_cq_param {
  55         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  56         struct mlx5_wq_param       wq;
  57         u16                        eq_ix;
  58 };
  59
  60 struct mlx5e_channel_param {
  61         struct mlx5e_rq_param      rq;
  62         struct mlx5e_sq_param      sq;
  63         struct mlx5e_sq_param      icosq;
  64         struct mlx5e_cq_param      rx_cq;
  65         struct mlx5e_cq_param      tx_cq;
  66         struct mlx5e_cq_param      icosq_cq;
  67 };
  68
  69 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
  70 {
  71         struct mlx5_core_dev *mdev = priv->mdev;
  72         u8 port_state;
  73
  74         port_state = mlx5_query_vport_state(mdev,
  75                 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
  76
  77         if (port_state == VPORT_STATE_UP)
  78                 netif_carrier_on(priv->netdev);
  79         else
  80                 netif_carrier_off(priv->netdev);
  81 }
  82
  83 static void mlx5e_update_carrier_work(struct work_struct *work)
  84 {
  85         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
  86                                                update_carrier_work);
  87
  88         mutex_lock(&priv->state_lock);
  89         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
  90                 mlx5e_update_carrier(priv);
  91         mutex_unlock(&priv->state_lock);
  92 }
  93
  94 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
  95 {
  96         struct mlx5e_sw_stats *s = &priv->stats.sw;
  97         struct mlx5e_rq_stats *rq_stats;
  98         struct mlx5e_sq_stats *sq_stats;
  99         u64 tx_offload_none = 0;
 100         int i, j;
 101
 102         memset(s, 0, sizeof(*s));
 103         for (i = 0; i < priv->params.num_channels; i++) {
 104                 rq_stats = &priv->channel[i]->rq.stats;
 105
 106                 s->rx_packets   += rq_stats->packets;
 107                 s->rx_bytes     += rq_stats->bytes;
 108                 s->lro_packets  += rq_stats->lro_packets;
 109                 s->lro_bytes    += rq_stats->lro_bytes;
 110                 s->rx_csum_none += rq_stats->csum_none;
 111                 s->rx_csum_sw   += rq_stats->csum_sw;
 112                 s->rx_csum_inner += rq_stats->csum_inner;
 113                 s->rx_wqe_err   += rq_stats->wqe_err;
 114                 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
 115                 s->rx_mpwqe_frag   += rq_stats->mpwqe_frag;
 116                 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
 117
 118                 for (j = 0; j < priv->params.num_tc; j++) {
 119                         sq_stats = &priv->channel[i]->sq[j].stats;
 120
 121                         s->tx_packets           += sq_stats->packets;
 122                         s->tx_bytes             += sq_stats->bytes;
 123                         s->tso_packets          += sq_stats->tso_packets;
 124                         s->tso_bytes            += sq_stats->tso_bytes;
 125                         s->tso_inner_packets    += sq_stats->tso_inner_packets;
 126                         s->tso_inner_bytes      += sq_stats->tso_inner_bytes;
 127                         s->tx_queue_stopped     += sq_stats->stopped;
 128                         s->tx_queue_wake        += sq_stats->wake;
 129                         s->tx_queue_dropped     += sq_stats->dropped;
 130                         s->tx_csum_inner        += sq_stats->csum_offload_inner;
 131                         tx_offload_none         += sq_stats->csum_offload_none;
 132                 }
 133         }
 134
 135         /* Update calculated offload counters */
 136         s->tx_csum_offload = s->tx_packets - tx_offload_none - s->tx_csum_inner;
 137         s->rx_csum_good    = s->rx_packets - s->rx_csum_none -
 138                              s->rx_csum_sw;
 139
 140         s->link_down_events = MLX5_GET(ppcnt_reg,
 141                                 priv->stats.pport.phy_counters,
 142                                 counter_set.phys_layer_cntrs.link_down_events);
 143 }
 144
 145 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
 146 {
 147         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 148         u32 *out = (u32 *)priv->stats.vport.query_vport_out;
 149         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 150         struct mlx5_core_dev *mdev = priv->mdev;
 151
 152         memset(in, 0, sizeof(in));
 153
 154         MLX5_SET(query_vport_counter_in, in, opcode,
 155                  MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 156         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 157         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 158
 159         memset(out, 0, outlen);
 160
 161         mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
 162 }
 163
 164 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 165 {
 166         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
 167         struct mlx5_core_dev *mdev = priv->mdev;
 168         int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 169         int prio;
 170         void *out;
 171         u32 *in;
 172
 173         in = mlx5_vzalloc(sz);
 174         if (!in)
 175                 goto free_out;
 176
 177         MLX5_SET(ppcnt_reg, in, local_port, 1);
 178
 179         out = pstats->IEEE_802_3_counters;
 180         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 181         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 182
 183         out = pstats->RFC_2863_counters;
 184         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 185         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 186
 187         out = pstats->RFC_2819_counters;
 188         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 189         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 190
 191         out = pstats->phy_counters;
 192         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 193         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 194
 195         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
 196         for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
 197                 out = pstats->per_prio_counters[prio];
 198                 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
 199                 mlx5_core_access_reg(mdev, in, sz, out, sz,
 200                                      MLX5_REG_PPCNT, 0, 0);
 201         }
 202
 203 free_out:
 204         kvfree(in);
 205 }
 206
 207 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
 208 {
 209         struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
 210
 211         if (!priv->q_counter)
 212                 return;
 213
 214         mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
 215                                       &qcnt->rx_out_of_buffer);
 216 }
 217
 218 void mlx5e_update_stats(struct mlx5e_priv *priv)
 219 {
 220         mlx5e_update_q_counter(priv);
 221         mlx5e_update_vport_counters(priv);
 222         mlx5e_update_pport_counters(priv);
 223         mlx5e_update_sw_counters(priv);
 224 }
 225
 226 static void mlx5e_update_stats_work(struct work_struct *work)
 227 {
 228         struct delayed_work *dwork = to_delayed_work(work);
 229         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 230                                                update_stats_work);
 231         mutex_lock(&priv->state_lock);
 232         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 233                 mlx5e_update_stats(priv);
 234                 queue_delayed_work(priv->wq, dwork,
 235                                    msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
 236         }
 237         mutex_unlock(&priv->state_lock);
 238 }
 239
 240 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 241                               enum mlx5_dev_event event, unsigned long param)
 242 {
 243         struct mlx5e_priv *priv = vpriv;
 244
 245         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
 246                 return;
 247
 248         switch (event) {
 249         case MLX5_DEV_EVENT_PORT_UP:
 250         case MLX5_DEV_EVENT_PORT_DOWN:
 251                 queue_work(priv->wq, &priv->update_carrier_work);
 252                 break;
 253
 254         default:
 255                 break;
 256         }
 257 }
 258
 259 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 260 {
 261         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 262 }
 263
 264 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 265 {
 266         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 267         synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
 268 }
 269
 270 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 271 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 272
 273 static int mlx5e_create_rq(struct mlx5e_channel *c,
 274                            struct mlx5e_rq_param *param,
 275                            struct mlx5e_rq *rq)
 276 {
 277         struct mlx5e_priv *priv = c->priv;
 278         struct mlx5_core_dev *mdev = priv->mdev;
 279         void *rqc = param->rqc;
 280         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 281         u32 byte_count;
 282         int wq_sz;
 283         int err;
 284         int i;
 285
 286         param->wq.db_numa_node = cpu_to_node(c->cpu);
 287
 288         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 289                                 &rq->wq_ctrl);
 290         if (err)
 291                 return err;
 292
 293         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 294
 295         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 296
 297         switch (priv->params.rq_wq_type) {
 298         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 299                 rq->wqe_info = kzalloc_node(wq_sz * sizeof(*rq->wqe_info),
 300                                             GFP_KERNEL, cpu_to_node(c->cpu));
 301                 if (!rq->wqe_info) {
 302                         err = -ENOMEM;
 303                         goto err_rq_wq_destroy;
 304                 }
 305                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
 306                 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
 307
 308                 rq->wqe_sz = MLX5_MPWRQ_NUM_STRIDES * MLX5_MPWRQ_STRIDE_SIZE;
 309                 byte_count = rq->wqe_sz;
 310                 break;
 311         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 312                 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
 313                                        cpu_to_node(c->cpu));
 314                 if (!rq->skb) {
 315                         err = -ENOMEM;
 316                         goto err_rq_wq_destroy;
 317                 }
 318                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
 319                 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
 320
 321                 rq->wqe_sz = (priv->params.lro_en) ?
 322                                 priv->params.lro_wqe_sz :
 323                                 MLX5E_SW2HW_MTU(priv->netdev->mtu);
 324                 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz);
 325                 byte_count = rq->wqe_sz;
 326                 byte_count |= MLX5_HW_START_PADDING;
 327         }
 328
 329         for (i = 0; i < wq_sz; i++) {
 330                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 331
 332                 wqe->data.byte_count = cpu_to_be32(byte_count);
 333         }
 334
 335         rq->wq_type = priv->params.rq_wq_type;
 336         rq->pdev    = c->pdev;
 337         rq->netdev  = c->netdev;
 338         rq->tstamp  = &priv->tstamp;
 339         rq->channel = c;
 340         rq->ix      = c->ix;
 341         rq->priv    = c->priv;
 342         rq->mkey_be = c->mkey_be;
 343         rq->umr_mkey_be = cpu_to_be32(c->priv->umr_mkey.key);
 344
 345         return 0;
 346
 347 err_rq_wq_destroy:
 348         mlx5_wq_destroy(&rq->wq_ctrl);
 349
 350         return err;
 351 }
 352
 353 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 354 {
 355         switch (rq->wq_type) {
 356         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 357                 kfree(rq->wqe_info);
 358                 break;
 359         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 360                 kfree(rq->skb);
 361         }
 362
 363         mlx5_wq_destroy(&rq->wq_ctrl);
 364 }
 365
 366 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 367 {
 368         struct mlx5e_priv *priv = rq->priv;
 369         struct mlx5_core_dev *mdev = priv->mdev;
 370
 371         void *in;
 372         void *rqc;
 373         void *wq;
 374         int inlen;
 375         int err;
 376
 377         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 378                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 379         in = mlx5_vzalloc(inlen);
 380         if (!in)
 381                 return -ENOMEM;
 382
 383         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 384         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 385
 386         memcpy(rqc, param->rqc, sizeof(param->rqc));
 387
 388         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 389         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 390         MLX5_SET(rqc,  rqc, flush_in_error_en,  1);
 391         MLX5_SET(rqc,  rqc, vsd, priv->params.vlan_strip_disable);
 392         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 393                                                 MLX5_ADAPTER_PAGE_SHIFT);
 394         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 395
 396         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 397                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 398
 399         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 400
 401         kvfree(in);
 402
 403         return err;
 404 }
 405
 406 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
 407                                  int next_state)
 408 {
 409         struct mlx5e_channel *c = rq->channel;
 410         struct mlx5e_priv *priv = c->priv;
 411         struct mlx5_core_dev *mdev = priv->mdev;
 412
 413         void *in;
 414         void *rqc;
 415         int inlen;
 416         int err;
 417
 418         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 419         in = mlx5_vzalloc(inlen);
 420         if (!in)
 421                 return -ENOMEM;
 422
 423         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 424
 425         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 426         MLX5_SET(rqc, rqc, state, next_state);
 427
 428         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 429
 430         kvfree(in);
 431
 432         return err;
 433 }
 434
 435 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 436 {
 437         struct mlx5e_channel *c = rq->channel;
 438         struct mlx5e_priv *priv = c->priv;
 439         struct mlx5_core_dev *mdev = priv->mdev;
 440
 441         void *in;
 442         void *rqc;
 443         int inlen;
 444         int err;
 445
 446         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 447         in = mlx5_vzalloc(inlen);
 448         if (!in)
 449                 return -ENOMEM;
 450
 451         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 452
 453         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 454         MLX5_SET64(modify_rq_in, in, modify_bitmask, MLX5_RQ_BITMASK_VSD);
 455         MLX5_SET(rqc, rqc, vsd, vsd);
 456         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 457
 458         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 459
 460         kvfree(in);
 461
 462         return err;
 463 }
 464
 465 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
 466 {
 467         mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
 468 }
 469
 470 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 471 {
 472         unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
 473         struct mlx5e_channel *c = rq->channel;
 474         struct mlx5e_priv *priv = c->priv;
 475         struct mlx5_wq_ll *wq = &rq->wq;
 476
 477         while (time_before(jiffies, exp_time)) {
 478                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 479                         return 0;
 480
 481                 msleep(20);
 482         }
 483
 484         return -ETIMEDOUT;
 485 }
 486
 487 static int mlx5e_open_rq(struct mlx5e_channel *c,
 488                          struct mlx5e_rq_param *param,
 489                          struct mlx5e_rq *rq)
 490 {
 491         struct mlx5e_sq *sq = &c->icosq;
 492         u16 pi = sq->pc & sq->wq.sz_m1;
 493         int err;
 494
 495         err = mlx5e_create_rq(c, param, rq);
 496         if (err)
 497                 return err;
 498
 499         err = mlx5e_enable_rq(rq, param);
 500         if (err)
 501                 goto err_destroy_rq;
 502
 503         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 504         if (err)
 505                 goto err_disable_rq;
 506
 507         set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 508
 509         sq->ico_wqe_info[pi].opcode     = MLX5_OPCODE_NOP;
 510         sq->ico_wqe_info[pi].num_wqebbs = 1;
 511         mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
 512
 513         return 0;
 514
 515 err_disable_rq:
 516         mlx5e_disable_rq(rq);
 517 err_destroy_rq:
 518         mlx5e_destroy_rq(rq);
 519
 520         return err;
 521 }
 522
 523 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 524 {
 525         clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 526         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 527
 528         mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
 529         while (!mlx5_wq_ll_is_empty(&rq->wq))
 530                 msleep(20);
 531
 532         /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
 533         napi_synchronize(&rq->channel->napi);
 534
 535         mlx5e_disable_rq(rq);
 536         mlx5e_destroy_rq(rq);
 537 }
 538
 539 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
 540 {
 541         kfree(sq->wqe_info);
 542         kfree(sq->dma_fifo);
 543         kfree(sq->skb);
 544 }
 545
 546 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
 547 {
 548         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 549         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 550
 551         sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
 552         sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
 553                                     numa);
 554         sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
 555                                     numa);
 556
 557         if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
 558                 mlx5e_free_sq_db(sq);
 559                 return -ENOMEM;
 560         }
 561
 562         sq->dma_fifo_mask = df_sz - 1;
 563
 564         return 0;
 565 }
 566
 567 static int mlx5e_create_sq(struct mlx5e_channel *c,
 568                            int tc,
 569                            struct mlx5e_sq_param *param,
 570                            struct mlx5e_sq *sq)
 571 {
 572         struct mlx5e_priv *priv = c->priv;
 573         struct mlx5_core_dev *mdev = priv->mdev;
 574
 575         void *sqc = param->sqc;
 576         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
 577         int err;
 578
 579         err = mlx5_alloc_map_uar(mdev, &sq->uar, true);
 580         if (err)
 581                 return err;
 582
 583         param->wq.db_numa_node = cpu_to_node(c->cpu);
 584
 585         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
 586                                  &sq->wq_ctrl);
 587         if (err)
 588                 goto err_unmap_free_uar;
 589
 590         sq->wq.db       = &sq->wq.db[MLX5_SND_DBR];
 591         if (sq->uar.bf_map) {
 592                 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
 593                 sq->uar_map = sq->uar.bf_map;
 594         } else {
 595                 sq->uar_map = sq->uar.map;
 596         }
 597         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
 598         sq->max_inline  = param->max_inline;
 599
 600         err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
 601         if (err)
 602                 goto err_sq_wq_destroy;
 603
 604         if (param->icosq) {
 605                 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 606
 607                 sq->ico_wqe_info = kzalloc_node(sizeof(*sq->ico_wqe_info) *
 608                                                 wq_sz,
 609                                                 GFP_KERNEL,
 610                                                 cpu_to_node(c->cpu));
 611                 if (!sq->ico_wqe_info) {
 612                         err = -ENOMEM;
 613                         goto err_free_sq_db;
 614                 }
 615         } else {
 616                 int txq_ix;
 617
 618                 txq_ix = c->ix + tc * priv->params.num_channels;
 619                 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
 620                 priv->txq_to_sq_map[txq_ix] = sq;
 621         }
 622
 623         sq->pdev      = c->pdev;
 624         sq->tstamp    = &priv->tstamp;
 625         sq->mkey_be   = c->mkey_be;
 626         sq->channel   = c;
 627         sq->tc        = tc;
 628         sq->edge      = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
 629         sq->bf_budget = MLX5E_SQ_BF_BUDGET;
 630
 631         return 0;
 632
 633 err_free_sq_db:
 634         mlx5e_free_sq_db(sq);
 635
 636 err_sq_wq_destroy:
 637         mlx5_wq_destroy(&sq->wq_ctrl);
 638
 639 err_unmap_free_uar:
 640         mlx5_unmap_free_uar(mdev, &sq->uar);
 641
 642         return err;
 643 }
 644
 645 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
 646 {
 647         struct mlx5e_channel *c = sq->channel;
 648         struct mlx5e_priv *priv = c->priv;
 649
 650         kfree(sq->ico_wqe_info);
 651         mlx5e_free_sq_db(sq);
 652         mlx5_wq_destroy(&sq->wq_ctrl);
 653         mlx5_unmap_free_uar(priv->mdev, &sq->uar);
 654 }
 655
 656 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
 657 {
 658         struct mlx5e_channel *c = sq->channel;
 659         struct mlx5e_priv *priv = c->priv;
 660         struct mlx5_core_dev *mdev = priv->mdev;
 661
 662         void *in;
 663         void *sqc;
 664         void *wq;
 665         int inlen;
 666         int err;
 667
 668         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
 669                 sizeof(u64) * sq->wq_ctrl.buf.npages;
 670         in = mlx5_vzalloc(inlen);
 671         if (!in)
 672                 return -ENOMEM;
 673
 674         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
 675         wq = MLX5_ADDR_OF(sqc, sqc, wq);
 676
 677         memcpy(sqc, param->sqc, sizeof(param->sqc));
 678
 679         MLX5_SET(sqc,  sqc, tis_num_0, param->icosq ? 0 : priv->tisn[sq->tc]);
 680         MLX5_SET(sqc,  sqc, cqn,                sq->cq.mcq.cqn);
 681         MLX5_SET(sqc,  sqc, state,              MLX5_SQC_STATE_RST);
 682         MLX5_SET(sqc,  sqc, tis_lst_sz,         param->icosq ? 0 : 1);
 683         MLX5_SET(sqc,  sqc, flush_in_error_en,  1);
 684
 685         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
 686         MLX5_SET(wq,   wq, uar_page,      sq->uar.index);
 687         MLX5_SET(wq,   wq, log_wq_pg_sz,  sq->wq_ctrl.buf.page_shift -
 688                                           MLX5_ADAPTER_PAGE_SHIFT);
 689         MLX5_SET64(wq, wq, dbr_addr,      sq->wq_ctrl.db.dma);
 690
 691         mlx5_fill_page_array(&sq->wq_ctrl.buf,
 692                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 693
 694         err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
 695
 696         kvfree(in);
 697
 698         return err;
 699 }
 700
 701 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
 702 {
 703         struct mlx5e_channel *c = sq->channel;
 704         struct mlx5e_priv *priv = c->priv;
 705         struct mlx5_core_dev *mdev = priv->mdev;
 706
 707         void *in;
 708         void *sqc;
 709         int inlen;
 710         int err;
 711
 712         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
 713         in = mlx5_vzalloc(inlen);
 714         if (!in)
 715                 return -ENOMEM;
 716
 717         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
 718
 719         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
 720         MLX5_SET(sqc, sqc, state, next_state);
 721
 722         err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
 723
 724         kvfree(in);
 725
 726         return err;
 727 }
 728
 729 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
 730 {
 731         struct mlx5e_channel *c = sq->channel;
 732         struct mlx5e_priv *priv = c->priv;
 733         struct mlx5_core_dev *mdev = priv->mdev;
 734
 735         mlx5_core_destroy_sq(mdev, sq->sqn);
 736 }
 737
 738 static int mlx5e_open_sq(struct mlx5e_channel *c,
 739                          int tc,
 740                          struct mlx5e_sq_param *param,
 741                          struct mlx5e_sq *sq)
 742 {
 743         int err;
 744
 745         err = mlx5e_create_sq(c, tc, param, sq);
 746         if (err)
 747                 return err;
 748
 749         err = mlx5e_enable_sq(sq, param);
 750         if (err)
 751                 goto err_destroy_sq;
 752
 753         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
 754         if (err)
 755                 goto err_disable_sq;
 756
 757         if (sq->txq) {
 758                 set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 759                 netdev_tx_reset_queue(sq->txq);
 760                 netif_tx_start_queue(sq->txq);
 761         }
 762
 763         return 0;
 764
 765 err_disable_sq:
 766         mlx5e_disable_sq(sq);
 767 err_destroy_sq:
 768         mlx5e_destroy_sq(sq);
 769
 770         return err;
 771 }
 772
 773 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
 774 {
 775         __netif_tx_lock_bh(txq);
 776         netif_tx_stop_queue(txq);
 777         __netif_tx_unlock_bh(txq);
 778 }
 779
 780 static void mlx5e_close_sq(struct mlx5e_sq *sq)
 781 {
 782         if (sq->txq) {
 783                 clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 784                 /* prevent netif_tx_wake_queue */
 785                 napi_synchronize(&sq->channel->napi);
 786                 netif_tx_disable_queue(sq->txq);
 787
 788                 /* ensure hw is notified of all pending wqes */
 789                 if (mlx5e_sq_has_room_for(sq, 1))
 790                         mlx5e_send_nop(sq, true);
 791
 792                 mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
 793         }
 794
 795         while (sq->cc != sq->pc) /* wait till sq is empty */
 796                 msleep(20);
 797
 798         /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
 799         napi_synchronize(&sq->channel->napi);
 800
 801         mlx5e_disable_sq(sq);
 802         mlx5e_destroy_sq(sq);
 803 }
 804
 805 static int mlx5e_create_cq(struct mlx5e_channel *c,
 806                            struct mlx5e_cq_param *param,
 807                            struct mlx5e_cq *cq)
 808 {
 809         struct mlx5e_priv *priv = c->priv;
 810         struct mlx5_core_dev *mdev = priv->mdev;
 811         struct mlx5_core_cq *mcq = &cq->mcq;
 812         int eqn_not_used;
 813         unsigned int irqn;
 814         int err;
 815         u32 i;
 816
 817         param->wq.buf_numa_node = cpu_to_node(c->cpu);
 818         param->wq.db_numa_node  = cpu_to_node(c->cpu);
 819         param->eq_ix   = c->ix;
 820
 821         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
 822                                &cq->wq_ctrl);
 823         if (err)
 824                 return err;
 825
 826         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
 827
 828         cq->napi        = &c->napi;
 829
 830         mcq->cqe_sz     = 64;
 831         mcq->set_ci_db  = cq->wq_ctrl.db.db;
 832         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
 833         *mcq->set_ci_db = 0;
 834         *mcq->arm_db    = 0;
 835         mcq->vector     = param->eq_ix;
 836         mcq->comp       = mlx5e_completion_event;
 837         mcq->event      = mlx5e_cq_error_event;
 838         mcq->irqn       = irqn;
 839         mcq->uar        = &priv->cq_uar;
 840
 841         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
 842                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
 843
 844                 cqe->op_own = 0xf1;
 845         }
 846
 847         cq->channel = c;
 848         cq->priv = priv;
 849
 850         return 0;
 851 }
 852
 853 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
 854 {
 855         mlx5_wq_destroy(&cq->wq_ctrl);
 856 }
 857
 858 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
 859 {
 860         struct mlx5e_priv *priv = cq->priv;
 861         struct mlx5_core_dev *mdev = priv->mdev;
 862         struct mlx5_core_cq *mcq = &cq->mcq;
 863
 864         void *in;
 865         void *cqc;
 866         int inlen;
 867         unsigned int irqn_not_used;
 868         int eqn;
 869         int err;
 870
 871         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
 872                 sizeof(u64) * cq->wq_ctrl.buf.npages;
 873         in = mlx5_vzalloc(inlen);
 874         if (!in)
 875                 return -ENOMEM;
 876
 877         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
 878
 879         memcpy(cqc, param->cqc, sizeof(param->cqc));
 880
 881         mlx5_fill_page_array(&cq->wq_ctrl.buf,
 882                              (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
 883
 884         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
 885
 886         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
 887         MLX5_SET(cqc,   cqc, uar_page,      mcq->uar->index);
 888         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
 889                                             MLX5_ADAPTER_PAGE_SHIFT);
 890         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
 891
 892         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
 893
 894         kvfree(in);
 895
 896         if (err)
 897                 return err;
 898
 899         mlx5e_cq_arm(cq);
 900
 901         return 0;
 902 }
 903
 904 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
 905 {
 906         struct mlx5e_priv *priv = cq->priv;
 907         struct mlx5_core_dev *mdev = priv->mdev;
 908
 909         mlx5_core_destroy_cq(mdev, &cq->mcq);
 910 }
 911
 912 static int mlx5e_open_cq(struct mlx5e_channel *c,
 913                          struct mlx5e_cq_param *param,
 914                          struct mlx5e_cq *cq,
 915                          u16 moderation_usecs,
 916                          u16 moderation_frames)
 917 {
 918         int err;
 919         struct mlx5e_priv *priv = c->priv;
 920         struct mlx5_core_dev *mdev = priv->mdev;
 921
 922         err = mlx5e_create_cq(c, param, cq);
 923         if (err)
 924                 return err;
 925
 926         err = mlx5e_enable_cq(cq, param);
 927         if (err)
 928                 goto err_destroy_cq;
 929
 930         if (MLX5_CAP_GEN(mdev, cq_moderation))
 931                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
 932                                                moderation_usecs,
 933                                                moderation_frames);
 934         return 0;
 935
 936 err_destroy_cq:
 937         mlx5e_destroy_cq(cq);
 938
 939         return err;
 940 }
 941
 942 static void mlx5e_close_cq(struct mlx5e_cq *cq)
 943 {
 944         mlx5e_disable_cq(cq);
 945         mlx5e_destroy_cq(cq);
 946 }
 947
 948 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
 949 {
 950         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
 951 }
 952
 953 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
 954                              struct mlx5e_channel_param *cparam)
 955 {
 956         struct mlx5e_priv *priv = c->priv;
 957         int err;
 958         int tc;
 959
 960         for (tc = 0; tc < c->num_tc; tc++) {
 961                 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
 962                                     priv->params.tx_cq_moderation_usec,
 963                                     priv->params.tx_cq_moderation_pkts);
 964                 if (err)
 965                         goto err_close_tx_cqs;
 966         }
 967
 968         return 0;
 969
 970 err_close_tx_cqs:
 971         for (tc--; tc >= 0; tc--)
 972                 mlx5e_close_cq(&c->sq[tc].cq);
 973
 974         return err;
 975 }
 976
 977 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
 978 {
 979         int tc;
 980
 981         for (tc = 0; tc < c->num_tc; tc++)
 982                 mlx5e_close_cq(&c->sq[tc].cq);
 983 }
 984
 985 static int mlx5e_open_sqs(struct mlx5e_channel *c,
 986                           struct mlx5e_channel_param *cparam)
 987 {
 988         int err;
 989         int tc;
 990
 991         for (tc = 0; tc < c->num_tc; tc++) {
 992                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
 993                 if (err)
 994                         goto err_close_sqs;
 995         }
 996
 997         return 0;
 998
 999 err_close_sqs:
1000         for (tc--; tc >= 0; tc--)
1001                 mlx5e_close_sq(&c->sq[tc]);
1002
1003         return err;
1004 }
1005
1006 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1007 {
1008         int tc;
1009
1010         for (tc = 0; tc < c->num_tc; tc++)
1011                 mlx5e_close_sq(&c->sq[tc]);
1012 }
1013
1014 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
1015 {
1016         int i;
1017
1018         for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
1019                 priv->channeltc_to_txq_map[ix][i] =
1020                         ix + i * priv->params.num_channels;
1021 }
1022
1023 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1024                               struct mlx5e_channel_param *cparam,
1025                               struct mlx5e_channel **cp)
1026 {
1027         struct net_device *netdev = priv->netdev;
1028         int cpu = mlx5e_get_cpu(priv, ix);
1029         struct mlx5e_channel *c;
1030         int err;
1031
1032         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1033         if (!c)
1034                 return -ENOMEM;
1035
1036         c->priv     = priv;
1037         c->ix       = ix;
1038         c->cpu      = cpu;
1039         c->pdev     = &priv->mdev->pdev->dev;
1040         c->netdev   = priv->netdev;
1041         c->mkey_be  = cpu_to_be32(priv->mkey.key);
1042         c->num_tc   = priv->params.num_tc;
1043
1044         mlx5e_build_channeltc_to_txq_map(priv, ix);
1045
1046         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1047
1048         err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, 0, 0);
1049         if (err)
1050                 goto err_napi_del;
1051
1052         err = mlx5e_open_tx_cqs(c, cparam);
1053         if (err)
1054                 goto err_close_icosq_cq;
1055
1056         err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1057                             priv->params.rx_cq_moderation_usec,
1058                             priv->params.rx_cq_moderation_pkts);
1059         if (err)
1060                 goto err_close_tx_cqs;
1061
1062         napi_enable(&c->napi);
1063
1064         err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
1065         if (err)
1066                 goto err_disable_napi;
1067
1068         err = mlx5e_open_sqs(c, cparam);
1069         if (err)
1070                 goto err_close_icosq;
1071
1072         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1073         if (err)
1074                 goto err_close_sqs;
1075
1076         netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1077         *cp = c;
1078
1079         return 0;
1080
1081 err_close_sqs:
1082         mlx5e_close_sqs(c);
1083
1084 err_close_icosq:
1085         mlx5e_close_sq(&c->icosq);
1086
1087 err_disable_napi:
1088         napi_disable(&c->napi);
1089         mlx5e_close_cq(&c->rq.cq);
1090
1091 err_close_tx_cqs:
1092         mlx5e_close_tx_cqs(c);
1093
1094 err_close_icosq_cq:
1095         mlx5e_close_cq(&c->icosq.cq);
1096
1097 err_napi_del:
1098         netif_napi_del(&c->napi);
1099         napi_hash_del(&c->napi);
1100         kfree(c);
1101
1102         return err;
1103 }
1104
1105 static void mlx5e_close_channel(struct mlx5e_channel *c)
1106 {
1107         mlx5e_close_rq(&c->rq);
1108         mlx5e_close_sqs(c);
1109         mlx5e_close_sq(&c->icosq);
1110         napi_disable(&c->napi);
1111         mlx5e_close_cq(&c->rq.cq);
1112         mlx5e_close_tx_cqs(c);
1113         mlx5e_close_cq(&c->icosq.cq);
1114         netif_napi_del(&c->napi);
1115
1116         napi_hash_del(&c->napi);
1117         synchronize_rcu();
1118
1119         kfree(c);
1120 }
1121
1122 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1123                                  struct mlx5e_rq_param *param)
1124 {
1125         void *rqc = param->rqc;
1126         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1127
1128         switch (priv->params.rq_wq_type) {
1129         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1130                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1131                          MLX5_MPWRQ_LOG_NUM_STRIDES - 9);
1132                 MLX5_SET(wq, wq, log_wqe_stride_size,
1133                          MLX5_MPWRQ_LOG_STRIDE_SIZE - 6);
1134                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1135                 break;
1136         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1137                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1138         }
1139
1140         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1141         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1142         MLX5_SET(wq, wq, log_wq_sz,        priv->params.log_rq_size);
1143         MLX5_SET(wq, wq, pd,               priv->pdn);
1144         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1145
1146         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1147         param->wq.linear = 1;
1148 }
1149
1150 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1151 {
1152         void *rqc = param->rqc;
1153         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1154
1155         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1156         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1157 }
1158
1159 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1160                                         struct mlx5e_sq_param *param)
1161 {
1162         void *sqc = param->sqc;
1163         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1164
1165         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1166         MLX5_SET(wq, wq, pd,            priv->pdn);
1167
1168         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1169 }
1170
1171 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1172                                  struct mlx5e_sq_param *param)
1173 {
1174         void *sqc = param->sqc;
1175         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1176
1177         mlx5e_build_sq_param_common(priv, param);
1178         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1179
1180         param->max_inline = priv->params.tx_max_inline;
1181 }
1182
1183 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1184                                         struct mlx5e_cq_param *param)
1185 {
1186         void *cqc = param->cqc;
1187
1188         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1189 }
1190
1191 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1192                                     struct mlx5e_cq_param *param)
1193 {
1194         void *cqc = param->cqc;
1195         u8 log_cq_size;
1196
1197         switch (priv->params.rq_wq_type) {
1198         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1199                 log_cq_size = priv->params.log_rq_size +
1200                         MLX5_MPWRQ_LOG_NUM_STRIDES;
1201                 break;
1202         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1203                 log_cq_size = priv->params.log_rq_size;
1204         }
1205
1206         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1207
1208         mlx5e_build_common_cq_param(priv, param);
1209 }
1210
1211 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1212                                     struct mlx5e_cq_param *param)
1213 {
1214         void *cqc = param->cqc;
1215
1216         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1217
1218         mlx5e_build_common_cq_param(priv, param);
1219 }
1220
1221 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1222                                      struct mlx5e_cq_param *param,
1223                                      u8 log_wq_size)
1224 {
1225         void *cqc = param->cqc;
1226
1227         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1228
1229         mlx5e_build_common_cq_param(priv, param);
1230 }
1231
1232 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1233                                     struct mlx5e_sq_param *param,
1234                                     u8 log_wq_size)
1235 {
1236         void *sqc = param->sqc;
1237         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1238
1239         mlx5e_build_sq_param_common(priv, param);
1240
1241         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
1242         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
1243
1244         param->icosq = true;
1245 }
1246
1247 static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
1248 {
1249         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
1250
1251         mlx5e_build_rq_param(priv, &cparam->rq);
1252         mlx5e_build_sq_param(priv, &cparam->sq);
1253         mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
1254         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1255         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1256         mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
1257 }
1258
1259 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1260 {
1261         struct mlx5e_channel_param *cparam;
1262         int nch = priv->params.num_channels;
1263         int err = -ENOMEM;
1264         int i;
1265         int j;
1266
1267         priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1268                                 GFP_KERNEL);
1269
1270         priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1271                                       sizeof(struct mlx5e_sq *), GFP_KERNEL);
1272
1273         cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1274
1275         if (!priv->channel || !priv->txq_to_sq_map || !cparam)
1276                 goto err_free_txq_to_sq_map;
1277
1278         mlx5e_build_channel_param(priv, cparam);
1279
1280         for (i = 0; i < nch; i++) {
1281                 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
1282                 if (err)
1283                         goto err_close_channels;
1284         }
1285
1286         for (j = 0; j < nch; j++) {
1287                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1288                 if (err)
1289                         goto err_close_channels;
1290         }
1291
1292         kfree(cparam);
1293         return 0;
1294
1295 err_close_channels:
1296         for (i--; i >= 0; i--)
1297                 mlx5e_close_channel(priv->channel[i]);
1298
1299 err_free_txq_to_sq_map:
1300         kfree(priv->txq_to_sq_map);
1301         kfree(priv->channel);
1302         kfree(cparam);
1303
1304         return err;
1305 }
1306
1307 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1308 {
1309         int i;
1310
1311         for (i = 0; i < priv->params.num_channels; i++)
1312                 mlx5e_close_channel(priv->channel[i]);
1313
1314         kfree(priv->txq_to_sq_map);
1315         kfree(priv->channel);
1316 }
1317
1318 static int mlx5e_rx_hash_fn(int hfunc)
1319 {
1320         return (hfunc == ETH_RSS_HASH_TOP) ?
1321                MLX5_RX_HASH_FN_TOEPLITZ :
1322                MLX5_RX_HASH_FN_INVERTED_XOR8;
1323 }
1324
1325 static int mlx5e_bits_invert(unsigned long a, int size)
1326 {
1327         int inv = 0;
1328         int i;
1329
1330         for (i = 0; i < size; i++)
1331                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1332
1333         return inv;
1334 }
1335
1336 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1337 {
1338         int i;
1339
1340         for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1341                 int ix = i;
1342                 u32 rqn;
1343
1344                 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1345                         ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1346
1347                 ix = priv->params.indirection_rqt[ix];
1348                 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1349                                 priv->channel[ix]->rq.rqn :
1350                                 priv->drop_rq.rqn;
1351                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
1352         }
1353 }
1354
1355 static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1356                                       int ix)
1357 {
1358         u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1359                         priv->channel[ix]->rq.rqn :
1360                         priv->drop_rq.rqn;
1361
1362         MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
1363 }
1364
1365 static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, int ix, u32 *rqtn)
1366 {
1367         struct mlx5_core_dev *mdev = priv->mdev;
1368         void *rqtc;
1369         int inlen;
1370         int err;
1371         u32 *in;
1372
1373         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1374         in = mlx5_vzalloc(inlen);
1375         if (!in)
1376                 return -ENOMEM;
1377
1378         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1379
1380         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1381         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1382
1383         if (sz > 1) /* RSS */
1384                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1385         else
1386                 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1387
1388         err = mlx5_core_create_rqt(mdev, in, inlen, rqtn);
1389
1390         kvfree(in);
1391         return err;
1392 }
1393
1394 static void mlx5e_destroy_rqt(struct mlx5e_priv *priv, u32 rqtn)
1395 {
1396         mlx5_core_destroy_rqt(priv->mdev, rqtn);
1397 }
1398
1399 static int mlx5e_create_rqts(struct mlx5e_priv *priv)
1400 {
1401         int nch = mlx5e_get_max_num_channels(priv->mdev);
1402         u32 *rqtn;
1403         int err;
1404         int ix;
1405
1406         /* Indirect RQT */
1407         rqtn = &priv->indir_rqtn;
1408         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqtn);
1409         if (err)
1410                 return err;
1411
1412         /* Direct RQTs */
1413         for (ix = 0; ix < nch; ix++) {
1414                 rqtn = &priv->direct_tir[ix].rqtn;
1415                 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqtn);
1416                 if (err)
1417                         goto err_destroy_rqts;
1418         }
1419
1420         return 0;
1421
1422 err_destroy_rqts:
1423         for (ix--; ix >= 0; ix--)
1424                 mlx5e_destroy_rqt(priv, priv->direct_tir[ix].rqtn);
1425
1426         mlx5e_destroy_rqt(priv, priv->indir_rqtn);
1427
1428         return err;
1429 }
1430
1431 static void mlx5e_destroy_rqts(struct mlx5e_priv *priv)
1432 {
1433         int nch = mlx5e_get_max_num_channels(priv->mdev);
1434         int i;
1435
1436         for (i = 0; i < nch; i++)
1437                 mlx5e_destroy_rqt(priv, priv->direct_tir[i].rqtn);
1438
1439         mlx5e_destroy_rqt(priv, priv->indir_rqtn);
1440 }
1441
1442 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
1443 {
1444         struct mlx5_core_dev *mdev = priv->mdev;
1445         void *rqtc;
1446         int inlen;
1447         u32 *in;
1448         int err;
1449
1450         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1451         in = mlx5_vzalloc(inlen);
1452         if (!in)
1453                 return -ENOMEM;
1454
1455         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1456
1457         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1458         if (sz > 1) /* RSS */
1459                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1460         else
1461                 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1462
1463         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1464
1465         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
1466
1467         kvfree(in);
1468
1469         return err;
1470 }
1471
1472 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1473 {
1474         u32 rqtn;
1475         int ix;
1476
1477         rqtn = priv->indir_rqtn;
1478         mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
1479         for (ix = 0; ix < priv->params.num_channels; ix++) {
1480                 rqtn = priv->direct_tir[ix].rqtn;
1481                 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
1482         }
1483 }
1484
1485 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1486 {
1487         if (!priv->params.lro_en)
1488                 return;
1489
1490 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1491
1492         MLX5_SET(tirc, tirc, lro_enable_mask,
1493                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1494                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1495         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1496                  (priv->params.lro_wqe_sz -
1497                   ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1498         MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1499                  MLX5_CAP_ETH(priv->mdev,
1500                               lro_timer_supported_periods[2]));
1501 }
1502
1503 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1504 {
1505         MLX5_SET(tirc, tirc, rx_hash_fn,
1506                  mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1507         if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1508                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1509                                              rx_hash_toeplitz_key);
1510                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1511                                                rx_hash_toeplitz_key);
1512
1513                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1514                 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1515         }
1516 }
1517
1518 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
1519 {
1520         struct mlx5_core_dev *mdev = priv->mdev;
1521
1522         void *in;
1523         void *tirc;
1524         int inlen;
1525         int err;
1526         int tt;
1527         int ix;
1528
1529         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1530         in = mlx5_vzalloc(inlen);
1531         if (!in)
1532                 return -ENOMEM;
1533
1534         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1535         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1536
1537         mlx5e_build_tir_ctx_lro(tirc, priv);
1538
1539         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
1540                 err = mlx5_core_modify_tir(mdev, priv->indir_tirn[tt], in,
1541                                            inlen);
1542                 if (err)
1543                         goto free_in;
1544         }
1545
1546         for (ix = 0; ix < mlx5e_get_max_num_channels(mdev); ix++) {
1547                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
1548                                            in, inlen);
1549                 if (err)
1550                         goto free_in;
1551         }
1552
1553 free_in:
1554         kvfree(in);
1555
1556         return err;
1557 }
1558
1559 static int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5e_priv *priv)
1560 {
1561         void *in;
1562         int inlen;
1563         int err;
1564         int i;
1565
1566         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1567         in = mlx5_vzalloc(inlen);
1568         if (!in)
1569                 return -ENOMEM;
1570
1571         MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);
1572
1573         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
1574                 err = mlx5_core_modify_tir(priv->mdev, priv->indir_tirn[i], in,
1575                                            inlen);
1576                 if (err)
1577                         return err;
1578         }
1579
1580         for (i = 0; i < priv->params.num_channels; i++) {
1581                 err = mlx5_core_modify_tir(priv->mdev,
1582                                            priv->direct_tir[i].tirn, in,
1583                                            inlen);
1584                 if (err)
1585                         return err;
1586         }
1587
1588         kvfree(in);
1589
1590         return 0;
1591 }
1592
1593 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
1594 {
1595         struct mlx5_core_dev *mdev = priv->mdev;
1596         u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
1597         int err;
1598
1599         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
1600         if (err)
1601                 return err;
1602
1603         /* Update vport context MTU */
1604         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
1605         return 0;
1606 }
1607
1608 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
1609 {
1610         struct mlx5_core_dev *mdev = priv->mdev;
1611         u16 hw_mtu = 0;
1612         int err;
1613
1614         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
1615         if (err || !hw_mtu) /* fallback to port oper mtu */
1616                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1617
1618         *mtu = MLX5E_HW2SW_MTU(hw_mtu);
1619 }
1620
1621 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1622 {
1623         struct mlx5e_priv *priv = netdev_priv(netdev);
1624         u16 mtu;
1625         int err;
1626
1627         err = mlx5e_set_mtu(priv, netdev->mtu);
1628         if (err)
1629                 return err;
1630
1631         mlx5e_query_mtu(priv, &mtu);
1632         if (mtu != netdev->mtu)
1633                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
1634                             __func__, mtu, netdev->mtu);
1635
1636         netdev->mtu = mtu;
1637         return 0;
1638 }
1639
1640 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1641 {
1642         struct mlx5e_priv *priv = netdev_priv(netdev);
1643         int nch = priv->params.num_channels;
1644         int ntc = priv->params.num_tc;
1645         int tc;
1646
1647         netdev_reset_tc(netdev);
1648
1649         if (ntc == 1)
1650                 return;
1651
1652         netdev_set_num_tc(netdev, ntc);
1653
1654         for (tc = 0; tc < ntc; tc++)
1655                 netdev_set_tc_queue(netdev, tc, nch, tc * nch);
1656 }
1657
1658 int mlx5e_open_locked(struct net_device *netdev)
1659 {
1660         struct mlx5e_priv *priv = netdev_priv(netdev);
1661         int num_txqs;
1662         int err;
1663
1664         set_bit(MLX5E_STATE_OPENED, &priv->state);
1665
1666         mlx5e_netdev_set_tcs(netdev);
1667
1668         num_txqs = priv->params.num_channels * priv->params.num_tc;
1669         netif_set_real_num_tx_queues(netdev, num_txqs);
1670         netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1671
1672         err = mlx5e_set_dev_port_mtu(netdev);
1673         if (err)
1674                 goto err_clear_state_opened_flag;
1675
1676         err = mlx5e_open_channels(priv);
1677         if (err) {
1678                 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1679                            __func__, err);
1680                 goto err_clear_state_opened_flag;
1681         }
1682
1683         err = mlx5e_refresh_tirs_self_loopback_enable(priv);
1684         if (err) {
1685                 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1686                            __func__, err);
1687                 goto err_close_channels;
1688         }
1689
1690         mlx5e_redirect_rqts(priv);
1691         mlx5e_update_carrier(priv);
1692         mlx5e_timestamp_init(priv);
1693 #ifdef CONFIG_RFS_ACCEL
1694         priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
1695 #endif
1696
1697         queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
1698
1699         return 0;
1700
1701 err_close_channels:
1702         mlx5e_close_channels(priv);
1703 err_clear_state_opened_flag:
1704         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1705         return err;
1706 }
1707
1708 static int mlx5e_open(struct net_device *netdev)
1709 {
1710         struct mlx5e_priv *priv = netdev_priv(netdev);
1711         int err;
1712
1713         mutex_lock(&priv->state_lock);
1714         err = mlx5e_open_locked(netdev);
1715         mutex_unlock(&priv->state_lock);
1716
1717         return err;
1718 }
1719
1720 int mlx5e_close_locked(struct net_device *netdev)
1721 {
1722         struct mlx5e_priv *priv = netdev_priv(netdev);
1723
1724         /* May already be CLOSED in case a previous configuration operation
1725          * (e.g RX/TX queue size change) that involves close&open failed.
1726          */
1727         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1728                 return 0;
1729
1730         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1731
1732         mlx5e_timestamp_cleanup(priv);
1733         netif_carrier_off(priv->netdev);
1734         mlx5e_redirect_rqts(priv);
1735         mlx5e_close_channels(priv);
1736
1737         return 0;
1738 }
1739
1740 static int mlx5e_close(struct net_device *netdev)
1741 {
1742         struct mlx5e_priv *priv = netdev_priv(netdev);
1743         int err;
1744
1745         mutex_lock(&priv->state_lock);
1746         err = mlx5e_close_locked(netdev);
1747         mutex_unlock(&priv->state_lock);
1748
1749         return err;
1750 }
1751
1752 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1753                                 struct mlx5e_rq *rq,
1754                                 struct mlx5e_rq_param *param)
1755 {
1756         struct mlx5_core_dev *mdev = priv->mdev;
1757         void *rqc = param->rqc;
1758         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1759         int err;
1760
1761         param->wq.db_numa_node = param->wq.buf_numa_node;
1762
1763         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1764                                 &rq->wq_ctrl);
1765         if (err)
1766                 return err;
1767
1768         rq->priv = priv;
1769
1770         return 0;
1771 }
1772
1773 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1774                                 struct mlx5e_cq *cq,
1775                                 struct mlx5e_cq_param *param)
1776 {
1777         struct mlx5_core_dev *mdev = priv->mdev;
1778         struct mlx5_core_cq *mcq = &cq->mcq;
1779         int eqn_not_used;
1780         unsigned int irqn;
1781         int err;
1782
1783         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1784                                &cq->wq_ctrl);
1785         if (err)
1786                 return err;
1787
1788         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1789
1790         mcq->cqe_sz     = 64;
1791         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1792         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1793         *mcq->set_ci_db = 0;
1794         *mcq->arm_db    = 0;
1795         mcq->vector     = param->eq_ix;
1796         mcq->comp       = mlx5e_completion_event;
1797         mcq->event      = mlx5e_cq_error_event;
1798         mcq->irqn       = irqn;
1799         mcq->uar        = &priv->cq_uar;
1800
1801         cq->priv = priv;
1802
1803         return 0;
1804 }
1805
1806 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1807 {
1808         struct mlx5e_cq_param cq_param;
1809         struct mlx5e_rq_param rq_param;
1810         struct mlx5e_rq *rq = &priv->drop_rq;
1811         struct mlx5e_cq *cq = &priv->drop_rq.cq;
1812         int err;
1813
1814         memset(&cq_param, 0, sizeof(cq_param));
1815         memset(&rq_param, 0, sizeof(rq_param));
1816         mlx5e_build_drop_rq_param(&rq_param);
1817
1818         err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1819         if (err)
1820                 return err;
1821
1822         err = mlx5e_enable_cq(cq, &cq_param);
1823         if (err)
1824                 goto err_destroy_cq;
1825
1826         err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1827         if (err)
1828                 goto err_disable_cq;
1829
1830         err = mlx5e_enable_rq(rq, &rq_param);
1831         if (err)
1832                 goto err_destroy_rq;
1833
1834         return 0;
1835
1836 err_destroy_rq:
1837         mlx5e_destroy_rq(&priv->drop_rq);
1838
1839 err_disable_cq:
1840         mlx5e_disable_cq(&priv->drop_rq.cq);
1841
1842 err_destroy_cq:
1843         mlx5e_destroy_cq(&priv->drop_rq.cq);
1844
1845         return err;
1846 }
1847
1848 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
1849 {
1850         mlx5e_disable_rq(&priv->drop_rq);
1851         mlx5e_destroy_rq(&priv->drop_rq);
1852         mlx5e_disable_cq(&priv->drop_rq.cq);
1853         mlx5e_destroy_cq(&priv->drop_rq.cq);
1854 }
1855
1856 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
1857 {
1858         struct mlx5_core_dev *mdev = priv->mdev;
1859         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1860         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1861
1862         memset(in, 0, sizeof(in));
1863
1864         MLX5_SET(tisc, tisc, prio, tc << 1);
1865         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1866
1867         return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1868 }
1869
1870 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
1871 {
1872         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1873 }
1874
1875 static int mlx5e_create_tises(struct mlx5e_priv *priv)
1876 {
1877         int err;
1878         int tc;
1879
1880         for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++) {
1881                 err = mlx5e_create_tis(priv, tc);
1882                 if (err)
1883                         goto err_close_tises;
1884         }
1885
1886         return 0;
1887
1888 err_close_tises:
1889         for (tc--; tc >= 0; tc--)
1890                 mlx5e_destroy_tis(priv, tc);
1891
1892         return err;
1893 }
1894
1895 static void mlx5e_destroy_tises(struct mlx5e_priv *priv)
1896 {
1897         int tc;
1898
1899         for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++)
1900                 mlx5e_destroy_tis(priv, tc);
1901 }
1902
1903 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
1904                                       enum mlx5e_traffic_types tt)
1905 {
1906         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1907
1908         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1909
1910 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1911                                  MLX5_HASH_FIELD_SEL_DST_IP)
1912
1913 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1914                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1915                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
1916                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
1917
1918 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1919                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1920                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1921
1922         mlx5e_build_tir_ctx_lro(tirc, priv);
1923
1924         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
1925         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqtn);
1926         mlx5e_build_tir_ctx_hash(tirc, priv);
1927
1928         switch (tt) {
1929         case MLX5E_TT_IPV4_TCP:
1930                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1931                          MLX5_L3_PROT_TYPE_IPV4);
1932                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1933                          MLX5_L4_PROT_TYPE_TCP);
1934                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1935                          MLX5_HASH_IP_L4PORTS);
1936                 break;
1937
1938         case MLX5E_TT_IPV6_TCP:
1939                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1940                          MLX5_L3_PROT_TYPE_IPV6);
1941                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1942                          MLX5_L4_PROT_TYPE_TCP);
1943                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1944                          MLX5_HASH_IP_L4PORTS);
1945                 break;
1946
1947         case MLX5E_TT_IPV4_UDP:
1948                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1949                          MLX5_L3_PROT_TYPE_IPV4);
1950                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1951                          MLX5_L4_PROT_TYPE_UDP);
1952                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1953                          MLX5_HASH_IP_L4PORTS);
1954                 break;
1955
1956         case MLX5E_TT_IPV6_UDP:
1957                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1958                          MLX5_L3_PROT_TYPE_IPV6);
1959                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1960                          MLX5_L4_PROT_TYPE_UDP);
1961                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1962                          MLX5_HASH_IP_L4PORTS);
1963                 break;
1964
1965         case MLX5E_TT_IPV4_IPSEC_AH:
1966                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1967                          MLX5_L3_PROT_TYPE_IPV4);
1968                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1969                          MLX5_HASH_IP_IPSEC_SPI);
1970                 break;
1971
1972         case MLX5E_TT_IPV6_IPSEC_AH:
1973                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1974                          MLX5_L3_PROT_TYPE_IPV6);
1975                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1976                          MLX5_HASH_IP_IPSEC_SPI);
1977                 break;
1978
1979         case MLX5E_TT_IPV4_IPSEC_ESP:
1980                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1981                          MLX5_L3_PROT_TYPE_IPV4);
1982                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1983                          MLX5_HASH_IP_IPSEC_SPI);
1984                 break;
1985
1986         case MLX5E_TT_IPV6_IPSEC_ESP:
1987                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1988                          MLX5_L3_PROT_TYPE_IPV6);
1989                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1990                          MLX5_HASH_IP_IPSEC_SPI);
1991                 break;
1992
1993         case MLX5E_TT_IPV4:
1994                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1995                          MLX5_L3_PROT_TYPE_IPV4);
1996                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1997                          MLX5_HASH_IP);
1998                 break;
1999
2000         case MLX5E_TT_IPV6:
2001                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2002                          MLX5_L3_PROT_TYPE_IPV6);
2003                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2004                          MLX5_HASH_IP);
2005                 break;
2006         default:
2007                 WARN_ONCE(true,
2008                           "mlx5e_build_indir_tir_ctx: bad traffic type!\n");
2009         }
2010 }
2011
2012 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2013                                        u32 rqtn)
2014 {
2015         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2016
2017         mlx5e_build_tir_ctx_lro(tirc, priv);
2018
2019         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2020         MLX5_SET(tirc, tirc, indirect_table, rqtn);
2021         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2022 }
2023
2024 static int mlx5e_create_tirs(struct mlx5e_priv *priv)
2025 {
2026         int nch = mlx5e_get_max_num_channels(priv->mdev);
2027         void *tirc;
2028         int inlen;
2029         u32 *tirn;
2030         int err;
2031         u32 *in;
2032         int ix;
2033         int tt;
2034
2035         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2036         in = mlx5_vzalloc(inlen);
2037         if (!in)
2038                 return -ENOMEM;
2039
2040         /* indirect tirs */
2041         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2042                 memset(in, 0, inlen);
2043                 tirn = &priv->indir_tirn[tt];
2044                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2045                 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
2046                 err = mlx5_core_create_tir(priv->mdev, in, inlen, tirn);
2047                 if (err)
2048                         goto err_destroy_tirs;
2049         }
2050
2051         /* direct tirs */
2052         for (ix = 0; ix < nch; ix++) {
2053                 memset(in, 0, inlen);
2054                 tirn = &priv->direct_tir[ix].tirn;
2055                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2056                 mlx5e_build_direct_tir_ctx(priv, tirc,
2057                                            priv->direct_tir[ix].rqtn);
2058                 err = mlx5_core_create_tir(priv->mdev, in, inlen, tirn);
2059                 if (err)
2060                         goto err_destroy_ch_tirs;
2061         }
2062
2063         kvfree(in);
2064
2065         return 0;
2066
2067 err_destroy_ch_tirs:
2068         for (ix--; ix >= 0; ix--)
2069                 mlx5_core_destroy_tir(priv->mdev, priv->direct_tir[ix].tirn);
2070
2071 err_destroy_tirs:
2072         for (tt--; tt >= 0; tt--)
2073                 mlx5_core_destroy_tir(priv->mdev, priv->indir_tirn[tt]);
2074
2075         kvfree(in);
2076
2077         return err;
2078 }
2079
2080 static void mlx5e_destroy_tirs(struct mlx5e_priv *priv)
2081 {
2082         int nch = mlx5e_get_max_num_channels(priv->mdev);
2083         int i;
2084
2085         for (i = 0; i < nch; i++)
2086                 mlx5_core_destroy_tir(priv->mdev, priv->direct_tir[i].tirn);
2087
2088         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2089                 mlx5_core_destroy_tir(priv->mdev, priv->indir_tirn[i]);
2090 }
2091
2092 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2093 {
2094         int err = 0;
2095         int i;
2096
2097         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2098                 return 0;
2099
2100         for (i = 0; i < priv->params.num_channels; i++) {
2101                 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2102                 if (err)
2103                         return err;
2104         }
2105
2106         return 0;
2107 }
2108
2109 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2110 {
2111         struct mlx5e_priv *priv = netdev_priv(netdev);
2112         bool was_opened;
2113         int err = 0;
2114
2115         if (tc && tc != MLX5E_MAX_NUM_TC)
2116                 return -EINVAL;
2117
2118         mutex_lock(&priv->state_lock);
2119
2120         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2121         if (was_opened)
2122                 mlx5e_close_locked(priv->netdev);
2123
2124         priv->params.num_tc = tc ? tc : 1;
2125
2126         if (was_opened)
2127                 err = mlx5e_open_locked(priv->netdev);
2128
2129         mutex_unlock(&priv->state_lock);
2130
2131         return err;
2132 }
2133
2134 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2135                               __be16 proto, struct tc_to_netdev *tc)
2136 {
2137         struct mlx5e_priv *priv = netdev_priv(dev);
2138
2139         if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2140                 goto mqprio;
2141
2142         switch (tc->type) {
2143         case TC_SETUP_CLSFLOWER:
2144                 switch (tc->cls_flower->command) {
2145                 case TC_CLSFLOWER_REPLACE:
2146                         return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2147                 case TC_CLSFLOWER_DESTROY:
2148                         return mlx5e_delete_flower(priv, tc->cls_flower);
2149                 }
2150         default:
2151                 return -EOPNOTSUPP;
2152         }
2153
2154 mqprio:
2155         if (tc->type != TC_SETUP_MQPRIO)
2156                 return -EINVAL;
2157
2158         return mlx5e_setup_tc(dev, tc->tc);
2159 }
2160
2161 static struct rtnl_link_stats64 *
2162 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2163 {
2164         struct mlx5e_priv *priv = netdev_priv(dev);
2165         struct mlx5e_sw_stats *sstats = &priv->stats.sw;
2166         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
2167         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
2168
2169         stats->rx_packets = sstats->rx_packets;
2170         stats->rx_bytes   = sstats->rx_bytes;
2171         stats->tx_packets = sstats->tx_packets;
2172         stats->tx_bytes   = sstats->tx_bytes;
2173
2174         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
2175         stats->tx_dropped = sstats->tx_queue_dropped;
2176
2177         stats->rx_length_errors =
2178                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2179                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2180                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
2181         stats->rx_crc_errors =
2182                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2183         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2184         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
2185         stats->tx_carrier_errors =
2186                 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
2187         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2188                            stats->rx_frame_errors;
2189         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2190
2191         /* vport multicast also counts packets that are dropped due to steering
2192          * or rx out of buffer
2193          */
2194         stats->multicast =
2195                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
2196
2197         return stats;
2198 }
2199
2200 static void mlx5e_set_rx_mode(struct net_device *dev)
2201 {
2202         struct mlx5e_priv *priv = netdev_priv(dev);
2203
2204         queue_work(priv->wq, &priv->set_rx_mode_work);
2205 }
2206
2207 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2208 {
2209         struct mlx5e_priv *priv = netdev_priv(netdev);
2210         struct sockaddr *saddr = addr;
2211
2212         if (!is_valid_ether_addr(saddr->sa_data))
2213                 return -EADDRNOTAVAIL;
2214
2215         netif_addr_lock_bh(netdev);
2216         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2217         netif_addr_unlock_bh(netdev);
2218
2219         queue_work(priv->wq, &priv->set_rx_mode_work);
2220
2221         return 0;
2222 }
2223
2224 #define MLX5E_SET_FEATURE(netdev, feature, enable)      \
2225         do {                                            \
2226                 if (enable)                             \
2227                         netdev->features |= feature;    \
2228                 else                                    \
2229                         netdev->features &= ~feature;   \
2230         } while (0)
2231
2232 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2233
2234 static int set_feature_lro(struct net_device *netdev, bool enable)
2235 {
2236         struct mlx5e_priv *priv = netdev_priv(netdev);
2237         bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2238         int err;
2239
2240         mutex_lock(&priv->state_lock);
2241
2242         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2243                 mlx5e_close_locked(priv->netdev);
2244
2245         priv->params.lro_en = enable;
2246         err = mlx5e_modify_tirs_lro(priv);
2247         if (err) {
2248                 netdev_err(netdev, "lro modify failed, %d\n", err);
2249                 priv->params.lro_en = !enable;
2250         }
2251
2252         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2253                 mlx5e_open_locked(priv->netdev);
2254
2255         mutex_unlock(&priv->state_lock);
2256
2257         return err;
2258 }
2259
2260 static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2261 {
2262         struct mlx5e_priv *priv = netdev_priv(netdev);
2263
2264         if (enable)
2265                 mlx5e_enable_vlan_filter(priv);
2266         else
2267                 mlx5e_disable_vlan_filter(priv);
2268
2269         return 0;
2270 }
2271
2272 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2273 {
2274         struct mlx5e_priv *priv = netdev_priv(netdev);
2275
2276         if (!enable && mlx5e_tc_num_filters(priv)) {
2277                 netdev_err(netdev,
2278                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2279                 return -EINVAL;
2280         }
2281
2282         return 0;
2283 }
2284
2285 static int set_feature_rx_all(struct net_device *netdev, bool enable)
2286 {
2287         struct mlx5e_priv *priv = netdev_priv(netdev);
2288         struct mlx5_core_dev *mdev = priv->mdev;
2289
2290         return mlx5_set_port_fcs(mdev, !enable);
2291 }
2292
2293 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2294 {
2295         struct mlx5e_priv *priv = netdev_priv(netdev);
2296         int err;
2297
2298         mutex_lock(&priv->state_lock);
2299
2300         priv->params.vlan_strip_disable = !enable;
2301         err = mlx5e_modify_rqs_vsd(priv, !enable);
2302         if (err)
2303                 priv->params.vlan_strip_disable = enable;
2304
2305         mutex_unlock(&priv->state_lock);
2306
2307         return err;
2308 }
2309
2310 #ifdef CONFIG_RFS_ACCEL
2311 static int set_feature_arfs(struct net_device *netdev, bool enable)
2312 {
2313         struct mlx5e_priv *priv = netdev_priv(netdev);
2314         int err;
2315
2316         if (enable)
2317                 err = mlx5e_arfs_enable(priv);
2318         else
2319                 err = mlx5e_arfs_disable(priv);
2320
2321         return err;
2322 }
2323 #endif
2324
2325 static int mlx5e_handle_feature(struct net_device *netdev,
2326                                 netdev_features_t wanted_features,
2327                                 netdev_features_t feature,
2328                                 mlx5e_feature_handler feature_handler)
2329 {
2330         netdev_features_t changes = wanted_features ^ netdev->features;
2331         bool enable = !!(wanted_features & feature);
2332         int err;
2333
2334         if (!(changes & feature))
2335                 return 0;
2336
2337         err = feature_handler(netdev, enable);
2338         if (err) {
2339                 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2340                            enable ? "Enable" : "Disable", feature, err);
2341                 return err;
2342         }
2343
2344         MLX5E_SET_FEATURE(netdev, feature, enable);
2345         return 0;
2346 }
2347
2348 static int mlx5e_set_features(struct net_device *netdev,
2349                               netdev_features_t features)
2350 {
2351         int err;
2352
2353         err  = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2354                                     set_feature_lro);
2355         err |= mlx5e_handle_feature(netdev, features,
2356                                     NETIF_F_HW_VLAN_CTAG_FILTER,
2357                                     set_feature_vlan_filter);
2358         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2359                                     set_feature_tc_num_filters);
2360         err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2361                                     set_feature_rx_all);
2362         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2363                                     set_feature_rx_vlan);
2364 #ifdef CONFIG_RFS_ACCEL
2365         err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2366                                     set_feature_arfs);
2367 #endif
2368
2369         return err ? -EINVAL : 0;
2370 }
2371
2372 #define MXL5_HW_MIN_MTU 64
2373 #define MXL5E_MIN_MTU (MXL5_HW_MIN_MTU + ETH_FCS_LEN)
2374
2375 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2376 {
2377         struct mlx5e_priv *priv = netdev_priv(netdev);
2378         struct mlx5_core_dev *mdev = priv->mdev;
2379         bool was_opened;
2380         u16 max_mtu;
2381         u16 min_mtu;
2382         int err = 0;
2383
2384         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2385
2386         max_mtu = MLX5E_HW2SW_MTU(max_mtu);
2387         min_mtu = MLX5E_HW2SW_MTU(MXL5E_MIN_MTU);
2388
2389         if (new_mtu > max_mtu || new_mtu < min_mtu) {
2390                 netdev_err(netdev,
2391                            "%s: Bad MTU (%d), valid range is: [%d..%d]\n",
2392                            __func__, new_mtu, min_mtu, max_mtu);
2393                 return -EINVAL;
2394         }
2395
2396         mutex_lock(&priv->state_lock);
2397
2398         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2399         if (was_opened)
2400                 mlx5e_close_locked(netdev);
2401
2402         netdev->mtu = new_mtu;
2403
2404         if (was_opened)
2405                 err = mlx5e_open_locked(netdev);
2406
2407         mutex_unlock(&priv->state_lock);
2408
2409         return err;
2410 }
2411
2412 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2413 {
2414         switch (cmd) {
2415         case SIOCSHWTSTAMP:
2416                 return mlx5e_hwstamp_set(dev, ifr);
2417         case SIOCGHWTSTAMP:
2418                 return mlx5e_hwstamp_get(dev, ifr);
2419         default:
2420                 return -EOPNOTSUPP;
2421         }
2422 }
2423
2424 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2425 {
2426         struct mlx5e_priv *priv = netdev_priv(dev);
2427         struct mlx5_core_dev *mdev = priv->mdev;
2428
2429         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2430 }
2431
2432 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2433 {
2434         struct mlx5e_priv *priv = netdev_priv(dev);
2435         struct mlx5_core_dev *mdev = priv->mdev;
2436
2437         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2438                                            vlan, qos);
2439 }
2440
2441 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2442 {
2443         struct mlx5e_priv *priv = netdev_priv(dev);
2444         struct mlx5_core_dev *mdev = priv->mdev;
2445
2446         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
2447 }
2448
2449 static int mlx5_vport_link2ifla(u8 esw_link)
2450 {
2451         switch (esw_link) {
2452         case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2453                 return IFLA_VF_LINK_STATE_DISABLE;
2454         case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2455                 return IFLA_VF_LINK_STATE_ENABLE;
2456         }
2457         return IFLA_VF_LINK_STATE_AUTO;
2458 }
2459
2460 static int mlx5_ifla_link2vport(u8 ifla_link)
2461 {
2462         switch (ifla_link) {
2463         case IFLA_VF_LINK_STATE_DISABLE:
2464                 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2465         case IFLA_VF_LINK_STATE_ENABLE:
2466                 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2467         }
2468         return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2469 }
2470
2471 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2472                                    int link_state)
2473 {
2474         struct mlx5e_priv *priv = netdev_priv(dev);
2475         struct mlx5_core_dev *mdev = priv->mdev;
2476
2477         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2478                                             mlx5_ifla_link2vport(link_state));
2479 }
2480
2481 static int mlx5e_get_vf_config(struct net_device *dev,
2482                                int vf, struct ifla_vf_info *ivi)
2483 {
2484         struct mlx5e_priv *priv = netdev_priv(dev);
2485         struct mlx5_core_dev *mdev = priv->mdev;
2486         int err;
2487
2488         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2489         if (err)
2490                 return err;
2491         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2492         return 0;
2493 }
2494
2495 static int mlx5e_get_vf_stats(struct net_device *dev,
2496                               int vf, struct ifla_vf_stats *vf_stats)
2497 {
2498         struct mlx5e_priv *priv = netdev_priv(dev);
2499         struct mlx5_core_dev *mdev = priv->mdev;
2500
2501         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2502                                             vf_stats);
2503 }
2504
2505 static void mlx5e_add_vxlan_port(struct net_device *netdev,
2506                                  sa_family_t sa_family, __be16 port)
2507 {
2508         struct mlx5e_priv *priv = netdev_priv(netdev);
2509
2510         if (!mlx5e_vxlan_allowed(priv->mdev))
2511                 return;
2512
2513         mlx5e_vxlan_queue_work(priv, sa_family, be16_to_cpu(port), 1);
2514 }
2515
2516 static void mlx5e_del_vxlan_port(struct net_device *netdev,
2517                                  sa_family_t sa_family, __be16 port)
2518 {
2519         struct mlx5e_priv *priv = netdev_priv(netdev);
2520
2521         if (!mlx5e_vxlan_allowed(priv->mdev))
2522                 return;
2523
2524         mlx5e_vxlan_queue_work(priv, sa_family, be16_to_cpu(port), 0);
2525 }
2526
2527 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
2528                                                     struct sk_buff *skb,
2529                                                     netdev_features_t features)
2530 {
2531         struct udphdr *udph;
2532         u16 proto;
2533         u16 port = 0;
2534
2535         switch (vlan_get_protocol(skb)) {
2536         case htons(ETH_P_IP):
2537                 proto = ip_hdr(skb)->protocol;
2538                 break;
2539         case htons(ETH_P_IPV6):
2540                 proto = ipv6_hdr(skb)->nexthdr;
2541                 break;
2542         default:
2543                 goto out;
2544         }
2545
2546         if (proto == IPPROTO_UDP) {
2547                 udph = udp_hdr(skb);
2548                 port = be16_to_cpu(udph->dest);
2549         }
2550
2551         /* Verify if UDP port is being offloaded by HW */
2552         if (port && mlx5e_vxlan_lookup_port(priv, port))
2553                 return features;
2554
2555 out:
2556         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2557         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2558 }
2559
2560 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
2561                                               struct net_device *netdev,
2562                                               netdev_features_t features)
2563 {
2564         struct mlx5e_priv *priv = netdev_priv(netdev);
2565
2566         features = vlan_features_check(skb, features);
2567         features = vxlan_features_check(skb, features);
2568
2569         /* Validate if the tunneled packet is being offloaded by HW */
2570         if (skb->encapsulation &&
2571             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
2572                 return mlx5e_vxlan_features_check(priv, skb, features);
2573
2574         return features;
2575 }
2576
2577 static const struct net_device_ops mlx5e_netdev_ops_basic = {
2578         .ndo_open                = mlx5e_open,
2579         .ndo_stop                = mlx5e_close,
2580         .ndo_start_xmit          = mlx5e_xmit,
2581         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2582         .ndo_select_queue        = mlx5e_select_queue,
2583         .ndo_get_stats64         = mlx5e_get_stats,
2584         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2585         .ndo_set_mac_address     = mlx5e_set_mac,
2586         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2587         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2588         .ndo_set_features        = mlx5e_set_features,
2589         .ndo_change_mtu          = mlx5e_change_mtu,
2590         .ndo_do_ioctl            = mlx5e_ioctl,
2591 #ifdef CONFIG_RFS_ACCEL
2592         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
2593 #endif
2594 };
2595
2596 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2597         .ndo_open                = mlx5e_open,
2598         .ndo_stop                = mlx5e_close,
2599         .ndo_start_xmit          = mlx5e_xmit,
2600         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2601         .ndo_select_queue        = mlx5e_select_queue,
2602         .ndo_get_stats64         = mlx5e_get_stats,
2603         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2604         .ndo_set_mac_address     = mlx5e_set_mac,
2605         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2606         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2607         .ndo_set_features        = mlx5e_set_features,
2608         .ndo_change_mtu          = mlx5e_change_mtu,
2609         .ndo_do_ioctl            = mlx5e_ioctl,
2610         .ndo_add_vxlan_port      = mlx5e_add_vxlan_port,
2611         .ndo_del_vxlan_port      = mlx5e_del_vxlan_port,
2612         .ndo_features_check      = mlx5e_features_check,
2613 #ifdef CONFIG_RFS_ACCEL
2614         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
2615 #endif
2616         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
2617         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
2618         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
2619         .ndo_get_vf_config       = mlx5e_get_vf_config,
2620         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
2621         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
2622 };
2623
2624 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2625 {
2626         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2627                 return -ENOTSUPP;
2628         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2629             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2630             !MLX5_CAP_ETH(mdev, csum_cap) ||
2631             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2632             !MLX5_CAP_ETH(mdev, vlan_cap) ||
2633             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2634             MLX5_CAP_FLOWTABLE(mdev,
2635                                flow_table_properties_nic_receive.max_ft_level)
2636                                < 3) {
2637                 mlx5_core_warn(mdev,
2638                                "Not creating net device, some required device capabilities are missing\n");
2639                 return -ENOTSUPP;
2640         }
2641         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2642                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
2643         if (!MLX5_CAP_GEN(mdev, cq_moderation))
2644                 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
2645
2646         return 0;
2647 }
2648
2649 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2650 {
2651         int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2652
2653         return bf_buf_size -
2654                sizeof(struct mlx5e_tx_wqe) +
2655                2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2656 }
2657
2658 #ifdef CONFIG_MLX5_CORE_EN_DCB
2659 static void mlx5e_ets_init(struct mlx5e_priv *priv)
2660 {
2661         int i;
2662
2663         priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
2664         for (i = 0; i < priv->params.ets.ets_cap; i++) {
2665                 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
2666                 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
2667                 priv->params.ets.prio_tc[i] = i;
2668         }
2669
2670         /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2671         priv->params.ets.prio_tc[0] = 1;
2672         priv->params.ets.prio_tc[1] = 0;
2673 }
2674 #endif
2675
2676 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
2677                                    u32 *indirection_rqt, int len,
2678                                    int num_channels)
2679 {
2680         int node = mdev->priv.numa_node;
2681         int node_num_of_cores;
2682         int i;
2683
2684         if (node == -1)
2685                 node = first_online_node;
2686
2687         node_num_of_cores = cpumask_weight(cpumask_of_node(node));
2688
2689         if (node_num_of_cores)
2690                 num_channels = min_t(int, num_channels, node_num_of_cores);
2691
2692         for (i = 0; i < len; i++)
2693                 indirection_rqt[i] = i % num_channels;
2694 }
2695
2696 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
2697 {
2698         return MLX5_CAP_GEN(mdev, striding_rq) &&
2699                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
2700                 MLX5_CAP_ETH(mdev, reg_umr_sq);
2701 }
2702
2703 static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
2704                                     struct net_device *netdev,
2705                                     int num_channels)
2706 {
2707         struct mlx5e_priv *priv = netdev_priv(netdev);
2708
2709         priv->params.log_sq_size           =
2710                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2711         priv->params.rq_wq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) ?
2712                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
2713                 MLX5_WQ_TYPE_LINKED_LIST;
2714
2715         switch (priv->params.rq_wq_type) {
2716         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2717                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
2718                 priv->params.lro_en = true;
2719                 break;
2720         default: /* MLX5_WQ_TYPE_LINKED_LIST */
2721                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2722         }
2723
2724         priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
2725                                             BIT(priv->params.log_rq_size));
2726         priv->params.rx_cq_moderation_usec =
2727                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2728         priv->params.rx_cq_moderation_pkts =
2729                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2730         priv->params.tx_cq_moderation_usec =
2731                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2732         priv->params.tx_cq_moderation_pkts =
2733                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
2734         priv->params.tx_max_inline         = mlx5e_get_max_inline_cap(mdev);
2735         priv->params.num_tc                = 1;
2736         priv->params.rss_hfunc             = ETH_RSS_HASH_XOR;
2737
2738         netdev_rss_key_fill(priv->params.toeplitz_hash_key,
2739                             sizeof(priv->params.toeplitz_hash_key));
2740
2741         mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
2742                                       MLX5E_INDIR_RQT_SIZE, num_channels);
2743
2744         priv->params.lro_wqe_sz            =
2745                 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2746
2747         priv->mdev                         = mdev;
2748         priv->netdev                       = netdev;
2749         priv->params.num_channels          = num_channels;
2750
2751 #ifdef CONFIG_MLX5_CORE_EN_DCB
2752         mlx5e_ets_init(priv);
2753 #endif
2754
2755         mutex_init(&priv->state_lock);
2756
2757         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2758         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2759         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2760 }
2761
2762 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
2763 {
2764         struct mlx5e_priv *priv = netdev_priv(netdev);
2765
2766         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
2767         if (is_zero_ether_addr(netdev->dev_addr) &&
2768             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
2769                 eth_hw_addr_random(netdev);
2770                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
2771         }
2772 }
2773
2774 static void mlx5e_build_netdev(struct net_device *netdev)
2775 {
2776         struct mlx5e_priv *priv = netdev_priv(netdev);
2777         struct mlx5_core_dev *mdev = priv->mdev;
2778         bool fcs_supported;
2779         bool fcs_enabled;
2780
2781         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
2782
2783         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
2784                 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
2785 #ifdef CONFIG_MLX5_CORE_EN_DCB
2786                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
2787 #endif
2788         } else {
2789                 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
2790         }
2791
2792         netdev->watchdog_timeo    = 15 * HZ;
2793
2794         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
2795
2796         netdev->vlan_features    |= NETIF_F_SG;
2797         netdev->vlan_features    |= NETIF_F_IP_CSUM;
2798         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
2799         netdev->vlan_features    |= NETIF_F_GRO;
2800         netdev->vlan_features    |= NETIF_F_TSO;
2801         netdev->vlan_features    |= NETIF_F_TSO6;
2802         netdev->vlan_features    |= NETIF_F_RXCSUM;
2803         netdev->vlan_features    |= NETIF_F_RXHASH;
2804
2805         if (!!MLX5_CAP_ETH(mdev, lro_cap))
2806                 netdev->vlan_features    |= NETIF_F_LRO;
2807
2808         netdev->hw_features       = netdev->vlan_features;
2809         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
2810         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
2811         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
2812
2813         if (mlx5e_vxlan_allowed(mdev)) {
2814                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
2815                                            NETIF_F_GSO_UDP_TUNNEL_CSUM |
2816                                            NETIF_F_GSO_PARTIAL;
2817                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
2818                 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
2819                 netdev->hw_enc_features |= NETIF_F_TSO;
2820                 netdev->hw_enc_features |= NETIF_F_TSO6;
2821                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
2822                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
2823                                            NETIF_F_GSO_PARTIAL;
2824                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
2825         }
2826
2827         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
2828
2829         if (fcs_supported)
2830                 netdev->hw_features |= NETIF_F_RXALL;
2831
2832         netdev->features          = netdev->hw_features;
2833         if (!priv->params.lro_en)
2834                 netdev->features  &= ~NETIF_F_LRO;
2835
2836         if (fcs_enabled)
2837                 netdev->features  &= ~NETIF_F_RXALL;
2838
2839 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
2840         if (FT_CAP(flow_modify_en) &&
2841             FT_CAP(modify_root) &&
2842             FT_CAP(identified_miss_table_mode) &&
2843             FT_CAP(flow_table_modify)) {
2844                 netdev->hw_features      |= NETIF_F_HW_TC;
2845 #ifdef CONFIG_RFS_ACCEL
2846                 netdev->hw_features      |= NETIF_F_NTUPLE;
2847 #endif
2848         }
2849
2850         netdev->features         |= NETIF_F_HIGHDMA;
2851
2852         netdev->priv_flags       |= IFF_UNICAST_FLT;
2853
2854         mlx5e_set_netdev_dev_addr(netdev);
2855 }
2856
2857 static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
2858                              struct mlx5_core_mkey *mkey)
2859 {
2860         struct mlx5_core_dev *mdev = priv->mdev;
2861         struct mlx5_create_mkey_mbox_in *in;
2862         int err;
2863
2864         in = mlx5_vzalloc(sizeof(*in));
2865         if (!in)
2866                 return -ENOMEM;
2867
2868         in->seg.flags = MLX5_PERM_LOCAL_WRITE |
2869                         MLX5_PERM_LOCAL_READ  |
2870                         MLX5_ACCESS_MODE_PA;
2871         in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
2872         in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2873
2874         err = mlx5_core_create_mkey(mdev, mkey, in, sizeof(*in), NULL, NULL,
2875                                     NULL);
2876
2877         kvfree(in);
2878
2879         return err;
2880 }
2881
2882 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
2883 {
2884         struct mlx5_core_dev *mdev = priv->mdev;
2885         int err;
2886
2887         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
2888         if (err) {
2889                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
2890                 priv->q_counter = 0;
2891         }
2892 }
2893
2894 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
2895 {
2896         if (!priv->q_counter)
2897                 return;
2898
2899         mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
2900 }
2901
2902 static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv)
2903 {
2904         struct mlx5_core_dev *mdev = priv->mdev;
2905         struct mlx5_create_mkey_mbox_in *in;
2906         struct mlx5_mkey_seg *mkc;
2907         int inlen = sizeof(*in);
2908         u64 npages =
2909                 mlx5e_get_max_num_channels(mdev) * MLX5_CHANNEL_MAX_NUM_MTTS;
2910         int err;
2911
2912         in = mlx5_vzalloc(inlen);
2913         if (!in)
2914                 return -ENOMEM;
2915
2916         mkc = &in->seg;
2917         mkc->status = MLX5_MKEY_STATUS_FREE;
2918         mkc->flags = MLX5_PERM_UMR_EN |
2919                      MLX5_PERM_LOCAL_READ |
2920                      MLX5_PERM_LOCAL_WRITE |
2921                      MLX5_ACCESS_MODE_MTT;
2922
2923         mkc->qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2924         mkc->flags_pd = cpu_to_be32(priv->pdn);
2925         mkc->len = cpu_to_be64(npages << PAGE_SHIFT);
2926         mkc->xlt_oct_size = cpu_to_be32(mlx5e_get_mtt_octw(npages));
2927         mkc->log2_page_size = PAGE_SHIFT;
2928
2929         err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen, NULL,
2930                                     NULL, NULL);
2931
2932         kvfree(in);
2933
2934         return err;
2935 }
2936
2937 static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
2938 {
2939         struct net_device *netdev;
2940         struct mlx5e_priv *priv;
2941         int nch = mlx5e_get_max_num_channels(mdev);
2942         int err;
2943
2944         if (mlx5e_check_required_hca_cap(mdev))
2945                 return NULL;
2946
2947         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
2948                                     nch * MLX5E_MAX_NUM_TC,
2949                                     nch);
2950         if (!netdev) {
2951                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
2952                 return NULL;
2953         }
2954
2955         mlx5e_build_netdev_priv(mdev, netdev, nch);
2956         mlx5e_build_netdev(netdev);
2957
2958         netif_carrier_off(netdev);
2959
2960         priv = netdev_priv(netdev);
2961
2962         priv->wq = create_singlethread_workqueue("mlx5e");
2963         if (!priv->wq)
2964                 goto err_free_netdev;
2965
2966         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar, false);
2967         if (err) {
2968                 mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err);
2969                 goto err_destroy_wq;
2970         }
2971
2972         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
2973         if (err) {
2974                 mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
2975                 goto err_unmap_free_uar;
2976         }
2977
2978         err = mlx5_core_alloc_transport_domain(mdev, &priv->tdn);
2979         if (err) {
2980                 mlx5_core_err(mdev, "alloc td failed, %d\n", err);
2981                 goto err_dealloc_pd;
2982         }
2983
2984         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mkey);
2985         if (err) {
2986                 mlx5_core_err(mdev, "create mkey failed, %d\n", err);
2987                 goto err_dealloc_transport_domain;
2988         }
2989
2990         err = mlx5e_create_umr_mkey(priv);
2991         if (err) {
2992                 mlx5_core_err(mdev, "create umr mkey failed, %d\n", err);
2993                 goto err_destroy_mkey;
2994         }
2995
2996         err = mlx5e_create_tises(priv);
2997         if (err) {
2998                 mlx5_core_warn(mdev, "create tises failed, %d\n", err);
2999                 goto err_destroy_umr_mkey;
3000         }
3001
3002         err = mlx5e_open_drop_rq(priv);
3003         if (err) {
3004                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
3005                 goto err_destroy_tises;
3006         }
3007
3008         err = mlx5e_create_rqts(priv);
3009         if (err) {
3010                 mlx5_core_warn(mdev, "create rqts failed, %d\n", err);
3011                 goto err_close_drop_rq;
3012         }
3013
3014         err = mlx5e_create_tirs(priv);
3015         if (err) {
3016                 mlx5_core_warn(mdev, "create tirs failed, %d\n", err);
3017                 goto err_destroy_rqts;
3018         }
3019
3020         err = mlx5e_create_flow_steering(priv);
3021         if (err) {
3022                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
3023                 goto err_destroy_tirs;
3024         }
3025
3026         mlx5e_create_q_counter(priv);
3027
3028         mlx5e_init_l2_addr(priv);
3029
3030         mlx5e_vxlan_init(priv);
3031
3032         err = mlx5e_tc_init(priv);
3033         if (err)
3034                 goto err_dealloc_q_counters;
3035
3036 #ifdef CONFIG_MLX5_CORE_EN_DCB
3037         mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
3038 #endif
3039
3040         err = register_netdev(netdev);
3041         if (err) {
3042                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
3043                 goto err_tc_cleanup;
3044         }
3045
3046         if (mlx5e_vxlan_allowed(mdev)) {
3047                 rtnl_lock();
3048                 vxlan_get_rx_port(netdev);
3049                 rtnl_unlock();
3050         }
3051
3052         mlx5e_enable_async_events(priv);
3053         queue_work(priv->wq, &priv->set_rx_mode_work);
3054
3055         return priv;
3056
3057 err_tc_cleanup:
3058         mlx5e_tc_cleanup(priv);
3059
3060 err_dealloc_q_counters:
3061         mlx5e_destroy_q_counter(priv);
3062         mlx5e_destroy_flow_steering(priv);
3063
3064 err_destroy_tirs:
3065         mlx5e_destroy_tirs(priv);
3066
3067 err_destroy_rqts:
3068         mlx5e_destroy_rqts(priv);
3069
3070 err_close_drop_rq:
3071         mlx5e_close_drop_rq(priv);
3072
3073 err_destroy_tises:
3074         mlx5e_destroy_tises(priv);
3075
3076 err_destroy_umr_mkey:
3077         mlx5_core_destroy_mkey(mdev, &priv->umr_mkey);
3078
3079 err_destroy_mkey:
3080         mlx5_core_destroy_mkey(mdev, &priv->mkey);
3081
3082 err_dealloc_transport_domain:
3083         mlx5_core_dealloc_transport_domain(mdev, priv->tdn);
3084
3085 err_dealloc_pd:
3086         mlx5_core_dealloc_pd(mdev, priv->pdn);
3087
3088 err_unmap_free_uar:
3089         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
3090
3091 err_destroy_wq:
3092         destroy_workqueue(priv->wq);
3093
3094 err_free_netdev:
3095         free_netdev(netdev);
3096
3097         return NULL;
3098 }
3099
3100 static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
3101 {
3102         struct mlx5e_priv *priv = vpriv;
3103         struct net_device *netdev = priv->netdev;
3104
3105         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
3106
3107         queue_work(priv->wq, &priv->set_rx_mode_work);
3108         mlx5e_disable_async_events(priv);
3109         flush_workqueue(priv->wq);
3110         if (test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state)) {
3111                 netif_device_detach(netdev);
3112                 mutex_lock(&priv->state_lock);
3113                 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
3114                         mlx5e_close_locked(netdev);
3115                 mutex_unlock(&priv->state_lock);
3116         } else {
3117                 unregister_netdev(netdev);
3118         }
3119
3120         mlx5e_tc_cleanup(priv);
3121         mlx5e_vxlan_cleanup(priv);
3122         mlx5e_destroy_q_counter(priv);
3123         mlx5e_destroy_flow_steering(priv);
3124         mlx5e_destroy_tirs(priv);
3125         mlx5e_destroy_rqts(priv);
3126         mlx5e_close_drop_rq(priv);
3127         mlx5e_destroy_tises(priv);
3128         mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey);
3129         mlx5_core_destroy_mkey(priv->mdev, &priv->mkey);
3130         mlx5_core_dealloc_transport_domain(priv->mdev, priv->tdn);
3131         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
3132         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
3133         cancel_delayed_work_sync(&priv->update_stats_work);
3134         destroy_workqueue(priv->wq);
3135
3136         if (!test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state))
3137                 free_netdev(netdev);
3138 }
3139
3140 static void *mlx5e_get_netdev(void *vpriv)
3141 {
3142         struct mlx5e_priv *priv = vpriv;
3143
3144         return priv->netdev;
3145 }
3146
3147 static struct mlx5_interface mlx5e_interface = {
3148         .add       = mlx5e_create_netdev,
3149         .remove    = mlx5e_destroy_netdev,
3150         .event     = mlx5e_async_event,
3151         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
3152         .get_dev   = mlx5e_get_netdev,
3153 };
3154
3155 void mlx5e_init(void)
3156 {
3157         mlx5_register_interface(&mlx5e_interface);
3158 }
3159
3160 void mlx5e_cleanup(void)
3161 {
3162         mlx5_unregister_interface(&mlx5e_interface);
3163 }