drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <linux/bpf.h>
  38 #include "en.h"
  39 #include "en_tc.h"
  40 #include "eswitch.h"
  41 #include "vxlan.h"
  42
  43 struct mlx5e_rq_param {
  44         u32                     rqc[MLX5_ST_SZ_DW(rqc)];
  45         struct mlx5_wq_param    wq;
  46         bool                    am_enabled;
  47 };
  48
  49 struct mlx5e_sq_param {
  50         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  51         struct mlx5_wq_param       wq;
  52         u16                        max_inline;
  53         u8                         min_inline_mode;
  54         enum mlx5e_sq_type         type;
  55 };
  56
  57 struct mlx5e_cq_param {
  58         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  59         struct mlx5_wq_param       wq;
  60         u16                        eq_ix;
  61         u8                         cq_period_mode;
  62 };
  63
  64 struct mlx5e_channel_param {
  65         struct mlx5e_rq_param      rq;
  66         struct mlx5e_sq_param      sq;
  67         struct mlx5e_sq_param      xdp_sq;
  68         struct mlx5e_sq_param      icosq;
  69         struct mlx5e_cq_param      rx_cq;
  70         struct mlx5e_cq_param      tx_cq;
  71         struct mlx5e_cq_param      icosq_cq;
  72 };
  73
  74 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  75 {
  76         return MLX5_CAP_GEN(mdev, striding_rq) &&
  77                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  78                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  79 }
  80
  81 static void mlx5e_set_rq_type_params(struct mlx5e_priv *priv, u8 rq_type)
  82 {
  83         priv->params.rq_wq_type = rq_type;
  84         switch (priv->params.rq_wq_type) {
  85         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
  86                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
  87                 priv->params.mpwqe_log_stride_sz = priv->params.rx_cqe_compress ?
  88                         MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS :
  89                         MLX5_MPWRQ_LOG_STRIDE_SIZE;
  90                 priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
  91                         priv->params.mpwqe_log_stride_sz;
  92                 break;
  93         default: /* MLX5_WQ_TYPE_LINKED_LIST */
  94                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
  95         }
  96         priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
  97                                                BIT(priv->params.log_rq_size));
  98
  99         mlx5_core_info(priv->mdev,
 100                        "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
 101                        priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
 102                        BIT(priv->params.log_rq_size),
 103                        BIT(priv->params.mpwqe_log_stride_sz),
 104                        priv->params.rx_cqe_compress_admin);
 105 }
 106
 107 static void mlx5e_set_rq_priv_params(struct mlx5e_priv *priv)
 108 {
 109         u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(priv->mdev) &&
 110                     !priv->xdp_prog ?
 111                     MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
 112                     MLX5_WQ_TYPE_LINKED_LIST;
 113         mlx5e_set_rq_type_params(priv, rq_type);
 114 }
 115
 116 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
 117 {
 118         struct mlx5_core_dev *mdev = priv->mdev;
 119         u8 port_state;
 120
 121         port_state = mlx5_query_vport_state(mdev,
 122                 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
 123
 124         if (port_state == VPORT_STATE_UP) {
 125                 netdev_info(priv->netdev, "Link up\n");
 126                 netif_carrier_on(priv->netdev);
 127         } else {
 128                 netdev_info(priv->netdev, "Link down\n");
 129                 netif_carrier_off(priv->netdev);
 130         }
 131 }
 132
 133 static void mlx5e_update_carrier_work(struct work_struct *work)
 134 {
 135         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 136                                                update_carrier_work);
 137
 138         mutex_lock(&priv->state_lock);
 139         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 140                 mlx5e_update_carrier(priv);
 141         mutex_unlock(&priv->state_lock);
 142 }
 143
 144 static void mlx5e_tx_timeout_work(struct work_struct *work)
 145 {
 146         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 147                                                tx_timeout_work);
 148         int err;
 149
 150         rtnl_lock();
 151         mutex_lock(&priv->state_lock);
 152         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
 153                 goto unlock;
 154         mlx5e_close_locked(priv->netdev);
 155         err = mlx5e_open_locked(priv->netdev);
 156         if (err)
 157                 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
 158                            err);
 159 unlock:
 160         mutex_unlock(&priv->state_lock);
 161         rtnl_unlock();
 162 }
 163
 164 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
 165 {
 166         struct mlx5e_sw_stats *s = &priv->stats.sw;
 167         struct mlx5e_rq_stats *rq_stats;
 168         struct mlx5e_sq_stats *sq_stats;
 169         u64 tx_offload_none = 0;
 170         int i, j;
 171
 172         memset(s, 0, sizeof(*s));
 173         for (i = 0; i < priv->params.num_channels; i++) {
 174                 rq_stats = &priv->channel[i]->rq.stats;
 175
 176                 s->rx_packets   += rq_stats->packets;
 177                 s->rx_bytes     += rq_stats->bytes;
 178                 s->rx_lro_packets += rq_stats->lro_packets;
 179                 s->rx_lro_bytes += rq_stats->lro_bytes;
 180                 s->rx_csum_none += rq_stats->csum_none;
 181                 s->rx_csum_complete += rq_stats->csum_complete;
 182                 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
 183                 s->rx_xdp_drop += rq_stats->xdp_drop;
 184                 s->rx_xdp_tx += rq_stats->xdp_tx;
 185                 s->rx_xdp_tx_full += rq_stats->xdp_tx_full;
 186                 s->rx_wqe_err   += rq_stats->wqe_err;
 187                 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
 188                 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
 189                 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
 190                 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
 191                 s->rx_cache_reuse += rq_stats->cache_reuse;
 192                 s->rx_cache_full  += rq_stats->cache_full;
 193                 s->rx_cache_empty += rq_stats->cache_empty;
 194                 s->rx_cache_busy  += rq_stats->cache_busy;
 195
 196                 for (j = 0; j < priv->params.num_tc; j++) {
 197                         sq_stats = &priv->channel[i]->sq[j].stats;
 198
 199                         s->tx_packets           += sq_stats->packets;
 200                         s->tx_bytes             += sq_stats->bytes;
 201                         s->tx_tso_packets       += sq_stats->tso_packets;
 202                         s->tx_tso_bytes         += sq_stats->tso_bytes;
 203                         s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
 204                         s->tx_tso_inner_bytes   += sq_stats->tso_inner_bytes;
 205                         s->tx_queue_stopped     += sq_stats->stopped;
 206                         s->tx_queue_wake        += sq_stats->wake;
 207                         s->tx_queue_dropped     += sq_stats->dropped;
 208                         s->tx_xmit_more         += sq_stats->xmit_more;
 209                         s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
 210                         tx_offload_none         += sq_stats->csum_none;
 211                 }
 212         }
 213
 214         /* Update calculated offload counters */
 215         s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
 216         s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
 217
 218         s->link_down_events_phy = MLX5_GET(ppcnt_reg,
 219                                 priv->stats.pport.phy_counters,
 220                                 counter_set.phys_layer_cntrs.link_down_events);
 221 }
 222
 223 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
 224 {
 225         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 226         u32 *out = (u32 *)priv->stats.vport.query_vport_out;
 227         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
 228         struct mlx5_core_dev *mdev = priv->mdev;
 229
 230         MLX5_SET(query_vport_counter_in, in, opcode,
 231                  MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 232         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 233         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 234
 235         memset(out, 0, outlen);
 236         mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
 237 }
 238
 239 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 240 {
 241         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
 242         struct mlx5_core_dev *mdev = priv->mdev;
 243         int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 244         int prio;
 245         void *out;
 246         u32 *in;
 247
 248         in = mlx5_vzalloc(sz);
 249         if (!in)
 250                 goto free_out;
 251
 252         MLX5_SET(ppcnt_reg, in, local_port, 1);
 253
 254         out = pstats->IEEE_802_3_counters;
 255         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 256         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 257
 258         out = pstats->RFC_2863_counters;
 259         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 260         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 261
 262         out = pstats->RFC_2819_counters;
 263         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 264         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 265
 266         out = pstats->phy_counters;
 267         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 268         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 269
 270         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
 271         for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
 272                 out = pstats->per_prio_counters[prio];
 273                 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
 274                 mlx5_core_access_reg(mdev, in, sz, out, sz,
 275                                      MLX5_REG_PPCNT, 0, 0);
 276         }
 277
 278 free_out:
 279         kvfree(in);
 280 }
 281
 282 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
 283 {
 284         struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
 285
 286         if (!priv->q_counter)
 287                 return;
 288
 289         mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
 290                                       &qcnt->rx_out_of_buffer);
 291 }
 292
 293 void mlx5e_update_stats(struct mlx5e_priv *priv)
 294 {
 295         mlx5e_update_q_counter(priv);
 296         mlx5e_update_vport_counters(priv);
 297         mlx5e_update_pport_counters(priv);
 298         mlx5e_update_sw_counters(priv);
 299 }
 300
 301 void mlx5e_update_stats_work(struct work_struct *work)
 302 {
 303         struct delayed_work *dwork = to_delayed_work(work);
 304         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 305                                                update_stats_work);
 306         mutex_lock(&priv->state_lock);
 307         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 308                 priv->profile->update_stats(priv);
 309                 queue_delayed_work(priv->wq, dwork,
 310                                    msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
 311         }
 312         mutex_unlock(&priv->state_lock);
 313 }
 314
 315 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 316                               enum mlx5_dev_event event, unsigned long param)
 317 {
 318         struct mlx5e_priv *priv = vpriv;
 319
 320         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
 321                 return;
 322
 323         switch (event) {
 324         case MLX5_DEV_EVENT_PORT_UP:
 325         case MLX5_DEV_EVENT_PORT_DOWN:
 326                 queue_work(priv->wq, &priv->update_carrier_work);
 327                 break;
 328
 329         default:
 330                 break;
 331         }
 332 }
 333
 334 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 335 {
 336         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 337 }
 338
 339 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 340 {
 341         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 342         synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
 343 }
 344
 345 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 346 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 347
 348 static inline int mlx5e_get_wqe_mtt_sz(void)
 349 {
 350         /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
 351          * To avoid copying garbage after the mtt array, we allocate
 352          * a little more.
 353          */
 354         return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
 355                      MLX5_UMR_MTT_ALIGNMENT);
 356 }
 357
 358 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq, struct mlx5e_sq *sq,
 359                                        struct mlx5e_umr_wqe *wqe, u16 ix)
 360 {
 361         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 362         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 363         struct mlx5_wqe_data_seg      *dseg = &wqe->data;
 364         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 365         u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
 366         u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
 367
 368         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 369                                       ds_cnt);
 370         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
 371         cseg->imm       = rq->mkey_be;
 372
 373         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
 374         ucseg->klm_octowords =
 375                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 376         ucseg->bsf_octowords =
 377                 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
 378         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 379
 380         dseg->lkey = sq->mkey_be;
 381         dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
 382 }
 383
 384 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
 385                                      struct mlx5e_channel *c)
 386 {
 387         int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 388         int mtt_sz = mlx5e_get_wqe_mtt_sz();
 389         int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
 390         int i;
 391
 392         rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
 393                                       GFP_KERNEL, cpu_to_node(c->cpu));
 394         if (!rq->mpwqe.info)
 395                 goto err_out;
 396
 397         /* We allocate more than mtt_sz as we will align the pointer */
 398         rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL,
 399                                         cpu_to_node(c->cpu));
 400         if (unlikely(!rq->mpwqe.mtt_no_align))
 401                 goto err_free_wqe_info;
 402
 403         for (i = 0; i < wq_sz; i++) {
 404                 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
 405
 406                 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
 407                                         MLX5_UMR_ALIGN);
 408                 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
 409                                                   PCI_DMA_TODEVICE);
 410                 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
 411                         goto err_unmap_mtts;
 412
 413                 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
 414         }
 415
 416         return 0;
 417
 418 err_unmap_mtts:
 419         while (--i >= 0) {
 420                 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
 421
 422                 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
 423                                  PCI_DMA_TODEVICE);
 424         }
 425         kfree(rq->mpwqe.mtt_no_align);
 426 err_free_wqe_info:
 427         kfree(rq->mpwqe.info);
 428
 429 err_out:
 430         return -ENOMEM;
 431 }
 432
 433 static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
 434 {
 435         int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 436         int mtt_sz = mlx5e_get_wqe_mtt_sz();
 437         int i;
 438
 439         for (i = 0; i < wq_sz; i++) {
 440                 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
 441
 442                 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
 443                                  PCI_DMA_TODEVICE);
 444         }
 445         kfree(rq->mpwqe.mtt_no_align);
 446         kfree(rq->mpwqe.info);
 447 }
 448
 449 static bool mlx5e_is_vf_vport_rep(struct mlx5e_priv *priv)
 450 {
 451         struct mlx5_eswitch_rep *rep = (struct mlx5_eswitch_rep *)priv->ppriv;
 452
 453         if (rep && rep->vport != FDB_UPLINK_VPORT)
 454                 return true;
 455
 456         return false;
 457 }
 458
 459 static int mlx5e_create_rq(struct mlx5e_channel *c,
 460                            struct mlx5e_rq_param *param,
 461                            struct mlx5e_rq *rq)
 462 {
 463         struct mlx5e_priv *priv = c->priv;
 464         struct mlx5_core_dev *mdev = priv->mdev;
 465         void *rqc = param->rqc;
 466         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 467         u32 byte_count;
 468         u32 frag_sz;
 469         int npages;
 470         int wq_sz;
 471         int err;
 472         int i;
 473
 474         param->wq.db_numa_node = cpu_to_node(c->cpu);
 475
 476         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 477                                 &rq->wq_ctrl);
 478         if (err)
 479                 return err;
 480
 481         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 482
 483         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 484
 485         rq->wq_type = priv->params.rq_wq_type;
 486         rq->pdev    = c->pdev;
 487         rq->netdev  = c->netdev;
 488         rq->tstamp  = &priv->tstamp;
 489         rq->channel = c;
 490         rq->ix      = c->ix;
 491         rq->priv    = c->priv;
 492         rq->xdp_prog = priv->xdp_prog;
 493
 494         rq->buff.map_dir = DMA_FROM_DEVICE;
 495         if (rq->xdp_prog)
 496                 rq->buff.map_dir = DMA_BIDIRECTIONAL;
 497
 498         switch (priv->params.rq_wq_type) {
 499         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 500                 if (mlx5e_is_vf_vport_rep(priv)) {
 501                         err = -EINVAL;
 502                         goto err_rq_wq_destroy;
 503                 }
 504
 505                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
 506                 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
 507                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 508
 509                 rq->mpwqe.mtt_offset = c->ix *
 510                         MLX5E_REQUIRED_MTTS(1, BIT(priv->params.log_rq_size));
 511
 512                 rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz);
 513                 rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides);
 514
 515                 rq->buff.wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
 516                 byte_count = rq->buff.wqe_sz;
 517                 rq->mkey_be = cpu_to_be32(c->priv->umr_mkey.key);
 518                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
 519                 if (err)
 520                         goto err_rq_wq_destroy;
 521                 break;
 522         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 523                 rq->dma_info = kzalloc_node(wq_sz * sizeof(*rq->dma_info),
 524                                             GFP_KERNEL, cpu_to_node(c->cpu));
 525                 if (!rq->dma_info) {
 526                         err = -ENOMEM;
 527                         goto err_rq_wq_destroy;
 528                 }
 529
 530                 if (mlx5e_is_vf_vport_rep(priv))
 531                         rq->handle_rx_cqe = mlx5e_handle_rx_cqe_rep;
 532                 else
 533                         rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
 534
 535                 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
 536                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 537
 538                 rq->buff.wqe_sz = (priv->params.lro_en) ?
 539                                 priv->params.lro_wqe_sz :
 540                                 MLX5E_SW2HW_MTU(priv->netdev->mtu);
 541                 byte_count = rq->buff.wqe_sz;
 542
 543                 /* calc the required page order */
 544                 frag_sz = MLX5_RX_HEADROOM +
 545                           byte_count /* packet data */ +
 546                           SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
 547                 frag_sz = SKB_DATA_ALIGN(frag_sz);
 548
 549                 npages = DIV_ROUND_UP(frag_sz, PAGE_SIZE);
 550                 rq->buff.page_order = order_base_2(npages);
 551
 552                 byte_count |= MLX5_HW_START_PADDING;
 553                 rq->mkey_be = c->mkey_be;
 554         }
 555
 556         for (i = 0; i < wq_sz; i++) {
 557                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 558
 559                 wqe->data.byte_count = cpu_to_be32(byte_count);
 560                 wqe->data.lkey = rq->mkey_be;
 561         }
 562
 563         INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
 564         rq->am.mode = priv->params.rx_cq_period_mode;
 565
 566         rq->page_cache.head = 0;
 567         rq->page_cache.tail = 0;
 568
 569         if (rq->xdp_prog)
 570                 bpf_prog_add(rq->xdp_prog, 1);
 571
 572         return 0;
 573
 574 err_rq_wq_destroy:
 575         mlx5_wq_destroy(&rq->wq_ctrl);
 576
 577         return err;
 578 }
 579
 580 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 581 {
 582         int i;
 583
 584         if (rq->xdp_prog)
 585                 bpf_prog_put(rq->xdp_prog);
 586
 587         switch (rq->wq_type) {
 588         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 589                 mlx5e_rq_free_mpwqe_info(rq);
 590                 break;
 591         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 592                 kfree(rq->dma_info);
 593         }
 594
 595         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 596              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 597                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 598
 599                 mlx5e_page_release(rq, dma_info, false);
 600         }
 601         mlx5_wq_destroy(&rq->wq_ctrl);
 602 }
 603
 604 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 605 {
 606         struct mlx5e_priv *priv = rq->priv;
 607         struct mlx5_core_dev *mdev = priv->mdev;
 608
 609         void *in;
 610         void *rqc;
 611         void *wq;
 612         int inlen;
 613         int err;
 614
 615         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 616                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 617         in = mlx5_vzalloc(inlen);
 618         if (!in)
 619                 return -ENOMEM;
 620
 621         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 622         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 623
 624         memcpy(rqc, param->rqc, sizeof(param->rqc));
 625
 626         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 627         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 628         MLX5_SET(rqc,  rqc, vsd, priv->params.vlan_strip_disable);
 629         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 630                                                 MLX5_ADAPTER_PAGE_SHIFT);
 631         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 632
 633         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 634                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 635
 636         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 637
 638         kvfree(in);
 639
 640         return err;
 641 }
 642
 643 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
 644                                  int next_state)
 645 {
 646         struct mlx5e_channel *c = rq->channel;
 647         struct mlx5e_priv *priv = c->priv;
 648         struct mlx5_core_dev *mdev = priv->mdev;
 649
 650         void *in;
 651         void *rqc;
 652         int inlen;
 653         int err;
 654
 655         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 656         in = mlx5_vzalloc(inlen);
 657         if (!in)
 658                 return -ENOMEM;
 659
 660         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 661
 662         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 663         MLX5_SET(rqc, rqc, state, next_state);
 664
 665         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 666
 667         kvfree(in);
 668
 669         return err;
 670 }
 671
 672 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 673 {
 674         struct mlx5e_channel *c = rq->channel;
 675         struct mlx5e_priv *priv = c->priv;
 676         struct mlx5_core_dev *mdev = priv->mdev;
 677
 678         void *in;
 679         void *rqc;
 680         int inlen;
 681         int err;
 682
 683         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 684         in = mlx5_vzalloc(inlen);
 685         if (!in)
 686                 return -ENOMEM;
 687
 688         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 689
 690         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 691         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 692                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 693         MLX5_SET(rqc, rqc, vsd, vsd);
 694         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 695
 696         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 697
 698         kvfree(in);
 699
 700         return err;
 701 }
 702
 703 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
 704 {
 705         mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
 706 }
 707
 708 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 709 {
 710         unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
 711         struct mlx5e_channel *c = rq->channel;
 712         struct mlx5e_priv *priv = c->priv;
 713         struct mlx5_wq_ll *wq = &rq->wq;
 714
 715         while (time_before(jiffies, exp_time)) {
 716                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 717                         return 0;
 718
 719                 msleep(20);
 720         }
 721
 722         return -ETIMEDOUT;
 723 }
 724
 725 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 726 {
 727         struct mlx5_wq_ll *wq = &rq->wq;
 728         struct mlx5e_rx_wqe *wqe;
 729         __be16 wqe_ix_be;
 730         u16 wqe_ix;
 731
 732         /* UMR WQE (if in progress) is always at wq->head */
 733         if (test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
 734                 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
 735
 736         while (!mlx5_wq_ll_is_empty(wq)) {
 737                 wqe_ix_be = *wq->tail_next;
 738                 wqe_ix    = be16_to_cpu(wqe_ix_be);
 739                 wqe       = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
 740                 rq->dealloc_wqe(rq, wqe_ix);
 741                 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
 742                                &wqe->next.next_wqe_index);
 743         }
 744 }
 745
 746 static int mlx5e_open_rq(struct mlx5e_channel *c,
 747                          struct mlx5e_rq_param *param,
 748                          struct mlx5e_rq *rq)
 749 {
 750         struct mlx5e_sq *sq = &c->icosq;
 751         u16 pi = sq->pc & sq->wq.sz_m1;
 752         int err;
 753
 754         err = mlx5e_create_rq(c, param, rq);
 755         if (err)
 756                 return err;
 757
 758         err = mlx5e_enable_rq(rq, param);
 759         if (err)
 760                 goto err_destroy_rq;
 761
 762         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 763         if (err)
 764                 goto err_disable_rq;
 765
 766         if (param->am_enabled)
 767                 set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
 768
 769         sq->db.ico_wqe[pi].opcode     = MLX5_OPCODE_NOP;
 770         sq->db.ico_wqe[pi].num_wqebbs = 1;
 771         mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
 772
 773         return 0;
 774
 775 err_disable_rq:
 776         mlx5e_disable_rq(rq);
 777 err_destroy_rq:
 778         mlx5e_destroy_rq(rq);
 779
 780         return err;
 781 }
 782
 783 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 784 {
 785         set_bit(MLX5E_RQ_STATE_FLUSH, &rq->state);
 786         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 787         cancel_work_sync(&rq->am.work);
 788
 789         mlx5e_disable_rq(rq);
 790         mlx5e_free_rx_descs(rq);
 791         mlx5e_destroy_rq(rq);
 792 }
 793
 794 static void mlx5e_free_sq_xdp_db(struct mlx5e_sq *sq)
 795 {
 796         kfree(sq->db.xdp.di);
 797         kfree(sq->db.xdp.wqe_info);
 798 }
 799
 800 static int mlx5e_alloc_sq_xdp_db(struct mlx5e_sq *sq, int numa)
 801 {
 802         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 803
 804         sq->db.xdp.di = kzalloc_node(sizeof(*sq->db.xdp.di) * wq_sz,
 805                                      GFP_KERNEL, numa);
 806         sq->db.xdp.wqe_info = kzalloc_node(sizeof(*sq->db.xdp.wqe_info) * wq_sz,
 807                                            GFP_KERNEL, numa);
 808         if (!sq->db.xdp.di || !sq->db.xdp.wqe_info) {
 809                 mlx5e_free_sq_xdp_db(sq);
 810                 return -ENOMEM;
 811         }
 812
 813         return 0;
 814 }
 815
 816 static void mlx5e_free_sq_ico_db(struct mlx5e_sq *sq)
 817 {
 818         kfree(sq->db.ico_wqe);
 819 }
 820
 821 static int mlx5e_alloc_sq_ico_db(struct mlx5e_sq *sq, int numa)
 822 {
 823         u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 824
 825         sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
 826                                       GFP_KERNEL, numa);
 827         if (!sq->db.ico_wqe)
 828                 return -ENOMEM;
 829
 830         return 0;
 831 }
 832
 833 static void mlx5e_free_sq_txq_db(struct mlx5e_sq *sq)
 834 {
 835         kfree(sq->db.txq.wqe_info);
 836         kfree(sq->db.txq.dma_fifo);
 837         kfree(sq->db.txq.skb);
 838 }
 839
 840 static int mlx5e_alloc_sq_txq_db(struct mlx5e_sq *sq, int numa)
 841 {
 842         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 843         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 844
 845         sq->db.txq.skb = kzalloc_node(wq_sz * sizeof(*sq->db.txq.skb),
 846                                       GFP_KERNEL, numa);
 847         sq->db.txq.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.txq.dma_fifo),
 848                                            GFP_KERNEL, numa);
 849         sq->db.txq.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.txq.wqe_info),
 850                                            GFP_KERNEL, numa);
 851         if (!sq->db.txq.skb || !sq->db.txq.dma_fifo || !sq->db.txq.wqe_info) {
 852                 mlx5e_free_sq_txq_db(sq);
 853                 return -ENOMEM;
 854         }
 855
 856         sq->dma_fifo_mask = df_sz - 1;
 857
 858         return 0;
 859 }
 860
 861 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
 862 {
 863         switch (sq->type) {
 864         case MLX5E_SQ_TXQ:
 865                 mlx5e_free_sq_txq_db(sq);
 866                 break;
 867         case MLX5E_SQ_ICO:
 868                 mlx5e_free_sq_ico_db(sq);
 869                 break;
 870         case MLX5E_SQ_XDP:
 871                 mlx5e_free_sq_xdp_db(sq);
 872                 break;
 873         }
 874 }
 875
 876 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
 877 {
 878         switch (sq->type) {
 879         case MLX5E_SQ_TXQ:
 880                 return mlx5e_alloc_sq_txq_db(sq, numa);
 881         case MLX5E_SQ_ICO:
 882                 return mlx5e_alloc_sq_ico_db(sq, numa);
 883         case MLX5E_SQ_XDP:
 884                 return mlx5e_alloc_sq_xdp_db(sq, numa);
 885         }
 886
 887         return 0;
 888 }
 889
 890 static int mlx5e_sq_get_max_wqebbs(u8 sq_type)
 891 {
 892         switch (sq_type) {
 893         case MLX5E_SQ_ICO:
 894                 return MLX5E_ICOSQ_MAX_WQEBBS;
 895         case MLX5E_SQ_XDP:
 896                 return MLX5E_XDP_TX_WQEBBS;
 897         }
 898         return MLX5_SEND_WQE_MAX_WQEBBS;
 899 }
 900
 901 static int mlx5e_create_sq(struct mlx5e_channel *c,
 902                            int tc,
 903                            struct mlx5e_sq_param *param,
 904                            struct mlx5e_sq *sq)
 905 {
 906         struct mlx5e_priv *priv = c->priv;
 907         struct mlx5_core_dev *mdev = priv->mdev;
 908
 909         void *sqc = param->sqc;
 910         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
 911         int err;
 912
 913         sq->type      = param->type;
 914         sq->pdev      = c->pdev;
 915         sq->tstamp    = &priv->tstamp;
 916         sq->mkey_be   = c->mkey_be;
 917         sq->channel   = c;
 918         sq->tc        = tc;
 919
 920         err = mlx5_alloc_map_uar(mdev, &sq->uar, !!MLX5_CAP_GEN(mdev, bf));
 921         if (err)
 922                 return err;
 923
 924         param->wq.db_numa_node = cpu_to_node(c->cpu);
 925
 926         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
 927                                  &sq->wq_ctrl);
 928         if (err)
 929                 goto err_unmap_free_uar;
 930
 931         sq->wq.db       = &sq->wq.db[MLX5_SND_DBR];
 932         if (sq->uar.bf_map) {
 933                 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
 934                 sq->uar_map = sq->uar.bf_map;
 935         } else {
 936                 sq->uar_map = sq->uar.map;
 937         }
 938         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
 939         sq->max_inline  = param->max_inline;
 940         sq->min_inline_mode =
 941                 MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5E_INLINE_MODE_VPORT_CONTEXT ?
 942                 param->min_inline_mode : 0;
 943
 944         err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
 945         if (err)
 946                 goto err_sq_wq_destroy;
 947
 948         if (sq->type == MLX5E_SQ_TXQ) {
 949                 int txq_ix;
 950
 951                 txq_ix = c->ix + tc * priv->params.num_channels;
 952                 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
 953                 priv->txq_to_sq_map[txq_ix] = sq;
 954         }
 955
 956         sq->edge = (sq->wq.sz_m1 + 1) - mlx5e_sq_get_max_wqebbs(sq->type);
 957         sq->bf_budget = MLX5E_SQ_BF_BUDGET;
 958
 959         return 0;
 960
 961 err_sq_wq_destroy:
 962         mlx5_wq_destroy(&sq->wq_ctrl);
 963
 964 err_unmap_free_uar:
 965         mlx5_unmap_free_uar(mdev, &sq->uar);
 966
 967         return err;
 968 }
 969
 970 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
 971 {
 972         struct mlx5e_channel *c = sq->channel;
 973         struct mlx5e_priv *priv = c->priv;
 974
 975         mlx5e_free_sq_db(sq);
 976         mlx5_wq_destroy(&sq->wq_ctrl);
 977         mlx5_unmap_free_uar(priv->mdev, &sq->uar);
 978 }
 979
 980 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
 981 {
 982         struct mlx5e_channel *c = sq->channel;
 983         struct mlx5e_priv *priv = c->priv;
 984         struct mlx5_core_dev *mdev = priv->mdev;
 985
 986         void *in;
 987         void *sqc;
 988         void *wq;
 989         int inlen;
 990         int err;
 991
 992         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
 993                 sizeof(u64) * sq->wq_ctrl.buf.npages;
 994         in = mlx5_vzalloc(inlen);
 995         if (!in)
 996                 return -ENOMEM;
 997
 998         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
 999         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1000
1001         memcpy(sqc, param->sqc, sizeof(param->sqc));
1002
1003         MLX5_SET(sqc,  sqc, tis_num_0, param->type == MLX5E_SQ_ICO ?
1004                                        0 : priv->tisn[sq->tc]);
1005         MLX5_SET(sqc,  sqc, cqn,                sq->cq.mcq.cqn);
1006         MLX5_SET(sqc,  sqc, min_wqe_inline_mode, sq->min_inline_mode);
1007         MLX5_SET(sqc,  sqc, state,              MLX5_SQC_STATE_RST);
1008         MLX5_SET(sqc,  sqc, tis_lst_sz, param->type == MLX5E_SQ_ICO ? 0 : 1);
1009         MLX5_SET(sqc,  sqc, flush_in_error_en,  1);
1010
1011         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1012         MLX5_SET(wq,   wq, uar_page,      sq->uar.index);
1013         MLX5_SET(wq,   wq, log_wq_pg_sz,  sq->wq_ctrl.buf.page_shift -
1014                                           MLX5_ADAPTER_PAGE_SHIFT);
1015         MLX5_SET64(wq, wq, dbr_addr,      sq->wq_ctrl.db.dma);
1016
1017         mlx5_fill_page_array(&sq->wq_ctrl.buf,
1018                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1019
1020         err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
1021
1022         kvfree(in);
1023
1024         return err;
1025 }
1026
1027 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state,
1028                            int next_state, bool update_rl, int rl_index)
1029 {
1030         struct mlx5e_channel *c = sq->channel;
1031         struct mlx5e_priv *priv = c->priv;
1032         struct mlx5_core_dev *mdev = priv->mdev;
1033
1034         void *in;
1035         void *sqc;
1036         int inlen;
1037         int err;
1038
1039         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1040         in = mlx5_vzalloc(inlen);
1041         if (!in)
1042                 return -ENOMEM;
1043
1044         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1045
1046         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1047         MLX5_SET(sqc, sqc, state, next_state);
1048         if (update_rl && next_state == MLX5_SQC_STATE_RDY) {
1049                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1050                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, rl_index);
1051         }
1052
1053         err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
1054
1055         kvfree(in);
1056
1057         return err;
1058 }
1059
1060 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
1061 {
1062         struct mlx5e_channel *c = sq->channel;
1063         struct mlx5e_priv *priv = c->priv;
1064         struct mlx5_core_dev *mdev = priv->mdev;
1065
1066         mlx5_core_destroy_sq(mdev, sq->sqn);
1067         if (sq->rate_limit)
1068                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1069 }
1070
1071 static int mlx5e_open_sq(struct mlx5e_channel *c,
1072                          int tc,
1073                          struct mlx5e_sq_param *param,
1074                          struct mlx5e_sq *sq)
1075 {
1076         int err;
1077
1078         err = mlx5e_create_sq(c, tc, param, sq);
1079         if (err)
1080                 return err;
1081
1082         err = mlx5e_enable_sq(sq, param);
1083         if (err)
1084                 goto err_destroy_sq;
1085
1086         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY,
1087                               false, 0);
1088         if (err)
1089                 goto err_disable_sq;
1090
1091         if (sq->txq) {
1092                 netdev_tx_reset_queue(sq->txq);
1093                 netif_tx_start_queue(sq->txq);
1094         }
1095
1096         return 0;
1097
1098 err_disable_sq:
1099         mlx5e_disable_sq(sq);
1100 err_destroy_sq:
1101         mlx5e_destroy_sq(sq);
1102
1103         return err;
1104 }
1105
1106 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1107 {
1108         __netif_tx_lock_bh(txq);
1109         netif_tx_stop_queue(txq);
1110         __netif_tx_unlock_bh(txq);
1111 }
1112
1113 static void mlx5e_close_sq(struct mlx5e_sq *sq)
1114 {
1115         set_bit(MLX5E_SQ_STATE_FLUSH, &sq->state);
1116         /* prevent netif_tx_wake_queue */
1117         napi_synchronize(&sq->channel->napi);
1118
1119         if (sq->txq) {
1120                 netif_tx_disable_queue(sq->txq);
1121
1122                 /* last doorbell out, godspeed .. */
1123                 if (mlx5e_sq_has_room_for(sq, 1)) {
1124                         sq->db.txq.skb[(sq->pc & sq->wq.sz_m1)] = NULL;
1125                         mlx5e_send_nop(sq, true);
1126                 }
1127         }
1128
1129         mlx5e_disable_sq(sq);
1130         mlx5e_free_sq_descs(sq);
1131         mlx5e_destroy_sq(sq);
1132 }
1133
1134 static int mlx5e_create_cq(struct mlx5e_channel *c,
1135                            struct mlx5e_cq_param *param,
1136                            struct mlx5e_cq *cq)
1137 {
1138         struct mlx5e_priv *priv = c->priv;
1139         struct mlx5_core_dev *mdev = priv->mdev;
1140         struct mlx5_core_cq *mcq = &cq->mcq;
1141         int eqn_not_used;
1142         unsigned int irqn;
1143         int err;
1144         u32 i;
1145
1146         param->wq.buf_numa_node = cpu_to_node(c->cpu);
1147         param->wq.db_numa_node  = cpu_to_node(c->cpu);
1148         param->eq_ix   = c->ix;
1149
1150         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1151                                &cq->wq_ctrl);
1152         if (err)
1153                 return err;
1154
1155         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1156
1157         cq->napi        = &c->napi;
1158
1159         mcq->cqe_sz     = 64;
1160         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1161         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1162         *mcq->set_ci_db = 0;
1163         *mcq->arm_db    = 0;
1164         mcq->vector     = param->eq_ix;
1165         mcq->comp       = mlx5e_completion_event;
1166         mcq->event      = mlx5e_cq_error_event;
1167         mcq->irqn       = irqn;
1168         mcq->uar        = &mdev->mlx5e_res.cq_uar;
1169
1170         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1171                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1172
1173                 cqe->op_own = 0xf1;
1174         }
1175
1176         cq->channel = c;
1177         cq->priv = priv;
1178
1179         return 0;
1180 }
1181
1182 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1183 {
1184         mlx5_wq_destroy(&cq->wq_ctrl);
1185 }
1186
1187 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1188 {
1189         struct mlx5e_priv *priv = cq->priv;
1190         struct mlx5_core_dev *mdev = priv->mdev;
1191         struct mlx5_core_cq *mcq = &cq->mcq;
1192
1193         void *in;
1194         void *cqc;
1195         int inlen;
1196         unsigned int irqn_not_used;
1197         int eqn;
1198         int err;
1199
1200         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1201                 sizeof(u64) * cq->wq_ctrl.buf.npages;
1202         in = mlx5_vzalloc(inlen);
1203         if (!in)
1204                 return -ENOMEM;
1205
1206         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1207
1208         memcpy(cqc, param->cqc, sizeof(param->cqc));
1209
1210         mlx5_fill_page_array(&cq->wq_ctrl.buf,
1211                              (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1212
1213         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1214
1215         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1216         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1217         MLX5_SET(cqc,   cqc, uar_page,      mcq->uar->index);
1218         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1219                                             MLX5_ADAPTER_PAGE_SHIFT);
1220         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1221
1222         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1223
1224         kvfree(in);
1225
1226         if (err)
1227                 return err;
1228
1229         mlx5e_cq_arm(cq);
1230
1231         return 0;
1232 }
1233
1234 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
1235 {
1236         struct mlx5e_priv *priv = cq->priv;
1237         struct mlx5_core_dev *mdev = priv->mdev;
1238
1239         mlx5_core_destroy_cq(mdev, &cq->mcq);
1240 }
1241
1242 static int mlx5e_open_cq(struct mlx5e_channel *c,
1243                          struct mlx5e_cq_param *param,
1244                          struct mlx5e_cq *cq,
1245                          struct mlx5e_cq_moder moderation)
1246 {
1247         int err;
1248         struct mlx5e_priv *priv = c->priv;
1249         struct mlx5_core_dev *mdev = priv->mdev;
1250
1251         err = mlx5e_create_cq(c, param, cq);
1252         if (err)
1253                 return err;
1254
1255         err = mlx5e_enable_cq(cq, param);
1256         if (err)
1257                 goto err_destroy_cq;
1258
1259         if (MLX5_CAP_GEN(mdev, cq_moderation))
1260                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
1261                                                moderation.usec,
1262                                                moderation.pkts);
1263         return 0;
1264
1265 err_destroy_cq:
1266         mlx5e_destroy_cq(cq);
1267
1268         return err;
1269 }
1270
1271 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1272 {
1273         mlx5e_disable_cq(cq);
1274         mlx5e_destroy_cq(cq);
1275 }
1276
1277 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1278 {
1279         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1280 }
1281
1282 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1283                              struct mlx5e_channel_param *cparam)
1284 {
1285         struct mlx5e_priv *priv = c->priv;
1286         int err;
1287         int tc;
1288
1289         for (tc = 0; tc < c->num_tc; tc++) {
1290                 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
1291                                     priv->params.tx_cq_moderation);
1292                 if (err)
1293                         goto err_close_tx_cqs;
1294         }
1295
1296         return 0;
1297
1298 err_close_tx_cqs:
1299         for (tc--; tc >= 0; tc--)
1300                 mlx5e_close_cq(&c->sq[tc].cq);
1301
1302         return err;
1303 }
1304
1305 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1306 {
1307         int tc;
1308
1309         for (tc = 0; tc < c->num_tc; tc++)
1310                 mlx5e_close_cq(&c->sq[tc].cq);
1311 }
1312
1313 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1314                           struct mlx5e_channel_param *cparam)
1315 {
1316         int err;
1317         int tc;
1318
1319         for (tc = 0; tc < c->num_tc; tc++) {
1320                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1321                 if (err)
1322                         goto err_close_sqs;
1323         }
1324
1325         return 0;
1326
1327 err_close_sqs:
1328         for (tc--; tc >= 0; tc--)
1329                 mlx5e_close_sq(&c->sq[tc]);
1330
1331         return err;
1332 }
1333
1334 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1335 {
1336         int tc;
1337
1338         for (tc = 0; tc < c->num_tc; tc++)
1339                 mlx5e_close_sq(&c->sq[tc]);
1340 }
1341
1342 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
1343 {
1344         int i;
1345
1346         for (i = 0; i < priv->profile->max_tc; i++)
1347                 priv->channeltc_to_txq_map[ix][i] =
1348                         ix + i * priv->params.num_channels;
1349 }
1350
1351 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1352                                 struct mlx5e_sq *sq, u32 rate)
1353 {
1354         struct mlx5e_priv *priv = netdev_priv(dev);
1355         struct mlx5_core_dev *mdev = priv->mdev;
1356         u16 rl_index = 0;
1357         int err;
1358
1359         if (rate == sq->rate_limit)
1360                 /* nothing to do */
1361                 return 0;
1362
1363         if (sq->rate_limit)
1364                 /* remove current rl index to free space to next ones */
1365                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1366
1367         sq->rate_limit = 0;
1368
1369         if (rate) {
1370                 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1371                 if (err) {
1372                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1373                                    rate, err);
1374                         return err;
1375                 }
1376         }
1377
1378         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
1379                               MLX5_SQC_STATE_RDY, true, rl_index);
1380         if (err) {
1381                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1382                            rate, err);
1383                 /* remove the rate from the table */
1384                 if (rate)
1385                         mlx5_rl_remove_rate(mdev, rate);
1386                 return err;
1387         }
1388
1389         sq->rate_limit = rate;
1390         return 0;
1391 }
1392
1393 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1394 {
1395         struct mlx5e_priv *priv = netdev_priv(dev);
1396         struct mlx5_core_dev *mdev = priv->mdev;
1397         struct mlx5e_sq *sq = priv->txq_to_sq_map[index];
1398         int err = 0;
1399
1400         if (!mlx5_rl_is_supported(mdev)) {
1401                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1402                 return -EINVAL;
1403         }
1404
1405         /* rate is given in Mb/sec, HW config is in Kb/sec */
1406         rate = rate << 10;
1407
1408         /* Check whether rate in valid range, 0 is always valid */
1409         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1410                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1411                 return -ERANGE;
1412         }
1413
1414         mutex_lock(&priv->state_lock);
1415         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1416                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1417         if (!err)
1418                 priv->tx_rates[index] = rate;
1419         mutex_unlock(&priv->state_lock);
1420
1421         return err;
1422 }
1423
1424 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1425                               struct mlx5e_channel_param *cparam,
1426                               struct mlx5e_channel **cp)
1427 {
1428         struct mlx5e_cq_moder icosq_cq_moder = {0, 0};
1429         struct net_device *netdev = priv->netdev;
1430         struct mlx5e_cq_moder rx_cq_profile;
1431         int cpu = mlx5e_get_cpu(priv, ix);
1432         struct mlx5e_channel *c;
1433         struct mlx5e_sq *sq;
1434         int err;
1435         int i;
1436
1437         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1438         if (!c)
1439                 return -ENOMEM;
1440
1441         c->priv     = priv;
1442         c->ix       = ix;
1443         c->cpu      = cpu;
1444         c->pdev     = &priv->mdev->pdev->dev;
1445         c->netdev   = priv->netdev;
1446         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1447         c->num_tc   = priv->params.num_tc;
1448
1449         if (priv->params.rx_am_enabled)
1450                 rx_cq_profile = mlx5e_am_get_def_profile(priv->params.rx_cq_period_mode);
1451         else
1452                 rx_cq_profile = priv->params.rx_cq_moderation;
1453
1454         mlx5e_build_channeltc_to_txq_map(priv, ix);
1455
1456         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1457
1458         err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, icosq_cq_moder);
1459         if (err)
1460                 goto err_napi_del;
1461
1462         err = mlx5e_open_tx_cqs(c, cparam);
1463         if (err)
1464                 goto err_close_icosq_cq;
1465
1466         err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1467                             rx_cq_profile);
1468         if (err)
1469                 goto err_close_tx_cqs;
1470
1471         napi_enable(&c->napi);
1472
1473         err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
1474         if (err)
1475                 goto err_disable_napi;
1476
1477         err = mlx5e_open_sqs(c, cparam);
1478         if (err)
1479                 goto err_close_icosq;
1480
1481         for (i = 0; i < priv->params.num_tc; i++) {
1482                 u32 txq_ix = priv->channeltc_to_txq_map[ix][i];
1483
1484                 if (priv->tx_rates[txq_ix]) {
1485                         sq = priv->txq_to_sq_map[txq_ix];
1486                         mlx5e_set_sq_maxrate(priv->netdev, sq,
1487                                              priv->tx_rates[txq_ix]);
1488                 }
1489         }
1490
1491         if (priv->xdp_prog) {
1492                 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1493                 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->xdp_sq.cq,
1494                                     priv->params.tx_cq_moderation);
1495                 if (err)
1496                         goto err_close_sqs;
1497
1498                 err = mlx5e_open_sq(c, 0, &cparam->xdp_sq, &c->xdp_sq);
1499                 if (err) {
1500                         mlx5e_close_cq(&c->xdp_sq.cq);
1501                         goto err_close_sqs;
1502                 }
1503         }
1504
1505         c->xdp = !!priv->xdp_prog;
1506         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1507         if (err)
1508                 goto err_close_xdp_sq;
1509
1510         netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1511         *cp = c;
1512
1513         return 0;
1514 err_close_xdp_sq:
1515         mlx5e_close_sq(&c->xdp_sq);
1516
1517 err_close_sqs:
1518         mlx5e_close_sqs(c);
1519
1520 err_close_icosq:
1521         mlx5e_close_sq(&c->icosq);
1522
1523 err_disable_napi:
1524         napi_disable(&c->napi);
1525         mlx5e_close_cq(&c->rq.cq);
1526
1527 err_close_tx_cqs:
1528         mlx5e_close_tx_cqs(c);
1529
1530 err_close_icosq_cq:
1531         mlx5e_close_cq(&c->icosq.cq);
1532
1533 err_napi_del:
1534         netif_napi_del(&c->napi);
1535         napi_hash_del(&c->napi);
1536         kfree(c);
1537
1538         return err;
1539 }
1540
1541 static void mlx5e_close_channel(struct mlx5e_channel *c)
1542 {
1543         mlx5e_close_rq(&c->rq);
1544         if (c->xdp)
1545                 mlx5e_close_sq(&c->xdp_sq);
1546         mlx5e_close_sqs(c);
1547         mlx5e_close_sq(&c->icosq);
1548         napi_disable(&c->napi);
1549         if (c->xdp)
1550                 mlx5e_close_cq(&c->xdp_sq.cq);
1551         mlx5e_close_cq(&c->rq.cq);
1552         mlx5e_close_tx_cqs(c);
1553         mlx5e_close_cq(&c->icosq.cq);
1554         netif_napi_del(&c->napi);
1555
1556         napi_hash_del(&c->napi);
1557         synchronize_rcu();
1558
1559         kfree(c);
1560 }
1561
1562 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1563                                  struct mlx5e_rq_param *param)
1564 {
1565         void *rqc = param->rqc;
1566         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1567
1568         switch (priv->params.rq_wq_type) {
1569         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1570                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1571                          priv->params.mpwqe_log_num_strides - 9);
1572                 MLX5_SET(wq, wq, log_wqe_stride_size,
1573                          priv->params.mpwqe_log_stride_sz - 6);
1574                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1575                 break;
1576         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1577                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1578         }
1579
1580         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1581         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1582         MLX5_SET(wq, wq, log_wq_sz,        priv->params.log_rq_size);
1583         MLX5_SET(wq, wq, pd,               priv->mdev->mlx5e_res.pdn);
1584         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1585
1586         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1587         param->wq.linear = 1;
1588
1589         param->am_enabled = priv->params.rx_am_enabled;
1590 }
1591
1592 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1593 {
1594         void *rqc = param->rqc;
1595         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1596
1597         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1598         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1599 }
1600
1601 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1602                                         struct mlx5e_sq_param *param)
1603 {
1604         void *sqc = param->sqc;
1605         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1606
1607         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1608         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
1609
1610         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1611 }
1612
1613 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1614                                  struct mlx5e_sq_param *param)
1615 {
1616         void *sqc = param->sqc;
1617         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1618
1619         mlx5e_build_sq_param_common(priv, param);
1620         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1621
1622         param->max_inline = priv->params.tx_max_inline;
1623         param->min_inline_mode = priv->params.tx_min_inline_mode;
1624         param->type = MLX5E_SQ_TXQ;
1625 }
1626
1627 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1628                                         struct mlx5e_cq_param *param)
1629 {
1630         void *cqc = param->cqc;
1631
1632         MLX5_SET(cqc, cqc, uar_page, priv->mdev->mlx5e_res.cq_uar.index);
1633 }
1634
1635 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1636                                     struct mlx5e_cq_param *param)
1637 {
1638         void *cqc = param->cqc;
1639         u8 log_cq_size;
1640
1641         switch (priv->params.rq_wq_type) {
1642         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1643                 log_cq_size = priv->params.log_rq_size +
1644                         priv->params.mpwqe_log_num_strides;
1645                 break;
1646         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1647                 log_cq_size = priv->params.log_rq_size;
1648         }
1649
1650         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1651         if (priv->params.rx_cqe_compress) {
1652                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1653                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1654         }
1655
1656         mlx5e_build_common_cq_param(priv, param);
1657
1658         param->cq_period_mode = priv->params.rx_cq_period_mode;
1659 }
1660
1661 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1662                                     struct mlx5e_cq_param *param)
1663 {
1664         void *cqc = param->cqc;
1665
1666         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1667
1668         mlx5e_build_common_cq_param(priv, param);
1669
1670         param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1671 }
1672
1673 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1674                                      struct mlx5e_cq_param *param,
1675                                      u8 log_wq_size)
1676 {
1677         void *cqc = param->cqc;
1678
1679         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1680
1681         mlx5e_build_common_cq_param(priv, param);
1682
1683         param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1684 }
1685
1686 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1687                                     struct mlx5e_sq_param *param,
1688                                     u8 log_wq_size)
1689 {
1690         void *sqc = param->sqc;
1691         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1692
1693         mlx5e_build_sq_param_common(priv, param);
1694
1695         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
1696         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
1697
1698         param->type = MLX5E_SQ_ICO;
1699 }
1700
1701 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
1702                                     struct mlx5e_sq_param *param)
1703 {
1704         void *sqc = param->sqc;
1705         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1706
1707         mlx5e_build_sq_param_common(priv, param);
1708         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1709
1710         param->max_inline = priv->params.tx_max_inline;
1711         /* FOR XDP SQs will support only L2 inline mode */
1712         param->min_inline_mode = MLX5_INLINE_MODE_NONE;
1713         param->type = MLX5E_SQ_XDP;
1714 }
1715
1716 static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
1717 {
1718         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
1719
1720         mlx5e_build_rq_param(priv, &cparam->rq);
1721         mlx5e_build_sq_param(priv, &cparam->sq);
1722         mlx5e_build_xdpsq_param(priv, &cparam->xdp_sq);
1723         mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
1724         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1725         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1726         mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
1727 }
1728
1729 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1730 {
1731         struct mlx5e_channel_param *cparam;
1732         int nch = priv->params.num_channels;
1733         int err = -ENOMEM;
1734         int i;
1735         int j;
1736
1737         priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1738                                 GFP_KERNEL);
1739
1740         priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1741                                       sizeof(struct mlx5e_sq *), GFP_KERNEL);
1742
1743         cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1744
1745         if (!priv->channel || !priv->txq_to_sq_map || !cparam)
1746                 goto err_free_txq_to_sq_map;
1747
1748         mlx5e_build_channel_param(priv, cparam);
1749
1750         for (i = 0; i < nch; i++) {
1751                 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
1752                 if (err)
1753                         goto err_close_channels;
1754         }
1755
1756         for (j = 0; j < nch; j++) {
1757                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1758                 if (err)
1759                         goto err_close_channels;
1760         }
1761
1762         /* FIXME: This is a W/A for tx timeout watch dog false alarm when
1763          * polling for inactive tx queues.
1764          */
1765         netif_tx_start_all_queues(priv->netdev);
1766
1767         kfree(cparam);
1768         return 0;
1769
1770 err_close_channels:
1771         for (i--; i >= 0; i--)
1772                 mlx5e_close_channel(priv->channel[i]);
1773
1774 err_free_txq_to_sq_map:
1775         kfree(priv->txq_to_sq_map);
1776         kfree(priv->channel);
1777         kfree(cparam);
1778
1779         return err;
1780 }
1781
1782 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1783 {
1784         int i;
1785
1786         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
1787          * polling for inactive tx queues.
1788          */
1789         netif_tx_stop_all_queues(priv->netdev);
1790         netif_tx_disable(priv->netdev);
1791
1792         for (i = 0; i < priv->params.num_channels; i++)
1793                 mlx5e_close_channel(priv->channel[i]);
1794
1795         kfree(priv->txq_to_sq_map);
1796         kfree(priv->channel);
1797 }
1798
1799 static int mlx5e_rx_hash_fn(int hfunc)
1800 {
1801         return (hfunc == ETH_RSS_HASH_TOP) ?
1802                MLX5_RX_HASH_FN_TOEPLITZ :
1803                MLX5_RX_HASH_FN_INVERTED_XOR8;
1804 }
1805
1806 static int mlx5e_bits_invert(unsigned long a, int size)
1807 {
1808         int inv = 0;
1809         int i;
1810
1811         for (i = 0; i < size; i++)
1812                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1813
1814         return inv;
1815 }
1816
1817 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1818 {
1819         int i;
1820
1821         for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1822                 int ix = i;
1823                 u32 rqn;
1824
1825                 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1826                         ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1827
1828                 ix = priv->params.indirection_rqt[ix];
1829                 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1830                                 priv->channel[ix]->rq.rqn :
1831                                 priv->drop_rq.rqn;
1832                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
1833         }
1834 }
1835
1836 static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1837                                       int ix)
1838 {
1839         u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1840                         priv->channel[ix]->rq.rqn :
1841                         priv->drop_rq.rqn;
1842
1843         MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
1844 }
1845
1846 static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz,
1847                             int ix, struct mlx5e_rqt *rqt)
1848 {
1849         struct mlx5_core_dev *mdev = priv->mdev;
1850         void *rqtc;
1851         int inlen;
1852         int err;
1853         u32 *in;
1854
1855         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1856         in = mlx5_vzalloc(inlen);
1857         if (!in)
1858                 return -ENOMEM;
1859
1860         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1861
1862         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1863         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1864
1865         if (sz > 1) /* RSS */
1866                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1867         else
1868                 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1869
1870         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
1871         if (!err)
1872                 rqt->enabled = true;
1873
1874         kvfree(in);
1875         return err;
1876 }
1877
1878 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1879 {
1880         rqt->enabled = false;
1881         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1882 }
1883
1884 static int mlx5e_create_indirect_rqts(struct mlx5e_priv *priv)
1885 {
1886         struct mlx5e_rqt *rqt = &priv->indir_rqt;
1887
1888         return mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqt);
1889 }
1890
1891 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1892 {
1893         struct mlx5e_rqt *rqt;
1894         int err;
1895         int ix;
1896
1897         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1898                 rqt = &priv->direct_tir[ix].rqt;
1899                 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqt);
1900                 if (err)
1901                         goto err_destroy_rqts;
1902         }
1903
1904         return 0;
1905
1906 err_destroy_rqts:
1907         for (ix--; ix >= 0; ix--)
1908                 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
1909
1910         return err;
1911 }
1912
1913 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
1914 {
1915         struct mlx5_core_dev *mdev = priv->mdev;
1916         void *rqtc;
1917         int inlen;
1918         u32 *in;
1919         int err;
1920
1921         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1922         in = mlx5_vzalloc(inlen);
1923         if (!in)
1924                 return -ENOMEM;
1925
1926         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1927
1928         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1929         if (sz > 1) /* RSS */
1930                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1931         else
1932                 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1933
1934         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1935
1936         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
1937
1938         kvfree(in);
1939
1940         return err;
1941 }
1942
1943 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1944 {
1945         u32 rqtn;
1946         int ix;
1947
1948         if (priv->indir_rqt.enabled) {
1949                 rqtn = priv->indir_rqt.rqtn;
1950                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
1951         }
1952
1953         for (ix = 0; ix < priv->params.num_channels; ix++) {
1954                 if (!priv->direct_tir[ix].rqt.enabled)
1955                         continue;
1956                 rqtn = priv->direct_tir[ix].rqt.rqtn;
1957                 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
1958         }
1959 }
1960
1961 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1962 {
1963         if (!priv->params.lro_en)
1964                 return;
1965
1966 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1967
1968         MLX5_SET(tirc, tirc, lro_enable_mask,
1969                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1970                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1971         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1972                  (priv->params.lro_wqe_sz -
1973                   ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1974         MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1975                  MLX5_CAP_ETH(priv->mdev,
1976                               lro_timer_supported_periods[2]));
1977 }
1978
1979 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1980 {
1981         MLX5_SET(tirc, tirc, rx_hash_fn,
1982                  mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1983         if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1984                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1985                                              rx_hash_toeplitz_key);
1986                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1987                                                rx_hash_toeplitz_key);
1988
1989                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1990                 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1991         }
1992 }
1993
1994 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
1995 {
1996         struct mlx5_core_dev *mdev = priv->mdev;
1997
1998         void *in;
1999         void *tirc;
2000         int inlen;
2001         int err;
2002         int tt;
2003         int ix;
2004
2005         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2006         in = mlx5_vzalloc(inlen);
2007         if (!in)
2008                 return -ENOMEM;
2009
2010         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2011         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2012
2013         mlx5e_build_tir_ctx_lro(tirc, priv);
2014
2015         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2016                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2017                                            inlen);
2018                 if (err)
2019                         goto free_in;
2020         }
2021
2022         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2023                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2024                                            in, inlen);
2025                 if (err)
2026                         goto free_in;
2027         }
2028
2029 free_in:
2030         kvfree(in);
2031
2032         return err;
2033 }
2034
2035 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
2036 {
2037         struct mlx5_core_dev *mdev = priv->mdev;
2038         u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
2039         int err;
2040
2041         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2042         if (err)
2043                 return err;
2044
2045         /* Update vport context MTU */
2046         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2047         return 0;
2048 }
2049
2050 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
2051 {
2052         struct mlx5_core_dev *mdev = priv->mdev;
2053         u16 hw_mtu = 0;
2054         int err;
2055
2056         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2057         if (err || !hw_mtu) /* fallback to port oper mtu */
2058                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2059
2060         *mtu = MLX5E_HW2SW_MTU(hw_mtu);
2061 }
2062
2063 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
2064 {
2065         struct mlx5e_priv *priv = netdev_priv(netdev);
2066         u16 mtu;
2067         int err;
2068
2069         err = mlx5e_set_mtu(priv, netdev->mtu);
2070         if (err)
2071                 return err;
2072
2073         mlx5e_query_mtu(priv, &mtu);
2074         if (mtu != netdev->mtu)
2075                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2076                             __func__, mtu, netdev->mtu);
2077
2078         netdev->mtu = mtu;
2079         return 0;
2080 }
2081
2082 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2083 {
2084         struct mlx5e_priv *priv = netdev_priv(netdev);
2085         int nch = priv->params.num_channels;
2086         int ntc = priv->params.num_tc;
2087         int tc;
2088
2089         netdev_reset_tc(netdev);
2090
2091         if (ntc == 1)
2092                 return;
2093
2094         netdev_set_num_tc(netdev, ntc);
2095
2096         /* Map netdev TCs to offset 0
2097          * We have our own UP to TXQ mapping for QoS
2098          */
2099         for (tc = 0; tc < ntc; tc++)
2100                 netdev_set_tc_queue(netdev, tc, nch, 0);
2101 }
2102
2103 int mlx5e_open_locked(struct net_device *netdev)
2104 {
2105         struct mlx5e_priv *priv = netdev_priv(netdev);
2106         struct mlx5_core_dev *mdev = priv->mdev;
2107         int num_txqs;
2108         int err;
2109
2110         set_bit(MLX5E_STATE_OPENED, &priv->state);
2111
2112         mlx5e_netdev_set_tcs(netdev);
2113
2114         num_txqs = priv->params.num_channels * priv->params.num_tc;
2115         netif_set_real_num_tx_queues(netdev, num_txqs);
2116         netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
2117
2118         err = mlx5e_open_channels(priv);
2119         if (err) {
2120                 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
2121                            __func__, err);
2122                 goto err_clear_state_opened_flag;
2123         }
2124
2125         err = mlx5e_refresh_tirs_self_loopback_enable(priv->mdev);
2126         if (err) {
2127                 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
2128                            __func__, err);
2129                 goto err_close_channels;
2130         }
2131
2132         mlx5e_redirect_rqts(priv);
2133         mlx5e_update_carrier(priv);
2134         mlx5e_timestamp_init(priv);
2135 #ifdef CONFIG_RFS_ACCEL
2136         priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
2137 #endif
2138         if (priv->profile->update_stats)
2139                 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
2140
2141         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
2142                 err = mlx5e_add_sqs_fwd_rules(priv);
2143                 if (err)
2144                         goto err_close_channels;
2145         }
2146         return 0;
2147
2148 err_close_channels:
2149         mlx5e_close_channels(priv);
2150 err_clear_state_opened_flag:
2151         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2152         return err;
2153 }
2154
2155 int mlx5e_open(struct net_device *netdev)
2156 {
2157         struct mlx5e_priv *priv = netdev_priv(netdev);
2158         int err;
2159
2160         mutex_lock(&priv->state_lock);
2161         err = mlx5e_open_locked(netdev);
2162         mutex_unlock(&priv->state_lock);
2163
2164         return err;
2165 }
2166
2167 int mlx5e_close_locked(struct net_device *netdev)
2168 {
2169         struct mlx5e_priv *priv = netdev_priv(netdev);
2170         struct mlx5_core_dev *mdev = priv->mdev;
2171
2172         /* May already be CLOSED in case a previous configuration operation
2173          * (e.g RX/TX queue size change) that involves close&open failed.
2174          */
2175         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2176                 return 0;
2177
2178         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2179
2180         if (MLX5_CAP_GEN(mdev, vport_group_manager))
2181                 mlx5e_remove_sqs_fwd_rules(priv);
2182
2183         mlx5e_timestamp_cleanup(priv);
2184         netif_carrier_off(priv->netdev);
2185         mlx5e_redirect_rqts(priv);
2186         mlx5e_close_channels(priv);
2187
2188         return 0;
2189 }
2190
2191 int mlx5e_close(struct net_device *netdev)
2192 {
2193         struct mlx5e_priv *priv = netdev_priv(netdev);
2194         int err;
2195
2196         if (!netif_device_present(netdev))
2197                 return -ENODEV;
2198
2199         mutex_lock(&priv->state_lock);
2200         err = mlx5e_close_locked(netdev);
2201         mutex_unlock(&priv->state_lock);
2202
2203         return err;
2204 }
2205
2206 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
2207                                 struct mlx5e_rq *rq,
2208                                 struct mlx5e_rq_param *param)
2209 {
2210         struct mlx5_core_dev *mdev = priv->mdev;
2211         void *rqc = param->rqc;
2212         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2213         int err;
2214
2215         param->wq.db_numa_node = param->wq.buf_numa_node;
2216
2217         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2218                                 &rq->wq_ctrl);
2219         if (err)
2220                 return err;
2221
2222         rq->priv = priv;
2223
2224         return 0;
2225 }
2226
2227 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
2228                                 struct mlx5e_cq *cq,
2229                                 struct mlx5e_cq_param *param)
2230 {
2231         struct mlx5_core_dev *mdev = priv->mdev;
2232         struct mlx5_core_cq *mcq = &cq->mcq;
2233         int eqn_not_used;
2234         unsigned int irqn;
2235         int err;
2236
2237         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
2238                                &cq->wq_ctrl);
2239         if (err)
2240                 return err;
2241
2242         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
2243
2244         mcq->cqe_sz     = 64;
2245         mcq->set_ci_db  = cq->wq_ctrl.db.db;
2246         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
2247         *mcq->set_ci_db = 0;
2248         *mcq->arm_db    = 0;
2249         mcq->vector     = param->eq_ix;
2250         mcq->comp       = mlx5e_completion_event;
2251         mcq->event      = mlx5e_cq_error_event;
2252         mcq->irqn       = irqn;
2253         mcq->uar        = &mdev->mlx5e_res.cq_uar;
2254
2255         cq->priv = priv;
2256
2257         return 0;
2258 }
2259
2260 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
2261 {
2262         struct mlx5e_cq_param cq_param;
2263         struct mlx5e_rq_param rq_param;
2264         struct mlx5e_rq *rq = &priv->drop_rq;
2265         struct mlx5e_cq *cq = &priv->drop_rq.cq;
2266         int err;
2267
2268         memset(&cq_param, 0, sizeof(cq_param));
2269         memset(&rq_param, 0, sizeof(rq_param));
2270         mlx5e_build_drop_rq_param(&rq_param);
2271
2272         err = mlx5e_create_drop_cq(priv, cq, &cq_param);
2273         if (err)
2274                 return err;
2275
2276         err = mlx5e_enable_cq(cq, &cq_param);
2277         if (err)
2278                 goto err_destroy_cq;
2279
2280         err = mlx5e_create_drop_rq(priv, rq, &rq_param);
2281         if (err)
2282                 goto err_disable_cq;
2283
2284         err = mlx5e_enable_rq(rq, &rq_param);
2285         if (err)
2286                 goto err_destroy_rq;
2287
2288         return 0;
2289
2290 err_destroy_rq:
2291         mlx5e_destroy_rq(&priv->drop_rq);
2292
2293 err_disable_cq:
2294         mlx5e_disable_cq(&priv->drop_rq.cq);
2295
2296 err_destroy_cq:
2297         mlx5e_destroy_cq(&priv->drop_rq.cq);
2298
2299         return err;
2300 }
2301
2302 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
2303 {
2304         mlx5e_disable_rq(&priv->drop_rq);
2305         mlx5e_destroy_rq(&priv->drop_rq);
2306         mlx5e_disable_cq(&priv->drop_rq.cq);
2307         mlx5e_destroy_cq(&priv->drop_rq.cq);
2308 }
2309
2310 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
2311 {
2312         struct mlx5_core_dev *mdev = priv->mdev;
2313         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
2314         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2315
2316         MLX5_SET(tisc, tisc, prio, tc << 1);
2317         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
2318
2319         if (mlx5_lag_is_lacp_owner(mdev))
2320                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2321
2322         return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
2323 }
2324
2325 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
2326 {
2327         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2328 }
2329
2330 int mlx5e_create_tises(struct mlx5e_priv *priv)
2331 {
2332         int err;
2333         int tc;
2334
2335         for (tc = 0; tc < priv->profile->max_tc; tc++) {
2336                 err = mlx5e_create_tis(priv, tc);
2337                 if (err)
2338                         goto err_close_tises;
2339         }
2340
2341         return 0;
2342
2343 err_close_tises:
2344         for (tc--; tc >= 0; tc--)
2345                 mlx5e_destroy_tis(priv, tc);
2346
2347         return err;
2348 }
2349
2350 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2351 {
2352         int tc;
2353
2354         for (tc = 0; tc < priv->profile->max_tc; tc++)
2355                 mlx5e_destroy_tis(priv, tc);
2356 }
2357
2358 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2359                                       enum mlx5e_traffic_types tt)
2360 {
2361         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2362
2363         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2364
2365 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2366                                  MLX5_HASH_FIELD_SEL_DST_IP)
2367
2368 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2369                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2370                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
2371                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
2372
2373 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2374                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2375                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2376
2377         mlx5e_build_tir_ctx_lro(tirc, priv);
2378
2379         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2380         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2381         mlx5e_build_tir_ctx_hash(tirc, priv);
2382
2383         switch (tt) {
2384         case MLX5E_TT_IPV4_TCP:
2385                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2386                          MLX5_L3_PROT_TYPE_IPV4);
2387                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2388                          MLX5_L4_PROT_TYPE_TCP);
2389                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2390                          MLX5_HASH_IP_L4PORTS);
2391                 break;
2392
2393         case MLX5E_TT_IPV6_TCP:
2394                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2395                          MLX5_L3_PROT_TYPE_IPV6);
2396                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2397                          MLX5_L4_PROT_TYPE_TCP);
2398                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2399                          MLX5_HASH_IP_L4PORTS);
2400                 break;
2401
2402         case MLX5E_TT_IPV4_UDP:
2403                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2404                          MLX5_L3_PROT_TYPE_IPV4);
2405                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2406                          MLX5_L4_PROT_TYPE_UDP);
2407                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2408                          MLX5_HASH_IP_L4PORTS);
2409                 break;
2410
2411         case MLX5E_TT_IPV6_UDP:
2412                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2413                          MLX5_L3_PROT_TYPE_IPV6);
2414                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2415                          MLX5_L4_PROT_TYPE_UDP);
2416                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2417                          MLX5_HASH_IP_L4PORTS);
2418                 break;
2419
2420         case MLX5E_TT_IPV4_IPSEC_AH:
2421                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2422                          MLX5_L3_PROT_TYPE_IPV4);
2423                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2424                          MLX5_HASH_IP_IPSEC_SPI);
2425                 break;
2426
2427         case MLX5E_TT_IPV6_IPSEC_AH:
2428                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2429                          MLX5_L3_PROT_TYPE_IPV6);
2430                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2431                          MLX5_HASH_IP_IPSEC_SPI);
2432                 break;
2433
2434         case MLX5E_TT_IPV4_IPSEC_ESP:
2435                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2436                          MLX5_L3_PROT_TYPE_IPV4);
2437                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2438                          MLX5_HASH_IP_IPSEC_SPI);
2439                 break;
2440
2441         case MLX5E_TT_IPV6_IPSEC_ESP:
2442                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2443                          MLX5_L3_PROT_TYPE_IPV6);
2444                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2445                          MLX5_HASH_IP_IPSEC_SPI);
2446                 break;
2447
2448         case MLX5E_TT_IPV4:
2449                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2450                          MLX5_L3_PROT_TYPE_IPV4);
2451                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2452                          MLX5_HASH_IP);
2453                 break;
2454
2455         case MLX5E_TT_IPV6:
2456                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2457                          MLX5_L3_PROT_TYPE_IPV6);
2458                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2459                          MLX5_HASH_IP);
2460                 break;
2461         default:
2462                 WARN_ONCE(true,
2463                           "mlx5e_build_indir_tir_ctx: bad traffic type!\n");
2464         }
2465 }
2466
2467 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2468                                        u32 rqtn)
2469 {
2470         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2471
2472         mlx5e_build_tir_ctx_lro(tirc, priv);
2473
2474         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2475         MLX5_SET(tirc, tirc, indirect_table, rqtn);
2476         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2477 }
2478
2479 static int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
2480 {
2481         struct mlx5e_tir *tir;
2482         void *tirc;
2483         int inlen;
2484         int err;
2485         u32 *in;
2486         int tt;
2487
2488         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2489         in = mlx5_vzalloc(inlen);
2490         if (!in)
2491                 return -ENOMEM;
2492
2493         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2494                 memset(in, 0, inlen);
2495                 tir = &priv->indir_tir[tt];
2496                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2497                 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
2498                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2499                 if (err)
2500                         goto err_destroy_tirs;
2501         }
2502
2503         kvfree(in);
2504
2505         return 0;
2506
2507 err_destroy_tirs:
2508         for (tt--; tt >= 0; tt--)
2509                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2510
2511         kvfree(in);
2512
2513         return err;
2514 }
2515
2516 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
2517 {
2518         int nch = priv->profile->max_nch(priv->mdev);
2519         struct mlx5e_tir *tir;
2520         void *tirc;
2521         int inlen;
2522         int err;
2523         u32 *in;
2524         int ix;
2525
2526         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2527         in = mlx5_vzalloc(inlen);
2528         if (!in)
2529                 return -ENOMEM;
2530
2531         for (ix = 0; ix < nch; ix++) {
2532                 memset(in, 0, inlen);
2533                 tir = &priv->direct_tir[ix];
2534                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2535                 mlx5e_build_direct_tir_ctx(priv, tirc,
2536                                            priv->direct_tir[ix].rqt.rqtn);
2537                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2538                 if (err)
2539                         goto err_destroy_ch_tirs;
2540         }
2541
2542         kvfree(in);
2543
2544         return 0;
2545
2546 err_destroy_ch_tirs:
2547         for (ix--; ix >= 0; ix--)
2548                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
2549
2550         kvfree(in);
2551
2552         return err;
2553 }
2554
2555 static void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
2556 {
2557         int i;
2558
2559         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2560                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
2561 }
2562
2563 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
2564 {
2565         int nch = priv->profile->max_nch(priv->mdev);
2566         int i;
2567
2568         for (i = 0; i < nch; i++)
2569                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2570 }
2571
2572 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2573 {
2574         int err = 0;
2575         int i;
2576
2577         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2578                 return 0;
2579
2580         for (i = 0; i < priv->params.num_channels; i++) {
2581                 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2582                 if (err)
2583                         return err;
2584         }
2585
2586         return 0;
2587 }
2588
2589 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2590 {
2591         struct mlx5e_priv *priv = netdev_priv(netdev);
2592         bool was_opened;
2593         int err = 0;
2594
2595         if (tc && tc != MLX5E_MAX_NUM_TC)
2596                 return -EINVAL;
2597
2598         mutex_lock(&priv->state_lock);
2599
2600         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2601         if (was_opened)
2602                 mlx5e_close_locked(priv->netdev);
2603
2604         priv->params.num_tc = tc ? tc : 1;
2605
2606         if (was_opened)
2607                 err = mlx5e_open_locked(priv->netdev);
2608
2609         mutex_unlock(&priv->state_lock);
2610
2611         return err;
2612 }
2613
2614 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2615                               __be16 proto, struct tc_to_netdev *tc)
2616 {
2617         struct mlx5e_priv *priv = netdev_priv(dev);
2618
2619         if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2620                 goto mqprio;
2621
2622         switch (tc->type) {
2623         case TC_SETUP_CLSFLOWER:
2624                 switch (tc->cls_flower->command) {
2625                 case TC_CLSFLOWER_REPLACE:
2626                         return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2627                 case TC_CLSFLOWER_DESTROY:
2628                         return mlx5e_delete_flower(priv, tc->cls_flower);
2629                 case TC_CLSFLOWER_STATS:
2630                         return mlx5e_stats_flower(priv, tc->cls_flower);
2631                 }
2632         default:
2633                 return -EOPNOTSUPP;
2634         }
2635
2636 mqprio:
2637         if (tc->type != TC_SETUP_MQPRIO)
2638                 return -EINVAL;
2639
2640         return mlx5e_setup_tc(dev, tc->tc);
2641 }
2642
2643 struct rtnl_link_stats64 *
2644 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2645 {
2646         struct mlx5e_priv *priv = netdev_priv(dev);
2647         struct mlx5e_sw_stats *sstats = &priv->stats.sw;
2648         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
2649         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
2650
2651         stats->rx_packets = sstats->rx_packets;
2652         stats->rx_bytes   = sstats->rx_bytes;
2653         stats->tx_packets = sstats->tx_packets;
2654         stats->tx_bytes   = sstats->tx_bytes;
2655
2656         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
2657         stats->tx_dropped = sstats->tx_queue_dropped;
2658
2659         stats->rx_length_errors =
2660                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2661                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2662                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
2663         stats->rx_crc_errors =
2664                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2665         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2666         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
2667         stats->tx_carrier_errors =
2668                 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
2669         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2670                            stats->rx_frame_errors;
2671         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2672
2673         /* vport multicast also counts packets that are dropped due to steering
2674          * or rx out of buffer
2675          */
2676         stats->multicast =
2677                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
2678
2679         return stats;
2680 }
2681
2682 static void mlx5e_set_rx_mode(struct net_device *dev)
2683 {
2684         struct mlx5e_priv *priv = netdev_priv(dev);
2685
2686         queue_work(priv->wq, &priv->set_rx_mode_work);
2687 }
2688
2689 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2690 {
2691         struct mlx5e_priv *priv = netdev_priv(netdev);
2692         struct sockaddr *saddr = addr;
2693
2694         if (!is_valid_ether_addr(saddr->sa_data))
2695                 return -EADDRNOTAVAIL;
2696
2697         netif_addr_lock_bh(netdev);
2698         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2699         netif_addr_unlock_bh(netdev);
2700
2701         queue_work(priv->wq, &priv->set_rx_mode_work);
2702
2703         return 0;
2704 }
2705
2706 #define MLX5E_SET_FEATURE(netdev, feature, enable)      \
2707         do {                                            \
2708                 if (enable)                             \
2709                         netdev->features |= feature;    \
2710                 else                                    \
2711                         netdev->features &= ~feature;   \
2712         } while (0)
2713
2714 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2715
2716 static int set_feature_lro(struct net_device *netdev, bool enable)
2717 {
2718         struct mlx5e_priv *priv = netdev_priv(netdev);
2719         bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2720         int err;
2721
2722         mutex_lock(&priv->state_lock);
2723
2724         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2725                 mlx5e_close_locked(priv->netdev);
2726
2727         priv->params.lro_en = enable;
2728         err = mlx5e_modify_tirs_lro(priv);
2729         if (err) {
2730                 netdev_err(netdev, "lro modify failed, %d\n", err);
2731                 priv->params.lro_en = !enable;
2732         }
2733
2734         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2735                 mlx5e_open_locked(priv->netdev);
2736
2737         mutex_unlock(&priv->state_lock);
2738
2739         return err;
2740 }
2741
2742 static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2743 {
2744         struct mlx5e_priv *priv = netdev_priv(netdev);
2745
2746         if (enable)
2747                 mlx5e_enable_vlan_filter(priv);
2748         else
2749                 mlx5e_disable_vlan_filter(priv);
2750
2751         return 0;
2752 }
2753
2754 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2755 {
2756         struct mlx5e_priv *priv = netdev_priv(netdev);
2757
2758         if (!enable && mlx5e_tc_num_filters(priv)) {
2759                 netdev_err(netdev,
2760                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2761                 return -EINVAL;
2762         }
2763
2764         return 0;
2765 }
2766
2767 static int set_feature_rx_all(struct net_device *netdev, bool enable)
2768 {
2769         struct mlx5e_priv *priv = netdev_priv(netdev);
2770         struct mlx5_core_dev *mdev = priv->mdev;
2771
2772         return mlx5_set_port_fcs(mdev, !enable);
2773 }
2774
2775 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2776 {
2777         struct mlx5e_priv *priv = netdev_priv(netdev);
2778         int err;
2779
2780         mutex_lock(&priv->state_lock);
2781
2782         priv->params.vlan_strip_disable = !enable;
2783         err = mlx5e_modify_rqs_vsd(priv, !enable);
2784         if (err)
2785                 priv->params.vlan_strip_disable = enable;
2786
2787         mutex_unlock(&priv->state_lock);
2788
2789         return err;
2790 }
2791
2792 #ifdef CONFIG_RFS_ACCEL
2793 static int set_feature_arfs(struct net_device *netdev, bool enable)
2794 {
2795         struct mlx5e_priv *priv = netdev_priv(netdev);
2796         int err;
2797
2798         if (enable)
2799                 err = mlx5e_arfs_enable(priv);
2800         else
2801                 err = mlx5e_arfs_disable(priv);
2802
2803         return err;
2804 }
2805 #endif
2806
2807 static int mlx5e_handle_feature(struct net_device *netdev,
2808                                 netdev_features_t wanted_features,
2809                                 netdev_features_t feature,
2810                                 mlx5e_feature_handler feature_handler)
2811 {
2812         netdev_features_t changes = wanted_features ^ netdev->features;
2813         bool enable = !!(wanted_features & feature);
2814         int err;
2815
2816         if (!(changes & feature))
2817                 return 0;
2818
2819         err = feature_handler(netdev, enable);
2820         if (err) {
2821                 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2822                            enable ? "Enable" : "Disable", feature, err);
2823                 return err;
2824         }
2825
2826         MLX5E_SET_FEATURE(netdev, feature, enable);
2827         return 0;
2828 }
2829
2830 static int mlx5e_set_features(struct net_device *netdev,
2831                               netdev_features_t features)
2832 {
2833         int err;
2834
2835         err  = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2836                                     set_feature_lro);
2837         err |= mlx5e_handle_feature(netdev, features,
2838                                     NETIF_F_HW_VLAN_CTAG_FILTER,
2839                                     set_feature_vlan_filter);
2840         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2841                                     set_feature_tc_num_filters);
2842         err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2843                                     set_feature_rx_all);
2844         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2845                                     set_feature_rx_vlan);
2846 #ifdef CONFIG_RFS_ACCEL
2847         err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2848                                     set_feature_arfs);
2849 #endif
2850
2851         return err ? -EINVAL : 0;
2852 }
2853
2854 #define MXL5_HW_MIN_MTU 64
2855 #define MXL5E_MIN_MTU (MXL5_HW_MIN_MTU + ETH_FCS_LEN)
2856
2857 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2858 {
2859         struct mlx5e_priv *priv = netdev_priv(netdev);
2860         struct mlx5_core_dev *mdev = priv->mdev;
2861         bool was_opened;
2862         u16 max_mtu;
2863         u16 min_mtu;
2864         int err = 0;
2865         bool reset;
2866
2867         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2868
2869         max_mtu = MLX5E_HW2SW_MTU(max_mtu);
2870         min_mtu = MLX5E_HW2SW_MTU(MXL5E_MIN_MTU);
2871
2872         if (new_mtu > max_mtu || new_mtu < min_mtu) {
2873                 netdev_err(netdev,
2874                            "%s: Bad MTU (%d), valid range is: [%d..%d]\n",
2875                            __func__, new_mtu, min_mtu, max_mtu);
2876                 return -EINVAL;
2877         }
2878
2879         mutex_lock(&priv->state_lock);
2880
2881         reset = !priv->params.lro_en &&
2882                 (priv->params.rq_wq_type !=
2883                  MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
2884
2885         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2886         if (was_opened && reset)
2887                 mlx5e_close_locked(netdev);
2888
2889         netdev->mtu = new_mtu;
2890         mlx5e_set_dev_port_mtu(netdev);
2891
2892         if (was_opened && reset)
2893                 err = mlx5e_open_locked(netdev);
2894
2895         mutex_unlock(&priv->state_lock);
2896
2897         return err;
2898 }
2899
2900 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2901 {
2902         switch (cmd) {
2903         case SIOCSHWTSTAMP:
2904                 return mlx5e_hwstamp_set(dev, ifr);
2905         case SIOCGHWTSTAMP:
2906                 return mlx5e_hwstamp_get(dev, ifr);
2907         default:
2908                 return -EOPNOTSUPP;
2909         }
2910 }
2911
2912 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2913 {
2914         struct mlx5e_priv *priv = netdev_priv(dev);
2915         struct mlx5_core_dev *mdev = priv->mdev;
2916
2917         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2918 }
2919
2920 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
2921                              __be16 vlan_proto)
2922 {
2923         struct mlx5e_priv *priv = netdev_priv(dev);
2924         struct mlx5_core_dev *mdev = priv->mdev;
2925
2926         if (vlan_proto != htons(ETH_P_8021Q))
2927                 return -EPROTONOSUPPORT;
2928
2929         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2930                                            vlan, qos);
2931 }
2932
2933 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2934 {
2935         struct mlx5e_priv *priv = netdev_priv(dev);
2936         struct mlx5_core_dev *mdev = priv->mdev;
2937
2938         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
2939 }
2940
2941 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
2942 {
2943         struct mlx5e_priv *priv = netdev_priv(dev);
2944         struct mlx5_core_dev *mdev = priv->mdev;
2945
2946         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
2947 }
2948 static int mlx5_vport_link2ifla(u8 esw_link)
2949 {
2950         switch (esw_link) {
2951         case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2952                 return IFLA_VF_LINK_STATE_DISABLE;
2953         case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2954                 return IFLA_VF_LINK_STATE_ENABLE;
2955         }
2956         return IFLA_VF_LINK_STATE_AUTO;
2957 }
2958
2959 static int mlx5_ifla_link2vport(u8 ifla_link)
2960 {
2961         switch (ifla_link) {
2962         case IFLA_VF_LINK_STATE_DISABLE:
2963                 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2964         case IFLA_VF_LINK_STATE_ENABLE:
2965                 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2966         }
2967         return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2968 }
2969
2970 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2971                                    int link_state)
2972 {
2973         struct mlx5e_priv *priv = netdev_priv(dev);
2974         struct mlx5_core_dev *mdev = priv->mdev;
2975
2976         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2977                                             mlx5_ifla_link2vport(link_state));
2978 }
2979
2980 static int mlx5e_get_vf_config(struct net_device *dev,
2981                                int vf, struct ifla_vf_info *ivi)
2982 {
2983         struct mlx5e_priv *priv = netdev_priv(dev);
2984         struct mlx5_core_dev *mdev = priv->mdev;
2985         int err;
2986
2987         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2988         if (err)
2989                 return err;
2990         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2991         return 0;
2992 }
2993
2994 static int mlx5e_get_vf_stats(struct net_device *dev,
2995                               int vf, struct ifla_vf_stats *vf_stats)
2996 {
2997         struct mlx5e_priv *priv = netdev_priv(dev);
2998         struct mlx5_core_dev *mdev = priv->mdev;
2999
3000         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3001                                             vf_stats);
3002 }
3003
3004 static void mlx5e_add_vxlan_port(struct net_device *netdev,
3005                                  struct udp_tunnel_info *ti)
3006 {
3007         struct mlx5e_priv *priv = netdev_priv(netdev);
3008
3009         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3010                 return;
3011
3012         if (!mlx5e_vxlan_allowed(priv->mdev))
3013                 return;
3014
3015         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
3016 }
3017
3018 static void mlx5e_del_vxlan_port(struct net_device *netdev,
3019                                  struct udp_tunnel_info *ti)
3020 {
3021         struct mlx5e_priv *priv = netdev_priv(netdev);
3022
3023         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3024                 return;
3025
3026         if (!mlx5e_vxlan_allowed(priv->mdev))
3027                 return;
3028
3029         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
3030 }
3031
3032 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
3033                                                     struct sk_buff *skb,
3034                                                     netdev_features_t features)
3035 {
3036         struct udphdr *udph;
3037         u16 proto;
3038         u16 port = 0;
3039
3040         switch (vlan_get_protocol(skb)) {
3041         case htons(ETH_P_IP):
3042                 proto = ip_hdr(skb)->protocol;
3043                 break;
3044         case htons(ETH_P_IPV6):
3045                 proto = ipv6_hdr(skb)->nexthdr;
3046                 break;
3047         default:
3048                 goto out;
3049         }
3050
3051         if (proto == IPPROTO_UDP) {
3052                 udph = udp_hdr(skb);
3053                 port = be16_to_cpu(udph->dest);
3054         }
3055
3056         /* Verify if UDP port is being offloaded by HW */
3057         if (port && mlx5e_vxlan_lookup_port(priv, port))
3058                 return features;
3059
3060 out:
3061         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3062         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3063 }
3064
3065 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3066                                               struct net_device *netdev,
3067                                               netdev_features_t features)
3068 {
3069         struct mlx5e_priv *priv = netdev_priv(netdev);
3070
3071         features = vlan_features_check(skb, features);
3072         features = vxlan_features_check(skb, features);
3073
3074         /* Validate if the tunneled packet is being offloaded by HW */
3075         if (skb->encapsulation &&
3076             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
3077                 return mlx5e_vxlan_features_check(priv, skb, features);
3078
3079         return features;
3080 }
3081
3082 static void mlx5e_tx_timeout(struct net_device *dev)
3083 {
3084         struct mlx5e_priv *priv = netdev_priv(dev);
3085         bool sched_work = false;
3086         int i;
3087
3088         netdev_err(dev, "TX timeout detected\n");
3089
3090         for (i = 0; i < priv->params.num_channels * priv->params.num_tc; i++) {
3091                 struct mlx5e_sq *sq = priv->txq_to_sq_map[i];
3092
3093                 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
3094                         continue;
3095                 sched_work = true;
3096                 set_bit(MLX5E_SQ_STATE_FLUSH, &sq->state);
3097                 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
3098                            i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
3099         }
3100
3101         if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
3102                 schedule_work(&priv->tx_timeout_work);
3103 }
3104
3105 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3106 {
3107         struct mlx5e_priv *priv = netdev_priv(netdev);
3108         struct bpf_prog *old_prog;
3109         int err = 0;
3110         bool reset, was_opened;
3111         int i;
3112
3113         mutex_lock(&priv->state_lock);
3114
3115         if ((netdev->features & NETIF_F_LRO) && prog) {
3116                 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3117                 err = -EINVAL;
3118                 goto unlock;
3119         }
3120
3121         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3122         /* no need for full reset when exchanging programs */
3123         reset = (!priv->xdp_prog || !prog);
3124
3125         if (was_opened && reset)
3126                 mlx5e_close_locked(netdev);
3127
3128         /* exchange programs */
3129         old_prog = xchg(&priv->xdp_prog, prog);
3130         if (prog)
3131                 bpf_prog_add(prog, 1);
3132         if (old_prog)
3133                 bpf_prog_put(old_prog);
3134
3135         if (reset) /* change RQ type according to priv->xdp_prog */
3136                 mlx5e_set_rq_priv_params(priv);
3137
3138         if (was_opened && reset)
3139                 mlx5e_open_locked(netdev);
3140
3141         if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3142                 goto unlock;
3143
3144         /* exchanging programs w/o reset, we update ref counts on behalf
3145          * of the channels RQs here.
3146          */
3147         bpf_prog_add(prog, priv->params.num_channels);
3148         for (i = 0; i < priv->params.num_channels; i++) {
3149                 struct mlx5e_channel *c = priv->channel[i];
3150
3151                 set_bit(MLX5E_RQ_STATE_FLUSH, &c->rq.state);
3152                 napi_synchronize(&c->napi);
3153                 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3154
3155                 old_prog = xchg(&c->rq.xdp_prog, prog);
3156
3157                 clear_bit(MLX5E_RQ_STATE_FLUSH, &c->rq.state);
3158                 /* napi_schedule in case we have missed anything */
3159                 set_bit(MLX5E_CHANNEL_NAPI_SCHED, &c->flags);
3160                 napi_schedule(&c->napi);
3161
3162                 if (old_prog)
3163                         bpf_prog_put(old_prog);
3164         }
3165
3166 unlock:
3167         mutex_unlock(&priv->state_lock);
3168         return err;
3169 }
3170
3171 static bool mlx5e_xdp_attached(struct net_device *dev)
3172 {
3173         struct mlx5e_priv *priv = netdev_priv(dev);
3174
3175         return !!priv->xdp_prog;
3176 }
3177
3178 static int mlx5e_xdp(struct net_device *dev, struct netdev_xdp *xdp)
3179 {
3180         switch (xdp->command) {
3181         case XDP_SETUP_PROG:
3182                 return mlx5e_xdp_set(dev, xdp->prog);
3183         case XDP_QUERY_PROG:
3184                 xdp->prog_attached = mlx5e_xdp_attached(dev);
3185                 return 0;
3186         default:
3187                 return -EINVAL;
3188         }
3189 }
3190
3191 #ifdef CONFIG_NET_POLL_CONTROLLER
3192 /* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3193  * reenabling interrupts.
3194  */
3195 static void mlx5e_netpoll(struct net_device *dev)
3196 {
3197         struct mlx5e_priv *priv = netdev_priv(dev);
3198         int i;
3199
3200         for (i = 0; i < priv->params.num_channels; i++)
3201                 napi_schedule(&priv->channel[i]->napi);
3202 }
3203 #endif
3204
3205 static const struct net_device_ops mlx5e_netdev_ops_basic = {
3206         .ndo_open                = mlx5e_open,
3207         .ndo_stop                = mlx5e_close,
3208         .ndo_start_xmit          = mlx5e_xmit,
3209         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
3210         .ndo_select_queue        = mlx5e_select_queue,
3211         .ndo_get_stats64         = mlx5e_get_stats,
3212         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
3213         .ndo_set_mac_address     = mlx5e_set_mac,
3214         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
3215         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
3216         .ndo_set_features        = mlx5e_set_features,
3217         .ndo_change_mtu          = mlx5e_change_mtu,
3218         .ndo_do_ioctl            = mlx5e_ioctl,
3219         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
3220 #ifdef CONFIG_RFS_ACCEL
3221         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
3222 #endif
3223         .ndo_tx_timeout          = mlx5e_tx_timeout,
3224         .ndo_xdp                 = mlx5e_xdp,
3225 #ifdef CONFIG_NET_POLL_CONTROLLER
3226         .ndo_poll_controller     = mlx5e_netpoll,
3227 #endif
3228 };
3229
3230 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
3231         .ndo_open                = mlx5e_open,
3232         .ndo_stop                = mlx5e_close,
3233         .ndo_start_xmit          = mlx5e_xmit,
3234         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
3235         .ndo_select_queue        = mlx5e_select_queue,
3236         .ndo_get_stats64         = mlx5e_get_stats,
3237         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
3238         .ndo_set_mac_address     = mlx5e_set_mac,
3239         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
3240         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
3241         .ndo_set_features        = mlx5e_set_features,
3242         .ndo_change_mtu          = mlx5e_change_mtu,
3243         .ndo_do_ioctl            = mlx5e_ioctl,
3244         .ndo_udp_tunnel_add      = mlx5e_add_vxlan_port,
3245         .ndo_udp_tunnel_del      = mlx5e_del_vxlan_port,
3246         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
3247         .ndo_features_check      = mlx5e_features_check,
3248 #ifdef CONFIG_RFS_ACCEL
3249         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
3250 #endif
3251         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
3252         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
3253         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
3254         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
3255         .ndo_get_vf_config       = mlx5e_get_vf_config,
3256         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
3257         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
3258         .ndo_tx_timeout          = mlx5e_tx_timeout,
3259         .ndo_xdp                 = mlx5e_xdp,
3260 #ifdef CONFIG_NET_POLL_CONTROLLER
3261         .ndo_poll_controller     = mlx5e_netpoll,
3262 #endif
3263 };
3264
3265 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3266 {
3267         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3268                 return -ENOTSUPP;
3269         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
3270             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
3271             !MLX5_CAP_ETH(mdev, csum_cap) ||
3272             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
3273             !MLX5_CAP_ETH(mdev, vlan_cap) ||
3274             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
3275             MLX5_CAP_FLOWTABLE(mdev,
3276                                flow_table_properties_nic_receive.max_ft_level)
3277                                < 3) {
3278                 mlx5_core_warn(mdev,
3279                                "Not creating net device, some required device capabilities are missing\n");
3280                 return -ENOTSUPP;
3281         }
3282         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
3283                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
3284         if (!MLX5_CAP_GEN(mdev, cq_moderation))
3285                 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
3286
3287         return 0;
3288 }
3289
3290 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3291 {
3292         int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
3293
3294         return bf_buf_size -
3295                sizeof(struct mlx5e_tx_wqe) +
3296                2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3297 }
3298
3299 #ifdef CONFIG_MLX5_CORE_EN_DCB
3300 static void mlx5e_ets_init(struct mlx5e_priv *priv)
3301 {
3302         int i;
3303
3304         priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
3305         for (i = 0; i < priv->params.ets.ets_cap; i++) {
3306                 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
3307                 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
3308                 priv->params.ets.prio_tc[i] = i;
3309         }
3310
3311         /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
3312         priv->params.ets.prio_tc[0] = 1;
3313         priv->params.ets.prio_tc[1] = 0;
3314 }
3315 #endif
3316
3317 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
3318                                    u32 *indirection_rqt, int len,
3319                                    int num_channels)
3320 {
3321         int node = mdev->priv.numa_node;
3322         int node_num_of_cores;
3323         int i;
3324
3325         if (node == -1)
3326                 node = first_online_node;
3327
3328         node_num_of_cores = cpumask_weight(cpumask_of_node(node));
3329
3330         if (node_num_of_cores)
3331                 num_channels = min_t(int, num_channels, node_num_of_cores);
3332
3333         for (i = 0; i < len; i++)
3334                 indirection_rqt[i] = i % num_channels;
3335 }
3336
3337 static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
3338 {
3339         enum pcie_link_width width;
3340         enum pci_bus_speed speed;
3341         int err = 0;
3342
3343         err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
3344         if (err)
3345                 return err;
3346
3347         if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
3348                 return -EINVAL;
3349
3350         switch (speed) {
3351         case PCIE_SPEED_2_5GT:
3352                 *pci_bw = 2500 * width;
3353                 break;
3354         case PCIE_SPEED_5_0GT:
3355                 *pci_bw = 5000 * width;
3356                 break;
3357         case PCIE_SPEED_8_0GT:
3358                 *pci_bw = 8000 * width;
3359                 break;
3360         default:
3361                 return -EINVAL;
3362         }
3363
3364         return 0;
3365 }
3366
3367 static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
3368 {
3369         return (link_speed && pci_bw &&
3370                 (pci_bw < 40000) && (pci_bw < link_speed));
3371 }
3372
3373 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
3374 {
3375         params->rx_cq_period_mode = cq_period_mode;
3376
3377         params->rx_cq_moderation.pkts =
3378                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3379         params->rx_cq_moderation.usec =
3380                         MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3381
3382         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
3383                 params->rx_cq_moderation.usec =
3384                         MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
3385 }
3386
3387 static void mlx5e_query_min_inline(struct mlx5_core_dev *mdev,
3388                                    u8 *min_inline_mode)
3389 {
3390         switch (MLX5_CAP_ETH(mdev, wqe_inline_mode)) {
3391         case MLX5E_INLINE_MODE_L2:
3392                 *min_inline_mode = MLX5_INLINE_MODE_L2;
3393                 break;
3394         case MLX5E_INLINE_MODE_VPORT_CONTEXT:
3395                 mlx5_query_nic_vport_min_inline(mdev,
3396                                                 min_inline_mode);
3397                 break;
3398         case MLX5_INLINE_MODE_NOT_REQUIRED:
3399                 *min_inline_mode = MLX5_INLINE_MODE_NONE;
3400                 break;
3401         }
3402 }
3403
3404 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
3405                                         struct net_device *netdev,
3406                                         const struct mlx5e_profile *profile,
3407                                         void *ppriv)
3408 {
3409         struct mlx5e_priv *priv = netdev_priv(netdev);
3410         u32 link_speed = 0;
3411         u32 pci_bw = 0;
3412         u8 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3413                                          MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
3414                                          MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
3415
3416         priv->mdev                         = mdev;
3417         priv->netdev                       = netdev;
3418         priv->params.num_channels          = profile->max_nch(mdev);
3419         priv->profile                      = profile;
3420         priv->ppriv                        = ppriv;
3421
3422         priv->params.log_sq_size = MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3423
3424         /* set CQE compression */
3425         priv->params.rx_cqe_compress_admin = false;
3426         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
3427             MLX5_CAP_GEN(mdev, vport_group_manager)) {
3428                 mlx5e_get_max_linkspeed(mdev, &link_speed);
3429                 mlx5e_get_pci_bw(mdev, &pci_bw);
3430                 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
3431                               link_speed, pci_bw);
3432                 priv->params.rx_cqe_compress_admin =
3433                         cqe_compress_heuristic(link_speed, pci_bw);
3434         }
3435         priv->params.rx_cqe_compress = priv->params.rx_cqe_compress_admin;
3436
3437         mlx5e_set_rq_priv_params(priv);
3438         if (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
3439                 priv->params.lro_en = true;
3440
3441         priv->params.rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
3442         mlx5e_set_rx_cq_mode_params(&priv->params, cq_period_mode);
3443
3444         priv->params.tx_cq_moderation.usec =
3445                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3446         priv->params.tx_cq_moderation.pkts =
3447                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3448         priv->params.tx_max_inline         = mlx5e_get_max_inline_cap(mdev);
3449         mlx5e_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3450         priv->params.num_tc                = 1;
3451         priv->params.rss_hfunc             = ETH_RSS_HASH_XOR;
3452
3453         netdev_rss_key_fill(priv->params.toeplitz_hash_key,
3454                             sizeof(priv->params.toeplitz_hash_key));
3455
3456         mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
3457                                       MLX5E_INDIR_RQT_SIZE, profile->max_nch(mdev));
3458
3459         priv->params.lro_wqe_sz =
3460                 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ -
3461                 /* Extra room needed for build_skb */
3462                 MLX5_RX_HEADROOM -
3463                 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3464
3465         /* Initialize pflags */
3466         MLX5E_SET_PRIV_FLAG(priv, MLX5E_PFLAG_RX_CQE_BASED_MODER,
3467                             priv->params.rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
3468
3469 #ifdef CONFIG_MLX5_CORE_EN_DCB
3470         mlx5e_ets_init(priv);
3471 #endif
3472
3473         mutex_init(&priv->state_lock);
3474
3475         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3476         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3477         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
3478         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3479 }
3480
3481 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
3482 {
3483         struct mlx5e_priv *priv = netdev_priv(netdev);
3484
3485         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
3486         if (is_zero_ether_addr(netdev->dev_addr) &&
3487             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
3488                 eth_hw_addr_random(netdev);
3489                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
3490         }
3491 }
3492
3493 static const struct switchdev_ops mlx5e_switchdev_ops = {
3494         .switchdev_port_attr_get        = mlx5e_attr_get,
3495 };
3496
3497 static void mlx5e_build_nic_netdev(struct net_device *netdev)
3498 {
3499         struct mlx5e_priv *priv = netdev_priv(netdev);
3500         struct mlx5_core_dev *mdev = priv->mdev;
3501         bool fcs_supported;
3502         bool fcs_enabled;
3503
3504         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
3505
3506         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
3507                 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
3508 #ifdef CONFIG_MLX5_CORE_EN_DCB
3509                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
3510 #endif
3511         } else {
3512                 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
3513         }
3514
3515         netdev->watchdog_timeo    = 15 * HZ;
3516
3517         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
3518
3519         netdev->vlan_features    |= NETIF_F_SG;
3520         netdev->vlan_features    |= NETIF_F_IP_CSUM;
3521         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
3522         netdev->vlan_features    |= NETIF_F_GRO;
3523         netdev->vlan_features    |= NETIF_F_TSO;
3524         netdev->vlan_features    |= NETIF_F_TSO6;
3525         netdev->vlan_features    |= NETIF_F_RXCSUM;
3526         netdev->vlan_features    |= NETIF_F_RXHASH;
3527
3528         if (!!MLX5_CAP_ETH(mdev, lro_cap))
3529                 netdev->vlan_features    |= NETIF_F_LRO;
3530
3531         netdev->hw_features       = netdev->vlan_features;
3532         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
3533         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
3534         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
3535
3536         if (mlx5e_vxlan_allowed(mdev)) {
3537                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
3538                                            NETIF_F_GSO_UDP_TUNNEL_CSUM |
3539                                            NETIF_F_GSO_PARTIAL;
3540                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
3541                 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
3542                 netdev->hw_enc_features |= NETIF_F_TSO;
3543                 netdev->hw_enc_features |= NETIF_F_TSO6;
3544                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
3545                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
3546                                            NETIF_F_GSO_PARTIAL;
3547                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
3548         }
3549
3550         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
3551
3552         if (fcs_supported)
3553                 netdev->hw_features |= NETIF_F_RXALL;
3554
3555         netdev->features          = netdev->hw_features;
3556         if (!priv->params.lro_en)
3557                 netdev->features  &= ~NETIF_F_LRO;
3558
3559         if (fcs_enabled)
3560                 netdev->features  &= ~NETIF_F_RXALL;
3561
3562 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
3563         if (FT_CAP(flow_modify_en) &&
3564             FT_CAP(modify_root) &&
3565             FT_CAP(identified_miss_table_mode) &&
3566             FT_CAP(flow_table_modify)) {
3567                 netdev->hw_features      |= NETIF_F_HW_TC;
3568 #ifdef CONFIG_RFS_ACCEL
3569                 netdev->hw_features      |= NETIF_F_NTUPLE;
3570 #endif
3571         }
3572
3573         netdev->features         |= NETIF_F_HIGHDMA;
3574
3575         netdev->priv_flags       |= IFF_UNICAST_FLT;
3576
3577         mlx5e_set_netdev_dev_addr(netdev);
3578
3579 #ifdef CONFIG_NET_SWITCHDEV
3580         if (MLX5_CAP_GEN(mdev, vport_group_manager))
3581                 netdev->switchdev_ops = &mlx5e_switchdev_ops;
3582 #endif
3583 }
3584
3585 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
3586 {
3587         struct mlx5_core_dev *mdev = priv->mdev;
3588         int err;
3589
3590         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
3591         if (err) {
3592                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
3593                 priv->q_counter = 0;
3594         }
3595 }
3596
3597 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
3598 {
3599         if (!priv->q_counter)
3600                 return;
3601
3602         mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
3603 }
3604
3605 static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv)
3606 {
3607         struct mlx5_core_dev *mdev = priv->mdev;
3608         u64 npages = MLX5E_REQUIRED_MTTS(priv->profile->max_nch(mdev),
3609                                          BIT(MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW));
3610         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
3611         void *mkc;
3612         u32 *in;
3613         int err;
3614
3615         in = mlx5_vzalloc(inlen);
3616         if (!in)
3617                 return -ENOMEM;
3618
3619         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
3620
3621         npages = min_t(u32, ALIGN(U16_MAX, 4) * 2, npages);
3622
3623         MLX5_SET(mkc, mkc, free, 1);
3624         MLX5_SET(mkc, mkc, umr_en, 1);
3625         MLX5_SET(mkc, mkc, lw, 1);
3626         MLX5_SET(mkc, mkc, lr, 1);
3627         MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
3628
3629         MLX5_SET(mkc, mkc, qpn, 0xffffff);
3630         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
3631         MLX5_SET64(mkc, mkc, len, npages << PAGE_SHIFT);
3632         MLX5_SET(mkc, mkc, translations_octword_size,
3633                  MLX5_MTT_OCTW(npages));
3634         MLX5_SET(mkc, mkc, log_page_size, PAGE_SHIFT);
3635
3636         err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen);
3637
3638         kvfree(in);
3639         return err;
3640 }
3641
3642 static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
3643                            struct net_device *netdev,
3644                            const struct mlx5e_profile *profile,
3645                            void *ppriv)
3646 {
3647         struct mlx5e_priv *priv = netdev_priv(netdev);
3648
3649         mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
3650         mlx5e_build_nic_netdev(netdev);
3651         mlx5e_vxlan_init(priv);
3652 }
3653
3654 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
3655 {
3656         struct mlx5_core_dev *mdev = priv->mdev;
3657         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3658
3659         mlx5e_vxlan_cleanup(priv);
3660
3661         if (MLX5_CAP_GEN(mdev, vport_group_manager))
3662                 mlx5_eswitch_unregister_vport_rep(esw, 0);
3663 }
3664
3665 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
3666 {
3667         struct mlx5_core_dev *mdev = priv->mdev;
3668         int err;
3669         int i;
3670
3671         err = mlx5e_create_indirect_rqts(priv);
3672         if (err) {
3673                 mlx5_core_warn(mdev, "create indirect rqts failed, %d\n", err);
3674                 return err;
3675         }
3676
3677         err = mlx5e_create_direct_rqts(priv);
3678         if (err) {
3679                 mlx5_core_warn(mdev, "create direct rqts failed, %d\n", err);
3680                 goto err_destroy_indirect_rqts;
3681         }
3682
3683         err = mlx5e_create_indirect_tirs(priv);
3684         if (err) {
3685                 mlx5_core_warn(mdev, "create indirect tirs failed, %d\n", err);
3686                 goto err_destroy_direct_rqts;
3687         }
3688
3689         err = mlx5e_create_direct_tirs(priv);
3690         if (err) {
3691                 mlx5_core_warn(mdev, "create direct tirs failed, %d\n", err);
3692                 goto err_destroy_indirect_tirs;
3693         }
3694
3695         err = mlx5e_create_flow_steering(priv);
3696         if (err) {
3697                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
3698                 goto err_destroy_direct_tirs;
3699         }
3700
3701         err = mlx5e_tc_init(priv);
3702         if (err)
3703                 goto err_destroy_flow_steering;
3704
3705         return 0;
3706
3707 err_destroy_flow_steering:
3708         mlx5e_destroy_flow_steering(priv);
3709 err_destroy_direct_tirs:
3710         mlx5e_destroy_direct_tirs(priv);
3711 err_destroy_indirect_tirs:
3712         mlx5e_destroy_indirect_tirs(priv);
3713 err_destroy_direct_rqts:
3714         for (i = 0; i < priv->profile->max_nch(mdev); i++)
3715                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3716 err_destroy_indirect_rqts:
3717         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3718         return err;
3719 }
3720
3721 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
3722 {
3723         int i;
3724
3725         mlx5e_tc_cleanup(priv);
3726         mlx5e_destroy_flow_steering(priv);
3727         mlx5e_destroy_direct_tirs(priv);
3728         mlx5e_destroy_indirect_tirs(priv);
3729         for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
3730                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3731         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3732 }
3733
3734 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
3735 {
3736         int err;
3737
3738         err = mlx5e_create_tises(priv);
3739         if (err) {
3740                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
3741                 return err;
3742         }
3743
3744 #ifdef CONFIG_MLX5_CORE_EN_DCB
3745         mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
3746 #endif
3747         return 0;
3748 }
3749
3750 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
3751 {
3752         struct net_device *netdev = priv->netdev;
3753         struct mlx5_core_dev *mdev = priv->mdev;
3754         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3755         struct mlx5_eswitch_rep rep;
3756
3757         mlx5_lag_add(mdev, netdev);
3758
3759         if (mlx5e_vxlan_allowed(mdev)) {
3760                 rtnl_lock();
3761                 udp_tunnel_get_rx_info(netdev);
3762                 rtnl_unlock();
3763         }
3764
3765         mlx5e_enable_async_events(priv);
3766         queue_work(priv->wq, &priv->set_rx_mode_work);
3767
3768         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
3769                 mlx5_query_nic_vport_mac_address(mdev, 0, rep.hw_id);
3770                 rep.load = mlx5e_nic_rep_load;
3771                 rep.unload = mlx5e_nic_rep_unload;
3772                 rep.vport = FDB_UPLINK_VPORT;
3773                 rep.priv_data = priv;
3774                 mlx5_eswitch_register_vport_rep(esw, 0, &rep);
3775         }
3776 }
3777
3778 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
3779 {
3780         queue_work(priv->wq, &priv->set_rx_mode_work);
3781         mlx5e_disable_async_events(priv);
3782         mlx5_lag_remove(priv->mdev);
3783 }
3784
3785 static const struct mlx5e_profile mlx5e_nic_profile = {
3786         .init              = mlx5e_nic_init,
3787         .cleanup           = mlx5e_nic_cleanup,
3788         .init_rx           = mlx5e_init_nic_rx,
3789         .cleanup_rx        = mlx5e_cleanup_nic_rx,
3790         .init_tx           = mlx5e_init_nic_tx,
3791         .cleanup_tx        = mlx5e_cleanup_nic_tx,
3792         .enable            = mlx5e_nic_enable,
3793         .disable           = mlx5e_nic_disable,
3794         .update_stats      = mlx5e_update_stats,
3795         .max_nch           = mlx5e_get_max_num_channels,
3796         .max_tc            = MLX5E_MAX_NUM_TC,
3797 };
3798
3799 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
3800                                        const struct mlx5e_profile *profile,
3801                                        void *ppriv)
3802 {
3803         int nch = profile->max_nch(mdev);
3804         struct net_device *netdev;
3805         struct mlx5e_priv *priv;
3806
3807         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
3808                                     nch * profile->max_tc,
3809                                     nch);
3810         if (!netdev) {
3811                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
3812                 return NULL;
3813         }
3814
3815         profile->init(mdev, netdev, profile, ppriv);
3816
3817         netif_carrier_off(netdev);
3818
3819         priv = netdev_priv(netdev);
3820
3821         priv->wq = create_singlethread_workqueue("mlx5e");
3822         if (!priv->wq)
3823                 goto err_cleanup_nic;
3824
3825         return netdev;
3826
3827 err_cleanup_nic:
3828         profile->cleanup(priv);
3829         free_netdev(netdev);
3830
3831         return NULL;
3832 }
3833
3834 int mlx5e_attach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
3835 {
3836         const struct mlx5e_profile *profile;
3837         struct mlx5e_priv *priv;
3838         int err;
3839
3840         priv = netdev_priv(netdev);
3841         profile = priv->profile;
3842         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
3843
3844         err = mlx5e_create_umr_mkey(priv);
3845         if (err) {
3846                 mlx5_core_err(mdev, "create umr mkey failed, %d\n", err);
3847                 goto out;
3848         }
3849
3850         err = profile->init_tx(priv);
3851         if (err)
3852                 goto err_destroy_umr_mkey;
3853
3854         err = mlx5e_open_drop_rq(priv);
3855         if (err) {
3856                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
3857                 goto err_cleanup_tx;
3858         }
3859
3860         err = profile->init_rx(priv);
3861         if (err)
3862                 goto err_close_drop_rq;
3863
3864         mlx5e_create_q_counter(priv);
3865
3866         mlx5e_init_l2_addr(priv);
3867
3868         mlx5e_set_dev_port_mtu(netdev);
3869
3870         if (profile->enable)
3871                 profile->enable(priv);
3872
3873         rtnl_lock();
3874         if (netif_running(netdev))
3875                 mlx5e_open(netdev);
3876         netif_device_attach(netdev);
3877         rtnl_unlock();
3878
3879         return 0;
3880
3881 err_close_drop_rq:
3882         mlx5e_close_drop_rq(priv);
3883
3884 err_cleanup_tx:
3885         profile->cleanup_tx(priv);
3886
3887 err_destroy_umr_mkey:
3888         mlx5_core_destroy_mkey(mdev, &priv->umr_mkey);
3889
3890 out:
3891         return err;
3892 }
3893
3894 static void mlx5e_register_vport_rep(struct mlx5_core_dev *mdev)
3895 {
3896         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3897         int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3898         int vport;
3899         u8 mac[ETH_ALEN];
3900
3901         if (!MLX5_CAP_GEN(mdev, vport_group_manager))
3902                 return;
3903
3904         mlx5_query_nic_vport_mac_address(mdev, 0, mac);
3905
3906         for (vport = 1; vport < total_vfs; vport++) {
3907                 struct mlx5_eswitch_rep rep;
3908
3909                 rep.load = mlx5e_vport_rep_load;
3910                 rep.unload = mlx5e_vport_rep_unload;
3911                 rep.vport = vport;
3912                 ether_addr_copy(rep.hw_id, mac);
3913                 mlx5_eswitch_register_vport_rep(esw, vport, &rep);
3914         }
3915 }
3916
3917 void mlx5e_detach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
3918 {
3919         struct mlx5e_priv *priv = netdev_priv(netdev);
3920         const struct mlx5e_profile *profile = priv->profile;
3921
3922         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
3923         if (profile->disable)
3924                 profile->disable(priv);
3925
3926         flush_workqueue(priv->wq);
3927
3928         rtnl_lock();
3929         if (netif_running(netdev))
3930                 mlx5e_close(netdev);
3931         netif_device_detach(netdev);
3932         rtnl_unlock();
3933
3934         mlx5e_destroy_q_counter(priv);
3935         profile->cleanup_rx(priv);
3936         mlx5e_close_drop_rq(priv);
3937         profile->cleanup_tx(priv);
3938         mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey);
3939         cancel_delayed_work_sync(&priv->update_stats_work);
3940 }
3941
3942 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
3943  * hardware contexts and to connect it to the current netdev.
3944  */
3945 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
3946 {
3947         struct mlx5e_priv *priv = vpriv;
3948         struct net_device *netdev = priv->netdev;
3949         int err;
3950
3951         if (netif_device_present(netdev))
3952                 return 0;
3953
3954         err = mlx5e_create_mdev_resources(mdev);
3955         if (err)
3956                 return err;
3957
3958         err = mlx5e_attach_netdev(mdev, netdev);
3959         if (err) {
3960                 mlx5e_destroy_mdev_resources(mdev);
3961                 return err;
3962         }
3963
3964         return 0;
3965 }
3966
3967 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
3968 {
3969         struct mlx5e_priv *priv = vpriv;
3970         struct net_device *netdev = priv->netdev;
3971
3972         if (!netif_device_present(netdev))
3973                 return;
3974
3975         mlx5e_detach_netdev(mdev, netdev);
3976         mlx5e_destroy_mdev_resources(mdev);
3977 }
3978
3979 static void *mlx5e_add(struct mlx5_core_dev *mdev)
3980 {
3981         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3982         int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3983         void *ppriv = NULL;
3984         void *priv;
3985         int vport;
3986         int err;
3987         struct net_device *netdev;
3988
3989         err = mlx5e_check_required_hca_cap(mdev);
3990         if (err)
3991                 return NULL;
3992
3993         mlx5e_register_vport_rep(mdev);
3994
3995         if (MLX5_CAP_GEN(mdev, vport_group_manager))
3996                 ppriv = &esw->offloads.vport_reps[0];
3997
3998         netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, ppriv);
3999         if (!netdev) {
4000                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
4001                 goto err_unregister_reps;
4002         }
4003
4004         priv = netdev_priv(netdev);
4005
4006         err = mlx5e_attach(mdev, priv);
4007         if (err) {
4008                 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4009                 goto err_destroy_netdev;
4010         }
4011
4012         err = register_netdev(netdev);
4013         if (err) {
4014                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4015                 goto err_detach;
4016         }
4017
4018         return priv;
4019
4020 err_detach:
4021         mlx5e_detach(mdev, priv);
4022
4023 err_destroy_netdev:
4024         mlx5e_destroy_netdev(mdev, priv);
4025
4026 err_unregister_reps:
4027         for (vport = 1; vport < total_vfs; vport++)
4028                 mlx5_eswitch_unregister_vport_rep(esw, vport);
4029
4030         return NULL;
4031 }
4032
4033 void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv)
4034 {
4035         const struct mlx5e_profile *profile = priv->profile;
4036         struct net_device *netdev = priv->netdev;
4037
4038         unregister_netdev(netdev);
4039         destroy_workqueue(priv->wq);
4040         if (profile->cleanup)
4041                 profile->cleanup(priv);
4042         free_netdev(netdev);
4043 }
4044
4045 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
4046 {
4047         struct mlx5_eswitch *esw = mdev->priv.eswitch;
4048         int total_vfs = MLX5_TOTAL_VPORTS(mdev);
4049         struct mlx5e_priv *priv = vpriv;
4050         int vport;
4051
4052         for (vport = 1; vport < total_vfs; vport++)
4053                 mlx5_eswitch_unregister_vport_rep(esw, vport);
4054
4055         mlx5e_detach(mdev, vpriv);
4056         mlx5e_destroy_netdev(mdev, priv);
4057 }
4058
4059 static void *mlx5e_get_netdev(void *vpriv)
4060 {
4061         struct mlx5e_priv *priv = vpriv;
4062
4063         return priv->netdev;
4064 }
4065
4066 static struct mlx5_interface mlx5e_interface = {
4067         .add       = mlx5e_add,
4068         .remove    = mlx5e_remove,
4069         .attach    = mlx5e_attach,
4070         .detach    = mlx5e_detach,
4071         .event     = mlx5e_async_event,
4072         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
4073         .get_dev   = mlx5e_get_netdev,
4074 };
4075
4076 void mlx5e_init(void)
4077 {
4078         mlx5e_build_ptys2ethtool_map();
4079         mlx5_register_interface(&mlx5e_interface);
4080 }
4081
4082 void mlx5e_cleanup(void)
4083 {
4084         mlx5_unregister_interface(&mlx5e_interface);
4085 }