drivers/net/ethernet/mellanox/mlxsw/pci.c

   1 /*
   2  * drivers/net/ethernet/mellanox/mlxsw/pci.c
   3  * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
   4  * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are met:
   8  *
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. Neither the names of the copyright holders nor the names of its
  15  *    contributors may be used to endorse or promote products derived from
  16  *    this software without specific prior written permission.
  17  *
  18  * Alternatively, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") version 2 as published by the Free
  20  * Software Foundation.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  23  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  26  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  32  * POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 #include <linux/kernel.h>
  36 #include <linux/module.h>
  37 #include <linux/export.h>
  38 #include <linux/err.h>
  39 #include <linux/device.h>
  40 #include <linux/pci.h>
  41 #include <linux/interrupt.h>
  42 #include <linux/wait.h>
  43 #include <linux/types.h>
  44 #include <linux/skbuff.h>
  45 #include <linux/if_vlan.h>
  46 #include <linux/log2.h>
  47 #include <linux/debugfs.h>
  48 #include <linux/seq_file.h>
  49
  50 #include "pci.h"
  51 #include "core.h"
  52 #include "cmd.h"
  53 #include "port.h"
  54
  55 static const char mlxsw_pci_driver_name[] = "mlxsw_pci";
  56
  57 static const struct pci_device_id mlxsw_pci_id_table[] = {
  58         {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SWITCHX2), 0},
  59         {0, }
  60 };
  61
  62 static struct dentry *mlxsw_pci_dbg_root;
  63
  64 static const char *mlxsw_pci_device_kind_get(const struct pci_device_id *id)
  65 {
  66         switch (id->device) {
  67         case PCI_DEVICE_ID_MELLANOX_SWITCHX2:
  68                 return MLXSW_DEVICE_KIND_SWITCHX2;
  69         default:
  70                 BUG();
  71         }
  72 }
  73
  74 #define mlxsw_pci_write32(mlxsw_pci, reg, val) \
  75         iowrite32be(val, (mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg))
  76 #define mlxsw_pci_read32(mlxsw_pci, reg) \
  77         ioread32be((mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg))
  78
  79 enum mlxsw_pci_queue_type {
  80         MLXSW_PCI_QUEUE_TYPE_SDQ,
  81         MLXSW_PCI_QUEUE_TYPE_RDQ,
  82         MLXSW_PCI_QUEUE_TYPE_CQ,
  83         MLXSW_PCI_QUEUE_TYPE_EQ,
  84 };
  85
  86 static const char *mlxsw_pci_queue_type_str(enum mlxsw_pci_queue_type q_type)
  87 {
  88         switch (q_type) {
  89         case MLXSW_PCI_QUEUE_TYPE_SDQ:
  90                 return "sdq";
  91         case MLXSW_PCI_QUEUE_TYPE_RDQ:
  92                 return "rdq";
  93         case MLXSW_PCI_QUEUE_TYPE_CQ:
  94                 return "cq";
  95         case MLXSW_PCI_QUEUE_TYPE_EQ:
  96                 return "eq";
  97         }
  98         BUG();
  99 }
 100
 101 #define MLXSW_PCI_QUEUE_TYPE_COUNT      4
 102
 103 static const u16 mlxsw_pci_doorbell_type_offset[] = {
 104         MLXSW_PCI_DOORBELL_SDQ_OFFSET,  /* for type MLXSW_PCI_QUEUE_TYPE_SDQ */
 105         MLXSW_PCI_DOORBELL_RDQ_OFFSET,  /* for type MLXSW_PCI_QUEUE_TYPE_RDQ */
 106         MLXSW_PCI_DOORBELL_CQ_OFFSET,   /* for type MLXSW_PCI_QUEUE_TYPE_CQ */
 107         MLXSW_PCI_DOORBELL_EQ_OFFSET,   /* for type MLXSW_PCI_QUEUE_TYPE_EQ */
 108 };
 109
 110 static const u16 mlxsw_pci_doorbell_arm_type_offset[] = {
 111         0, /* unused */
 112         0, /* unused */
 113         MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_CQ */
 114         MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_EQ */
 115 };
 116
 117 struct mlxsw_pci_mem_item {
 118         char *buf;
 119         dma_addr_t mapaddr;
 120         size_t size;
 121 };
 122
 123 struct mlxsw_pci_queue_elem_info {
 124         char *elem; /* pointer to actual dma mapped element mem chunk */
 125         union {
 126                 struct {
 127                         struct sk_buff *skb;
 128                 } sdq;
 129                 struct {
 130                         struct sk_buff *skb;
 131                 } rdq;
 132         } u;
 133 };
 134
 135 struct mlxsw_pci_queue {
 136         spinlock_t lock; /* for queue accesses */
 137         struct mlxsw_pci_mem_item mem_item;
 138         struct mlxsw_pci_queue_elem_info *elem_info;
 139         u16 producer_counter;
 140         u16 consumer_counter;
 141         u16 count; /* number of elements in queue */
 142         u8 num; /* queue number */
 143         u8 elem_size; /* size of one element */
 144         enum mlxsw_pci_queue_type type;
 145         struct tasklet_struct tasklet; /* queue processing tasklet */
 146         struct mlxsw_pci *pci;
 147         union {
 148                 struct {
 149                         u32 comp_sdq_count;
 150                         u32 comp_rdq_count;
 151                 } cq;
 152                 struct {
 153                         u32 ev_cmd_count;
 154                         u32 ev_comp_count;
 155                         u32 ev_other_count;
 156                 } eq;
 157         } u;
 158 };
 159
 160 struct mlxsw_pci_queue_type_group {
 161         struct mlxsw_pci_queue *q;
 162         u8 count; /* number of queues in group */
 163 };
 164
 165 struct mlxsw_pci {
 166         struct pci_dev *pdev;
 167         u8 __iomem *hw_addr;
 168         struct mlxsw_pci_queue_type_group queues[MLXSW_PCI_QUEUE_TYPE_COUNT];
 169         u32 doorbell_offset;
 170         struct msix_entry msix_entry;
 171         struct mlxsw_core *core;
 172         struct {
 173                 u16 num_pages;
 174                 struct mlxsw_pci_mem_item *items;
 175         } fw_area;
 176         struct {
 177                 struct mutex lock; /* Lock access to command registers */
 178                 bool nopoll;
 179                 wait_queue_head_t wait;
 180                 bool wait_done;
 181                 struct {
 182                         u8 status;
 183                         u64 out_param;
 184                 } comp;
 185         } cmd;
 186         struct mlxsw_bus_info bus_info;
 187         struct dentry *dbg_dir;
 188 };
 189
 190 static void mlxsw_pci_queue_tasklet_schedule(struct mlxsw_pci_queue *q)
 191 {
 192         tasklet_schedule(&q->tasklet);
 193 }
 194
 195 static char *__mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue *q,
 196                                         size_t elem_size, int elem_index)
 197 {
 198         return q->mem_item.buf + (elem_size * elem_index);
 199 }
 200
 201 static struct mlxsw_pci_queue_elem_info *
 202 mlxsw_pci_queue_elem_info_get(struct mlxsw_pci_queue *q, int elem_index)
 203 {
 204         return &q->elem_info[elem_index];
 205 }
 206
 207 static struct mlxsw_pci_queue_elem_info *
 208 mlxsw_pci_queue_elem_info_producer_get(struct mlxsw_pci_queue *q)
 209 {
 210         int index = q->producer_counter & (q->count - 1);
 211
 212         if ((q->producer_counter - q->consumer_counter) == q->count)
 213                 return NULL;
 214         return mlxsw_pci_queue_elem_info_get(q, index);
 215 }
 216
 217 static struct mlxsw_pci_queue_elem_info *
 218 mlxsw_pci_queue_elem_info_consumer_get(struct mlxsw_pci_queue *q)
 219 {
 220         int index = q->consumer_counter & (q->count - 1);
 221
 222         return mlxsw_pci_queue_elem_info_get(q, index);
 223 }
 224
 225 static char *mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue *q, int elem_index)
 226 {
 227         return mlxsw_pci_queue_elem_info_get(q, elem_index)->elem;
 228 }
 229
 230 static bool mlxsw_pci_elem_hw_owned(struct mlxsw_pci_queue *q, bool owner_bit)
 231 {
 232         return owner_bit != !!(q->consumer_counter & q->count);
 233 }
 234
 235 static char *mlxsw_pci_queue_sw_elem_get(struct mlxsw_pci_queue *q,
 236                                          u32 (*get_elem_owner_func)(char *))
 237 {
 238         struct mlxsw_pci_queue_elem_info *elem_info;
 239         char *elem;
 240         bool owner_bit;
 241
 242         elem_info = mlxsw_pci_queue_elem_info_consumer_get(q);
 243         elem = elem_info->elem;
 244         owner_bit = get_elem_owner_func(elem);
 245         if (mlxsw_pci_elem_hw_owned(q, owner_bit))
 246                 return NULL;
 247         q->consumer_counter++;
 248         rmb(); /* make sure we read owned bit before the rest of elem */
 249         return elem;
 250 }
 251
 252 static struct mlxsw_pci_queue_type_group *
 253 mlxsw_pci_queue_type_group_get(struct mlxsw_pci *mlxsw_pci,
 254                                enum mlxsw_pci_queue_type q_type)
 255 {
 256         return &mlxsw_pci->queues[q_type];
 257 }
 258
 259 static u8 __mlxsw_pci_queue_count(struct mlxsw_pci *mlxsw_pci,
 260                                   enum mlxsw_pci_queue_type q_type)
 261 {
 262         struct mlxsw_pci_queue_type_group *queue_group;
 263
 264         queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_type);
 265         return queue_group->count;
 266 }
 267
 268 static u8 mlxsw_pci_sdq_count(struct mlxsw_pci *mlxsw_pci)
 269 {
 270         return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_SDQ);
 271 }
 272
 273 static u8 mlxsw_pci_rdq_count(struct mlxsw_pci *mlxsw_pci)
 274 {
 275         return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_RDQ);
 276 }
 277
 278 static u8 mlxsw_pci_cq_count(struct mlxsw_pci *mlxsw_pci)
 279 {
 280         return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_CQ);
 281 }
 282
 283 static u8 mlxsw_pci_eq_count(struct mlxsw_pci *mlxsw_pci)
 284 {
 285         return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_EQ);
 286 }
 287
 288 static struct mlxsw_pci_queue *
 289 __mlxsw_pci_queue_get(struct mlxsw_pci *mlxsw_pci,
 290                       enum mlxsw_pci_queue_type q_type, u8 q_num)
 291 {
 292         return &mlxsw_pci->queues[q_type].q[q_num];
 293 }
 294
 295 static struct mlxsw_pci_queue *mlxsw_pci_sdq_get(struct mlxsw_pci *mlxsw_pci,
 296                                                  u8 q_num)
 297 {
 298         return __mlxsw_pci_queue_get(mlxsw_pci,
 299                                      MLXSW_PCI_QUEUE_TYPE_SDQ, q_num);
 300 }
 301
 302 static struct mlxsw_pci_queue *mlxsw_pci_rdq_get(struct mlxsw_pci *mlxsw_pci,
 303                                                  u8 q_num)
 304 {
 305         return __mlxsw_pci_queue_get(mlxsw_pci,
 306                                      MLXSW_PCI_QUEUE_TYPE_RDQ, q_num);
 307 }
 308
 309 static struct mlxsw_pci_queue *mlxsw_pci_cq_get(struct mlxsw_pci *mlxsw_pci,
 310                                                 u8 q_num)
 311 {
 312         return __mlxsw_pci_queue_get(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_CQ, q_num);
 313 }
 314
 315 static struct mlxsw_pci_queue *mlxsw_pci_eq_get(struct mlxsw_pci *mlxsw_pci,
 316                                                 u8 q_num)
 317 {
 318         return __mlxsw_pci_queue_get(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_EQ, q_num);
 319 }
 320
 321 static void __mlxsw_pci_queue_doorbell_set(struct mlxsw_pci *mlxsw_pci,
 322                                            struct mlxsw_pci_queue *q,
 323                                            u16 val)
 324 {
 325         mlxsw_pci_write32(mlxsw_pci,
 326                           DOORBELL(mlxsw_pci->doorbell_offset,
 327                                    mlxsw_pci_doorbell_type_offset[q->type],
 328                                    q->num), val);
 329 }
 330
 331 static void __mlxsw_pci_queue_doorbell_arm_set(struct mlxsw_pci *mlxsw_pci,
 332                                                struct mlxsw_pci_queue *q,
 333                                                u16 val)
 334 {
 335         mlxsw_pci_write32(mlxsw_pci,
 336                           DOORBELL(mlxsw_pci->doorbell_offset,
 337                                    mlxsw_pci_doorbell_arm_type_offset[q->type],
 338                                    q->num), val);
 339 }
 340
 341 static void mlxsw_pci_queue_doorbell_producer_ring(struct mlxsw_pci *mlxsw_pci,
 342                                                    struct mlxsw_pci_queue *q)
 343 {
 344         wmb(); /* ensure all writes are done before we ring a bell */
 345         __mlxsw_pci_queue_doorbell_set(mlxsw_pci, q, q->producer_counter);
 346 }
 347
 348 static void mlxsw_pci_queue_doorbell_consumer_ring(struct mlxsw_pci *mlxsw_pci,
 349                                                    struct mlxsw_pci_queue *q)
 350 {
 351         wmb(); /* ensure all writes are done before we ring a bell */
 352         __mlxsw_pci_queue_doorbell_set(mlxsw_pci, q,
 353                                        q->consumer_counter + q->count);
 354 }
 355
 356 static void
 357 mlxsw_pci_queue_doorbell_arm_consumer_ring(struct mlxsw_pci *mlxsw_pci,
 358                                            struct mlxsw_pci_queue *q)
 359 {
 360         wmb(); /* ensure all writes are done before we ring a bell */
 361         __mlxsw_pci_queue_doorbell_arm_set(mlxsw_pci, q, q->consumer_counter);
 362 }
 363
 364 static dma_addr_t __mlxsw_pci_queue_page_get(struct mlxsw_pci_queue *q,
 365                                              int page_index)
 366 {
 367         return q->mem_item.mapaddr + MLXSW_PCI_PAGE_SIZE * page_index;
 368 }
 369
 370 static int mlxsw_pci_sdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
 371                               struct mlxsw_pci_queue *q)
 372 {
 373         int i;
 374         int err;
 375
 376         q->producer_counter = 0;
 377         q->consumer_counter = 0;
 378
 379         /* Set CQ of same number of this SDQ. */
 380         mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, q->num);
 381         mlxsw_cmd_mbox_sw2hw_dq_sdq_tclass_set(mbox, 7);
 382         mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3); /* 8 pages */
 383         for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
 384                 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
 385
 386                 mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr);
 387         }
 388
 389         err = mlxsw_cmd_sw2hw_sdq(mlxsw_pci->core, mbox, q->num);
 390         if (err)
 391                 return err;
 392         mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
 393         return 0;
 394 }
 395
 396 static void mlxsw_pci_sdq_fini(struct mlxsw_pci *mlxsw_pci,
 397                                struct mlxsw_pci_queue *q)
 398 {
 399         mlxsw_cmd_hw2sw_sdq(mlxsw_pci->core, q->num);
 400 }
 401
 402 static int mlxsw_pci_sdq_dbg_read(struct seq_file *file, void *data)
 403 {
 404         struct mlxsw_pci *mlxsw_pci = dev_get_drvdata(file->private);
 405         struct mlxsw_pci_queue *q;
 406         int i;
 407         static const char hdr[] =
 408                 "NUM PROD_COUNT CONS_COUNT COUNT\n";
 409
 410         seq_printf(file, hdr);
 411         for (i = 0; i < mlxsw_pci_sdq_count(mlxsw_pci); i++) {
 412                 q = mlxsw_pci_sdq_get(mlxsw_pci, i);
 413                 spin_lock_bh(&q->lock);
 414                 seq_printf(file, "%3d %10d %10d %5d\n",
 415                            i, q->producer_counter, q->consumer_counter,
 416                            q->count);
 417                 spin_unlock_bh(&q->lock);
 418         }
 419         return 0;
 420 }
 421
 422 static int mlxsw_pci_wqe_frag_map(struct mlxsw_pci *mlxsw_pci, char *wqe,
 423                                   int index, char *frag_data, size_t frag_len,
 424                                   int direction)
 425 {
 426         struct pci_dev *pdev = mlxsw_pci->pdev;
 427         dma_addr_t mapaddr;
 428
 429         mapaddr = pci_map_single(pdev, frag_data, frag_len, direction);
 430         if (unlikely(pci_dma_mapping_error(pdev, mapaddr))) {
 431                 if (net_ratelimit())
 432                         dev_err(&pdev->dev, "failed to dma map tx frag\n");
 433                 return -EIO;
 434         }
 435         mlxsw_pci_wqe_address_set(wqe, index, mapaddr);
 436         mlxsw_pci_wqe_byte_count_set(wqe, index, frag_len);
 437         return 0;
 438 }
 439
 440 static void mlxsw_pci_wqe_frag_unmap(struct mlxsw_pci *mlxsw_pci, char *wqe,
 441                                      int index, int direction)
 442 {
 443         struct pci_dev *pdev = mlxsw_pci->pdev;
 444         size_t frag_len = mlxsw_pci_wqe_byte_count_get(wqe, index);
 445         dma_addr_t mapaddr = mlxsw_pci_wqe_address_get(wqe, index);
 446
 447         if (!frag_len)
 448                 return;
 449         pci_unmap_single(pdev, mapaddr, frag_len, direction);
 450 }
 451
 452 static int mlxsw_pci_rdq_skb_alloc(struct mlxsw_pci *mlxsw_pci,
 453                                    struct mlxsw_pci_queue_elem_info *elem_info)
 454 {
 455         size_t buf_len = MLXSW_PORT_MAX_MTU;
 456         char *wqe = elem_info->elem;
 457         struct sk_buff *skb;
 458         int err;
 459
 460         elem_info->u.rdq.skb = NULL;
 461         skb = netdev_alloc_skb_ip_align(NULL, buf_len);
 462         if (!skb)
 463                 return -ENOMEM;
 464
 465         /* Assume that wqe was previously zeroed. */
 466
 467         err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, 0, skb->data,
 468                                      buf_len, DMA_FROM_DEVICE);
 469         if (err)
 470                 goto err_frag_map;
 471
 472         elem_info->u.rdq.skb = skb;
 473         return 0;
 474
 475 err_frag_map:
 476         dev_kfree_skb_any(skb);
 477         return err;
 478 }
 479
 480 static void mlxsw_pci_rdq_skb_free(struct mlxsw_pci *mlxsw_pci,
 481                                    struct mlxsw_pci_queue_elem_info *elem_info)
 482 {
 483         struct sk_buff *skb;
 484         char *wqe;
 485
 486         skb = elem_info->u.rdq.skb;
 487         wqe = elem_info->elem;
 488
 489         mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, 0, DMA_FROM_DEVICE);
 490         dev_kfree_skb_any(skb);
 491 }
 492
 493 static int mlxsw_pci_rdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
 494                               struct mlxsw_pci_queue *q)
 495 {
 496         struct mlxsw_pci_queue_elem_info *elem_info;
 497         int i;
 498         int err;
 499
 500         q->producer_counter = 0;
 501         q->consumer_counter = 0;
 502
 503         /* Set CQ of same number of this RDQ with base
 504          * above MLXSW_PCI_SDQS_MAX as the lower ones are assigned to SDQs.
 505          */
 506         mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, q->num + MLXSW_PCI_SDQS_COUNT);
 507         mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3); /* 8 pages */
 508         for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
 509                 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
 510
 511                 mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr);
 512         }
 513
 514         err = mlxsw_cmd_sw2hw_rdq(mlxsw_pci->core, mbox, q->num);
 515         if (err)
 516                 return err;
 517
 518         mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
 519
 520         for (i = 0; i < q->count; i++) {
 521                 elem_info = mlxsw_pci_queue_elem_info_producer_get(q);
 522                 BUG_ON(!elem_info);
 523                 err = mlxsw_pci_rdq_skb_alloc(mlxsw_pci, elem_info);
 524                 if (err)
 525                         goto rollback;
 526                 /* Everything is set up, ring doorbell to pass elem to HW */
 527                 q->producer_counter++;
 528                 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
 529         }
 530
 531         return 0;
 532
 533 rollback:
 534         for (i--; i >= 0; i--) {
 535                 elem_info = mlxsw_pci_queue_elem_info_get(q, i);
 536                 mlxsw_pci_rdq_skb_free(mlxsw_pci, elem_info);
 537         }
 538         mlxsw_cmd_hw2sw_rdq(mlxsw_pci->core, q->num);
 539
 540         return err;
 541 }
 542
 543 static void mlxsw_pci_rdq_fini(struct mlxsw_pci *mlxsw_pci,
 544                                struct mlxsw_pci_queue *q)
 545 {
 546         struct mlxsw_pci_queue_elem_info *elem_info;
 547         int i;
 548
 549         mlxsw_cmd_hw2sw_rdq(mlxsw_pci->core, q->num);
 550         for (i = 0; i < q->count; i++) {
 551                 elem_info = mlxsw_pci_queue_elem_info_get(q, i);
 552                 mlxsw_pci_rdq_skb_free(mlxsw_pci, elem_info);
 553         }
 554 }
 555
 556 static int mlxsw_pci_rdq_dbg_read(struct seq_file *file, void *data)
 557 {
 558         struct mlxsw_pci *mlxsw_pci = dev_get_drvdata(file->private);
 559         struct mlxsw_pci_queue *q;
 560         int i;
 561         static const char hdr[] =
 562                 "NUM PROD_COUNT CONS_COUNT COUNT\n";
 563
 564         seq_printf(file, hdr);
 565         for (i = 0; i < mlxsw_pci_rdq_count(mlxsw_pci); i++) {
 566                 q = mlxsw_pci_rdq_get(mlxsw_pci, i);
 567                 spin_lock_bh(&q->lock);
 568                 seq_printf(file, "%3d %10d %10d %5d\n",
 569                            i, q->producer_counter, q->consumer_counter,
 570                            q->count);
 571                 spin_unlock_bh(&q->lock);
 572         }
 573         return 0;
 574 }
 575
 576 static int mlxsw_pci_cq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
 577                              struct mlxsw_pci_queue *q)
 578 {
 579         int i;
 580         int err;
 581
 582         q->consumer_counter = 0;
 583
 584         for (i = 0; i < q->count; i++) {
 585                 char *elem = mlxsw_pci_queue_elem_get(q, i);
 586
 587                 mlxsw_pci_cqe_owner_set(elem, 1);
 588         }
 589
 590         mlxsw_cmd_mbox_sw2hw_cq_cv_set(mbox, 0); /* CQE ver 0 */
 591         mlxsw_cmd_mbox_sw2hw_cq_c_eqn_set(mbox, MLXSW_PCI_EQ_COMP_NUM);
 592         mlxsw_cmd_mbox_sw2hw_cq_oi_set(mbox, 0);
 593         mlxsw_cmd_mbox_sw2hw_cq_st_set(mbox, 0);
 594         mlxsw_cmd_mbox_sw2hw_cq_log_cq_size_set(mbox, ilog2(q->count));
 595         for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
 596                 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
 597
 598                 mlxsw_cmd_mbox_sw2hw_cq_pa_set(mbox, i, mapaddr);
 599         }
 600         err = mlxsw_cmd_sw2hw_cq(mlxsw_pci->core, mbox, q->num);
 601         if (err)
 602                 return err;
 603         mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
 604         mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
 605         return 0;
 606 }
 607
 608 static void mlxsw_pci_cq_fini(struct mlxsw_pci *mlxsw_pci,
 609                               struct mlxsw_pci_queue *q)
 610 {
 611         mlxsw_cmd_hw2sw_cq(mlxsw_pci->core, q->num);
 612 }
 613
 614 static int mlxsw_pci_cq_dbg_read(struct seq_file *file, void *data)
 615 {
 616         struct mlxsw_pci *mlxsw_pci = dev_get_drvdata(file->private);
 617
 618         struct mlxsw_pci_queue *q;
 619         int i;
 620         static const char hdr[] =
 621                 "NUM CONS_INDEX  SDQ_COUNT  RDQ_COUNT COUNT\n";
 622
 623         seq_printf(file, hdr);
 624         for (i = 0; i < mlxsw_pci_cq_count(mlxsw_pci); i++) {
 625                 q = mlxsw_pci_cq_get(mlxsw_pci, i);
 626                 spin_lock_bh(&q->lock);
 627                 seq_printf(file, "%3d %10d %10d %10d %5d\n",
 628                            i, q->consumer_counter, q->u.cq.comp_sdq_count,
 629                            q->u.cq.comp_rdq_count, q->count);
 630                 spin_unlock_bh(&q->lock);
 631         }
 632         return 0;
 633 }
 634
 635 static void mlxsw_pci_cqe_sdq_handle(struct mlxsw_pci *mlxsw_pci,
 636                                      struct mlxsw_pci_queue *q,
 637                                      u16 consumer_counter_limit,
 638                                      char *cqe)
 639 {
 640         struct pci_dev *pdev = mlxsw_pci->pdev;
 641         struct mlxsw_pci_queue_elem_info *elem_info;
 642         char *wqe;
 643         struct sk_buff *skb;
 644         int i;
 645
 646         spin_lock(&q->lock);
 647         elem_info = mlxsw_pci_queue_elem_info_consumer_get(q);
 648         skb = elem_info->u.sdq.skb;
 649         wqe = elem_info->elem;
 650         for (i = 0; i < MLXSW_PCI_WQE_SG_ENTRIES; i++)
 651                 mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, i, DMA_TO_DEVICE);
 652         dev_kfree_skb_any(skb);
 653         elem_info->u.sdq.skb = NULL;
 654
 655         if (q->consumer_counter++ != consumer_counter_limit)
 656                 dev_dbg_ratelimited(&pdev->dev, "Consumer counter does not match limit in SDQ\n");
 657         spin_unlock(&q->lock);
 658 }
 659
 660 static void mlxsw_pci_cqe_rdq_handle(struct mlxsw_pci *mlxsw_pci,
 661                                      struct mlxsw_pci_queue *q,
 662                                      u16 consumer_counter_limit,
 663                                      char *cqe)
 664 {
 665         struct pci_dev *pdev = mlxsw_pci->pdev;
 666         struct mlxsw_pci_queue_elem_info *elem_info;
 667         char *wqe;
 668         struct sk_buff *skb;
 669         struct mlxsw_rx_info rx_info;
 670         int err;
 671
 672         elem_info = mlxsw_pci_queue_elem_info_consumer_get(q);
 673         skb = elem_info->u.sdq.skb;
 674         if (!skb)
 675                 return;
 676         wqe = elem_info->elem;
 677         mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, 0, DMA_FROM_DEVICE);
 678
 679         if (q->consumer_counter++ != consumer_counter_limit)
 680                 dev_dbg_ratelimited(&pdev->dev, "Consumer counter does not match limit in RDQ\n");
 681
 682         /* We do not support lag now */
 683         if (mlxsw_pci_cqe_lag_get(cqe))
 684                 goto drop;
 685
 686         rx_info.sys_port = mlxsw_pci_cqe_system_port_get(cqe);
 687         rx_info.trap_id = mlxsw_pci_cqe_trap_id_get(cqe);
 688
 689         skb_put(skb, mlxsw_pci_cqe_byte_count_get(cqe));
 690         mlxsw_core_skb_receive(mlxsw_pci->core, skb, &rx_info);
 691
 692 put_new_skb:
 693         memset(wqe, 0, q->elem_size);
 694         err = mlxsw_pci_rdq_skb_alloc(mlxsw_pci, elem_info);
 695         if (err && net_ratelimit())
 696                 dev_dbg(&pdev->dev, "Failed to alloc skb for RDQ\n");
 697         /* Everything is set up, ring doorbell to pass elem to HW */
 698         q->producer_counter++;
 699         mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
 700         return;
 701
 702 drop:
 703         dev_kfree_skb_any(skb);
 704         goto put_new_skb;
 705 }
 706
 707 static char *mlxsw_pci_cq_sw_cqe_get(struct mlxsw_pci_queue *q)
 708 {
 709         return mlxsw_pci_queue_sw_elem_get(q, mlxsw_pci_cqe_owner_get);
 710 }
 711
 712 static void mlxsw_pci_cq_tasklet(unsigned long data)
 713 {
 714         struct mlxsw_pci_queue *q = (struct mlxsw_pci_queue *) data;
 715         struct mlxsw_pci *mlxsw_pci = q->pci;
 716         char *cqe;
 717         int items = 0;
 718         int credits = q->count >> 1;
 719
 720         while ((cqe = mlxsw_pci_cq_sw_cqe_get(q))) {
 721                 u16 wqe_counter = mlxsw_pci_cqe_wqe_counter_get(cqe);
 722                 u8 sendq = mlxsw_pci_cqe_sr_get(cqe);
 723                 u8 dqn = mlxsw_pci_cqe_dqn_get(cqe);
 724
 725                 if (sendq) {
 726                         struct mlxsw_pci_queue *sdq;
 727
 728                         sdq = mlxsw_pci_sdq_get(mlxsw_pci, dqn);
 729                         mlxsw_pci_cqe_sdq_handle(mlxsw_pci, sdq,
 730                                                  wqe_counter, cqe);
 731                         q->u.cq.comp_sdq_count++;
 732                 } else {
 733                         struct mlxsw_pci_queue *rdq;
 734
 735                         rdq = mlxsw_pci_rdq_get(mlxsw_pci, dqn);
 736                         mlxsw_pci_cqe_rdq_handle(mlxsw_pci, rdq,
 737                                                  wqe_counter, cqe);
 738                         q->u.cq.comp_rdq_count++;
 739                 }
 740                 if (++items == credits)
 741                         break;
 742         }
 743         if (items) {
 744                 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
 745                 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
 746         }
 747 }
 748
 749 static int mlxsw_pci_eq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
 750                              struct mlxsw_pci_queue *q)
 751 {
 752         int i;
 753         int err;
 754
 755         q->consumer_counter = 0;
 756
 757         for (i = 0; i < q->count; i++) {
 758                 char *elem = mlxsw_pci_queue_elem_get(q, i);
 759
 760                 mlxsw_pci_eqe_owner_set(elem, 1);
 761         }
 762
 763         mlxsw_cmd_mbox_sw2hw_eq_int_msix_set(mbox, 1); /* MSI-X used */
 764         mlxsw_cmd_mbox_sw2hw_eq_oi_set(mbox, 0);
 765         mlxsw_cmd_mbox_sw2hw_eq_st_set(mbox, 1); /* armed */
 766         mlxsw_cmd_mbox_sw2hw_eq_log_eq_size_set(mbox, ilog2(q->count));
 767         for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
 768                 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
 769
 770                 mlxsw_cmd_mbox_sw2hw_eq_pa_set(mbox, i, mapaddr);
 771         }
 772         err = mlxsw_cmd_sw2hw_eq(mlxsw_pci->core, mbox, q->num);
 773         if (err)
 774                 return err;
 775         mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
 776         mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
 777         return 0;
 778 }
 779
 780 static void mlxsw_pci_eq_fini(struct mlxsw_pci *mlxsw_pci,
 781                               struct mlxsw_pci_queue *q)
 782 {
 783         mlxsw_cmd_hw2sw_eq(mlxsw_pci->core, q->num);
 784 }
 785
 786 static int mlxsw_pci_eq_dbg_read(struct seq_file *file, void *data)
 787 {
 788         struct mlxsw_pci *mlxsw_pci = dev_get_drvdata(file->private);
 789         struct mlxsw_pci_queue *q;
 790         int i;
 791         static const char hdr[] =
 792                 "NUM CONS_COUNT     EV_CMD    EV_COMP   EV_OTHER COUNT\n";
 793
 794         seq_printf(file, hdr);
 795         for (i = 0; i < mlxsw_pci_eq_count(mlxsw_pci); i++) {
 796                 q = mlxsw_pci_eq_get(mlxsw_pci, i);
 797                 spin_lock_bh(&q->lock);
 798                 seq_printf(file, "%3d %10d %10d %10d %10d %5d\n",
 799                            i, q->consumer_counter, q->u.eq.ev_cmd_count,
 800                            q->u.eq.ev_comp_count, q->u.eq.ev_other_count,
 801                            q->count);
 802                 spin_unlock_bh(&q->lock);
 803         }
 804         return 0;
 805 }
 806
 807 static void mlxsw_pci_eq_cmd_event(struct mlxsw_pci *mlxsw_pci, char *eqe)
 808 {
 809         mlxsw_pci->cmd.comp.status = mlxsw_pci_eqe_cmd_status_get(eqe);
 810         mlxsw_pci->cmd.comp.out_param =
 811                 ((u64) mlxsw_pci_eqe_cmd_out_param_h_get(eqe)) << 32 |
 812                 mlxsw_pci_eqe_cmd_out_param_l_get(eqe);
 813         mlxsw_pci->cmd.wait_done = true;
 814         wake_up(&mlxsw_pci->cmd.wait);
 815 }
 816
 817 static char *mlxsw_pci_eq_sw_eqe_get(struct mlxsw_pci_queue *q)
 818 {
 819         return mlxsw_pci_queue_sw_elem_get(q, mlxsw_pci_eqe_owner_get);
 820 }
 821
 822 static void mlxsw_pci_eq_tasklet(unsigned long data)
 823 {
 824         struct mlxsw_pci_queue *q = (struct mlxsw_pci_queue *) data;
 825         struct mlxsw_pci *mlxsw_pci = q->pci;
 826         unsigned long active_cqns[BITS_TO_LONGS(MLXSW_PCI_CQS_COUNT)];
 827         char *eqe;
 828         u8 cqn;
 829         bool cq_handle = false;
 830         int items = 0;
 831         int credits = q->count >> 1;
 832
 833         memset(&active_cqns, 0, sizeof(active_cqns));
 834
 835         while ((eqe = mlxsw_pci_eq_sw_eqe_get(q))) {
 836                 u8 event_type = mlxsw_pci_eqe_event_type_get(eqe);
 837
 838                 switch (event_type) {
 839                 case MLXSW_PCI_EQE_EVENT_TYPE_CMD:
 840                         mlxsw_pci_eq_cmd_event(mlxsw_pci, eqe);
 841                         q->u.eq.ev_cmd_count++;
 842                         break;
 843                 case MLXSW_PCI_EQE_EVENT_TYPE_COMP:
 844                         cqn = mlxsw_pci_eqe_cqn_get(eqe);
 845                         set_bit(cqn, active_cqns);
 846                         cq_handle = true;
 847                         q->u.eq.ev_comp_count++;
 848                         break;
 849                 default:
 850                         q->u.eq.ev_other_count++;
 851                 }
 852                 if (++items == credits)
 853                         break;
 854         }
 855         if (items) {
 856                 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
 857                 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
 858         }
 859
 860         if (!cq_handle)
 861                 return;
 862         for_each_set_bit(cqn, active_cqns, MLXSW_PCI_CQS_COUNT) {
 863                 q = mlxsw_pci_cq_get(mlxsw_pci, cqn);
 864                 mlxsw_pci_queue_tasklet_schedule(q);
 865         }
 866 }
 867
 868 struct mlxsw_pci_queue_ops {
 869         const char *name;
 870         enum mlxsw_pci_queue_type type;
 871         int (*init)(struct mlxsw_pci *mlxsw_pci, char *mbox,
 872                     struct mlxsw_pci_queue *q);
 873         void (*fini)(struct mlxsw_pci *mlxsw_pci,
 874                      struct mlxsw_pci_queue *q);
 875         void (*tasklet)(unsigned long data);
 876         int (*dbg_read)(struct seq_file *s, void *data);
 877         u16 elem_count;
 878         u8 elem_size;
 879 };
 880
 881 static const struct mlxsw_pci_queue_ops mlxsw_pci_sdq_ops = {
 882         .type           = MLXSW_PCI_QUEUE_TYPE_SDQ,
 883         .init           = mlxsw_pci_sdq_init,
 884         .fini           = mlxsw_pci_sdq_fini,
 885         .dbg_read       = mlxsw_pci_sdq_dbg_read,
 886         .elem_count     = MLXSW_PCI_WQE_COUNT,
 887         .elem_size      = MLXSW_PCI_WQE_SIZE,
 888 };
 889
 890 static const struct mlxsw_pci_queue_ops mlxsw_pci_rdq_ops = {
 891         .type           = MLXSW_PCI_QUEUE_TYPE_RDQ,
 892         .init           = mlxsw_pci_rdq_init,
 893         .fini           = mlxsw_pci_rdq_fini,
 894         .dbg_read       = mlxsw_pci_rdq_dbg_read,
 895         .elem_count     = MLXSW_PCI_WQE_COUNT,
 896         .elem_size      = MLXSW_PCI_WQE_SIZE
 897 };
 898
 899 static const struct mlxsw_pci_queue_ops mlxsw_pci_cq_ops = {
 900         .type           = MLXSW_PCI_QUEUE_TYPE_CQ,
 901         .init           = mlxsw_pci_cq_init,
 902         .fini           = mlxsw_pci_cq_fini,
 903         .tasklet        = mlxsw_pci_cq_tasklet,
 904         .dbg_read       = mlxsw_pci_cq_dbg_read,
 905         .elem_count     = MLXSW_PCI_CQE_COUNT,
 906         .elem_size      = MLXSW_PCI_CQE_SIZE
 907 };
 908
 909 static const struct mlxsw_pci_queue_ops mlxsw_pci_eq_ops = {
 910         .type           = MLXSW_PCI_QUEUE_TYPE_EQ,
 911         .init           = mlxsw_pci_eq_init,
 912         .fini           = mlxsw_pci_eq_fini,
 913         .tasklet        = mlxsw_pci_eq_tasklet,
 914         .dbg_read       = mlxsw_pci_eq_dbg_read,
 915         .elem_count     = MLXSW_PCI_EQE_COUNT,
 916         .elem_size      = MLXSW_PCI_EQE_SIZE
 917 };
 918
 919 static int mlxsw_pci_queue_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
 920                                 const struct mlxsw_pci_queue_ops *q_ops,
 921                                 struct mlxsw_pci_queue *q, u8 q_num)
 922 {
 923         struct mlxsw_pci_mem_item *mem_item = &q->mem_item;
 924         int i;
 925         int err;
 926
 927         spin_lock_init(&q->lock);
 928         q->num = q_num;
 929         q->count = q_ops->elem_count;
 930         q->elem_size = q_ops->elem_size;
 931         q->type = q_ops->type;
 932         q->pci = mlxsw_pci;
 933
 934         if (q_ops->tasklet)
 935                 tasklet_init(&q->tasklet, q_ops->tasklet, (unsigned long) q);
 936
 937         mem_item->size = MLXSW_PCI_AQ_SIZE;
 938         mem_item->buf = pci_alloc_consistent(mlxsw_pci->pdev,
 939                                              mem_item->size,
 940                                              &mem_item->mapaddr);
 941         if (!mem_item->buf)
 942                 return -ENOMEM;
 943         memset(mem_item->buf, 0, mem_item->size);
 944
 945         q->elem_info = kcalloc(q->count, sizeof(*q->elem_info), GFP_KERNEL);
 946         if (!q->elem_info) {
 947                 err = -ENOMEM;
 948                 goto err_elem_info_alloc;
 949         }
 950
 951         /* Initialize dma mapped elements info elem_info for
 952          * future easy access.
 953          */
 954         for (i = 0; i < q->count; i++) {
 955                 struct mlxsw_pci_queue_elem_info *elem_info;
 956
 957                 elem_info = mlxsw_pci_queue_elem_info_get(q, i);
 958                 elem_info->elem =
 959                         __mlxsw_pci_queue_elem_get(q, q_ops->elem_size, i);
 960         }
 961
 962         mlxsw_cmd_mbox_zero(mbox);
 963         err = q_ops->init(mlxsw_pci, mbox, q);
 964         if (err)
 965                 goto err_q_ops_init;
 966         return 0;
 967
 968 err_q_ops_init:
 969         kfree(q->elem_info);
 970 err_elem_info_alloc:
 971         pci_free_consistent(mlxsw_pci->pdev, mem_item->size,
 972                             mem_item->buf, mem_item->mapaddr);
 973         return err;
 974 }
 975
 976 static void mlxsw_pci_queue_fini(struct mlxsw_pci *mlxsw_pci,
 977                                  const struct mlxsw_pci_queue_ops *q_ops,
 978                                  struct mlxsw_pci_queue *q)
 979 {
 980         struct mlxsw_pci_mem_item *mem_item = &q->mem_item;
 981
 982         q_ops->fini(mlxsw_pci, q);
 983         kfree(q->elem_info);
 984         pci_free_consistent(mlxsw_pci->pdev, mem_item->size,
 985                             mem_item->buf, mem_item->mapaddr);
 986 }
 987
 988 static int mlxsw_pci_queue_group_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
 989                                       const struct mlxsw_pci_queue_ops *q_ops,
 990                                       u8 num_qs)
 991 {
 992         struct pci_dev *pdev = mlxsw_pci->pdev;
 993         struct mlxsw_pci_queue_type_group *queue_group;
 994         char tmp[16];
 995         int i;
 996         int err;
 997
 998         queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_ops->type);
 999         queue_group->q = kcalloc(num_qs, sizeof(*queue_group->q), GFP_KERNEL);
1000         if (!queue_group->q)
1001                 return -ENOMEM;
1002
1003         for (i = 0; i < num_qs; i++) {
1004                 err = mlxsw_pci_queue_init(mlxsw_pci, mbox, q_ops,
1005                                            &queue_group->q[i], i);
1006                 if (err)
1007                         goto err_queue_init;
1008         }
1009         queue_group->count = num_qs;
1010
1011         sprintf(tmp, "%s_stats", mlxsw_pci_queue_type_str(q_ops->type));
1012         debugfs_create_devm_seqfile(&pdev->dev, tmp, mlxsw_pci->dbg_dir,
1013                                     q_ops->dbg_read);
1014
1015         return 0;
1016
1017 err_queue_init:
1018         for (i--; i >= 0; i--)
1019                 mlxsw_pci_queue_fini(mlxsw_pci, q_ops, &queue_group->q[i]);
1020         kfree(queue_group->q);
1021         return err;
1022 }
1023
1024 static void mlxsw_pci_queue_group_fini(struct mlxsw_pci *mlxsw_pci,
1025                                        const struct mlxsw_pci_queue_ops *q_ops)
1026 {
1027         struct mlxsw_pci_queue_type_group *queue_group;
1028         int i;
1029
1030         queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_ops->type);
1031         for (i = 0; i < queue_group->count; i++)
1032                 mlxsw_pci_queue_fini(mlxsw_pci, q_ops, &queue_group->q[i]);
1033         kfree(queue_group->q);
1034 }
1035
1036 static int mlxsw_pci_aqs_init(struct mlxsw_pci *mlxsw_pci, char *mbox)
1037 {
1038         struct pci_dev *pdev = mlxsw_pci->pdev;
1039         u8 num_sdqs;
1040         u8 sdq_log2sz;
1041         u8 num_rdqs;
1042         u8 rdq_log2sz;
1043         u8 num_cqs;
1044         u8 cq_log2sz;
1045         u8 num_eqs;
1046         u8 eq_log2sz;
1047         int err;
1048
1049         mlxsw_cmd_mbox_zero(mbox);
1050         err = mlxsw_cmd_query_aq_cap(mlxsw_pci->core, mbox);
1051         if (err)
1052                 return err;
1053
1054         num_sdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_sdqs_get(mbox);
1055         sdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_sdq_sz_get(mbox);
1056         num_rdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_rdqs_get(mbox);
1057         rdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_rdq_sz_get(mbox);
1058         num_cqs = mlxsw_cmd_mbox_query_aq_cap_max_num_cqs_get(mbox);
1059         cq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_cq_sz_get(mbox);
1060         num_eqs = mlxsw_cmd_mbox_query_aq_cap_max_num_eqs_get(mbox);
1061         eq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_eq_sz_get(mbox);
1062
1063         if ((num_sdqs != MLXSW_PCI_SDQS_COUNT) ||
1064             (num_rdqs != MLXSW_PCI_RDQS_COUNT) ||
1065             (num_cqs != MLXSW_PCI_CQS_COUNT) ||
1066             (num_eqs != MLXSW_PCI_EQS_COUNT)) {
1067                 dev_err(&pdev->dev, "Unsupported number of queues\n");
1068                 return -EINVAL;
1069         }
1070
1071         if ((1 << sdq_log2sz != MLXSW_PCI_WQE_COUNT) ||
1072             (1 << rdq_log2sz != MLXSW_PCI_WQE_COUNT) ||
1073             (1 << cq_log2sz != MLXSW_PCI_CQE_COUNT) ||
1074             (1 << eq_log2sz != MLXSW_PCI_EQE_COUNT)) {
1075                 dev_err(&pdev->dev, "Unsupported number of async queue descriptors\n");
1076                 return -EINVAL;
1077         }
1078
1079         err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_eq_ops,
1080                                          num_eqs);
1081         if (err) {
1082                 dev_err(&pdev->dev, "Failed to initialize event queues\n");
1083                 return err;
1084         }
1085
1086         err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_cq_ops,
1087                                          num_cqs);
1088         if (err) {
1089                 dev_err(&pdev->dev, "Failed to initialize completion queues\n");
1090                 goto err_cqs_init;
1091         }
1092
1093         err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_sdq_ops,
1094                                          num_sdqs);
1095         if (err) {
1096                 dev_err(&pdev->dev, "Failed to initialize send descriptor queues\n");
1097                 goto err_sdqs_init;
1098         }
1099
1100         err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_rdq_ops,
1101                                          num_rdqs);
1102         if (err) {
1103                 dev_err(&pdev->dev, "Failed to initialize receive descriptor queues\n");
1104                 goto err_rdqs_init;
1105         }
1106
1107         /* We have to poll in command interface until queues are initialized */
1108         mlxsw_pci->cmd.nopoll = true;
1109         return 0;
1110
1111 err_rdqs_init:
1112         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_sdq_ops);
1113 err_sdqs_init:
1114         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_cq_ops);
1115 err_cqs_init:
1116         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_eq_ops);
1117         return err;
1118 }
1119
1120 static void mlxsw_pci_aqs_fini(struct mlxsw_pci *mlxsw_pci)
1121 {
1122         mlxsw_pci->cmd.nopoll = false;
1123         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_rdq_ops);
1124         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_sdq_ops);
1125         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_cq_ops);
1126         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_eq_ops);
1127 }
1128
1129 static void
1130 mlxsw_pci_config_profile_swid_config(struct mlxsw_pci *mlxsw_pci,
1131                                      char *mbox, int index,
1132                                      const struct mlxsw_swid_config *swid)
1133 {
1134         u8 mask = 0;
1135
1136         if (swid->used_type) {
1137                 mlxsw_cmd_mbox_config_profile_swid_config_type_set(
1138                         mbox, index, swid->type);
1139                 mask |= 1;
1140         }
1141         if (swid->used_properties) {
1142                 mlxsw_cmd_mbox_config_profile_swid_config_properties_set(
1143                         mbox, index, swid->properties);
1144                 mask |= 2;
1145         }
1146         mlxsw_cmd_mbox_config_profile_swid_config_mask_set(mbox, index, mask);
1147 }
1148
1149 static int mlxsw_pci_config_profile(struct mlxsw_pci *mlxsw_pci, char *mbox,
1150                                     const struct mlxsw_config_profile *profile)
1151 {
1152         int i;
1153
1154         mlxsw_cmd_mbox_zero(mbox);
1155
1156         if (profile->used_max_vepa_channels) {
1157                 mlxsw_cmd_mbox_config_profile_set_max_vepa_channels_set(
1158                         mbox, 1);
1159                 mlxsw_cmd_mbox_config_profile_max_vepa_channels_set(
1160                         mbox, profile->max_vepa_channels);
1161         }
1162         if (profile->used_max_lag) {
1163                 mlxsw_cmd_mbox_config_profile_set_max_lag_set(
1164                         mbox, 1);
1165                 mlxsw_cmd_mbox_config_profile_max_lag_set(
1166                         mbox, profile->max_lag);
1167         }
1168         if (profile->used_max_port_per_lag) {
1169                 mlxsw_cmd_mbox_config_profile_set_max_port_per_lag_set(
1170                         mbox, 1);
1171                 mlxsw_cmd_mbox_config_profile_max_port_per_lag_set(
1172                         mbox, profile->max_port_per_lag);
1173         }
1174         if (profile->used_max_mid) {
1175                 mlxsw_cmd_mbox_config_profile_set_max_mid_set(
1176                         mbox, 1);
1177                 mlxsw_cmd_mbox_config_profile_max_mid_set(
1178                         mbox, profile->max_mid);
1179         }
1180         if (profile->used_max_pgt) {
1181                 mlxsw_cmd_mbox_config_profile_set_max_pgt_set(
1182                         mbox, 1);
1183                 mlxsw_cmd_mbox_config_profile_max_pgt_set(
1184                         mbox, profile->max_pgt);
1185         }
1186         if (profile->used_max_system_port) {
1187                 mlxsw_cmd_mbox_config_profile_set_max_system_port_set(
1188                         mbox, 1);
1189                 mlxsw_cmd_mbox_config_profile_max_system_port_set(
1190                         mbox, profile->max_system_port);
1191         }
1192         if (profile->used_max_vlan_groups) {
1193                 mlxsw_cmd_mbox_config_profile_set_max_vlan_groups_set(
1194                         mbox, 1);
1195                 mlxsw_cmd_mbox_config_profile_max_vlan_groups_set(
1196                         mbox, profile->max_vlan_groups);
1197         }
1198         if (profile->used_max_regions) {
1199                 mlxsw_cmd_mbox_config_profile_set_max_regions_set(
1200                         mbox, 1);
1201                 mlxsw_cmd_mbox_config_profile_max_regions_set(
1202                         mbox, profile->max_regions);
1203         }
1204         if (profile->used_flood_tables) {
1205                 mlxsw_cmd_mbox_config_profile_set_flood_tables_set(
1206                         mbox, 1);
1207                 mlxsw_cmd_mbox_config_profile_max_flood_tables_set(
1208                         mbox, profile->max_flood_tables);
1209                 mlxsw_cmd_mbox_config_profile_max_vid_flood_tables_set(
1210                         mbox, profile->max_vid_flood_tables);
1211         }
1212         if (profile->used_flood_mode) {
1213                 mlxsw_cmd_mbox_config_profile_set_flood_mode_set(
1214                         mbox, 1);
1215                 mlxsw_cmd_mbox_config_profile_flood_mode_set(
1216                         mbox, profile->flood_mode);
1217         }
1218         if (profile->used_max_ib_mc) {
1219                 mlxsw_cmd_mbox_config_profile_set_max_ib_mc_set(
1220                         mbox, 1);
1221                 mlxsw_cmd_mbox_config_profile_max_ib_mc_set(
1222                         mbox, profile->max_ib_mc);
1223         }
1224         if (profile->used_max_pkey) {
1225                 mlxsw_cmd_mbox_config_profile_set_max_pkey_set(
1226                         mbox, 1);
1227                 mlxsw_cmd_mbox_config_profile_max_pkey_set(
1228                         mbox, profile->max_pkey);
1229         }
1230         if (profile->used_ar_sec) {
1231                 mlxsw_cmd_mbox_config_profile_set_ar_sec_set(
1232                         mbox, 1);
1233                 mlxsw_cmd_mbox_config_profile_ar_sec_set(
1234                         mbox, profile->ar_sec);
1235         }
1236         if (profile->used_adaptive_routing_group_cap) {
1237                 mlxsw_cmd_mbox_config_profile_set_adaptive_routing_group_cap_set(
1238                         mbox, 1);
1239                 mlxsw_cmd_mbox_config_profile_adaptive_routing_group_cap_set(
1240                         mbox, profile->adaptive_routing_group_cap);
1241         }
1242
1243         for (i = 0; i < MLXSW_CONFIG_PROFILE_SWID_COUNT; i++)
1244                 mlxsw_pci_config_profile_swid_config(mlxsw_pci, mbox, i,
1245                                                      &profile->swid_config[i]);
1246
1247         return mlxsw_cmd_config_profile_set(mlxsw_pci->core, mbox);
1248 }
1249
1250 static int mlxsw_pci_boardinfo(struct mlxsw_pci *mlxsw_pci, char *mbox)
1251 {
1252         struct mlxsw_bus_info *bus_info = &mlxsw_pci->bus_info;
1253         int err;
1254
1255         mlxsw_cmd_mbox_zero(mbox);
1256         err = mlxsw_cmd_boardinfo(mlxsw_pci->core, mbox);
1257         if (err)
1258                 return err;
1259         mlxsw_cmd_mbox_boardinfo_vsd_memcpy_from(mbox, bus_info->vsd);
1260         mlxsw_cmd_mbox_boardinfo_psid_memcpy_from(mbox, bus_info->psid);
1261         return 0;
1262 }
1263
1264 static int mlxsw_pci_fw_area_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
1265                                   u16 num_pages)
1266 {
1267         struct mlxsw_pci_mem_item *mem_item;
1268         int i;
1269         int err;
1270
1271         mlxsw_pci->fw_area.items = kcalloc(num_pages, sizeof(*mem_item),
1272                                            GFP_KERNEL);
1273         if (!mlxsw_pci->fw_area.items)
1274                 return -ENOMEM;
1275         mlxsw_pci->fw_area.num_pages = num_pages;
1276
1277         mlxsw_cmd_mbox_zero(mbox);
1278         for (i = 0; i < num_pages; i++) {
1279                 mem_item = &mlxsw_pci->fw_area.items[i];
1280
1281                 mem_item->size = MLXSW_PCI_PAGE_SIZE;
1282                 mem_item->buf = pci_alloc_consistent(mlxsw_pci->pdev,
1283                                                      mem_item->size,
1284                                                      &mem_item->mapaddr);
1285                 if (!mem_item->buf) {
1286                         err = -ENOMEM;
1287                         goto err_alloc;
1288                 }
1289                 mlxsw_cmd_mbox_map_fa_pa_set(mbox, i, mem_item->mapaddr);
1290                 mlxsw_cmd_mbox_map_fa_log2size_set(mbox, i, 0); /* 1 page */
1291         }
1292
1293         err = mlxsw_cmd_map_fa(mlxsw_pci->core, mbox, num_pages);
1294         if (err)
1295                 goto err_cmd_map_fa;
1296
1297         return 0;
1298
1299 err_cmd_map_fa:
1300 err_alloc:
1301         for (i--; i >= 0; i--) {
1302                 mem_item = &mlxsw_pci->fw_area.items[i];
1303
1304                 pci_free_consistent(mlxsw_pci->pdev, mem_item->size,
1305                                     mem_item->buf, mem_item->mapaddr);
1306         }
1307         kfree(mlxsw_pci->fw_area.items);
1308         return err;
1309 }
1310
1311 static void mlxsw_pci_fw_area_fini(struct mlxsw_pci *mlxsw_pci)
1312 {
1313         struct mlxsw_pci_mem_item *mem_item;
1314         int i;
1315
1316         mlxsw_cmd_unmap_fa(mlxsw_pci->core);
1317
1318         for (i = 0; i < mlxsw_pci->fw_area.num_pages; i++) {
1319                 mem_item = &mlxsw_pci->fw_area.items[i];
1320
1321                 pci_free_consistent(mlxsw_pci->pdev, mem_item->size,
1322                                     mem_item->buf, mem_item->mapaddr);
1323         }
1324         kfree(mlxsw_pci->fw_area.items);
1325 }
1326
1327 static irqreturn_t mlxsw_pci_eq_irq_handler(int irq, void *dev_id)
1328 {
1329         struct mlxsw_pci *mlxsw_pci = dev_id;
1330         struct mlxsw_pci_queue *q;
1331         int i;
1332
1333         for (i = 0; i < MLXSW_PCI_EQS_COUNT; i++) {
1334                 q = mlxsw_pci_eq_get(mlxsw_pci, i);
1335                 mlxsw_pci_queue_tasklet_schedule(q);
1336         }
1337         return IRQ_HANDLED;
1338 }
1339
1340 static int mlxsw_pci_init(void *bus_priv, struct mlxsw_core *mlxsw_core,
1341                           const struct mlxsw_config_profile *profile)
1342 {
1343         struct mlxsw_pci *mlxsw_pci = bus_priv;
1344         struct pci_dev *pdev = mlxsw_pci->pdev;
1345         char *mbox;
1346         u16 num_pages;
1347         int err;
1348
1349         mutex_init(&mlxsw_pci->cmd.lock);
1350         init_waitqueue_head(&mlxsw_pci->cmd.wait);
1351
1352         mlxsw_pci->core = mlxsw_core;
1353
1354         mbox = mlxsw_cmd_mbox_alloc();
1355         if (!mbox)
1356                 return -ENOMEM;
1357         err = mlxsw_cmd_query_fw(mlxsw_core, mbox);
1358         if (err)
1359                 goto err_query_fw;
1360
1361         mlxsw_pci->bus_info.fw_rev.major =
1362                 mlxsw_cmd_mbox_query_fw_fw_rev_major_get(mbox);
1363         mlxsw_pci->bus_info.fw_rev.minor =
1364                 mlxsw_cmd_mbox_query_fw_fw_rev_minor_get(mbox);
1365         mlxsw_pci->bus_info.fw_rev.subminor =
1366                 mlxsw_cmd_mbox_query_fw_fw_rev_subminor_get(mbox);
1367
1368         if (mlxsw_cmd_mbox_query_fw_cmd_interface_rev_get(mbox) != 1) {
1369                 dev_err(&pdev->dev, "Unsupported cmd interface revision ID queried from hw\n");
1370                 err = -EINVAL;
1371                 goto err_iface_rev;
1372         }
1373         if (mlxsw_cmd_mbox_query_fw_doorbell_page_bar_get(mbox) != 0) {
1374                 dev_err(&pdev->dev, "Unsupported doorbell page bar queried from hw\n");
1375                 err = -EINVAL;
1376                 goto err_doorbell_page_bar;
1377         }
1378
1379         mlxsw_pci->doorbell_offset =
1380                 mlxsw_cmd_mbox_query_fw_doorbell_page_offset_get(mbox);
1381
1382         num_pages = mlxsw_cmd_mbox_query_fw_fw_pages_get(mbox);
1383         err = mlxsw_pci_fw_area_init(mlxsw_pci, mbox, num_pages);
1384         if (err)
1385                 goto err_fw_area_init;
1386
1387         err = mlxsw_pci_boardinfo(mlxsw_pci, mbox);
1388         if (err)
1389                 goto err_boardinfo;
1390
1391         err = mlxsw_pci_config_profile(mlxsw_pci, mbox, profile);
1392         if (err)
1393                 goto err_config_profile;
1394
1395         err = mlxsw_pci_aqs_init(mlxsw_pci, mbox);
1396         if (err)
1397                 goto err_aqs_init;
1398
1399         err = request_irq(mlxsw_pci->msix_entry.vector,
1400                           mlxsw_pci_eq_irq_handler, 0,
1401                           mlxsw_pci_driver_name, mlxsw_pci);
1402         if (err) {
1403                 dev_err(&pdev->dev, "IRQ request failed\n");
1404                 goto err_request_eq_irq;
1405         }
1406
1407         goto mbox_put;
1408
1409 err_request_eq_irq:
1410         mlxsw_pci_aqs_fini(mlxsw_pci);
1411 err_aqs_init:
1412 err_config_profile:
1413 err_boardinfo:
1414         mlxsw_pci_fw_area_fini(mlxsw_pci);
1415 err_fw_area_init:
1416 err_doorbell_page_bar:
1417 err_iface_rev:
1418 err_query_fw:
1419 mbox_put:
1420         mlxsw_cmd_mbox_free(mbox);
1421         return err;
1422 }
1423
1424 static void mlxsw_pci_fini(void *bus_priv)
1425 {
1426         struct mlxsw_pci *mlxsw_pci = bus_priv;
1427
1428         free_irq(mlxsw_pci->msix_entry.vector, mlxsw_pci);
1429         mlxsw_pci_aqs_fini(mlxsw_pci);
1430         mlxsw_pci_fw_area_fini(mlxsw_pci);
1431 }
1432
1433 static struct mlxsw_pci_queue *
1434 mlxsw_pci_sdq_pick(struct mlxsw_pci *mlxsw_pci,
1435                    const struct mlxsw_tx_info *tx_info)
1436 {
1437         u8 sdqn = tx_info->local_port % mlxsw_pci_sdq_count(mlxsw_pci);
1438
1439         return mlxsw_pci_sdq_get(mlxsw_pci, sdqn);
1440 }
1441
1442 static int mlxsw_pci_skb_transmit(void *bus_priv, struct sk_buff *skb,
1443                                   const struct mlxsw_tx_info *tx_info)
1444 {
1445         struct mlxsw_pci *mlxsw_pci = bus_priv;
1446         struct mlxsw_pci_queue *q;
1447         struct mlxsw_pci_queue_elem_info *elem_info;
1448         char *wqe;
1449         int i;
1450         int err;
1451
1452         if (skb_shinfo(skb)->nr_frags > MLXSW_PCI_WQE_SG_ENTRIES - 1) {
1453                 err = skb_linearize(skb);
1454                 if (err)
1455                         return err;
1456         }
1457
1458         q = mlxsw_pci_sdq_pick(mlxsw_pci, tx_info);
1459         spin_lock_bh(&q->lock);
1460         elem_info = mlxsw_pci_queue_elem_info_producer_get(q);
1461         if (!elem_info) {
1462                 /* queue is full */
1463                 err = -EAGAIN;
1464                 goto unlock;
1465         }
1466         elem_info->u.sdq.skb = skb;
1467
1468         wqe = elem_info->elem;
1469         mlxsw_pci_wqe_c_set(wqe, 1); /* always report completion */
1470         mlxsw_pci_wqe_lp_set(wqe, !!tx_info->is_emad);
1471         mlxsw_pci_wqe_type_set(wqe, MLXSW_PCI_WQE_TYPE_ETHERNET);
1472
1473         err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, 0, skb->data,
1474                                      skb_headlen(skb), DMA_TO_DEVICE);
1475         if (err)
1476                 goto unlock;
1477
1478         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1479                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1480
1481                 err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, i + 1,
1482                                              skb_frag_address(frag),
1483                                              skb_frag_size(frag),
1484                                              DMA_TO_DEVICE);
1485                 if (err)
1486                         goto unmap_frags;
1487         }
1488
1489         /* Set unused sq entries byte count to zero. */
1490         for (i++; i < MLXSW_PCI_WQE_SG_ENTRIES; i++)
1491                 mlxsw_pci_wqe_byte_count_set(wqe, i, 0);
1492
1493         /* Everything is set up, ring producer doorbell to get HW going */
1494         q->producer_counter++;
1495         mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
1496
1497         goto unlock;
1498
1499 unmap_frags:
1500         for (; i >= 0; i--)
1501                 mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, i, DMA_TO_DEVICE);
1502 unlock:
1503         spin_unlock_bh(&q->lock);
1504         return err;
1505 }
1506
1507 static int mlxsw_pci_cmd_exec(void *bus_priv, u16 opcode, u8 opcode_mod,
1508                               u32 in_mod, bool out_mbox_direct,
1509                               char *in_mbox, size_t in_mbox_size,
1510                               char *out_mbox, size_t out_mbox_size,
1511                               u8 *p_status)
1512 {
1513         struct mlxsw_pci *mlxsw_pci = bus_priv;
1514         dma_addr_t in_mapaddr = 0;
1515         dma_addr_t out_mapaddr = 0;
1516         bool evreq = mlxsw_pci->cmd.nopoll;
1517         unsigned long timeout = msecs_to_jiffies(MLXSW_PCI_CIR_TIMEOUT_MSECS);
1518         bool *p_wait_done = &mlxsw_pci->cmd.wait_done;
1519         int err;
1520
1521         *p_status = MLXSW_CMD_STATUS_OK;
1522
1523         err = mutex_lock_interruptible(&mlxsw_pci->cmd.lock);
1524         if (err)
1525                 return err;
1526
1527         if (in_mbox) {
1528                 in_mapaddr = pci_map_single(mlxsw_pci->pdev, in_mbox,
1529                                             in_mbox_size, PCI_DMA_TODEVICE);
1530                 if (unlikely(pci_dma_mapping_error(mlxsw_pci->pdev,
1531                                                    in_mapaddr))) {
1532                         err = -EIO;
1533                         goto err_in_mbox_map;
1534                 }
1535         }
1536         mlxsw_pci_write32(mlxsw_pci, CIR_IN_PARAM_HI, in_mapaddr >> 32);
1537         mlxsw_pci_write32(mlxsw_pci, CIR_IN_PARAM_LO, in_mapaddr);
1538
1539         if (out_mbox) {
1540                 out_mapaddr = pci_map_single(mlxsw_pci->pdev, out_mbox,
1541                                              out_mbox_size, PCI_DMA_FROMDEVICE);
1542                 if (unlikely(pci_dma_mapping_error(mlxsw_pci->pdev,
1543                                                    out_mapaddr))) {
1544                         err = -EIO;
1545                         goto err_out_mbox_map;
1546                 }
1547         }
1548         mlxsw_pci_write32(mlxsw_pci, CIR_OUT_PARAM_HI, out_mapaddr >> 32);
1549         mlxsw_pci_write32(mlxsw_pci, CIR_OUT_PARAM_LO, out_mapaddr);
1550
1551         mlxsw_pci_write32(mlxsw_pci, CIR_IN_MODIFIER, in_mod);
1552         mlxsw_pci_write32(mlxsw_pci, CIR_TOKEN, 0);
1553
1554         *p_wait_done = false;
1555
1556         wmb(); /* all needs to be written before we write control register */
1557         mlxsw_pci_write32(mlxsw_pci, CIR_CTRL,
1558                           MLXSW_PCI_CIR_CTRL_GO_BIT |
1559                           (evreq ? MLXSW_PCI_CIR_CTRL_EVREQ_BIT : 0) |
1560                           (opcode_mod << MLXSW_PCI_CIR_CTRL_OPCODE_MOD_SHIFT) |
1561                           opcode);
1562
1563         if (!evreq) {
1564                 unsigned long end;
1565
1566                 end = jiffies + timeout;
1567                 do {
1568                         u32 ctrl = mlxsw_pci_read32(mlxsw_pci, CIR_CTRL);
1569
1570                         if (!(ctrl & MLXSW_PCI_CIR_CTRL_GO_BIT)) {
1571                                 *p_wait_done = true;
1572                                 *p_status = ctrl >> MLXSW_PCI_CIR_CTRL_STATUS_SHIFT;
1573                                 break;
1574                         }
1575                         cond_resched();
1576                 } while (time_before(jiffies, end));
1577         } else {
1578                 wait_event_timeout(mlxsw_pci->cmd.wait, *p_wait_done, timeout);
1579                 *p_status = mlxsw_pci->cmd.comp.status;
1580         }
1581
1582         err = 0;
1583         if (*p_wait_done) {
1584                 if (*p_status)
1585                         err = -EIO;
1586         } else {
1587                 err = -ETIMEDOUT;
1588         }
1589
1590         if (!err && out_mbox && out_mbox_direct) {
1591                 /* Some commands does not use output param as address to mailbox
1592                  * but they store output directly into registers. In that case,
1593                  * copy registers into mbox buffer.
1594                  */
1595                 __be32 tmp;
1596
1597                 if (!evreq) {
1598                         tmp = cpu_to_be32(mlxsw_pci_read32(mlxsw_pci,
1599                                                            CIR_OUT_PARAM_HI));
1600                         memcpy(out_mbox, &tmp, sizeof(tmp));
1601                         tmp = cpu_to_be32(mlxsw_pci_read32(mlxsw_pci,
1602                                                            CIR_OUT_PARAM_LO));
1603                         memcpy(out_mbox + sizeof(tmp), &tmp, sizeof(tmp));
1604                 }
1605         }
1606
1607         if (out_mapaddr)
1608                 pci_unmap_single(mlxsw_pci->pdev, out_mapaddr, out_mbox_size,
1609                                  PCI_DMA_FROMDEVICE);
1610
1611         /* fall through */
1612
1613 err_out_mbox_map:
1614         if (in_mapaddr)
1615                 pci_unmap_single(mlxsw_pci->pdev, in_mapaddr, in_mbox_size,
1616                                  PCI_DMA_TODEVICE);
1617 err_in_mbox_map:
1618         mutex_unlock(&mlxsw_pci->cmd.lock);
1619
1620         return err;
1621 }
1622
1623 static const struct mlxsw_bus mlxsw_pci_bus = {
1624         .kind           = "pci",
1625         .init           = mlxsw_pci_init,
1626         .fini           = mlxsw_pci_fini,
1627         .skb_transmit   = mlxsw_pci_skb_transmit,
1628         .cmd_exec       = mlxsw_pci_cmd_exec,
1629 };
1630
1631 static int mlxsw_pci_sw_reset(struct mlxsw_pci *mlxsw_pci)
1632 {
1633         mlxsw_pci_write32(mlxsw_pci, SW_RESET, MLXSW_PCI_SW_RESET_RST_BIT);
1634         /* Current firware does not let us know when the reset is done.
1635          * So we just wait here for constant time and hope for the best.
1636          */
1637         msleep(MLXSW_PCI_SW_RESET_TIMEOUT_MSECS);
1638         return 0;
1639 }
1640
1641 static int mlxsw_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1642 {
1643         struct mlxsw_pci *mlxsw_pci;
1644         int err;
1645
1646         mlxsw_pci = kzalloc(sizeof(*mlxsw_pci), GFP_KERNEL);
1647         if (!mlxsw_pci)
1648                 return -ENOMEM;
1649
1650         err = pci_enable_device(pdev);
1651         if (err) {
1652                 dev_err(&pdev->dev, "pci_enable_device failed\n");
1653                 goto err_pci_enable_device;
1654         }
1655
1656         err = pci_request_regions(pdev, mlxsw_pci_driver_name);
1657         if (err) {
1658                 dev_err(&pdev->dev, "pci_request_regions failed\n");
1659                 goto err_pci_request_regions;
1660         }
1661
1662         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1663         if (!err) {
1664                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1665                 if (err) {
1666                         dev_err(&pdev->dev, "pci_set_consistent_dma_mask failed\n");
1667                         goto err_pci_set_dma_mask;
1668                 }
1669         } else {
1670                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1671                 if (err) {
1672                         dev_err(&pdev->dev, "pci_set_dma_mask failed\n");
1673                         goto err_pci_set_dma_mask;
1674                 }
1675         }
1676
1677         if (pci_resource_len(pdev, 0) < MLXSW_PCI_BAR0_SIZE) {
1678                 dev_err(&pdev->dev, "invalid PCI region size\n");
1679                 err = -EINVAL;
1680                 goto err_pci_resource_len_check;
1681         }
1682
1683         mlxsw_pci->hw_addr = ioremap(pci_resource_start(pdev, 0),
1684                                      pci_resource_len(pdev, 0));
1685         if (!mlxsw_pci->hw_addr) {
1686                 dev_err(&pdev->dev, "ioremap failed\n");
1687                 err = -EIO;
1688                 goto err_ioremap;
1689         }
1690         pci_set_master(pdev);
1691
1692         mlxsw_pci->pdev = pdev;
1693         pci_set_drvdata(pdev, mlxsw_pci);
1694
1695         err = mlxsw_pci_sw_reset(mlxsw_pci);
1696         if (err) {
1697                 dev_err(&pdev->dev, "Software reset failed\n");
1698                 goto err_sw_reset;
1699         }
1700
1701         err = pci_enable_msix_exact(pdev, &mlxsw_pci->msix_entry, 1);
1702         if (err) {
1703                 dev_err(&pdev->dev, "MSI-X init failed\n");
1704                 goto err_msix_init;
1705         }
1706
1707         mlxsw_pci->bus_info.device_kind = mlxsw_pci_device_kind_get(id);
1708         mlxsw_pci->bus_info.device_name = pci_name(mlxsw_pci->pdev);
1709         mlxsw_pci->bus_info.dev = &pdev->dev;
1710
1711         mlxsw_pci->dbg_dir = debugfs_create_dir(mlxsw_pci->bus_info.device_name,
1712                                                 mlxsw_pci_dbg_root);
1713         if (!mlxsw_pci->dbg_dir) {
1714                 dev_err(&pdev->dev, "Failed to create debugfs dir\n");
1715                 goto err_dbg_create_dir;
1716         }
1717
1718         err = mlxsw_core_bus_device_register(&mlxsw_pci->bus_info,
1719                                              &mlxsw_pci_bus, mlxsw_pci);
1720         if (err) {
1721                 dev_err(&pdev->dev, "cannot register bus device\n");
1722                 goto err_bus_device_register;
1723         }
1724
1725         return 0;
1726
1727 err_bus_device_register:
1728         debugfs_remove_recursive(mlxsw_pci->dbg_dir);
1729 err_dbg_create_dir:
1730         pci_disable_msix(mlxsw_pci->pdev);
1731 err_msix_init:
1732 err_sw_reset:
1733         iounmap(mlxsw_pci->hw_addr);
1734 err_ioremap:
1735 err_pci_resource_len_check:
1736 err_pci_set_dma_mask:
1737         pci_release_regions(pdev);
1738 err_pci_request_regions:
1739         pci_disable_device(pdev);
1740 err_pci_enable_device:
1741         kfree(mlxsw_pci);
1742         return err;
1743 }
1744
1745 static void mlxsw_pci_remove(struct pci_dev *pdev)
1746 {
1747         struct mlxsw_pci *mlxsw_pci = pci_get_drvdata(pdev);
1748
1749         mlxsw_core_bus_device_unregister(mlxsw_pci->core);
1750         debugfs_remove_recursive(mlxsw_pci->dbg_dir);
1751         pci_disable_msix(mlxsw_pci->pdev);
1752         iounmap(mlxsw_pci->hw_addr);
1753         pci_release_regions(mlxsw_pci->pdev);
1754         pci_disable_device(mlxsw_pci->pdev);
1755         kfree(mlxsw_pci);
1756 }
1757
1758 static struct pci_driver mlxsw_pci_driver = {
1759         .name           = mlxsw_pci_driver_name,
1760         .id_table       = mlxsw_pci_id_table,
1761         .probe          = mlxsw_pci_probe,
1762         .remove         = mlxsw_pci_remove,
1763 };
1764
1765 static int __init mlxsw_pci_module_init(void)
1766 {
1767         int err;
1768
1769         mlxsw_pci_dbg_root = debugfs_create_dir(mlxsw_pci_driver_name, NULL);
1770         if (!mlxsw_pci_dbg_root)
1771                 return -ENOMEM;
1772         err = pci_register_driver(&mlxsw_pci_driver);
1773         if (err)
1774                 goto err_register_driver;
1775         return 0;
1776
1777 err_register_driver:
1778         debugfs_remove_recursive(mlxsw_pci_dbg_root);
1779         return err;
1780 }
1781
1782 static void __exit mlxsw_pci_module_exit(void)
1783 {
1784         pci_unregister_driver(&mlxsw_pci_driver);
1785         debugfs_remove_recursive(mlxsw_pci_dbg_root);
1786 }
1787
1788 module_init(mlxsw_pci_module_init);
1789 module_exit(mlxsw_pci_module_exit);
1790
1791 MODULE_LICENSE("Dual BSD/GPL");
1792 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
1793 MODULE_DESCRIPTION("Mellanox switch PCI interface driver");
1794 MODULE_DEVICE_TABLE(pci, mlxsw_pci_id_table);