drivers/net/ethernet/mellanox/mlxsw/pci.c

   1 /*
   2  * drivers/net/ethernet/mellanox/mlxsw/pci.c
   3  * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
   4  * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are met:
   8  *
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. Neither the names of the copyright holders nor the names of its
  15  *    contributors may be used to endorse or promote products derived from
  16  *    this software without specific prior written permission.
  17  *
  18  * Alternatively, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") version 2 as published by the Free
  20  * Software Foundation.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  23  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  26  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  32  * POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 #include <linux/kernel.h>
  36 #include <linux/module.h>
  37 #include <linux/export.h>
  38 #include <linux/err.h>
  39 #include <linux/device.h>
  40 #include <linux/pci.h>
  41 #include <linux/interrupt.h>
  42 #include <linux/wait.h>
  43 #include <linux/types.h>
  44 #include <linux/skbuff.h>
  45 #include <linux/if_vlan.h>
  46 #include <linux/log2.h>
  47 #include <linux/debugfs.h>
  48 #include <linux/seq_file.h>
  49 #include <linux/string.h>
  50
  51 #include "pci.h"
  52 #include "core.h"
  53 #include "cmd.h"
  54 #include "port.h"
  55
  56 static const char mlxsw_pci_driver_name[] = "mlxsw_pci";
  57
  58 static const struct pci_device_id mlxsw_pci_id_table[] = {
  59         {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SWITCHX2), 0},
  60         {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
  61         {0, }
  62 };
  63
  64 static struct dentry *mlxsw_pci_dbg_root;
  65
  66 static const char *mlxsw_pci_device_kind_get(const struct pci_device_id *id)
  67 {
  68         switch (id->device) {
  69         case PCI_DEVICE_ID_MELLANOX_SWITCHX2:
  70                 return MLXSW_DEVICE_KIND_SWITCHX2;
  71         case PCI_DEVICE_ID_MELLANOX_SPECTRUM:
  72                 return MLXSW_DEVICE_KIND_SPECTRUM;
  73         default:
  74                 BUG();
  75         }
  76 }
  77
  78 #define mlxsw_pci_write32(mlxsw_pci, reg, val) \
  79         iowrite32be(val, (mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg))
  80 #define mlxsw_pci_read32(mlxsw_pci, reg) \
  81         ioread32be((mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg))
  82
  83 enum mlxsw_pci_queue_type {
  84         MLXSW_PCI_QUEUE_TYPE_SDQ,
  85         MLXSW_PCI_QUEUE_TYPE_RDQ,
  86         MLXSW_PCI_QUEUE_TYPE_CQ,
  87         MLXSW_PCI_QUEUE_TYPE_EQ,
  88 };
  89
  90 static const char *mlxsw_pci_queue_type_str(enum mlxsw_pci_queue_type q_type)
  91 {
  92         switch (q_type) {
  93         case MLXSW_PCI_QUEUE_TYPE_SDQ:
  94                 return "sdq";
  95         case MLXSW_PCI_QUEUE_TYPE_RDQ:
  96                 return "rdq";
  97         case MLXSW_PCI_QUEUE_TYPE_CQ:
  98                 return "cq";
  99         case MLXSW_PCI_QUEUE_TYPE_EQ:
 100                 return "eq";
 101         }
 102         BUG();
 103 }
 104
 105 #define MLXSW_PCI_QUEUE_TYPE_COUNT      4
 106
 107 static const u16 mlxsw_pci_doorbell_type_offset[] = {
 108         MLXSW_PCI_DOORBELL_SDQ_OFFSET,  /* for type MLXSW_PCI_QUEUE_TYPE_SDQ */
 109         MLXSW_PCI_DOORBELL_RDQ_OFFSET,  /* for type MLXSW_PCI_QUEUE_TYPE_RDQ */
 110         MLXSW_PCI_DOORBELL_CQ_OFFSET,   /* for type MLXSW_PCI_QUEUE_TYPE_CQ */
 111         MLXSW_PCI_DOORBELL_EQ_OFFSET,   /* for type MLXSW_PCI_QUEUE_TYPE_EQ */
 112 };
 113
 114 static const u16 mlxsw_pci_doorbell_arm_type_offset[] = {
 115         0, /* unused */
 116         0, /* unused */
 117         MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_CQ */
 118         MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_EQ */
 119 };
 120
 121 struct mlxsw_pci_mem_item {
 122         char *buf;
 123         dma_addr_t mapaddr;
 124         size_t size;
 125 };
 126
 127 struct mlxsw_pci_queue_elem_info {
 128         char *elem; /* pointer to actual dma mapped element mem chunk */
 129         union {
 130                 struct {
 131                         struct sk_buff *skb;
 132                 } sdq;
 133                 struct {
 134                         struct sk_buff *skb;
 135                 } rdq;
 136         } u;
 137 };
 138
 139 struct mlxsw_pci_queue {
 140         spinlock_t lock; /* for queue accesses */
 141         struct mlxsw_pci_mem_item mem_item;
 142         struct mlxsw_pci_queue_elem_info *elem_info;
 143         u16 producer_counter;
 144         u16 consumer_counter;
 145         u16 count; /* number of elements in queue */
 146         u8 num; /* queue number */
 147         u8 elem_size; /* size of one element */
 148         enum mlxsw_pci_queue_type type;
 149         struct tasklet_struct tasklet; /* queue processing tasklet */
 150         struct mlxsw_pci *pci;
 151         union {
 152                 struct {
 153                         u32 comp_sdq_count;
 154                         u32 comp_rdq_count;
 155                 } cq;
 156                 struct {
 157                         u32 ev_cmd_count;
 158                         u32 ev_comp_count;
 159                         u32 ev_other_count;
 160                 } eq;
 161         } u;
 162 };
 163
 164 struct mlxsw_pci_queue_type_group {
 165         struct mlxsw_pci_queue *q;
 166         u8 count; /* number of queues in group */
 167 };
 168
 169 struct mlxsw_pci {
 170         struct pci_dev *pdev;
 171         u8 __iomem *hw_addr;
 172         struct mlxsw_pci_queue_type_group queues[MLXSW_PCI_QUEUE_TYPE_COUNT];
 173         u32 doorbell_offset;
 174         struct msix_entry msix_entry;
 175         struct mlxsw_core *core;
 176         struct {
 177                 struct mlxsw_pci_mem_item *items;
 178                 unsigned int count;
 179         } fw_area;
 180         struct {
 181                 struct mlxsw_pci_mem_item out_mbox;
 182                 struct mlxsw_pci_mem_item in_mbox;
 183                 struct mutex lock; /* Lock access to command registers */
 184                 bool nopoll;
 185                 wait_queue_head_t wait;
 186                 bool wait_done;
 187                 struct {
 188                         u8 status;
 189                         u64 out_param;
 190                 } comp;
 191         } cmd;
 192         struct mlxsw_bus_info bus_info;
 193         struct dentry *dbg_dir;
 194 };
 195
 196 static void mlxsw_pci_queue_tasklet_schedule(struct mlxsw_pci_queue *q)
 197 {
 198         tasklet_schedule(&q->tasklet);
 199 }
 200
 201 static char *__mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue *q,
 202                                         size_t elem_size, int elem_index)
 203 {
 204         return q->mem_item.buf + (elem_size * elem_index);
 205 }
 206
 207 static struct mlxsw_pci_queue_elem_info *
 208 mlxsw_pci_queue_elem_info_get(struct mlxsw_pci_queue *q, int elem_index)
 209 {
 210         return &q->elem_info[elem_index];
 211 }
 212
 213 static struct mlxsw_pci_queue_elem_info *
 214 mlxsw_pci_queue_elem_info_producer_get(struct mlxsw_pci_queue *q)
 215 {
 216         int index = q->producer_counter & (q->count - 1);
 217
 218         if ((u16) (q->producer_counter - q->consumer_counter) == q->count)
 219                 return NULL;
 220         return mlxsw_pci_queue_elem_info_get(q, index);
 221 }
 222
 223 static struct mlxsw_pci_queue_elem_info *
 224 mlxsw_pci_queue_elem_info_consumer_get(struct mlxsw_pci_queue *q)
 225 {
 226         int index = q->consumer_counter & (q->count - 1);
 227
 228         return mlxsw_pci_queue_elem_info_get(q, index);
 229 }
 230
 231 static char *mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue *q, int elem_index)
 232 {
 233         return mlxsw_pci_queue_elem_info_get(q, elem_index)->elem;
 234 }
 235
 236 static bool mlxsw_pci_elem_hw_owned(struct mlxsw_pci_queue *q, bool owner_bit)
 237 {
 238         return owner_bit != !!(q->consumer_counter & q->count);
 239 }
 240
 241 static char *mlxsw_pci_queue_sw_elem_get(struct mlxsw_pci_queue *q,
 242                                          u32 (*get_elem_owner_func)(char *))
 243 {
 244         struct mlxsw_pci_queue_elem_info *elem_info;
 245         char *elem;
 246         bool owner_bit;
 247
 248         elem_info = mlxsw_pci_queue_elem_info_consumer_get(q);
 249         elem = elem_info->elem;
 250         owner_bit = get_elem_owner_func(elem);
 251         if (mlxsw_pci_elem_hw_owned(q, owner_bit))
 252                 return NULL;
 253         q->consumer_counter++;
 254         rmb(); /* make sure we read owned bit before the rest of elem */
 255         return elem;
 256 }
 257
 258 static struct mlxsw_pci_queue_type_group *
 259 mlxsw_pci_queue_type_group_get(struct mlxsw_pci *mlxsw_pci,
 260                                enum mlxsw_pci_queue_type q_type)
 261 {
 262         return &mlxsw_pci->queues[q_type];
 263 }
 264
 265 static u8 __mlxsw_pci_queue_count(struct mlxsw_pci *mlxsw_pci,
 266                                   enum mlxsw_pci_queue_type q_type)
 267 {
 268         struct mlxsw_pci_queue_type_group *queue_group;
 269
 270         queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_type);
 271         return queue_group->count;
 272 }
 273
 274 static u8 mlxsw_pci_sdq_count(struct mlxsw_pci *mlxsw_pci)
 275 {
 276         return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_SDQ);
 277 }
 278
 279 static u8 mlxsw_pci_rdq_count(struct mlxsw_pci *mlxsw_pci)
 280 {
 281         return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_RDQ);
 282 }
 283
 284 static u8 mlxsw_pci_cq_count(struct mlxsw_pci *mlxsw_pci)
 285 {
 286         return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_CQ);
 287 }
 288
 289 static u8 mlxsw_pci_eq_count(struct mlxsw_pci *mlxsw_pci)
 290 {
 291         return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_EQ);
 292 }
 293
 294 static struct mlxsw_pci_queue *
 295 __mlxsw_pci_queue_get(struct mlxsw_pci *mlxsw_pci,
 296                       enum mlxsw_pci_queue_type q_type, u8 q_num)
 297 {
 298         return &mlxsw_pci->queues[q_type].q[q_num];
 299 }
 300
 301 static struct mlxsw_pci_queue *mlxsw_pci_sdq_get(struct mlxsw_pci *mlxsw_pci,
 302                                                  u8 q_num)
 303 {
 304         return __mlxsw_pci_queue_get(mlxsw_pci,
 305                                      MLXSW_PCI_QUEUE_TYPE_SDQ, q_num);
 306 }
 307
 308 static struct mlxsw_pci_queue *mlxsw_pci_rdq_get(struct mlxsw_pci *mlxsw_pci,
 309                                                  u8 q_num)
 310 {
 311         return __mlxsw_pci_queue_get(mlxsw_pci,
 312                                      MLXSW_PCI_QUEUE_TYPE_RDQ, q_num);
 313 }
 314
 315 static struct mlxsw_pci_queue *mlxsw_pci_cq_get(struct mlxsw_pci *mlxsw_pci,
 316                                                 u8 q_num)
 317 {
 318         return __mlxsw_pci_queue_get(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_CQ, q_num);
 319 }
 320
 321 static struct mlxsw_pci_queue *mlxsw_pci_eq_get(struct mlxsw_pci *mlxsw_pci,
 322                                                 u8 q_num)
 323 {
 324         return __mlxsw_pci_queue_get(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_EQ, q_num);
 325 }
 326
 327 static void __mlxsw_pci_queue_doorbell_set(struct mlxsw_pci *mlxsw_pci,
 328                                            struct mlxsw_pci_queue *q,
 329                                            u16 val)
 330 {
 331         mlxsw_pci_write32(mlxsw_pci,
 332                           DOORBELL(mlxsw_pci->doorbell_offset,
 333                                    mlxsw_pci_doorbell_type_offset[q->type],
 334                                    q->num), val);
 335 }
 336
 337 static void __mlxsw_pci_queue_doorbell_arm_set(struct mlxsw_pci *mlxsw_pci,
 338                                                struct mlxsw_pci_queue *q,
 339                                                u16 val)
 340 {
 341         mlxsw_pci_write32(mlxsw_pci,
 342                           DOORBELL(mlxsw_pci->doorbell_offset,
 343                                    mlxsw_pci_doorbell_arm_type_offset[q->type],
 344                                    q->num), val);
 345 }
 346
 347 static void mlxsw_pci_queue_doorbell_producer_ring(struct mlxsw_pci *mlxsw_pci,
 348                                                    struct mlxsw_pci_queue *q)
 349 {
 350         wmb(); /* ensure all writes are done before we ring a bell */
 351         __mlxsw_pci_queue_doorbell_set(mlxsw_pci, q, q->producer_counter);
 352 }
 353
 354 static void mlxsw_pci_queue_doorbell_consumer_ring(struct mlxsw_pci *mlxsw_pci,
 355                                                    struct mlxsw_pci_queue *q)
 356 {
 357         wmb(); /* ensure all writes are done before we ring a bell */
 358         __mlxsw_pci_queue_doorbell_set(mlxsw_pci, q,
 359                                        q->consumer_counter + q->count);
 360 }
 361
 362 static void
 363 mlxsw_pci_queue_doorbell_arm_consumer_ring(struct mlxsw_pci *mlxsw_pci,
 364                                            struct mlxsw_pci_queue *q)
 365 {
 366         wmb(); /* ensure all writes are done before we ring a bell */
 367         __mlxsw_pci_queue_doorbell_arm_set(mlxsw_pci, q, q->consumer_counter);
 368 }
 369
 370 static dma_addr_t __mlxsw_pci_queue_page_get(struct mlxsw_pci_queue *q,
 371                                              int page_index)
 372 {
 373         return q->mem_item.mapaddr + MLXSW_PCI_PAGE_SIZE * page_index;
 374 }
 375
 376 static int mlxsw_pci_sdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
 377                               struct mlxsw_pci_queue *q)
 378 {
 379         int i;
 380         int err;
 381
 382         q->producer_counter = 0;
 383         q->consumer_counter = 0;
 384
 385         /* Set CQ of same number of this SDQ. */
 386         mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, q->num);
 387         mlxsw_cmd_mbox_sw2hw_dq_sdq_tclass_set(mbox, 3);
 388         mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3); /* 8 pages */
 389         for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
 390                 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
 391
 392                 mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr);
 393         }
 394
 395         err = mlxsw_cmd_sw2hw_sdq(mlxsw_pci->core, mbox, q->num);
 396         if (err)
 397                 return err;
 398         mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
 399         return 0;
 400 }
 401
 402 static void mlxsw_pci_sdq_fini(struct mlxsw_pci *mlxsw_pci,
 403                                struct mlxsw_pci_queue *q)
 404 {
 405         mlxsw_cmd_hw2sw_sdq(mlxsw_pci->core, q->num);
 406 }
 407
 408 static int mlxsw_pci_sdq_dbg_read(struct seq_file *file, void *data)
 409 {
 410         struct mlxsw_pci *mlxsw_pci = dev_get_drvdata(file->private);
 411         struct mlxsw_pci_queue *q;
 412         int i;
 413         static const char hdr[] =
 414                 "NUM PROD_COUNT CONS_COUNT COUNT\n";
 415
 416         seq_printf(file, hdr);
 417         for (i = 0; i < mlxsw_pci_sdq_count(mlxsw_pci); i++) {
 418                 q = mlxsw_pci_sdq_get(mlxsw_pci, i);
 419                 spin_lock_bh(&q->lock);
 420                 seq_printf(file, "%3d %10d %10d %5d\n",
 421                            i, q->producer_counter, q->consumer_counter,
 422                            q->count);
 423                 spin_unlock_bh(&q->lock);
 424         }
 425         return 0;
 426 }
 427
 428 static int mlxsw_pci_wqe_frag_map(struct mlxsw_pci *mlxsw_pci, char *wqe,
 429                                   int index, char *frag_data, size_t frag_len,
 430                                   int direction)
 431 {
 432         struct pci_dev *pdev = mlxsw_pci->pdev;
 433         dma_addr_t mapaddr;
 434
 435         mapaddr = pci_map_single(pdev, frag_data, frag_len, direction);
 436         if (unlikely(pci_dma_mapping_error(pdev, mapaddr))) {
 437                 dev_err_ratelimited(&pdev->dev, "failed to dma map tx frag\n");
 438                 return -EIO;
 439         }
 440         mlxsw_pci_wqe_address_set(wqe, index, mapaddr);
 441         mlxsw_pci_wqe_byte_count_set(wqe, index, frag_len);
 442         return 0;
 443 }
 444
 445 static void mlxsw_pci_wqe_frag_unmap(struct mlxsw_pci *mlxsw_pci, char *wqe,
 446                                      int index, int direction)
 447 {
 448         struct pci_dev *pdev = mlxsw_pci->pdev;
 449         size_t frag_len = mlxsw_pci_wqe_byte_count_get(wqe, index);
 450         dma_addr_t mapaddr = mlxsw_pci_wqe_address_get(wqe, index);
 451
 452         if (!frag_len)
 453                 return;
 454         pci_unmap_single(pdev, mapaddr, frag_len, direction);
 455 }
 456
 457 static int mlxsw_pci_rdq_skb_alloc(struct mlxsw_pci *mlxsw_pci,
 458                                    struct mlxsw_pci_queue_elem_info *elem_info)
 459 {
 460         size_t buf_len = MLXSW_PORT_MAX_MTU;
 461         char *wqe = elem_info->elem;
 462         struct sk_buff *skb;
 463         int err;
 464
 465         elem_info->u.rdq.skb = NULL;
 466         skb = netdev_alloc_skb_ip_align(NULL, buf_len);
 467         if (!skb)
 468                 return -ENOMEM;
 469
 470         /* Assume that wqe was previously zeroed. */
 471
 472         err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, 0, skb->data,
 473                                      buf_len, DMA_FROM_DEVICE);
 474         if (err)
 475                 goto err_frag_map;
 476
 477         elem_info->u.rdq.skb = skb;
 478         return 0;
 479
 480 err_frag_map:
 481         dev_kfree_skb_any(skb);
 482         return err;
 483 }
 484
 485 static void mlxsw_pci_rdq_skb_free(struct mlxsw_pci *mlxsw_pci,
 486                                    struct mlxsw_pci_queue_elem_info *elem_info)
 487 {
 488         struct sk_buff *skb;
 489         char *wqe;
 490
 491         skb = elem_info->u.rdq.skb;
 492         wqe = elem_info->elem;
 493
 494         mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, 0, DMA_FROM_DEVICE);
 495         dev_kfree_skb_any(skb);
 496 }
 497
 498 static int mlxsw_pci_rdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
 499                               struct mlxsw_pci_queue *q)
 500 {
 501         struct mlxsw_pci_queue_elem_info *elem_info;
 502         u8 sdq_count = mlxsw_pci_sdq_count(mlxsw_pci);
 503         int i;
 504         int err;
 505
 506         q->producer_counter = 0;
 507         q->consumer_counter = 0;
 508
 509         /* Set CQ of same number of this RDQ with base
 510          * above SDQ count as the lower ones are assigned to SDQs.
 511          */
 512         mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, sdq_count + q->num);
 513         mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3); /* 8 pages */
 514         for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
 515                 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
 516
 517                 mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr);
 518         }
 519
 520         err = mlxsw_cmd_sw2hw_rdq(mlxsw_pci->core, mbox, q->num);
 521         if (err)
 522                 return err;
 523
 524         mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
 525
 526         for (i = 0; i < q->count; i++) {
 527                 elem_info = mlxsw_pci_queue_elem_info_producer_get(q);
 528                 BUG_ON(!elem_info);
 529                 err = mlxsw_pci_rdq_skb_alloc(mlxsw_pci, elem_info);
 530                 if (err)
 531                         goto rollback;
 532                 /* Everything is set up, ring doorbell to pass elem to HW */
 533                 q->producer_counter++;
 534                 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
 535         }
 536
 537         return 0;
 538
 539 rollback:
 540         for (i--; i >= 0; i--) {
 541                 elem_info = mlxsw_pci_queue_elem_info_get(q, i);
 542                 mlxsw_pci_rdq_skb_free(mlxsw_pci, elem_info);
 543         }
 544         mlxsw_cmd_hw2sw_rdq(mlxsw_pci->core, q->num);
 545
 546         return err;
 547 }
 548
 549 static void mlxsw_pci_rdq_fini(struct mlxsw_pci *mlxsw_pci,
 550                                struct mlxsw_pci_queue *q)
 551 {
 552         struct mlxsw_pci_queue_elem_info *elem_info;
 553         int i;
 554
 555         mlxsw_cmd_hw2sw_rdq(mlxsw_pci->core, q->num);
 556         for (i = 0; i < q->count; i++) {
 557                 elem_info = mlxsw_pci_queue_elem_info_get(q, i);
 558                 mlxsw_pci_rdq_skb_free(mlxsw_pci, elem_info);
 559         }
 560 }
 561
 562 static int mlxsw_pci_rdq_dbg_read(struct seq_file *file, void *data)
 563 {
 564         struct mlxsw_pci *mlxsw_pci = dev_get_drvdata(file->private);
 565         struct mlxsw_pci_queue *q;
 566         int i;
 567         static const char hdr[] =
 568                 "NUM PROD_COUNT CONS_COUNT COUNT\n";
 569
 570         seq_printf(file, hdr);
 571         for (i = 0; i < mlxsw_pci_rdq_count(mlxsw_pci); i++) {
 572                 q = mlxsw_pci_rdq_get(mlxsw_pci, i);
 573                 spin_lock_bh(&q->lock);
 574                 seq_printf(file, "%3d %10d %10d %5d\n",
 575                            i, q->producer_counter, q->consumer_counter,
 576                            q->count);
 577                 spin_unlock_bh(&q->lock);
 578         }
 579         return 0;
 580 }
 581
 582 static int mlxsw_pci_cq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
 583                              struct mlxsw_pci_queue *q)
 584 {
 585         int i;
 586         int err;
 587
 588         q->consumer_counter = 0;
 589
 590         for (i = 0; i < q->count; i++) {
 591                 char *elem = mlxsw_pci_queue_elem_get(q, i);
 592
 593                 mlxsw_pci_cqe_owner_set(elem, 1);
 594         }
 595
 596         mlxsw_cmd_mbox_sw2hw_cq_cv_set(mbox, 0); /* CQE ver 0 */
 597         mlxsw_cmd_mbox_sw2hw_cq_c_eqn_set(mbox, MLXSW_PCI_EQ_COMP_NUM);
 598         mlxsw_cmd_mbox_sw2hw_cq_oi_set(mbox, 0);
 599         mlxsw_cmd_mbox_sw2hw_cq_st_set(mbox, 0);
 600         mlxsw_cmd_mbox_sw2hw_cq_log_cq_size_set(mbox, ilog2(q->count));
 601         for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
 602                 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
 603
 604                 mlxsw_cmd_mbox_sw2hw_cq_pa_set(mbox, i, mapaddr);
 605         }
 606         err = mlxsw_cmd_sw2hw_cq(mlxsw_pci->core, mbox, q->num);
 607         if (err)
 608                 return err;
 609         mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
 610         mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
 611         return 0;
 612 }
 613
 614 static void mlxsw_pci_cq_fini(struct mlxsw_pci *mlxsw_pci,
 615                               struct mlxsw_pci_queue *q)
 616 {
 617         mlxsw_cmd_hw2sw_cq(mlxsw_pci->core, q->num);
 618 }
 619
 620 static int mlxsw_pci_cq_dbg_read(struct seq_file *file, void *data)
 621 {
 622         struct mlxsw_pci *mlxsw_pci = dev_get_drvdata(file->private);
 623
 624         struct mlxsw_pci_queue *q;
 625         int i;
 626         static const char hdr[] =
 627                 "NUM CONS_INDEX  SDQ_COUNT  RDQ_COUNT COUNT\n";
 628
 629         seq_printf(file, hdr);
 630         for (i = 0; i < mlxsw_pci_cq_count(mlxsw_pci); i++) {
 631                 q = mlxsw_pci_cq_get(mlxsw_pci, i);
 632                 spin_lock_bh(&q->lock);
 633                 seq_printf(file, "%3d %10d %10d %10d %5d\n",
 634                            i, q->consumer_counter, q->u.cq.comp_sdq_count,
 635                            q->u.cq.comp_rdq_count, q->count);
 636                 spin_unlock_bh(&q->lock);
 637         }
 638         return 0;
 639 }
 640
 641 static void mlxsw_pci_cqe_sdq_handle(struct mlxsw_pci *mlxsw_pci,
 642                                      struct mlxsw_pci_queue *q,
 643                                      u16 consumer_counter_limit,
 644                                      char *cqe)
 645 {
 646         struct pci_dev *pdev = mlxsw_pci->pdev;
 647         struct mlxsw_pci_queue_elem_info *elem_info;
 648         char *wqe;
 649         struct sk_buff *skb;
 650         int i;
 651
 652         spin_lock(&q->lock);
 653         elem_info = mlxsw_pci_queue_elem_info_consumer_get(q);
 654         skb = elem_info->u.sdq.skb;
 655         wqe = elem_info->elem;
 656         for (i = 0; i < MLXSW_PCI_WQE_SG_ENTRIES; i++)
 657                 mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, i, DMA_TO_DEVICE);
 658         dev_kfree_skb_any(skb);
 659         elem_info->u.sdq.skb = NULL;
 660
 661         if (q->consumer_counter++ != consumer_counter_limit)
 662                 dev_dbg_ratelimited(&pdev->dev, "Consumer counter does not match limit in SDQ\n");
 663         spin_unlock(&q->lock);
 664 }
 665
 666 static void mlxsw_pci_cqe_rdq_handle(struct mlxsw_pci *mlxsw_pci,
 667                                      struct mlxsw_pci_queue *q,
 668                                      u16 consumer_counter_limit,
 669                                      char *cqe)
 670 {
 671         struct pci_dev *pdev = mlxsw_pci->pdev;
 672         struct mlxsw_pci_queue_elem_info *elem_info;
 673         char *wqe;
 674         struct sk_buff *skb;
 675         struct mlxsw_rx_info rx_info;
 676         u16 byte_count;
 677         int err;
 678
 679         elem_info = mlxsw_pci_queue_elem_info_consumer_get(q);
 680         skb = elem_info->u.sdq.skb;
 681         if (!skb)
 682                 return;
 683         wqe = elem_info->elem;
 684         mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, 0, DMA_FROM_DEVICE);
 685
 686         if (q->consumer_counter++ != consumer_counter_limit)
 687                 dev_dbg_ratelimited(&pdev->dev, "Consumer counter does not match limit in RDQ\n");
 688
 689         if (mlxsw_pci_cqe_lag_get(cqe)) {
 690                 rx_info.is_lag = true;
 691                 rx_info.u.lag_id = mlxsw_pci_cqe_lag_id_get(cqe);
 692                 rx_info.lag_port_index = mlxsw_pci_cqe_lag_port_index_get(cqe);
 693         } else {
 694                 rx_info.is_lag = false;
 695                 rx_info.u.sys_port = mlxsw_pci_cqe_system_port_get(cqe);
 696         }
 697
 698         rx_info.trap_id = mlxsw_pci_cqe_trap_id_get(cqe);
 699
 700         byte_count = mlxsw_pci_cqe_byte_count_get(cqe);
 701         if (mlxsw_pci_cqe_crc_get(cqe))
 702                 byte_count -= ETH_FCS_LEN;
 703         skb_put(skb, byte_count);
 704         mlxsw_core_skb_receive(mlxsw_pci->core, skb, &rx_info);
 705
 706         memset(wqe, 0, q->elem_size);
 707         err = mlxsw_pci_rdq_skb_alloc(mlxsw_pci, elem_info);
 708         if (err)
 709                 dev_dbg_ratelimited(&pdev->dev, "Failed to alloc skb for RDQ\n");
 710         /* Everything is set up, ring doorbell to pass elem to HW */
 711         q->producer_counter++;
 712         mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
 713         return;
 714 }
 715
 716 static char *mlxsw_pci_cq_sw_cqe_get(struct mlxsw_pci_queue *q)
 717 {
 718         return mlxsw_pci_queue_sw_elem_get(q, mlxsw_pci_cqe_owner_get);
 719 }
 720
 721 static void mlxsw_pci_cq_tasklet(unsigned long data)
 722 {
 723         struct mlxsw_pci_queue *q = (struct mlxsw_pci_queue *) data;
 724         struct mlxsw_pci *mlxsw_pci = q->pci;
 725         char *cqe;
 726         int items = 0;
 727         int credits = q->count >> 1;
 728
 729         while ((cqe = mlxsw_pci_cq_sw_cqe_get(q))) {
 730                 u16 wqe_counter = mlxsw_pci_cqe_wqe_counter_get(cqe);
 731                 u8 sendq = mlxsw_pci_cqe_sr_get(cqe);
 732                 u8 dqn = mlxsw_pci_cqe_dqn_get(cqe);
 733
 734                 if (sendq) {
 735                         struct mlxsw_pci_queue *sdq;
 736
 737                         sdq = mlxsw_pci_sdq_get(mlxsw_pci, dqn);
 738                         mlxsw_pci_cqe_sdq_handle(mlxsw_pci, sdq,
 739                                                  wqe_counter, cqe);
 740                         q->u.cq.comp_sdq_count++;
 741                 } else {
 742                         struct mlxsw_pci_queue *rdq;
 743
 744                         rdq = mlxsw_pci_rdq_get(mlxsw_pci, dqn);
 745                         mlxsw_pci_cqe_rdq_handle(mlxsw_pci, rdq,
 746                                                  wqe_counter, cqe);
 747                         q->u.cq.comp_rdq_count++;
 748                 }
 749                 if (++items == credits)
 750                         break;
 751         }
 752         if (items) {
 753                 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
 754                 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
 755         }
 756 }
 757
 758 static int mlxsw_pci_eq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
 759                              struct mlxsw_pci_queue *q)
 760 {
 761         int i;
 762         int err;
 763
 764         q->consumer_counter = 0;
 765
 766         for (i = 0; i < q->count; i++) {
 767                 char *elem = mlxsw_pci_queue_elem_get(q, i);
 768
 769                 mlxsw_pci_eqe_owner_set(elem, 1);
 770         }
 771
 772         mlxsw_cmd_mbox_sw2hw_eq_int_msix_set(mbox, 1); /* MSI-X used */
 773         mlxsw_cmd_mbox_sw2hw_eq_oi_set(mbox, 0);
 774         mlxsw_cmd_mbox_sw2hw_eq_st_set(mbox, 1); /* armed */
 775         mlxsw_cmd_mbox_sw2hw_eq_log_eq_size_set(mbox, ilog2(q->count));
 776         for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
 777                 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
 778
 779                 mlxsw_cmd_mbox_sw2hw_eq_pa_set(mbox, i, mapaddr);
 780         }
 781         err = mlxsw_cmd_sw2hw_eq(mlxsw_pci->core, mbox, q->num);
 782         if (err)
 783                 return err;
 784         mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
 785         mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
 786         return 0;
 787 }
 788
 789 static void mlxsw_pci_eq_fini(struct mlxsw_pci *mlxsw_pci,
 790                               struct mlxsw_pci_queue *q)
 791 {
 792         mlxsw_cmd_hw2sw_eq(mlxsw_pci->core, q->num);
 793 }
 794
 795 static int mlxsw_pci_eq_dbg_read(struct seq_file *file, void *data)
 796 {
 797         struct mlxsw_pci *mlxsw_pci = dev_get_drvdata(file->private);
 798         struct mlxsw_pci_queue *q;
 799         int i;
 800         static const char hdr[] =
 801                 "NUM CONS_COUNT     EV_CMD    EV_COMP   EV_OTHER COUNT\n";
 802
 803         seq_printf(file, hdr);
 804         for (i = 0; i < mlxsw_pci_eq_count(mlxsw_pci); i++) {
 805                 q = mlxsw_pci_eq_get(mlxsw_pci, i);
 806                 spin_lock_bh(&q->lock);
 807                 seq_printf(file, "%3d %10d %10d %10d %10d %5d\n",
 808                            i, q->consumer_counter, q->u.eq.ev_cmd_count,
 809                            q->u.eq.ev_comp_count, q->u.eq.ev_other_count,
 810                            q->count);
 811                 spin_unlock_bh(&q->lock);
 812         }
 813         return 0;
 814 }
 815
 816 static void mlxsw_pci_eq_cmd_event(struct mlxsw_pci *mlxsw_pci, char *eqe)
 817 {
 818         mlxsw_pci->cmd.comp.status = mlxsw_pci_eqe_cmd_status_get(eqe);
 819         mlxsw_pci->cmd.comp.out_param =
 820                 ((u64) mlxsw_pci_eqe_cmd_out_param_h_get(eqe)) << 32 |
 821                 mlxsw_pci_eqe_cmd_out_param_l_get(eqe);
 822         mlxsw_pci->cmd.wait_done = true;
 823         wake_up(&mlxsw_pci->cmd.wait);
 824 }
 825
 826 static char *mlxsw_pci_eq_sw_eqe_get(struct mlxsw_pci_queue *q)
 827 {
 828         return mlxsw_pci_queue_sw_elem_get(q, mlxsw_pci_eqe_owner_get);
 829 }
 830
 831 static void mlxsw_pci_eq_tasklet(unsigned long data)
 832 {
 833         struct mlxsw_pci_queue *q = (struct mlxsw_pci_queue *) data;
 834         struct mlxsw_pci *mlxsw_pci = q->pci;
 835         u8 cq_count = mlxsw_pci_cq_count(mlxsw_pci);
 836         unsigned long active_cqns[BITS_TO_LONGS(MLXSW_PCI_CQS_MAX)];
 837         char *eqe;
 838         u8 cqn;
 839         bool cq_handle = false;
 840         int items = 0;
 841         int credits = q->count >> 1;
 842
 843         memset(&active_cqns, 0, sizeof(active_cqns));
 844
 845         while ((eqe = mlxsw_pci_eq_sw_eqe_get(q))) {
 846                 u8 event_type = mlxsw_pci_eqe_event_type_get(eqe);
 847
 848                 switch (event_type) {
 849                 case MLXSW_PCI_EQE_EVENT_TYPE_CMD:
 850                         mlxsw_pci_eq_cmd_event(mlxsw_pci, eqe);
 851                         q->u.eq.ev_cmd_count++;
 852                         break;
 853                 case MLXSW_PCI_EQE_EVENT_TYPE_COMP:
 854                         cqn = mlxsw_pci_eqe_cqn_get(eqe);
 855                         set_bit(cqn, active_cqns);
 856                         cq_handle = true;
 857                         q->u.eq.ev_comp_count++;
 858                         break;
 859                 default:
 860                         q->u.eq.ev_other_count++;
 861                 }
 862                 if (++items == credits)
 863                         break;
 864         }
 865         if (items) {
 866                 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
 867                 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
 868         }
 869
 870         if (!cq_handle)
 871                 return;
 872         for_each_set_bit(cqn, active_cqns, cq_count) {
 873                 q = mlxsw_pci_cq_get(mlxsw_pci, cqn);
 874                 mlxsw_pci_queue_tasklet_schedule(q);
 875         }
 876 }
 877
 878 struct mlxsw_pci_queue_ops {
 879         const char *name;
 880         enum mlxsw_pci_queue_type type;
 881         int (*init)(struct mlxsw_pci *mlxsw_pci, char *mbox,
 882                     struct mlxsw_pci_queue *q);
 883         void (*fini)(struct mlxsw_pci *mlxsw_pci,
 884                      struct mlxsw_pci_queue *q);
 885         void (*tasklet)(unsigned long data);
 886         int (*dbg_read)(struct seq_file *s, void *data);
 887         u16 elem_count;
 888         u8 elem_size;
 889 };
 890
 891 static const struct mlxsw_pci_queue_ops mlxsw_pci_sdq_ops = {
 892         .type           = MLXSW_PCI_QUEUE_TYPE_SDQ,
 893         .init           = mlxsw_pci_sdq_init,
 894         .fini           = mlxsw_pci_sdq_fini,
 895         .dbg_read       = mlxsw_pci_sdq_dbg_read,
 896         .elem_count     = MLXSW_PCI_WQE_COUNT,
 897         .elem_size      = MLXSW_PCI_WQE_SIZE,
 898 };
 899
 900 static const struct mlxsw_pci_queue_ops mlxsw_pci_rdq_ops = {
 901         .type           = MLXSW_PCI_QUEUE_TYPE_RDQ,
 902         .init           = mlxsw_pci_rdq_init,
 903         .fini           = mlxsw_pci_rdq_fini,
 904         .dbg_read       = mlxsw_pci_rdq_dbg_read,
 905         .elem_count     = MLXSW_PCI_WQE_COUNT,
 906         .elem_size      = MLXSW_PCI_WQE_SIZE
 907 };
 908
 909 static const struct mlxsw_pci_queue_ops mlxsw_pci_cq_ops = {
 910         .type           = MLXSW_PCI_QUEUE_TYPE_CQ,
 911         .init           = mlxsw_pci_cq_init,
 912         .fini           = mlxsw_pci_cq_fini,
 913         .tasklet        = mlxsw_pci_cq_tasklet,
 914         .dbg_read       = mlxsw_pci_cq_dbg_read,
 915         .elem_count     = MLXSW_PCI_CQE_COUNT,
 916         .elem_size      = MLXSW_PCI_CQE_SIZE
 917 };
 918
 919 static const struct mlxsw_pci_queue_ops mlxsw_pci_eq_ops = {
 920         .type           = MLXSW_PCI_QUEUE_TYPE_EQ,
 921         .init           = mlxsw_pci_eq_init,
 922         .fini           = mlxsw_pci_eq_fini,
 923         .tasklet        = mlxsw_pci_eq_tasklet,
 924         .dbg_read       = mlxsw_pci_eq_dbg_read,
 925         .elem_count     = MLXSW_PCI_EQE_COUNT,
 926         .elem_size      = MLXSW_PCI_EQE_SIZE
 927 };
 928
 929 static int mlxsw_pci_queue_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
 930                                 const struct mlxsw_pci_queue_ops *q_ops,
 931                                 struct mlxsw_pci_queue *q, u8 q_num)
 932 {
 933         struct mlxsw_pci_mem_item *mem_item = &q->mem_item;
 934         int i;
 935         int err;
 936
 937         spin_lock_init(&q->lock);
 938         q->num = q_num;
 939         q->count = q_ops->elem_count;
 940         q->elem_size = q_ops->elem_size;
 941         q->type = q_ops->type;
 942         q->pci = mlxsw_pci;
 943
 944         if (q_ops->tasklet)
 945                 tasklet_init(&q->tasklet, q_ops->tasklet, (unsigned long) q);
 946
 947         mem_item->size = MLXSW_PCI_AQ_SIZE;
 948         mem_item->buf = pci_alloc_consistent(mlxsw_pci->pdev,
 949                                              mem_item->size,
 950                                              &mem_item->mapaddr);
 951         if (!mem_item->buf)
 952                 return -ENOMEM;
 953         memset(mem_item->buf, 0, mem_item->size);
 954
 955         q->elem_info = kcalloc(q->count, sizeof(*q->elem_info), GFP_KERNEL);
 956         if (!q->elem_info) {
 957                 err = -ENOMEM;
 958                 goto err_elem_info_alloc;
 959         }
 960
 961         /* Initialize dma mapped elements info elem_info for
 962          * future easy access.
 963          */
 964         for (i = 0; i < q->count; i++) {
 965                 struct mlxsw_pci_queue_elem_info *elem_info;
 966
 967                 elem_info = mlxsw_pci_queue_elem_info_get(q, i);
 968                 elem_info->elem =
 969                         __mlxsw_pci_queue_elem_get(q, q_ops->elem_size, i);
 970         }
 971
 972         mlxsw_cmd_mbox_zero(mbox);
 973         err = q_ops->init(mlxsw_pci, mbox, q);
 974         if (err)
 975                 goto err_q_ops_init;
 976         return 0;
 977
 978 err_q_ops_init:
 979         kfree(q->elem_info);
 980 err_elem_info_alloc:
 981         pci_free_consistent(mlxsw_pci->pdev, mem_item->size,
 982                             mem_item->buf, mem_item->mapaddr);
 983         return err;
 984 }
 985
 986 static void mlxsw_pci_queue_fini(struct mlxsw_pci *mlxsw_pci,
 987                                  const struct mlxsw_pci_queue_ops *q_ops,
 988                                  struct mlxsw_pci_queue *q)
 989 {
 990         struct mlxsw_pci_mem_item *mem_item = &q->mem_item;
 991
 992         q_ops->fini(mlxsw_pci, q);
 993         kfree(q->elem_info);
 994         pci_free_consistent(mlxsw_pci->pdev, mem_item->size,
 995                             mem_item->buf, mem_item->mapaddr);
 996 }
 997
 998 static int mlxsw_pci_queue_group_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
 999                                       const struct mlxsw_pci_queue_ops *q_ops,
1000                                       u8 num_qs)
1001 {
1002         struct pci_dev *pdev = mlxsw_pci->pdev;
1003         struct mlxsw_pci_queue_type_group *queue_group;
1004         char tmp[16];
1005         int i;
1006         int err;
1007
1008         queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_ops->type);
1009         queue_group->q = kcalloc(num_qs, sizeof(*queue_group->q), GFP_KERNEL);
1010         if (!queue_group->q)
1011                 return -ENOMEM;
1012
1013         for (i = 0; i < num_qs; i++) {
1014                 err = mlxsw_pci_queue_init(mlxsw_pci, mbox, q_ops,
1015                                            &queue_group->q[i], i);
1016                 if (err)
1017                         goto err_queue_init;
1018         }
1019         queue_group->count = num_qs;
1020
1021         sprintf(tmp, "%s_stats", mlxsw_pci_queue_type_str(q_ops->type));
1022         debugfs_create_devm_seqfile(&pdev->dev, tmp, mlxsw_pci->dbg_dir,
1023                                     q_ops->dbg_read);
1024
1025         return 0;
1026
1027 err_queue_init:
1028         for (i--; i >= 0; i--)
1029                 mlxsw_pci_queue_fini(mlxsw_pci, q_ops, &queue_group->q[i]);
1030         kfree(queue_group->q);
1031         return err;
1032 }
1033
1034 static void mlxsw_pci_queue_group_fini(struct mlxsw_pci *mlxsw_pci,
1035                                        const struct mlxsw_pci_queue_ops *q_ops)
1036 {
1037         struct mlxsw_pci_queue_type_group *queue_group;
1038         int i;
1039
1040         queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_ops->type);
1041         for (i = 0; i < queue_group->count; i++)
1042                 mlxsw_pci_queue_fini(mlxsw_pci, q_ops, &queue_group->q[i]);
1043         kfree(queue_group->q);
1044 }
1045
1046 static int mlxsw_pci_aqs_init(struct mlxsw_pci *mlxsw_pci, char *mbox)
1047 {
1048         struct pci_dev *pdev = mlxsw_pci->pdev;
1049         u8 num_sdqs;
1050         u8 sdq_log2sz;
1051         u8 num_rdqs;
1052         u8 rdq_log2sz;
1053         u8 num_cqs;
1054         u8 cq_log2sz;
1055         u8 num_eqs;
1056         u8 eq_log2sz;
1057         int err;
1058
1059         mlxsw_cmd_mbox_zero(mbox);
1060         err = mlxsw_cmd_query_aq_cap(mlxsw_pci->core, mbox);
1061         if (err)
1062                 return err;
1063
1064         num_sdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_sdqs_get(mbox);
1065         sdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_sdq_sz_get(mbox);
1066         num_rdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_rdqs_get(mbox);
1067         rdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_rdq_sz_get(mbox);
1068         num_cqs = mlxsw_cmd_mbox_query_aq_cap_max_num_cqs_get(mbox);
1069         cq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_cq_sz_get(mbox);
1070         num_eqs = mlxsw_cmd_mbox_query_aq_cap_max_num_eqs_get(mbox);
1071         eq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_eq_sz_get(mbox);
1072
1073         if (num_sdqs + num_rdqs > num_cqs ||
1074             num_cqs > MLXSW_PCI_CQS_MAX || num_eqs != MLXSW_PCI_EQS_COUNT) {
1075                 dev_err(&pdev->dev, "Unsupported number of queues\n");
1076                 return -EINVAL;
1077         }
1078
1079         if ((1 << sdq_log2sz != MLXSW_PCI_WQE_COUNT) ||
1080             (1 << rdq_log2sz != MLXSW_PCI_WQE_COUNT) ||
1081             (1 << cq_log2sz != MLXSW_PCI_CQE_COUNT) ||
1082             (1 << eq_log2sz != MLXSW_PCI_EQE_COUNT)) {
1083                 dev_err(&pdev->dev, "Unsupported number of async queue descriptors\n");
1084                 return -EINVAL;
1085         }
1086
1087         err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_eq_ops,
1088                                          num_eqs);
1089         if (err) {
1090                 dev_err(&pdev->dev, "Failed to initialize event queues\n");
1091                 return err;
1092         }
1093
1094         err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_cq_ops,
1095                                          num_cqs);
1096         if (err) {
1097                 dev_err(&pdev->dev, "Failed to initialize completion queues\n");
1098                 goto err_cqs_init;
1099         }
1100
1101         err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_sdq_ops,
1102                                          num_sdqs);
1103         if (err) {
1104                 dev_err(&pdev->dev, "Failed to initialize send descriptor queues\n");
1105                 goto err_sdqs_init;
1106         }
1107
1108         err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_rdq_ops,
1109                                          num_rdqs);
1110         if (err) {
1111                 dev_err(&pdev->dev, "Failed to initialize receive descriptor queues\n");
1112                 goto err_rdqs_init;
1113         }
1114
1115         /* We have to poll in command interface until queues are initialized */
1116         mlxsw_pci->cmd.nopoll = true;
1117         return 0;
1118
1119 err_rdqs_init:
1120         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_sdq_ops);
1121 err_sdqs_init:
1122         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_cq_ops);
1123 err_cqs_init:
1124         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_eq_ops);
1125         return err;
1126 }
1127
1128 static void mlxsw_pci_aqs_fini(struct mlxsw_pci *mlxsw_pci)
1129 {
1130         mlxsw_pci->cmd.nopoll = false;
1131         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_rdq_ops);
1132         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_sdq_ops);
1133         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_cq_ops);
1134         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_eq_ops);
1135 }
1136
1137 static void
1138 mlxsw_pci_config_profile_swid_config(struct mlxsw_pci *mlxsw_pci,
1139                                      char *mbox, int index,
1140                                      const struct mlxsw_swid_config *swid)
1141 {
1142         u8 mask = 0;
1143
1144         if (swid->used_type) {
1145                 mlxsw_cmd_mbox_config_profile_swid_config_type_set(
1146                         mbox, index, swid->type);
1147                 mask |= 1;
1148         }
1149         if (swid->used_properties) {
1150                 mlxsw_cmd_mbox_config_profile_swid_config_properties_set(
1151                         mbox, index, swid->properties);
1152                 mask |= 2;
1153         }
1154         mlxsw_cmd_mbox_config_profile_swid_config_mask_set(mbox, index, mask);
1155 }
1156
1157 #define MLXSW_RESOURCES_TABLE_END_ID 0xffff
1158 #define MLXSW_MAX_SPAN_ID 0x2420
1159 #define MLXSW_MAX_LAG_ID 0x2520
1160 #define MLXSW_MAX_PORTS_IN_LAG_ID 0x2521
1161 #define MLXSW_KVD_SIZE_ID 0x1001
1162 #define MLXSW_KVD_SINGLE_MIN_SIZE_ID 0x1002
1163 #define MLXSW_KVD_DOUBLE_MIN_SIZE_ID 0x1003
1164 #define MLXSW_MAX_VIRTUAL_ROUTERS_ID 0x2C01
1165 #define MLXSW_MAX_SYSTEM_PORT_ID 0x2502
1166 #define MLXSW_MAX_VLAN_GROUPS_ID 0x2906
1167 #define MLXSW_MAX_REGIONS_ID 0x2901
1168 #define MLXSW_MAX_RIF_ID 0x2C02
1169 #define MLXSW_RESOURCES_QUERY_MAX_QUERIES 100
1170 #define MLXSW_RESOURCES_PER_QUERY 32
1171
1172 static void mlxsw_pci_resources_query_parse(int id, u64 val,
1173                                             struct mlxsw_resources *resources)
1174 {
1175         switch (id) {
1176         case MLXSW_MAX_SPAN_ID:
1177                 resources->max_span = val;
1178                 resources->max_span_valid = 1;
1179                 break;
1180         case MLXSW_MAX_LAG_ID:
1181                 resources->max_lag = val;
1182                 resources->max_lag_valid = 1;
1183                 break;
1184         case MLXSW_MAX_PORTS_IN_LAG_ID:
1185                 resources->max_ports_in_lag = val;
1186                 resources->max_ports_in_lag_valid = 1;
1187                 break;
1188         case MLXSW_KVD_SIZE_ID:
1189                 resources->kvd_size = val;
1190                 resources->kvd_size_valid = 1;
1191                 break;
1192         case MLXSW_KVD_SINGLE_MIN_SIZE_ID:
1193                 resources->kvd_single_min_size = val;
1194                 resources->kvd_single_min_size_valid = 1;
1195                 break;
1196         case MLXSW_KVD_DOUBLE_MIN_SIZE_ID:
1197                 resources->kvd_double_min_size = val;
1198                 resources->kvd_double_min_size_valid = 1;
1199                 break;
1200         case MLXSW_MAX_VIRTUAL_ROUTERS_ID:
1201                 resources->max_virtual_routers = val;
1202                 resources->max_virtual_routers_valid = 1;
1203                 break;
1204         case MLXSW_MAX_SYSTEM_PORT_ID:
1205                 resources->max_system_ports = val;
1206                 resources->max_system_ports_valid = 1;
1207                 break;
1208         case MLXSW_MAX_VLAN_GROUPS_ID:
1209                 resources->max_vlan_groups = val;
1210                 resources->max_vlan_groups_valid = 1;
1211                 break;
1212         case MLXSW_MAX_REGIONS_ID:
1213                 resources->max_regions = val;
1214                 resources->max_regions_valid = 1;
1215                 break;
1216         case MLXSW_MAX_RIF_ID:
1217                 resources->max_rif = val;
1218                 resources->max_rif_valid = 1;
1219                 break;
1220         default:
1221                 break;
1222         }
1223 }
1224
1225 static int mlxsw_pci_resources_query(struct mlxsw_pci *mlxsw_pci, char *mbox,
1226                                      struct mlxsw_resources *resources,
1227                                      u8 query_enabled)
1228 {
1229         int index, i;
1230         u64 data;
1231         u16 id;
1232         int err;
1233
1234         /* Not all the versions support resources query */
1235         if (!query_enabled)
1236                 return 0;
1237
1238         mlxsw_cmd_mbox_zero(mbox);
1239
1240         for (index = 0; index < MLXSW_RESOURCES_QUERY_MAX_QUERIES; index++) {
1241                 err = mlxsw_cmd_query_resources(mlxsw_pci->core, mbox, index);
1242                 if (err)
1243                         return err;
1244
1245                 for (i = 0; i < MLXSW_RESOURCES_PER_QUERY; i++) {
1246                         id = mlxsw_cmd_mbox_query_resource_id_get(mbox, i);
1247                         data = mlxsw_cmd_mbox_query_resource_data_get(mbox, i);
1248
1249                         if (id == MLXSW_RESOURCES_TABLE_END_ID)
1250                                 return 0;
1251
1252                         mlxsw_pci_resources_query_parse(id, data, resources);
1253                 }
1254         }
1255
1256         /* If after MLXSW_RESOURCES_QUERY_MAX_QUERIES we still didn't get
1257          * MLXSW_RESOURCES_TABLE_END_ID, something went bad in the FW.
1258          */
1259         return -EIO;
1260 }
1261
1262 static int mlxsw_pci_profile_get_kvd_sizes(const struct mlxsw_config_profile *profile,
1263                                            struct mlxsw_resources *resources)
1264 {
1265         u32 singles_size, doubles_size, linear_size;
1266
1267         if (!resources->kvd_single_min_size_valid ||
1268             !resources->kvd_double_min_size_valid ||
1269             !profile->used_kvd_split_data)
1270                 return -EIO;
1271
1272         linear_size = profile->kvd_linear_size;
1273
1274         /* The hash part is what left of the kvd without the
1275          * linear part. It is split to the single size and
1276          * double size by the parts ratio from the profile.
1277          * Both sizes must be a multiplications of the
1278          * granularity from the profile.
1279          */
1280         doubles_size = (resources->kvd_size - linear_size);
1281         doubles_size *= profile->kvd_hash_double_parts;
1282         doubles_size /= (profile->kvd_hash_double_parts +
1283                          profile->kvd_hash_single_parts);
1284         doubles_size /= profile->kvd_hash_granularity;
1285         doubles_size *= profile->kvd_hash_granularity;
1286         singles_size = resources->kvd_size - doubles_size -
1287                        linear_size;
1288
1289         /* Check results are legal. */
1290         if (singles_size < resources->kvd_single_min_size ||
1291             doubles_size < resources->kvd_double_min_size ||
1292             resources->kvd_size < linear_size)
1293                 return -EIO;
1294
1295         resources->kvd_single_size = singles_size;
1296         resources->kvd_double_size = doubles_size;
1297         resources->kvd_linear_size = linear_size;
1298
1299         return 0;
1300 }
1301
1302 static int mlxsw_pci_config_profile(struct mlxsw_pci *mlxsw_pci, char *mbox,
1303                                     const struct mlxsw_config_profile *profile,
1304                                     struct mlxsw_resources *resources)
1305 {
1306         int i;
1307         int err;
1308
1309         mlxsw_cmd_mbox_zero(mbox);
1310
1311         if (profile->used_max_vepa_channels) {
1312                 mlxsw_cmd_mbox_config_profile_set_max_vepa_channels_set(
1313                         mbox, 1);
1314                 mlxsw_cmd_mbox_config_profile_max_vepa_channels_set(
1315                         mbox, profile->max_vepa_channels);
1316         }
1317         if (profile->used_max_mid) {
1318                 mlxsw_cmd_mbox_config_profile_set_max_mid_set(
1319                         mbox, 1);
1320                 mlxsw_cmd_mbox_config_profile_max_mid_set(
1321                         mbox, profile->max_mid);
1322         }
1323         if (profile->used_max_pgt) {
1324                 mlxsw_cmd_mbox_config_profile_set_max_pgt_set(
1325                         mbox, 1);
1326                 mlxsw_cmd_mbox_config_profile_max_pgt_set(
1327                         mbox, profile->max_pgt);
1328         }
1329         if (profile->used_max_system_port) {
1330                 mlxsw_cmd_mbox_config_profile_set_max_system_port_set(
1331                         mbox, 1);
1332                 mlxsw_cmd_mbox_config_profile_max_system_port_set(
1333                         mbox, profile->max_system_port);
1334         }
1335         if (profile->used_max_vlan_groups) {
1336                 mlxsw_cmd_mbox_config_profile_set_max_vlan_groups_set(
1337                         mbox, 1);
1338                 mlxsw_cmd_mbox_config_profile_max_vlan_groups_set(
1339                         mbox, profile->max_vlan_groups);
1340         }
1341         if (profile->used_max_regions) {
1342                 mlxsw_cmd_mbox_config_profile_set_max_regions_set(
1343                         mbox, 1);
1344                 mlxsw_cmd_mbox_config_profile_max_regions_set(
1345                         mbox, profile->max_regions);
1346         }
1347         if (profile->used_flood_tables) {
1348                 mlxsw_cmd_mbox_config_profile_set_flood_tables_set(
1349                         mbox, 1);
1350                 mlxsw_cmd_mbox_config_profile_max_flood_tables_set(
1351                         mbox, profile->max_flood_tables);
1352                 mlxsw_cmd_mbox_config_profile_max_vid_flood_tables_set(
1353                         mbox, profile->max_vid_flood_tables);
1354                 mlxsw_cmd_mbox_config_profile_max_fid_offset_flood_tables_set(
1355                         mbox, profile->max_fid_offset_flood_tables);
1356                 mlxsw_cmd_mbox_config_profile_fid_offset_flood_table_size_set(
1357                         mbox, profile->fid_offset_flood_table_size);
1358                 mlxsw_cmd_mbox_config_profile_max_fid_flood_tables_set(
1359                         mbox, profile->max_fid_flood_tables);
1360                 mlxsw_cmd_mbox_config_profile_fid_flood_table_size_set(
1361                         mbox, profile->fid_flood_table_size);
1362         }
1363         if (profile->used_flood_mode) {
1364                 mlxsw_cmd_mbox_config_profile_set_flood_mode_set(
1365                         mbox, 1);
1366                 mlxsw_cmd_mbox_config_profile_flood_mode_set(
1367                         mbox, profile->flood_mode);
1368         }
1369         if (profile->used_max_ib_mc) {
1370                 mlxsw_cmd_mbox_config_profile_set_max_ib_mc_set(
1371                         mbox, 1);
1372                 mlxsw_cmd_mbox_config_profile_max_ib_mc_set(
1373                         mbox, profile->max_ib_mc);
1374         }
1375         if (profile->used_max_pkey) {
1376                 mlxsw_cmd_mbox_config_profile_set_max_pkey_set(
1377                         mbox, 1);
1378                 mlxsw_cmd_mbox_config_profile_max_pkey_set(
1379                         mbox, profile->max_pkey);
1380         }
1381         if (profile->used_ar_sec) {
1382                 mlxsw_cmd_mbox_config_profile_set_ar_sec_set(
1383                         mbox, 1);
1384                 mlxsw_cmd_mbox_config_profile_ar_sec_set(
1385                         mbox, profile->ar_sec);
1386         }
1387         if (profile->used_adaptive_routing_group_cap) {
1388                 mlxsw_cmd_mbox_config_profile_set_adaptive_routing_group_cap_set(
1389                         mbox, 1);
1390                 mlxsw_cmd_mbox_config_profile_adaptive_routing_group_cap_set(
1391                         mbox, profile->adaptive_routing_group_cap);
1392         }
1393         if (resources->kvd_size_valid) {
1394                 err = mlxsw_pci_profile_get_kvd_sizes(profile, resources);
1395                 if (err)
1396                         return err;
1397
1398                 mlxsw_cmd_mbox_config_profile_set_kvd_linear_size_set(mbox, 1);
1399                 mlxsw_cmd_mbox_config_profile_kvd_linear_size_set(mbox,
1400                                                 resources->kvd_linear_size);
1401                 mlxsw_cmd_mbox_config_profile_set_kvd_hash_single_size_set(mbox,
1402                                                                            1);
1403                 mlxsw_cmd_mbox_config_profile_kvd_hash_single_size_set(mbox,
1404                                                 resources->kvd_single_size);
1405                 mlxsw_cmd_mbox_config_profile_set_kvd_hash_double_size_set(
1406                                                                 mbox, 1);
1407                 mlxsw_cmd_mbox_config_profile_kvd_hash_double_size_set(mbox,
1408                                                 resources->kvd_double_size);
1409         }
1410
1411         for (i = 0; i < MLXSW_CONFIG_PROFILE_SWID_COUNT; i++)
1412                 mlxsw_pci_config_profile_swid_config(mlxsw_pci, mbox, i,
1413                                                      &profile->swid_config[i]);
1414
1415         return mlxsw_cmd_config_profile_set(mlxsw_pci->core, mbox);
1416 }
1417
1418 static int mlxsw_pci_boardinfo(struct mlxsw_pci *mlxsw_pci, char *mbox)
1419 {
1420         struct mlxsw_bus_info *bus_info = &mlxsw_pci->bus_info;
1421         int err;
1422
1423         mlxsw_cmd_mbox_zero(mbox);
1424         err = mlxsw_cmd_boardinfo(mlxsw_pci->core, mbox);
1425         if (err)
1426                 return err;
1427         mlxsw_cmd_mbox_boardinfo_vsd_memcpy_from(mbox, bus_info->vsd);
1428         mlxsw_cmd_mbox_boardinfo_psid_memcpy_from(mbox, bus_info->psid);
1429         return 0;
1430 }
1431
1432 static int mlxsw_pci_fw_area_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
1433                                   u16 num_pages)
1434 {
1435         struct mlxsw_pci_mem_item *mem_item;
1436         int nent = 0;
1437         int i;
1438         int err;
1439
1440         mlxsw_pci->fw_area.items = kcalloc(num_pages, sizeof(*mem_item),
1441                                            GFP_KERNEL);
1442         if (!mlxsw_pci->fw_area.items)
1443                 return -ENOMEM;
1444         mlxsw_pci->fw_area.count = num_pages;
1445
1446         mlxsw_cmd_mbox_zero(mbox);
1447         for (i = 0; i < num_pages; i++) {
1448                 mem_item = &mlxsw_pci->fw_area.items[i];
1449
1450                 mem_item->size = MLXSW_PCI_PAGE_SIZE;
1451                 mem_item->buf = pci_alloc_consistent(mlxsw_pci->pdev,
1452                                                      mem_item->size,
1453                                                      &mem_item->mapaddr);
1454                 if (!mem_item->buf) {
1455                         err = -ENOMEM;
1456                         goto err_alloc;
1457                 }
1458                 mlxsw_cmd_mbox_map_fa_pa_set(mbox, nent, mem_item->mapaddr);
1459                 mlxsw_cmd_mbox_map_fa_log2size_set(mbox, nent, 0); /* 1 page */
1460                 if (++nent == MLXSW_CMD_MAP_FA_VPM_ENTRIES_MAX) {
1461                         err = mlxsw_cmd_map_fa(mlxsw_pci->core, mbox, nent);
1462                         if (err)
1463                                 goto err_cmd_map_fa;
1464                         nent = 0;
1465                         mlxsw_cmd_mbox_zero(mbox);
1466                 }
1467         }
1468
1469         if (nent) {
1470                 err = mlxsw_cmd_map_fa(mlxsw_pci->core, mbox, nent);
1471                 if (err)
1472                         goto err_cmd_map_fa;
1473         }
1474
1475         return 0;
1476
1477 err_cmd_map_fa:
1478 err_alloc:
1479         for (i--; i >= 0; i--) {
1480                 mem_item = &mlxsw_pci->fw_area.items[i];
1481
1482                 pci_free_consistent(mlxsw_pci->pdev, mem_item->size,
1483                                     mem_item->buf, mem_item->mapaddr);
1484         }
1485         kfree(mlxsw_pci->fw_area.items);
1486         return err;
1487 }
1488
1489 static void mlxsw_pci_fw_area_fini(struct mlxsw_pci *mlxsw_pci)
1490 {
1491         struct mlxsw_pci_mem_item *mem_item;
1492         int i;
1493
1494         mlxsw_cmd_unmap_fa(mlxsw_pci->core);
1495
1496         for (i = 0; i < mlxsw_pci->fw_area.count; i++) {
1497                 mem_item = &mlxsw_pci->fw_area.items[i];
1498
1499                 pci_free_consistent(mlxsw_pci->pdev, mem_item->size,
1500                                     mem_item->buf, mem_item->mapaddr);
1501         }
1502         kfree(mlxsw_pci->fw_area.items);
1503 }
1504
1505 static irqreturn_t mlxsw_pci_eq_irq_handler(int irq, void *dev_id)
1506 {
1507         struct mlxsw_pci *mlxsw_pci = dev_id;
1508         struct mlxsw_pci_queue *q;
1509         int i;
1510
1511         for (i = 0; i < MLXSW_PCI_EQS_COUNT; i++) {
1512                 q = mlxsw_pci_eq_get(mlxsw_pci, i);
1513                 mlxsw_pci_queue_tasklet_schedule(q);
1514         }
1515         return IRQ_HANDLED;
1516 }
1517
1518 static int mlxsw_pci_mbox_alloc(struct mlxsw_pci *mlxsw_pci,
1519                                 struct mlxsw_pci_mem_item *mbox)
1520 {
1521         struct pci_dev *pdev = mlxsw_pci->pdev;
1522         int err = 0;
1523
1524         mbox->size = MLXSW_CMD_MBOX_SIZE;
1525         mbox->buf = pci_alloc_consistent(pdev, MLXSW_CMD_MBOX_SIZE,
1526                                          &mbox->mapaddr);
1527         if (!mbox->buf) {
1528                 dev_err(&pdev->dev, "Failed allocating memory for mailbox\n");
1529                 err = -ENOMEM;
1530         }
1531
1532         return err;
1533 }
1534
1535 static void mlxsw_pci_mbox_free(struct mlxsw_pci *mlxsw_pci,
1536                                 struct mlxsw_pci_mem_item *mbox)
1537 {
1538         struct pci_dev *pdev = mlxsw_pci->pdev;
1539
1540         pci_free_consistent(pdev, MLXSW_CMD_MBOX_SIZE, mbox->buf,
1541                             mbox->mapaddr);
1542 }
1543
1544 static int mlxsw_pci_init(void *bus_priv, struct mlxsw_core *mlxsw_core,
1545                           const struct mlxsw_config_profile *profile,
1546                           struct mlxsw_resources *resources)
1547 {
1548         struct mlxsw_pci *mlxsw_pci = bus_priv;
1549         struct pci_dev *pdev = mlxsw_pci->pdev;
1550         char *mbox;
1551         u16 num_pages;
1552         int err;
1553
1554         mutex_init(&mlxsw_pci->cmd.lock);
1555         init_waitqueue_head(&mlxsw_pci->cmd.wait);
1556
1557         mlxsw_pci->core = mlxsw_core;
1558
1559         mbox = mlxsw_cmd_mbox_alloc();
1560         if (!mbox)
1561                 return -ENOMEM;
1562
1563         err = mlxsw_pci_mbox_alloc(mlxsw_pci, &mlxsw_pci->cmd.in_mbox);
1564         if (err)
1565                 goto mbox_put;
1566
1567         err = mlxsw_pci_mbox_alloc(mlxsw_pci, &mlxsw_pci->cmd.out_mbox);
1568         if (err)
1569                 goto err_out_mbox_alloc;
1570
1571         err = mlxsw_cmd_query_fw(mlxsw_core, mbox);
1572         if (err)
1573                 goto err_query_fw;
1574
1575         mlxsw_pci->bus_info.fw_rev.major =
1576                 mlxsw_cmd_mbox_query_fw_fw_rev_major_get(mbox);
1577         mlxsw_pci->bus_info.fw_rev.minor =
1578                 mlxsw_cmd_mbox_query_fw_fw_rev_minor_get(mbox);
1579         mlxsw_pci->bus_info.fw_rev.subminor =
1580                 mlxsw_cmd_mbox_query_fw_fw_rev_subminor_get(mbox);
1581
1582         if (mlxsw_cmd_mbox_query_fw_cmd_interface_rev_get(mbox) != 1) {
1583                 dev_err(&pdev->dev, "Unsupported cmd interface revision ID queried from hw\n");
1584                 err = -EINVAL;
1585                 goto err_iface_rev;
1586         }
1587         if (mlxsw_cmd_mbox_query_fw_doorbell_page_bar_get(mbox) != 0) {
1588                 dev_err(&pdev->dev, "Unsupported doorbell page bar queried from hw\n");
1589                 err = -EINVAL;
1590                 goto err_doorbell_page_bar;
1591         }
1592
1593         mlxsw_pci->doorbell_offset =
1594                 mlxsw_cmd_mbox_query_fw_doorbell_page_offset_get(mbox);
1595
1596         num_pages = mlxsw_cmd_mbox_query_fw_fw_pages_get(mbox);
1597         err = mlxsw_pci_fw_area_init(mlxsw_pci, mbox, num_pages);
1598         if (err)
1599                 goto err_fw_area_init;
1600
1601         err = mlxsw_pci_boardinfo(mlxsw_pci, mbox);
1602         if (err)
1603                 goto err_boardinfo;
1604
1605         err = mlxsw_pci_resources_query(mlxsw_pci, mbox, resources,
1606                                         profile->resource_query_enable);
1607         if (err)
1608                 goto err_query_resources;
1609
1610         err = mlxsw_pci_config_profile(mlxsw_pci, mbox, profile, resources);
1611         if (err)
1612                 goto err_config_profile;
1613
1614         err = mlxsw_pci_aqs_init(mlxsw_pci, mbox);
1615         if (err)
1616                 goto err_aqs_init;
1617
1618         err = request_irq(mlxsw_pci->msix_entry.vector,
1619                           mlxsw_pci_eq_irq_handler, 0,
1620                           mlxsw_pci_driver_name, mlxsw_pci);
1621         if (err) {
1622                 dev_err(&pdev->dev, "IRQ request failed\n");
1623                 goto err_request_eq_irq;
1624         }
1625
1626         goto mbox_put;
1627
1628 err_request_eq_irq:
1629         mlxsw_pci_aqs_fini(mlxsw_pci);
1630 err_aqs_init:
1631 err_config_profile:
1632 err_query_resources:
1633 err_boardinfo:
1634         mlxsw_pci_fw_area_fini(mlxsw_pci);
1635 err_fw_area_init:
1636 err_doorbell_page_bar:
1637 err_iface_rev:
1638 err_query_fw:
1639         mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.out_mbox);
1640 err_out_mbox_alloc:
1641         mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.in_mbox);
1642 mbox_put:
1643         mlxsw_cmd_mbox_free(mbox);
1644         return err;
1645 }
1646
1647 static void mlxsw_pci_fini(void *bus_priv)
1648 {
1649         struct mlxsw_pci *mlxsw_pci = bus_priv;
1650
1651         free_irq(mlxsw_pci->msix_entry.vector, mlxsw_pci);
1652         mlxsw_pci_aqs_fini(mlxsw_pci);
1653         mlxsw_pci_fw_area_fini(mlxsw_pci);
1654         mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.out_mbox);
1655         mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.in_mbox);
1656 }
1657
1658 static struct mlxsw_pci_queue *
1659 mlxsw_pci_sdq_pick(struct mlxsw_pci *mlxsw_pci,
1660                    const struct mlxsw_tx_info *tx_info)
1661 {
1662         u8 sdqn = tx_info->local_port % mlxsw_pci_sdq_count(mlxsw_pci);
1663
1664         return mlxsw_pci_sdq_get(mlxsw_pci, sdqn);
1665 }
1666
1667 static bool mlxsw_pci_skb_transmit_busy(void *bus_priv,
1668                                         const struct mlxsw_tx_info *tx_info)
1669 {
1670         struct mlxsw_pci *mlxsw_pci = bus_priv;
1671         struct mlxsw_pci_queue *q = mlxsw_pci_sdq_pick(mlxsw_pci, tx_info);
1672
1673         return !mlxsw_pci_queue_elem_info_producer_get(q);
1674 }
1675
1676 static int mlxsw_pci_skb_transmit(void *bus_priv, struct sk_buff *skb,
1677                                   const struct mlxsw_tx_info *tx_info)
1678 {
1679         struct mlxsw_pci *mlxsw_pci = bus_priv;
1680         struct mlxsw_pci_queue *q;
1681         struct mlxsw_pci_queue_elem_info *elem_info;
1682         char *wqe;
1683         int i;
1684         int err;
1685
1686         if (skb_shinfo(skb)->nr_frags > MLXSW_PCI_WQE_SG_ENTRIES - 1) {
1687                 err = skb_linearize(skb);
1688                 if (err)
1689                         return err;
1690         }
1691
1692         q = mlxsw_pci_sdq_pick(mlxsw_pci, tx_info);
1693         spin_lock_bh(&q->lock);
1694         elem_info = mlxsw_pci_queue_elem_info_producer_get(q);
1695         if (!elem_info) {
1696                 /* queue is full */
1697                 err = -EAGAIN;
1698                 goto unlock;
1699         }
1700         elem_info->u.sdq.skb = skb;
1701
1702         wqe = elem_info->elem;
1703         mlxsw_pci_wqe_c_set(wqe, 1); /* always report completion */
1704         mlxsw_pci_wqe_lp_set(wqe, !!tx_info->is_emad);
1705         mlxsw_pci_wqe_type_set(wqe, MLXSW_PCI_WQE_TYPE_ETHERNET);
1706
1707         err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, 0, skb->data,
1708                                      skb_headlen(skb), DMA_TO_DEVICE);
1709         if (err)
1710                 goto unlock;
1711
1712         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1713                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1714
1715                 err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, i + 1,
1716                                              skb_frag_address(frag),
1717                                              skb_frag_size(frag),
1718                                              DMA_TO_DEVICE);
1719                 if (err)
1720                         goto unmap_frags;
1721         }
1722
1723         /* Set unused sq entries byte count to zero. */
1724         for (i++; i < MLXSW_PCI_WQE_SG_ENTRIES; i++)
1725                 mlxsw_pci_wqe_byte_count_set(wqe, i, 0);
1726
1727         /* Everything is set up, ring producer doorbell to get HW going */
1728         q->producer_counter++;
1729         mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
1730
1731         goto unlock;
1732
1733 unmap_frags:
1734         for (; i >= 0; i--)
1735                 mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, i, DMA_TO_DEVICE);
1736 unlock:
1737         spin_unlock_bh(&q->lock);
1738         return err;
1739 }
1740
1741 static int mlxsw_pci_cmd_exec(void *bus_priv, u16 opcode, u8 opcode_mod,
1742                               u32 in_mod, bool out_mbox_direct,
1743                               char *in_mbox, size_t in_mbox_size,
1744                               char *out_mbox, size_t out_mbox_size,
1745                               u8 *p_status)
1746 {
1747         struct mlxsw_pci *mlxsw_pci = bus_priv;
1748         dma_addr_t in_mapaddr = mlxsw_pci->cmd.in_mbox.mapaddr;
1749         dma_addr_t out_mapaddr = mlxsw_pci->cmd.out_mbox.mapaddr;
1750         bool evreq = mlxsw_pci->cmd.nopoll;
1751         unsigned long timeout = msecs_to_jiffies(MLXSW_PCI_CIR_TIMEOUT_MSECS);
1752         bool *p_wait_done = &mlxsw_pci->cmd.wait_done;
1753         int err;
1754
1755         *p_status = MLXSW_CMD_STATUS_OK;
1756
1757         err = mutex_lock_interruptible(&mlxsw_pci->cmd.lock);
1758         if (err)
1759                 return err;
1760
1761         if (in_mbox)
1762                 memcpy(mlxsw_pci->cmd.in_mbox.buf, in_mbox, in_mbox_size);
1763         mlxsw_pci_write32(mlxsw_pci, CIR_IN_PARAM_HI, upper_32_bits(in_mapaddr));
1764         mlxsw_pci_write32(mlxsw_pci, CIR_IN_PARAM_LO, lower_32_bits(in_mapaddr));
1765
1766         mlxsw_pci_write32(mlxsw_pci, CIR_OUT_PARAM_HI, upper_32_bits(out_mapaddr));
1767         mlxsw_pci_write32(mlxsw_pci, CIR_OUT_PARAM_LO, lower_32_bits(out_mapaddr));
1768
1769         mlxsw_pci_write32(mlxsw_pci, CIR_IN_MODIFIER, in_mod);
1770         mlxsw_pci_write32(mlxsw_pci, CIR_TOKEN, 0);
1771
1772         *p_wait_done = false;
1773
1774         wmb(); /* all needs to be written before we write control register */
1775         mlxsw_pci_write32(mlxsw_pci, CIR_CTRL,
1776                           MLXSW_PCI_CIR_CTRL_GO_BIT |
1777                           (evreq ? MLXSW_PCI_CIR_CTRL_EVREQ_BIT : 0) |
1778                           (opcode_mod << MLXSW_PCI_CIR_CTRL_OPCODE_MOD_SHIFT) |
1779                           opcode);
1780
1781         if (!evreq) {
1782                 unsigned long end;
1783
1784                 end = jiffies + timeout;
1785                 do {
1786                         u32 ctrl = mlxsw_pci_read32(mlxsw_pci, CIR_CTRL);
1787
1788                         if (!(ctrl & MLXSW_PCI_CIR_CTRL_GO_BIT)) {
1789                                 *p_wait_done = true;
1790                                 *p_status = ctrl >> MLXSW_PCI_CIR_CTRL_STATUS_SHIFT;
1791                                 break;
1792                         }
1793                         cond_resched();
1794                 } while (time_before(jiffies, end));
1795         } else {
1796                 wait_event_timeout(mlxsw_pci->cmd.wait, *p_wait_done, timeout);
1797                 *p_status = mlxsw_pci->cmd.comp.status;
1798         }
1799
1800         err = 0;
1801         if (*p_wait_done) {
1802                 if (*p_status)
1803                         err = -EIO;
1804         } else {
1805                 err = -ETIMEDOUT;
1806         }
1807
1808         if (!err && out_mbox && out_mbox_direct) {
1809                 /* Some commands don't use output param as address to mailbox
1810                  * but they store output directly into registers. In that case,
1811                  * copy registers into mbox buffer.
1812                  */
1813                 __be32 tmp;
1814
1815                 if (!evreq) {
1816                         tmp = cpu_to_be32(mlxsw_pci_read32(mlxsw_pci,
1817                                                            CIR_OUT_PARAM_HI));
1818                         memcpy(out_mbox, &tmp, sizeof(tmp));
1819                         tmp = cpu_to_be32(mlxsw_pci_read32(mlxsw_pci,
1820                                                            CIR_OUT_PARAM_LO));
1821                         memcpy(out_mbox + sizeof(tmp), &tmp, sizeof(tmp));
1822                 }
1823         } else if (!err && out_mbox) {
1824                 memcpy(out_mbox, mlxsw_pci->cmd.out_mbox.buf, out_mbox_size);
1825         }
1826
1827         mutex_unlock(&mlxsw_pci->cmd.lock);
1828
1829         return err;
1830 }
1831
1832 static const struct mlxsw_bus mlxsw_pci_bus = {
1833         .kind                   = "pci",
1834         .init                   = mlxsw_pci_init,
1835         .fini                   = mlxsw_pci_fini,
1836         .skb_transmit_busy      = mlxsw_pci_skb_transmit_busy,
1837         .skb_transmit           = mlxsw_pci_skb_transmit,
1838         .cmd_exec               = mlxsw_pci_cmd_exec,
1839 };
1840
1841 static int mlxsw_pci_sw_reset(struct mlxsw_pci *mlxsw_pci,
1842                               const struct pci_device_id *id)
1843 {
1844         unsigned long end;
1845
1846         mlxsw_pci_write32(mlxsw_pci, SW_RESET, MLXSW_PCI_SW_RESET_RST_BIT);
1847         if (id->device == PCI_DEVICE_ID_MELLANOX_SWITCHX2) {
1848                 msleep(MLXSW_PCI_SW_RESET_TIMEOUT_MSECS);
1849                 return 0;
1850         }
1851
1852         wmb(); /* reset needs to be written before we read control register */
1853         end = jiffies + msecs_to_jiffies(MLXSW_PCI_SW_RESET_TIMEOUT_MSECS);
1854         do {
1855                 u32 val = mlxsw_pci_read32(mlxsw_pci, FW_READY);
1856
1857                 if ((val & MLXSW_PCI_FW_READY_MASK) == MLXSW_PCI_FW_READY_MAGIC)
1858                         break;
1859                 cond_resched();
1860         } while (time_before(jiffies, end));
1861         return 0;
1862 }
1863
1864 static int mlxsw_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1865 {
1866         struct mlxsw_pci *mlxsw_pci;
1867         int err;
1868
1869         mlxsw_pci = kzalloc(sizeof(*mlxsw_pci), GFP_KERNEL);
1870         if (!mlxsw_pci)
1871                 return -ENOMEM;
1872
1873         err = pci_enable_device(pdev);
1874         if (err) {
1875                 dev_err(&pdev->dev, "pci_enable_device failed\n");
1876                 goto err_pci_enable_device;
1877         }
1878
1879         err = pci_request_regions(pdev, mlxsw_pci_driver_name);
1880         if (err) {
1881                 dev_err(&pdev->dev, "pci_request_regions failed\n");
1882                 goto err_pci_request_regions;
1883         }
1884
1885         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1886         if (!err) {
1887                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1888                 if (err) {
1889                         dev_err(&pdev->dev, "pci_set_consistent_dma_mask failed\n");
1890                         goto err_pci_set_dma_mask;
1891                 }
1892         } else {
1893                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1894                 if (err) {
1895                         dev_err(&pdev->dev, "pci_set_dma_mask failed\n");
1896                         goto err_pci_set_dma_mask;
1897                 }
1898         }
1899
1900         if (pci_resource_len(pdev, 0) < MLXSW_PCI_BAR0_SIZE) {
1901                 dev_err(&pdev->dev, "invalid PCI region size\n");
1902                 err = -EINVAL;
1903                 goto err_pci_resource_len_check;
1904         }
1905
1906         mlxsw_pci->hw_addr = ioremap(pci_resource_start(pdev, 0),
1907                                      pci_resource_len(pdev, 0));
1908         if (!mlxsw_pci->hw_addr) {
1909                 dev_err(&pdev->dev, "ioremap failed\n");
1910                 err = -EIO;
1911                 goto err_ioremap;
1912         }
1913         pci_set_master(pdev);
1914
1915         mlxsw_pci->pdev = pdev;
1916         pci_set_drvdata(pdev, mlxsw_pci);
1917
1918         err = mlxsw_pci_sw_reset(mlxsw_pci, id);
1919         if (err) {
1920                 dev_err(&pdev->dev, "Software reset failed\n");
1921                 goto err_sw_reset;
1922         }
1923
1924         err = pci_enable_msix_exact(pdev, &mlxsw_pci->msix_entry, 1);
1925         if (err) {
1926                 dev_err(&pdev->dev, "MSI-X init failed\n");
1927                 goto err_msix_init;
1928         }
1929
1930         mlxsw_pci->bus_info.device_kind = mlxsw_pci_device_kind_get(id);
1931         mlxsw_pci->bus_info.device_name = pci_name(mlxsw_pci->pdev);
1932         mlxsw_pci->bus_info.dev = &pdev->dev;
1933
1934         mlxsw_pci->dbg_dir = debugfs_create_dir(mlxsw_pci->bus_info.device_name,
1935                                                 mlxsw_pci_dbg_root);
1936         if (!mlxsw_pci->dbg_dir) {
1937                 dev_err(&pdev->dev, "Failed to create debugfs dir\n");
1938                 err = -ENOMEM;
1939                 goto err_dbg_create_dir;
1940         }
1941
1942         err = mlxsw_core_bus_device_register(&mlxsw_pci->bus_info,
1943                                              &mlxsw_pci_bus, mlxsw_pci);
1944         if (err) {
1945                 dev_err(&pdev->dev, "cannot register bus device\n");
1946                 goto err_bus_device_register;
1947         }
1948
1949         return 0;
1950
1951 err_bus_device_register:
1952         debugfs_remove_recursive(mlxsw_pci->dbg_dir);
1953 err_dbg_create_dir:
1954         pci_disable_msix(mlxsw_pci->pdev);
1955 err_msix_init:
1956 err_sw_reset:
1957         iounmap(mlxsw_pci->hw_addr);
1958 err_ioremap:
1959 err_pci_resource_len_check:
1960 err_pci_set_dma_mask:
1961         pci_release_regions(pdev);
1962 err_pci_request_regions:
1963         pci_disable_device(pdev);
1964 err_pci_enable_device:
1965         kfree(mlxsw_pci);
1966         return err;
1967 }
1968
1969 static void mlxsw_pci_remove(struct pci_dev *pdev)
1970 {
1971         struct mlxsw_pci *mlxsw_pci = pci_get_drvdata(pdev);
1972
1973         mlxsw_core_bus_device_unregister(mlxsw_pci->core);
1974         debugfs_remove_recursive(mlxsw_pci->dbg_dir);
1975         pci_disable_msix(mlxsw_pci->pdev);
1976         iounmap(mlxsw_pci->hw_addr);
1977         pci_release_regions(mlxsw_pci->pdev);
1978         pci_disable_device(mlxsw_pci->pdev);
1979         kfree(mlxsw_pci);
1980 }
1981
1982 static struct pci_driver mlxsw_pci_driver = {
1983         .name           = mlxsw_pci_driver_name,
1984         .id_table       = mlxsw_pci_id_table,
1985         .probe          = mlxsw_pci_probe,
1986         .remove         = mlxsw_pci_remove,
1987 };
1988
1989 static int __init mlxsw_pci_module_init(void)
1990 {
1991         int err;
1992
1993         mlxsw_pci_dbg_root = debugfs_create_dir(mlxsw_pci_driver_name, NULL);
1994         if (!mlxsw_pci_dbg_root)
1995                 return -ENOMEM;
1996         err = pci_register_driver(&mlxsw_pci_driver);
1997         if (err)
1998                 goto err_register_driver;
1999         return 0;
2000
2001 err_register_driver:
2002         debugfs_remove_recursive(mlxsw_pci_dbg_root);
2003         return err;
2004 }
2005
2006 static void __exit mlxsw_pci_module_exit(void)
2007 {
2008         pci_unregister_driver(&mlxsw_pci_driver);
2009         debugfs_remove_recursive(mlxsw_pci_dbg_root);
2010 }
2011
2012 module_init(mlxsw_pci_module_init);
2013 module_exit(mlxsw_pci_module_exit);
2014
2015 MODULE_LICENSE("Dual BSD/GPL");
2016 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
2017 MODULE_DESCRIPTION("Mellanox switch PCI interface driver");
2018 MODULE_DEVICE_TABLE(pci, mlxsw_pci_id_table);