drivers/net/ethernet/mellanox/mlxsw/switchx2.c

   1 /*
   2  * drivers/net/ethernet/mellanox/mlxsw/switchx2.c
   3  * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
   4  * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
   5  * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
   6  * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions are met:
  10  *
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  * 3. Neither the names of the copyright holders nor the names of its
  17  *    contributors may be used to endorse or promote products derived from
  18  *    this software without specific prior written permission.
  19  *
  20  * Alternatively, this software may be distributed under the terms of the
  21  * GNU General Public License ("GPL") version 2 as published by the Free
  22  * Software Foundation.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  27  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  28  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  29  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  30  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  31  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  32  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  33  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  34  * POSSIBILITY OF SUCH DAMAGE.
  35  */
  36
  37 #include <linux/kernel.h>
  38 #include <linux/module.h>
  39 #include <linux/types.h>
  40 #include <linux/netdevice.h>
  41 #include <linux/etherdevice.h>
  42 #include <linux/slab.h>
  43 #include <linux/device.h>
  44 #include <linux/skbuff.h>
  45 #include <linux/if_vlan.h>
  46 #include <net/switchdev.h>
  47 #include <generated/utsrelease.h>
  48
  49 #include "core.h"
  50 #include "reg.h"
  51 #include "port.h"
  52 #include "trap.h"
  53 #include "txheader.h"
  54
  55 static const char mlxsw_sx_driver_name[] = "mlxsw_switchx2";
  56 static const char mlxsw_sx_driver_version[] = "1.0";
  57
  58 struct mlxsw_sx_port;
  59
  60 #define MLXSW_SW_HW_ID_LEN 6
  61
  62 struct mlxsw_sx {
  63         struct mlxsw_sx_port **ports;
  64         struct mlxsw_core *core;
  65         const struct mlxsw_bus_info *bus_info;
  66         u8 hw_id[MLXSW_SW_HW_ID_LEN];
  67 };
  68
  69 struct mlxsw_sx_port_pcpu_stats {
  70         u64                     rx_packets;
  71         u64                     rx_bytes;
  72         u64                     tx_packets;
  73         u64                     tx_bytes;
  74         struct u64_stats_sync   syncp;
  75         u32                     tx_dropped;
  76 };
  77
  78 struct mlxsw_sx_port {
  79         struct net_device *dev;
  80         struct mlxsw_sx_port_pcpu_stats __percpu *pcpu_stats;
  81         struct mlxsw_sx *mlxsw_sx;
  82         u8 local_port;
  83 };
  84
  85 /* tx_hdr_version
  86  * Tx header version.
  87  * Must be set to 0.
  88  */
  89 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
  90
  91 /* tx_hdr_ctl
  92  * Packet control type.
  93  * 0 - Ethernet control (e.g. EMADs, LACP)
  94  * 1 - Ethernet data
  95  */
  96 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
  97
  98 /* tx_hdr_proto
  99  * Packet protocol type. Must be set to 1 (Ethernet).
 100  */
 101 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
 102
 103 /* tx_hdr_etclass
 104  * Egress TClass to be used on the egress device on the egress port.
 105  * The MSB is specified in the 'ctclass3' field.
 106  * Range is 0-15, where 15 is the highest priority.
 107  */
 108 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 18, 3);
 109
 110 /* tx_hdr_swid
 111  * Switch partition ID.
 112  */
 113 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
 114
 115 /* tx_hdr_port_mid
 116  * Destination local port for unicast packets.
 117  * Destination multicast ID for multicast packets.
 118  *
 119  * Control packets are directed to a specific egress port, while data
 120  * packets are transmitted through the CPU port (0) into the switch partition,
 121  * where forwarding rules are applied.
 122  */
 123 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
 124
 125 /* tx_hdr_ctclass3
 126  * See field 'etclass'.
 127  */
 128 MLXSW_ITEM32(tx, hdr, ctclass3, 0x04, 14, 1);
 129
 130 /* tx_hdr_rdq
 131  * RDQ for control packets sent to remote CPU.
 132  * Must be set to 0x1F for EMADs, otherwise 0.
 133  */
 134 MLXSW_ITEM32(tx, hdr, rdq, 0x04, 9, 5);
 135
 136 /* tx_hdr_cpu_sig
 137  * Signature control for packets going to CPU. Must be set to 0.
 138  */
 139 MLXSW_ITEM32(tx, hdr, cpu_sig, 0x04, 0, 9);
 140
 141 /* tx_hdr_sig
 142  * Stacking protocl signature. Must be set to 0xE0E0.
 143  */
 144 MLXSW_ITEM32(tx, hdr, sig, 0x0C, 16, 16);
 145
 146 /* tx_hdr_stclass
 147  * Stacking TClass.
 148  */
 149 MLXSW_ITEM32(tx, hdr, stclass, 0x0C, 13, 3);
 150
 151 /* tx_hdr_emad
 152  * EMAD bit. Must be set for EMADs.
 153  */
 154 MLXSW_ITEM32(tx, hdr, emad, 0x0C, 5, 1);
 155
 156 /* tx_hdr_type
 157  * 0 - Data packets
 158  * 6 - Control packets
 159  */
 160 MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
 161
 162 static void mlxsw_sx_txhdr_construct(struct sk_buff *skb,
 163                                      const struct mlxsw_tx_info *tx_info)
 164 {
 165         char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
 166         bool is_emad = tx_info->is_emad;
 167
 168         memset(txhdr, 0, MLXSW_TXHDR_LEN);
 169
 170         /* We currently set default values for the egress tclass (QoS). */
 171         mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_0);
 172         mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
 173         mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
 174         mlxsw_tx_hdr_etclass_set(txhdr, is_emad ? MLXSW_TXHDR_ETCLASS_6 :
 175                                                   MLXSW_TXHDR_ETCLASS_5);
 176         mlxsw_tx_hdr_swid_set(txhdr, 0);
 177         mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
 178         mlxsw_tx_hdr_ctclass3_set(txhdr, MLXSW_TXHDR_CTCLASS3);
 179         mlxsw_tx_hdr_rdq_set(txhdr, is_emad ? MLXSW_TXHDR_RDQ_EMAD :
 180                                               MLXSW_TXHDR_RDQ_OTHER);
 181         mlxsw_tx_hdr_cpu_sig_set(txhdr, MLXSW_TXHDR_CPU_SIG);
 182         mlxsw_tx_hdr_sig_set(txhdr, MLXSW_TXHDR_SIG);
 183         mlxsw_tx_hdr_stclass_set(txhdr, MLXSW_TXHDR_STCLASS_NONE);
 184         mlxsw_tx_hdr_emad_set(txhdr, is_emad ? MLXSW_TXHDR_EMAD :
 185                                                MLXSW_TXHDR_NOT_EMAD);
 186         mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
 187 }
 188
 189 static int mlxsw_sx_port_admin_status_set(struct mlxsw_sx_port *mlxsw_sx_port,
 190                                           bool is_up)
 191 {
 192         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 193         char paos_pl[MLXSW_REG_PAOS_LEN];
 194
 195         mlxsw_reg_paos_pack(paos_pl, mlxsw_sx_port->local_port,
 196                             is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
 197                             MLXSW_PORT_ADMIN_STATUS_DOWN);
 198         return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(paos), paos_pl);
 199 }
 200
 201 static int mlxsw_sx_port_oper_status_get(struct mlxsw_sx_port *mlxsw_sx_port,
 202                                          bool *p_is_up)
 203 {
 204         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 205         char paos_pl[MLXSW_REG_PAOS_LEN];
 206         u8 oper_status;
 207         int err;
 208
 209         mlxsw_reg_paos_pack(paos_pl, mlxsw_sx_port->local_port, 0);
 210         err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(paos), paos_pl);
 211         if (err)
 212                 return err;
 213         oper_status = mlxsw_reg_paos_oper_status_get(paos_pl);
 214         *p_is_up = oper_status == MLXSW_PORT_ADMIN_STATUS_UP ? true : false;
 215         return 0;
 216 }
 217
 218 static int mlxsw_sx_port_mtu_set(struct mlxsw_sx_port *mlxsw_sx_port, u16 mtu)
 219 {
 220         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 221         char pmtu_pl[MLXSW_REG_PMTU_LEN];
 222         int max_mtu;
 223         int err;
 224
 225         mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
 226         mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sx_port->local_port, 0);
 227         err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(pmtu), pmtu_pl);
 228         if (err)
 229                 return err;
 230         max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
 231
 232         if (mtu > max_mtu)
 233                 return -EINVAL;
 234
 235         mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sx_port->local_port, mtu);
 236         return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(pmtu), pmtu_pl);
 237 }
 238
 239 static int mlxsw_sx_port_swid_set(struct mlxsw_sx_port *mlxsw_sx_port, u8 swid)
 240 {
 241         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 242         char pspa_pl[MLXSW_REG_PSPA_LEN];
 243
 244         mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sx_port->local_port);
 245         return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(pspa), pspa_pl);
 246 }
 247
 248 static int mlxsw_sx_port_module_check(struct mlxsw_sx_port *mlxsw_sx_port,
 249                                       bool *p_usable)
 250 {
 251         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 252         char pmlp_pl[MLXSW_REG_PMLP_LEN];
 253         int err;
 254
 255         mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sx_port->local_port);
 256         err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(pmlp), pmlp_pl);
 257         if (err)
 258                 return err;
 259         *p_usable = mlxsw_reg_pmlp_width_get(pmlp_pl) ? true : false;
 260         return 0;
 261 }
 262
 263 static int mlxsw_sx_port_open(struct net_device *dev)
 264 {
 265         struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
 266         int err;
 267
 268         err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, true);
 269         if (err)
 270                 return err;
 271         netif_start_queue(dev);
 272         return 0;
 273 }
 274
 275 static int mlxsw_sx_port_stop(struct net_device *dev)
 276 {
 277         struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
 278
 279         netif_stop_queue(dev);
 280         return mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
 281 }
 282
 283 static netdev_tx_t mlxsw_sx_port_xmit(struct sk_buff *skb,
 284                                       struct net_device *dev)
 285 {
 286         struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
 287         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 288         struct mlxsw_sx_port_pcpu_stats *pcpu_stats;
 289         const struct mlxsw_tx_info tx_info = {
 290                 .local_port = mlxsw_sx_port->local_port,
 291                 .is_emad = false,
 292         };
 293         struct sk_buff *skb_old = NULL;
 294         int err;
 295
 296         if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
 297                 struct sk_buff *skb_new;
 298
 299                 skb_old = skb;
 300                 skb_new = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
 301                 if (!skb_new) {
 302                         this_cpu_inc(mlxsw_sx_port->pcpu_stats->tx_dropped);
 303                         dev_kfree_skb_any(skb_old);
 304                         return NETDEV_TX_OK;
 305                 }
 306                 skb = skb_new;
 307         }
 308         mlxsw_sx_txhdr_construct(skb, &tx_info);
 309         err = mlxsw_core_skb_transmit(mlxsw_sx, skb, &tx_info);
 310         if (err == -EAGAIN) {
 311                 if (skb_old)
 312                         dev_kfree_skb_any(skb);
 313                 return NETDEV_TX_BUSY;
 314         }
 315
 316         if (skb_old)
 317                 dev_kfree_skb_any(skb_old);
 318
 319         if (!err) {
 320                 pcpu_stats = this_cpu_ptr(mlxsw_sx_port->pcpu_stats);
 321                 u64_stats_update_begin(&pcpu_stats->syncp);
 322                 pcpu_stats->tx_packets++;
 323                 pcpu_stats->tx_bytes += skb->len;
 324                 u64_stats_update_end(&pcpu_stats->syncp);
 325         } else {
 326                 this_cpu_inc(mlxsw_sx_port->pcpu_stats->tx_dropped);
 327                 dev_kfree_skb_any(skb);
 328         }
 329         return NETDEV_TX_OK;
 330 }
 331
 332 static int mlxsw_sx_port_change_mtu(struct net_device *dev, int mtu)
 333 {
 334         struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
 335         int err;
 336
 337         err = mlxsw_sx_port_mtu_set(mlxsw_sx_port, mtu);
 338         if (err)
 339                 return err;
 340         dev->mtu = mtu;
 341         return 0;
 342 }
 343
 344 static struct rtnl_link_stats64 *
 345 mlxsw_sx_port_get_stats64(struct net_device *dev,
 346                           struct rtnl_link_stats64 *stats)
 347 {
 348         struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
 349         struct mlxsw_sx_port_pcpu_stats *p;
 350         u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
 351         u32 tx_dropped = 0;
 352         unsigned int start;
 353         int i;
 354
 355         for_each_possible_cpu(i) {
 356                 p = per_cpu_ptr(mlxsw_sx_port->pcpu_stats, i);
 357                 do {
 358                         start = u64_stats_fetch_begin_irq(&p->syncp);
 359                         rx_packets      = p->rx_packets;
 360                         rx_bytes        = p->rx_bytes;
 361                         tx_packets      = p->tx_packets;
 362                         tx_bytes        = p->tx_bytes;
 363                 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
 364
 365                 stats->rx_packets       += rx_packets;
 366                 stats->rx_bytes         += rx_bytes;
 367                 stats->tx_packets       += tx_packets;
 368                 stats->tx_bytes         += tx_bytes;
 369                 /* tx_dropped is u32, updated without syncp protection. */
 370                 tx_dropped      += p->tx_dropped;
 371         }
 372         stats->tx_dropped       = tx_dropped;
 373         return stats;
 374 }
 375
 376 static const struct net_device_ops mlxsw_sx_port_netdev_ops = {
 377         .ndo_open               = mlxsw_sx_port_open,
 378         .ndo_stop               = mlxsw_sx_port_stop,
 379         .ndo_start_xmit         = mlxsw_sx_port_xmit,
 380         .ndo_change_mtu         = mlxsw_sx_port_change_mtu,
 381         .ndo_get_stats64        = mlxsw_sx_port_get_stats64,
 382 };
 383
 384 static void mlxsw_sx_port_get_drvinfo(struct net_device *dev,
 385                                       struct ethtool_drvinfo *drvinfo)
 386 {
 387         struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
 388         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 389
 390         strlcpy(drvinfo->driver, mlxsw_sx_driver_name, sizeof(drvinfo->driver));
 391         strlcpy(drvinfo->version, mlxsw_sx_driver_version,
 392                 sizeof(drvinfo->version));
 393         snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
 394                  "%d.%d.%d",
 395                  mlxsw_sx->bus_info->fw_rev.major,
 396                  mlxsw_sx->bus_info->fw_rev.minor,
 397                  mlxsw_sx->bus_info->fw_rev.subminor);
 398         strlcpy(drvinfo->bus_info, mlxsw_sx->bus_info->device_name,
 399                 sizeof(drvinfo->bus_info));
 400 }
 401
 402 struct mlxsw_sx_port_hw_stats {
 403         char str[ETH_GSTRING_LEN];
 404         u64 (*getter)(char *payload);
 405 };
 406
 407 static const struct mlxsw_sx_port_hw_stats mlxsw_sx_port_hw_stats[] = {
 408         {
 409                 .str = "a_frames_transmitted_ok",
 410                 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
 411         },
 412         {
 413                 .str = "a_frames_received_ok",
 414                 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
 415         },
 416         {
 417                 .str = "a_frame_check_sequence_errors",
 418                 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
 419         },
 420         {
 421                 .str = "a_alignment_errors",
 422                 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
 423         },
 424         {
 425                 .str = "a_octets_transmitted_ok",
 426                 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
 427         },
 428         {
 429                 .str = "a_octets_received_ok",
 430                 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
 431         },
 432         {
 433                 .str = "a_multicast_frames_xmitted_ok",
 434                 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
 435         },
 436         {
 437                 .str = "a_broadcast_frames_xmitted_ok",
 438                 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
 439         },
 440         {
 441                 .str = "a_multicast_frames_received_ok",
 442                 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
 443         },
 444         {
 445                 .str = "a_broadcast_frames_received_ok",
 446                 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
 447         },
 448         {
 449                 .str = "a_in_range_length_errors",
 450                 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
 451         },
 452         {
 453                 .str = "a_out_of_range_length_field",
 454                 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
 455         },
 456         {
 457                 .str = "a_frame_too_long_errors",
 458                 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
 459         },
 460         {
 461                 .str = "a_symbol_error_during_carrier",
 462                 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
 463         },
 464         {
 465                 .str = "a_mac_control_frames_transmitted",
 466                 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
 467         },
 468         {
 469                 .str = "a_mac_control_frames_received",
 470                 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
 471         },
 472         {
 473                 .str = "a_unsupported_opcodes_received",
 474                 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
 475         },
 476         {
 477                 .str = "a_pause_mac_ctrl_frames_received",
 478                 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
 479         },
 480         {
 481                 .str = "a_pause_mac_ctrl_frames_xmitted",
 482                 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
 483         },
 484 };
 485
 486 #define MLXSW_SX_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sx_port_hw_stats)
 487
 488 static void mlxsw_sx_port_get_strings(struct net_device *dev,
 489                                       u32 stringset, u8 *data)
 490 {
 491         u8 *p = data;
 492         int i;
 493
 494         switch (stringset) {
 495         case ETH_SS_STATS:
 496                 for (i = 0; i < MLXSW_SX_PORT_HW_STATS_LEN; i++) {
 497                         memcpy(p, mlxsw_sx_port_hw_stats[i].str,
 498                                ETH_GSTRING_LEN);
 499                         p += ETH_GSTRING_LEN;
 500                 }
 501                 break;
 502         }
 503 }
 504
 505 static void mlxsw_sx_port_get_stats(struct net_device *dev,
 506                                     struct ethtool_stats *stats, u64 *data)
 507 {
 508         struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
 509         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 510         char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
 511         int i;
 512         int err;
 513
 514         mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sx_port->local_port);
 515         err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ppcnt), ppcnt_pl);
 516         for (i = 0; i < MLXSW_SX_PORT_HW_STATS_LEN; i++)
 517                 data[i] = !err ? mlxsw_sx_port_hw_stats[i].getter(ppcnt_pl) : 0;
 518 }
 519
 520 static int mlxsw_sx_port_get_sset_count(struct net_device *dev, int sset)
 521 {
 522         switch (sset) {
 523         case ETH_SS_STATS:
 524                 return MLXSW_SX_PORT_HW_STATS_LEN;
 525         default:
 526                 return -EOPNOTSUPP;
 527         }
 528 }
 529
 530 struct mlxsw_sx_port_link_mode {
 531         u32 mask;
 532         u32 supported;
 533         u32 advertised;
 534         u32 speed;
 535 };
 536
 537 static const struct mlxsw_sx_port_link_mode mlxsw_sx_port_link_mode[] = {
 538         {
 539                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
 540                 .supported      = SUPPORTED_100baseT_Full,
 541                 .advertised     = ADVERTISED_100baseT_Full,
 542                 .speed          = 100,
 543         },
 544         {
 545                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX,
 546                 .speed          = 100,
 547         },
 548         {
 549                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
 550                                   MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
 551                 .supported      = SUPPORTED_1000baseKX_Full,
 552                 .advertised     = ADVERTISED_1000baseKX_Full,
 553                 .speed          = 1000,
 554         },
 555         {
 556                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
 557                 .supported      = SUPPORTED_10000baseT_Full,
 558                 .advertised     = ADVERTISED_10000baseT_Full,
 559                 .speed          = 10000,
 560         },
 561         {
 562                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
 563                                   MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
 564                 .supported      = SUPPORTED_10000baseKX4_Full,
 565                 .advertised     = ADVERTISED_10000baseKX4_Full,
 566                 .speed          = 10000,
 567         },
 568         {
 569                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
 570                                   MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
 571                                   MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
 572                                   MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
 573                 .supported      = SUPPORTED_10000baseKR_Full,
 574                 .advertised     = ADVERTISED_10000baseKR_Full,
 575                 .speed          = 10000,
 576         },
 577         {
 578                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
 579                 .supported      = SUPPORTED_20000baseKR2_Full,
 580                 .advertised     = ADVERTISED_20000baseKR2_Full,
 581                 .speed          = 20000,
 582         },
 583         {
 584                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
 585                 .supported      = SUPPORTED_40000baseCR4_Full,
 586                 .advertised     = ADVERTISED_40000baseCR4_Full,
 587                 .speed          = 40000,
 588         },
 589         {
 590                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
 591                 .supported      = SUPPORTED_40000baseKR4_Full,
 592                 .advertised     = ADVERTISED_40000baseKR4_Full,
 593                 .speed          = 40000,
 594         },
 595         {
 596                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
 597                 .supported      = SUPPORTED_40000baseSR4_Full,
 598                 .advertised     = ADVERTISED_40000baseSR4_Full,
 599                 .speed          = 40000,
 600         },
 601         {
 602                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
 603                 .supported      = SUPPORTED_40000baseLR4_Full,
 604                 .advertised     = ADVERTISED_40000baseLR4_Full,
 605                 .speed          = 40000,
 606         },
 607         {
 608                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR |
 609                                   MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR |
 610                                   MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
 611                 .speed          = 25000,
 612         },
 613         {
 614                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 |
 615                                   MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 |
 616                                   MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
 617                 .speed          = 50000,
 618         },
 619         {
 620                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
 621                 .supported      = SUPPORTED_56000baseKR4_Full,
 622                 .advertised     = ADVERTISED_56000baseKR4_Full,
 623                 .speed          = 56000,
 624         },
 625         {
 626                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 |
 627                                   MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
 628                                   MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
 629                                   MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
 630                 .speed          = 100000,
 631         },
 632 };
 633
 634 #define MLXSW_SX_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sx_port_link_mode)
 635
 636 static u32 mlxsw_sx_from_ptys_supported_port(u32 ptys_eth_proto)
 637 {
 638         if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
 639                               MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
 640                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
 641                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
 642                               MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
 643                               MLXSW_REG_PTYS_ETH_SPEED_SGMII))
 644                 return SUPPORTED_FIBRE;
 645
 646         if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
 647                               MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
 648                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
 649                               MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
 650                               MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
 651                 return SUPPORTED_Backplane;
 652         return 0;
 653 }
 654
 655 static u32 mlxsw_sx_from_ptys_supported_link(u32 ptys_eth_proto)
 656 {
 657         u32 modes = 0;
 658         int i;
 659
 660         for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
 661                 if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask)
 662                         modes |= mlxsw_sx_port_link_mode[i].supported;
 663         }
 664         return modes;
 665 }
 666
 667 static u32 mlxsw_sx_from_ptys_advert_link(u32 ptys_eth_proto)
 668 {
 669         u32 modes = 0;
 670         int i;
 671
 672         for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
 673                 if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask)
 674                         modes |= mlxsw_sx_port_link_mode[i].advertised;
 675         }
 676         return modes;
 677 }
 678
 679 static void mlxsw_sx_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
 680                                             struct ethtool_cmd *cmd)
 681 {
 682         u32 speed = SPEED_UNKNOWN;
 683         u8 duplex = DUPLEX_UNKNOWN;
 684         int i;
 685
 686         if (!carrier_ok)
 687                 goto out;
 688
 689         for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
 690                 if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask) {
 691                         speed = mlxsw_sx_port_link_mode[i].speed;
 692                         duplex = DUPLEX_FULL;
 693                         break;
 694                 }
 695         }
 696 out:
 697         ethtool_cmd_speed_set(cmd, speed);
 698         cmd->duplex = duplex;
 699 }
 700
 701 static u8 mlxsw_sx_port_connector_port(u32 ptys_eth_proto)
 702 {
 703         if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
 704                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
 705                               MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
 706                               MLXSW_REG_PTYS_ETH_SPEED_SGMII))
 707                 return PORT_FIBRE;
 708
 709         if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
 710                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
 711                               MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
 712                 return PORT_DA;
 713
 714         if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
 715                               MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
 716                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
 717                               MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
 718                 return PORT_NONE;
 719
 720         return PORT_OTHER;
 721 }
 722
 723 static int mlxsw_sx_port_get_settings(struct net_device *dev,
 724                                       struct ethtool_cmd *cmd)
 725 {
 726         struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
 727         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 728         char ptys_pl[MLXSW_REG_PTYS_LEN];
 729         u32 eth_proto_cap;
 730         u32 eth_proto_admin;
 731         u32 eth_proto_oper;
 732         int err;
 733
 734         mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sx_port->local_port, 0);
 735         err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
 736         if (err) {
 737                 netdev_err(dev, "Failed to get proto");
 738                 return err;
 739         }
 740         mlxsw_reg_ptys_unpack(ptys_pl, &eth_proto_cap,
 741                               &eth_proto_admin, &eth_proto_oper);
 742
 743         cmd->supported = mlxsw_sx_from_ptys_supported_port(eth_proto_cap) |
 744                          mlxsw_sx_from_ptys_supported_link(eth_proto_cap) |
 745                          SUPPORTED_Pause | SUPPORTED_Asym_Pause;
 746         cmd->advertising = mlxsw_sx_from_ptys_advert_link(eth_proto_admin);
 747         mlxsw_sx_from_ptys_speed_duplex(netif_carrier_ok(dev),
 748                                         eth_proto_oper, cmd);
 749
 750         eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
 751         cmd->port = mlxsw_sx_port_connector_port(eth_proto_oper);
 752         cmd->lp_advertising = mlxsw_sx_from_ptys_advert_link(eth_proto_oper);
 753
 754         cmd->transceiver = XCVR_INTERNAL;
 755         return 0;
 756 }
 757
 758 static u32 mlxsw_sx_to_ptys_advert_link(u32 advertising)
 759 {
 760         u32 ptys_proto = 0;
 761         int i;
 762
 763         for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
 764                 if (advertising & mlxsw_sx_port_link_mode[i].advertised)
 765                         ptys_proto |= mlxsw_sx_port_link_mode[i].mask;
 766         }
 767         return ptys_proto;
 768 }
 769
 770 static u32 mlxsw_sx_to_ptys_speed(u32 speed)
 771 {
 772         u32 ptys_proto = 0;
 773         int i;
 774
 775         for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
 776                 if (speed == mlxsw_sx_port_link_mode[i].speed)
 777                         ptys_proto |= mlxsw_sx_port_link_mode[i].mask;
 778         }
 779         return ptys_proto;
 780 }
 781
 782 static int mlxsw_sx_port_set_settings(struct net_device *dev,
 783                                       struct ethtool_cmd *cmd)
 784 {
 785         struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
 786         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 787         char ptys_pl[MLXSW_REG_PTYS_LEN];
 788         u32 speed;
 789         u32 eth_proto_new;
 790         u32 eth_proto_cap;
 791         u32 eth_proto_admin;
 792         bool is_up;
 793         int err;
 794
 795         speed = ethtool_cmd_speed(cmd);
 796
 797         eth_proto_new = cmd->autoneg == AUTONEG_ENABLE ?
 798                 mlxsw_sx_to_ptys_advert_link(cmd->advertising) :
 799                 mlxsw_sx_to_ptys_speed(speed);
 800
 801         mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sx_port->local_port, 0);
 802         err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
 803         if (err) {
 804                 netdev_err(dev, "Failed to get proto");
 805                 return err;
 806         }
 807         mlxsw_reg_ptys_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin, NULL);
 808
 809         eth_proto_new = eth_proto_new & eth_proto_cap;
 810         if (!eth_proto_new) {
 811                 netdev_err(dev, "Not supported proto admin requested");
 812                 return -EINVAL;
 813         }
 814         if (eth_proto_new == eth_proto_admin)
 815                 return 0;
 816
 817         mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sx_port->local_port, eth_proto_new);
 818         err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
 819         if (err) {
 820                 netdev_err(dev, "Failed to set proto admin");
 821                 return err;
 822         }
 823
 824         err = mlxsw_sx_port_oper_status_get(mlxsw_sx_port, &is_up);
 825         if (err) {
 826                 netdev_err(dev, "Failed to get oper status");
 827                 return err;
 828         }
 829         if (!is_up)
 830                 return 0;
 831
 832         err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
 833         if (err) {
 834                 netdev_err(dev, "Failed to set admin status");
 835                 return err;
 836         }
 837
 838         err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, true);
 839         if (err) {
 840                 netdev_err(dev, "Failed to set admin status");
 841                 return err;
 842         }
 843
 844         return 0;
 845 }
 846
 847 static const struct ethtool_ops mlxsw_sx_port_ethtool_ops = {
 848         .get_drvinfo            = mlxsw_sx_port_get_drvinfo,
 849         .get_link               = ethtool_op_get_link,
 850         .get_strings            = mlxsw_sx_port_get_strings,
 851         .get_ethtool_stats      = mlxsw_sx_port_get_stats,
 852         .get_sset_count         = mlxsw_sx_port_get_sset_count,
 853         .get_settings           = mlxsw_sx_port_get_settings,
 854         .set_settings           = mlxsw_sx_port_set_settings,
 855 };
 856
 857 static int mlxsw_sx_port_attr_get(struct net_device *dev,
 858                                   struct switchdev_attr *attr)
 859 {
 860         struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
 861         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 862
 863         switch (attr->id) {
 864         case SWITCHDEV_ATTR_PORT_PARENT_ID:
 865                 attr->u.ppid.id_len = sizeof(mlxsw_sx->hw_id);
 866                 memcpy(&attr->u.ppid.id, &mlxsw_sx->hw_id, attr->u.ppid.id_len);
 867                 break;
 868         default:
 869                 return -EOPNOTSUPP;
 870         }
 871
 872         return 0;
 873 }
 874
 875 static const struct switchdev_ops mlxsw_sx_port_switchdev_ops = {
 876         .switchdev_port_attr_get        = mlxsw_sx_port_attr_get,
 877 };
 878
 879 static int mlxsw_sx_hw_id_get(struct mlxsw_sx *mlxsw_sx)
 880 {
 881         char spad_pl[MLXSW_REG_SPAD_LEN];
 882         int err;
 883
 884         err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(spad), spad_pl);
 885         if (err)
 886                 return err;
 887         mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sx->hw_id);
 888         return 0;
 889 }
 890
 891 static int mlxsw_sx_port_dev_addr_get(struct mlxsw_sx_port *mlxsw_sx_port)
 892 {
 893         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 894         struct net_device *dev = mlxsw_sx_port->dev;
 895         char ppad_pl[MLXSW_REG_PPAD_LEN];
 896         int err;
 897
 898         mlxsw_reg_ppad_pack(ppad_pl, false, 0);
 899         err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ppad), ppad_pl);
 900         if (err)
 901                 return err;
 902         mlxsw_reg_ppad_mac_memcpy_from(ppad_pl, dev->dev_addr);
 903         /* The last byte value in base mac address is guaranteed
 904          * to be such it does not overflow when adding local_port
 905          * value.
 906          */
 907         dev->dev_addr[ETH_ALEN - 1] += mlxsw_sx_port->local_port;
 908         return 0;
 909 }
 910
 911 static int mlxsw_sx_port_stp_state_set(struct mlxsw_sx_port *mlxsw_sx_port,
 912                                        u16 vid, enum mlxsw_reg_spms_state state)
 913 {
 914         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 915         char *spms_pl;
 916         int err;
 917
 918         spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
 919         if (!spms_pl)
 920                 return -ENOMEM;
 921         mlxsw_reg_spms_pack(spms_pl, mlxsw_sx_port->local_port, vid, state);
 922         err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(spms), spms_pl);
 923         kfree(spms_pl);
 924         return err;
 925 }
 926
 927 static int mlxsw_sx_port_speed_set(struct mlxsw_sx_port *mlxsw_sx_port,
 928                                    u32 speed)
 929 {
 930         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 931         char ptys_pl[MLXSW_REG_PTYS_LEN];
 932
 933         mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sx_port->local_port, speed);
 934         return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
 935 }
 936
 937 static int
 938 mlxsw_sx_port_mac_learning_mode_set(struct mlxsw_sx_port *mlxsw_sx_port,
 939                                     enum mlxsw_reg_spmlr_learn_mode mode)
 940 {
 941         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 942         char spmlr_pl[MLXSW_REG_SPMLR_LEN];
 943
 944         mlxsw_reg_spmlr_pack(spmlr_pl, mlxsw_sx_port->local_port, mode);
 945         return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(spmlr), spmlr_pl);
 946 }
 947
 948 static int mlxsw_sx_port_create(struct mlxsw_sx *mlxsw_sx, u8 local_port)
 949 {
 950         struct mlxsw_sx_port *mlxsw_sx_port;
 951         struct net_device *dev;
 952         bool usable;
 953         int err;
 954
 955         dev = alloc_etherdev(sizeof(struct mlxsw_sx_port));
 956         if (!dev)
 957                 return -ENOMEM;
 958         mlxsw_sx_port = netdev_priv(dev);
 959         mlxsw_sx_port->dev = dev;
 960         mlxsw_sx_port->mlxsw_sx = mlxsw_sx;
 961         mlxsw_sx_port->local_port = local_port;
 962
 963         mlxsw_sx_port->pcpu_stats =
 964                 netdev_alloc_pcpu_stats(struct mlxsw_sx_port_pcpu_stats);
 965         if (!mlxsw_sx_port->pcpu_stats) {
 966                 err = -ENOMEM;
 967                 goto err_alloc_stats;
 968         }
 969
 970         dev->netdev_ops = &mlxsw_sx_port_netdev_ops;
 971         dev->ethtool_ops = &mlxsw_sx_port_ethtool_ops;
 972         dev->switchdev_ops = &mlxsw_sx_port_switchdev_ops;
 973
 974         err = mlxsw_sx_port_dev_addr_get(mlxsw_sx_port);
 975         if (err) {
 976                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Unable to get port mac address\n",
 977                         mlxsw_sx_port->local_port);
 978                 goto err_dev_addr_get;
 979         }
 980
 981         netif_carrier_off(dev);
 982
 983         dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
 984                          NETIF_F_VLAN_CHALLENGED;
 985
 986         /* Each packet needs to have a Tx header (metadata) on top all other
 987          * headers.
 988          */
 989         dev->hard_header_len += MLXSW_TXHDR_LEN;
 990
 991         err = mlxsw_sx_port_module_check(mlxsw_sx_port, &usable);
 992         if (err) {
 993                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to check module\n",
 994                         mlxsw_sx_port->local_port);
 995                 goto err_port_module_check;
 996         }
 997
 998         if (!usable) {
 999                 dev_dbg(mlxsw_sx->bus_info->dev, "Port %d: Not usable, skipping initialization\n",
1000                         mlxsw_sx_port->local_port);
1001                 goto port_not_usable;
1002         }
1003
1004         err = mlxsw_sx_port_swid_set(mlxsw_sx_port, 0);
1005         if (err) {
1006                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set SWID\n",
1007                         mlxsw_sx_port->local_port);
1008                 goto err_port_swid_set;
1009         }
1010
1011         err = mlxsw_sx_port_speed_set(mlxsw_sx_port,
1012                                       MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4);
1013         if (err) {
1014                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set speed\n",
1015                         mlxsw_sx_port->local_port);
1016                 goto err_port_speed_set;
1017         }
1018
1019         err = mlxsw_sx_port_mtu_set(mlxsw_sx_port, ETH_DATA_LEN);
1020         if (err) {
1021                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set MTU\n",
1022                         mlxsw_sx_port->local_port);
1023                 goto err_port_mtu_set;
1024         }
1025
1026         err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
1027         if (err)
1028                 goto err_port_admin_status_set;
1029
1030         err = mlxsw_sx_port_stp_state_set(mlxsw_sx_port,
1031                                           MLXSW_PORT_DEFAULT_VID,
1032                                           MLXSW_REG_SPMS_STATE_FORWARDING);
1033         if (err) {
1034                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set STP state\n",
1035                         mlxsw_sx_port->local_port);
1036                 goto err_port_stp_state_set;
1037         }
1038
1039         err = mlxsw_sx_port_mac_learning_mode_set(mlxsw_sx_port,
1040                                                   MLXSW_REG_SPMLR_LEARN_MODE_DISABLE);
1041         if (err) {
1042                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set MAC learning mode\n",
1043                         mlxsw_sx_port->local_port);
1044                 goto err_port_mac_learning_mode_set;
1045         }
1046
1047         err = register_netdev(dev);
1048         if (err) {
1049                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to register netdev\n",
1050                         mlxsw_sx_port->local_port);
1051                 goto err_register_netdev;
1052         }
1053
1054         mlxsw_sx->ports[local_port] = mlxsw_sx_port;
1055         return 0;
1056
1057 err_register_netdev:
1058 err_port_admin_status_set:
1059 err_port_mac_learning_mode_set:
1060 err_port_stp_state_set:
1061 err_port_mtu_set:
1062 err_port_speed_set:
1063 err_port_swid_set:
1064 port_not_usable:
1065 err_port_module_check:
1066 err_dev_addr_get:
1067         free_percpu(mlxsw_sx_port->pcpu_stats);
1068 err_alloc_stats:
1069         free_netdev(dev);
1070         return err;
1071 }
1072
1073 static void mlxsw_sx_port_remove(struct mlxsw_sx *mlxsw_sx, u8 local_port)
1074 {
1075         struct mlxsw_sx_port *mlxsw_sx_port = mlxsw_sx->ports[local_port];
1076
1077         if (!mlxsw_sx_port)
1078                 return;
1079         unregister_netdev(mlxsw_sx_port->dev); /* This calls ndo_stop */
1080         mlxsw_sx_port_swid_set(mlxsw_sx_port, MLXSW_PORT_SWID_DISABLED_PORT);
1081         free_percpu(mlxsw_sx_port->pcpu_stats);
1082 }
1083
1084 static void mlxsw_sx_ports_remove(struct mlxsw_sx *mlxsw_sx)
1085 {
1086         int i;
1087
1088         for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++)
1089                 mlxsw_sx_port_remove(mlxsw_sx, i);
1090         kfree(mlxsw_sx->ports);
1091 }
1092
1093 static int mlxsw_sx_ports_create(struct mlxsw_sx *mlxsw_sx)
1094 {
1095         size_t alloc_size;
1096         int i;
1097         int err;
1098
1099         alloc_size = sizeof(struct mlxsw_sx_port *) * MLXSW_PORT_MAX_PORTS;
1100         mlxsw_sx->ports = kzalloc(alloc_size, GFP_KERNEL);
1101         if (!mlxsw_sx->ports)
1102                 return -ENOMEM;
1103
1104         for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++) {
1105                 err = mlxsw_sx_port_create(mlxsw_sx, i);
1106                 if (err)
1107                         goto err_port_create;
1108         }
1109         return 0;
1110
1111 err_port_create:
1112         for (i--; i >= 1; i--)
1113                 mlxsw_sx_port_remove(mlxsw_sx, i);
1114         kfree(mlxsw_sx->ports);
1115         return err;
1116 }
1117
1118 static void mlxsw_sx_pude_event_func(const struct mlxsw_reg_info *reg,
1119                                      char *pude_pl, void *priv)
1120 {
1121         struct mlxsw_sx *mlxsw_sx = priv;
1122         struct mlxsw_sx_port *mlxsw_sx_port;
1123         enum mlxsw_reg_pude_oper_status status;
1124         u8 local_port;
1125
1126         local_port = mlxsw_reg_pude_local_port_get(pude_pl);
1127         mlxsw_sx_port = mlxsw_sx->ports[local_port];
1128         if (!mlxsw_sx_port) {
1129                 dev_warn(mlxsw_sx->bus_info->dev, "Port %d: Link event received for non-existent port\n",
1130                          local_port);
1131                 return;
1132         }
1133
1134         status = mlxsw_reg_pude_oper_status_get(pude_pl);
1135         if (MLXSW_PORT_OPER_STATUS_UP == status) {
1136                 netdev_info(mlxsw_sx_port->dev, "link up\n");
1137                 netif_carrier_on(mlxsw_sx_port->dev);
1138         } else {
1139                 netdev_info(mlxsw_sx_port->dev, "link down\n");
1140                 netif_carrier_off(mlxsw_sx_port->dev);
1141         }
1142 }
1143
1144 static struct mlxsw_event_listener mlxsw_sx_pude_event = {
1145         .func = mlxsw_sx_pude_event_func,
1146         .trap_id = MLXSW_TRAP_ID_PUDE,
1147 };
1148
1149 static int mlxsw_sx_event_register(struct mlxsw_sx *mlxsw_sx,
1150                                    enum mlxsw_event_trap_id trap_id)
1151 {
1152         struct mlxsw_event_listener *el;
1153         char hpkt_pl[MLXSW_REG_HPKT_LEN];
1154         int err;
1155
1156         switch (trap_id) {
1157         case MLXSW_TRAP_ID_PUDE:
1158                 el = &mlxsw_sx_pude_event;
1159                 break;
1160         }
1161         err = mlxsw_core_event_listener_register(mlxsw_sx->core, el, mlxsw_sx);
1162         if (err)
1163                 return err;
1164
1165         mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD,
1166                             MLXSW_REG_HTGT_TRAP_GROUP_EMAD, trap_id);
1167         err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(hpkt), hpkt_pl);
1168         if (err)
1169                 goto err_event_trap_set;
1170
1171         return 0;
1172
1173 err_event_trap_set:
1174         mlxsw_core_event_listener_unregister(mlxsw_sx->core, el, mlxsw_sx);
1175         return err;
1176 }
1177
1178 static void mlxsw_sx_event_unregister(struct mlxsw_sx *mlxsw_sx,
1179                                       enum mlxsw_event_trap_id trap_id)
1180 {
1181         struct mlxsw_event_listener *el;
1182
1183         switch (trap_id) {
1184         case MLXSW_TRAP_ID_PUDE:
1185                 el = &mlxsw_sx_pude_event;
1186                 break;
1187         }
1188         mlxsw_core_event_listener_unregister(mlxsw_sx->core, el, mlxsw_sx);
1189 }
1190
1191 static void mlxsw_sx_rx_listener_func(struct sk_buff *skb, u8 local_port,
1192                                       void *priv)
1193 {
1194         struct mlxsw_sx *mlxsw_sx = priv;
1195         struct mlxsw_sx_port *mlxsw_sx_port = mlxsw_sx->ports[local_port];
1196         struct mlxsw_sx_port_pcpu_stats *pcpu_stats;
1197
1198         if (unlikely(!mlxsw_sx_port)) {
1199                 if (net_ratelimit())
1200                         dev_warn(mlxsw_sx->bus_info->dev, "Port %d: skb received for non-existent port\n",
1201                                  local_port);
1202                 return;
1203         }
1204
1205         skb->dev = mlxsw_sx_port->dev;
1206
1207         pcpu_stats = this_cpu_ptr(mlxsw_sx_port->pcpu_stats);
1208         u64_stats_update_begin(&pcpu_stats->syncp);
1209         pcpu_stats->rx_packets++;
1210         pcpu_stats->rx_bytes += skb->len;
1211         u64_stats_update_end(&pcpu_stats->syncp);
1212
1213         skb->protocol = eth_type_trans(skb, skb->dev);
1214         netif_receive_skb(skb);
1215 }
1216
1217 static const struct mlxsw_rx_listener mlxsw_sx_rx_listener[] = {
1218         {
1219                 .func = mlxsw_sx_rx_listener_func,
1220                 .local_port = MLXSW_PORT_DONT_CARE,
1221                 .trap_id = MLXSW_TRAP_ID_FDB_MC,
1222         },
1223         /* Traps for specific L2 packet types, not trapped as FDB MC */
1224         {
1225                 .func = mlxsw_sx_rx_listener_func,
1226                 .local_port = MLXSW_PORT_DONT_CARE,
1227                 .trap_id = MLXSW_TRAP_ID_STP,
1228         },
1229         {
1230                 .func = mlxsw_sx_rx_listener_func,
1231                 .local_port = MLXSW_PORT_DONT_CARE,
1232                 .trap_id = MLXSW_TRAP_ID_LACP,
1233         },
1234         {
1235                 .func = mlxsw_sx_rx_listener_func,
1236                 .local_port = MLXSW_PORT_DONT_CARE,
1237                 .trap_id = MLXSW_TRAP_ID_EAPOL,
1238         },
1239         {
1240                 .func = mlxsw_sx_rx_listener_func,
1241                 .local_port = MLXSW_PORT_DONT_CARE,
1242                 .trap_id = MLXSW_TRAP_ID_LLDP,
1243         },
1244         {
1245                 .func = mlxsw_sx_rx_listener_func,
1246                 .local_port = MLXSW_PORT_DONT_CARE,
1247                 .trap_id = MLXSW_TRAP_ID_MMRP,
1248         },
1249         {
1250                 .func = mlxsw_sx_rx_listener_func,
1251                 .local_port = MLXSW_PORT_DONT_CARE,
1252                 .trap_id = MLXSW_TRAP_ID_MVRP,
1253         },
1254         {
1255                 .func = mlxsw_sx_rx_listener_func,
1256                 .local_port = MLXSW_PORT_DONT_CARE,
1257                 .trap_id = MLXSW_TRAP_ID_RPVST,
1258         },
1259         {
1260                 .func = mlxsw_sx_rx_listener_func,
1261                 .local_port = MLXSW_PORT_DONT_CARE,
1262                 .trap_id = MLXSW_TRAP_ID_DHCP,
1263         },
1264         {
1265                 .func = mlxsw_sx_rx_listener_func,
1266                 .local_port = MLXSW_PORT_DONT_CARE,
1267                 .trap_id = MLXSW_TRAP_ID_IGMP_QUERY,
1268         },
1269         {
1270                 .func = mlxsw_sx_rx_listener_func,
1271                 .local_port = MLXSW_PORT_DONT_CARE,
1272                 .trap_id = MLXSW_TRAP_ID_IGMP_V1_REPORT,
1273         },
1274         {
1275                 .func = mlxsw_sx_rx_listener_func,
1276                 .local_port = MLXSW_PORT_DONT_CARE,
1277                 .trap_id = MLXSW_TRAP_ID_IGMP_V2_REPORT,
1278         },
1279         {
1280                 .func = mlxsw_sx_rx_listener_func,
1281                 .local_port = MLXSW_PORT_DONT_CARE,
1282                 .trap_id = MLXSW_TRAP_ID_IGMP_V2_LEAVE,
1283         },
1284         {
1285                 .func = mlxsw_sx_rx_listener_func,
1286                 .local_port = MLXSW_PORT_DONT_CARE,
1287                 .trap_id = MLXSW_TRAP_ID_IGMP_V3_REPORT,
1288         },
1289 };
1290
1291 static int mlxsw_sx_traps_init(struct mlxsw_sx *mlxsw_sx)
1292 {
1293         char htgt_pl[MLXSW_REG_HTGT_LEN];
1294         char hpkt_pl[MLXSW_REG_HPKT_LEN];
1295         int i;
1296         int err;
1297
1298         mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_RX);
1299         err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(htgt), htgt_pl);
1300         if (err)
1301                 return err;
1302
1303         for (i = 0; i < ARRAY_SIZE(mlxsw_sx_rx_listener); i++) {
1304                 err = mlxsw_core_rx_listener_register(mlxsw_sx->core,
1305                                                       &mlxsw_sx_rx_listener[i],
1306                                                       mlxsw_sx);
1307                 if (err)
1308                         goto err_rx_listener_register;
1309
1310                 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
1311                                     MLXSW_REG_HTGT_TRAP_GROUP_RX,
1312                                     mlxsw_sx_rx_listener[i].trap_id);
1313                 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(hpkt), hpkt_pl);
1314                 if (err)
1315                         goto err_rx_trap_set;
1316         }
1317         return 0;
1318
1319 err_rx_trap_set:
1320         mlxsw_core_rx_listener_unregister(mlxsw_sx->core,
1321                                           &mlxsw_sx_rx_listener[i],
1322                                           mlxsw_sx);
1323 err_rx_listener_register:
1324         for (i--; i >= 0; i--) {
1325                 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD,
1326                                     MLXSW_REG_HTGT_TRAP_GROUP_RX,
1327                                     mlxsw_sx_rx_listener[i].trap_id);
1328                 mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(hpkt), hpkt_pl);
1329
1330                 mlxsw_core_rx_listener_unregister(mlxsw_sx->core,
1331                                                   &mlxsw_sx_rx_listener[i],
1332                                                   mlxsw_sx);
1333         }
1334         return err;
1335 }
1336
1337 static void mlxsw_sx_traps_fini(struct mlxsw_sx *mlxsw_sx)
1338 {
1339         char hpkt_pl[MLXSW_REG_HPKT_LEN];
1340         int i;
1341
1342         for (i = 0; i < ARRAY_SIZE(mlxsw_sx_rx_listener); i++) {
1343                 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD,
1344                                     MLXSW_REG_HTGT_TRAP_GROUP_RX,
1345                                     mlxsw_sx_rx_listener[i].trap_id);
1346                 mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(hpkt), hpkt_pl);
1347
1348                 mlxsw_core_rx_listener_unregister(mlxsw_sx->core,
1349                                                   &mlxsw_sx_rx_listener[i],
1350                                                   mlxsw_sx);
1351         }
1352 }
1353
1354 static int mlxsw_sx_flood_init(struct mlxsw_sx *mlxsw_sx)
1355 {
1356         char sfgc_pl[MLXSW_REG_SFGC_LEN];
1357         char sgcr_pl[MLXSW_REG_SGCR_LEN];
1358         char *smid_pl;
1359         char *sftr_pl;
1360         int err;
1361
1362         /* Due to FW bug, we must configure SMID. */
1363         smid_pl = kmalloc(MLXSW_REG_SMID_LEN, GFP_KERNEL);
1364         if (!smid_pl)
1365                 return -ENOMEM;
1366         mlxsw_reg_smid_pack(smid_pl, MLXSW_PORT_MID);
1367         err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(smid), smid_pl);
1368         kfree(smid_pl);
1369         if (err)
1370                 return err;
1371
1372         /* Configure a flooding table, which includes only CPU port. */
1373         sftr_pl = kmalloc(MLXSW_REG_SFTR_LEN, GFP_KERNEL);
1374         if (!sftr_pl)
1375                 return -ENOMEM;
1376         mlxsw_reg_sftr_pack(sftr_pl, 0, 0, MLXSW_REG_SFGC_TABLE_TYPE_SINGLE, 0);
1377         err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sftr), sftr_pl);
1378         kfree(sftr_pl);
1379         if (err)
1380                 return err;
1381
1382         /* Flood different packet types using the flooding table. */
1383         mlxsw_reg_sfgc_pack(sfgc_pl,
1384                             MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,
1385                             MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1386                             MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1387                             0);
1388         err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1389         if (err)
1390                 return err;
1391
1392         mlxsw_reg_sfgc_pack(sfgc_pl,
1393                             MLXSW_REG_SFGC_TYPE_BROADCAST,
1394                             MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1395                             MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1396                             0);
1397         err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1398         if (err)
1399                 return err;
1400
1401         mlxsw_reg_sfgc_pack(sfgc_pl,
1402                             MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,
1403                             MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1404                             MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1405                             0);
1406         err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1407         if (err)
1408                 return err;
1409
1410         mlxsw_reg_sfgc_pack(sfgc_pl,
1411                             MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,
1412                             MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1413                             MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1414                             0);
1415         err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1416         if (err)
1417                 return err;
1418
1419         mlxsw_reg_sfgc_pack(sfgc_pl,
1420                             MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,
1421                             MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1422                             MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1423                             0);
1424         err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1425         if (err)
1426                 return err;
1427
1428         mlxsw_reg_sgcr_pack(sgcr_pl, true);
1429         return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sgcr), sgcr_pl);
1430 }
1431
1432 static int mlxsw_sx_init(void *priv, struct mlxsw_core *mlxsw_core,
1433                          const struct mlxsw_bus_info *mlxsw_bus_info)
1434 {
1435         struct mlxsw_sx *mlxsw_sx = priv;
1436         int err;
1437
1438         mlxsw_sx->core = mlxsw_core;
1439         mlxsw_sx->bus_info = mlxsw_bus_info;
1440
1441         err = mlxsw_sx_hw_id_get(mlxsw_sx);
1442         if (err) {
1443                 dev_err(mlxsw_sx->bus_info->dev, "Failed to get switch HW ID\n");
1444                 return err;
1445         }
1446
1447         err = mlxsw_sx_ports_create(mlxsw_sx);
1448         if (err) {
1449                 dev_err(mlxsw_sx->bus_info->dev, "Failed to create ports\n");
1450                 return err;
1451         }
1452
1453         err = mlxsw_sx_event_register(mlxsw_sx, MLXSW_TRAP_ID_PUDE);
1454         if (err) {
1455                 dev_err(mlxsw_sx->bus_info->dev, "Failed to register for PUDE events\n");
1456                 goto err_event_register;
1457         }
1458
1459         err = mlxsw_sx_traps_init(mlxsw_sx);
1460         if (err) {
1461                 dev_err(mlxsw_sx->bus_info->dev, "Failed to set traps for RX\n");
1462                 goto err_rx_listener_register;
1463         }
1464
1465         err = mlxsw_sx_flood_init(mlxsw_sx);
1466         if (err) {
1467                 dev_err(mlxsw_sx->bus_info->dev, "Failed to initialize flood tables\n");
1468                 goto err_flood_init;
1469         }
1470
1471         return 0;
1472
1473 err_flood_init:
1474         mlxsw_sx_traps_fini(mlxsw_sx);
1475 err_rx_listener_register:
1476         mlxsw_sx_event_unregister(mlxsw_sx, MLXSW_TRAP_ID_PUDE);
1477 err_event_register:
1478         mlxsw_sx_ports_remove(mlxsw_sx);
1479         return err;
1480 }
1481
1482 static void mlxsw_sx_fini(void *priv)
1483 {
1484         struct mlxsw_sx *mlxsw_sx = priv;
1485
1486         mlxsw_sx_traps_fini(mlxsw_sx);
1487         mlxsw_sx_event_unregister(mlxsw_sx, MLXSW_TRAP_ID_PUDE);
1488         mlxsw_sx_ports_remove(mlxsw_sx);
1489 }
1490
1491 static struct mlxsw_config_profile mlxsw_sx_config_profile = {
1492         .used_max_vepa_channels         = 1,
1493         .max_vepa_channels              = 0,
1494         .used_max_lag                   = 1,
1495         .max_lag                        = 64,
1496         .used_max_port_per_lag          = 1,
1497         .max_port_per_lag               = 16,
1498         .used_max_mid                   = 1,
1499         .max_mid                        = 7000,
1500         .used_max_pgt                   = 1,
1501         .max_pgt                        = 0,
1502         .used_max_system_port           = 1,
1503         .max_system_port                = 48000,
1504         .used_max_vlan_groups           = 1,
1505         .max_vlan_groups                = 127,
1506         .used_max_regions               = 1,
1507         .max_regions                    = 400,
1508         .used_flood_tables              = 1,
1509         .max_flood_tables               = 2,
1510         .max_vid_flood_tables           = 1,
1511         .used_flood_mode                = 1,
1512         .flood_mode                     = 3,
1513         .used_max_ib_mc                 = 1,
1514         .max_ib_mc                      = 0,
1515         .used_max_pkey                  = 1,
1516         .max_pkey                       = 0,
1517         .swid_config                    = {
1518                 {
1519                         .used_type      = 1,
1520                         .type           = MLXSW_PORT_SWID_TYPE_ETH,
1521                 }
1522         },
1523 };
1524
1525 static struct mlxsw_driver mlxsw_sx_driver = {
1526         .kind                   = MLXSW_DEVICE_KIND_SWITCHX2,
1527         .owner                  = THIS_MODULE,
1528         .priv_size              = sizeof(struct mlxsw_sx),
1529         .init                   = mlxsw_sx_init,
1530         .fini                   = mlxsw_sx_fini,
1531         .txhdr_construct        = mlxsw_sx_txhdr_construct,
1532         .txhdr_len              = MLXSW_TXHDR_LEN,
1533         .profile                = &mlxsw_sx_config_profile,
1534 };
1535
1536 static int __init mlxsw_sx_module_init(void)
1537 {
1538         return mlxsw_core_driver_register(&mlxsw_sx_driver);
1539 }
1540
1541 static void __exit mlxsw_sx_module_exit(void)
1542 {
1543         mlxsw_core_driver_unregister(&mlxsw_sx_driver);
1544 }
1545
1546 module_init(mlxsw_sx_module_init);
1547 module_exit(mlxsw_sx_module_exit);
1548
1549 MODULE_LICENSE("Dual BSD/GPL");
1550 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
1551 MODULE_DESCRIPTION("Mellanox SwitchX-2 driver");
1552 MODULE_MLXSW_DRIVER_ALIAS(MLXSW_DEVICE_KIND_SWITCHX2);