drivers/net/ethernet/qlogic/qed/qed.h

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015 QLogic Corporation
   3  *
   4  * This software is available under the terms of the GNU General Public License
   5  * (GPL) Version 2, available from the file COPYING in the main directory of
   6  * this source tree.
   7  */
   8
   9 #ifndef _QED_H
  10 #define _QED_H
  11
  12 #include <linux/types.h>
  13 #include <linux/io.h>
  14 #include <linux/delay.h>
  15 #include <linux/firmware.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/list.h>
  18 #include <linux/mutex.h>
  19 #include <linux/pci.h>
  20 #include <linux/slab.h>
  21 #include <linux/string.h>
  22 #include <linux/workqueue.h>
  23 #include <linux/zlib.h>
  24 #include <linux/hashtable.h>
  25 #include <linux/qed/qed_if.h>
  26 #include "qed_debug.h"
  27 #include "qed_hsi.h"
  28
  29 extern const struct qed_common_ops qed_common_ops_pass;
  30 #define DRV_MODULE_VERSION "8.10.9.20"
  31
  32 #define MAX_HWFNS_PER_DEVICE    (4)
  33 #define NAME_SIZE 16
  34 #define VER_SIZE 16
  35
  36 #define QED_WFQ_UNIT    100
  37
  38 /* cau states */
  39 enum qed_coalescing_mode {
  40         QED_COAL_MODE_DISABLE,
  41         QED_COAL_MODE_ENABLE
  42 };
  43
  44 struct qed_eth_cb_ops;
  45 struct qed_dev_info;
  46 union qed_mcp_protocol_stats;
  47 enum qed_mcp_protocol_type;
  48
  49 /* helpers */
  50 static inline u32 qed_db_addr(u32 cid, u32 DEMS)
  51 {
  52         u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
  53                       FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
  54
  55         return db_addr;
  56 }
  57
  58 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn)                                 \
  59         ((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \
  60          ~((1 << (p_hwfn->cdev->cache_shift)) - 1))
  61
  62 #define for_each_hwfn(cdev, i)  for (i = 0; i < cdev->num_hwfns; i++)
  63
  64 #define D_TRINE(val, cond1, cond2, true1, true2, def) \
  65         (val == (cond1) ? true1 :                     \
  66          (val == (cond2) ? true2 : def))
  67
  68 /* forward */
  69 struct qed_ptt_pool;
  70 struct qed_spq;
  71 struct qed_sb_info;
  72 struct qed_sb_attn_info;
  73 struct qed_cxt_mngr;
  74 struct qed_sb_sp_info;
  75 struct qed_ll2_info;
  76 struct qed_mcp_info;
  77
  78 struct qed_rt_data {
  79         u32     *init_val;
  80         bool    *b_valid;
  81 };
  82
  83 enum qed_tunn_mode {
  84         QED_MODE_L2GENEVE_TUNN,
  85         QED_MODE_IPGENEVE_TUNN,
  86         QED_MODE_L2GRE_TUNN,
  87         QED_MODE_IPGRE_TUNN,
  88         QED_MODE_VXLAN_TUNN,
  89 };
  90
  91 enum qed_tunn_clss {
  92         QED_TUNN_CLSS_MAC_VLAN,
  93         QED_TUNN_CLSS_MAC_VNI,
  94         QED_TUNN_CLSS_INNER_MAC_VLAN,
  95         QED_TUNN_CLSS_INNER_MAC_VNI,
  96         MAX_QED_TUNN_CLSS,
  97 };
  98
  99 struct qed_tunn_start_params {
 100         unsigned long   tunn_mode;
 101         u16             vxlan_udp_port;
 102         u16             geneve_udp_port;
 103         u8              update_vxlan_udp_port;
 104         u8              update_geneve_udp_port;
 105         u8              tunn_clss_vxlan;
 106         u8              tunn_clss_l2geneve;
 107         u8              tunn_clss_ipgeneve;
 108         u8              tunn_clss_l2gre;
 109         u8              tunn_clss_ipgre;
 110 };
 111
 112 struct qed_tunn_update_params {
 113         unsigned long   tunn_mode_update_mask;
 114         unsigned long   tunn_mode;
 115         u16             vxlan_udp_port;
 116         u16             geneve_udp_port;
 117         u8              update_rx_pf_clss;
 118         u8              update_tx_pf_clss;
 119         u8              update_vxlan_udp_port;
 120         u8              update_geneve_udp_port;
 121         u8              tunn_clss_vxlan;
 122         u8              tunn_clss_l2geneve;
 123         u8              tunn_clss_ipgeneve;
 124         u8              tunn_clss_l2gre;
 125         u8              tunn_clss_ipgre;
 126 };
 127
 128 /* The PCI personality is not quite synonymous to protocol ID:
 129  * 1. All personalities need CORE connections
 130  * 2. The Ethernet personality may support also the RoCE protocol
 131  */
 132 enum qed_pci_personality {
 133         QED_PCI_ETH,
 134         QED_PCI_ISCSI,
 135         QED_PCI_ETH_ROCE,
 136         QED_PCI_DEFAULT /* default in shmem */
 137 };
 138
 139 /* All VFs are symmetric, all counters are PF + all VFs */
 140 struct qed_qm_iids {
 141         u32 cids;
 142         u32 vf_cids;
 143         u32 tids;
 144 };
 145
 146 enum QED_RESOURCES {
 147         QED_SB,
 148         QED_L2_QUEUE,
 149         QED_VPORT,
 150         QED_RSS_ENG,
 151         QED_PQ,
 152         QED_RL,
 153         QED_MAC,
 154         QED_VLAN,
 155         QED_ILT,
 156         QED_LL2_QUEUE,
 157         QED_MAX_RESC,
 158 };
 159
 160 enum QED_FEATURE {
 161         QED_PF_L2_QUE,
 162         QED_VF,
 163         QED_MAX_FEATURES,
 164 };
 165
 166 enum QED_PORT_MODE {
 167         QED_PORT_MODE_DE_2X40G,
 168         QED_PORT_MODE_DE_2X50G,
 169         QED_PORT_MODE_DE_1X100G,
 170         QED_PORT_MODE_DE_4X10G_F,
 171         QED_PORT_MODE_DE_4X10G_E,
 172         QED_PORT_MODE_DE_4X20G,
 173         QED_PORT_MODE_DE_1X40G,
 174         QED_PORT_MODE_DE_2X25G,
 175         QED_PORT_MODE_DE_1X25G
 176 };
 177
 178 enum qed_dev_cap {
 179         QED_DEV_CAP_ETH,
 180         QED_DEV_CAP_ISCSI,
 181         QED_DEV_CAP_ROCE,
 182 };
 183
 184 struct qed_hw_info {
 185         /* PCI personality */
 186         enum qed_pci_personality        personality;
 187
 188         /* Resource Allocation scheme results */
 189         u32                             resc_start[QED_MAX_RESC];
 190         u32                             resc_num[QED_MAX_RESC];
 191         u32                             feat_num[QED_MAX_FEATURES];
 192
 193 #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
 194 #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
 195 #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
 196                                  RESC_NUM(_p_hwfn, resc))
 197 #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
 198
 199         u8                              num_tc;
 200         u8                              offload_tc;
 201         u8                              non_offload_tc;
 202
 203         u32                             concrete_fid;
 204         u16                             opaque_fid;
 205         u16                             ovlan;
 206         u32                             part_num[4];
 207
 208         unsigned char                   hw_mac_addr[ETH_ALEN];
 209
 210         struct qed_igu_info             *p_igu_info;
 211
 212         u32                             port_mode;
 213         u32                             hw_mode;
 214         unsigned long           device_capabilities;
 215 };
 216
 217 struct qed_hw_cid_data {
 218         u32     cid;
 219         bool    b_cid_allocated;
 220
 221         /* Additional identifiers */
 222         u16     opaque_fid;
 223         u8      vport_id;
 224 };
 225
 226 /* maximun size of read/write commands (HW limit) */
 227 #define DMAE_MAX_RW_SIZE        0x2000
 228
 229 struct qed_dmae_info {
 230         /* Mutex for synchronizing access to functions */
 231         struct mutex    mutex;
 232
 233         u8              channel;
 234
 235         dma_addr_t      completion_word_phys_addr;
 236
 237         /* The memory location where the DMAE writes the completion
 238          * value when an operation is finished on this context.
 239          */
 240         u32             *p_completion_word;
 241
 242         dma_addr_t      intermediate_buffer_phys_addr;
 243
 244         /* An intermediate buffer for DMAE operations that use virtual
 245          * addresses - data is DMA'd to/from this buffer and then
 246          * memcpy'd to/from the virtual address
 247          */
 248         u32             *p_intermediate_buffer;
 249
 250         dma_addr_t      dmae_cmd_phys_addr;
 251         struct dmae_cmd *p_dmae_cmd;
 252 };
 253
 254 struct qed_wfq_data {
 255         /* when feature is configured for at least 1 vport */
 256         u32     min_speed;
 257         bool    configured;
 258 };
 259
 260 struct qed_qm_info {
 261         struct init_qm_pq_params        *qm_pq_params;
 262         struct init_qm_vport_params     *qm_vport_params;
 263         struct init_qm_port_params      *qm_port_params;
 264         u16                             start_pq;
 265         u8                              start_vport;
 266         u8                              pure_lb_pq;
 267         u8                              offload_pq;
 268         u8                              pure_ack_pq;
 269         u8 ooo_pq;
 270         u8                              vf_queues_offset;
 271         u16                             num_pqs;
 272         u16                             num_vf_pqs;
 273         u8                              num_vports;
 274         u8                              max_phys_tcs_per_port;
 275         bool                            pf_rl_en;
 276         bool                            pf_wfq_en;
 277         bool                            vport_rl_en;
 278         bool                            vport_wfq_en;
 279         u8                              pf_wfq;
 280         u32                             pf_rl;
 281         struct qed_wfq_data             *wfq_data;
 282         u8 num_pf_rls;
 283 };
 284
 285 struct storm_stats {
 286         u32     address;
 287         u32     len;
 288 };
 289
 290 struct qed_storm_stats {
 291         struct storm_stats mstats;
 292         struct storm_stats pstats;
 293         struct storm_stats tstats;
 294         struct storm_stats ustats;
 295 };
 296
 297 struct qed_fw_data {
 298         struct fw_ver_info      *fw_ver_info;
 299         const u8                *modes_tree_buf;
 300         union init_op           *init_ops;
 301         const u32               *arr_data;
 302         u32                     init_ops_size;
 303 };
 304
 305 struct qed_simd_fp_handler {
 306         void    *token;
 307         void    (*func)(void *);
 308 };
 309
 310 struct qed_hwfn {
 311         struct qed_dev                  *cdev;
 312         u8                              my_id;          /* ID inside the PF */
 313 #define IS_LEAD_HWFN(edev)              (!((edev)->my_id))
 314         u8                              rel_pf_id;      /* Relative to engine*/
 315         u8                              abs_pf_id;
 316 #define QED_PATH_ID(_p_hwfn)            ((_p_hwfn)->abs_pf_id & 1)
 317         u8                              port_id;
 318         bool                            b_active;
 319
 320         u32                             dp_module;
 321         u8                              dp_level;
 322         char                            name[NAME_SIZE];
 323
 324         bool                            first_on_engine;
 325         bool                            hw_init_done;
 326
 327         u8                              num_funcs_on_engine;
 328         u8 enabled_func_idx;
 329
 330         /* BAR access */
 331         void __iomem                    *regview;
 332         void __iomem                    *doorbells;
 333         u64                             db_phys_addr;
 334         unsigned long                   db_size;
 335
 336         /* PTT pool */
 337         struct qed_ptt_pool             *p_ptt_pool;
 338
 339         /* HW info */
 340         struct qed_hw_info              hw_info;
 341
 342         /* rt_array (for init-tool) */
 343         struct qed_rt_data              rt_data;
 344
 345         /* SPQ */
 346         struct qed_spq                  *p_spq;
 347
 348         /* EQ */
 349         struct qed_eq                   *p_eq;
 350
 351         /* Consolidate Q*/
 352         struct qed_consq                *p_consq;
 353
 354         /* Slow-Path definitions */
 355         struct tasklet_struct           *sp_dpc;
 356         bool                            b_sp_dpc_enabled;
 357
 358         struct qed_ptt                  *p_main_ptt;
 359         struct qed_ptt                  *p_dpc_ptt;
 360
 361         struct qed_sb_sp_info           *p_sp_sb;
 362         struct qed_sb_attn_info         *p_sb_attn;
 363
 364         /* Protocol related */
 365         bool                            using_ll2;
 366         struct qed_ll2_info             *p_ll2_info;
 367         struct qed_pf_params            pf_params;
 368
 369         bool b_rdma_enabled_in_prs;
 370         u32 rdma_prs_search_reg;
 371
 372         /* Array of sb_info of all status blocks */
 373         struct qed_sb_info              *sbs_info[MAX_SB_PER_PF_MIMD];
 374         u16                             num_sbs;
 375
 376         struct qed_cxt_mngr             *p_cxt_mngr;
 377
 378         /* Flag indicating whether interrupts are enabled or not*/
 379         bool                            b_int_enabled;
 380         bool                            b_int_requested;
 381
 382         /* True if the driver requests for the link */
 383         bool                            b_drv_link_init;
 384
 385         struct qed_vf_iov               *vf_iov_info;
 386         struct qed_pf_iov               *pf_iov_info;
 387         struct qed_mcp_info             *mcp_info;
 388
 389         struct qed_dcbx_info            *p_dcbx_info;
 390
 391         struct qed_hw_cid_data          *p_tx_cids;
 392         struct qed_hw_cid_data          *p_rx_cids;
 393
 394         struct qed_dmae_info            dmae_info;
 395
 396         /* QM init */
 397         struct qed_qm_info              qm_info;
 398         struct qed_storm_stats          storm_stats;
 399
 400         /* Buffer for unzipping firmware data */
 401         void                            *unzip_buf;
 402
 403         struct dbg_tools_data           dbg_info;
 404
 405         struct qed_simd_fp_handler      simd_proto_handler[64];
 406
 407 #ifdef CONFIG_QED_SRIOV
 408         struct workqueue_struct *iov_wq;
 409         struct delayed_work iov_task;
 410         unsigned long iov_task_flags;
 411 #endif
 412
 413         struct z_stream_s               *stream;
 414 };
 415
 416 struct pci_params {
 417         int             pm_cap;
 418
 419         unsigned long   mem_start;
 420         unsigned long   mem_end;
 421         unsigned int    irq;
 422         u8              pf_num;
 423 };
 424
 425 struct qed_int_param {
 426         u32     int_mode;
 427         u8      num_vectors;
 428         u8      min_msix_cnt; /* for minimal functionality */
 429 };
 430
 431 struct qed_int_params {
 432         struct qed_int_param    in;
 433         struct qed_int_param    out;
 434         struct msix_entry       *msix_table;
 435         bool                    fp_initialized;
 436         u8                      fp_msix_base;
 437         u8                      fp_msix_cnt;
 438 };
 439
 440 struct qed_dbg_feature {
 441         struct dentry *dentry;
 442         u8 *dump_buf;
 443         u32 buf_size;
 444         u32 dumped_dwords;
 445 };
 446
 447 struct qed_dbg_params {
 448         struct qed_dbg_feature features[DBG_FEATURE_NUM];
 449         u8 engine_for_debug;
 450         bool print_data;
 451 };
 452
 453 struct qed_dev {
 454         u32     dp_module;
 455         u8      dp_level;
 456         char    name[NAME_SIZE];
 457
 458         u8      type;
 459 #define QED_DEV_TYPE_BB (0 << 0)
 460 #define QED_DEV_TYPE_AH BIT(0)
 461 /* Translate type/revision combo into the proper conditions */
 462 #define QED_IS_BB(dev)  ((dev)->type == QED_DEV_TYPE_BB)
 463 #define QED_IS_BB_A0(dev)       (QED_IS_BB(dev) && \
 464                                  CHIP_REV_IS_A0(dev))
 465 #define QED_IS_BB_B0(dev)       (QED_IS_BB(dev) && \
 466                                  CHIP_REV_IS_B0(dev))
 467 #define QED_IS_AH(dev)  ((dev)->type == QED_DEV_TYPE_AH)
 468 #define QED_IS_K2(dev)  QED_IS_AH(dev)
 469
 470 #define QED_GET_TYPE(dev)       (QED_IS_BB_A0(dev) ? CHIP_BB_A0 : \
 471                                  QED_IS_BB_B0(dev) ? CHIP_BB_B0 : CHIP_K2)
 472
 473         u16     vendor_id;
 474         u16     device_id;
 475
 476         u16     chip_num;
 477 #define CHIP_NUM_MASK                   0xffff
 478 #define CHIP_NUM_SHIFT                  16
 479
 480         u16     chip_rev;
 481 #define CHIP_REV_MASK                   0xf
 482 #define CHIP_REV_SHIFT                  12
 483 #define CHIP_REV_IS_A0(_cdev)   (!(_cdev)->chip_rev)
 484 #define CHIP_REV_IS_B0(_cdev)   ((_cdev)->chip_rev == 1)
 485
 486         u16                             chip_metal;
 487 #define CHIP_METAL_MASK                 0xff
 488 #define CHIP_METAL_SHIFT                4
 489
 490         u16                             chip_bond_id;
 491 #define CHIP_BOND_ID_MASK               0xf
 492 #define CHIP_BOND_ID_SHIFT              0
 493
 494         u8                              num_engines;
 495         u8                              num_ports_in_engines;
 496         u8                              num_funcs_in_port;
 497
 498         u8                              path_id;
 499         enum qed_mf_mode                mf_mode;
 500 #define IS_MF_DEFAULT(_p_hwfn)  (((_p_hwfn)->cdev)->mf_mode == QED_MF_DEFAULT)
 501 #define IS_MF_SI(_p_hwfn)       (((_p_hwfn)->cdev)->mf_mode == QED_MF_NPAR)
 502 #define IS_MF_SD(_p_hwfn)       (((_p_hwfn)->cdev)->mf_mode == QED_MF_OVLAN)
 503
 504         int                             pcie_width;
 505         int                             pcie_speed;
 506         u8                              ver_str[VER_SIZE];
 507
 508         /* Add MF related configuration */
 509         u8                              mcp_rev;
 510         u8                              boot_mode;
 511
 512         u8                              wol;
 513
 514         u32                             int_mode;
 515         enum qed_coalescing_mode        int_coalescing_mode;
 516         u16                             rx_coalesce_usecs;
 517         u16                             tx_coalesce_usecs;
 518
 519         /* Start Bar offset of first hwfn */
 520         void __iomem                    *regview;
 521         void __iomem                    *doorbells;
 522         u64                             db_phys_addr;
 523         unsigned long                   db_size;
 524
 525         /* PCI */
 526         u8                              cache_shift;
 527
 528         /* Init */
 529         const struct iro                *iro_arr;
 530 #define IRO (p_hwfn->cdev->iro_arr)
 531
 532         /* HW functions */
 533         u8                              num_hwfns;
 534         struct qed_hwfn                 hwfns[MAX_HWFNS_PER_DEVICE];
 535
 536         /* SRIOV */
 537         struct qed_hw_sriov_info *p_iov_info;
 538 #define IS_QED_SRIOV(cdev)              (!!(cdev)->p_iov_info)
 539
 540         unsigned long                   tunn_mode;
 541
 542         bool                            b_is_vf;
 543         u32                             drv_type;
 544
 545         struct qed_eth_stats            *reset_stats;
 546         struct qed_fw_data              *fw_data;
 547
 548         u32                             mcp_nvm_resp;
 549
 550         /* Linux specific here */
 551         struct  qede_dev                *edev;
 552         struct  pci_dev                 *pdev;
 553         int                             msg_enable;
 554
 555         struct pci_params               pci_params;
 556
 557         struct qed_int_params           int_params;
 558
 559         u8                              protocol;
 560 #define IS_QED_ETH_IF(cdev)     ((cdev)->protocol == QED_PROTOCOL_ETH)
 561
 562         /* Callbacks to protocol driver */
 563         union {
 564                 struct qed_common_cb_ops        *common;
 565                 struct qed_eth_cb_ops           *eth;
 566         } protocol_ops;
 567         void                            *ops_cookie;
 568
 569         struct qed_dbg_params           dbg_params;
 570
 571 #ifdef CONFIG_QED_LL2
 572         struct qed_cb_ll2_info          *ll2;
 573         u8                              ll2_mac_address[ETH_ALEN];
 574 #endif
 575
 576         const struct firmware           *firmware;
 577 };
 578
 579 #define NUM_OF_VFS(dev)         MAX_NUM_VFS_BB
 580 #define NUM_OF_L2_QUEUES(dev)   MAX_NUM_L2_QUEUES_BB
 581 #define NUM_OF_SBS(dev)         MAX_SB_PER_PATH_BB
 582 #define NUM_OF_ENG_PFS(dev)     MAX_NUM_PFS_BB
 583
 584 /**
 585  * @brief qed_concrete_to_sw_fid - get the sw function id from
 586  *        the concrete value.
 587  *
 588  * @param concrete_fid
 589  *
 590  * @return inline u8
 591  */
 592 static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev,
 593                                         u32 concrete_fid)
 594 {
 595         u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);
 596         u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
 597         u8 vf_valid = GET_FIELD(concrete_fid,
 598                                 PXP_CONCRETE_FID_VFVALID);
 599         u8 sw_fid;
 600
 601         if (vf_valid)
 602                 sw_fid = vfid + MAX_NUM_PFS;
 603         else
 604                 sw_fid = pfid;
 605
 606         return sw_fid;
 607 }
 608
 609 #define PURE_LB_TC 8
 610 #define OOO_LB_TC 9
 611
 612 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate);
 613 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, u32 min_pf_rate);
 614
 615 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
 616 #define QED_LEADING_HWFN(dev)   (&dev->hwfns[0])
 617
 618 /* Other Linux specific common definitions */
 619 #define DP_NAME(cdev) ((cdev)->name)
 620
 621 #define REG_ADDR(cdev, offset)          (void __iomem *)((u8 __iomem *)\
 622                                                 (cdev->regview) + \
 623                                                          (offset))
 624
 625 #define REG_RD(cdev, offset)            readl(REG_ADDR(cdev, offset))
 626 #define REG_WR(cdev, offset, val)       writel((u32)val, REG_ADDR(cdev, offset))
 627 #define REG_WR16(cdev, offset, val)     writew((u16)val, REG_ADDR(cdev, offset))
 628
 629 #define DOORBELL(cdev, db_addr, val)                     \
 630         writel((u32)val, (void __iomem *)((u8 __iomem *)\
 631                                           (cdev->doorbells) + (db_addr)))
 632
 633 /* Prototypes */
 634 int qed_fill_dev_info(struct qed_dev *cdev,
 635                       struct qed_dev_info *dev_info);
 636 void qed_link_update(struct qed_hwfn *hwfn);
 637 u32 qed_unzip_data(struct qed_hwfn *p_hwfn,
 638                    u32 input_len, u8 *input_buf,
 639                    u32 max_size, u8 *unzip_buf);
 640 void qed_get_protocol_stats(struct qed_dev *cdev,
 641                             enum qed_mcp_protocol_type type,
 642                             union qed_mcp_protocol_stats *stats);
 643 int qed_slowpath_irq_req(struct qed_hwfn *hwfn);
 644
 645 #endif /* _QED_H */