drivers/net/ethernet/qlogic/qed/qed_cxt.c

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015 QLogic Corporation
   3  *
   4  * This software is available under the terms of the GNU General Public License
   5  * (GPL) Version 2, available from the file COPYING in the main directory of
   6  * this source tree.
   7  */
   8
   9 #include <linux/types.h>
  10 #include <linux/bitops.h>
  11 #include <linux/dma-mapping.h>
  12 #include <linux/errno.h>
  13 #include <linux/kernel.h>
  14 #include <linux/list.h>
  15 #include <linux/log2.h>
  16 #include <linux/pci.h>
  17 #include <linux/slab.h>
  18 #include <linux/string.h>
  19 #include <linux/bitops.h>
  20 #include "qed.h"
  21 #include "qed_cxt.h"
  22 #include "qed_dev_api.h"
  23 #include "qed_hsi.h"
  24 #include "qed_hw.h"
  25 #include "qed_init_ops.h"
  26 #include "qed_reg_addr.h"
  27 #include "qed_sriov.h"
  28
  29 /* Max number of connection types in HW (DQ/CDU etc.) */
  30 #define MAX_CONN_TYPES          PROTOCOLID_COMMON
  31 #define NUM_TASK_TYPES          2
  32 #define NUM_TASK_PF_SEGMENTS    4
  33 #define NUM_TASK_VF_SEGMENTS    1
  34
  35 /* QM constants */
  36 #define QM_PQ_ELEMENT_SIZE      4 /* in bytes */
  37
  38 /* Doorbell-Queue constants */
  39 #define DQ_RANGE_SHIFT          4
  40 #define DQ_RANGE_ALIGN          BIT(DQ_RANGE_SHIFT)
  41
  42 /* Searcher constants */
  43 #define SRC_MIN_NUM_ELEMS 256
  44
  45 /* Timers constants */
  46 #define TM_SHIFT        7
  47 #define TM_ALIGN        BIT(TM_SHIFT)
  48 #define TM_ELEM_SIZE    4
  49
  50 /* ILT constants */
  51 #define ILT_DEFAULT_HW_P_SIZE           3
  52 #define ILT_PAGE_IN_BYTES(hw_p_size)    (1U << ((hw_p_size) + 12))
  53 #define ILT_CFG_REG(cli, reg)   PSWRQ2_REG_ ## cli ## _ ## reg ## _RT_OFFSET
  54
  55 /* ILT entry structure */
  56 #define ILT_ENTRY_PHY_ADDR_MASK         0x000FFFFFFFFFFFULL
  57 #define ILT_ENTRY_PHY_ADDR_SHIFT        0
  58 #define ILT_ENTRY_VALID_MASK            0x1ULL
  59 #define ILT_ENTRY_VALID_SHIFT           52
  60 #define ILT_ENTRY_IN_REGS               2
  61 #define ILT_REG_SIZE_IN_BYTES           4
  62
  63 /* connection context union */
  64 union conn_context {
  65         struct core_conn_context core_ctx;
  66         struct eth_conn_context eth_ctx;
  67         struct iscsi_conn_context iscsi_ctx;
  68         struct roce_conn_context roce_ctx;
  69 };
  70
  71 /* TYPE-0 task context - iSCSI */
  72 union type0_task_context {
  73         struct iscsi_task_context iscsi_ctx;
  74 };
  75
  76 /* TYPE-1 task context - ROCE */
  77 union type1_task_context {
  78         struct rdma_task_context roce_ctx;
  79 };
  80
  81 struct src_ent {
  82         u8 opaque[56];
  83         u64 next;
  84 };
  85
  86 #define CDUT_SEG_ALIGNMET 3     /* in 4k chunks */
  87 #define CDUT_SEG_ALIGNMET_IN_BYTES (1 << (CDUT_SEG_ALIGNMET + 12))
  88
  89 #define CONN_CXT_SIZE(p_hwfn) \
  90         ALIGNED_TYPE_SIZE(union conn_context, p_hwfn)
  91
  92 #define SRQ_CXT_SIZE (sizeof(struct rdma_srq_context))
  93
  94 #define TYPE0_TASK_CXT_SIZE(p_hwfn) \
  95         ALIGNED_TYPE_SIZE(union type0_task_context, p_hwfn)
  96
  97 /* Alignment is inherent to the type1_task_context structure */
  98 #define TYPE1_TASK_CXT_SIZE(p_hwfn) sizeof(union type1_task_context)
  99
 100 /* PF per protocl configuration object */
 101 #define TASK_SEGMENTS   (NUM_TASK_PF_SEGMENTS + NUM_TASK_VF_SEGMENTS)
 102 #define TASK_SEGMENT_VF (NUM_TASK_PF_SEGMENTS)
 103
 104 struct qed_tid_seg {
 105         u32 count;
 106         u8 type;
 107         bool has_fl_mem;
 108 };
 109
 110 struct qed_conn_type_cfg {
 111         u32 cid_count;
 112         u32 cid_start;
 113         u32 cids_per_vf;
 114         struct qed_tid_seg tid_seg[TASK_SEGMENTS];
 115 };
 116
 117 /* ILT Client configuration, Per connection type (protocol) resources. */
 118 #define ILT_CLI_PF_BLOCKS       (1 + NUM_TASK_PF_SEGMENTS * 2)
 119 #define ILT_CLI_VF_BLOCKS       (1 + NUM_TASK_VF_SEGMENTS * 2)
 120 #define CDUC_BLK                (0)
 121 #define SRQ_BLK                 (0)
 122 #define CDUT_SEG_BLK(n)         (1 + (u8)(n))
 123 #define CDUT_FL_SEG_BLK(n, X)   (1 + (n) + NUM_TASK_ ## X ## _SEGMENTS)
 124
 125 enum ilt_clients {
 126         ILT_CLI_CDUC,
 127         ILT_CLI_CDUT,
 128         ILT_CLI_QM,
 129         ILT_CLI_TM,
 130         ILT_CLI_SRC,
 131         ILT_CLI_TSDM,
 132         ILT_CLI_MAX
 133 };
 134
 135 struct ilt_cfg_pair {
 136         u32 reg;
 137         u32 val;
 138 };
 139
 140 struct qed_ilt_cli_blk {
 141         u32 total_size; /* 0 means not active */
 142         u32 real_size_in_page;
 143         u32 start_line;
 144         u32 dynamic_line_cnt;
 145 };
 146
 147 struct qed_ilt_client_cfg {
 148         bool active;
 149
 150         /* ILT boundaries */
 151         struct ilt_cfg_pair first;
 152         struct ilt_cfg_pair last;
 153         struct ilt_cfg_pair p_size;
 154
 155         /* ILT client blocks for PF */
 156         struct qed_ilt_cli_blk pf_blks[ILT_CLI_PF_BLOCKS];
 157         u32 pf_total_lines;
 158
 159         /* ILT client blocks for VFs */
 160         struct qed_ilt_cli_blk vf_blks[ILT_CLI_VF_BLOCKS];
 161         u32 vf_total_lines;
 162 };
 163
 164 /* Per Path -
 165  *      ILT shadow table
 166  *      Protocol acquired CID lists
 167  *      PF start line in ILT
 168  */
 169 struct qed_dma_mem {
 170         dma_addr_t p_phys;
 171         void *p_virt;
 172         size_t size;
 173 };
 174
 175 struct qed_cid_acquired_map {
 176         u32             start_cid;
 177         u32             max_count;
 178         unsigned long   *cid_map;
 179 };
 180
 181 struct qed_cxt_mngr {
 182         /* Per protocl configuration */
 183         struct qed_conn_type_cfg        conn_cfg[MAX_CONN_TYPES];
 184
 185         /* computed ILT structure */
 186         struct qed_ilt_client_cfg       clients[ILT_CLI_MAX];
 187
 188         /* Task type sizes */
 189         u32 task_type_size[NUM_TASK_TYPES];
 190
 191         /* total number of VFs for this hwfn -
 192          * ALL VFs are symmetric in terms of HW resources
 193          */
 194         u32                             vf_count;
 195
 196         /* total number of SRQ's for this hwfn */
 197         u32 srq_count;
 198
 199         /* Acquired CIDs */
 200         struct qed_cid_acquired_map     acquired[MAX_CONN_TYPES];
 201
 202         /* ILT  shadow table */
 203         struct qed_dma_mem              *ilt_shadow;
 204         u32                             pf_start_line;
 205
 206         /* Mutex for a dynamic ILT allocation */
 207         struct mutex mutex;
 208
 209         /* SRC T2 */
 210         struct qed_dma_mem *t2;
 211         u32 t2_num_pages;
 212         u64 first_free;
 213         u64 last_free;
 214 };
 215 static bool src_proto(enum protocol_type type)
 216 {
 217         return type == PROTOCOLID_ISCSI ||
 218                type == PROTOCOLID_ROCE;
 219 }
 220
 221 static bool tm_cid_proto(enum protocol_type type)
 222 {
 223         return type == PROTOCOLID_ISCSI ||
 224                type == PROTOCOLID_ROCE;
 225 }
 226
 227 /* counts the iids for the CDU/CDUC ILT client configuration */
 228 struct qed_cdu_iids {
 229         u32 pf_cids;
 230         u32 per_vf_cids;
 231 };
 232
 233 static void qed_cxt_cdu_iids(struct qed_cxt_mngr *p_mngr,
 234                              struct qed_cdu_iids *iids)
 235 {
 236         u32 type;
 237
 238         for (type = 0; type < MAX_CONN_TYPES; type++) {
 239                 iids->pf_cids += p_mngr->conn_cfg[type].cid_count;
 240                 iids->per_vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
 241         }
 242 }
 243
 244 /* counts the iids for the Searcher block configuration */
 245 struct qed_src_iids {
 246         u32 pf_cids;
 247         u32 per_vf_cids;
 248 };
 249
 250 static void qed_cxt_src_iids(struct qed_cxt_mngr *p_mngr,
 251                              struct qed_src_iids *iids)
 252 {
 253         u32 i;
 254
 255         for (i = 0; i < MAX_CONN_TYPES; i++) {
 256                 if (!src_proto(i))
 257                         continue;
 258
 259                 iids->pf_cids += p_mngr->conn_cfg[i].cid_count;
 260                 iids->per_vf_cids += p_mngr->conn_cfg[i].cids_per_vf;
 261         }
 262 }
 263
 264 /* counts the iids for the Timers block configuration */
 265 struct qed_tm_iids {
 266         u32 pf_cids;
 267         u32 pf_tids[NUM_TASK_PF_SEGMENTS];      /* per segment */
 268         u32 pf_tids_total;
 269         u32 per_vf_cids;
 270         u32 per_vf_tids;
 271 };
 272
 273 static void qed_cxt_tm_iids(struct qed_cxt_mngr *p_mngr,
 274                             struct qed_tm_iids *iids)
 275 {
 276         u32 i, j;
 277
 278         for (i = 0; i < MAX_CONN_TYPES; i++) {
 279                 struct qed_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[i];
 280
 281                 if (tm_cid_proto(i)) {
 282                         iids->pf_cids += p_cfg->cid_count;
 283                         iids->per_vf_cids += p_cfg->cids_per_vf;
 284                 }
 285         }
 286
 287         iids->pf_cids = roundup(iids->pf_cids, TM_ALIGN);
 288         iids->per_vf_cids = roundup(iids->per_vf_cids, TM_ALIGN);
 289         iids->per_vf_tids = roundup(iids->per_vf_tids, TM_ALIGN);
 290
 291         for (iids->pf_tids_total = 0, j = 0; j < NUM_TASK_PF_SEGMENTS; j++) {
 292                 iids->pf_tids[j] = roundup(iids->pf_tids[j], TM_ALIGN);
 293                 iids->pf_tids_total += iids->pf_tids[j];
 294         }
 295 }
 296
 297 static void qed_cxt_qm_iids(struct qed_hwfn *p_hwfn,
 298                             struct qed_qm_iids *iids)
 299 {
 300         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 301         struct qed_tid_seg *segs;
 302         u32 vf_cids = 0, type, j;
 303         u32 vf_tids = 0;
 304
 305         for (type = 0; type < MAX_CONN_TYPES; type++) {
 306                 iids->cids += p_mngr->conn_cfg[type].cid_count;
 307                 vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
 308
 309                 segs = p_mngr->conn_cfg[type].tid_seg;
 310                 /* for each segment there is at most one
 311                  * protocol for which count is not 0.
 312                  */
 313                 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
 314                         iids->tids += segs[j].count;
 315
 316                 /* The last array elelment is for the VFs. As for PF
 317                  * segments there can be only one protocol for
 318                  * which this value is not 0.
 319                  */
 320                 vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
 321         }
 322
 323         iids->vf_cids += vf_cids * p_mngr->vf_count;
 324         iids->tids += vf_tids * p_mngr->vf_count;
 325
 326         DP_VERBOSE(p_hwfn, QED_MSG_ILT,
 327                    "iids: CIDS %08x vf_cids %08x tids %08x vf_tids %08x\n",
 328                    iids->cids, iids->vf_cids, iids->tids, vf_tids);
 329 }
 330
 331 static struct qed_tid_seg *qed_cxt_tid_seg_info(struct qed_hwfn *p_hwfn,
 332                                                 u32 seg)
 333 {
 334         struct qed_cxt_mngr *p_cfg = p_hwfn->p_cxt_mngr;
 335         u32 i;
 336
 337         /* Find the protocol with tid count > 0 for this segment.
 338          * Note: there can only be one and this is already validated.
 339          */
 340         for (i = 0; i < MAX_CONN_TYPES; i++)
 341                 if (p_cfg->conn_cfg[i].tid_seg[seg].count)
 342                         return &p_cfg->conn_cfg[i].tid_seg[seg];
 343         return NULL;
 344 }
 345
 346 void qed_cxt_set_srq_count(struct qed_hwfn *p_hwfn, u32 num_srqs)
 347 {
 348         struct qed_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
 349
 350         p_mgr->srq_count = num_srqs;
 351 }
 352
 353 u32 qed_cxt_get_srq_count(struct qed_hwfn *p_hwfn)
 354 {
 355         struct qed_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
 356
 357         return p_mgr->srq_count;
 358 }
 359
 360 /* set the iids count per protocol */
 361 static void qed_cxt_set_proto_cid_count(struct qed_hwfn *p_hwfn,
 362                                         enum protocol_type type,
 363                                         u32 cid_count, u32 vf_cid_cnt)
 364 {
 365         struct qed_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
 366         struct qed_conn_type_cfg *p_conn = &p_mgr->conn_cfg[type];
 367
 368         p_conn->cid_count = roundup(cid_count, DQ_RANGE_ALIGN);
 369         p_conn->cids_per_vf = roundup(vf_cid_cnt, DQ_RANGE_ALIGN);
 370
 371         if (type == PROTOCOLID_ROCE) {
 372                 u32 page_sz = p_mgr->clients[ILT_CLI_CDUC].p_size.val;
 373                 u32 cxt_size = CONN_CXT_SIZE(p_hwfn);
 374                 u32 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
 375
 376                 p_conn->cid_count = roundup(p_conn->cid_count, elems_per_page);
 377         }
 378 }
 379
 380 u32 qed_cxt_get_proto_cid_count(struct qed_hwfn *p_hwfn,
 381                                 enum protocol_type type, u32 *vf_cid)
 382 {
 383         if (vf_cid)
 384                 *vf_cid = p_hwfn->p_cxt_mngr->conn_cfg[type].cids_per_vf;
 385
 386         return p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
 387 }
 388
 389 u32 qed_cxt_get_proto_cid_start(struct qed_hwfn *p_hwfn,
 390                                 enum protocol_type type)
 391 {
 392         return p_hwfn->p_cxt_mngr->acquired[type].start_cid;
 393 }
 394
 395 u32 qed_cxt_get_proto_tid_count(struct qed_hwfn *p_hwfn,
 396                                 enum protocol_type type)
 397 {
 398         u32 cnt = 0;
 399         int i;
 400
 401         for (i = 0; i < TASK_SEGMENTS; i++)
 402                 cnt += p_hwfn->p_cxt_mngr->conn_cfg[type].tid_seg[i].count;
 403
 404         return cnt;
 405 }
 406
 407 static void qed_cxt_set_proto_tid_count(struct qed_hwfn *p_hwfn,
 408                                         enum protocol_type proto,
 409                                         u8 seg,
 410                                         u8 seg_type, u32 count, bool has_fl)
 411 {
 412         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 413         struct qed_tid_seg *p_seg = &p_mngr->conn_cfg[proto].tid_seg[seg];
 414
 415         p_seg->count = count;
 416         p_seg->has_fl_mem = has_fl;
 417         p_seg->type = seg_type;
 418 }
 419
 420 static void qed_ilt_cli_blk_fill(struct qed_ilt_client_cfg *p_cli,
 421                                  struct qed_ilt_cli_blk *p_blk,
 422                                  u32 start_line, u32 total_size, u32 elem_size)
 423 {
 424         u32 ilt_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val);
 425
 426         /* verify thatits called only once for each block */
 427         if (p_blk->total_size)
 428                 return;
 429
 430         p_blk->total_size = total_size;
 431         p_blk->real_size_in_page = 0;
 432         if (elem_size)
 433                 p_blk->real_size_in_page = (ilt_size / elem_size) * elem_size;
 434         p_blk->start_line = start_line;
 435 }
 436
 437 static void qed_ilt_cli_adv_line(struct qed_hwfn *p_hwfn,
 438                                  struct qed_ilt_client_cfg *p_cli,
 439                                  struct qed_ilt_cli_blk *p_blk,
 440                                  u32 *p_line, enum ilt_clients client_id)
 441 {
 442         if (!p_blk->total_size)
 443                 return;
 444
 445         if (!p_cli->active)
 446                 p_cli->first.val = *p_line;
 447
 448         p_cli->active = true;
 449         *p_line += DIV_ROUND_UP(p_blk->total_size, p_blk->real_size_in_page);
 450         p_cli->last.val = *p_line - 1;
 451
 452         DP_VERBOSE(p_hwfn, QED_MSG_ILT,
 453                    "ILT[Client %d] - Lines: [%08x - %08x]. Block - Size %08x [Real %08x] Start line %d\n",
 454                    client_id, p_cli->first.val,
 455                    p_cli->last.val, p_blk->total_size,
 456                    p_blk->real_size_in_page, p_blk->start_line);
 457 }
 458
 459 static u32 qed_ilt_get_dynamic_line_cnt(struct qed_hwfn *p_hwfn,
 460                                         enum ilt_clients ilt_client)
 461 {
 462         u32 cid_count = p_hwfn->p_cxt_mngr->conn_cfg[PROTOCOLID_ROCE].cid_count;
 463         struct qed_ilt_client_cfg *p_cli;
 464         u32 lines_to_skip = 0;
 465         u32 cxts_per_p;
 466
 467         if (ilt_client == ILT_CLI_CDUC) {
 468                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
 469
 470                 cxts_per_p = ILT_PAGE_IN_BYTES(p_cli->p_size.val) /
 471                     (u32) CONN_CXT_SIZE(p_hwfn);
 472
 473                 lines_to_skip = cid_count / cxts_per_p;
 474         }
 475
 476         return lines_to_skip;
 477 }
 478
 479 int qed_cxt_cfg_ilt_compute(struct qed_hwfn *p_hwfn)
 480 {
 481         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 482         u32 curr_line, total, i, task_size, line;
 483         struct qed_ilt_client_cfg *p_cli;
 484         struct qed_ilt_cli_blk *p_blk;
 485         struct qed_cdu_iids cdu_iids;
 486         struct qed_src_iids src_iids;
 487         struct qed_qm_iids qm_iids;
 488         struct qed_tm_iids tm_iids;
 489         struct qed_tid_seg *p_seg;
 490
 491         memset(&qm_iids, 0, sizeof(qm_iids));
 492         memset(&cdu_iids, 0, sizeof(cdu_iids));
 493         memset(&src_iids, 0, sizeof(src_iids));
 494         memset(&tm_iids, 0, sizeof(tm_iids));
 495
 496         p_mngr->pf_start_line = RESC_START(p_hwfn, QED_ILT);
 497
 498         DP_VERBOSE(p_hwfn, QED_MSG_ILT,
 499                    "hwfn [%d] - Set context manager starting line to be 0x%08x\n",
 500                    p_hwfn->my_id, p_hwfn->p_cxt_mngr->pf_start_line);
 501
 502         /* CDUC */
 503         p_cli = &p_mngr->clients[ILT_CLI_CDUC];
 504         curr_line = p_mngr->pf_start_line;
 505
 506         /* CDUC PF */
 507         p_cli->pf_total_lines = 0;
 508
 509         /* get the counters for the CDUC and QM clients  */
 510         qed_cxt_cdu_iids(p_mngr, &cdu_iids);
 511
 512         p_blk = &p_cli->pf_blks[CDUC_BLK];
 513
 514         total = cdu_iids.pf_cids * CONN_CXT_SIZE(p_hwfn);
 515
 516         qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 517                              total, CONN_CXT_SIZE(p_hwfn));
 518
 519         qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
 520         p_cli->pf_total_lines = curr_line - p_blk->start_line;
 521
 522         p_blk->dynamic_line_cnt = qed_ilt_get_dynamic_line_cnt(p_hwfn,
 523                                                                ILT_CLI_CDUC);
 524
 525         /* CDUC VF */
 526         p_blk = &p_cli->vf_blks[CDUC_BLK];
 527         total = cdu_iids.per_vf_cids * CONN_CXT_SIZE(p_hwfn);
 528
 529         qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 530                              total, CONN_CXT_SIZE(p_hwfn));
 531
 532         qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
 533         p_cli->vf_total_lines = curr_line - p_blk->start_line;
 534
 535         for (i = 1; i < p_mngr->vf_count; i++)
 536                 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 537                                      ILT_CLI_CDUC);
 538
 539         /* CDUT PF */
 540         p_cli = &p_mngr->clients[ILT_CLI_CDUT];
 541         p_cli->first.val = curr_line;
 542
 543         /* first the 'working' task memory */
 544         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
 545                 p_seg = qed_cxt_tid_seg_info(p_hwfn, i);
 546                 if (!p_seg || p_seg->count == 0)
 547                         continue;
 548
 549                 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(i)];
 550                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 551                 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total,
 552                                      p_mngr->task_type_size[p_seg->type]);
 553
 554                 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 555                                      ILT_CLI_CDUT);
 556         }
 557
 558         /* next the 'init' task memory (forced load memory) */
 559         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
 560                 p_seg = qed_cxt_tid_seg_info(p_hwfn, i);
 561                 if (!p_seg || p_seg->count == 0)
 562                         continue;
 563
 564                 p_blk = &p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)];
 565
 566                 if (!p_seg->has_fl_mem) {
 567                         /* The segment is active (total size pf 'working'
 568                          * memory is > 0) but has no FL (forced-load, Init)
 569                          * memory. Thus:
 570                          *
 571                          * 1.   The total-size in the corrsponding FL block of
 572                          *      the ILT client is set to 0 - No ILT line are
 573                          *      provisioned and no ILT memory allocated.
 574                          *
 575                          * 2.   The start-line of said block is set to the
 576                          *      start line of the matching working memory
 577                          *      block in the ILT client. This is later used to
 578                          *      configure the CDU segment offset registers and
 579                          *      results in an FL command for TIDs of this
 580                          *      segement behaves as regular load commands
 581                          *      (loading TIDs from the working memory).
 582                          */
 583                         line = p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line;
 584
 585                         qed_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
 586                         continue;
 587                 }
 588                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 589
 590                 qed_ilt_cli_blk_fill(p_cli, p_blk,
 591                                      curr_line, total,
 592                                      p_mngr->task_type_size[p_seg->type]);
 593
 594                 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 595                                      ILT_CLI_CDUT);
 596         }
 597         p_cli->pf_total_lines = curr_line - p_cli->pf_blks[0].start_line;
 598
 599         /* CDUT VF */
 600         p_seg = qed_cxt_tid_seg_info(p_hwfn, TASK_SEGMENT_VF);
 601         if (p_seg && p_seg->count) {
 602                 /* Stricly speaking we need to iterate over all VF
 603                  * task segment types, but a VF has only 1 segment
 604                  */
 605
 606                 /* 'working' memory */
 607                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 608
 609                 p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
 610                 qed_ilt_cli_blk_fill(p_cli, p_blk,
 611                                      curr_line, total,
 612                                      p_mngr->task_type_size[p_seg->type]);
 613
 614                 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 615                                      ILT_CLI_CDUT);
 616
 617                 /* 'init' memory */
 618                 p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
 619                 if (!p_seg->has_fl_mem) {
 620                         /* see comment above */
 621                         line = p_cli->vf_blks[CDUT_SEG_BLK(0)].start_line;
 622                         qed_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
 623                 } else {
 624                         task_size = p_mngr->task_type_size[p_seg->type];
 625                         qed_ilt_cli_blk_fill(p_cli, p_blk,
 626                                              curr_line, total, task_size);
 627                         qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 628                                              ILT_CLI_CDUT);
 629                 }
 630                 p_cli->vf_total_lines = curr_line -
 631                     p_cli->vf_blks[0].start_line;
 632
 633                 /* Now for the rest of the VFs */
 634                 for (i = 1; i < p_mngr->vf_count; i++) {
 635                         p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
 636                         qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 637                                              ILT_CLI_CDUT);
 638
 639                         p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
 640                         qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 641                                              ILT_CLI_CDUT);
 642                 }
 643         }
 644
 645         /* QM */
 646         p_cli = &p_mngr->clients[ILT_CLI_QM];
 647         p_blk = &p_cli->pf_blks[0];
 648
 649         qed_cxt_qm_iids(p_hwfn, &qm_iids);
 650         total = qed_qm_pf_mem_size(p_hwfn->rel_pf_id, qm_iids.cids,
 651                                    qm_iids.vf_cids, qm_iids.tids,
 652                                    p_hwfn->qm_info.num_pqs,
 653                                    p_hwfn->qm_info.num_vf_pqs);
 654
 655         DP_VERBOSE(p_hwfn,
 656                    QED_MSG_ILT,
 657                    "QM ILT Info, (cids=%d, vf_cids=%d, tids=%d, num_pqs=%d, num_vf_pqs=%d, memory_size=%d)\n",
 658                    qm_iids.cids,
 659                    qm_iids.vf_cids,
 660                    qm_iids.tids,
 661                    p_hwfn->qm_info.num_pqs, p_hwfn->qm_info.num_vf_pqs, total);
 662
 663         qed_ilt_cli_blk_fill(p_cli, p_blk,
 664                              curr_line, total * 0x1000,
 665                              QM_PQ_ELEMENT_SIZE);
 666
 667         qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_QM);
 668         p_cli->pf_total_lines = curr_line - p_blk->start_line;
 669
 670         /* SRC */
 671         p_cli = &p_mngr->clients[ILT_CLI_SRC];
 672         qed_cxt_src_iids(p_mngr, &src_iids);
 673
 674         /* Both the PF and VFs searcher connections are stored in the per PF
 675          * database. Thus sum the PF searcher cids and all the VFs searcher
 676          * cids.
 677          */
 678         total = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
 679         if (total) {
 680                 u32 local_max = max_t(u32, total,
 681                                       SRC_MIN_NUM_ELEMS);
 682
 683                 total = roundup_pow_of_two(local_max);
 684
 685                 p_blk = &p_cli->pf_blks[0];
 686                 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 687                                      total * sizeof(struct src_ent),
 688                                      sizeof(struct src_ent));
 689
 690                 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 691                                      ILT_CLI_SRC);
 692                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 693         }
 694
 695         /* TM PF */
 696         p_cli = &p_mngr->clients[ILT_CLI_TM];
 697         qed_cxt_tm_iids(p_mngr, &tm_iids);
 698         total = tm_iids.pf_cids + tm_iids.pf_tids_total;
 699         if (total) {
 700                 p_blk = &p_cli->pf_blks[0];
 701                 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 702                                      total * TM_ELEM_SIZE, TM_ELEM_SIZE);
 703
 704                 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 705                                      ILT_CLI_TM);
 706                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 707         }
 708
 709         /* TM VF */
 710         total = tm_iids.per_vf_cids + tm_iids.per_vf_tids;
 711         if (total) {
 712                 p_blk = &p_cli->vf_blks[0];
 713                 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 714                                      total * TM_ELEM_SIZE, TM_ELEM_SIZE);
 715
 716                 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 717                                      ILT_CLI_TM);
 718                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 719
 720                 for (i = 1; i < p_mngr->vf_count; i++)
 721                         qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 722                                              ILT_CLI_TM);
 723         }
 724
 725         /* TSDM (SRQ CONTEXT) */
 726         total = qed_cxt_get_srq_count(p_hwfn);
 727
 728         if (total) {
 729                 p_cli = &p_mngr->clients[ILT_CLI_TSDM];
 730                 p_blk = &p_cli->pf_blks[SRQ_BLK];
 731                 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 732                                      total * SRQ_CXT_SIZE, SRQ_CXT_SIZE);
 733
 734                 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 735                                      ILT_CLI_TSDM);
 736                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 737         }
 738
 739         if (curr_line - p_hwfn->p_cxt_mngr->pf_start_line >
 740             RESC_NUM(p_hwfn, QED_ILT)) {
 741                 DP_ERR(p_hwfn, "too many ilt lines...#lines=%d\n",
 742                        curr_line - p_hwfn->p_cxt_mngr->pf_start_line);
 743                 return -EINVAL;
 744         }
 745
 746         return 0;
 747 }
 748
 749 static void qed_cxt_src_t2_free(struct qed_hwfn *p_hwfn)
 750 {
 751         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 752         u32 i;
 753
 754         if (!p_mngr->t2)
 755                 return;
 756
 757         for (i = 0; i < p_mngr->t2_num_pages; i++)
 758                 if (p_mngr->t2[i].p_virt)
 759                         dma_free_coherent(&p_hwfn->cdev->pdev->dev,
 760                                           p_mngr->t2[i].size,
 761                                           p_mngr->t2[i].p_virt,
 762                                           p_mngr->t2[i].p_phys);
 763
 764         kfree(p_mngr->t2);
 765         p_mngr->t2 = NULL;
 766 }
 767
 768 static int qed_cxt_src_t2_alloc(struct qed_hwfn *p_hwfn)
 769 {
 770         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 771         u32 conn_num, total_size, ent_per_page, psz, i;
 772         struct qed_ilt_client_cfg *p_src;
 773         struct qed_src_iids src_iids;
 774         struct qed_dma_mem *p_t2;
 775         int rc;
 776
 777         memset(&src_iids, 0, sizeof(src_iids));
 778
 779         /* if the SRC ILT client is inactive - there are no connection
 780          * requiring the searcer, leave.
 781          */
 782         p_src = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_SRC];
 783         if (!p_src->active)
 784                 return 0;
 785
 786         qed_cxt_src_iids(p_mngr, &src_iids);
 787         conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
 788         total_size = conn_num * sizeof(struct src_ent);
 789
 790         /* use the same page size as the SRC ILT client */
 791         psz = ILT_PAGE_IN_BYTES(p_src->p_size.val);
 792         p_mngr->t2_num_pages = DIV_ROUND_UP(total_size, psz);
 793
 794         /* allocate t2 */
 795         p_mngr->t2 = kzalloc(p_mngr->t2_num_pages * sizeof(struct qed_dma_mem),
 796                              GFP_KERNEL);
 797         if (!p_mngr->t2) {
 798                 DP_NOTICE(p_hwfn, "Failed to allocate t2 table\n");
 799                 rc = -ENOMEM;
 800                 goto t2_fail;
 801         }
 802
 803         /* allocate t2 pages */
 804         for (i = 0; i < p_mngr->t2_num_pages; i++) {
 805                 u32 size = min_t(u32, total_size, psz);
 806                 void **p_virt = &p_mngr->t2[i].p_virt;
 807
 808                 *p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
 809                                              size,
 810                                              &p_mngr->t2[i].p_phys, GFP_KERNEL);
 811                 if (!p_mngr->t2[i].p_virt) {
 812                         rc = -ENOMEM;
 813                         goto t2_fail;
 814                 }
 815                 memset(*p_virt, 0, size);
 816                 p_mngr->t2[i].size = size;
 817                 total_size -= size;
 818         }
 819
 820         /* Set the t2 pointers */
 821
 822         /* entries per page - must be a power of two */
 823         ent_per_page = psz / sizeof(struct src_ent);
 824
 825         p_mngr->first_free = (u64) p_mngr->t2[0].p_phys;
 826
 827         p_t2 = &p_mngr->t2[(conn_num - 1) / ent_per_page];
 828         p_mngr->last_free = (u64) p_t2->p_phys +
 829             ((conn_num - 1) & (ent_per_page - 1)) * sizeof(struct src_ent);
 830
 831         for (i = 0; i < p_mngr->t2_num_pages; i++) {
 832                 u32 ent_num = min_t(u32,
 833                                     ent_per_page,
 834                                     conn_num);
 835                 struct src_ent *entries = p_mngr->t2[i].p_virt;
 836                 u64 p_ent_phys = (u64) p_mngr->t2[i].p_phys, val;
 837                 u32 j;
 838
 839                 for (j = 0; j < ent_num - 1; j++) {
 840                         val = p_ent_phys + (j + 1) * sizeof(struct src_ent);
 841                         entries[j].next = cpu_to_be64(val);
 842                 }
 843
 844                 if (i < p_mngr->t2_num_pages - 1)
 845                         val = (u64) p_mngr->t2[i + 1].p_phys;
 846                 else
 847                         val = 0;
 848                 entries[j].next = cpu_to_be64(val);
 849
 850                 conn_num -= ent_num;
 851         }
 852
 853         return 0;
 854
 855 t2_fail:
 856         qed_cxt_src_t2_free(p_hwfn);
 857         return rc;
 858 }
 859
 860 #define for_each_ilt_valid_client(pos, clients) \
 861         for (pos = 0; pos < ILT_CLI_MAX; pos++) \
 862                 if (!clients[pos].active) {     \
 863                         continue;               \
 864                 } else                          \
 865
 866 /* Total number of ILT lines used by this PF */
 867 static u32 qed_cxt_ilt_shadow_size(struct qed_ilt_client_cfg *ilt_clients)
 868 {
 869         u32 size = 0;
 870         u32 i;
 871
 872         for_each_ilt_valid_client(i, ilt_clients)
 873             size += (ilt_clients[i].last.val - ilt_clients[i].first.val + 1);
 874
 875         return size;
 876 }
 877
 878 static void qed_ilt_shadow_free(struct qed_hwfn *p_hwfn)
 879 {
 880         struct qed_ilt_client_cfg *p_cli = p_hwfn->p_cxt_mngr->clients;
 881         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 882         u32 ilt_size, i;
 883
 884         ilt_size = qed_cxt_ilt_shadow_size(p_cli);
 885
 886         for (i = 0; p_mngr->ilt_shadow && i < ilt_size; i++) {
 887                 struct qed_dma_mem *p_dma = &p_mngr->ilt_shadow[i];
 888
 889                 if (p_dma->p_virt)
 890                         dma_free_coherent(&p_hwfn->cdev->pdev->dev,
 891                                           p_dma->size, p_dma->p_virt,
 892                                           p_dma->p_phys);
 893                 p_dma->p_virt = NULL;
 894         }
 895         kfree(p_mngr->ilt_shadow);
 896 }
 897
 898 static int qed_ilt_blk_alloc(struct qed_hwfn *p_hwfn,
 899                              struct qed_ilt_cli_blk *p_blk,
 900                              enum ilt_clients ilt_client,
 901                              u32 start_line_offset)
 902 {
 903         struct qed_dma_mem *ilt_shadow = p_hwfn->p_cxt_mngr->ilt_shadow;
 904         u32 lines, line, sz_left, lines_to_skip = 0;
 905
 906         /* Special handling for RoCE that supports dynamic allocation */
 907         if ((p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) &&
 908             ((ilt_client == ILT_CLI_CDUT) || ilt_client == ILT_CLI_TSDM))
 909                 return 0;
 910
 911         lines_to_skip = p_blk->dynamic_line_cnt;
 912
 913         if (!p_blk->total_size)
 914                 return 0;
 915
 916         sz_left = p_blk->total_size;
 917         lines = DIV_ROUND_UP(sz_left, p_blk->real_size_in_page) - lines_to_skip;
 918         line = p_blk->start_line + start_line_offset -
 919             p_hwfn->p_cxt_mngr->pf_start_line + lines_to_skip;
 920
 921         for (; lines; lines--) {
 922                 dma_addr_t p_phys;
 923                 void *p_virt;
 924                 u32 size;
 925
 926                 size = min_t(u32, sz_left, p_blk->real_size_in_page);
 927                 p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
 928                                             size, &p_phys, GFP_KERNEL);
 929                 if (!p_virt)
 930                         return -ENOMEM;
 931                 memset(p_virt, 0, size);
 932
 933                 ilt_shadow[line].p_phys = p_phys;
 934                 ilt_shadow[line].p_virt = p_virt;
 935                 ilt_shadow[line].size = size;
 936
 937                 DP_VERBOSE(p_hwfn, QED_MSG_ILT,
 938                            "ILT shadow: Line [%d] Physical 0x%llx Virtual %p Size %d\n",
 939                             line, (u64)p_phys, p_virt, size);
 940
 941                 sz_left -= size;
 942                 line++;
 943         }
 944
 945         return 0;
 946 }
 947
 948 static int qed_ilt_shadow_alloc(struct qed_hwfn *p_hwfn)
 949 {
 950         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 951         struct qed_ilt_client_cfg *clients = p_mngr->clients;
 952         struct qed_ilt_cli_blk *p_blk;
 953         u32 size, i, j, k;
 954         int rc;
 955
 956         size = qed_cxt_ilt_shadow_size(clients);
 957         p_mngr->ilt_shadow = kcalloc(size, sizeof(struct qed_dma_mem),
 958                                      GFP_KERNEL);
 959         if (!p_mngr->ilt_shadow) {
 960                 DP_NOTICE(p_hwfn, "Failed to allocate ilt shadow table\n");
 961                 rc = -ENOMEM;
 962                 goto ilt_shadow_fail;
 963         }
 964
 965         DP_VERBOSE(p_hwfn, QED_MSG_ILT,
 966                    "Allocated 0x%x bytes for ilt shadow\n",
 967                    (u32)(size * sizeof(struct qed_dma_mem)));
 968
 969         for_each_ilt_valid_client(i, clients) {
 970                 for (j = 0; j < ILT_CLI_PF_BLOCKS; j++) {
 971                         p_blk = &clients[i].pf_blks[j];
 972                         rc = qed_ilt_blk_alloc(p_hwfn, p_blk, i, 0);
 973                         if (rc)
 974                                 goto ilt_shadow_fail;
 975                 }
 976                 for (k = 0; k < p_mngr->vf_count; k++) {
 977                         for (j = 0; j < ILT_CLI_VF_BLOCKS; j++) {
 978                                 u32 lines = clients[i].vf_total_lines * k;
 979
 980                                 p_blk = &clients[i].vf_blks[j];
 981                                 rc = qed_ilt_blk_alloc(p_hwfn, p_blk, i, lines);
 982                                 if (rc)
 983                                         goto ilt_shadow_fail;
 984                         }
 985                 }
 986         }
 987
 988         return 0;
 989
 990 ilt_shadow_fail:
 991         qed_ilt_shadow_free(p_hwfn);
 992         return rc;
 993 }
 994
 995 static void qed_cid_map_free(struct qed_hwfn *p_hwfn)
 996 {
 997         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 998         u32 type;
 999
1000         for (type = 0; type < MAX_CONN_TYPES; type++) {
1001                 kfree(p_mngr->acquired[type].cid_map);
1002                 p_mngr->acquired[type].max_count = 0;
1003                 p_mngr->acquired[type].start_cid = 0;
1004         }
1005 }
1006
1007 static int qed_cid_map_alloc(struct qed_hwfn *p_hwfn)
1008 {
1009         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1010         u32 start_cid = 0;
1011         u32 type;
1012
1013         for (type = 0; type < MAX_CONN_TYPES; type++) {
1014                 u32 cid_cnt = p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
1015                 u32 size;
1016
1017                 if (cid_cnt == 0)
1018                         continue;
1019
1020                 size = DIV_ROUND_UP(cid_cnt,
1021                                     sizeof(unsigned long) * BITS_PER_BYTE) *
1022                        sizeof(unsigned long);
1023                 p_mngr->acquired[type].cid_map = kzalloc(size, GFP_KERNEL);
1024                 if (!p_mngr->acquired[type].cid_map)
1025                         goto cid_map_fail;
1026
1027                 p_mngr->acquired[type].max_count = cid_cnt;
1028                 p_mngr->acquired[type].start_cid = start_cid;
1029
1030                 p_hwfn->p_cxt_mngr->conn_cfg[type].cid_start = start_cid;
1031
1032                 DP_VERBOSE(p_hwfn, QED_MSG_CXT,
1033                            "Type %08x start: %08x count %08x\n",
1034                            type, p_mngr->acquired[type].start_cid,
1035                            p_mngr->acquired[type].max_count);
1036                 start_cid += cid_cnt;
1037         }
1038
1039         return 0;
1040
1041 cid_map_fail:
1042         qed_cid_map_free(p_hwfn);
1043         return -ENOMEM;
1044 }
1045
1046 int qed_cxt_mngr_alloc(struct qed_hwfn *p_hwfn)
1047 {
1048         struct qed_ilt_client_cfg *clients;
1049         struct qed_cxt_mngr *p_mngr;
1050         u32 i;
1051
1052         p_mngr = kzalloc(sizeof(*p_mngr), GFP_KERNEL);
1053         if (!p_mngr) {
1054                 DP_NOTICE(p_hwfn, "Failed to allocate `struct qed_cxt_mngr'\n");
1055                 return -ENOMEM;
1056         }
1057
1058         /* Initialize ILT client registers */
1059         clients = p_mngr->clients;
1060         clients[ILT_CLI_CDUC].first.reg = ILT_CFG_REG(CDUC, FIRST_ILT);
1061         clients[ILT_CLI_CDUC].last.reg = ILT_CFG_REG(CDUC, LAST_ILT);
1062         clients[ILT_CLI_CDUC].p_size.reg = ILT_CFG_REG(CDUC, P_SIZE);
1063
1064         clients[ILT_CLI_QM].first.reg = ILT_CFG_REG(QM, FIRST_ILT);
1065         clients[ILT_CLI_QM].last.reg = ILT_CFG_REG(QM, LAST_ILT);
1066         clients[ILT_CLI_QM].p_size.reg = ILT_CFG_REG(QM, P_SIZE);
1067
1068         clients[ILT_CLI_TM].first.reg = ILT_CFG_REG(TM, FIRST_ILT);
1069         clients[ILT_CLI_TM].last.reg = ILT_CFG_REG(TM, LAST_ILT);
1070         clients[ILT_CLI_TM].p_size.reg = ILT_CFG_REG(TM, P_SIZE);
1071
1072         clients[ILT_CLI_SRC].first.reg = ILT_CFG_REG(SRC, FIRST_ILT);
1073         clients[ILT_CLI_SRC].last.reg = ILT_CFG_REG(SRC, LAST_ILT);
1074         clients[ILT_CLI_SRC].p_size.reg = ILT_CFG_REG(SRC, P_SIZE);
1075
1076         clients[ILT_CLI_CDUT].first.reg = ILT_CFG_REG(CDUT, FIRST_ILT);
1077         clients[ILT_CLI_CDUT].last.reg = ILT_CFG_REG(CDUT, LAST_ILT);
1078         clients[ILT_CLI_CDUT].p_size.reg = ILT_CFG_REG(CDUT, P_SIZE);
1079
1080         clients[ILT_CLI_TSDM].first.reg = ILT_CFG_REG(TSDM, FIRST_ILT);
1081         clients[ILT_CLI_TSDM].last.reg = ILT_CFG_REG(TSDM, LAST_ILT);
1082         clients[ILT_CLI_TSDM].p_size.reg = ILT_CFG_REG(TSDM, P_SIZE);
1083         /* default ILT page size for all clients is 32K */
1084         for (i = 0; i < ILT_CLI_MAX; i++)
1085                 p_mngr->clients[i].p_size.val = ILT_DEFAULT_HW_P_SIZE;
1086
1087         /* Initialize task sizes */
1088         p_mngr->task_type_size[0] = TYPE0_TASK_CXT_SIZE(p_hwfn);
1089         p_mngr->task_type_size[1] = TYPE1_TASK_CXT_SIZE(p_hwfn);
1090
1091         if (p_hwfn->cdev->p_iov_info)
1092                 p_mngr->vf_count = p_hwfn->cdev->p_iov_info->total_vfs;
1093         /* Initialize the dynamic ILT allocation mutex */
1094         mutex_init(&p_mngr->mutex);
1095
1096         /* Set the cxt mangr pointer priori to further allocations */
1097         p_hwfn->p_cxt_mngr = p_mngr;
1098
1099         return 0;
1100 }
1101
1102 int qed_cxt_tables_alloc(struct qed_hwfn *p_hwfn)
1103 {
1104         int rc;
1105
1106         /* Allocate the ILT shadow table */
1107         rc = qed_ilt_shadow_alloc(p_hwfn);
1108         if (rc) {
1109                 DP_NOTICE(p_hwfn, "Failed to allocate ilt memory\n");
1110                 goto tables_alloc_fail;
1111         }
1112
1113         /* Allocate the T2  table */
1114         rc = qed_cxt_src_t2_alloc(p_hwfn);
1115         if (rc) {
1116                 DP_NOTICE(p_hwfn, "Failed to allocate T2 memory\n");
1117                 goto tables_alloc_fail;
1118         }
1119
1120         /* Allocate and initialize the acquired cids bitmaps */
1121         rc = qed_cid_map_alloc(p_hwfn);
1122         if (rc) {
1123                 DP_NOTICE(p_hwfn, "Failed to allocate cid maps\n");
1124                 goto tables_alloc_fail;
1125         }
1126
1127         return 0;
1128
1129 tables_alloc_fail:
1130         qed_cxt_mngr_free(p_hwfn);
1131         return rc;
1132 }
1133
1134 void qed_cxt_mngr_free(struct qed_hwfn *p_hwfn)
1135 {
1136         if (!p_hwfn->p_cxt_mngr)
1137                 return;
1138
1139         qed_cid_map_free(p_hwfn);
1140         qed_cxt_src_t2_free(p_hwfn);
1141         qed_ilt_shadow_free(p_hwfn);
1142         kfree(p_hwfn->p_cxt_mngr);
1143
1144         p_hwfn->p_cxt_mngr = NULL;
1145 }
1146
1147 void qed_cxt_mngr_setup(struct qed_hwfn *p_hwfn)
1148 {
1149         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1150         int type;
1151
1152         /* Reset acquired cids */
1153         for (type = 0; type < MAX_CONN_TYPES; type++) {
1154                 u32 cid_cnt = p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
1155
1156                 if (cid_cnt == 0)
1157                         continue;
1158
1159                 memset(p_mngr->acquired[type].cid_map, 0,
1160                        DIV_ROUND_UP(cid_cnt,
1161                                     sizeof(unsigned long) * BITS_PER_BYTE) *
1162                        sizeof(unsigned long));
1163         }
1164 }
1165
1166 /* CDU Common */
1167 #define CDUC_CXT_SIZE_SHIFT \
1168         CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT
1169
1170 #define CDUC_CXT_SIZE_MASK \
1171         (CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE >> CDUC_CXT_SIZE_SHIFT)
1172
1173 #define CDUC_BLOCK_WASTE_SHIFT \
1174         CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT
1175
1176 #define CDUC_BLOCK_WASTE_MASK \
1177         (CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE >> CDUC_BLOCK_WASTE_SHIFT)
1178
1179 #define CDUC_NCIB_SHIFT \
1180         CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT
1181
1182 #define CDUC_NCIB_MASK \
1183         (CDU_REG_CID_ADDR_PARAMS_NCIB >> CDUC_NCIB_SHIFT)
1184
1185 #define CDUT_TYPE0_CXT_SIZE_SHIFT \
1186         CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT
1187
1188 #define CDUT_TYPE0_CXT_SIZE_MASK                \
1189         (CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE >> \
1190          CDUT_TYPE0_CXT_SIZE_SHIFT)
1191
1192 #define CDUT_TYPE0_BLOCK_WASTE_SHIFT \
1193         CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT
1194
1195 #define CDUT_TYPE0_BLOCK_WASTE_MASK                    \
1196         (CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE >> \
1197          CDUT_TYPE0_BLOCK_WASTE_SHIFT)
1198
1199 #define CDUT_TYPE0_NCIB_SHIFT \
1200         CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT
1201
1202 #define CDUT_TYPE0_NCIB_MASK                             \
1203         (CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK >> \
1204          CDUT_TYPE0_NCIB_SHIFT)
1205
1206 #define CDUT_TYPE1_CXT_SIZE_SHIFT \
1207         CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT
1208
1209 #define CDUT_TYPE1_CXT_SIZE_MASK                \
1210         (CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE >> \
1211          CDUT_TYPE1_CXT_SIZE_SHIFT)
1212
1213 #define CDUT_TYPE1_BLOCK_WASTE_SHIFT \
1214         CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT
1215
1216 #define CDUT_TYPE1_BLOCK_WASTE_MASK                    \
1217         (CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE >> \
1218          CDUT_TYPE1_BLOCK_WASTE_SHIFT)
1219
1220 #define CDUT_TYPE1_NCIB_SHIFT \
1221         CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT
1222
1223 #define CDUT_TYPE1_NCIB_MASK                             \
1224         (CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK >> \
1225          CDUT_TYPE1_NCIB_SHIFT)
1226
1227 static void qed_cdu_init_common(struct qed_hwfn *p_hwfn)
1228 {
1229         u32 page_sz, elems_per_page, block_waste, cxt_size, cdu_params = 0;
1230
1231         /* CDUC - connection configuration */
1232         page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1233         cxt_size = CONN_CXT_SIZE(p_hwfn);
1234         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1235         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1236
1237         SET_FIELD(cdu_params, CDUC_CXT_SIZE, cxt_size);
1238         SET_FIELD(cdu_params, CDUC_BLOCK_WASTE, block_waste);
1239         SET_FIELD(cdu_params, CDUC_NCIB, elems_per_page);
1240         STORE_RT_REG(p_hwfn, CDU_REG_CID_ADDR_PARAMS_RT_OFFSET, cdu_params);
1241
1242         /* CDUT - type-0 tasks configuration */
1243         page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT].p_size.val;
1244         cxt_size = p_hwfn->p_cxt_mngr->task_type_size[0];
1245         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1246         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1247
1248         /* cxt size and block-waste are multipes of 8 */
1249         cdu_params = 0;
1250         SET_FIELD(cdu_params, CDUT_TYPE0_CXT_SIZE, (cxt_size >> 3));
1251         SET_FIELD(cdu_params, CDUT_TYPE0_BLOCK_WASTE, (block_waste >> 3));
1252         SET_FIELD(cdu_params, CDUT_TYPE0_NCIB, elems_per_page);
1253         STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT0_PARAMS_RT_OFFSET, cdu_params);
1254
1255         /* CDUT - type-1 tasks configuration */
1256         cxt_size = p_hwfn->p_cxt_mngr->task_type_size[1];
1257         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1258         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1259
1260         /* cxt size and block-waste are multipes of 8 */
1261         cdu_params = 0;
1262         SET_FIELD(cdu_params, CDUT_TYPE1_CXT_SIZE, (cxt_size >> 3));
1263         SET_FIELD(cdu_params, CDUT_TYPE1_BLOCK_WASTE, (block_waste >> 3));
1264         SET_FIELD(cdu_params, CDUT_TYPE1_NCIB, elems_per_page);
1265         STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT1_PARAMS_RT_OFFSET, cdu_params);
1266 }
1267
1268 /* CDU PF */
1269 #define CDU_SEG_REG_TYPE_SHIFT          CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT
1270 #define CDU_SEG_REG_TYPE_MASK           0x1
1271 #define CDU_SEG_REG_OFFSET_SHIFT        0
1272 #define CDU_SEG_REG_OFFSET_MASK         CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK
1273
1274 static void qed_cdu_init_pf(struct qed_hwfn *p_hwfn)
1275 {
1276         struct qed_ilt_client_cfg *p_cli;
1277         struct qed_tid_seg *p_seg;
1278         u32 cdu_seg_params, offset;
1279         int i;
1280
1281         static const u32 rt_type_offset_arr[] = {
1282                 CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET,
1283                 CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET,
1284                 CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET,
1285                 CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET
1286         };
1287
1288         static const u32 rt_type_offset_fl_arr[] = {
1289                 CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET,
1290                 CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET,
1291                 CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET,
1292                 CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET
1293         };
1294
1295         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1296
1297         /* There are initializations only for CDUT during pf Phase */
1298         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1299                 /* Segment 0 */
1300                 p_seg = qed_cxt_tid_seg_info(p_hwfn, i);
1301                 if (!p_seg)
1302                         continue;
1303
1304                 /* Note: start_line is already adjusted for the CDU
1305                  * segment register granularity, so we just need to
1306                  * divide. Adjustment is implicit as we assume ILT
1307                  * Page size is larger than 32K!
1308                  */
1309                 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1310                           (p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line -
1311                            p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1312
1313                 cdu_seg_params = 0;
1314                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1315                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1316                 STORE_RT_REG(p_hwfn, rt_type_offset_arr[i], cdu_seg_params);
1317
1318                 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1319                           (p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)].start_line -
1320                            p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1321
1322                 cdu_seg_params = 0;
1323                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1324                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1325                 STORE_RT_REG(p_hwfn, rt_type_offset_fl_arr[i], cdu_seg_params);
1326         }
1327 }
1328
1329 void qed_qm_init_pf(struct qed_hwfn *p_hwfn)
1330 {
1331         struct qed_qm_pf_rt_init_params params;
1332         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1333         struct qed_qm_iids iids;
1334
1335         memset(&iids, 0, sizeof(iids));
1336         qed_cxt_qm_iids(p_hwfn, &iids);
1337
1338         memset(&params, 0, sizeof(params));
1339         params.port_id = p_hwfn->port_id;
1340         params.pf_id = p_hwfn->rel_pf_id;
1341         params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
1342         params.is_first_pf = p_hwfn->first_on_engine;
1343         params.num_pf_cids = iids.cids;
1344         params.num_vf_cids = iids.vf_cids;
1345         params.start_pq = qm_info->start_pq;
1346         params.num_pf_pqs = qm_info->num_pqs - qm_info->num_vf_pqs;
1347         params.num_vf_pqs = qm_info->num_vf_pqs;
1348         params.start_vport = qm_info->start_vport;
1349         params.num_vports = qm_info->num_vports;
1350         params.pf_wfq = qm_info->pf_wfq;
1351         params.pf_rl = qm_info->pf_rl;
1352         params.pq_params = qm_info->qm_pq_params;
1353         params.vport_params = qm_info->qm_vport_params;
1354
1355         qed_qm_pf_rt_init(p_hwfn, p_hwfn->p_main_ptt, &params);
1356 }
1357
1358 /* CM PF */
1359 static int qed_cm_init_pf(struct qed_hwfn *p_hwfn)
1360 {
1361         union qed_qm_pq_params pq_params;
1362         u16 pq;
1363
1364         /* XCM pure-LB queue */
1365         memset(&pq_params, 0, sizeof(pq_params));
1366         pq_params.core.tc = LB_TC;
1367         pq = qed_get_qm_pq(p_hwfn, PROTOCOLID_CORE, &pq_params);
1368         STORE_RT_REG(p_hwfn, XCM_REG_CON_PHY_Q3_RT_OFFSET, pq);
1369
1370         return 0;
1371 }
1372
1373 /* DQ PF */
1374 static void qed_dq_init_pf(struct qed_hwfn *p_hwfn)
1375 {
1376         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1377         u32 dq_pf_max_cid = 0, dq_vf_max_cid = 0;
1378
1379         dq_pf_max_cid += (p_mngr->conn_cfg[0].cid_count >> DQ_RANGE_SHIFT);
1380         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_0_RT_OFFSET, dq_pf_max_cid);
1381
1382         dq_vf_max_cid += (p_mngr->conn_cfg[0].cids_per_vf >> DQ_RANGE_SHIFT);
1383         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_0_RT_OFFSET, dq_vf_max_cid);
1384
1385         dq_pf_max_cid += (p_mngr->conn_cfg[1].cid_count >> DQ_RANGE_SHIFT);
1386         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_1_RT_OFFSET, dq_pf_max_cid);
1387
1388         dq_vf_max_cid += (p_mngr->conn_cfg[1].cids_per_vf >> DQ_RANGE_SHIFT);
1389         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_1_RT_OFFSET, dq_vf_max_cid);
1390
1391         dq_pf_max_cid += (p_mngr->conn_cfg[2].cid_count >> DQ_RANGE_SHIFT);
1392         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_2_RT_OFFSET, dq_pf_max_cid);
1393
1394         dq_vf_max_cid += (p_mngr->conn_cfg[2].cids_per_vf >> DQ_RANGE_SHIFT);
1395         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_2_RT_OFFSET, dq_vf_max_cid);
1396
1397         dq_pf_max_cid += (p_mngr->conn_cfg[3].cid_count >> DQ_RANGE_SHIFT);
1398         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_3_RT_OFFSET, dq_pf_max_cid);
1399
1400         dq_vf_max_cid += (p_mngr->conn_cfg[3].cids_per_vf >> DQ_RANGE_SHIFT);
1401         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_3_RT_OFFSET, dq_vf_max_cid);
1402
1403         dq_pf_max_cid += (p_mngr->conn_cfg[4].cid_count >> DQ_RANGE_SHIFT);
1404         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_4_RT_OFFSET, dq_pf_max_cid);
1405
1406         dq_vf_max_cid += (p_mngr->conn_cfg[4].cids_per_vf >> DQ_RANGE_SHIFT);
1407         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_4_RT_OFFSET, dq_vf_max_cid);
1408
1409         dq_pf_max_cid += (p_mngr->conn_cfg[5].cid_count >> DQ_RANGE_SHIFT);
1410         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_5_RT_OFFSET, dq_pf_max_cid);
1411
1412         dq_vf_max_cid += (p_mngr->conn_cfg[5].cids_per_vf >> DQ_RANGE_SHIFT);
1413         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_5_RT_OFFSET, dq_vf_max_cid);
1414
1415         /* Connection types 6 & 7 are not in use, yet they must be configured
1416          * as the highest possible connection. Not configuring them means the
1417          * defaults will be  used, and with a large number of cids a bug may
1418          * occur, if the defaults will be smaller than dq_pf_max_cid /
1419          * dq_vf_max_cid.
1420          */
1421         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_6_RT_OFFSET, dq_pf_max_cid);
1422         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_6_RT_OFFSET, dq_vf_max_cid);
1423
1424         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_7_RT_OFFSET, dq_pf_max_cid);
1425         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_7_RT_OFFSET, dq_vf_max_cid);
1426 }
1427
1428 static void qed_ilt_bounds_init(struct qed_hwfn *p_hwfn)
1429 {
1430         struct qed_ilt_client_cfg *ilt_clients;
1431         int i;
1432
1433         ilt_clients = p_hwfn->p_cxt_mngr->clients;
1434         for_each_ilt_valid_client(i, ilt_clients) {
1435                 STORE_RT_REG(p_hwfn,
1436                              ilt_clients[i].first.reg,
1437                              ilt_clients[i].first.val);
1438                 STORE_RT_REG(p_hwfn,
1439                              ilt_clients[i].last.reg, ilt_clients[i].last.val);
1440                 STORE_RT_REG(p_hwfn,
1441                              ilt_clients[i].p_size.reg,
1442                              ilt_clients[i].p_size.val);
1443         }
1444 }
1445
1446 static void qed_ilt_vf_bounds_init(struct qed_hwfn *p_hwfn)
1447 {
1448         struct qed_ilt_client_cfg *p_cli;
1449         u32 blk_factor;
1450
1451         /* For simplicty  we set the 'block' to be an ILT page */
1452         if (p_hwfn->cdev->p_iov_info) {
1453                 struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info;
1454
1455                 STORE_RT_REG(p_hwfn,
1456                              PSWRQ2_REG_VF_BASE_RT_OFFSET,
1457                              p_iov->first_vf_in_pf);
1458                 STORE_RT_REG(p_hwfn,
1459                              PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET,
1460                              p_iov->first_vf_in_pf + p_iov->total_vfs);
1461         }
1462
1463         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
1464         blk_factor = ilog2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1465         if (p_cli->active) {
1466                 STORE_RT_REG(p_hwfn,
1467                              PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET,
1468                              blk_factor);
1469                 STORE_RT_REG(p_hwfn,
1470                              PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1471                              p_cli->pf_total_lines);
1472                 STORE_RT_REG(p_hwfn,
1473                              PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET,
1474                              p_cli->vf_total_lines);
1475         }
1476
1477         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1478         blk_factor = ilog2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1479         if (p_cli->active) {
1480                 STORE_RT_REG(p_hwfn,
1481                              PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET,
1482                              blk_factor);
1483                 STORE_RT_REG(p_hwfn,
1484                              PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1485                              p_cli->pf_total_lines);
1486                 STORE_RT_REG(p_hwfn,
1487                              PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET,
1488                              p_cli->vf_total_lines);
1489         }
1490
1491         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TM];
1492         blk_factor = ilog2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1493         if (p_cli->active) {
1494                 STORE_RT_REG(p_hwfn,
1495                              PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET, blk_factor);
1496                 STORE_RT_REG(p_hwfn,
1497                              PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1498                              p_cli->pf_total_lines);
1499                 STORE_RT_REG(p_hwfn,
1500                              PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET,
1501                              p_cli->vf_total_lines);
1502         }
1503 }
1504
1505 /* ILT (PSWRQ2) PF */
1506 static void qed_ilt_init_pf(struct qed_hwfn *p_hwfn)
1507 {
1508         struct qed_ilt_client_cfg *clients;
1509         struct qed_cxt_mngr *p_mngr;
1510         struct qed_dma_mem *p_shdw;
1511         u32 line, rt_offst, i;
1512
1513         qed_ilt_bounds_init(p_hwfn);
1514         qed_ilt_vf_bounds_init(p_hwfn);
1515
1516         p_mngr = p_hwfn->p_cxt_mngr;
1517         p_shdw = p_mngr->ilt_shadow;
1518         clients = p_hwfn->p_cxt_mngr->clients;
1519
1520         for_each_ilt_valid_client(i, clients) {
1521                 /** Client's 1st val and RT array are absolute, ILT shadows'
1522                  *  lines are relative.
1523                  */
1524                 line = clients[i].first.val - p_mngr->pf_start_line;
1525                 rt_offst = PSWRQ2_REG_ILT_MEMORY_RT_OFFSET +
1526                            clients[i].first.val * ILT_ENTRY_IN_REGS;
1527
1528                 for (; line <= clients[i].last.val - p_mngr->pf_start_line;
1529                      line++, rt_offst += ILT_ENTRY_IN_REGS) {
1530                         u64 ilt_hw_entry = 0;
1531
1532                         /** p_virt could be NULL incase of dynamic
1533                          *  allocation
1534                          */
1535                         if (p_shdw[line].p_virt) {
1536                                 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
1537                                 SET_FIELD(ilt_hw_entry, ILT_ENTRY_PHY_ADDR,
1538                                           (p_shdw[line].p_phys >> 12));
1539
1540                                 DP_VERBOSE(p_hwfn, QED_MSG_ILT,
1541                                            "Setting RT[0x%08x] from ILT[0x%08x] [Client is %d] to Physical addr: 0x%llx\n",
1542                                            rt_offst, line, i,
1543                                            (u64)(p_shdw[line].p_phys >> 12));
1544                         }
1545
1546                         STORE_RT_REG_AGG(p_hwfn, rt_offst, ilt_hw_entry);
1547                 }
1548         }
1549 }
1550
1551 /* SRC (Searcher) PF */
1552 static void qed_src_init_pf(struct qed_hwfn *p_hwfn)
1553 {
1554         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1555         u32 rounded_conn_num, conn_num, conn_max;
1556         struct qed_src_iids src_iids;
1557
1558         memset(&src_iids, 0, sizeof(src_iids));
1559         qed_cxt_src_iids(p_mngr, &src_iids);
1560         conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
1561         if (!conn_num)
1562                 return;
1563
1564         conn_max = max_t(u32, conn_num, SRC_MIN_NUM_ELEMS);
1565         rounded_conn_num = roundup_pow_of_two(conn_max);
1566
1567         STORE_RT_REG(p_hwfn, SRC_REG_COUNTFREE_RT_OFFSET, conn_num);
1568         STORE_RT_REG(p_hwfn, SRC_REG_NUMBER_HASH_BITS_RT_OFFSET,
1569                      ilog2(rounded_conn_num));
1570
1571         STORE_RT_REG_AGG(p_hwfn, SRC_REG_FIRSTFREE_RT_OFFSET,
1572                          p_hwfn->p_cxt_mngr->first_free);
1573         STORE_RT_REG_AGG(p_hwfn, SRC_REG_LASTFREE_RT_OFFSET,
1574                          p_hwfn->p_cxt_mngr->last_free);
1575 }
1576
1577 /* Timers PF */
1578 #define TM_CFG_NUM_IDS_SHIFT            0
1579 #define TM_CFG_NUM_IDS_MASK             0xFFFFULL
1580 #define TM_CFG_PRE_SCAN_OFFSET_SHIFT    16
1581 #define TM_CFG_PRE_SCAN_OFFSET_MASK     0x1FFULL
1582 #define TM_CFG_PARENT_PF_SHIFT          25
1583 #define TM_CFG_PARENT_PF_MASK           0x7ULL
1584
1585 #define TM_CFG_CID_PRE_SCAN_ROWS_SHIFT  30
1586 #define TM_CFG_CID_PRE_SCAN_ROWS_MASK   0x1FFULL
1587
1588 #define TM_CFG_TID_OFFSET_SHIFT         30
1589 #define TM_CFG_TID_OFFSET_MASK          0x7FFFFULL
1590 #define TM_CFG_TID_PRE_SCAN_ROWS_SHIFT  49
1591 #define TM_CFG_TID_PRE_SCAN_ROWS_MASK   0x1FFULL
1592
1593 static void qed_tm_init_pf(struct qed_hwfn *p_hwfn)
1594 {
1595         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1596         u32 active_seg_mask = 0, tm_offset, rt_reg;
1597         struct qed_tm_iids tm_iids;
1598         u64 cfg_word;
1599         u8 i;
1600
1601         memset(&tm_iids, 0, sizeof(tm_iids));
1602         qed_cxt_tm_iids(p_mngr, &tm_iids);
1603
1604         /* @@@TBD No pre-scan for now */
1605
1606         /* Note: We assume consecutive VFs for a PF */
1607         for (i = 0; i < p_mngr->vf_count; i++) {
1608                 cfg_word = 0;
1609                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_cids);
1610                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1611                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1612                 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0);
1613                 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1614                     (sizeof(cfg_word) / sizeof(u32)) *
1615                     (p_hwfn->cdev->p_iov_info->first_vf_in_pf + i);
1616                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1617         }
1618
1619         cfg_word = 0;
1620         SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_cids);
1621         SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1622         SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0);       /* n/a for PF */
1623         SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0);       /* scan all   */
1624
1625         rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1626             (sizeof(cfg_word) / sizeof(u32)) *
1627             (NUM_OF_VFS(p_hwfn->cdev) + p_hwfn->rel_pf_id);
1628         STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1629
1630         /* enale scan */
1631         STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_CONN_RT_OFFSET,
1632                      tm_iids.pf_cids ? 0x1 : 0x0);
1633
1634         /* @@@TBD how to enable the scan for the VFs */
1635
1636         tm_offset = tm_iids.per_vf_cids;
1637
1638         /* Note: We assume consecutive VFs for a PF */
1639         for (i = 0; i < p_mngr->vf_count; i++) {
1640                 cfg_word = 0;
1641                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_tids);
1642                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1643                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1644                 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1645                 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64) 0);
1646
1647                 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1648                     (sizeof(cfg_word) / sizeof(u32)) *
1649                     (p_hwfn->cdev->p_iov_info->first_vf_in_pf + i);
1650
1651                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1652         }
1653
1654         tm_offset = tm_iids.pf_cids;
1655         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1656                 cfg_word = 0;
1657                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_tids[i]);
1658                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1659                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0);
1660                 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1661                 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64) 0);
1662
1663                 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1664                     (sizeof(cfg_word) / sizeof(u32)) *
1665                     (NUM_OF_VFS(p_hwfn->cdev) +
1666                      p_hwfn->rel_pf_id * NUM_TASK_PF_SEGMENTS + i);
1667
1668                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1669                 active_seg_mask |= (tm_iids.pf_tids[i] ? BIT(i) : 0);
1670
1671                 tm_offset += tm_iids.pf_tids[i];
1672         }
1673
1674         if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE)
1675                 active_seg_mask = 0;
1676
1677         STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_TASK_RT_OFFSET, active_seg_mask);
1678
1679         /* @@@TBD how to enable the scan for the VFs */
1680 }
1681
1682 void qed_cxt_hw_init_common(struct qed_hwfn *p_hwfn)
1683 {
1684         qed_cdu_init_common(p_hwfn);
1685 }
1686
1687 void qed_cxt_hw_init_pf(struct qed_hwfn *p_hwfn)
1688 {
1689         qed_qm_init_pf(p_hwfn);
1690         qed_cm_init_pf(p_hwfn);
1691         qed_dq_init_pf(p_hwfn);
1692         qed_cdu_init_pf(p_hwfn);
1693         qed_ilt_init_pf(p_hwfn);
1694         qed_src_init_pf(p_hwfn);
1695         qed_tm_init_pf(p_hwfn);
1696 }
1697
1698 int qed_cxt_acquire_cid(struct qed_hwfn *p_hwfn,
1699                         enum protocol_type type, u32 *p_cid)
1700 {
1701         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1702         u32 rel_cid;
1703
1704         if (type >= MAX_CONN_TYPES || !p_mngr->acquired[type].cid_map) {
1705                 DP_NOTICE(p_hwfn, "Invalid protocol type %d", type);
1706                 return -EINVAL;
1707         }
1708
1709         rel_cid = find_first_zero_bit(p_mngr->acquired[type].cid_map,
1710                                       p_mngr->acquired[type].max_count);
1711
1712         if (rel_cid >= p_mngr->acquired[type].max_count) {
1713                 DP_NOTICE(p_hwfn, "no CID available for protocol %d\n", type);
1714                 return -EINVAL;
1715         }
1716
1717         __set_bit(rel_cid, p_mngr->acquired[type].cid_map);
1718
1719         *p_cid = rel_cid + p_mngr->acquired[type].start_cid;
1720
1721         return 0;
1722 }
1723
1724 static bool qed_cxt_test_cid_acquired(struct qed_hwfn *p_hwfn,
1725                                       u32 cid, enum protocol_type *p_type)
1726 {
1727         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1728         struct qed_cid_acquired_map *p_map;
1729         enum protocol_type p;
1730         u32 rel_cid;
1731
1732         /* Iterate over protocols and find matching cid range */
1733         for (p = 0; p < MAX_CONN_TYPES; p++) {
1734                 p_map = &p_mngr->acquired[p];
1735
1736                 if (!p_map->cid_map)
1737                         continue;
1738                 if (cid >= p_map->start_cid &&
1739                     cid < p_map->start_cid + p_map->max_count)
1740                         break;
1741         }
1742         *p_type = p;
1743
1744         if (p == MAX_CONN_TYPES) {
1745                 DP_NOTICE(p_hwfn, "Invalid CID %d", cid);
1746                 return false;
1747         }
1748
1749         rel_cid = cid - p_map->start_cid;
1750         if (!test_bit(rel_cid, p_map->cid_map)) {
1751                 DP_NOTICE(p_hwfn, "CID %d not acquired", cid);
1752                 return false;
1753         }
1754         return true;
1755 }
1756
1757 void qed_cxt_release_cid(struct qed_hwfn *p_hwfn, u32 cid)
1758 {
1759         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1760         enum protocol_type type;
1761         bool b_acquired;
1762         u32 rel_cid;
1763
1764         /* Test acquired and find matching per-protocol map */
1765         b_acquired = qed_cxt_test_cid_acquired(p_hwfn, cid, &type);
1766
1767         if (!b_acquired)
1768                 return;
1769
1770         rel_cid = cid - p_mngr->acquired[type].start_cid;
1771         __clear_bit(rel_cid, p_mngr->acquired[type].cid_map);
1772 }
1773
1774 int qed_cxt_get_cid_info(struct qed_hwfn *p_hwfn, struct qed_cxt_info *p_info)
1775 {
1776         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1777         u32 conn_cxt_size, hw_p_size, cxts_per_p, line;
1778         enum protocol_type type;
1779         bool b_acquired;
1780
1781         /* Test acquired and find matching per-protocol map */
1782         b_acquired = qed_cxt_test_cid_acquired(p_hwfn, p_info->iid, &type);
1783
1784         if (!b_acquired)
1785                 return -EINVAL;
1786
1787         /* set the protocl type */
1788         p_info->type = type;
1789
1790         /* compute context virtual pointer */
1791         hw_p_size = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1792
1793         conn_cxt_size = CONN_CXT_SIZE(p_hwfn);
1794         cxts_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / conn_cxt_size;
1795         line = p_info->iid / cxts_per_p;
1796
1797         /* Make sure context is allocated (dynamic allocation) */
1798         if (!p_mngr->ilt_shadow[line].p_virt)
1799                 return -EINVAL;
1800
1801         p_info->p_cxt = p_mngr->ilt_shadow[line].p_virt +
1802                         p_info->iid % cxts_per_p * conn_cxt_size;
1803
1804         DP_VERBOSE(p_hwfn, (QED_MSG_ILT | QED_MSG_CXT),
1805                    "Accessing ILT shadow[%d]: CXT pointer is at %p (for iid %d)\n",
1806                    p_info->iid / cxts_per_p, p_info->p_cxt, p_info->iid);
1807
1808         return 0;
1809 }
1810
1811 void qed_rdma_set_pf_params(struct qed_hwfn *p_hwfn,
1812                             struct qed_rdma_pf_params *p_params)
1813 {
1814         u32 num_cons, num_tasks, num_qps, num_mrs, num_srqs;
1815         enum protocol_type proto;
1816
1817         num_mrs = min_t(u32, RDMA_MAX_TIDS, p_params->num_mrs);
1818         num_tasks = num_mrs;    /* each mr uses a single task id */
1819         num_srqs = min_t(u32, 32 * 1024, p_params->num_srqs);
1820
1821         switch (p_hwfn->hw_info.personality) {
1822         case QED_PCI_ETH_ROCE:
1823                 num_qps = min_t(u32, ROCE_MAX_QPS, p_params->num_qps);
1824                 num_cons = num_qps * 2; /* each QP requires two connections */
1825                 proto = PROTOCOLID_ROCE;
1826                 break;
1827         default:
1828                 return;
1829         }
1830
1831         if (num_cons && num_tasks) {
1832                 qed_cxt_set_proto_cid_count(p_hwfn, proto, num_cons, 0);
1833
1834                 /* Deliberatly passing ROCE for tasks id. This is because
1835                  * iWARP / RoCE share the task id.
1836                  */
1837                 qed_cxt_set_proto_tid_count(p_hwfn, PROTOCOLID_ROCE,
1838                                             QED_CXT_ROCE_TID_SEG, 1,
1839                                             num_tasks, false);
1840                 qed_cxt_set_srq_count(p_hwfn, num_srqs);
1841         } else {
1842                 DP_INFO(p_hwfn->cdev,
1843                         "RDMA personality used without setting params!\n");
1844         }
1845 }
1846
1847 int qed_cxt_set_pf_params(struct qed_hwfn *p_hwfn)
1848 {
1849         /* Set the number of required CORE connections */
1850         u32 core_cids = 1; /* SPQ */
1851
1852         qed_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_CORE, core_cids, 0);
1853
1854         switch (p_hwfn->hw_info.personality) {
1855         case QED_PCI_ETH_ROCE:
1856         {
1857                 qed_rdma_set_pf_params(p_hwfn,
1858                                        &p_hwfn->
1859                                        pf_params.rdma_pf_params);
1860                 /* no need for break since RoCE coexist with Ethernet */
1861         }
1862         case QED_PCI_ETH:
1863         {
1864                 struct qed_eth_pf_params *p_params =
1865                     &p_hwfn->pf_params.eth_pf_params;
1866
1867                 qed_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
1868                                             p_params->num_cons, 1);
1869                 break;
1870         }
1871         case QED_PCI_ISCSI:
1872         {
1873                 struct qed_iscsi_pf_params *p_params;
1874
1875                 p_params = &p_hwfn->pf_params.iscsi_pf_params;
1876
1877                 if (p_params->num_cons && p_params->num_tasks) {
1878                         qed_cxt_set_proto_cid_count(p_hwfn,
1879                                                     PROTOCOLID_ISCSI,
1880                                                     p_params->num_cons,
1881                                                     0);
1882
1883                         qed_cxt_set_proto_tid_count(p_hwfn,
1884                                                     PROTOCOLID_ISCSI,
1885                                                     QED_CXT_ISCSI_TID_SEG,
1886                                                     0,
1887                                                     p_params->num_tasks,
1888                                                     true);
1889                 } else {
1890                         DP_INFO(p_hwfn->cdev,
1891                                 "Iscsi personality used without setting params!\n");
1892                 }
1893                 break;
1894         }
1895         default:
1896                 return -EINVAL;
1897         }
1898
1899         return 0;
1900 }
1901
1902 int qed_cxt_get_tid_mem_info(struct qed_hwfn *p_hwfn,
1903                              struct qed_tid_mem *p_info)
1904 {
1905         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1906         u32 proto, seg, total_lines, i, shadow_line;
1907         struct qed_ilt_client_cfg *p_cli;
1908         struct qed_ilt_cli_blk *p_fl_seg;
1909         struct qed_tid_seg *p_seg_info;
1910
1911         /* Verify the personality */
1912         switch (p_hwfn->hw_info.personality) {
1913         case QED_PCI_ISCSI:
1914                 proto = PROTOCOLID_ISCSI;
1915                 seg = QED_CXT_ISCSI_TID_SEG;
1916                 break;
1917         default:
1918                 return -EINVAL;
1919         }
1920
1921         p_cli = &p_mngr->clients[ILT_CLI_CDUT];
1922         if (!p_cli->active)
1923                 return -EINVAL;
1924
1925         p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg];
1926         if (!p_seg_info->has_fl_mem)
1927                 return -EINVAL;
1928
1929         p_fl_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)];
1930         total_lines = DIV_ROUND_UP(p_fl_seg->total_size,
1931                                    p_fl_seg->real_size_in_page);
1932
1933         for (i = 0; i < total_lines; i++) {
1934                 shadow_line = i + p_fl_seg->start_line -
1935                     p_hwfn->p_cxt_mngr->pf_start_line;
1936                 p_info->blocks[i] = p_mngr->ilt_shadow[shadow_line].p_virt;
1937         }
1938         p_info->waste = ILT_PAGE_IN_BYTES(p_cli->p_size.val) -
1939             p_fl_seg->real_size_in_page;
1940         p_info->tid_size = p_mngr->task_type_size[p_seg_info->type];
1941         p_info->num_tids_per_block = p_fl_seg->real_size_in_page /
1942             p_info->tid_size;
1943
1944         return 0;
1945 }
1946
1947 /* This function is very RoCE oriented, if another protocol in the future
1948  * will want this feature we'll need to modify the function to be more generic
1949  */
1950 int
1951 qed_cxt_dynamic_ilt_alloc(struct qed_hwfn *p_hwfn,
1952                           enum qed_cxt_elem_type elem_type, u32 iid)
1953 {
1954         u32 reg_offset, shadow_line, elem_size, hw_p_size, elems_per_p, line;
1955         struct qed_ilt_client_cfg *p_cli;
1956         struct qed_ilt_cli_blk *p_blk;
1957         struct qed_ptt *p_ptt;
1958         dma_addr_t p_phys;
1959         u64 ilt_hw_entry;
1960         void *p_virt;
1961         int rc = 0;
1962
1963         switch (elem_type) {
1964         case QED_ELEM_CXT:
1965                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
1966                 elem_size = CONN_CXT_SIZE(p_hwfn);
1967                 p_blk = &p_cli->pf_blks[CDUC_BLK];
1968                 break;
1969         case QED_ELEM_SRQ:
1970                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
1971                 elem_size = SRQ_CXT_SIZE;
1972                 p_blk = &p_cli->pf_blks[SRQ_BLK];
1973                 break;
1974         case QED_ELEM_TASK:
1975                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1976                 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
1977                 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(QED_CXT_ROCE_TID_SEG)];
1978                 break;
1979         default:
1980                 DP_NOTICE(p_hwfn, "-EINVALID elem type = %d", elem_type);
1981                 return -EINVAL;
1982         }
1983
1984         /* Calculate line in ilt */
1985         hw_p_size = p_cli->p_size.val;
1986         elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
1987         line = p_blk->start_line + (iid / elems_per_p);
1988         shadow_line = line - p_hwfn->p_cxt_mngr->pf_start_line;
1989
1990         /* If line is already allocated, do nothing, otherwise allocate it and
1991          * write it to the PSWRQ2 registers.
1992          * This section can be run in parallel from different contexts and thus
1993          * a mutex protection is needed.
1994          */
1995
1996         mutex_lock(&p_hwfn->p_cxt_mngr->mutex);
1997
1998         if (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt)
1999                 goto out0;
2000
2001         p_ptt = qed_ptt_acquire(p_hwfn);
2002         if (!p_ptt) {
2003                 DP_NOTICE(p_hwfn,
2004                           "QED_TIME_OUT on ptt acquire - dynamic allocation");
2005                 rc = -EBUSY;
2006                 goto out0;
2007         }
2008
2009         p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
2010                                     p_blk->real_size_in_page,
2011                                     &p_phys, GFP_KERNEL);
2012         if (!p_virt) {
2013                 rc = -ENOMEM;
2014                 goto out1;
2015         }
2016         memset(p_virt, 0, p_blk->real_size_in_page);
2017
2018         /* configuration of refTagMask to 0xF is required for RoCE DIF MR only,
2019          * to compensate for a HW bug, but it is configured even if DIF is not
2020          * enabled. This is harmless and allows us to avoid a dedicated API. We
2021          * configure the field for all of the contexts on the newly allocated
2022          * page.
2023          */
2024         if (elem_type == QED_ELEM_TASK) {
2025                 u32 elem_i;
2026                 u8 *elem_start = (u8 *)p_virt;
2027                 union type1_task_context *elem;
2028
2029                 for (elem_i = 0; elem_i < elems_per_p; elem_i++) {
2030                         elem = (union type1_task_context *)elem_start;
2031                         SET_FIELD(elem->roce_ctx.tdif_context.flags1,
2032                                   TDIF_TASK_CONTEXT_REFTAGMASK, 0xf);
2033                         elem_start += TYPE1_TASK_CXT_SIZE(p_hwfn);
2034                 }
2035         }
2036
2037         p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt = p_virt;
2038         p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys = p_phys;
2039         p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].size =
2040             p_blk->real_size_in_page;
2041
2042         /* compute absolute offset */
2043         reg_offset = PSWRQ2_REG_ILT_MEMORY +
2044             (line * ILT_REG_SIZE_IN_BYTES * ILT_ENTRY_IN_REGS);
2045
2046         ilt_hw_entry = 0;
2047         SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
2048         SET_FIELD(ilt_hw_entry,
2049                   ILT_ENTRY_PHY_ADDR,
2050                   (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys >> 12));
2051
2052         /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a wide-bus */
2053         qed_dmae_host2grc(p_hwfn, p_ptt, (u64) (uintptr_t)&ilt_hw_entry,
2054                           reg_offset, sizeof(ilt_hw_entry) / sizeof(u32), 0);
2055
2056         if (elem_type == QED_ELEM_CXT) {
2057                 u32 last_cid_allocated = (1 + (iid / elems_per_p)) *
2058                     elems_per_p;
2059
2060                 /* Update the relevant register in the parser */
2061                 qed_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF,
2062                        last_cid_allocated - 1);
2063
2064                 if (!p_hwfn->b_rdma_enabled_in_prs) {
2065                         /* Enable RoCE search */
2066                         qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 1);
2067                         p_hwfn->b_rdma_enabled_in_prs = true;
2068                 }
2069         }
2070
2071 out1:
2072         qed_ptt_release(p_hwfn, p_ptt);
2073 out0:
2074         mutex_unlock(&p_hwfn->p_cxt_mngr->mutex);
2075
2076         return rc;
2077 }
2078
2079 /* This function is very RoCE oriented, if another protocol in the future
2080  * will want this feature we'll need to modify the function to be more generic
2081  */
2082 static int
2083 qed_cxt_free_ilt_range(struct qed_hwfn *p_hwfn,
2084                        enum qed_cxt_elem_type elem_type,
2085                        u32 start_iid, u32 count)
2086 {
2087         u32 start_line, end_line, shadow_start_line, shadow_end_line;
2088         u32 reg_offset, elem_size, hw_p_size, elems_per_p;
2089         struct qed_ilt_client_cfg *p_cli;
2090         struct qed_ilt_cli_blk *p_blk;
2091         u32 end_iid = start_iid + count;
2092         struct qed_ptt *p_ptt;
2093         u64 ilt_hw_entry = 0;
2094         u32 i;
2095
2096         switch (elem_type) {
2097         case QED_ELEM_CXT:
2098                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
2099                 elem_size = CONN_CXT_SIZE(p_hwfn);
2100                 p_blk = &p_cli->pf_blks[CDUC_BLK];
2101                 break;
2102         case QED_ELEM_SRQ:
2103                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
2104                 elem_size = SRQ_CXT_SIZE;
2105                 p_blk = &p_cli->pf_blks[SRQ_BLK];
2106                 break;
2107         case QED_ELEM_TASK:
2108                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
2109                 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
2110                 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(QED_CXT_ROCE_TID_SEG)];
2111                 break;
2112         default:
2113                 DP_NOTICE(p_hwfn, "-EINVALID elem type = %d", elem_type);
2114                 return -EINVAL;
2115         }
2116
2117         /* Calculate line in ilt */
2118         hw_p_size = p_cli->p_size.val;
2119         elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
2120         start_line = p_blk->start_line + (start_iid / elems_per_p);
2121         end_line = p_blk->start_line + (end_iid / elems_per_p);
2122         if (((end_iid + 1) / elems_per_p) != (end_iid / elems_per_p))
2123                 end_line--;
2124
2125         shadow_start_line = start_line - p_hwfn->p_cxt_mngr->pf_start_line;
2126         shadow_end_line = end_line - p_hwfn->p_cxt_mngr->pf_start_line;
2127
2128         p_ptt = qed_ptt_acquire(p_hwfn);
2129         if (!p_ptt) {
2130                 DP_NOTICE(p_hwfn,
2131                           "QED_TIME_OUT on ptt acquire - dynamic allocation");
2132                 return -EBUSY;
2133         }
2134
2135         for (i = shadow_start_line; i < shadow_end_line; i++) {
2136                 if (!p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt)
2137                         continue;
2138
2139                 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
2140                                   p_hwfn->p_cxt_mngr->ilt_shadow[i].size,
2141                                   p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt,
2142                                   p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys);
2143
2144                 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt = NULL;
2145                 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys = 0;
2146                 p_hwfn->p_cxt_mngr->ilt_shadow[i].size = 0;
2147
2148                 /* compute absolute offset */
2149                 reg_offset = PSWRQ2_REG_ILT_MEMORY +
2150                     ((start_line++) * ILT_REG_SIZE_IN_BYTES *
2151                      ILT_ENTRY_IN_REGS);
2152
2153                 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a
2154                  * wide-bus.
2155                  */
2156                 qed_dmae_host2grc(p_hwfn, p_ptt,
2157                                   (u64) (uintptr_t) &ilt_hw_entry,
2158                                   reg_offset,
2159                                   sizeof(ilt_hw_entry) / sizeof(u32),
2160                                   0);
2161         }
2162
2163         qed_ptt_release(p_hwfn, p_ptt);
2164
2165         return 0;
2166 }
2167
2168 int qed_cxt_free_proto_ilt(struct qed_hwfn *p_hwfn, enum protocol_type proto)
2169 {
2170         int rc;
2171         u32 cid;
2172
2173         /* Free Connection CXT */
2174         rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_CXT,
2175                                     qed_cxt_get_proto_cid_start(p_hwfn,
2176                                                                 proto),
2177                                     qed_cxt_get_proto_cid_count(p_hwfn,
2178                                                                 proto, &cid));
2179
2180         if (rc)
2181                 return rc;
2182
2183         /* Free Task CXT */
2184         rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_TASK, 0,
2185                                     qed_cxt_get_proto_tid_count(p_hwfn, proto));
2186         if (rc)
2187                 return rc;
2188
2189         /* Free TSDM CXT */
2190         rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_SRQ, 0,
2191                                     qed_cxt_get_srq_count(p_hwfn));
2192
2193         return rc;
2194 }
2195
2196 int qed_cxt_get_task_ctx(struct qed_hwfn *p_hwfn,
2197                          u32 tid, u8 ctx_type, void **pp_task_ctx)
2198 {
2199         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
2200         struct qed_ilt_client_cfg *p_cli;
2201         struct qed_ilt_cli_blk *p_seg;
2202         struct qed_tid_seg *p_seg_info;
2203         u32 proto, seg;
2204         u32 total_lines;
2205         u32 tid_size, ilt_idx;
2206         u32 num_tids_per_block;
2207
2208         /* Verify the personality */
2209         switch (p_hwfn->hw_info.personality) {
2210         case QED_PCI_ISCSI:
2211                 proto = PROTOCOLID_ISCSI;
2212                 seg = QED_CXT_ISCSI_TID_SEG;
2213                 break;
2214         default:
2215                 return -EINVAL;
2216         }
2217
2218         p_cli = &p_mngr->clients[ILT_CLI_CDUT];
2219         if (!p_cli->active)
2220                 return -EINVAL;
2221
2222         p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg];
2223
2224         if (ctx_type == QED_CTX_WORKING_MEM) {
2225                 p_seg = &p_cli->pf_blks[CDUT_SEG_BLK(seg)];
2226         } else if (ctx_type == QED_CTX_FL_MEM) {
2227                 if (!p_seg_info->has_fl_mem)
2228                         return -EINVAL;
2229                 p_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)];
2230         } else {
2231                 return -EINVAL;
2232         }
2233         total_lines = DIV_ROUND_UP(p_seg->total_size, p_seg->real_size_in_page);
2234         tid_size = p_mngr->task_type_size[p_seg_info->type];
2235         num_tids_per_block = p_seg->real_size_in_page / tid_size;
2236
2237         if (total_lines < tid / num_tids_per_block)
2238                 return -EINVAL;
2239
2240         ilt_idx = tid / num_tids_per_block + p_seg->start_line -
2241                   p_mngr->pf_start_line;
2242         *pp_task_ctx = (u8 *)p_mngr->ilt_shadow[ilt_idx].p_virt +
2243                        (tid % num_tids_per_block) * tid_size;
2244
2245         return 0;
2246 }