drivers/net/ethernet/qlogic/qed/qed_cxt.c

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015 QLogic Corporation
   3  *
   4  * This software is available under the terms of the GNU General Public License
   5  * (GPL) Version 2, available from the file COPYING in the main directory of
   6  * this source tree.
   7  */
   8
   9 #include <linux/types.h>
  10 #include <linux/bitops.h>
  11 #include <linux/dma-mapping.h>
  12 #include <linux/errno.h>
  13 #include <linux/kernel.h>
  14 #include <linux/list.h>
  15 #include <linux/log2.h>
  16 #include <linux/pci.h>
  17 #include <linux/slab.h>
  18 #include <linux/string.h>
  19 #include <linux/bitops.h>
  20 #include "qed.h"
  21 #include "qed_cxt.h"
  22 #include "qed_dev_api.h"
  23 #include "qed_hsi.h"
  24 #include "qed_hw.h"
  25 #include "qed_init_ops.h"
  26 #include "qed_reg_addr.h"
  27 #include "qed_sriov.h"
  28
  29 /* Max number of connection types in HW (DQ/CDU etc.) */
  30 #define MAX_CONN_TYPES          PROTOCOLID_COMMON
  31 #define NUM_TASK_TYPES          2
  32 #define NUM_TASK_PF_SEGMENTS    4
  33 #define NUM_TASK_VF_SEGMENTS    1
  34
  35 /* QM constants */
  36 #define QM_PQ_ELEMENT_SIZE      4 /* in bytes */
  37
  38 /* Doorbell-Queue constants */
  39 #define DQ_RANGE_SHIFT          4
  40 #define DQ_RANGE_ALIGN          BIT(DQ_RANGE_SHIFT)
  41
  42 /* Searcher constants */
  43 #define SRC_MIN_NUM_ELEMS 256
  44
  45 /* Timers constants */
  46 #define TM_SHIFT        7
  47 #define TM_ALIGN        BIT(TM_SHIFT)
  48 #define TM_ELEM_SIZE    4
  49
  50 /* ILT constants */
  51 #if IS_ENABLED(CONFIG_INFINIBAND_QEDR)
  52 /* For RoCE we configure to 64K to cover for RoCE max tasks 256K purpose. */
  53 #define ILT_DEFAULT_HW_P_SIZE           4
  54 #else
  55 #define ILT_DEFAULT_HW_P_SIZE           3
  56 #endif
  57
  58 #define ILT_PAGE_IN_BYTES(hw_p_size)    (1U << ((hw_p_size) + 12))
  59 #define ILT_CFG_REG(cli, reg)   PSWRQ2_REG_ ## cli ## _ ## reg ## _RT_OFFSET
  60
  61 /* ILT entry structure */
  62 #define ILT_ENTRY_PHY_ADDR_MASK         0x000FFFFFFFFFFFULL
  63 #define ILT_ENTRY_PHY_ADDR_SHIFT        0
  64 #define ILT_ENTRY_VALID_MASK            0x1ULL
  65 #define ILT_ENTRY_VALID_SHIFT           52
  66 #define ILT_ENTRY_IN_REGS               2
  67 #define ILT_REG_SIZE_IN_BYTES           4
  68
  69 /* connection context union */
  70 union conn_context {
  71         struct core_conn_context core_ctx;
  72         struct eth_conn_context eth_ctx;
  73         struct iscsi_conn_context iscsi_ctx;
  74         struct roce_conn_context roce_ctx;
  75 };
  76
  77 /* TYPE-0 task context - iSCSI */
  78 union type0_task_context {
  79         struct iscsi_task_context iscsi_ctx;
  80 };
  81
  82 /* TYPE-1 task context - ROCE */
  83 union type1_task_context {
  84         struct rdma_task_context roce_ctx;
  85 };
  86
  87 struct src_ent {
  88         u8 opaque[56];
  89         u64 next;
  90 };
  91
  92 #define CDUT_SEG_ALIGNMET 3     /* in 4k chunks */
  93 #define CDUT_SEG_ALIGNMET_IN_BYTES (1 << (CDUT_SEG_ALIGNMET + 12))
  94
  95 #define CONN_CXT_SIZE(p_hwfn) \
  96         ALIGNED_TYPE_SIZE(union conn_context, p_hwfn)
  97
  98 #define SRQ_CXT_SIZE (sizeof(struct rdma_srq_context))
  99
 100 #define TYPE0_TASK_CXT_SIZE(p_hwfn) \
 101         ALIGNED_TYPE_SIZE(union type0_task_context, p_hwfn)
 102
 103 /* Alignment is inherent to the type1_task_context structure */
 104 #define TYPE1_TASK_CXT_SIZE(p_hwfn) sizeof(union type1_task_context)
 105
 106 /* PF per protocl configuration object */
 107 #define TASK_SEGMENTS   (NUM_TASK_PF_SEGMENTS + NUM_TASK_VF_SEGMENTS)
 108 #define TASK_SEGMENT_VF (NUM_TASK_PF_SEGMENTS)
 109
 110 struct qed_tid_seg {
 111         u32 count;
 112         u8 type;
 113         bool has_fl_mem;
 114 };
 115
 116 struct qed_conn_type_cfg {
 117         u32 cid_count;
 118         u32 cid_start;
 119         u32 cids_per_vf;
 120         struct qed_tid_seg tid_seg[TASK_SEGMENTS];
 121 };
 122
 123 /* ILT Client configuration, Per connection type (protocol) resources. */
 124 #define ILT_CLI_PF_BLOCKS       (1 + NUM_TASK_PF_SEGMENTS * 2)
 125 #define ILT_CLI_VF_BLOCKS       (1 + NUM_TASK_VF_SEGMENTS * 2)
 126 #define CDUC_BLK                (0)
 127 #define SRQ_BLK                 (0)
 128 #define CDUT_SEG_BLK(n)         (1 + (u8)(n))
 129 #define CDUT_FL_SEG_BLK(n, X)   (1 + (n) + NUM_TASK_ ## X ## _SEGMENTS)
 130
 131 enum ilt_clients {
 132         ILT_CLI_CDUC,
 133         ILT_CLI_CDUT,
 134         ILT_CLI_QM,
 135         ILT_CLI_TM,
 136         ILT_CLI_SRC,
 137         ILT_CLI_TSDM,
 138         ILT_CLI_MAX
 139 };
 140
 141 struct ilt_cfg_pair {
 142         u32 reg;
 143         u32 val;
 144 };
 145
 146 struct qed_ilt_cli_blk {
 147         u32 total_size; /* 0 means not active */
 148         u32 real_size_in_page;
 149         u32 start_line;
 150         u32 dynamic_line_cnt;
 151 };
 152
 153 struct qed_ilt_client_cfg {
 154         bool active;
 155
 156         /* ILT boundaries */
 157         struct ilt_cfg_pair first;
 158         struct ilt_cfg_pair last;
 159         struct ilt_cfg_pair p_size;
 160
 161         /* ILT client blocks for PF */
 162         struct qed_ilt_cli_blk pf_blks[ILT_CLI_PF_BLOCKS];
 163         u32 pf_total_lines;
 164
 165         /* ILT client blocks for VFs */
 166         struct qed_ilt_cli_blk vf_blks[ILT_CLI_VF_BLOCKS];
 167         u32 vf_total_lines;
 168 };
 169
 170 /* Per Path -
 171  *      ILT shadow table
 172  *      Protocol acquired CID lists
 173  *      PF start line in ILT
 174  */
 175 struct qed_dma_mem {
 176         dma_addr_t p_phys;
 177         void *p_virt;
 178         size_t size;
 179 };
 180
 181 struct qed_cid_acquired_map {
 182         u32             start_cid;
 183         u32             max_count;
 184         unsigned long   *cid_map;
 185 };
 186
 187 struct qed_cxt_mngr {
 188         /* Per protocl configuration */
 189         struct qed_conn_type_cfg        conn_cfg[MAX_CONN_TYPES];
 190
 191         /* computed ILT structure */
 192         struct qed_ilt_client_cfg       clients[ILT_CLI_MAX];
 193
 194         /* Task type sizes */
 195         u32 task_type_size[NUM_TASK_TYPES];
 196
 197         /* total number of VFs for this hwfn -
 198          * ALL VFs are symmetric in terms of HW resources
 199          */
 200         u32                             vf_count;
 201
 202         /* total number of SRQ's for this hwfn */
 203         u32 srq_count;
 204
 205         /* Acquired CIDs */
 206         struct qed_cid_acquired_map     acquired[MAX_CONN_TYPES];
 207
 208         /* ILT  shadow table */
 209         struct qed_dma_mem              *ilt_shadow;
 210         u32                             pf_start_line;
 211
 212         /* Mutex for a dynamic ILT allocation */
 213         struct mutex mutex;
 214
 215         /* SRC T2 */
 216         struct qed_dma_mem *t2;
 217         u32 t2_num_pages;
 218         u64 first_free;
 219         u64 last_free;
 220 };
 221 static bool src_proto(enum protocol_type type)
 222 {
 223         return type == PROTOCOLID_ISCSI ||
 224                type == PROTOCOLID_ROCE;
 225 }
 226
 227 static bool tm_cid_proto(enum protocol_type type)
 228 {
 229         return type == PROTOCOLID_ISCSI ||
 230                type == PROTOCOLID_ROCE;
 231 }
 232
 233 /* counts the iids for the CDU/CDUC ILT client configuration */
 234 struct qed_cdu_iids {
 235         u32 pf_cids;
 236         u32 per_vf_cids;
 237 };
 238
 239 static void qed_cxt_cdu_iids(struct qed_cxt_mngr *p_mngr,
 240                              struct qed_cdu_iids *iids)
 241 {
 242         u32 type;
 243
 244         for (type = 0; type < MAX_CONN_TYPES; type++) {
 245                 iids->pf_cids += p_mngr->conn_cfg[type].cid_count;
 246                 iids->per_vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
 247         }
 248 }
 249
 250 /* counts the iids for the Searcher block configuration */
 251 struct qed_src_iids {
 252         u32 pf_cids;
 253         u32 per_vf_cids;
 254 };
 255
 256 static void qed_cxt_src_iids(struct qed_cxt_mngr *p_mngr,
 257                              struct qed_src_iids *iids)
 258 {
 259         u32 i;
 260
 261         for (i = 0; i < MAX_CONN_TYPES; i++) {
 262                 if (!src_proto(i))
 263                         continue;
 264
 265                 iids->pf_cids += p_mngr->conn_cfg[i].cid_count;
 266                 iids->per_vf_cids += p_mngr->conn_cfg[i].cids_per_vf;
 267         }
 268 }
 269
 270 /* counts the iids for the Timers block configuration */
 271 struct qed_tm_iids {
 272         u32 pf_cids;
 273         u32 pf_tids[NUM_TASK_PF_SEGMENTS];      /* per segment */
 274         u32 pf_tids_total;
 275         u32 per_vf_cids;
 276         u32 per_vf_tids;
 277 };
 278
 279 static void qed_cxt_tm_iids(struct qed_cxt_mngr *p_mngr,
 280                             struct qed_tm_iids *iids)
 281 {
 282         u32 i, j;
 283
 284         for (i = 0; i < MAX_CONN_TYPES; i++) {
 285                 struct qed_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[i];
 286
 287                 if (tm_cid_proto(i)) {
 288                         iids->pf_cids += p_cfg->cid_count;
 289                         iids->per_vf_cids += p_cfg->cids_per_vf;
 290                 }
 291         }
 292
 293         iids->pf_cids = roundup(iids->pf_cids, TM_ALIGN);
 294         iids->per_vf_cids = roundup(iids->per_vf_cids, TM_ALIGN);
 295         iids->per_vf_tids = roundup(iids->per_vf_tids, TM_ALIGN);
 296
 297         for (iids->pf_tids_total = 0, j = 0; j < NUM_TASK_PF_SEGMENTS; j++) {
 298                 iids->pf_tids[j] = roundup(iids->pf_tids[j], TM_ALIGN);
 299                 iids->pf_tids_total += iids->pf_tids[j];
 300         }
 301 }
 302
 303 static void qed_cxt_qm_iids(struct qed_hwfn *p_hwfn,
 304                             struct qed_qm_iids *iids)
 305 {
 306         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 307         struct qed_tid_seg *segs;
 308         u32 vf_cids = 0, type, j;
 309         u32 vf_tids = 0;
 310
 311         for (type = 0; type < MAX_CONN_TYPES; type++) {
 312                 iids->cids += p_mngr->conn_cfg[type].cid_count;
 313                 vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
 314
 315                 segs = p_mngr->conn_cfg[type].tid_seg;
 316                 /* for each segment there is at most one
 317                  * protocol for which count is not 0.
 318                  */
 319                 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
 320                         iids->tids += segs[j].count;
 321
 322                 /* The last array elelment is for the VFs. As for PF
 323                  * segments there can be only one protocol for
 324                  * which this value is not 0.
 325                  */
 326                 vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
 327         }
 328
 329         iids->vf_cids += vf_cids * p_mngr->vf_count;
 330         iids->tids += vf_tids * p_mngr->vf_count;
 331
 332         DP_VERBOSE(p_hwfn, QED_MSG_ILT,
 333                    "iids: CIDS %08x vf_cids %08x tids %08x vf_tids %08x\n",
 334                    iids->cids, iids->vf_cids, iids->tids, vf_tids);
 335 }
 336
 337 static struct qed_tid_seg *qed_cxt_tid_seg_info(struct qed_hwfn *p_hwfn,
 338                                                 u32 seg)
 339 {
 340         struct qed_cxt_mngr *p_cfg = p_hwfn->p_cxt_mngr;
 341         u32 i;
 342
 343         /* Find the protocol with tid count > 0 for this segment.
 344          * Note: there can only be one and this is already validated.
 345          */
 346         for (i = 0; i < MAX_CONN_TYPES; i++)
 347                 if (p_cfg->conn_cfg[i].tid_seg[seg].count)
 348                         return &p_cfg->conn_cfg[i].tid_seg[seg];
 349         return NULL;
 350 }
 351
 352 void qed_cxt_set_srq_count(struct qed_hwfn *p_hwfn, u32 num_srqs)
 353 {
 354         struct qed_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
 355
 356         p_mgr->srq_count = num_srqs;
 357 }
 358
 359 u32 qed_cxt_get_srq_count(struct qed_hwfn *p_hwfn)
 360 {
 361         struct qed_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
 362
 363         return p_mgr->srq_count;
 364 }
 365
 366 /* set the iids count per protocol */
 367 static void qed_cxt_set_proto_cid_count(struct qed_hwfn *p_hwfn,
 368                                         enum protocol_type type,
 369                                         u32 cid_count, u32 vf_cid_cnt)
 370 {
 371         struct qed_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
 372         struct qed_conn_type_cfg *p_conn = &p_mgr->conn_cfg[type];
 373
 374         p_conn->cid_count = roundup(cid_count, DQ_RANGE_ALIGN);
 375         p_conn->cids_per_vf = roundup(vf_cid_cnt, DQ_RANGE_ALIGN);
 376
 377         if (type == PROTOCOLID_ROCE) {
 378                 u32 page_sz = p_mgr->clients[ILT_CLI_CDUC].p_size.val;
 379                 u32 cxt_size = CONN_CXT_SIZE(p_hwfn);
 380                 u32 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
 381
 382                 p_conn->cid_count = roundup(p_conn->cid_count, elems_per_page);
 383         }
 384 }
 385
 386 u32 qed_cxt_get_proto_cid_count(struct qed_hwfn *p_hwfn,
 387                                 enum protocol_type type, u32 *vf_cid)
 388 {
 389         if (vf_cid)
 390                 *vf_cid = p_hwfn->p_cxt_mngr->conn_cfg[type].cids_per_vf;
 391
 392         return p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
 393 }
 394
 395 u32 qed_cxt_get_proto_cid_start(struct qed_hwfn *p_hwfn,
 396                                 enum protocol_type type)
 397 {
 398         return p_hwfn->p_cxt_mngr->acquired[type].start_cid;
 399 }
 400
 401 u32 qed_cxt_get_proto_tid_count(struct qed_hwfn *p_hwfn,
 402                                 enum protocol_type type)
 403 {
 404         u32 cnt = 0;
 405         int i;
 406
 407         for (i = 0; i < TASK_SEGMENTS; i++)
 408                 cnt += p_hwfn->p_cxt_mngr->conn_cfg[type].tid_seg[i].count;
 409
 410         return cnt;
 411 }
 412
 413 static void qed_cxt_set_proto_tid_count(struct qed_hwfn *p_hwfn,
 414                                         enum protocol_type proto,
 415                                         u8 seg,
 416                                         u8 seg_type, u32 count, bool has_fl)
 417 {
 418         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 419         struct qed_tid_seg *p_seg = &p_mngr->conn_cfg[proto].tid_seg[seg];
 420
 421         p_seg->count = count;
 422         p_seg->has_fl_mem = has_fl;
 423         p_seg->type = seg_type;
 424 }
 425
 426 static void qed_ilt_cli_blk_fill(struct qed_ilt_client_cfg *p_cli,
 427                                  struct qed_ilt_cli_blk *p_blk,
 428                                  u32 start_line, u32 total_size, u32 elem_size)
 429 {
 430         u32 ilt_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val);
 431
 432         /* verify thatits called only once for each block */
 433         if (p_blk->total_size)
 434                 return;
 435
 436         p_blk->total_size = total_size;
 437         p_blk->real_size_in_page = 0;
 438         if (elem_size)
 439                 p_blk->real_size_in_page = (ilt_size / elem_size) * elem_size;
 440         p_blk->start_line = start_line;
 441 }
 442
 443 static void qed_ilt_cli_adv_line(struct qed_hwfn *p_hwfn,
 444                                  struct qed_ilt_client_cfg *p_cli,
 445                                  struct qed_ilt_cli_blk *p_blk,
 446                                  u32 *p_line, enum ilt_clients client_id)
 447 {
 448         if (!p_blk->total_size)
 449                 return;
 450
 451         if (!p_cli->active)
 452                 p_cli->first.val = *p_line;
 453
 454         p_cli->active = true;
 455         *p_line += DIV_ROUND_UP(p_blk->total_size, p_blk->real_size_in_page);
 456         p_cli->last.val = *p_line - 1;
 457
 458         DP_VERBOSE(p_hwfn, QED_MSG_ILT,
 459                    "ILT[Client %d] - Lines: [%08x - %08x]. Block - Size %08x [Real %08x] Start line %d\n",
 460                    client_id, p_cli->first.val,
 461                    p_cli->last.val, p_blk->total_size,
 462                    p_blk->real_size_in_page, p_blk->start_line);
 463 }
 464
 465 static u32 qed_ilt_get_dynamic_line_cnt(struct qed_hwfn *p_hwfn,
 466                                         enum ilt_clients ilt_client)
 467 {
 468         u32 cid_count = p_hwfn->p_cxt_mngr->conn_cfg[PROTOCOLID_ROCE].cid_count;
 469         struct qed_ilt_client_cfg *p_cli;
 470         u32 lines_to_skip = 0;
 471         u32 cxts_per_p;
 472
 473         if (ilt_client == ILT_CLI_CDUC) {
 474                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
 475
 476                 cxts_per_p = ILT_PAGE_IN_BYTES(p_cli->p_size.val) /
 477                     (u32) CONN_CXT_SIZE(p_hwfn);
 478
 479                 lines_to_skip = cid_count / cxts_per_p;
 480         }
 481
 482         return lines_to_skip;
 483 }
 484
 485 int qed_cxt_cfg_ilt_compute(struct qed_hwfn *p_hwfn)
 486 {
 487         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 488         u32 curr_line, total, i, task_size, line;
 489         struct qed_ilt_client_cfg *p_cli;
 490         struct qed_ilt_cli_blk *p_blk;
 491         struct qed_cdu_iids cdu_iids;
 492         struct qed_src_iids src_iids;
 493         struct qed_qm_iids qm_iids;
 494         struct qed_tm_iids tm_iids;
 495         struct qed_tid_seg *p_seg;
 496
 497         memset(&qm_iids, 0, sizeof(qm_iids));
 498         memset(&cdu_iids, 0, sizeof(cdu_iids));
 499         memset(&src_iids, 0, sizeof(src_iids));
 500         memset(&tm_iids, 0, sizeof(tm_iids));
 501
 502         p_mngr->pf_start_line = RESC_START(p_hwfn, QED_ILT);
 503
 504         DP_VERBOSE(p_hwfn, QED_MSG_ILT,
 505                    "hwfn [%d] - Set context manager starting line to be 0x%08x\n",
 506                    p_hwfn->my_id, p_hwfn->p_cxt_mngr->pf_start_line);
 507
 508         /* CDUC */
 509         p_cli = &p_mngr->clients[ILT_CLI_CDUC];
 510         curr_line = p_mngr->pf_start_line;
 511
 512         /* CDUC PF */
 513         p_cli->pf_total_lines = 0;
 514
 515         /* get the counters for the CDUC and QM clients  */
 516         qed_cxt_cdu_iids(p_mngr, &cdu_iids);
 517
 518         p_blk = &p_cli->pf_blks[CDUC_BLK];
 519
 520         total = cdu_iids.pf_cids * CONN_CXT_SIZE(p_hwfn);
 521
 522         qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 523                              total, CONN_CXT_SIZE(p_hwfn));
 524
 525         qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
 526         p_cli->pf_total_lines = curr_line - p_blk->start_line;
 527
 528         p_blk->dynamic_line_cnt = qed_ilt_get_dynamic_line_cnt(p_hwfn,
 529                                                                ILT_CLI_CDUC);
 530
 531         /* CDUC VF */
 532         p_blk = &p_cli->vf_blks[CDUC_BLK];
 533         total = cdu_iids.per_vf_cids * CONN_CXT_SIZE(p_hwfn);
 534
 535         qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 536                              total, CONN_CXT_SIZE(p_hwfn));
 537
 538         qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
 539         p_cli->vf_total_lines = curr_line - p_blk->start_line;
 540
 541         for (i = 1; i < p_mngr->vf_count; i++)
 542                 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 543                                      ILT_CLI_CDUC);
 544
 545         /* CDUT PF */
 546         p_cli = &p_mngr->clients[ILT_CLI_CDUT];
 547         p_cli->first.val = curr_line;
 548
 549         /* first the 'working' task memory */
 550         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
 551                 p_seg = qed_cxt_tid_seg_info(p_hwfn, i);
 552                 if (!p_seg || p_seg->count == 0)
 553                         continue;
 554
 555                 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(i)];
 556                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 557                 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total,
 558                                      p_mngr->task_type_size[p_seg->type]);
 559
 560                 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 561                                      ILT_CLI_CDUT);
 562         }
 563
 564         /* next the 'init' task memory (forced load memory) */
 565         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
 566                 p_seg = qed_cxt_tid_seg_info(p_hwfn, i);
 567                 if (!p_seg || p_seg->count == 0)
 568                         continue;
 569
 570                 p_blk = &p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)];
 571
 572                 if (!p_seg->has_fl_mem) {
 573                         /* The segment is active (total size pf 'working'
 574                          * memory is > 0) but has no FL (forced-load, Init)
 575                          * memory. Thus:
 576                          *
 577                          * 1.   The total-size in the corrsponding FL block of
 578                          *      the ILT client is set to 0 - No ILT line are
 579                          *      provisioned and no ILT memory allocated.
 580                          *
 581                          * 2.   The start-line of said block is set to the
 582                          *      start line of the matching working memory
 583                          *      block in the ILT client. This is later used to
 584                          *      configure the CDU segment offset registers and
 585                          *      results in an FL command for TIDs of this
 586                          *      segement behaves as regular load commands
 587                          *      (loading TIDs from the working memory).
 588                          */
 589                         line = p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line;
 590
 591                         qed_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
 592                         continue;
 593                 }
 594                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 595
 596                 qed_ilt_cli_blk_fill(p_cli, p_blk,
 597                                      curr_line, total,
 598                                      p_mngr->task_type_size[p_seg->type]);
 599
 600                 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 601                                      ILT_CLI_CDUT);
 602         }
 603         p_cli->pf_total_lines = curr_line - p_cli->pf_blks[0].start_line;
 604
 605         /* CDUT VF */
 606         p_seg = qed_cxt_tid_seg_info(p_hwfn, TASK_SEGMENT_VF);
 607         if (p_seg && p_seg->count) {
 608                 /* Stricly speaking we need to iterate over all VF
 609                  * task segment types, but a VF has only 1 segment
 610                  */
 611
 612                 /* 'working' memory */
 613                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 614
 615                 p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
 616                 qed_ilt_cli_blk_fill(p_cli, p_blk,
 617                                      curr_line, total,
 618                                      p_mngr->task_type_size[p_seg->type]);
 619
 620                 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 621                                      ILT_CLI_CDUT);
 622
 623                 /* 'init' memory */
 624                 p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
 625                 if (!p_seg->has_fl_mem) {
 626                         /* see comment above */
 627                         line = p_cli->vf_blks[CDUT_SEG_BLK(0)].start_line;
 628                         qed_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
 629                 } else {
 630                         task_size = p_mngr->task_type_size[p_seg->type];
 631                         qed_ilt_cli_blk_fill(p_cli, p_blk,
 632                                              curr_line, total, task_size);
 633                         qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 634                                              ILT_CLI_CDUT);
 635                 }
 636                 p_cli->vf_total_lines = curr_line -
 637                     p_cli->vf_blks[0].start_line;
 638
 639                 /* Now for the rest of the VFs */
 640                 for (i = 1; i < p_mngr->vf_count; i++) {
 641                         p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
 642                         qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 643                                              ILT_CLI_CDUT);
 644
 645                         p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
 646                         qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 647                                              ILT_CLI_CDUT);
 648                 }
 649         }
 650
 651         /* QM */
 652         p_cli = &p_mngr->clients[ILT_CLI_QM];
 653         p_blk = &p_cli->pf_blks[0];
 654
 655         qed_cxt_qm_iids(p_hwfn, &qm_iids);
 656         total = qed_qm_pf_mem_size(p_hwfn->rel_pf_id, qm_iids.cids,
 657                                    qm_iids.vf_cids, qm_iids.tids,
 658                                    p_hwfn->qm_info.num_pqs,
 659                                    p_hwfn->qm_info.num_vf_pqs);
 660
 661         DP_VERBOSE(p_hwfn,
 662                    QED_MSG_ILT,
 663                    "QM ILT Info, (cids=%d, vf_cids=%d, tids=%d, num_pqs=%d, num_vf_pqs=%d, memory_size=%d)\n",
 664                    qm_iids.cids,
 665                    qm_iids.vf_cids,
 666                    qm_iids.tids,
 667                    p_hwfn->qm_info.num_pqs, p_hwfn->qm_info.num_vf_pqs, total);
 668
 669         qed_ilt_cli_blk_fill(p_cli, p_blk,
 670                              curr_line, total * 0x1000,
 671                              QM_PQ_ELEMENT_SIZE);
 672
 673         qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_QM);
 674         p_cli->pf_total_lines = curr_line - p_blk->start_line;
 675
 676         /* SRC */
 677         p_cli = &p_mngr->clients[ILT_CLI_SRC];
 678         qed_cxt_src_iids(p_mngr, &src_iids);
 679
 680         /* Both the PF and VFs searcher connections are stored in the per PF
 681          * database. Thus sum the PF searcher cids and all the VFs searcher
 682          * cids.
 683          */
 684         total = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
 685         if (total) {
 686                 u32 local_max = max_t(u32, total,
 687                                       SRC_MIN_NUM_ELEMS);
 688
 689                 total = roundup_pow_of_two(local_max);
 690
 691                 p_blk = &p_cli->pf_blks[0];
 692                 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 693                                      total * sizeof(struct src_ent),
 694                                      sizeof(struct src_ent));
 695
 696                 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 697                                      ILT_CLI_SRC);
 698                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 699         }
 700
 701         /* TM PF */
 702         p_cli = &p_mngr->clients[ILT_CLI_TM];
 703         qed_cxt_tm_iids(p_mngr, &tm_iids);
 704         total = tm_iids.pf_cids + tm_iids.pf_tids_total;
 705         if (total) {
 706                 p_blk = &p_cli->pf_blks[0];
 707                 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 708                                      total * TM_ELEM_SIZE, TM_ELEM_SIZE);
 709
 710                 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 711                                      ILT_CLI_TM);
 712                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 713         }
 714
 715         /* TM VF */
 716         total = tm_iids.per_vf_cids + tm_iids.per_vf_tids;
 717         if (total) {
 718                 p_blk = &p_cli->vf_blks[0];
 719                 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 720                                      total * TM_ELEM_SIZE, TM_ELEM_SIZE);
 721
 722                 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 723                                      ILT_CLI_TM);
 724                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 725
 726                 for (i = 1; i < p_mngr->vf_count; i++)
 727                         qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 728                                              ILT_CLI_TM);
 729         }
 730
 731         /* TSDM (SRQ CONTEXT) */
 732         total = qed_cxt_get_srq_count(p_hwfn);
 733
 734         if (total) {
 735                 p_cli = &p_mngr->clients[ILT_CLI_TSDM];
 736                 p_blk = &p_cli->pf_blks[SRQ_BLK];
 737                 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 738                                      total * SRQ_CXT_SIZE, SRQ_CXT_SIZE);
 739
 740                 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 741                                      ILT_CLI_TSDM);
 742                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 743         }
 744
 745         if (curr_line - p_hwfn->p_cxt_mngr->pf_start_line >
 746             RESC_NUM(p_hwfn, QED_ILT)) {
 747                 DP_ERR(p_hwfn, "too many ilt lines...#lines=%d\n",
 748                        curr_line - p_hwfn->p_cxt_mngr->pf_start_line);
 749                 return -EINVAL;
 750         }
 751
 752         return 0;
 753 }
 754
 755 static void qed_cxt_src_t2_free(struct qed_hwfn *p_hwfn)
 756 {
 757         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 758         u32 i;
 759
 760         if (!p_mngr->t2)
 761                 return;
 762
 763         for (i = 0; i < p_mngr->t2_num_pages; i++)
 764                 if (p_mngr->t2[i].p_virt)
 765                         dma_free_coherent(&p_hwfn->cdev->pdev->dev,
 766                                           p_mngr->t2[i].size,
 767                                           p_mngr->t2[i].p_virt,
 768                                           p_mngr->t2[i].p_phys);
 769
 770         kfree(p_mngr->t2);
 771         p_mngr->t2 = NULL;
 772 }
 773
 774 static int qed_cxt_src_t2_alloc(struct qed_hwfn *p_hwfn)
 775 {
 776         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 777         u32 conn_num, total_size, ent_per_page, psz, i;
 778         struct qed_ilt_client_cfg *p_src;
 779         struct qed_src_iids src_iids;
 780         struct qed_dma_mem *p_t2;
 781         int rc;
 782
 783         memset(&src_iids, 0, sizeof(src_iids));
 784
 785         /* if the SRC ILT client is inactive - there are no connection
 786          * requiring the searcer, leave.
 787          */
 788         p_src = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_SRC];
 789         if (!p_src->active)
 790                 return 0;
 791
 792         qed_cxt_src_iids(p_mngr, &src_iids);
 793         conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
 794         total_size = conn_num * sizeof(struct src_ent);
 795
 796         /* use the same page size as the SRC ILT client */
 797         psz = ILT_PAGE_IN_BYTES(p_src->p_size.val);
 798         p_mngr->t2_num_pages = DIV_ROUND_UP(total_size, psz);
 799
 800         /* allocate t2 */
 801         p_mngr->t2 = kcalloc(p_mngr->t2_num_pages, sizeof(struct qed_dma_mem),
 802                              GFP_KERNEL);
 803         if (!p_mngr->t2) {
 804                 rc = -ENOMEM;
 805                 goto t2_fail;
 806         }
 807
 808         /* allocate t2 pages */
 809         for (i = 0; i < p_mngr->t2_num_pages; i++) {
 810                 u32 size = min_t(u32, total_size, psz);
 811                 void **p_virt = &p_mngr->t2[i].p_virt;
 812
 813                 *p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
 814                                              size,
 815                                              &p_mngr->t2[i].p_phys, GFP_KERNEL);
 816                 if (!p_mngr->t2[i].p_virt) {
 817                         rc = -ENOMEM;
 818                         goto t2_fail;
 819                 }
 820                 memset(*p_virt, 0, size);
 821                 p_mngr->t2[i].size = size;
 822                 total_size -= size;
 823         }
 824
 825         /* Set the t2 pointers */
 826
 827         /* entries per page - must be a power of two */
 828         ent_per_page = psz / sizeof(struct src_ent);
 829
 830         p_mngr->first_free = (u64) p_mngr->t2[0].p_phys;
 831
 832         p_t2 = &p_mngr->t2[(conn_num - 1) / ent_per_page];
 833         p_mngr->last_free = (u64) p_t2->p_phys +
 834             ((conn_num - 1) & (ent_per_page - 1)) * sizeof(struct src_ent);
 835
 836         for (i = 0; i < p_mngr->t2_num_pages; i++) {
 837                 u32 ent_num = min_t(u32,
 838                                     ent_per_page,
 839                                     conn_num);
 840                 struct src_ent *entries = p_mngr->t2[i].p_virt;
 841                 u64 p_ent_phys = (u64) p_mngr->t2[i].p_phys, val;
 842                 u32 j;
 843
 844                 for (j = 0; j < ent_num - 1; j++) {
 845                         val = p_ent_phys + (j + 1) * sizeof(struct src_ent);
 846                         entries[j].next = cpu_to_be64(val);
 847                 }
 848
 849                 if (i < p_mngr->t2_num_pages - 1)
 850                         val = (u64) p_mngr->t2[i + 1].p_phys;
 851                 else
 852                         val = 0;
 853                 entries[j].next = cpu_to_be64(val);
 854
 855                 conn_num -= ent_num;
 856         }
 857
 858         return 0;
 859
 860 t2_fail:
 861         qed_cxt_src_t2_free(p_hwfn);
 862         return rc;
 863 }
 864
 865 #define for_each_ilt_valid_client(pos, clients) \
 866         for (pos = 0; pos < ILT_CLI_MAX; pos++) \
 867                 if (!clients[pos].active) {     \
 868                         continue;               \
 869                 } else                          \
 870
 871 /* Total number of ILT lines used by this PF */
 872 static u32 qed_cxt_ilt_shadow_size(struct qed_ilt_client_cfg *ilt_clients)
 873 {
 874         u32 size = 0;
 875         u32 i;
 876
 877         for_each_ilt_valid_client(i, ilt_clients)
 878             size += (ilt_clients[i].last.val - ilt_clients[i].first.val + 1);
 879
 880         return size;
 881 }
 882
 883 static void qed_ilt_shadow_free(struct qed_hwfn *p_hwfn)
 884 {
 885         struct qed_ilt_client_cfg *p_cli = p_hwfn->p_cxt_mngr->clients;
 886         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 887         u32 ilt_size, i;
 888
 889         ilt_size = qed_cxt_ilt_shadow_size(p_cli);
 890
 891         for (i = 0; p_mngr->ilt_shadow && i < ilt_size; i++) {
 892                 struct qed_dma_mem *p_dma = &p_mngr->ilt_shadow[i];
 893
 894                 if (p_dma->p_virt)
 895                         dma_free_coherent(&p_hwfn->cdev->pdev->dev,
 896                                           p_dma->size, p_dma->p_virt,
 897                                           p_dma->p_phys);
 898                 p_dma->p_virt = NULL;
 899         }
 900         kfree(p_mngr->ilt_shadow);
 901 }
 902
 903 static int qed_ilt_blk_alloc(struct qed_hwfn *p_hwfn,
 904                              struct qed_ilt_cli_blk *p_blk,
 905                              enum ilt_clients ilt_client,
 906                              u32 start_line_offset)
 907 {
 908         struct qed_dma_mem *ilt_shadow = p_hwfn->p_cxt_mngr->ilt_shadow;
 909         u32 lines, line, sz_left, lines_to_skip = 0;
 910
 911         /* Special handling for RoCE that supports dynamic allocation */
 912         if ((p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) &&
 913             ((ilt_client == ILT_CLI_CDUT) || ilt_client == ILT_CLI_TSDM))
 914                 return 0;
 915
 916         lines_to_skip = p_blk->dynamic_line_cnt;
 917
 918         if (!p_blk->total_size)
 919                 return 0;
 920
 921         sz_left = p_blk->total_size;
 922         lines = DIV_ROUND_UP(sz_left, p_blk->real_size_in_page) - lines_to_skip;
 923         line = p_blk->start_line + start_line_offset -
 924             p_hwfn->p_cxt_mngr->pf_start_line + lines_to_skip;
 925
 926         for (; lines; lines--) {
 927                 dma_addr_t p_phys;
 928                 void *p_virt;
 929                 u32 size;
 930
 931                 size = min_t(u32, sz_left, p_blk->real_size_in_page);
 932                 p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
 933                                             size, &p_phys, GFP_KERNEL);
 934                 if (!p_virt)
 935                         return -ENOMEM;
 936                 memset(p_virt, 0, size);
 937
 938                 ilt_shadow[line].p_phys = p_phys;
 939                 ilt_shadow[line].p_virt = p_virt;
 940                 ilt_shadow[line].size = size;
 941
 942                 DP_VERBOSE(p_hwfn, QED_MSG_ILT,
 943                            "ILT shadow: Line [%d] Physical 0x%llx Virtual %p Size %d\n",
 944                             line, (u64)p_phys, p_virt, size);
 945
 946                 sz_left -= size;
 947                 line++;
 948         }
 949
 950         return 0;
 951 }
 952
 953 static int qed_ilt_shadow_alloc(struct qed_hwfn *p_hwfn)
 954 {
 955         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 956         struct qed_ilt_client_cfg *clients = p_mngr->clients;
 957         struct qed_ilt_cli_blk *p_blk;
 958         u32 size, i, j, k;
 959         int rc;
 960
 961         size = qed_cxt_ilt_shadow_size(clients);
 962         p_mngr->ilt_shadow = kcalloc(size, sizeof(struct qed_dma_mem),
 963                                      GFP_KERNEL);
 964         if (!p_mngr->ilt_shadow) {
 965                 rc = -ENOMEM;
 966                 goto ilt_shadow_fail;
 967         }
 968
 969         DP_VERBOSE(p_hwfn, QED_MSG_ILT,
 970                    "Allocated 0x%x bytes for ilt shadow\n",
 971                    (u32)(size * sizeof(struct qed_dma_mem)));
 972
 973         for_each_ilt_valid_client(i, clients) {
 974                 for (j = 0; j < ILT_CLI_PF_BLOCKS; j++) {
 975                         p_blk = &clients[i].pf_blks[j];
 976                         rc = qed_ilt_blk_alloc(p_hwfn, p_blk, i, 0);
 977                         if (rc)
 978                                 goto ilt_shadow_fail;
 979                 }
 980                 for (k = 0; k < p_mngr->vf_count; k++) {
 981                         for (j = 0; j < ILT_CLI_VF_BLOCKS; j++) {
 982                                 u32 lines = clients[i].vf_total_lines * k;
 983
 984                                 p_blk = &clients[i].vf_blks[j];
 985                                 rc = qed_ilt_blk_alloc(p_hwfn, p_blk, i, lines);
 986                                 if (rc)
 987                                         goto ilt_shadow_fail;
 988                         }
 989                 }
 990         }
 991
 992         return 0;
 993
 994 ilt_shadow_fail:
 995         qed_ilt_shadow_free(p_hwfn);
 996         return rc;
 997 }
 998
 999 static void qed_cid_map_free(struct qed_hwfn *p_hwfn)
1000 {
1001         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1002         u32 type;
1003
1004         for (type = 0; type < MAX_CONN_TYPES; type++) {
1005                 kfree(p_mngr->acquired[type].cid_map);
1006                 p_mngr->acquired[type].max_count = 0;
1007                 p_mngr->acquired[type].start_cid = 0;
1008         }
1009 }
1010
1011 static int qed_cid_map_alloc(struct qed_hwfn *p_hwfn)
1012 {
1013         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1014         u32 start_cid = 0;
1015         u32 type;
1016
1017         for (type = 0; type < MAX_CONN_TYPES; type++) {
1018                 u32 cid_cnt = p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
1019                 u32 size;
1020
1021                 if (cid_cnt == 0)
1022                         continue;
1023
1024                 size = DIV_ROUND_UP(cid_cnt,
1025                                     sizeof(unsigned long) * BITS_PER_BYTE) *
1026                        sizeof(unsigned long);
1027                 p_mngr->acquired[type].cid_map = kzalloc(size, GFP_KERNEL);
1028                 if (!p_mngr->acquired[type].cid_map)
1029                         goto cid_map_fail;
1030
1031                 p_mngr->acquired[type].max_count = cid_cnt;
1032                 p_mngr->acquired[type].start_cid = start_cid;
1033
1034                 p_hwfn->p_cxt_mngr->conn_cfg[type].cid_start = start_cid;
1035
1036                 DP_VERBOSE(p_hwfn, QED_MSG_CXT,
1037                            "Type %08x start: %08x count %08x\n",
1038                            type, p_mngr->acquired[type].start_cid,
1039                            p_mngr->acquired[type].max_count);
1040                 start_cid += cid_cnt;
1041         }
1042
1043         return 0;
1044
1045 cid_map_fail:
1046         qed_cid_map_free(p_hwfn);
1047         return -ENOMEM;
1048 }
1049
1050 int qed_cxt_mngr_alloc(struct qed_hwfn *p_hwfn)
1051 {
1052         struct qed_ilt_client_cfg *clients;
1053         struct qed_cxt_mngr *p_mngr;
1054         u32 i;
1055
1056         p_mngr = kzalloc(sizeof(*p_mngr), GFP_KERNEL);
1057         if (!p_mngr)
1058                 return -ENOMEM;
1059
1060         /* Initialize ILT client registers */
1061         clients = p_mngr->clients;
1062         clients[ILT_CLI_CDUC].first.reg = ILT_CFG_REG(CDUC, FIRST_ILT);
1063         clients[ILT_CLI_CDUC].last.reg = ILT_CFG_REG(CDUC, LAST_ILT);
1064         clients[ILT_CLI_CDUC].p_size.reg = ILT_CFG_REG(CDUC, P_SIZE);
1065
1066         clients[ILT_CLI_QM].first.reg = ILT_CFG_REG(QM, FIRST_ILT);
1067         clients[ILT_CLI_QM].last.reg = ILT_CFG_REG(QM, LAST_ILT);
1068         clients[ILT_CLI_QM].p_size.reg = ILT_CFG_REG(QM, P_SIZE);
1069
1070         clients[ILT_CLI_TM].first.reg = ILT_CFG_REG(TM, FIRST_ILT);
1071         clients[ILT_CLI_TM].last.reg = ILT_CFG_REG(TM, LAST_ILT);
1072         clients[ILT_CLI_TM].p_size.reg = ILT_CFG_REG(TM, P_SIZE);
1073
1074         clients[ILT_CLI_SRC].first.reg = ILT_CFG_REG(SRC, FIRST_ILT);
1075         clients[ILT_CLI_SRC].last.reg = ILT_CFG_REG(SRC, LAST_ILT);
1076         clients[ILT_CLI_SRC].p_size.reg = ILT_CFG_REG(SRC, P_SIZE);
1077
1078         clients[ILT_CLI_CDUT].first.reg = ILT_CFG_REG(CDUT, FIRST_ILT);
1079         clients[ILT_CLI_CDUT].last.reg = ILT_CFG_REG(CDUT, LAST_ILT);
1080         clients[ILT_CLI_CDUT].p_size.reg = ILT_CFG_REG(CDUT, P_SIZE);
1081
1082         clients[ILT_CLI_TSDM].first.reg = ILT_CFG_REG(TSDM, FIRST_ILT);
1083         clients[ILT_CLI_TSDM].last.reg = ILT_CFG_REG(TSDM, LAST_ILT);
1084         clients[ILT_CLI_TSDM].p_size.reg = ILT_CFG_REG(TSDM, P_SIZE);
1085         /* default ILT page size for all clients is 32K */
1086         for (i = 0; i < ILT_CLI_MAX; i++)
1087                 p_mngr->clients[i].p_size.val = ILT_DEFAULT_HW_P_SIZE;
1088
1089         /* Initialize task sizes */
1090         p_mngr->task_type_size[0] = TYPE0_TASK_CXT_SIZE(p_hwfn);
1091         p_mngr->task_type_size[1] = TYPE1_TASK_CXT_SIZE(p_hwfn);
1092
1093         if (p_hwfn->cdev->p_iov_info)
1094                 p_mngr->vf_count = p_hwfn->cdev->p_iov_info->total_vfs;
1095         /* Initialize the dynamic ILT allocation mutex */
1096         mutex_init(&p_mngr->mutex);
1097
1098         /* Set the cxt mangr pointer priori to further allocations */
1099         p_hwfn->p_cxt_mngr = p_mngr;
1100
1101         return 0;
1102 }
1103
1104 int qed_cxt_tables_alloc(struct qed_hwfn *p_hwfn)
1105 {
1106         int rc;
1107
1108         /* Allocate the ILT shadow table */
1109         rc = qed_ilt_shadow_alloc(p_hwfn);
1110         if (rc)
1111                 goto tables_alloc_fail;
1112
1113         /* Allocate the T2  table */
1114         rc = qed_cxt_src_t2_alloc(p_hwfn);
1115         if (rc)
1116                 goto tables_alloc_fail;
1117
1118         /* Allocate and initialize the acquired cids bitmaps */
1119         rc = qed_cid_map_alloc(p_hwfn);
1120         if (rc)
1121                 goto tables_alloc_fail;
1122
1123         return 0;
1124
1125 tables_alloc_fail:
1126         qed_cxt_mngr_free(p_hwfn);
1127         return rc;
1128 }
1129
1130 void qed_cxt_mngr_free(struct qed_hwfn *p_hwfn)
1131 {
1132         if (!p_hwfn->p_cxt_mngr)
1133                 return;
1134
1135         qed_cid_map_free(p_hwfn);
1136         qed_cxt_src_t2_free(p_hwfn);
1137         qed_ilt_shadow_free(p_hwfn);
1138         kfree(p_hwfn->p_cxt_mngr);
1139
1140         p_hwfn->p_cxt_mngr = NULL;
1141 }
1142
1143 void qed_cxt_mngr_setup(struct qed_hwfn *p_hwfn)
1144 {
1145         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1146         int type;
1147
1148         /* Reset acquired cids */
1149         for (type = 0; type < MAX_CONN_TYPES; type++) {
1150                 u32 cid_cnt = p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
1151
1152                 if (cid_cnt == 0)
1153                         continue;
1154
1155                 memset(p_mngr->acquired[type].cid_map, 0,
1156                        DIV_ROUND_UP(cid_cnt,
1157                                     sizeof(unsigned long) * BITS_PER_BYTE) *
1158                        sizeof(unsigned long));
1159         }
1160 }
1161
1162 /* CDU Common */
1163 #define CDUC_CXT_SIZE_SHIFT \
1164         CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT
1165
1166 #define CDUC_CXT_SIZE_MASK \
1167         (CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE >> CDUC_CXT_SIZE_SHIFT)
1168
1169 #define CDUC_BLOCK_WASTE_SHIFT \
1170         CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT
1171
1172 #define CDUC_BLOCK_WASTE_MASK \
1173         (CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE >> CDUC_BLOCK_WASTE_SHIFT)
1174
1175 #define CDUC_NCIB_SHIFT \
1176         CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT
1177
1178 #define CDUC_NCIB_MASK \
1179         (CDU_REG_CID_ADDR_PARAMS_NCIB >> CDUC_NCIB_SHIFT)
1180
1181 #define CDUT_TYPE0_CXT_SIZE_SHIFT \
1182         CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT
1183
1184 #define CDUT_TYPE0_CXT_SIZE_MASK                \
1185         (CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE >> \
1186          CDUT_TYPE0_CXT_SIZE_SHIFT)
1187
1188 #define CDUT_TYPE0_BLOCK_WASTE_SHIFT \
1189         CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT
1190
1191 #define CDUT_TYPE0_BLOCK_WASTE_MASK                    \
1192         (CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE >> \
1193          CDUT_TYPE0_BLOCK_WASTE_SHIFT)
1194
1195 #define CDUT_TYPE0_NCIB_SHIFT \
1196         CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT
1197
1198 #define CDUT_TYPE0_NCIB_MASK                             \
1199         (CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK >> \
1200          CDUT_TYPE0_NCIB_SHIFT)
1201
1202 #define CDUT_TYPE1_CXT_SIZE_SHIFT \
1203         CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT
1204
1205 #define CDUT_TYPE1_CXT_SIZE_MASK                \
1206         (CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE >> \
1207          CDUT_TYPE1_CXT_SIZE_SHIFT)
1208
1209 #define CDUT_TYPE1_BLOCK_WASTE_SHIFT \
1210         CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT
1211
1212 #define CDUT_TYPE1_BLOCK_WASTE_MASK                    \
1213         (CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE >> \
1214          CDUT_TYPE1_BLOCK_WASTE_SHIFT)
1215
1216 #define CDUT_TYPE1_NCIB_SHIFT \
1217         CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT
1218
1219 #define CDUT_TYPE1_NCIB_MASK                             \
1220         (CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK >> \
1221          CDUT_TYPE1_NCIB_SHIFT)
1222
1223 static void qed_cdu_init_common(struct qed_hwfn *p_hwfn)
1224 {
1225         u32 page_sz, elems_per_page, block_waste, cxt_size, cdu_params = 0;
1226
1227         /* CDUC - connection configuration */
1228         page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1229         cxt_size = CONN_CXT_SIZE(p_hwfn);
1230         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1231         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1232
1233         SET_FIELD(cdu_params, CDUC_CXT_SIZE, cxt_size);
1234         SET_FIELD(cdu_params, CDUC_BLOCK_WASTE, block_waste);
1235         SET_FIELD(cdu_params, CDUC_NCIB, elems_per_page);
1236         STORE_RT_REG(p_hwfn, CDU_REG_CID_ADDR_PARAMS_RT_OFFSET, cdu_params);
1237
1238         /* CDUT - type-0 tasks configuration */
1239         page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT].p_size.val;
1240         cxt_size = p_hwfn->p_cxt_mngr->task_type_size[0];
1241         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1242         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1243
1244         /* cxt size and block-waste are multipes of 8 */
1245         cdu_params = 0;
1246         SET_FIELD(cdu_params, CDUT_TYPE0_CXT_SIZE, (cxt_size >> 3));
1247         SET_FIELD(cdu_params, CDUT_TYPE0_BLOCK_WASTE, (block_waste >> 3));
1248         SET_FIELD(cdu_params, CDUT_TYPE0_NCIB, elems_per_page);
1249         STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT0_PARAMS_RT_OFFSET, cdu_params);
1250
1251         /* CDUT - type-1 tasks configuration */
1252         cxt_size = p_hwfn->p_cxt_mngr->task_type_size[1];
1253         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1254         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1255
1256         /* cxt size and block-waste are multipes of 8 */
1257         cdu_params = 0;
1258         SET_FIELD(cdu_params, CDUT_TYPE1_CXT_SIZE, (cxt_size >> 3));
1259         SET_FIELD(cdu_params, CDUT_TYPE1_BLOCK_WASTE, (block_waste >> 3));
1260         SET_FIELD(cdu_params, CDUT_TYPE1_NCIB, elems_per_page);
1261         STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT1_PARAMS_RT_OFFSET, cdu_params);
1262 }
1263
1264 /* CDU PF */
1265 #define CDU_SEG_REG_TYPE_SHIFT          CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT
1266 #define CDU_SEG_REG_TYPE_MASK           0x1
1267 #define CDU_SEG_REG_OFFSET_SHIFT        0
1268 #define CDU_SEG_REG_OFFSET_MASK         CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK
1269
1270 static void qed_cdu_init_pf(struct qed_hwfn *p_hwfn)
1271 {
1272         struct qed_ilt_client_cfg *p_cli;
1273         struct qed_tid_seg *p_seg;
1274         u32 cdu_seg_params, offset;
1275         int i;
1276
1277         static const u32 rt_type_offset_arr[] = {
1278                 CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET,
1279                 CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET,
1280                 CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET,
1281                 CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET
1282         };
1283
1284         static const u32 rt_type_offset_fl_arr[] = {
1285                 CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET,
1286                 CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET,
1287                 CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET,
1288                 CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET
1289         };
1290
1291         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1292
1293         /* There are initializations only for CDUT during pf Phase */
1294         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1295                 /* Segment 0 */
1296                 p_seg = qed_cxt_tid_seg_info(p_hwfn, i);
1297                 if (!p_seg)
1298                         continue;
1299
1300                 /* Note: start_line is already adjusted for the CDU
1301                  * segment register granularity, so we just need to
1302                  * divide. Adjustment is implicit as we assume ILT
1303                  * Page size is larger than 32K!
1304                  */
1305                 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1306                           (p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line -
1307                            p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1308
1309                 cdu_seg_params = 0;
1310                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1311                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1312                 STORE_RT_REG(p_hwfn, rt_type_offset_arr[i], cdu_seg_params);
1313
1314                 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1315                           (p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)].start_line -
1316                            p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1317
1318                 cdu_seg_params = 0;
1319                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1320                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1321                 STORE_RT_REG(p_hwfn, rt_type_offset_fl_arr[i], cdu_seg_params);
1322         }
1323 }
1324
1325 void qed_qm_init_pf(struct qed_hwfn *p_hwfn)
1326 {
1327         struct qed_qm_pf_rt_init_params params;
1328         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1329         struct qed_qm_iids iids;
1330
1331         memset(&iids, 0, sizeof(iids));
1332         qed_cxt_qm_iids(p_hwfn, &iids);
1333
1334         memset(&params, 0, sizeof(params));
1335         params.port_id = p_hwfn->port_id;
1336         params.pf_id = p_hwfn->rel_pf_id;
1337         params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
1338         params.is_first_pf = p_hwfn->first_on_engine;
1339         params.num_pf_cids = iids.cids;
1340         params.num_vf_cids = iids.vf_cids;
1341         params.start_pq = qm_info->start_pq;
1342         params.num_pf_pqs = qm_info->num_pqs - qm_info->num_vf_pqs;
1343         params.num_vf_pqs = qm_info->num_vf_pqs;
1344         params.start_vport = qm_info->start_vport;
1345         params.num_vports = qm_info->num_vports;
1346         params.pf_wfq = qm_info->pf_wfq;
1347         params.pf_rl = qm_info->pf_rl;
1348         params.pq_params = qm_info->qm_pq_params;
1349         params.vport_params = qm_info->qm_vport_params;
1350
1351         qed_qm_pf_rt_init(p_hwfn, p_hwfn->p_main_ptt, &params);
1352 }
1353
1354 /* CM PF */
1355 static int qed_cm_init_pf(struct qed_hwfn *p_hwfn)
1356 {
1357         union qed_qm_pq_params pq_params;
1358         u16 pq;
1359
1360         /* XCM pure-LB queue */
1361         memset(&pq_params, 0, sizeof(pq_params));
1362         pq_params.core.tc = LB_TC;
1363         pq = qed_get_qm_pq(p_hwfn, PROTOCOLID_CORE, &pq_params);
1364         STORE_RT_REG(p_hwfn, XCM_REG_CON_PHY_Q3_RT_OFFSET, pq);
1365
1366         return 0;
1367 }
1368
1369 /* DQ PF */
1370 static void qed_dq_init_pf(struct qed_hwfn *p_hwfn)
1371 {
1372         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1373         u32 dq_pf_max_cid = 0, dq_vf_max_cid = 0;
1374
1375         dq_pf_max_cid += (p_mngr->conn_cfg[0].cid_count >> DQ_RANGE_SHIFT);
1376         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_0_RT_OFFSET, dq_pf_max_cid);
1377
1378         dq_vf_max_cid += (p_mngr->conn_cfg[0].cids_per_vf >> DQ_RANGE_SHIFT);
1379         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_0_RT_OFFSET, dq_vf_max_cid);
1380
1381         dq_pf_max_cid += (p_mngr->conn_cfg[1].cid_count >> DQ_RANGE_SHIFT);
1382         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_1_RT_OFFSET, dq_pf_max_cid);
1383
1384         dq_vf_max_cid += (p_mngr->conn_cfg[1].cids_per_vf >> DQ_RANGE_SHIFT);
1385         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_1_RT_OFFSET, dq_vf_max_cid);
1386
1387         dq_pf_max_cid += (p_mngr->conn_cfg[2].cid_count >> DQ_RANGE_SHIFT);
1388         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_2_RT_OFFSET, dq_pf_max_cid);
1389
1390         dq_vf_max_cid += (p_mngr->conn_cfg[2].cids_per_vf >> DQ_RANGE_SHIFT);
1391         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_2_RT_OFFSET, dq_vf_max_cid);
1392
1393         dq_pf_max_cid += (p_mngr->conn_cfg[3].cid_count >> DQ_RANGE_SHIFT);
1394         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_3_RT_OFFSET, dq_pf_max_cid);
1395
1396         dq_vf_max_cid += (p_mngr->conn_cfg[3].cids_per_vf >> DQ_RANGE_SHIFT);
1397         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_3_RT_OFFSET, dq_vf_max_cid);
1398
1399         dq_pf_max_cid += (p_mngr->conn_cfg[4].cid_count >> DQ_RANGE_SHIFT);
1400         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_4_RT_OFFSET, dq_pf_max_cid);
1401
1402         dq_vf_max_cid += (p_mngr->conn_cfg[4].cids_per_vf >> DQ_RANGE_SHIFT);
1403         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_4_RT_OFFSET, dq_vf_max_cid);
1404
1405         dq_pf_max_cid += (p_mngr->conn_cfg[5].cid_count >> DQ_RANGE_SHIFT);
1406         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_5_RT_OFFSET, dq_pf_max_cid);
1407
1408         dq_vf_max_cid += (p_mngr->conn_cfg[5].cids_per_vf >> DQ_RANGE_SHIFT);
1409         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_5_RT_OFFSET, dq_vf_max_cid);
1410
1411         /* Connection types 6 & 7 are not in use, yet they must be configured
1412          * as the highest possible connection. Not configuring them means the
1413          * defaults will be  used, and with a large number of cids a bug may
1414          * occur, if the defaults will be smaller than dq_pf_max_cid /
1415          * dq_vf_max_cid.
1416          */
1417         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_6_RT_OFFSET, dq_pf_max_cid);
1418         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_6_RT_OFFSET, dq_vf_max_cid);
1419
1420         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_7_RT_OFFSET, dq_pf_max_cid);
1421         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_7_RT_OFFSET, dq_vf_max_cid);
1422 }
1423
1424 static void qed_ilt_bounds_init(struct qed_hwfn *p_hwfn)
1425 {
1426         struct qed_ilt_client_cfg *ilt_clients;
1427         int i;
1428
1429         ilt_clients = p_hwfn->p_cxt_mngr->clients;
1430         for_each_ilt_valid_client(i, ilt_clients) {
1431                 STORE_RT_REG(p_hwfn,
1432                              ilt_clients[i].first.reg,
1433                              ilt_clients[i].first.val);
1434                 STORE_RT_REG(p_hwfn,
1435                              ilt_clients[i].last.reg, ilt_clients[i].last.val);
1436                 STORE_RT_REG(p_hwfn,
1437                              ilt_clients[i].p_size.reg,
1438                              ilt_clients[i].p_size.val);
1439         }
1440 }
1441
1442 static void qed_ilt_vf_bounds_init(struct qed_hwfn *p_hwfn)
1443 {
1444         struct qed_ilt_client_cfg *p_cli;
1445         u32 blk_factor;
1446
1447         /* For simplicty  we set the 'block' to be an ILT page */
1448         if (p_hwfn->cdev->p_iov_info) {
1449                 struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info;
1450
1451                 STORE_RT_REG(p_hwfn,
1452                              PSWRQ2_REG_VF_BASE_RT_OFFSET,
1453                              p_iov->first_vf_in_pf);
1454                 STORE_RT_REG(p_hwfn,
1455                              PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET,
1456                              p_iov->first_vf_in_pf + p_iov->total_vfs);
1457         }
1458
1459         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
1460         blk_factor = ilog2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1461         if (p_cli->active) {
1462                 STORE_RT_REG(p_hwfn,
1463                              PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET,
1464                              blk_factor);
1465                 STORE_RT_REG(p_hwfn,
1466                              PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1467                              p_cli->pf_total_lines);
1468                 STORE_RT_REG(p_hwfn,
1469                              PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET,
1470                              p_cli->vf_total_lines);
1471         }
1472
1473         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1474         blk_factor = ilog2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1475         if (p_cli->active) {
1476                 STORE_RT_REG(p_hwfn,
1477                              PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET,
1478                              blk_factor);
1479                 STORE_RT_REG(p_hwfn,
1480                              PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1481                              p_cli->pf_total_lines);
1482                 STORE_RT_REG(p_hwfn,
1483                              PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET,
1484                              p_cli->vf_total_lines);
1485         }
1486
1487         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TM];
1488         blk_factor = ilog2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1489         if (p_cli->active) {
1490                 STORE_RT_REG(p_hwfn,
1491                              PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET, blk_factor);
1492                 STORE_RT_REG(p_hwfn,
1493                              PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1494                              p_cli->pf_total_lines);
1495                 STORE_RT_REG(p_hwfn,
1496                              PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET,
1497                              p_cli->vf_total_lines);
1498         }
1499 }
1500
1501 /* ILT (PSWRQ2) PF */
1502 static void qed_ilt_init_pf(struct qed_hwfn *p_hwfn)
1503 {
1504         struct qed_ilt_client_cfg *clients;
1505         struct qed_cxt_mngr *p_mngr;
1506         struct qed_dma_mem *p_shdw;
1507         u32 line, rt_offst, i;
1508
1509         qed_ilt_bounds_init(p_hwfn);
1510         qed_ilt_vf_bounds_init(p_hwfn);
1511
1512         p_mngr = p_hwfn->p_cxt_mngr;
1513         p_shdw = p_mngr->ilt_shadow;
1514         clients = p_hwfn->p_cxt_mngr->clients;
1515
1516         for_each_ilt_valid_client(i, clients) {
1517                 /** Client's 1st val and RT array are absolute, ILT shadows'
1518                  *  lines are relative.
1519                  */
1520                 line = clients[i].first.val - p_mngr->pf_start_line;
1521                 rt_offst = PSWRQ2_REG_ILT_MEMORY_RT_OFFSET +
1522                            clients[i].first.val * ILT_ENTRY_IN_REGS;
1523
1524                 for (; line <= clients[i].last.val - p_mngr->pf_start_line;
1525                      line++, rt_offst += ILT_ENTRY_IN_REGS) {
1526                         u64 ilt_hw_entry = 0;
1527
1528                         /** p_virt could be NULL incase of dynamic
1529                          *  allocation
1530                          */
1531                         if (p_shdw[line].p_virt) {
1532                                 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
1533                                 SET_FIELD(ilt_hw_entry, ILT_ENTRY_PHY_ADDR,
1534                                           (p_shdw[line].p_phys >> 12));
1535
1536                                 DP_VERBOSE(p_hwfn, QED_MSG_ILT,
1537                                            "Setting RT[0x%08x] from ILT[0x%08x] [Client is %d] to Physical addr: 0x%llx\n",
1538                                            rt_offst, line, i,
1539                                            (u64)(p_shdw[line].p_phys >> 12));
1540                         }
1541
1542                         STORE_RT_REG_AGG(p_hwfn, rt_offst, ilt_hw_entry);
1543                 }
1544         }
1545 }
1546
1547 /* SRC (Searcher) PF */
1548 static void qed_src_init_pf(struct qed_hwfn *p_hwfn)
1549 {
1550         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1551         u32 rounded_conn_num, conn_num, conn_max;
1552         struct qed_src_iids src_iids;
1553
1554         memset(&src_iids, 0, sizeof(src_iids));
1555         qed_cxt_src_iids(p_mngr, &src_iids);
1556         conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
1557         if (!conn_num)
1558                 return;
1559
1560         conn_max = max_t(u32, conn_num, SRC_MIN_NUM_ELEMS);
1561         rounded_conn_num = roundup_pow_of_two(conn_max);
1562
1563         STORE_RT_REG(p_hwfn, SRC_REG_COUNTFREE_RT_OFFSET, conn_num);
1564         STORE_RT_REG(p_hwfn, SRC_REG_NUMBER_HASH_BITS_RT_OFFSET,
1565                      ilog2(rounded_conn_num));
1566
1567         STORE_RT_REG_AGG(p_hwfn, SRC_REG_FIRSTFREE_RT_OFFSET,
1568                          p_hwfn->p_cxt_mngr->first_free);
1569         STORE_RT_REG_AGG(p_hwfn, SRC_REG_LASTFREE_RT_OFFSET,
1570                          p_hwfn->p_cxt_mngr->last_free);
1571 }
1572
1573 /* Timers PF */
1574 #define TM_CFG_NUM_IDS_SHIFT            0
1575 #define TM_CFG_NUM_IDS_MASK             0xFFFFULL
1576 #define TM_CFG_PRE_SCAN_OFFSET_SHIFT    16
1577 #define TM_CFG_PRE_SCAN_OFFSET_MASK     0x1FFULL
1578 #define TM_CFG_PARENT_PF_SHIFT          25
1579 #define TM_CFG_PARENT_PF_MASK           0x7ULL
1580
1581 #define TM_CFG_CID_PRE_SCAN_ROWS_SHIFT  30
1582 #define TM_CFG_CID_PRE_SCAN_ROWS_MASK   0x1FFULL
1583
1584 #define TM_CFG_TID_OFFSET_SHIFT         30
1585 #define TM_CFG_TID_OFFSET_MASK          0x7FFFFULL
1586 #define TM_CFG_TID_PRE_SCAN_ROWS_SHIFT  49
1587 #define TM_CFG_TID_PRE_SCAN_ROWS_MASK   0x1FFULL
1588
1589 static void qed_tm_init_pf(struct qed_hwfn *p_hwfn)
1590 {
1591         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1592         u32 active_seg_mask = 0, tm_offset, rt_reg;
1593         struct qed_tm_iids tm_iids;
1594         u64 cfg_word;
1595         u8 i;
1596
1597         memset(&tm_iids, 0, sizeof(tm_iids));
1598         qed_cxt_tm_iids(p_mngr, &tm_iids);
1599
1600         /* @@@TBD No pre-scan for now */
1601
1602         /* Note: We assume consecutive VFs for a PF */
1603         for (i = 0; i < p_mngr->vf_count; i++) {
1604                 cfg_word = 0;
1605                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_cids);
1606                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1607                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1608                 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0);
1609                 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1610                     (sizeof(cfg_word) / sizeof(u32)) *
1611                     (p_hwfn->cdev->p_iov_info->first_vf_in_pf + i);
1612                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1613         }
1614
1615         cfg_word = 0;
1616         SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_cids);
1617         SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1618         SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0);       /* n/a for PF */
1619         SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0);       /* scan all   */
1620
1621         rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1622             (sizeof(cfg_word) / sizeof(u32)) *
1623             (NUM_OF_VFS(p_hwfn->cdev) + p_hwfn->rel_pf_id);
1624         STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1625
1626         /* enale scan */
1627         STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_CONN_RT_OFFSET,
1628                      tm_iids.pf_cids ? 0x1 : 0x0);
1629
1630         /* @@@TBD how to enable the scan for the VFs */
1631
1632         tm_offset = tm_iids.per_vf_cids;
1633
1634         /* Note: We assume consecutive VFs for a PF */
1635         for (i = 0; i < p_mngr->vf_count; i++) {
1636                 cfg_word = 0;
1637                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_tids);
1638                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1639                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1640                 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1641                 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64) 0);
1642
1643                 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1644                     (sizeof(cfg_word) / sizeof(u32)) *
1645                     (p_hwfn->cdev->p_iov_info->first_vf_in_pf + i);
1646
1647                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1648         }
1649
1650         tm_offset = tm_iids.pf_cids;
1651         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1652                 cfg_word = 0;
1653                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_tids[i]);
1654                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1655                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0);
1656                 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1657                 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64) 0);
1658
1659                 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1660                     (sizeof(cfg_word) / sizeof(u32)) *
1661                     (NUM_OF_VFS(p_hwfn->cdev) +
1662                      p_hwfn->rel_pf_id * NUM_TASK_PF_SEGMENTS + i);
1663
1664                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1665                 active_seg_mask |= (tm_iids.pf_tids[i] ? BIT(i) : 0);
1666
1667                 tm_offset += tm_iids.pf_tids[i];
1668         }
1669
1670         if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE)
1671                 active_seg_mask = 0;
1672
1673         STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_TASK_RT_OFFSET, active_seg_mask);
1674
1675         /* @@@TBD how to enable the scan for the VFs */
1676 }
1677
1678 void qed_cxt_hw_init_common(struct qed_hwfn *p_hwfn)
1679 {
1680         qed_cdu_init_common(p_hwfn);
1681 }
1682
1683 void qed_cxt_hw_init_pf(struct qed_hwfn *p_hwfn)
1684 {
1685         qed_qm_init_pf(p_hwfn);
1686         qed_cm_init_pf(p_hwfn);
1687         qed_dq_init_pf(p_hwfn);
1688         qed_cdu_init_pf(p_hwfn);
1689         qed_ilt_init_pf(p_hwfn);
1690         qed_src_init_pf(p_hwfn);
1691         qed_tm_init_pf(p_hwfn);
1692 }
1693
1694 int qed_cxt_acquire_cid(struct qed_hwfn *p_hwfn,
1695                         enum protocol_type type, u32 *p_cid)
1696 {
1697         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1698         u32 rel_cid;
1699
1700         if (type >= MAX_CONN_TYPES || !p_mngr->acquired[type].cid_map) {
1701                 DP_NOTICE(p_hwfn, "Invalid protocol type %d", type);
1702                 return -EINVAL;
1703         }
1704
1705         rel_cid = find_first_zero_bit(p_mngr->acquired[type].cid_map,
1706                                       p_mngr->acquired[type].max_count);
1707
1708         if (rel_cid >= p_mngr->acquired[type].max_count) {
1709                 DP_NOTICE(p_hwfn, "no CID available for protocol %d\n", type);
1710                 return -EINVAL;
1711         }
1712
1713         __set_bit(rel_cid, p_mngr->acquired[type].cid_map);
1714
1715         *p_cid = rel_cid + p_mngr->acquired[type].start_cid;
1716
1717         return 0;
1718 }
1719
1720 static bool qed_cxt_test_cid_acquired(struct qed_hwfn *p_hwfn,
1721                                       u32 cid, enum protocol_type *p_type)
1722 {
1723         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1724         struct qed_cid_acquired_map *p_map;
1725         enum protocol_type p;
1726         u32 rel_cid;
1727
1728         /* Iterate over protocols and find matching cid range */
1729         for (p = 0; p < MAX_CONN_TYPES; p++) {
1730                 p_map = &p_mngr->acquired[p];
1731
1732                 if (!p_map->cid_map)
1733                         continue;
1734                 if (cid >= p_map->start_cid &&
1735                     cid < p_map->start_cid + p_map->max_count)
1736                         break;
1737         }
1738         *p_type = p;
1739
1740         if (p == MAX_CONN_TYPES) {
1741                 DP_NOTICE(p_hwfn, "Invalid CID %d", cid);
1742                 return false;
1743         }
1744
1745         rel_cid = cid - p_map->start_cid;
1746         if (!test_bit(rel_cid, p_map->cid_map)) {
1747                 DP_NOTICE(p_hwfn, "CID %d not acquired", cid);
1748                 return false;
1749         }
1750         return true;
1751 }
1752
1753 void qed_cxt_release_cid(struct qed_hwfn *p_hwfn, u32 cid)
1754 {
1755         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1756         enum protocol_type type;
1757         bool b_acquired;
1758         u32 rel_cid;
1759
1760         /* Test acquired and find matching per-protocol map */
1761         b_acquired = qed_cxt_test_cid_acquired(p_hwfn, cid, &type);
1762
1763         if (!b_acquired)
1764                 return;
1765
1766         rel_cid = cid - p_mngr->acquired[type].start_cid;
1767         __clear_bit(rel_cid, p_mngr->acquired[type].cid_map);
1768 }
1769
1770 int qed_cxt_get_cid_info(struct qed_hwfn *p_hwfn, struct qed_cxt_info *p_info)
1771 {
1772         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1773         u32 conn_cxt_size, hw_p_size, cxts_per_p, line;
1774         enum protocol_type type;
1775         bool b_acquired;
1776
1777         /* Test acquired and find matching per-protocol map */
1778         b_acquired = qed_cxt_test_cid_acquired(p_hwfn, p_info->iid, &type);
1779
1780         if (!b_acquired)
1781                 return -EINVAL;
1782
1783         /* set the protocl type */
1784         p_info->type = type;
1785
1786         /* compute context virtual pointer */
1787         hw_p_size = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1788
1789         conn_cxt_size = CONN_CXT_SIZE(p_hwfn);
1790         cxts_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / conn_cxt_size;
1791         line = p_info->iid / cxts_per_p;
1792
1793         /* Make sure context is allocated (dynamic allocation) */
1794         if (!p_mngr->ilt_shadow[line].p_virt)
1795                 return -EINVAL;
1796
1797         p_info->p_cxt = p_mngr->ilt_shadow[line].p_virt +
1798                         p_info->iid % cxts_per_p * conn_cxt_size;
1799
1800         DP_VERBOSE(p_hwfn, (QED_MSG_ILT | QED_MSG_CXT),
1801                    "Accessing ILT shadow[%d]: CXT pointer is at %p (for iid %d)\n",
1802                    p_info->iid / cxts_per_p, p_info->p_cxt, p_info->iid);
1803
1804         return 0;
1805 }
1806
1807 void qed_rdma_set_pf_params(struct qed_hwfn *p_hwfn,
1808                             struct qed_rdma_pf_params *p_params)
1809 {
1810         u32 num_cons, num_tasks, num_qps, num_mrs, num_srqs;
1811         enum protocol_type proto;
1812
1813         num_mrs = min_t(u32, RDMA_MAX_TIDS, p_params->num_mrs);
1814         num_tasks = num_mrs;    /* each mr uses a single task id */
1815         num_srqs = min_t(u32, 32 * 1024, p_params->num_srqs);
1816
1817         switch (p_hwfn->hw_info.personality) {
1818         case QED_PCI_ETH_ROCE:
1819                 num_qps = min_t(u32, ROCE_MAX_QPS, p_params->num_qps);
1820                 num_cons = num_qps * 2; /* each QP requires two connections */
1821                 proto = PROTOCOLID_ROCE;
1822                 break;
1823         default:
1824                 return;
1825         }
1826
1827         if (num_cons && num_tasks) {
1828                 qed_cxt_set_proto_cid_count(p_hwfn, proto, num_cons, 0);
1829
1830                 /* Deliberatly passing ROCE for tasks id. This is because
1831                  * iWARP / RoCE share the task id.
1832                  */
1833                 qed_cxt_set_proto_tid_count(p_hwfn, PROTOCOLID_ROCE,
1834                                             QED_CXT_ROCE_TID_SEG, 1,
1835                                             num_tasks, false);
1836                 qed_cxt_set_srq_count(p_hwfn, num_srqs);
1837         } else {
1838                 DP_INFO(p_hwfn->cdev,
1839                         "RDMA personality used without setting params!\n");
1840         }
1841 }
1842
1843 int qed_cxt_set_pf_params(struct qed_hwfn *p_hwfn)
1844 {
1845         /* Set the number of required CORE connections */
1846         u32 core_cids = 1; /* SPQ */
1847
1848         if (p_hwfn->using_ll2)
1849                 core_cids += 4;
1850         qed_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_CORE, core_cids, 0);
1851
1852         switch (p_hwfn->hw_info.personality) {
1853         case QED_PCI_ETH_ROCE:
1854         {
1855                 qed_rdma_set_pf_params(p_hwfn,
1856                                        &p_hwfn->
1857                                        pf_params.rdma_pf_params);
1858                 /* no need for break since RoCE coexist with Ethernet */
1859         }
1860         case QED_PCI_ETH:
1861         {
1862                 struct qed_eth_pf_params *p_params =
1863                     &p_hwfn->pf_params.eth_pf_params;
1864
1865                 qed_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
1866                                             p_params->num_cons, 1);
1867                 break;
1868         }
1869         case QED_PCI_ISCSI:
1870         {
1871                 struct qed_iscsi_pf_params *p_params;
1872
1873                 p_params = &p_hwfn->pf_params.iscsi_pf_params;
1874
1875                 if (p_params->num_cons && p_params->num_tasks) {
1876                         qed_cxt_set_proto_cid_count(p_hwfn,
1877                                                     PROTOCOLID_ISCSI,
1878                                                     p_params->num_cons,
1879                                                     0);
1880
1881                         qed_cxt_set_proto_tid_count(p_hwfn,
1882                                                     PROTOCOLID_ISCSI,
1883                                                     QED_CXT_ISCSI_TID_SEG,
1884                                                     0,
1885                                                     p_params->num_tasks,
1886                                                     true);
1887                 } else {
1888                         DP_INFO(p_hwfn->cdev,
1889                                 "Iscsi personality used without setting params!\n");
1890                 }
1891                 break;
1892         }
1893         default:
1894                 return -EINVAL;
1895         }
1896
1897         return 0;
1898 }
1899
1900 int qed_cxt_get_tid_mem_info(struct qed_hwfn *p_hwfn,
1901                              struct qed_tid_mem *p_info)
1902 {
1903         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1904         u32 proto, seg, total_lines, i, shadow_line;
1905         struct qed_ilt_client_cfg *p_cli;
1906         struct qed_ilt_cli_blk *p_fl_seg;
1907         struct qed_tid_seg *p_seg_info;
1908
1909         /* Verify the personality */
1910         switch (p_hwfn->hw_info.personality) {
1911         case QED_PCI_ISCSI:
1912                 proto = PROTOCOLID_ISCSI;
1913                 seg = QED_CXT_ISCSI_TID_SEG;
1914                 break;
1915         default:
1916                 return -EINVAL;
1917         }
1918
1919         p_cli = &p_mngr->clients[ILT_CLI_CDUT];
1920         if (!p_cli->active)
1921                 return -EINVAL;
1922
1923         p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg];
1924         if (!p_seg_info->has_fl_mem)
1925                 return -EINVAL;
1926
1927         p_fl_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)];
1928         total_lines = DIV_ROUND_UP(p_fl_seg->total_size,
1929                                    p_fl_seg->real_size_in_page);
1930
1931         for (i = 0; i < total_lines; i++) {
1932                 shadow_line = i + p_fl_seg->start_line -
1933                     p_hwfn->p_cxt_mngr->pf_start_line;
1934                 p_info->blocks[i] = p_mngr->ilt_shadow[shadow_line].p_virt;
1935         }
1936         p_info->waste = ILT_PAGE_IN_BYTES(p_cli->p_size.val) -
1937             p_fl_seg->real_size_in_page;
1938         p_info->tid_size = p_mngr->task_type_size[p_seg_info->type];
1939         p_info->num_tids_per_block = p_fl_seg->real_size_in_page /
1940             p_info->tid_size;
1941
1942         return 0;
1943 }
1944
1945 /* This function is very RoCE oriented, if another protocol in the future
1946  * will want this feature we'll need to modify the function to be more generic
1947  */
1948 int
1949 qed_cxt_dynamic_ilt_alloc(struct qed_hwfn *p_hwfn,
1950                           enum qed_cxt_elem_type elem_type, u32 iid)
1951 {
1952         u32 reg_offset, shadow_line, elem_size, hw_p_size, elems_per_p, line;
1953         struct qed_ilt_client_cfg *p_cli;
1954         struct qed_ilt_cli_blk *p_blk;
1955         struct qed_ptt *p_ptt;
1956         dma_addr_t p_phys;
1957         u64 ilt_hw_entry;
1958         void *p_virt;
1959         int rc = 0;
1960
1961         switch (elem_type) {
1962         case QED_ELEM_CXT:
1963                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
1964                 elem_size = CONN_CXT_SIZE(p_hwfn);
1965                 p_blk = &p_cli->pf_blks[CDUC_BLK];
1966                 break;
1967         case QED_ELEM_SRQ:
1968                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
1969                 elem_size = SRQ_CXT_SIZE;
1970                 p_blk = &p_cli->pf_blks[SRQ_BLK];
1971                 break;
1972         case QED_ELEM_TASK:
1973                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1974                 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
1975                 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(QED_CXT_ROCE_TID_SEG)];
1976                 break;
1977         default:
1978                 DP_NOTICE(p_hwfn, "-EINVALID elem type = %d", elem_type);
1979                 return -EINVAL;
1980         }
1981
1982         /* Calculate line in ilt */
1983         hw_p_size = p_cli->p_size.val;
1984         elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
1985         line = p_blk->start_line + (iid / elems_per_p);
1986         shadow_line = line - p_hwfn->p_cxt_mngr->pf_start_line;
1987
1988         /* If line is already allocated, do nothing, otherwise allocate it and
1989          * write it to the PSWRQ2 registers.
1990          * This section can be run in parallel from different contexts and thus
1991          * a mutex protection is needed.
1992          */
1993
1994         mutex_lock(&p_hwfn->p_cxt_mngr->mutex);
1995
1996         if (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt)
1997                 goto out0;
1998
1999         p_ptt = qed_ptt_acquire(p_hwfn);
2000         if (!p_ptt) {
2001                 DP_NOTICE(p_hwfn,
2002                           "QED_TIME_OUT on ptt acquire - dynamic allocation");
2003                 rc = -EBUSY;
2004                 goto out0;
2005         }
2006
2007         p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
2008                                     p_blk->real_size_in_page,
2009                                     &p_phys, GFP_KERNEL);
2010         if (!p_virt) {
2011                 rc = -ENOMEM;
2012                 goto out1;
2013         }
2014         memset(p_virt, 0, p_blk->real_size_in_page);
2015
2016         /* configuration of refTagMask to 0xF is required for RoCE DIF MR only,
2017          * to compensate for a HW bug, but it is configured even if DIF is not
2018          * enabled. This is harmless and allows us to avoid a dedicated API. We
2019          * configure the field for all of the contexts on the newly allocated
2020          * page.
2021          */
2022         if (elem_type == QED_ELEM_TASK) {
2023                 u32 elem_i;
2024                 u8 *elem_start = (u8 *)p_virt;
2025                 union type1_task_context *elem;
2026
2027                 for (elem_i = 0; elem_i < elems_per_p; elem_i++) {
2028                         elem = (union type1_task_context *)elem_start;
2029                         SET_FIELD(elem->roce_ctx.tdif_context.flags1,
2030                                   TDIF_TASK_CONTEXT_REFTAGMASK, 0xf);
2031                         elem_start += TYPE1_TASK_CXT_SIZE(p_hwfn);
2032                 }
2033         }
2034
2035         p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt = p_virt;
2036         p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys = p_phys;
2037         p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].size =
2038             p_blk->real_size_in_page;
2039
2040         /* compute absolute offset */
2041         reg_offset = PSWRQ2_REG_ILT_MEMORY +
2042             (line * ILT_REG_SIZE_IN_BYTES * ILT_ENTRY_IN_REGS);
2043
2044         ilt_hw_entry = 0;
2045         SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
2046         SET_FIELD(ilt_hw_entry,
2047                   ILT_ENTRY_PHY_ADDR,
2048                   (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys >> 12));
2049
2050         /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a wide-bus */
2051         qed_dmae_host2grc(p_hwfn, p_ptt, (u64) (uintptr_t)&ilt_hw_entry,
2052                           reg_offset, sizeof(ilt_hw_entry) / sizeof(u32), 0);
2053
2054         if (elem_type == QED_ELEM_CXT) {
2055                 u32 last_cid_allocated = (1 + (iid / elems_per_p)) *
2056                     elems_per_p;
2057
2058                 /* Update the relevant register in the parser */
2059                 qed_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF,
2060                        last_cid_allocated - 1);
2061
2062                 if (!p_hwfn->b_rdma_enabled_in_prs) {
2063                         /* Enable RoCE search */
2064                         qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 1);
2065                         p_hwfn->b_rdma_enabled_in_prs = true;
2066                 }
2067         }
2068
2069 out1:
2070         qed_ptt_release(p_hwfn, p_ptt);
2071 out0:
2072         mutex_unlock(&p_hwfn->p_cxt_mngr->mutex);
2073
2074         return rc;
2075 }
2076
2077 /* This function is very RoCE oriented, if another protocol in the future
2078  * will want this feature we'll need to modify the function to be more generic
2079  */
2080 static int
2081 qed_cxt_free_ilt_range(struct qed_hwfn *p_hwfn,
2082                        enum qed_cxt_elem_type elem_type,
2083                        u32 start_iid, u32 count)
2084 {
2085         u32 start_line, end_line, shadow_start_line, shadow_end_line;
2086         u32 reg_offset, elem_size, hw_p_size, elems_per_p;
2087         struct qed_ilt_client_cfg *p_cli;
2088         struct qed_ilt_cli_blk *p_blk;
2089         u32 end_iid = start_iid + count;
2090         struct qed_ptt *p_ptt;
2091         u64 ilt_hw_entry = 0;
2092         u32 i;
2093
2094         switch (elem_type) {
2095         case QED_ELEM_CXT:
2096                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
2097                 elem_size = CONN_CXT_SIZE(p_hwfn);
2098                 p_blk = &p_cli->pf_blks[CDUC_BLK];
2099                 break;
2100         case QED_ELEM_SRQ:
2101                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
2102                 elem_size = SRQ_CXT_SIZE;
2103                 p_blk = &p_cli->pf_blks[SRQ_BLK];
2104                 break;
2105         case QED_ELEM_TASK:
2106                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
2107                 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
2108                 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(QED_CXT_ROCE_TID_SEG)];
2109                 break;
2110         default:
2111                 DP_NOTICE(p_hwfn, "-EINVALID elem type = %d", elem_type);
2112                 return -EINVAL;
2113         }
2114
2115         /* Calculate line in ilt */
2116         hw_p_size = p_cli->p_size.val;
2117         elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
2118         start_line = p_blk->start_line + (start_iid / elems_per_p);
2119         end_line = p_blk->start_line + (end_iid / elems_per_p);
2120         if (((end_iid + 1) / elems_per_p) != (end_iid / elems_per_p))
2121                 end_line--;
2122
2123         shadow_start_line = start_line - p_hwfn->p_cxt_mngr->pf_start_line;
2124         shadow_end_line = end_line - p_hwfn->p_cxt_mngr->pf_start_line;
2125
2126         p_ptt = qed_ptt_acquire(p_hwfn);
2127         if (!p_ptt) {
2128                 DP_NOTICE(p_hwfn,
2129                           "QED_TIME_OUT on ptt acquire - dynamic allocation");
2130                 return -EBUSY;
2131         }
2132
2133         for (i = shadow_start_line; i < shadow_end_line; i++) {
2134                 if (!p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt)
2135                         continue;
2136
2137                 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
2138                                   p_hwfn->p_cxt_mngr->ilt_shadow[i].size,
2139                                   p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt,
2140                                   p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys);
2141
2142                 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt = NULL;
2143                 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys = 0;
2144                 p_hwfn->p_cxt_mngr->ilt_shadow[i].size = 0;
2145
2146                 /* compute absolute offset */
2147                 reg_offset = PSWRQ2_REG_ILT_MEMORY +
2148                     ((start_line++) * ILT_REG_SIZE_IN_BYTES *
2149                      ILT_ENTRY_IN_REGS);
2150
2151                 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a
2152                  * wide-bus.
2153                  */
2154                 qed_dmae_host2grc(p_hwfn, p_ptt,
2155                                   (u64) (uintptr_t) &ilt_hw_entry,
2156                                   reg_offset,
2157                                   sizeof(ilt_hw_entry) / sizeof(u32),
2158                                   0);
2159         }
2160
2161         qed_ptt_release(p_hwfn, p_ptt);
2162
2163         return 0;
2164 }
2165
2166 int qed_cxt_free_proto_ilt(struct qed_hwfn *p_hwfn, enum protocol_type proto)
2167 {
2168         int rc;
2169         u32 cid;
2170
2171         /* Free Connection CXT */
2172         rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_CXT,
2173                                     qed_cxt_get_proto_cid_start(p_hwfn,
2174                                                                 proto),
2175                                     qed_cxt_get_proto_cid_count(p_hwfn,
2176                                                                 proto, &cid));
2177
2178         if (rc)
2179                 return rc;
2180
2181         /* Free Task CXT */
2182         rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_TASK, 0,
2183                                     qed_cxt_get_proto_tid_count(p_hwfn, proto));
2184         if (rc)
2185                 return rc;
2186
2187         /* Free TSDM CXT */
2188         rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_SRQ, 0,
2189                                     qed_cxt_get_srq_count(p_hwfn));
2190
2191         return rc;
2192 }
2193
2194 int qed_cxt_get_task_ctx(struct qed_hwfn *p_hwfn,
2195                          u32 tid, u8 ctx_type, void **pp_task_ctx)
2196 {
2197         struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
2198         struct qed_ilt_client_cfg *p_cli;
2199         struct qed_ilt_cli_blk *p_seg;
2200         struct qed_tid_seg *p_seg_info;
2201         u32 proto, seg;
2202         u32 total_lines;
2203         u32 tid_size, ilt_idx;
2204         u32 num_tids_per_block;
2205
2206         /* Verify the personality */
2207         switch (p_hwfn->hw_info.personality) {
2208         case QED_PCI_ISCSI:
2209                 proto = PROTOCOLID_ISCSI;
2210                 seg = QED_CXT_ISCSI_TID_SEG;
2211                 break;
2212         default:
2213                 return -EINVAL;
2214         }
2215
2216         p_cli = &p_mngr->clients[ILT_CLI_CDUT];
2217         if (!p_cli->active)
2218                 return -EINVAL;
2219
2220         p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg];
2221
2222         if (ctx_type == QED_CTX_WORKING_MEM) {
2223                 p_seg = &p_cli->pf_blks[CDUT_SEG_BLK(seg)];
2224         } else if (ctx_type == QED_CTX_FL_MEM) {
2225                 if (!p_seg_info->has_fl_mem)
2226                         return -EINVAL;
2227                 p_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)];
2228         } else {
2229                 return -EINVAL;
2230         }
2231         total_lines = DIV_ROUND_UP(p_seg->total_size, p_seg->real_size_in_page);
2232         tid_size = p_mngr->task_type_size[p_seg_info->type];
2233         num_tids_per_block = p_seg->real_size_in_page / tid_size;
2234
2235         if (total_lines < tid / num_tids_per_block)
2236                 return -EINVAL;
2237
2238         ilt_idx = tid / num_tids_per_block + p_seg->start_line -
2239                   p_mngr->pf_start_line;
2240         *pp_task_ctx = (u8 *)p_mngr->ilt_shadow[ilt_idx].p_virt +
2241                        (tid % num_tids_per_block) * tid_size;
2242
2243         return 0;
2244 }