drivers/net/ethernet/qlogic/qed/qed_hsi.h

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015 QLogic Corporation
   3  *
   4  * This software is available under the terms of the GNU General Public License
   5  * (GPL) Version 2, available from the file COPYING in the main directory of
   6  * this source tree.
   7  */
   8
   9 #ifndef _QED_HSI_H
  10 #define _QED_HSI_H
  11
  12 #include <linux/types.h>
  13 #include <linux/io.h>
  14 #include <linux/bitops.h>
  15 #include <linux/delay.h>
  16 #include <linux/kernel.h>
  17 #include <linux/list.h>
  18 #include <linux/slab.h>
  19 #include <linux/qed/common_hsi.h>
  20 #include <linux/qed/eth_common.h>
  21
  22 struct qed_hwfn;
  23 struct qed_ptt;
  24 /********************************/
  25 /* Add include to common target */
  26 /********************************/
  27
  28 /* opcodes for the event ring */
  29 enum common_event_opcode {
  30         COMMON_EVENT_PF_START,
  31         COMMON_EVENT_PF_STOP,
  32         COMMON_EVENT_VF_START,
  33         COMMON_EVENT_VF_STOP,
  34         COMMON_EVENT_VF_PF_CHANNEL,
  35         COMMON_EVENT_RESERVED4,
  36         COMMON_EVENT_RESERVED5,
  37         COMMON_EVENT_RESERVED6,
  38         COMMON_EVENT_EMPTY,
  39         MAX_COMMON_EVENT_OPCODE
  40 };
  41
  42 /* Common Ramrod Command IDs */
  43 enum common_ramrod_cmd_id {
  44         COMMON_RAMROD_UNUSED,
  45         COMMON_RAMROD_PF_START /* PF Function Start Ramrod */,
  46         COMMON_RAMROD_PF_STOP /* PF Function Stop Ramrod */,
  47         COMMON_RAMROD_VF_START,
  48         COMMON_RAMROD_VF_STOP,
  49         COMMON_RAMROD_PF_UPDATE,
  50         COMMON_RAMROD_EMPTY,
  51         MAX_COMMON_RAMROD_CMD_ID
  52 };
  53
  54 /* The core storm context for the Ystorm */
  55 struct ystorm_core_conn_st_ctx {
  56         __le32 reserved[4];
  57 };
  58
  59 /* The core storm context for the Pstorm */
  60 struct pstorm_core_conn_st_ctx {
  61         __le32 reserved[4];
  62 };
  63
  64 /* Core Slowpath Connection storm context of Xstorm */
  65 struct xstorm_core_conn_st_ctx {
  66         __le32          spq_base_lo /* SPQ Ring Base Address low dword */;
  67         __le32          spq_base_hi /* SPQ Ring Base Address high dword */;
  68         struct regpair  consolid_base_addr;
  69         __le16          spq_cons /* SPQ Ring Consumer */;
  70         __le16          consolid_cons /* Consolidation Ring Consumer */;
  71         __le32          reserved0[55] /* Pad to 15 cycles */;
  72 };
  73
  74 struct xstorm_core_conn_ag_ctx {
  75         u8      reserved0 /* cdu_validation */;
  76         u8      core_state /* state */;
  77         u8      flags0;
  78 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK         0x1
  79 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT        0
  80 #define XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK            0x1
  81 #define XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT           1
  82 #define XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK            0x1
  83 #define XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT           2
  84 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK         0x1
  85 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT        3
  86 #define XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK            0x1
  87 #define XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT           4
  88 #define XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK            0x1
  89 #define XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT           5
  90 #define XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK            0x1   /* bit6 */
  91 #define XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT           6
  92 #define XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK            0x1   /* bit7 */
  93 #define XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT           7
  94         u8 flags1;
  95 #define XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK            0x1   /* bit8 */
  96 #define XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT           0
  97 #define XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK            0x1   /* bit9 */
  98 #define XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT           1
  99 #define XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK            0x1   /* bit10 */
 100 #define XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT           2
 101 #define XSTORM_CORE_CONN_AG_CTX_BIT11_MASK                0x1   /* bit11 */
 102 #define XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT               3
 103 #define XSTORM_CORE_CONN_AG_CTX_BIT12_MASK                0x1   /* bit12 */
 104 #define XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT               4
 105 #define XSTORM_CORE_CONN_AG_CTX_BIT13_MASK                0x1   /* bit13 */
 106 #define XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT               5
 107 #define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK       0x1   /* bit14 */
 108 #define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT      6
 109 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK         0x1   /* bit15 */
 110 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT        7
 111         u8 flags2;
 112 #define XSTORM_CORE_CONN_AG_CTX_CF0_MASK                  0x3   /* timer0cf */
 113 #define XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT                 0
 114 #define XSTORM_CORE_CONN_AG_CTX_CF1_MASK                  0x3   /* timer1cf */
 115 #define XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT                 2
 116 #define XSTORM_CORE_CONN_AG_CTX_CF2_MASK                  0x3   /* timer2cf */
 117 #define XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT                 4
 118 #define XSTORM_CORE_CONN_AG_CTX_CF3_MASK                  0x3
 119 #define XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT                 6
 120         u8 flags3;
 121 #define XSTORM_CORE_CONN_AG_CTX_CF4_MASK                  0x3   /* cf4 */
 122 #define XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT                 0
 123 #define XSTORM_CORE_CONN_AG_CTX_CF5_MASK                  0x3   /* cf5 */
 124 #define XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT                 2
 125 #define XSTORM_CORE_CONN_AG_CTX_CF6_MASK                  0x3   /* cf6 */
 126 #define XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT                 4
 127 #define XSTORM_CORE_CONN_AG_CTX_CF7_MASK                  0x3   /* cf7 */
 128 #define XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT                 6
 129         u8 flags4;
 130 #define XSTORM_CORE_CONN_AG_CTX_CF8_MASK                  0x3   /* cf8 */
 131 #define XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT                 0
 132 #define XSTORM_CORE_CONN_AG_CTX_CF9_MASK                  0x3   /* cf9 */
 133 #define XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT                 2
 134 #define XSTORM_CORE_CONN_AG_CTX_CF10_MASK                 0x3   /* cf10 */
 135 #define XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT                4
 136 #define XSTORM_CORE_CONN_AG_CTX_CF11_MASK                 0x3   /* cf11 */
 137 #define XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT                6
 138         u8 flags5;
 139 #define XSTORM_CORE_CONN_AG_CTX_CF12_MASK                 0x3   /* cf12 */
 140 #define XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT                0
 141 #define XSTORM_CORE_CONN_AG_CTX_CF13_MASK                 0x3   /* cf13 */
 142 #define XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT                2
 143 #define XSTORM_CORE_CONN_AG_CTX_CF14_MASK                 0x3   /* cf14 */
 144 #define XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT                4
 145 #define XSTORM_CORE_CONN_AG_CTX_CF15_MASK                 0x3   /* cf15 */
 146 #define XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT                6
 147         u8 flags6;
 148 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK     0x3   /* cf16 */
 149 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT    0
 150 #define XSTORM_CORE_CONN_AG_CTX_CF17_MASK                 0x3
 151 #define XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT                2
 152 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK                0x3   /* cf18 */
 153 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT               4
 154 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK         0x3   /* cf19 */
 155 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT        6
 156         u8 flags7;
 157 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK             0x3   /* cf20 */
 158 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT            0
 159 #define XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK           0x3   /* cf21 */
 160 #define XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT          2
 161 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK            0x3   /* cf22 */
 162 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT           4
 163 #define XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK                0x1   /* cf0en */
 164 #define XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT               6
 165 #define XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK                0x1   /* cf1en */
 166 #define XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT               7
 167         u8 flags8;
 168 #define XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK                0x1   /* cf2en */
 169 #define XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT               0
 170 #define XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK                0x1   /* cf3en */
 171 #define XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT               1
 172 #define XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK                0x1   /* cf4en */
 173 #define XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT               2
 174 #define XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK                0x1   /* cf5en */
 175 #define XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT               3
 176 #define XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK                0x1   /* cf6en */
 177 #define XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT               4
 178 #define XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK                0x1   /* cf7en */
 179 #define XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT               5
 180 #define XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK                0x1   /* cf8en */
 181 #define XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT               6
 182 #define XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK                0x1   /* cf9en */
 183 #define XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT               7
 184         u8 flags9;
 185 #define XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK               0x1   /* cf10en */
 186 #define XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT              0
 187 #define XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK               0x1   /* cf11en */
 188 #define XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT              1
 189 #define XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK               0x1   /* cf12en */
 190 #define XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT              2
 191 #define XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK               0x1   /* cf13en */
 192 #define XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT              3
 193 #define XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK               0x1   /* cf14en */
 194 #define XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT              4
 195 #define XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK               0x1   /* cf15en */
 196 #define XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT              5
 197 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK  0x1   /* cf16en */
 198 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT 6
 199 #define XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK               0x1
 200 #define XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT              7
 201         u8 flags10;
 202 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK             0x1   /* cf18en */
 203 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT            0
 204 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK      0x1   /* cf19en */
 205 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT     1
 206 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK          0x1   /* cf20en */
 207 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT         2
 208 #define XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK           0x1   /* cf21en */
 209 #define XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT          3
 210 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK         0x1   /* cf22en */
 211 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT        4
 212 #define XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK               0x1   /* cf23en */
 213 #define XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT              5
 214 #define XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK           0x1   /* rule0en */
 215 #define XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT          6
 216 #define XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK           0x1   /* rule1en */
 217 #define XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT          7
 218         u8 flags11;
 219 #define XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK           0x1   /* rule2en */
 220 #define XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT          0
 221 #define XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK           0x1   /* rule3en */
 222 #define XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT          1
 223 #define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK       0x1   /* rule4en */
 224 #define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT      2
 225 #define XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK              0x1   /* rule5en */
 226 #define XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT             3
 227 #define XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK              0x1   /* rule6en */
 228 #define XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT             4
 229 #define XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK              0x1   /* rule7en */
 230 #define XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT             5
 231 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK         0x1   /* rule8en */
 232 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT        6
 233 #define XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK              0x1   /* rule9en */
 234 #define XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT             7
 235         u8 flags12;
 236 #define XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK             0x1   /* rule10en */
 237 #define XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT            0
 238 #define XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK             0x1   /* rule11en */
 239 #define XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT            1
 240 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK         0x1   /* rule12en */
 241 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT        2
 242 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK         0x1   /* rule13en */
 243 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT        3
 244 #define XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK             0x1   /* rule14en */
 245 #define XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT            4
 246 #define XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK             0x1   /* rule15en */
 247 #define XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT            5
 248 #define XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK             0x1   /* rule16en */
 249 #define XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT            6
 250 #define XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK             0x1   /* rule17en */
 251 #define XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT            7
 252         u8 flags13;
 253 #define XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK             0x1   /* rule18en */
 254 #define XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT            0
 255 #define XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK             0x1   /* rule19en */
 256 #define XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT            1
 257 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK         0x1   /* rule20en */
 258 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT        2
 259 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK         0x1   /* rule21en */
 260 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT        3
 261 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK         0x1   /* rule22en */
 262 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT        4
 263 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK         0x1   /* rule23en */
 264 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT        5
 265 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK         0x1   /* rule24en */
 266 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT        6
 267 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK         0x1   /* rule25en */
 268 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT        7
 269         u8 flags14;
 270 #define XSTORM_CORE_CONN_AG_CTX_BIT16_MASK                0x1   /* bit16 */
 271 #define XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT               0
 272 #define XSTORM_CORE_CONN_AG_CTX_BIT17_MASK                0x1   /* bit17 */
 273 #define XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT               1
 274 #define XSTORM_CORE_CONN_AG_CTX_BIT18_MASK                0x1   /* bit18 */
 275 #define XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT               2
 276 #define XSTORM_CORE_CONN_AG_CTX_BIT19_MASK                0x1   /* bit19 */
 277 #define XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT               3
 278 #define XSTORM_CORE_CONN_AG_CTX_BIT20_MASK                0x1   /* bit20 */
 279 #define XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT               4
 280 #define XSTORM_CORE_CONN_AG_CTX_BIT21_MASK                0x1   /* bit21 */
 281 #define XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT               5
 282 #define XSTORM_CORE_CONN_AG_CTX_CF23_MASK                 0x3   /* cf23 */
 283 #define XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT                6
 284         u8      byte2 /* byte2 */;
 285         __le16  physical_q0 /* physical_q0 */;
 286         __le16  consolid_prod /* physical_q1 */;
 287         __le16  reserved16 /* physical_q2 */;
 288         __le16  tx_bd_cons /* word3 */;
 289         __le16  tx_bd_or_spq_prod /* word4 */;
 290         __le16  word5 /* word5 */;
 291         __le16  conn_dpi /* conn_dpi */;
 292         u8      byte3 /* byte3 */;
 293         u8      byte4 /* byte4 */;
 294         u8      byte5 /* byte5 */;
 295         u8      byte6 /* byte6 */;
 296         __le32  reg0 /* reg0 */;
 297         __le32  reg1 /* reg1 */;
 298         __le32  reg2 /* reg2 */;
 299         __le32  reg3 /* reg3 */;
 300         __le32  reg4 /* reg4 */;
 301         __le32  reg5 /* cf_array0 */;
 302         __le32  reg6 /* cf_array1 */;
 303         __le16  word7 /* word7 */;
 304         __le16  word8 /* word8 */;
 305         __le16  word9 /* word9 */;
 306         __le16  word10 /* word10 */;
 307         __le32  reg7 /* reg7 */;
 308         __le32  reg8 /* reg8 */;
 309         __le32  reg9 /* reg9 */;
 310         u8      byte7 /* byte7 */;
 311         u8      byte8 /* byte8 */;
 312         u8      byte9 /* byte9 */;
 313         u8      byte10 /* byte10 */;
 314         u8      byte11 /* byte11 */;
 315         u8      byte12 /* byte12 */;
 316         u8      byte13 /* byte13 */;
 317         u8      byte14 /* byte14 */;
 318         u8      byte15 /* byte15 */;
 319         u8      byte16 /* byte16 */;
 320         __le16  word11 /* word11 */;
 321         __le32  reg10 /* reg10 */;
 322         __le32  reg11 /* reg11 */;
 323         __le32  reg12 /* reg12 */;
 324         __le32  reg13 /* reg13 */;
 325         __le32  reg14 /* reg14 */;
 326         __le32  reg15 /* reg15 */;
 327         __le32  reg16 /* reg16 */;
 328         __le32  reg17 /* reg17 */;
 329         __le32  reg18 /* reg18 */;
 330         __le32  reg19 /* reg19 */;
 331         __le16  word12 /* word12 */;
 332         __le16  word13 /* word13 */;
 333         __le16  word14 /* word14 */;
 334         __le16  word15 /* word15 */;
 335 };
 336
 337 struct tstorm_core_conn_ag_ctx {
 338         u8      byte0 /* cdu_validation */;
 339         u8      byte1 /* state */;
 340         u8      flags0;
 341 #define TSTORM_CORE_CONN_AG_CTX_BIT0_MASK     0x1       /* exist_in_qm0 */
 342 #define TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT    0
 343 #define TSTORM_CORE_CONN_AG_CTX_BIT1_MASK     0x1       /* exist_in_qm1 */
 344 #define TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT    1
 345 #define TSTORM_CORE_CONN_AG_CTX_BIT2_MASK     0x1       /* bit2 */
 346 #define TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT    2
 347 #define TSTORM_CORE_CONN_AG_CTX_BIT3_MASK     0x1       /* bit3 */
 348 #define TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT    3
 349 #define TSTORM_CORE_CONN_AG_CTX_BIT4_MASK     0x1       /* bit4 */
 350 #define TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT    4
 351 #define TSTORM_CORE_CONN_AG_CTX_BIT5_MASK     0x1       /* bit5 */
 352 #define TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT    5
 353 #define TSTORM_CORE_CONN_AG_CTX_CF0_MASK      0x3       /* timer0cf */
 354 #define TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT     6
 355         u8 flags1;
 356 #define TSTORM_CORE_CONN_AG_CTX_CF1_MASK      0x3       /* timer1cf */
 357 #define TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT     0
 358 #define TSTORM_CORE_CONN_AG_CTX_CF2_MASK      0x3       /* timer2cf */
 359 #define TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT     2
 360 #define TSTORM_CORE_CONN_AG_CTX_CF3_MASK      0x3       /* timer_stop_all */
 361 #define TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT     4
 362 #define TSTORM_CORE_CONN_AG_CTX_CF4_MASK      0x3       /* cf4 */
 363 #define TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT     6
 364         u8 flags2;
 365 #define TSTORM_CORE_CONN_AG_CTX_CF5_MASK      0x3       /* cf5 */
 366 #define TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT     0
 367 #define TSTORM_CORE_CONN_AG_CTX_CF6_MASK      0x3       /* cf6 */
 368 #define TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT     2
 369 #define TSTORM_CORE_CONN_AG_CTX_CF7_MASK      0x3       /* cf7 */
 370 #define TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT     4
 371 #define TSTORM_CORE_CONN_AG_CTX_CF8_MASK      0x3       /* cf8 */
 372 #define TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT     6
 373         u8 flags3;
 374 #define TSTORM_CORE_CONN_AG_CTX_CF9_MASK      0x3       /* cf9 */
 375 #define TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT     0
 376 #define TSTORM_CORE_CONN_AG_CTX_CF10_MASK     0x3       /* cf10 */
 377 #define TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT    2
 378 #define TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK    0x1       /* cf0en */
 379 #define TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT   4
 380 #define TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK    0x1       /* cf1en */
 381 #define TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT   5
 382 #define TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK    0x1       /* cf2en */
 383 #define TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT   6
 384 #define TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK    0x1       /* cf3en */
 385 #define TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT   7
 386         u8 flags4;
 387 #define TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK    0x1       /* cf4en */
 388 #define TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT   0
 389 #define TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK    0x1       /* cf5en */
 390 #define TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT   1
 391 #define TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK    0x1       /* cf6en */
 392 #define TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT   2
 393 #define TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK    0x1       /* cf7en */
 394 #define TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT   3
 395 #define TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK    0x1       /* cf8en */
 396 #define TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT   4
 397 #define TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK    0x1       /* cf9en */
 398 #define TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT   5
 399 #define TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK   0x1       /* cf10en */
 400 #define TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT  6
 401 #define TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK  0x1       /* rule0en */
 402 #define TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
 403         u8 flags5;
 404 #define TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK  0x1       /* rule1en */
 405 #define TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
 406 #define TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK  0x1       /* rule2en */
 407 #define TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
 408 #define TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK  0x1       /* rule3en */
 409 #define TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
 410 #define TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK  0x1       /* rule4en */
 411 #define TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
 412 #define TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK  0x1       /* rule5en */
 413 #define TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
 414 #define TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK  0x1       /* rule6en */
 415 #define TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
 416 #define TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK  0x1       /* rule7en */
 417 #define TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
 418 #define TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK  0x1       /* rule8en */
 419 #define TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
 420         __le32  reg0 /* reg0 */;
 421         __le32  reg1 /* reg1 */;
 422         __le32  reg2 /* reg2 */;
 423         __le32  reg3 /* reg3 */;
 424         __le32  reg4 /* reg4 */;
 425         __le32  reg5 /* reg5 */;
 426         __le32  reg6 /* reg6 */;
 427         __le32  reg7 /* reg7 */;
 428         __le32  reg8 /* reg8 */;
 429         u8      byte2 /* byte2 */;
 430         u8      byte3 /* byte3 */;
 431         __le16  word0 /* word0 */;
 432         u8      byte4 /* byte4 */;
 433         u8      byte5 /* byte5 */;
 434         __le16  word1 /* word1 */;
 435         __le16  word2 /* conn_dpi */;
 436         __le16  word3 /* word3 */;
 437         __le32  reg9 /* reg9 */;
 438         __le32  reg10 /* reg10 */;
 439 };
 440
 441 struct ustorm_core_conn_ag_ctx {
 442         u8      reserved /* cdu_validation */;
 443         u8      byte1 /* state */;
 444         u8      flags0;
 445 #define USTORM_CORE_CONN_AG_CTX_BIT0_MASK     0x1       /* exist_in_qm0 */
 446 #define USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT    0
 447 #define USTORM_CORE_CONN_AG_CTX_BIT1_MASK     0x1       /* exist_in_qm1 */
 448 #define USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT    1
 449 #define USTORM_CORE_CONN_AG_CTX_CF0_MASK      0x3       /* timer0cf */
 450 #define USTORM_CORE_CONN_AG_CTX_CF0_SHIFT     2
 451 #define USTORM_CORE_CONN_AG_CTX_CF1_MASK      0x3       /* timer1cf */
 452 #define USTORM_CORE_CONN_AG_CTX_CF1_SHIFT     4
 453 #define USTORM_CORE_CONN_AG_CTX_CF2_MASK      0x3       /* timer2cf */
 454 #define USTORM_CORE_CONN_AG_CTX_CF2_SHIFT     6
 455         u8 flags1;
 456 #define USTORM_CORE_CONN_AG_CTX_CF3_MASK      0x3       /* timer_stop_all */
 457 #define USTORM_CORE_CONN_AG_CTX_CF3_SHIFT     0
 458 #define USTORM_CORE_CONN_AG_CTX_CF4_MASK      0x3       /* cf4 */
 459 #define USTORM_CORE_CONN_AG_CTX_CF4_SHIFT     2
 460 #define USTORM_CORE_CONN_AG_CTX_CF5_MASK      0x3       /* cf5 */
 461 #define USTORM_CORE_CONN_AG_CTX_CF5_SHIFT     4
 462 #define USTORM_CORE_CONN_AG_CTX_CF6_MASK      0x3       /* cf6 */
 463 #define USTORM_CORE_CONN_AG_CTX_CF6_SHIFT     6
 464         u8 flags2;
 465 #define USTORM_CORE_CONN_AG_CTX_CF0EN_MASK    0x1       /* cf0en */
 466 #define USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT   0
 467 #define USTORM_CORE_CONN_AG_CTX_CF1EN_MASK    0x1       /* cf1en */
 468 #define USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT   1
 469 #define USTORM_CORE_CONN_AG_CTX_CF2EN_MASK    0x1       /* cf2en */
 470 #define USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT   2
 471 #define USTORM_CORE_CONN_AG_CTX_CF3EN_MASK    0x1       /* cf3en */
 472 #define USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT   3
 473 #define USTORM_CORE_CONN_AG_CTX_CF4EN_MASK    0x1       /* cf4en */
 474 #define USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT   4
 475 #define USTORM_CORE_CONN_AG_CTX_CF5EN_MASK    0x1       /* cf5en */
 476 #define USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT   5
 477 #define USTORM_CORE_CONN_AG_CTX_CF6EN_MASK    0x1       /* cf6en */
 478 #define USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT   6
 479 #define USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK  0x1       /* rule0en */
 480 #define USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
 481         u8 flags3;
 482 #define USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK  0x1       /* rule1en */
 483 #define USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
 484 #define USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK  0x1       /* rule2en */
 485 #define USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
 486 #define USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK  0x1       /* rule3en */
 487 #define USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
 488 #define USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK  0x1       /* rule4en */
 489 #define USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
 490 #define USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK  0x1       /* rule5en */
 491 #define USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
 492 #define USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK  0x1       /* rule6en */
 493 #define USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
 494 #define USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK  0x1       /* rule7en */
 495 #define USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
 496 #define USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK  0x1       /* rule8en */
 497 #define USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
 498         u8      byte2 /* byte2 */;
 499         u8      byte3 /* byte3 */;
 500         __le16  word0 /* conn_dpi */;
 501         __le16  word1 /* word1 */;
 502         __le32  rx_producers /* reg0 */;
 503         __le32  reg1 /* reg1 */;
 504         __le32  reg2 /* reg2 */;
 505         __le32  reg3 /* reg3 */;
 506         __le16  word2 /* word2 */;
 507         __le16  word3 /* word3 */;
 508 };
 509
 510 /* The core storm context for the Mstorm */
 511 struct mstorm_core_conn_st_ctx {
 512         __le32 reserved[24];
 513 };
 514
 515 /* The core storm context for the Ustorm */
 516 struct ustorm_core_conn_st_ctx {
 517         __le32 reserved[4];
 518 };
 519
 520 /* core connection context */
 521 struct core_conn_context {
 522         struct ystorm_core_conn_st_ctx  ystorm_st_context;
 523         struct regpair                  ystorm_st_padding[2] /* padding */;
 524         struct pstorm_core_conn_st_ctx  pstorm_st_context;
 525         struct regpair                  pstorm_st_padding[2];
 526         struct xstorm_core_conn_st_ctx  xstorm_st_context;
 527         struct xstorm_core_conn_ag_ctx  xstorm_ag_context;
 528         struct tstorm_core_conn_ag_ctx  tstorm_ag_context;
 529         struct ustorm_core_conn_ag_ctx  ustorm_ag_context;
 530         struct mstorm_core_conn_st_ctx  mstorm_st_context;
 531         struct ustorm_core_conn_st_ctx  ustorm_st_context;
 532         struct regpair                  ustorm_st_padding[2] /* padding */;
 533 };
 534
 535 struct eth_mstorm_per_queue_stat {
 536         struct regpair  ttl0_discard;
 537         struct regpair  packet_too_big_discard;
 538         struct regpair  no_buff_discard;
 539         struct regpair  not_active_discard;
 540         struct regpair  tpa_coalesced_pkts;
 541         struct regpair  tpa_coalesced_events;
 542         struct regpair  tpa_aborts_num;
 543         struct regpair  tpa_coalesced_bytes;
 544 };
 545
 546 struct eth_pstorm_per_queue_stat {
 547         struct regpair  sent_ucast_bytes;
 548         struct regpair  sent_mcast_bytes;
 549         struct regpair  sent_bcast_bytes;
 550         struct regpair  sent_ucast_pkts;
 551         struct regpair  sent_mcast_pkts;
 552         struct regpair  sent_bcast_pkts;
 553         struct regpair  error_drop_pkts;
 554 };
 555
 556 struct eth_ustorm_per_queue_stat {
 557         struct regpair  rcv_ucast_bytes;
 558         struct regpair  rcv_mcast_bytes;
 559         struct regpair  rcv_bcast_bytes;
 560         struct regpair  rcv_ucast_pkts;
 561         struct regpair  rcv_mcast_pkts;
 562         struct regpair  rcv_bcast_pkts;
 563 };
 564
 565 /* Event Ring Next Page Address */
 566 struct event_ring_next_addr {
 567         struct regpair  addr /* Next Page Address */;
 568         __le32          reserved[2] /* Reserved */;
 569 };
 570
 571 union event_ring_element {
 572         struct event_ring_entry         entry /* Event Ring Entry */;
 573         struct event_ring_next_addr     next_addr;
 574 };
 575
 576 struct mstorm_non_trigger_vf_zone {
 577         struct eth_mstorm_per_queue_stat eth_queue_stat;
 578 };
 579
 580 struct mstorm_vf_zone {
 581         struct mstorm_non_trigger_vf_zone non_trigger;
 582 };
 583
 584 enum personality_type {
 585         BAD_PERSONALITY_TYP,
 586         PERSONALITY_RESERVED,
 587         PERSONALITY_RESERVED2,
 588         PERSONALITY_RDMA_AND_ETH /* Roce or Iwarp */,
 589         PERSONALITY_RESERVED3,
 590         PERSONALITY_CORE,
 591         PERSONALITY_ETH /* Ethernet */,
 592         PERSONALITY_RESERVED4,
 593         MAX_PERSONALITY_TYPE
 594 };
 595
 596 struct pf_start_tunnel_config {
 597         u8      set_vxlan_udp_port_flg;
 598         u8      set_geneve_udp_port_flg;
 599         u8      tx_enable_vxlan /* If set, enable VXLAN tunnel in TX path. */;
 600         u8      tx_enable_l2geneve;
 601         u8      tx_enable_ipgeneve;
 602         u8      tx_enable_l2gre /* If set, enable l2 GRE tunnel in TX path. */;
 603         u8      tx_enable_ipgre /* If set, enable IP GRE tunnel in TX path. */;
 604         u8      tunnel_clss_vxlan /* Classification scheme for VXLAN tunnel. */;
 605         u8      tunnel_clss_l2geneve;
 606         u8      tunnel_clss_ipgeneve;
 607         u8      tunnel_clss_l2gre;
 608         u8      tunnel_clss_ipgre;
 609         __le16  vxlan_udp_port /* VXLAN tunnel UDP destination port. */;
 610         __le16  geneve_udp_port /* GENEVE tunnel UDP destination port. */;
 611 };
 612
 613 /* Ramrod data for PF start ramrod */
 614 struct pf_start_ramrod_data {
 615         struct regpair                  event_ring_pbl_addr;
 616         struct regpair                  consolid_q_pbl_addr;
 617         struct pf_start_tunnel_config   tunnel_config;
 618         __le16                          event_ring_sb_id;
 619         u8                              base_vf_id;
 620         u8                              num_vfs;
 621         u8                              event_ring_num_pages;
 622         u8                              event_ring_sb_index;
 623         u8                              path_id;
 624         u8                              warning_as_error;
 625         u8                              dont_log_ramrods;
 626         u8                              personality;
 627         __le16                          log_type_mask;
 628         u8                              mf_mode /* Multi function mode */;
 629         u8                              integ_phase /* Integration phase */;
 630         u8                              allow_npar_tx_switching;
 631         u8                              inner_to_outer_pri_map[8];
 632         u8                              pri_map_valid;
 633         u32                             outer_tag;
 634         u8                              reserved0[4];
 635 };
 636
 637 /* Data for port update ramrod */
 638 struct protocol_dcb_data {
 639         u8 dcb_enable_flag;
 640         u8 dcb_priority;
 641         u8 dcb_tc;
 642         u8 reserved;
 643 };
 644
 645 /* tunnel configuration */
 646 struct pf_update_tunnel_config {
 647         u8      update_rx_pf_clss;
 648         u8      update_tx_pf_clss;
 649         u8      set_vxlan_udp_port_flg;
 650         u8      set_geneve_udp_port_flg;
 651         u8      tx_enable_vxlan;
 652         u8      tx_enable_l2geneve;
 653         u8      tx_enable_ipgeneve;
 654         u8      tx_enable_l2gre;
 655         u8      tx_enable_ipgre;
 656         u8      tunnel_clss_vxlan;
 657         u8      tunnel_clss_l2geneve;
 658         u8      tunnel_clss_ipgeneve;
 659         u8      tunnel_clss_l2gre;
 660         u8      tunnel_clss_ipgre;
 661         __le16  vxlan_udp_port;
 662         __le16  geneve_udp_port;
 663         __le16  reserved[3];
 664 };
 665
 666 struct pf_update_ramrod_data {
 667         u8 pf_id;
 668         u8 update_eth_dcb_data_flag;
 669         u8 update_fcoe_dcb_data_flag;
 670         u8 update_iscsi_dcb_data_flag;
 671         u8 update_roce_dcb_data_flag;
 672         u8 update_mf_vlan_flag;
 673         __le16 mf_vlan;
 674         struct protocol_dcb_data eth_dcb_data;
 675         struct protocol_dcb_data fcoe_dcb_data;
 676         struct protocol_dcb_data iscsi_dcb_data;
 677         struct protocol_dcb_data roce_dcb_data;
 678         struct pf_update_tunnel_config  tunnel_config;
 679 };
 680
 681 /* Tunnel classification scheme */
 682 enum tunnel_clss {
 683         TUNNEL_CLSS_MAC_VLAN = 0,
 684         TUNNEL_CLSS_MAC_VNI,
 685         TUNNEL_CLSS_INNER_MAC_VLAN,
 686         TUNNEL_CLSS_INNER_MAC_VNI,
 687         MAX_TUNNEL_CLSS
 688 };
 689
 690 enum ports_mode {
 691         ENGX2_PORTX1 /* 2 engines x 1 port */,
 692         ENGX2_PORTX2 /* 2 engines x 2 ports */,
 693         ENGX1_PORTX1 /* 1 engine  x 1 port */,
 694         ENGX1_PORTX2 /* 1 engine  x 2 ports */,
 695         ENGX1_PORTX4 /* 1 engine  x 4 ports */,
 696         MAX_PORTS_MODE
 697 };
 698
 699 struct pstorm_non_trigger_vf_zone {
 700         struct eth_pstorm_per_queue_stat eth_queue_stat;
 701         struct regpair reserved[2];
 702 };
 703
 704 struct pstorm_vf_zone {
 705         struct pstorm_non_trigger_vf_zone non_trigger;
 706         struct regpair reserved[7];
 707 };
 708
 709 /* Ramrod Header of SPQE */
 710 struct ramrod_header {
 711         __le32  cid /* Slowpath Connection CID */;
 712         u8      cmd_id /* Ramrod Cmd (Per Protocol Type) */;
 713         u8      protocol_id /* Ramrod Protocol ID */;
 714         __le16  echo /* Ramrod echo */;
 715 };
 716
 717 /* Slowpath Element (SPQE) */
 718 struct slow_path_element {
 719         struct ramrod_header    hdr /* Ramrod Header */;
 720         struct regpair          data_ptr;
 721 };
 722
 723 struct tstorm_per_port_stat {
 724         struct regpair  trunc_error_discard;
 725         struct regpair  mac_error_discard;
 726         struct regpair  mftag_filter_discard;
 727         struct regpair  eth_mac_filter_discard;
 728         struct regpair  ll2_mac_filter_discard;
 729         struct regpair  ll2_conn_disabled_discard;
 730         struct regpair  iscsi_irregular_pkt;
 731         struct regpair  fcoe_irregular_pkt;
 732         struct regpair  roce_irregular_pkt;
 733         struct regpair  eth_irregular_pkt;
 734         struct regpair  toe_irregular_pkt;
 735         struct regpair  preroce_irregular_pkt;
 736 };
 737
 738 struct ustorm_non_trigger_vf_zone {
 739         struct eth_ustorm_per_queue_stat eth_queue_stat;
 740         struct regpair vf_pf_msg_addr;
 741 };
 742
 743 struct ustorm_trigger_vf_zone {
 744         u8 vf_pf_msg_valid;
 745         u8 reserved[7];
 746 };
 747
 748 struct ustorm_vf_zone {
 749         struct ustorm_non_trigger_vf_zone non_trigger;
 750         struct ustorm_trigger_vf_zone trigger;
 751 };
 752
 753 struct vf_start_ramrod_data {
 754         u8 vf_id;
 755         u8 enable_flr_ack;
 756         __le16 opaque_fid;
 757         u8 personality;
 758         u8 reserved[3];
 759 };
 760
 761 struct vf_stop_ramrod_data {
 762         u8 vf_id;
 763         u8 reserved0;
 764         __le16 reserved1;
 765         __le32 reserved2;
 766 };
 767
 768 struct atten_status_block {
 769         __le32  atten_bits;
 770         __le32  atten_ack;
 771         __le16  reserved0;
 772         __le16  sb_index /* status block running index */;
 773         __le32  reserved1;
 774 };
 775
 776 enum block_addr {
 777         GRCBASE_GRC             = 0x50000,
 778         GRCBASE_MISCS           = 0x9000,
 779         GRCBASE_MISC            = 0x8000,
 780         GRCBASE_DBU             = 0xa000,
 781         GRCBASE_PGLUE_B         = 0x2a8000,
 782         GRCBASE_CNIG            = 0x218000,
 783         GRCBASE_CPMU            = 0x30000,
 784         GRCBASE_NCSI            = 0x40000,
 785         GRCBASE_OPTE            = 0x53000,
 786         GRCBASE_BMB             = 0x540000,
 787         GRCBASE_PCIE            = 0x54000,
 788         GRCBASE_MCP             = 0xe00000,
 789         GRCBASE_MCP2            = 0x52000,
 790         GRCBASE_PSWHST          = 0x2a0000,
 791         GRCBASE_PSWHST2         = 0x29e000,
 792         GRCBASE_PSWRD           = 0x29c000,
 793         GRCBASE_PSWRD2          = 0x29d000,
 794         GRCBASE_PSWWR           = 0x29a000,
 795         GRCBASE_PSWWR2          = 0x29b000,
 796         GRCBASE_PSWRQ           = 0x280000,
 797         GRCBASE_PSWRQ2          = 0x240000,
 798         GRCBASE_PGLCS           = 0x0,
 799         GRCBASE_PTU             = 0x560000,
 800         GRCBASE_DMAE            = 0xc000,
 801         GRCBASE_TCM             = 0x1180000,
 802         GRCBASE_MCM             = 0x1200000,
 803         GRCBASE_UCM             = 0x1280000,
 804         GRCBASE_XCM             = 0x1000000,
 805         GRCBASE_YCM             = 0x1080000,
 806         GRCBASE_PCM             = 0x1100000,
 807         GRCBASE_QM              = 0x2f0000,
 808         GRCBASE_TM              = 0x2c0000,
 809         GRCBASE_DORQ            = 0x100000,
 810         GRCBASE_BRB             = 0x340000,
 811         GRCBASE_SRC             = 0x238000,
 812         GRCBASE_PRS             = 0x1f0000,
 813         GRCBASE_TSDM            = 0xfb0000,
 814         GRCBASE_MSDM            = 0xfc0000,
 815         GRCBASE_USDM            = 0xfd0000,
 816         GRCBASE_XSDM            = 0xf80000,
 817         GRCBASE_YSDM            = 0xf90000,
 818         GRCBASE_PSDM            = 0xfa0000,
 819         GRCBASE_TSEM            = 0x1700000,
 820         GRCBASE_MSEM            = 0x1800000,
 821         GRCBASE_USEM            = 0x1900000,
 822         GRCBASE_XSEM            = 0x1400000,
 823         GRCBASE_YSEM            = 0x1500000,
 824         GRCBASE_PSEM            = 0x1600000,
 825         GRCBASE_RSS             = 0x238800,
 826         GRCBASE_TMLD            = 0x4d0000,
 827         GRCBASE_MULD            = 0x4e0000,
 828         GRCBASE_YULD            = 0x4c8000,
 829         GRCBASE_XYLD            = 0x4c0000,
 830         GRCBASE_PRM             = 0x230000,
 831         GRCBASE_PBF_PB1         = 0xda0000,
 832         GRCBASE_PBF_PB2         = 0xda4000,
 833         GRCBASE_RPB             = 0x23c000,
 834         GRCBASE_BTB             = 0xdb0000,
 835         GRCBASE_PBF             = 0xd80000,
 836         GRCBASE_RDIF            = 0x300000,
 837         GRCBASE_TDIF            = 0x310000,
 838         GRCBASE_CDU             = 0x580000,
 839         GRCBASE_CCFC            = 0x2e0000,
 840         GRCBASE_TCFC            = 0x2d0000,
 841         GRCBASE_IGU             = 0x180000,
 842         GRCBASE_CAU             = 0x1c0000,
 843         GRCBASE_UMAC            = 0x51000,
 844         GRCBASE_XMAC            = 0x210000,
 845         GRCBASE_DBG             = 0x10000,
 846         GRCBASE_NIG             = 0x500000,
 847         GRCBASE_WOL             = 0x600000,
 848         GRCBASE_BMBN            = 0x610000,
 849         GRCBASE_IPC             = 0x20000,
 850         GRCBASE_NWM             = 0x800000,
 851         GRCBASE_NWS             = 0x700000,
 852         GRCBASE_MS              = 0x6a0000,
 853         GRCBASE_PHY_PCIE        = 0x620000,
 854         GRCBASE_MISC_AEU        = 0x8000,
 855         GRCBASE_BAR0_MAP        = 0x1c00000,
 856         MAX_BLOCK_ADDR
 857 };
 858
 859 enum block_id {
 860         BLOCK_GRC,
 861         BLOCK_MISCS,
 862         BLOCK_MISC,
 863         BLOCK_DBU,
 864         BLOCK_PGLUE_B,
 865         BLOCK_CNIG,
 866         BLOCK_CPMU,
 867         BLOCK_NCSI,
 868         BLOCK_OPTE,
 869         BLOCK_BMB,
 870         BLOCK_PCIE,
 871         BLOCK_MCP,
 872         BLOCK_MCP2,
 873         BLOCK_PSWHST,
 874         BLOCK_PSWHST2,
 875         BLOCK_PSWRD,
 876         BLOCK_PSWRD2,
 877         BLOCK_PSWWR,
 878         BLOCK_PSWWR2,
 879         BLOCK_PSWRQ,
 880         BLOCK_PSWRQ2,
 881         BLOCK_PGLCS,
 882         BLOCK_PTU,
 883         BLOCK_DMAE,
 884         BLOCK_TCM,
 885         BLOCK_MCM,
 886         BLOCK_UCM,
 887         BLOCK_XCM,
 888         BLOCK_YCM,
 889         BLOCK_PCM,
 890         BLOCK_QM,
 891         BLOCK_TM,
 892         BLOCK_DORQ,
 893         BLOCK_BRB,
 894         BLOCK_SRC,
 895         BLOCK_PRS,
 896         BLOCK_TSDM,
 897         BLOCK_MSDM,
 898         BLOCK_USDM,
 899         BLOCK_XSDM,
 900         BLOCK_YSDM,
 901         BLOCK_PSDM,
 902         BLOCK_TSEM,
 903         BLOCK_MSEM,
 904         BLOCK_USEM,
 905         BLOCK_XSEM,
 906         BLOCK_YSEM,
 907         BLOCK_PSEM,
 908         BLOCK_RSS,
 909         BLOCK_TMLD,
 910         BLOCK_MULD,
 911         BLOCK_YULD,
 912         BLOCK_XYLD,
 913         BLOCK_PRM,
 914         BLOCK_PBF_PB1,
 915         BLOCK_PBF_PB2,
 916         BLOCK_RPB,
 917         BLOCK_BTB,
 918         BLOCK_PBF,
 919         BLOCK_RDIF,
 920         BLOCK_TDIF,
 921         BLOCK_CDU,
 922         BLOCK_CCFC,
 923         BLOCK_TCFC,
 924         BLOCK_IGU,
 925         BLOCK_CAU,
 926         BLOCK_UMAC,
 927         BLOCK_XMAC,
 928         BLOCK_DBG,
 929         BLOCK_NIG,
 930         BLOCK_WOL,
 931         BLOCK_BMBN,
 932         BLOCK_IPC,
 933         BLOCK_NWM,
 934         BLOCK_NWS,
 935         BLOCK_MS,
 936         BLOCK_PHY_PCIE,
 937         BLOCK_MISC_AEU,
 938         BLOCK_BAR0_MAP,
 939         MAX_BLOCK_ID
 940 };
 941
 942 enum command_type_bit {
 943         IGU_COMMAND_TYPE_NOP    = 0,
 944         IGU_COMMAND_TYPE_SET    = 1,
 945         MAX_COMMAND_TYPE_BIT
 946 };
 947
 948 struct dmae_cmd {
 949         __le32 opcode;
 950 #define DMAE_CMD_SRC_MASK              0x1
 951 #define DMAE_CMD_SRC_SHIFT             0
 952 #define DMAE_CMD_DST_MASK              0x3
 953 #define DMAE_CMD_DST_SHIFT             1
 954 #define DMAE_CMD_C_DST_MASK            0x1
 955 #define DMAE_CMD_C_DST_SHIFT           3
 956 #define DMAE_CMD_CRC_RESET_MASK        0x1
 957 #define DMAE_CMD_CRC_RESET_SHIFT       4
 958 #define DMAE_CMD_SRC_ADDR_RESET_MASK   0x1
 959 #define DMAE_CMD_SRC_ADDR_RESET_SHIFT  5
 960 #define DMAE_CMD_DST_ADDR_RESET_MASK   0x1
 961 #define DMAE_CMD_DST_ADDR_RESET_SHIFT  6
 962 #define DMAE_CMD_COMP_FUNC_MASK        0x1
 963 #define DMAE_CMD_COMP_FUNC_SHIFT       7
 964 #define DMAE_CMD_COMP_WORD_EN_MASK     0x1
 965 #define DMAE_CMD_COMP_WORD_EN_SHIFT    8
 966 #define DMAE_CMD_COMP_CRC_EN_MASK      0x1
 967 #define DMAE_CMD_COMP_CRC_EN_SHIFT     9
 968 #define DMAE_CMD_COMP_CRC_OFFSET_MASK  0x7
 969 #define DMAE_CMD_COMP_CRC_OFFSET_SHIFT 10
 970 #define DMAE_CMD_RESERVED1_MASK        0x1
 971 #define DMAE_CMD_RESERVED1_SHIFT       13
 972 #define DMAE_CMD_ENDIANITY_MODE_MASK   0x3
 973 #define DMAE_CMD_ENDIANITY_MODE_SHIFT  14
 974 #define DMAE_CMD_ERR_HANDLING_MASK     0x3
 975 #define DMAE_CMD_ERR_HANDLING_SHIFT    16
 976 #define DMAE_CMD_PORT_ID_MASK          0x3
 977 #define DMAE_CMD_PORT_ID_SHIFT         18
 978 #define DMAE_CMD_SRC_PF_ID_MASK        0xF
 979 #define DMAE_CMD_SRC_PF_ID_SHIFT       20
 980 #define DMAE_CMD_DST_PF_ID_MASK        0xF
 981 #define DMAE_CMD_DST_PF_ID_SHIFT       24
 982 #define DMAE_CMD_SRC_VF_ID_VALID_MASK  0x1
 983 #define DMAE_CMD_SRC_VF_ID_VALID_SHIFT 28
 984 #define DMAE_CMD_DST_VF_ID_VALID_MASK  0x1
 985 #define DMAE_CMD_DST_VF_ID_VALID_SHIFT 29
 986 #define DMAE_CMD_RESERVED2_MASK        0x3
 987 #define DMAE_CMD_RESERVED2_SHIFT       30
 988         __le32  src_addr_lo;
 989         __le32  src_addr_hi;
 990         __le32  dst_addr_lo;
 991         __le32  dst_addr_hi;
 992         __le16  length /* Length in DW */;
 993         __le16  opcode_b;
 994 #define DMAE_CMD_SRC_VF_ID_MASK        0xFF     /* Source VF id */
 995 #define DMAE_CMD_SRC_VF_ID_SHIFT       0
 996 #define DMAE_CMD_DST_VF_ID_MASK        0xFF     /* Destination VF id */
 997 #define DMAE_CMD_DST_VF_ID_SHIFT       8
 998         __le32  comp_addr_lo /* PCIe completion address low or grc address */;
 999         __le32  comp_addr_hi;
1000         __le32  comp_val /* Value to write to copmletion address */;
1001         __le32  crc32 /* crc16 result */;
1002         __le32  crc_32_c /* crc32_c result */;
1003         __le16  crc16 /* crc16 result */;
1004         __le16  crc16_c /* crc16_c result */;
1005         __le16  crc10 /* crc_t10 result */;
1006         __le16  reserved;
1007         __le16  xsum16 /* checksum16 result  */;
1008         __le16  xsum8 /* checksum8 result  */;
1009 };
1010
1011 struct igu_cleanup {
1012         __le32 sb_id_and_flags;
1013 #define IGU_CLEANUP_RESERVED0_MASK     0x7FFFFFF
1014 #define IGU_CLEANUP_RESERVED0_SHIFT    0
1015 #define IGU_CLEANUP_CLEANUP_SET_MASK   0x1 /* cleanup clear - 0, set - 1 */
1016 #define IGU_CLEANUP_CLEANUP_SET_SHIFT  27
1017 #define IGU_CLEANUP_CLEANUP_TYPE_MASK  0x7
1018 #define IGU_CLEANUP_CLEANUP_TYPE_SHIFT 28
1019 #define IGU_CLEANUP_COMMAND_TYPE_MASK  0x1
1020 #define IGU_CLEANUP_COMMAND_TYPE_SHIFT 31
1021         __le32 reserved1;
1022 };
1023
1024 union igu_command {
1025         struct igu_prod_cons_update     prod_cons_update;
1026         struct igu_cleanup              cleanup;
1027 };
1028
1029 struct igu_command_reg_ctrl {
1030         __le16  opaque_fid;
1031         __le16  igu_command_reg_ctrl_fields;
1032 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_MASK  0xFFF
1033 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_SHIFT 0
1034 #define IGU_COMMAND_REG_CTRL_RESERVED_MASK      0x7
1035 #define IGU_COMMAND_REG_CTRL_RESERVED_SHIFT     12
1036 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_MASK  0x1
1037 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_SHIFT 15
1038 };
1039
1040 struct igu_mapping_line {
1041         __le32 igu_mapping_line_fields;
1042 #define IGU_MAPPING_LINE_VALID_MASK            0x1
1043 #define IGU_MAPPING_LINE_VALID_SHIFT           0
1044 #define IGU_MAPPING_LINE_VECTOR_NUMBER_MASK    0xFF
1045 #define IGU_MAPPING_LINE_VECTOR_NUMBER_SHIFT   1
1046 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_MASK  0xFF
1047 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_SHIFT 9
1048 #define IGU_MAPPING_LINE_PF_VALID_MASK         0x1      /* PF-1, VF-0 */
1049 #define IGU_MAPPING_LINE_PF_VALID_SHIFT        17
1050 #define IGU_MAPPING_LINE_IPS_GROUP_MASK        0x3F
1051 #define IGU_MAPPING_LINE_IPS_GROUP_SHIFT       18
1052 #define IGU_MAPPING_LINE_RESERVED_MASK         0xFF
1053 #define IGU_MAPPING_LINE_RESERVED_SHIFT        24
1054 };
1055
1056 struct igu_msix_vector {
1057         struct regpair  address;
1058         __le32          data;
1059         __le32          msix_vector_fields;
1060 #define IGU_MSIX_VECTOR_MASK_BIT_MASK      0x1
1061 #define IGU_MSIX_VECTOR_MASK_BIT_SHIFT     0
1062 #define IGU_MSIX_VECTOR_RESERVED0_MASK     0x7FFF
1063 #define IGU_MSIX_VECTOR_RESERVED0_SHIFT    1
1064 #define IGU_MSIX_VECTOR_STEERING_TAG_MASK  0xFF
1065 #define IGU_MSIX_VECTOR_STEERING_TAG_SHIFT 16
1066 #define IGU_MSIX_VECTOR_RESERVED1_MASK     0xFF
1067 #define IGU_MSIX_VECTOR_RESERVED1_SHIFT    24
1068 };
1069
1070 enum init_modes {
1071         MODE_BB_A0,
1072         MODE_BB_B0,
1073         MODE_RESERVED2,
1074         MODE_ASIC,
1075         MODE_RESERVED3,
1076         MODE_RESERVED4,
1077         MODE_RESERVED5,
1078         MODE_RESERVED6,
1079         MODE_SF,
1080         MODE_MF_SD,
1081         MODE_MF_SI,
1082         MODE_PORTS_PER_ENG_1,
1083         MODE_PORTS_PER_ENG_2,
1084         MODE_PORTS_PER_ENG_4,
1085         MODE_100G,
1086         MODE_EAGLE_ENG1_WORKAROUND,
1087         MAX_INIT_MODES
1088 };
1089
1090 enum init_phases {
1091         PHASE_ENGINE,
1092         PHASE_PORT,
1093         PHASE_PF,
1094         PHASE_VF,
1095         PHASE_QM_PF,
1096         MAX_INIT_PHASES
1097 };
1098
1099 /* per encapsulation type enabling flags */
1100 struct prs_reg_encapsulation_type_en {
1101         u8 flags;
1102 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_MASK     0x1
1103 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT    0
1104 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_MASK      0x1
1105 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT     1
1106 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_MASK            0x1
1107 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT           2
1108 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_MASK            0x1
1109 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_SHIFT           3
1110 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_MASK  0x1
1111 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT 4
1112 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_MASK   0x1
1113 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT  5
1114 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_MASK                0x3
1115 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_SHIFT               6
1116 };
1117
1118 enum pxp_tph_st_hint {
1119         TPH_ST_HINT_BIDIR /* Read/Write access by Host and Device */,
1120         TPH_ST_HINT_REQUESTER /* Read/Write access by Device */,
1121         TPH_ST_HINT_TARGET,
1122         TPH_ST_HINT_TARGET_PRIO,
1123         MAX_PXP_TPH_ST_HINT
1124 };
1125
1126 /* QM hardware structure of enable bypass credit mask */
1127 struct qm_rf_bypass_mask {
1128         u8 flags;
1129 #define QM_RF_BYPASS_MASK_LINEVOQ_MASK    0x1
1130 #define QM_RF_BYPASS_MASK_LINEVOQ_SHIFT   0
1131 #define QM_RF_BYPASS_MASK_RESERVED0_MASK  0x1
1132 #define QM_RF_BYPASS_MASK_RESERVED0_SHIFT 1
1133 #define QM_RF_BYPASS_MASK_PFWFQ_MASK      0x1
1134 #define QM_RF_BYPASS_MASK_PFWFQ_SHIFT     2
1135 #define QM_RF_BYPASS_MASK_VPWFQ_MASK      0x1
1136 #define QM_RF_BYPASS_MASK_VPWFQ_SHIFT     3
1137 #define QM_RF_BYPASS_MASK_PFRL_MASK       0x1
1138 #define QM_RF_BYPASS_MASK_PFRL_SHIFT      4
1139 #define QM_RF_BYPASS_MASK_VPQCNRL_MASK    0x1
1140 #define QM_RF_BYPASS_MASK_VPQCNRL_SHIFT   5
1141 #define QM_RF_BYPASS_MASK_FWPAUSE_MASK    0x1
1142 #define QM_RF_BYPASS_MASK_FWPAUSE_SHIFT   6
1143 #define QM_RF_BYPASS_MASK_RESERVED1_MASK  0x1
1144 #define QM_RF_BYPASS_MASK_RESERVED1_SHIFT 7
1145 };
1146
1147 /* QM hardware structure of opportunistic credit mask */
1148 struct qm_rf_opportunistic_mask {
1149         __le16 flags;
1150 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_MASK     0x1
1151 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT    0
1152 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_MASK     0x1
1153 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_SHIFT    1
1154 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_MASK       0x1
1155 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_SHIFT      2
1156 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_MASK       0x1
1157 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_SHIFT      3
1158 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_MASK        0x1
1159 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_SHIFT       4
1160 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_MASK     0x1
1161 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_SHIFT    5
1162 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_MASK     0x1
1163 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_SHIFT    6
1164 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_MASK   0x1
1165 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_SHIFT  7
1166 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_MASK  0x1
1167 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_SHIFT 8
1168 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_MASK   0x7F
1169 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_SHIFT  9
1170 };
1171
1172 /* QM hardware structure of QM map memory */
1173 struct qm_rf_pq_map {
1174         u32 reg;
1175 #define QM_RF_PQ_MAP_PQ_VALID_MASK          0x1         /* PQ active */
1176 #define QM_RF_PQ_MAP_PQ_VALID_SHIFT         0
1177 #define QM_RF_PQ_MAP_RL_ID_MASK             0xFF        /* RL ID */
1178 #define QM_RF_PQ_MAP_RL_ID_SHIFT            1
1179 #define QM_RF_PQ_MAP_VP_PQ_ID_MASK          0x1FF
1180 #define QM_RF_PQ_MAP_VP_PQ_ID_SHIFT         9
1181 #define QM_RF_PQ_MAP_VOQ_MASK               0x1F        /* VOQ */
1182 #define QM_RF_PQ_MAP_VOQ_SHIFT              18
1183 #define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_MASK  0x3         /* WRR weight */
1184 #define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_SHIFT 23
1185 #define QM_RF_PQ_MAP_RL_VALID_MASK          0x1         /* RL active */
1186 #define QM_RF_PQ_MAP_RL_VALID_SHIFT         25
1187 #define QM_RF_PQ_MAP_RESERVED_MASK          0x3F
1188 #define QM_RF_PQ_MAP_RESERVED_SHIFT         26
1189 };
1190
1191 /* Completion params for aggregated interrupt completion */
1192 struct sdm_agg_int_comp_params {
1193         __le16 params;
1194 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_MASK      0x3F
1195 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT     0
1196 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_MASK  0x1
1197 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT 6
1198 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_MASK     0x1FF
1199 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT    7
1200 };
1201
1202 /* SDM operation gen command (generate aggregative interrupt) */
1203 struct sdm_op_gen {
1204         __le32 command;
1205 #define SDM_OP_GEN_COMP_PARAM_MASK  0xFFFF      /* completion parameters 0-15 */
1206 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0
1207 #define SDM_OP_GEN_COMP_TYPE_MASK   0xF         /* completion type 16-19 */
1208 #define SDM_OP_GEN_COMP_TYPE_SHIFT  16
1209 #define SDM_OP_GEN_RESERVED_MASK    0xFFF       /* reserved 20-31 */
1210 #define SDM_OP_GEN_RESERVED_SHIFT   20
1211 };
1212
1213 /*********************************** Init ************************************/
1214
1215 /* Width of GRC address in bits (addresses are specified in dwords) */
1216 #define GRC_ADDR_BITS                   23
1217 #define MAX_GRC_ADDR                    ((1 << GRC_ADDR_BITS) - 1)
1218
1219 /* indicates an init that should be applied to any phase ID */
1220 #define ANY_PHASE_ID                    0xffff
1221
1222 /* init pattern size in bytes */
1223 #define INIT_PATTERN_SIZE_BITS  4
1224 #define MAX_INIT_PATTERN_SIZE   BIT(INIT_PATTERN_SIZE_BITS)
1225
1226 /* Max size in dwords of a zipped array */
1227 #define MAX_ZIPPED_SIZE                 8192
1228
1229 /* Global PXP window */
1230 #define NUM_OF_PXP_WIN                  19
1231 #define PXP_WIN_DWORD_SIZE_BITS 10
1232 #define PXP_WIN_DWORD_SIZE              BIT(PXP_WIN_DWORD_SIZE_BITS)
1233 #define PXP_WIN_BYTE_SIZE_BITS  (PXP_WIN_DWORD_SIZE_BITS + 2)
1234 #define PXP_WIN_BYTE_SIZE               (PXP_WIN_DWORD_SIZE * 4)
1235
1236 /********************************* GRC Dump **********************************/
1237
1238 /* width of GRC dump register sequence length in bits */
1239 #define DUMP_SEQ_LEN_BITS                       8
1240 #define DUMP_SEQ_LEN_MAX_VAL            ((1 << DUMP_SEQ_LEN_BITS) - 1)
1241
1242 /* width of GRC dump memory length in bits */
1243 #define DUMP_MEM_LEN_BITS                       18
1244 #define DUMP_MEM_LEN_MAX_VAL            ((1 << DUMP_MEM_LEN_BITS) - 1)
1245
1246 /* width of register type ID in bits */
1247 #define REG_TYPE_ID_BITS                        6
1248 #define REG_TYPE_ID_MAX_VAL                     ((1 << REG_TYPE_ID_BITS) - 1)
1249
1250 /* width of block ID in bits */
1251 #define BLOCK_ID_BITS                           8
1252 #define BLOCK_ID_MAX_VAL                        ((1 << BLOCK_ID_BITS) - 1)
1253
1254 /******************************** Idle Check *********************************/
1255
1256 /* max number of idle check predicate immediates */
1257 #define MAX_IDLE_CHK_PRED_IMM           3
1258
1259 /* max number of idle check argument registers */
1260 #define MAX_IDLE_CHK_READ_REGS          3
1261
1262 /* max number of idle check loops */
1263 #define MAX_IDLE_CHK_LOOPS                      0x10000
1264
1265 /* max idle check address increment */
1266 #define MAX_IDLE_CHK_INCREMENT          0x10000
1267
1268 /* inicates an undefined idle check line index */
1269 #define IDLE_CHK_UNDEFINED_LINE_IDX     0xffffff
1270
1271 /* max number of register values following the idle check header */
1272 #define IDLE_CHK_MAX_DUMP_REGS          2
1273
1274 /* arguments for IDLE_CHK_MACRO_TYPE_QM_RD_WR */
1275 #define IDLE_CHK_QM_RD_WR_PTR           0
1276 #define IDLE_CHK_QM_RD_WR_BANK          1
1277
1278 /**************************************/
1279 /* HSI Functions constants and macros */
1280 /**************************************/
1281
1282 /* Number of VLAN priorities */
1283 #define NUM_OF_VLAN_PRIORITIES                  8
1284
1285 /* the MCP Trace meta data signautre is duplicated in the perl script that
1286  * generats the NVRAM images.
1287  */
1288 #define MCP_TRACE_META_IMAGE_SIGNATURE  0x669955aa
1289
1290 /* Binary buffer header */
1291 struct bin_buffer_hdr {
1292         u32     offset;
1293         u32     length /* buffer length in bytes */;
1294 };
1295
1296 /* binary buffer types */
1297 enum bin_buffer_type {
1298         BIN_BUF_FW_VER_INFO /* fw_ver_info struct */,
1299         BIN_BUF_INIT_CMD /* init commands */,
1300         BIN_BUF_INIT_VAL /* init data */,
1301         BIN_BUF_INIT_MODE_TREE /* init modes tree */,
1302         BIN_BUF_IRO /* internal RAM offsets array */,
1303         MAX_BIN_BUFFER_TYPE
1304 };
1305
1306 /* Chip IDs */
1307 enum chip_ids {
1308         CHIP_BB_A0 /* BB A0 chip ID */,
1309         CHIP_BB_B0 /* BB B0 chip ID */,
1310         CHIP_K2 /* AH chip ID */,
1311         MAX_CHIP_IDS
1312 };
1313
1314 struct init_array_raw_hdr {
1315         __le32 data;
1316 #define INIT_ARRAY_RAW_HDR_TYPE_MASK    0xF
1317 #define INIT_ARRAY_RAW_HDR_TYPE_SHIFT   0
1318 #define INIT_ARRAY_RAW_HDR_PARAMS_MASK  0xFFFFFFF       /* init array params */
1319 #define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4
1320 };
1321
1322 struct init_array_standard_hdr {
1323         __le32 data;
1324 #define INIT_ARRAY_STANDARD_HDR_TYPE_MASK  0xF
1325 #define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0
1326 #define INIT_ARRAY_STANDARD_HDR_SIZE_MASK  0xFFFFFFF
1327 #define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT 4
1328 };
1329
1330 struct init_array_zipped_hdr {
1331         __le32 data;
1332 #define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK         0xF
1333 #define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT        0
1334 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK  0xFFFFFFF
1335 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4
1336 };
1337
1338 struct init_array_pattern_hdr {
1339         __le32 data;
1340 #define INIT_ARRAY_PATTERN_HDR_TYPE_MASK          0xF
1341 #define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT         0
1342 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK  0xF
1343 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT 4
1344 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK   0xFFFFFF
1345 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT  8
1346 };
1347
1348 union init_array_hdr {
1349         struct init_array_raw_hdr       raw /* raw init array header */;
1350         struct init_array_standard_hdr  standard;
1351         struct init_array_zipped_hdr    zipped /* zipped init array header */;
1352         struct init_array_pattern_hdr   pattern /* pattern init array header */;
1353 };
1354
1355 enum init_array_types {
1356         INIT_ARR_STANDARD /* standard init array */,
1357         INIT_ARR_ZIPPED /* zipped init array */,
1358         INIT_ARR_PATTERN /* a repeated pattern */,
1359         MAX_INIT_ARRAY_TYPES
1360 };
1361
1362 /* init operation: callback */
1363 struct init_callback_op {
1364         __le32  op_data;
1365 #define INIT_CALLBACK_OP_OP_MASK        0xF
1366 #define INIT_CALLBACK_OP_OP_SHIFT       0
1367 #define INIT_CALLBACK_OP_RESERVED_MASK  0xFFFFFFF
1368 #define INIT_CALLBACK_OP_RESERVED_SHIFT 4
1369         __le16  callback_id /* Callback ID */;
1370         __le16  block_id /* Blocks ID */;
1371 };
1372
1373 /* init operation: delay */
1374 struct init_delay_op {
1375         __le32  op_data;
1376 #define INIT_DELAY_OP_OP_MASK        0xF
1377 #define INIT_DELAY_OP_OP_SHIFT       0
1378 #define INIT_DELAY_OP_RESERVED_MASK  0xFFFFFFF
1379 #define INIT_DELAY_OP_RESERVED_SHIFT 4
1380         __le32  delay /* delay in us */;
1381 };
1382
1383 /* init operation: if_mode */
1384 struct init_if_mode_op {
1385         __le32 op_data;
1386 #define INIT_IF_MODE_OP_OP_MASK          0xF
1387 #define INIT_IF_MODE_OP_OP_SHIFT         0
1388 #define INIT_IF_MODE_OP_RESERVED1_MASK   0xFFF
1389 #define INIT_IF_MODE_OP_RESERVED1_SHIFT  4
1390 #define INIT_IF_MODE_OP_CMD_OFFSET_MASK  0xFFFF
1391 #define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16
1392         __le16  reserved2;
1393         __le16  modes_buf_offset;
1394 };
1395
1396 /*  init operation: if_phase */
1397 struct init_if_phase_op {
1398         __le32 op_data;
1399 #define INIT_IF_PHASE_OP_OP_MASK           0xF
1400 #define INIT_IF_PHASE_OP_OP_SHIFT          0
1401 #define INIT_IF_PHASE_OP_DMAE_ENABLE_MASK  0x1
1402 #define INIT_IF_PHASE_OP_DMAE_ENABLE_SHIFT 4
1403 #define INIT_IF_PHASE_OP_RESERVED1_MASK    0x7FF
1404 #define INIT_IF_PHASE_OP_RESERVED1_SHIFT   5
1405 #define INIT_IF_PHASE_OP_CMD_OFFSET_MASK   0xFFFF
1406 #define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT  16
1407         __le32 phase_data;
1408 #define INIT_IF_PHASE_OP_PHASE_MASK        0xFF /* Init phase */
1409 #define INIT_IF_PHASE_OP_PHASE_SHIFT       0
1410 #define INIT_IF_PHASE_OP_RESERVED2_MASK    0xFF
1411 #define INIT_IF_PHASE_OP_RESERVED2_SHIFT   8
1412 #define INIT_IF_PHASE_OP_PHASE_ID_MASK     0xFFFF /* Init phase ID */
1413 #define INIT_IF_PHASE_OP_PHASE_ID_SHIFT    16
1414 };
1415
1416 /* init mode operators */
1417 enum init_mode_ops {
1418         INIT_MODE_OP_NOT /* init mode not operator */,
1419         INIT_MODE_OP_OR /* init mode or operator */,
1420         INIT_MODE_OP_AND /* init mode and operator */,
1421         MAX_INIT_MODE_OPS
1422 };
1423
1424 /* init operation: raw */
1425 struct init_raw_op {
1426         __le32  op_data;
1427 #define INIT_RAW_OP_OP_MASK      0xF
1428 #define INIT_RAW_OP_OP_SHIFT     0
1429 #define INIT_RAW_OP_PARAM1_MASK  0xFFFFFFF      /* init param 1 */
1430 #define INIT_RAW_OP_PARAM1_SHIFT 4
1431         __le32  param2 /* Init param 2 */;
1432 };
1433
1434 /* init array params */
1435 struct init_op_array_params {
1436         __le16  size /* array size in dwords */;
1437         __le16  offset /* array start offset in dwords */;
1438 };
1439
1440 /* Write init operation arguments */
1441 union init_write_args {
1442         __le32                          inline_val;
1443         __le32                          zeros_count;
1444         __le32                          array_offset;
1445         struct init_op_array_params     runtime;
1446 };
1447
1448 /* init operation: write */
1449 struct init_write_op {
1450         __le32 data;
1451 #define INIT_WRITE_OP_OP_MASK        0xF
1452 #define INIT_WRITE_OP_OP_SHIFT       0
1453 #define INIT_WRITE_OP_SOURCE_MASK    0x7
1454 #define INIT_WRITE_OP_SOURCE_SHIFT   4
1455 #define INIT_WRITE_OP_RESERVED_MASK  0x1
1456 #define INIT_WRITE_OP_RESERVED_SHIFT 7
1457 #define INIT_WRITE_OP_WIDE_BUS_MASK  0x1
1458 #define INIT_WRITE_OP_WIDE_BUS_SHIFT 8
1459 #define INIT_WRITE_OP_ADDRESS_MASK   0x7FFFFF
1460 #define INIT_WRITE_OP_ADDRESS_SHIFT  9
1461         union init_write_args args /* Write init operation arguments */;
1462 };
1463
1464 /* init operation: read */
1465 struct init_read_op {
1466         __le32 op_data;
1467 #define INIT_READ_OP_OP_MASK         0xF
1468 #define INIT_READ_OP_OP_SHIFT        0
1469 #define INIT_READ_OP_POLL_TYPE_MASK  0xF
1470 #define INIT_READ_OP_POLL_TYPE_SHIFT 4
1471 #define INIT_READ_OP_RESERVED_MASK   0x1
1472 #define INIT_READ_OP_RESERVED_SHIFT  8
1473 #define INIT_READ_OP_ADDRESS_MASK    0x7FFFFF
1474 #define INIT_READ_OP_ADDRESS_SHIFT   9
1475         __le32 expected_val;
1476 };
1477
1478 /* Init operations union */
1479 union init_op {
1480         struct init_raw_op      raw /* raw init operation */;
1481         struct init_write_op    write /* write init operation */;
1482         struct init_read_op     read /* read init operation */;
1483         struct init_if_mode_op  if_mode /* if_mode init operation */;
1484         struct init_if_phase_op if_phase /* if_phase init operation */;
1485         struct init_callback_op callback /* callback init operation */;
1486         struct init_delay_op    delay /* delay init operation */;
1487 };
1488
1489 /* Init command operation types */
1490 enum init_op_types {
1491         INIT_OP_READ /* GRC read init command */,
1492         INIT_OP_WRITE /* GRC write init command */,
1493         INIT_OP_IF_MODE,
1494         INIT_OP_IF_PHASE,
1495         INIT_OP_DELAY /* delay init command */,
1496         INIT_OP_CALLBACK /* callback init command */,
1497         MAX_INIT_OP_TYPES
1498 };
1499
1500 enum init_poll_types {
1501         INIT_POLL_NONE /* No polling */,
1502         INIT_POLL_EQ /* init value is included in the init command */,
1503         INIT_POLL_OR /* init value is all zeros */,
1504         INIT_POLL_AND /* init value is an array of values */,
1505         MAX_INIT_POLL_TYPES
1506 };
1507
1508 /* init source types */
1509 enum init_source_types {
1510         INIT_SRC_INLINE /* init value is included in the init command */,
1511         INIT_SRC_ZEROS /* init value is all zeros */,
1512         INIT_SRC_ARRAY /* init value is an array of values */,
1513         INIT_SRC_RUNTIME /* init value is provided during runtime */,
1514         MAX_INIT_SOURCE_TYPES
1515 };
1516
1517 /* Internal RAM Offsets macro data */
1518 struct iro {
1519         u32     base /* RAM field offset */;
1520         u16     m1 /* multiplier 1 */;
1521         u16     m2 /* multiplier 2 */;
1522         u16     m3 /* multiplier 3 */;
1523         u16     size /* RAM field size */;
1524 };
1525
1526 /* QM per-port init parameters */
1527 struct init_qm_port_params {
1528         u8      active /* Indicates if this port is active */;
1529         u8      num_active_phys_tcs;
1530         u16     num_pbf_cmd_lines;
1531         u16     num_btb_blocks;
1532         __le16  reserved;
1533 };
1534
1535 /* QM per-PQ init parameters */
1536 struct init_qm_pq_params {
1537         u8      vport_id /* VPORT ID */;
1538         u8      tc_id /* TC ID */;
1539         u8      wrr_group /* WRR group */;
1540         u8      reserved;
1541 };
1542
1543 /* QM per-vport init parameters */
1544 struct init_qm_vport_params {
1545         u32     vport_rl;
1546         u16     vport_wfq;
1547         u16     first_tx_pq_id[NUM_OF_TCS];
1548 };
1549
1550 /* Win 2 */
1551 #define GTT_BAR0_MAP_REG_IGU_CMD \
1552         0x00f000UL
1553 /* Win 3 */
1554 #define GTT_BAR0_MAP_REG_TSDM_RAM \
1555         0x010000UL
1556 /* Win 4 */
1557 #define GTT_BAR0_MAP_REG_MSDM_RAM \
1558         0x011000UL
1559 /* Win 5 */
1560 #define GTT_BAR0_MAP_REG_MSDM_RAM_1024 \
1561         0x012000UL
1562 /* Win 6 */
1563 #define GTT_BAR0_MAP_REG_USDM_RAM \
1564         0x013000UL
1565 /* Win 7 */
1566 #define GTT_BAR0_MAP_REG_USDM_RAM_1024 \
1567         0x014000UL
1568 /* Win 8 */
1569 #define GTT_BAR0_MAP_REG_USDM_RAM_2048 \
1570         0x015000UL
1571 /* Win 9 */
1572 #define GTT_BAR0_MAP_REG_XSDM_RAM \
1573         0x016000UL
1574 /* Win 10 */
1575 #define GTT_BAR0_MAP_REG_YSDM_RAM \
1576         0x017000UL
1577 /* Win 11 */
1578 #define GTT_BAR0_MAP_REG_PSDM_RAM \
1579         0x018000UL
1580
1581 /**
1582  * @brief qed_qm_pf_mem_size - prepare QM ILT sizes
1583  *
1584  * Returns the required host memory size in 4KB units.
1585  * Must be called before all QM init HSI functions.
1586  *
1587  * @param pf_id                 - physical function ID
1588  * @param num_pf_cids   - number of connections used by this PF
1589  * @param num_vf_cids   - number of connections used by VFs of this PF
1590  * @param num_tids              - number of tasks used by this PF
1591  * @param num_pf_pqs    - number of PQs used by this PF
1592  * @param num_vf_pqs    - number of PQs used by VFs of this PF
1593  *
1594  * @return The required host memory size in 4KB units.
1595  */
1596 u32 qed_qm_pf_mem_size(u8       pf_id,
1597                        u32      num_pf_cids,
1598                        u32      num_vf_cids,
1599                        u32      num_tids,
1600                        u16      num_pf_pqs,
1601                        u16      num_vf_pqs);
1602
1603 struct qed_qm_common_rt_init_params {
1604         u8                              max_ports_per_engine;
1605         u8                              max_phys_tcs_per_port;
1606         bool                            pf_rl_en;
1607         bool                            pf_wfq_en;
1608         bool                            vport_rl_en;
1609         bool                            vport_wfq_en;
1610         struct init_qm_port_params      *port_params;
1611 };
1612
1613 /**
1614  * @brief qed_qm_common_rt_init - Prepare QM runtime init values for the
1615  * engine phase.
1616  *
1617  * @param p_hwfn
1618  * @param max_ports_per_engine  - max number of ports per engine in HW
1619  * @param max_phys_tcs_per_port - max number of physical TCs per port in HW
1620  * @param pf_rl_en                              - enable per-PF rate limiters
1621  * @param pf_wfq_en                             - enable per-PF WFQ
1622  * @param vport_rl_en                   - enable per-VPORT rate limiters
1623  * @param vport_wfq_en                  - enable per-VPORT WFQ
1624  * @param port_params                   - array of size MAX_NUM_PORTS with
1625  *                                              arameters for each port
1626  *
1627  * @return 0 on success, -1 on error.
1628  */
1629 int qed_qm_common_rt_init(
1630         struct qed_hwfn                         *p_hwfn,
1631         struct qed_qm_common_rt_init_params     *p_params);
1632
1633 struct qed_qm_pf_rt_init_params {
1634         u8                              port_id;
1635         u8                              pf_id;
1636         u8                              max_phys_tcs_per_port;
1637         bool                            is_first_pf;
1638         u32                             num_pf_cids;
1639         u32                             num_vf_cids;
1640         u32                             num_tids;
1641         u16                             start_pq;
1642         u16                             num_pf_pqs;
1643         u16                             num_vf_pqs;
1644         u8                              start_vport;
1645         u8                              num_vports;
1646         u8                              pf_wfq;
1647         u32                             pf_rl;
1648         struct init_qm_pq_params        *pq_params;
1649         struct init_qm_vport_params     *vport_params;
1650 };
1651
1652 int qed_qm_pf_rt_init(struct qed_hwfn                   *p_hwfn,
1653                       struct qed_ptt                    *p_ptt,
1654                       struct qed_qm_pf_rt_init_params   *p_params);
1655
1656 /**
1657  * @brief qed_init_pf_rl  Initializes the rate limit of the specified PF
1658  *
1659  * @param p_hwfn
1660  * @param p_ptt - ptt window used for writing the registers
1661  * @param pf_id - PF ID
1662  * @param pf_rl - rate limit in Mb/sec units
1663  *
1664  * @return 0 on success, -1 on error.
1665  */
1666 int qed_init_pf_rl(struct qed_hwfn      *p_hwfn,
1667                    struct qed_ptt       *p_ptt,
1668                    u8                   pf_id,
1669                    u32                  pf_rl);
1670
1671 /**
1672  * @brief qed_init_vport_rl  Initializes the rate limit of the specified VPORT
1673  *
1674  * @param p_hwfn
1675  * @param p_ptt         - ptt window used for writing the registers
1676  * @param vport_id      - VPORT ID
1677  * @param vport_rl      - rate limit in Mb/sec units
1678  *
1679  * @return 0 on success, -1 on error.
1680  */
1681
1682 int qed_init_vport_rl(struct qed_hwfn   *p_hwfn,
1683                       struct qed_ptt    *p_ptt,
1684                       u8                vport_id,
1685                       u32               vport_rl);
1686 /**
1687  * @brief qed_send_qm_stop_cmd  Sends a stop command to the QM
1688  *
1689  * @param p_hwfn
1690  * @param p_ptt          - ptt window used for writing the registers
1691  * @param is_release_cmd - true for release, false for stop.
1692  * @param is_tx_pq       - true for Tx PQs, false for Other PQs.
1693  * @param start_pq       - first PQ ID to stop
1694  * @param num_pqs        - Number of PQs to stop, starting from start_pq.
1695  *
1696  * @return bool, true if successful, false if timeout occurred while waiting
1697  *                                      for QM command done.
1698  */
1699
1700 bool qed_send_qm_stop_cmd(struct qed_hwfn       *p_hwfn,
1701                           struct qed_ptt        *p_ptt,
1702                           bool                  is_release_cmd,
1703                           bool                  is_tx_pq,
1704                           u16                   start_pq,
1705                           u16                   num_pqs);
1706
1707 void qed_set_vxlan_dest_port(struct qed_hwfn *p_hwfn,
1708                              struct qed_ptt  *p_ptt, u16 dest_port);
1709 void qed_set_vxlan_enable(struct qed_hwfn *p_hwfn,
1710                           struct qed_ptt *p_ptt, bool vxlan_enable);
1711 void qed_set_gre_enable(struct qed_hwfn *p_hwfn,
1712                         struct qed_ptt  *p_ptt, bool eth_gre_enable,
1713                         bool ip_gre_enable);
1714 void qed_set_geneve_dest_port(struct qed_hwfn *p_hwfn,
1715                               struct qed_ptt *p_ptt, u16 dest_port);
1716 void qed_set_geneve_enable(struct qed_hwfn *p_hwfn,
1717                            struct qed_ptt *p_ptt, bool eth_geneve_enable,
1718                            bool ip_geneve_enable);
1719
1720 /* Ystorm flow control mode. Use enum fw_flow_ctrl_mode */
1721 #define YSTORM_FLOW_CONTROL_MODE_OFFSET  (IRO[0].base)
1722 #define YSTORM_FLOW_CONTROL_MODE_SIZE    (IRO[0].size)
1723 /* Tstorm port statistics */
1724 #define TSTORM_PORT_STAT_OFFSET(port_id) (IRO[1].base + ((port_id) * IRO[1].m1))
1725 #define TSTORM_PORT_STAT_SIZE            (IRO[1].size)
1726 /* Tstorm ll2 port statistics */
1727 #define TSTORM_LL2_PORT_STAT_OFFSET(port_id) \
1728                                 (IRO[2].base + ((port_id) * IRO[2].m1))
1729 #define TSTORM_LL2_PORT_STAT_SIZE            (IRO[2].size)
1730 /* Ustorm VF-PF Channel ready flag */
1731 #define USTORM_VF_PF_CHANNEL_READY_OFFSET(vf_id) \
1732                                 (IRO[3].base +  ((vf_id) * IRO[3].m1))
1733 #define USTORM_VF_PF_CHANNEL_READY_SIZE          (IRO[3].size)
1734 /* Ustorm Final flr cleanup ack */
1735 #define USTORM_FLR_FINAL_ACK_OFFSET(pf_id) (IRO[4].base + ((pf_id) * IRO[4].m1))
1736 #define USTORM_FLR_FINAL_ACK_SIZE          (IRO[4].size)
1737 /* Ustorm Event ring consumer */
1738 #define USTORM_EQE_CONS_OFFSET(pf_id)    (IRO[5].base + ((pf_id) * IRO[5].m1))
1739 #define USTORM_EQE_CONS_SIZE             (IRO[5].size)
1740 /* Ustorm Common Queue ring consumer */
1741 #define USTORM_COMMON_QUEUE_CONS_OFFSET(global_queue_id) \
1742                         (IRO[6].base + ((global_queue_id) * IRO[6].m1))
1743 #define USTORM_COMMON_QUEUE_CONS_SIZE    (IRO[6].size)
1744 /* Xstorm Integration Test Data */
1745 #define XSTORM_INTEG_TEST_DATA_OFFSET    (IRO[7].base)
1746 #define XSTORM_INTEG_TEST_DATA_SIZE      (IRO[7].size)
1747 /* Ystorm Integration Test Data */
1748 #define YSTORM_INTEG_TEST_DATA_OFFSET    (IRO[8].base)
1749 #define YSTORM_INTEG_TEST_DATA_SIZE      (IRO[8].size)
1750 /* Pstorm Integration Test Data */
1751 #define PSTORM_INTEG_TEST_DATA_OFFSET    (IRO[9].base)
1752 #define PSTORM_INTEG_TEST_DATA_SIZE      (IRO[9].size)
1753 /* Tstorm Integration Test Data */
1754 #define TSTORM_INTEG_TEST_DATA_OFFSET    (IRO[10].base)
1755 #define TSTORM_INTEG_TEST_DATA_SIZE      (IRO[10].size)
1756 /* Mstorm Integration Test Data */
1757 #define MSTORM_INTEG_TEST_DATA_OFFSET    (IRO[11].base)
1758 #define MSTORM_INTEG_TEST_DATA_SIZE      (IRO[11].size)
1759 /* Ustorm Integration Test Data */
1760 #define USTORM_INTEG_TEST_DATA_OFFSET    (IRO[12].base)
1761 #define USTORM_INTEG_TEST_DATA_SIZE      (IRO[12].size)
1762 /* Tstorm producers */
1763 #define TSTORM_LL2_RX_PRODS_OFFSET(core_rx_queue_id) \
1764                         (IRO[13].base + ((core_rx_queue_id) * IRO[13].m1))
1765 #define TSTORM_LL2_RX_PRODS_SIZE         (IRO[13].size)
1766 /* Tstorm LightL2 queue statistics */
1767 #define CORE_LL2_TSTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
1768                         (IRO[14].base + ((core_rx_queue_id) * IRO[14].m1))
1769 #define CORE_LL2_TSTORM_PER_QUEUE_STAT_SIZE    (IRO[14].size)
1770 /* Ustorm LiteL2 queue statistics */
1771 #define CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
1772                         (IRO[15].base + ((core_rx_queue_id) * IRO[15].m1))
1773 #define CORE_LL2_USTORM_PER_QUEUE_STAT_SIZE    (IRO[15].size)
1774 /* Pstorm LiteL2 queue statistics */
1775 #define CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(core_tx_stats_id) \
1776                         (IRO[16].base + ((core_tx_stats_id) * IRO[16].m1))
1777 #define CORE_LL2_PSTORM_PER_QUEUE_STAT_SIZE    (IRO[16].size)
1778 /* Mstorm queue statistics */
1779 #define MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
1780                         (IRO[17].base + ((stat_counter_id) * IRO[17].m1))
1781 #define MSTORM_QUEUE_STAT_SIZE                 (IRO[17].size)
1782 /* Mstorm producers */
1783 #define MSTORM_PRODS_OFFSET(queue_id) (IRO[18].base + ((queue_id) * IRO[18].m1))
1784 #define MSTORM_PRODS_SIZE             (IRO[18].size)
1785 /* TPA agregation timeout in us resolution (on ASIC) */
1786 #define MSTORM_TPA_TIMEOUT_US_OFFSET  (IRO[19].base)
1787 #define MSTORM_TPA_TIMEOUT_US_SIZE    (IRO[19].size)
1788 /* Ustorm queue statistics */
1789 #define USTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
1790                         (IRO[20].base + ((stat_counter_id) * IRO[20].m1))
1791 #define USTORM_QUEUE_STAT_SIZE        (IRO[20].size)
1792 /* Ustorm queue zone */
1793 #define USTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) \
1794                         (IRO[21].base + ((queue_id) * IRO[21].m1))
1795 #define USTORM_ETH_QUEUE_ZONE_SIZE    (IRO[21].size)
1796 /* Pstorm queue statistics */
1797 #define PSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
1798                 (IRO[22].base + ((stat_counter_id) * IRO[22].m1))
1799 #define PSTORM_QUEUE_STAT_SIZE        (IRO[22].size)
1800 /* Tstorm last parser message */
1801 #define TSTORM_ETH_PRS_INPUT_OFFSET  (IRO[23].base)
1802 #define TSTORM_ETH_PRS_INPUT_SIZE    (IRO[23].size)
1803 /* Tstorm Eth limit Rx rate */
1804 #define ETH_RX_RATE_LIMIT_OFFSET(pf_id) (IRO[24].base + ((pf_id) * IRO[24].m1))
1805 #define ETH_RX_RATE_LIMIT_SIZE       (IRO[24].size)
1806 /* Ystorm queue zone */
1807 #define YSTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) \
1808                         (IRO[25].base + ((queue_id) * IRO[25].m1))
1809 #define YSTORM_ETH_QUEUE_ZONE_SIZE   (IRO[25].size)
1810 /* Ystorm cqe producer */
1811 #define YSTORM_TOE_CQ_PROD_OFFSET(rss_id) \
1812                         (IRO[26].base + ((rss_id) * IRO[26].m1))
1813 #define YSTORM_TOE_CQ_PROD_SIZE      (IRO[26].size)
1814 /* Ustorm cqe producer */
1815 #define USTORM_TOE_CQ_PROD_OFFSET(rss_id) \
1816                         (IRO[27].base + ((rss_id) * IRO[27].m1))
1817 #define USTORM_TOE_CQ_PROD_SIZE      (IRO[27].size)
1818 /* Ustorm grq producer */
1819 #define USTORM_TOE_GRQ_PROD_OFFSET(pf_id) \
1820                         (IRO[28].base + ((pf_id) * IRO[28].m1))
1821 #define USTORM_TOE_GRQ_PROD_SIZE     (IRO[28].size)
1822 /* Tstorm cmdq-cons of given command queue-id */
1823 #define TSTORM_SCSI_CMDQ_CONS_OFFSET(cmdq_queue_id) \
1824                         (IRO[29].base + ((cmdq_queue_id) * IRO[29].m1))
1825 #define TSTORM_SCSI_CMDQ_CONS_SIZE   (IRO[29].size)
1826 /* Mstorm rq-cons of given queue-id */
1827 #define MSTORM_SCSI_RQ_CONS_OFFSET(rq_queue_id) \
1828                 (IRO[30].base + ((rq_queue_id) * IRO[30].m1))
1829 #define MSTORM_SCSI_RQ_CONS_SIZE     (IRO[30].size)
1830 /* Mstorm bdq-external-producer of given BDQ function ID, BDqueue-id */
1831 #define MSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) \
1832         (IRO[31].base + ((func_id) * IRO[31].m1) + ((bdq_id) * IRO[31].m2))
1833 #define MSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[31].size)
1834 /* Tstorm (reflects M-Storm) bdq-external-producer of given fn ID, BDqueue-id */
1835 #define TSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) \
1836         (IRO[32].base + ((func_id) * IRO[32].m1) + ((bdq_id) * IRO[32].m2))
1837 #define TSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[32].size)
1838 /* Tstorm iSCSI RX stats */
1839 #define TSTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
1840                                 (IRO[33].base + ((pf_id) * IRO[33].m1))
1841 #define TSTORM_ISCSI_RX_STATS_SIZE    (IRO[33].size)
1842 /* Mstorm iSCSI RX stats */
1843 #define MSTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
1844                                 (IRO[34].base + ((pf_id) * IRO[34].m1))
1845 #define MSTORM_ISCSI_RX_STATS_SIZE    (IRO[34].size)
1846 /* Ustorm iSCSI RX stats */
1847 #define USTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
1848                                 (IRO[35].base + ((pf_id) * IRO[35].m1))
1849 #define USTORM_ISCSI_RX_STATS_SIZE    (IRO[35].size)
1850 /* Xstorm iSCSI TX stats */
1851 #define XSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
1852                                 (IRO[36].base + ((pf_id) * IRO[36].m1))
1853 #define XSTORM_ISCSI_TX_STATS_SIZE    (IRO[36].size)
1854 /* Ystorm iSCSI TX stats */
1855 #define YSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
1856                                 (IRO[37].base + ((pf_id) * IRO[37].m1))
1857 #define YSTORM_ISCSI_TX_STATS_SIZE    (IRO[37].size)
1858 /* Pstorm iSCSI TX stats */
1859 #define PSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
1860                                 (IRO[38].base + ((pf_id) * IRO[38].m1))
1861 #define PSTORM_ISCSI_TX_STATS_SIZE    (IRO[38].size)
1862 /* Tstorm FCoE RX stats */
1863 #define TSTORM_FCOE_RX_STATS_OFFSET(pf_id) \
1864                                 (IRO[39].base + ((pf_id) * IRO[39].m1))
1865 #define TSTORM_FCOE_RX_STATS_SIZE      (IRO[39].size)
1866 /* Mstorm FCoE RX stats */
1867 #define MSTORM_FCOE_RX_STATS_OFFSET(pf_id) \
1868                                 (IRO[40].base + ((pf_id) * IRO[40].m1))
1869 #define MSTORM_FCOE_RX_STATS_SIZE      (IRO[40].size)
1870 /* Pstorm FCoE TX stats */
1871 #define PSTORM_FCOE_TX_STATS_OFFSET(pf_id) \
1872                                 (IRO[41].base + ((pf_id) * IRO[41].m1))
1873 #define PSTORM_FCOE_TX_STATS_SIZE      (IRO[41].size)
1874 /* Pstorm RoCE statistics */
1875 #define PSTORM_ROCE_STAT_OFFSET(stat_counter_id) \
1876                         (IRO[42].base + ((stat_counter_id) * IRO[42].m1))
1877 #define PSTORM_ROCE_STAT_SIZE          (IRO[42].size)
1878 /* Tstorm RoCE statistics */
1879 #define TSTORM_ROCE_STAT_OFFSET(stat_counter_id) \
1880                         (IRO[43].base + ((stat_counter_id) * IRO[43].m1))
1881 #define TSTORM_ROCE_STAT_SIZE          (IRO[43].size)
1882
1883 static const struct iro iro_arr[44] = {
1884         { 0x10,    0x0,    0x0,    0x0,    0x8      },
1885         { 0x47c8,  0x60,   0x0,    0x0,    0x60     },
1886         { 0x5e30,  0x20,   0x0,    0x0,    0x20     },
1887         { 0x510,   0x8,    0x0,    0x0,    0x4      },
1888         { 0x490,   0x8,    0x0,    0x0,    0x4      },
1889         { 0x10,    0x8,    0x0,    0x0,    0x2      },
1890         { 0x90,    0x8,    0x0,    0x0,    0x2      },
1891         { 0x4940,  0x0,    0x0,    0x0,    0x78     },
1892         { 0x3de0,  0x0,    0x0,    0x0,    0x78     },
1893         { 0x2998,  0x0,    0x0,    0x0,    0x78     },
1894         { 0x4750,  0x0,    0x0,    0x0,    0x78     },
1895         { 0x56d0,  0x0,    0x0,    0x0,    0x78     },
1896         { 0x7e50,  0x0,    0x0,    0x0,    0x78     },
1897         { 0x100,   0x8,    0x0,    0x0,    0x8      },
1898         { 0x5c10,  0x10,   0x0,    0x0,    0x10     },
1899         { 0xb508,  0x30,   0x0,    0x0,    0x30     },
1900         { 0x95c0,  0x30,   0x0,    0x0,    0x30     },
1901         { 0x58a0,  0x40,   0x0,    0x0,    0x40     },
1902         { 0x200,   0x10,   0x0,    0x0,    0x8      },
1903         { 0xa230,  0x0,    0x0,    0x0,    0x4      },
1904         { 0x8058,  0x40,   0x0,    0x0,    0x30     },
1905         { 0xd00,   0x8,    0x0,    0x0,    0x8      },
1906         { 0x2b30,  0x80,   0x0,    0x0,    0x38     },
1907         { 0xa808,  0x0,    0x0,    0x0,    0xf0     },
1908         { 0xa8f8,  0x8,    0x0,    0x0,    0x8      },
1909         { 0x80,    0x8,    0x0,    0x0,    0x8      },
1910         { 0xac0,   0x8,    0x0,    0x0,    0x8      },
1911         { 0x2580,  0x8,    0x0,    0x0,    0x8      },
1912         { 0x2500,  0x8,    0x0,    0x0,    0x8      },
1913         { 0x440,   0x8,    0x0,    0x0,    0x2      },
1914         { 0x1800,  0x8,    0x0,    0x0,    0x2      },
1915         { 0x1a00,  0x10,   0x8,    0x0,    0x2      },
1916         { 0x640,   0x10,   0x8,    0x0,    0x2      },
1917         { 0xd9b8,  0x38,   0x0,    0x0,    0x24     },
1918         { 0x11048, 0x10,   0x0,    0x0,    0x8      },
1919         { 0x11678, 0x38,   0x0,    0x0,    0x18     },
1920         { 0xaec0,  0x30,   0x0,    0x0,    0x10     },
1921         { 0x8700,  0x28,   0x0,    0x0,    0x18     },
1922         { 0xec00,  0x10,   0x0,    0x0,    0x10     },
1923         { 0xde38,  0x40,   0x0,    0x0,    0x30     },
1924         { 0x121a8, 0x38,   0x0,    0x0,    0x8      },
1925         { 0xf068,  0x20,   0x0,    0x0,    0x20     },
1926         { 0x2b68,  0x80,   0x0,    0x0,    0x10     },
1927         { 0x4ab8,  0x10,   0x0,    0x0,    0x10     },
1928 };
1929
1930 /* Runtime array offsets */
1931 #define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET                                0
1932 #define DORQ_REG_PF_MAX_ICID_1_RT_OFFSET                                1
1933 #define DORQ_REG_PF_MAX_ICID_2_RT_OFFSET                                2
1934 #define DORQ_REG_PF_MAX_ICID_3_RT_OFFSET                                3
1935 #define DORQ_REG_PF_MAX_ICID_4_RT_OFFSET                                4
1936 #define DORQ_REG_PF_MAX_ICID_5_RT_OFFSET                                5
1937 #define DORQ_REG_PF_MAX_ICID_6_RT_OFFSET                                6
1938 #define DORQ_REG_PF_MAX_ICID_7_RT_OFFSET                                7
1939 #define DORQ_REG_VF_MAX_ICID_0_RT_OFFSET                                8
1940 #define DORQ_REG_VF_MAX_ICID_1_RT_OFFSET                                9
1941 #define DORQ_REG_VF_MAX_ICID_2_RT_OFFSET                                10
1942 #define DORQ_REG_VF_MAX_ICID_3_RT_OFFSET                                11
1943 #define DORQ_REG_VF_MAX_ICID_4_RT_OFFSET                                12
1944 #define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET                                13
1945 #define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET                                14
1946 #define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET                                15
1947 #define DORQ_REG_PF_WAKE_ALL_RT_OFFSET                                  16
1948 #define DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET                               17
1949 #define IGU_REG_PF_CONFIGURATION_RT_OFFSET                              18
1950 #define IGU_REG_VF_CONFIGURATION_RT_OFFSET                              19
1951 #define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET                               20
1952 #define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET                               21
1953 #define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET                            22
1954 #define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET                           23
1955 #define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET                             24
1956 #define CAU_REG_SB_VAR_MEMORY_RT_OFFSET                                 761
1957 #define CAU_REG_SB_VAR_MEMORY_RT_SIZE                                   736
1958 #define CAU_REG_SB_VAR_MEMORY_RT_OFFSET                                 761
1959 #define CAU_REG_SB_VAR_MEMORY_RT_SIZE                                   736
1960 #define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET                                1497
1961 #define CAU_REG_SB_ADDR_MEMORY_RT_SIZE                                  736
1962 #define CAU_REG_PI_MEMORY_RT_OFFSET                                     2233
1963 #define CAU_REG_PI_MEMORY_RT_SIZE                                       4416
1964 #define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET                    6649
1965 #define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET                      6650
1966 #define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET                      6651
1967 #define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET                         6652
1968 #define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET                         6653
1969 #define PRS_REG_SEARCH_TCP_RT_OFFSET                                    6654
1970 #define PRS_REG_SEARCH_FCOE_RT_OFFSET                                   6655
1971 #define PRS_REG_SEARCH_ROCE_RT_OFFSET                                   6656
1972 #define PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET                           6657
1973 #define PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET                           6658
1974 #define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET                               6659
1975 #define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET                     6660
1976 #define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET           6661
1977 #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET                      6662
1978 #define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET                               6663
1979 #define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET                         6664
1980 #define SRC_REG_FIRSTFREE_RT_OFFSET                                     6665
1981 #define SRC_REG_FIRSTFREE_RT_SIZE                                       2
1982 #define SRC_REG_LASTFREE_RT_OFFSET                                      6667
1983 #define SRC_REG_LASTFREE_RT_SIZE                                        2
1984 #define SRC_REG_COUNTFREE_RT_OFFSET                                     6669
1985 #define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET                              6670
1986 #define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET                                6671
1987 #define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET                                6672
1988 #define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET                                  6673
1989 #define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET                                  6674
1990 #define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET                                 6675
1991 #define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET                               6676
1992 #define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET                                6677
1993 #define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET                               6678
1994 #define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET                                6679
1995 #define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET                              6680
1996 #define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET                               6681
1997 #define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET                             6682
1998 #define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET                              6683
1999 #define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET                             6684
2000 #define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET                              6685
2001 #define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET                             6686
2002 #define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET                              6687
2003 #define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET                     6688
2004 #define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET                   6689
2005 #define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET                   6690
2006 #define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET                               6691
2007 #define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET                             6692
2008 #define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET                             6693
2009 #define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET                           6694
2010 #define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET                         6695
2011 #define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET                         6696
2012 #define PSWRQ2_REG_VF_BASE_RT_OFFSET                                    6697
2013 #define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET                                6698
2014 #define PSWRQ2_REG_WR_MBS0_RT_OFFSET                                    6699
2015 #define PSWRQ2_REG_RD_MBS0_RT_OFFSET                                    6700
2016 #define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET                              6701
2017 #define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET                              6702
2018 #define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET                                 6703
2019 #define PSWRQ2_REG_ILT_MEMORY_RT_SIZE                                   22000
2020 #define PGLUE_REG_B_VF_BASE_RT_OFFSET                                   28703
2021 #define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET                           28704
2022 #define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET                              28705
2023 #define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET                              28706
2024 #define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET                              28707
2025 #define TM_REG_VF_ENABLE_CONN_RT_OFFSET                                 28708
2026 #define TM_REG_PF_ENABLE_CONN_RT_OFFSET                                 28709
2027 #define TM_REG_PF_ENABLE_TASK_RT_OFFSET                                 28710
2028 #define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET                     28711
2029 #define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET                     28712
2030 #define TM_REG_CONFIG_CONN_MEM_RT_OFFSET                                28713
2031 #define TM_REG_CONFIG_CONN_MEM_RT_SIZE                                  416
2032 #define TM_REG_CONFIG_TASK_MEM_RT_OFFSET                                29129
2033 #define TM_REG_CONFIG_TASK_MEM_RT_SIZE                                  512
2034 #define QM_REG_MAXPQSIZE_0_RT_OFFSET                                    29641
2035 #define QM_REG_MAXPQSIZE_1_RT_OFFSET                                    29642
2036 #define QM_REG_MAXPQSIZE_2_RT_OFFSET                                    29643
2037 #define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET                               29644
2038 #define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET                               29645
2039 #define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET                               29646
2040 #define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET                               29647
2041 #define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET                               29648
2042 #define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET                               29649
2043 #define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET                               29650
2044 #define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET                               29651
2045 #define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET                               29652
2046 #define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET                               29653
2047 #define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET                              29654
2048 #define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET                              29655
2049 #define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET                              29656
2050 #define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET                              29657
2051 #define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET                              29658
2052 #define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET                              29659
2053 #define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET                              29660
2054 #define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET                              29661
2055 #define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET                              29662
2056 #define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET                              29663
2057 #define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET                              29664
2058 #define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET                              29665
2059 #define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET                              29666
2060 #define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET                              29667
2061 #define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET                              29668
2062 #define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET                              29669
2063 #define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET                              29670
2064 #define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET                              29671
2065 #define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET                              29672
2066 #define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET                              29673
2067 #define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET                              29674
2068 #define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET                              29675
2069 #define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET                              29676
2070 #define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET                              29677
2071 #define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET                              29678
2072 #define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET                              29679
2073 #define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET                              29680
2074 #define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET                              29681
2075 #define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET                              29682
2076 #define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET                              29683
2077 #define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET                              29684
2078 #define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET                              29685
2079 #define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET                              29686
2080 #define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET                              29687
2081 #define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET                              29688
2082 #define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET                              29689
2083 #define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET                              29690
2084 #define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET                              29691
2085 #define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET                              29692
2086 #define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET                              29693
2087 #define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET                              29694
2088 #define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET                              29695
2089 #define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET                              29696
2090 #define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET                              29697
2091 #define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET                              29698
2092 #define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET                              29699
2093 #define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET                              29700
2094 #define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET                              29701
2095 #define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET                              29702
2096 #define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET                              29703
2097 #define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET                              29704
2098 #define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET                              29705
2099 #define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET                              29706
2100 #define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET                              29707
2101 #define QM_REG_BASEADDROTHERPQ_RT_OFFSET                                29708
2102 #define QM_REG_BASEADDROTHERPQ_RT_SIZE                                  128
2103 #define QM_REG_VOQCRDLINE_RT_OFFSET                                     29836
2104 #define QM_REG_VOQCRDLINE_RT_SIZE                                       20
2105 #define QM_REG_VOQINITCRDLINE_RT_OFFSET                                 29856
2106 #define QM_REG_VOQINITCRDLINE_RT_SIZE                                   20
2107 #define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET                             29876
2108 #define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET                             29877
2109 #define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET                              29878
2110 #define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET                            29879
2111 #define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET                           29880
2112 #define QM_REG_WRROTHERPQGRP_0_RT_OFFSET                                29881
2113 #define QM_REG_WRROTHERPQGRP_1_RT_OFFSET                                29882
2114 #define QM_REG_WRROTHERPQGRP_2_RT_OFFSET                                29883
2115 #define QM_REG_WRROTHERPQGRP_3_RT_OFFSET                                29884
2116 #define QM_REG_WRROTHERPQGRP_4_RT_OFFSET                                29885
2117 #define QM_REG_WRROTHERPQGRP_5_RT_OFFSET                                29886
2118 #define QM_REG_WRROTHERPQGRP_6_RT_OFFSET                                29887
2119 #define QM_REG_WRROTHERPQGRP_7_RT_OFFSET                                29888
2120 #define QM_REG_WRROTHERPQGRP_8_RT_OFFSET                                29889
2121 #define QM_REG_WRROTHERPQGRP_9_RT_OFFSET                                29890
2122 #define QM_REG_WRROTHERPQGRP_10_RT_OFFSET                               29891
2123 #define QM_REG_WRROTHERPQGRP_11_RT_OFFSET                               29892
2124 #define QM_REG_WRROTHERPQGRP_12_RT_OFFSET                               29893
2125 #define QM_REG_WRROTHERPQGRP_13_RT_OFFSET                               29894
2126 #define QM_REG_WRROTHERPQGRP_14_RT_OFFSET                               29895
2127 #define QM_REG_WRROTHERPQGRP_15_RT_OFFSET                               29896
2128 #define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET                            29897
2129 #define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET                            29898
2130 #define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET                            29899
2131 #define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET                            29900
2132 #define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET                               29901
2133 #define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET                               29902
2134 #define QM_REG_PQTX2PF_0_RT_OFFSET                                      29903
2135 #define QM_REG_PQTX2PF_1_RT_OFFSET                                      29904
2136 #define QM_REG_PQTX2PF_2_RT_OFFSET                                      29905
2137 #define QM_REG_PQTX2PF_3_RT_OFFSET                                      29906
2138 #define QM_REG_PQTX2PF_4_RT_OFFSET                                      29907
2139 #define QM_REG_PQTX2PF_5_RT_OFFSET                                      29908
2140 #define QM_REG_PQTX2PF_6_RT_OFFSET                                      29909
2141 #define QM_REG_PQTX2PF_7_RT_OFFSET                                      29910
2142 #define QM_REG_PQTX2PF_8_RT_OFFSET                                      29911
2143 #define QM_REG_PQTX2PF_9_RT_OFFSET                                      29912
2144 #define QM_REG_PQTX2PF_10_RT_OFFSET                                     29913
2145 #define QM_REG_PQTX2PF_11_RT_OFFSET                                     29914
2146 #define QM_REG_PQTX2PF_12_RT_OFFSET                                     29915
2147 #define QM_REG_PQTX2PF_13_RT_OFFSET                                     29916
2148 #define QM_REG_PQTX2PF_14_RT_OFFSET                                     29917
2149 #define QM_REG_PQTX2PF_15_RT_OFFSET                                     29918
2150 #define QM_REG_PQTX2PF_16_RT_OFFSET                                     29919
2151 #define QM_REG_PQTX2PF_17_RT_OFFSET                                     29920
2152 #define QM_REG_PQTX2PF_18_RT_OFFSET                                     29921
2153 #define QM_REG_PQTX2PF_19_RT_OFFSET                                     29922
2154 #define QM_REG_PQTX2PF_20_RT_OFFSET                                     29923
2155 #define QM_REG_PQTX2PF_21_RT_OFFSET                                     29924
2156 #define QM_REG_PQTX2PF_22_RT_OFFSET                                     29925
2157 #define QM_REG_PQTX2PF_23_RT_OFFSET                                     29926
2158 #define QM_REG_PQTX2PF_24_RT_OFFSET                                     29927
2159 #define QM_REG_PQTX2PF_25_RT_OFFSET                                     29928
2160 #define QM_REG_PQTX2PF_26_RT_OFFSET                                     29929
2161 #define QM_REG_PQTX2PF_27_RT_OFFSET                                     29930
2162 #define QM_REG_PQTX2PF_28_RT_OFFSET                                     29931
2163 #define QM_REG_PQTX2PF_29_RT_OFFSET                                     29932
2164 #define QM_REG_PQTX2PF_30_RT_OFFSET                                     29933
2165 #define QM_REG_PQTX2PF_31_RT_OFFSET                                     29934
2166 #define QM_REG_PQTX2PF_32_RT_OFFSET                                     29935
2167 #define QM_REG_PQTX2PF_33_RT_OFFSET                                     29936
2168 #define QM_REG_PQTX2PF_34_RT_OFFSET                                     29937
2169 #define QM_REG_PQTX2PF_35_RT_OFFSET                                     29938
2170 #define QM_REG_PQTX2PF_36_RT_OFFSET                                     29939
2171 #define QM_REG_PQTX2PF_37_RT_OFFSET                                     29940
2172 #define QM_REG_PQTX2PF_38_RT_OFFSET                                     29941
2173 #define QM_REG_PQTX2PF_39_RT_OFFSET                                     29942
2174 #define QM_REG_PQTX2PF_40_RT_OFFSET                                     29943
2175 #define QM_REG_PQTX2PF_41_RT_OFFSET                                     29944
2176 #define QM_REG_PQTX2PF_42_RT_OFFSET                                     29945
2177 #define QM_REG_PQTX2PF_43_RT_OFFSET                                     29946
2178 #define QM_REG_PQTX2PF_44_RT_OFFSET                                     29947
2179 #define QM_REG_PQTX2PF_45_RT_OFFSET                                     29948
2180 #define QM_REG_PQTX2PF_46_RT_OFFSET                                     29949
2181 #define QM_REG_PQTX2PF_47_RT_OFFSET                                     29950
2182 #define QM_REG_PQTX2PF_48_RT_OFFSET                                     29951
2183 #define QM_REG_PQTX2PF_49_RT_OFFSET                                     29952
2184 #define QM_REG_PQTX2PF_50_RT_OFFSET                                     29953
2185 #define QM_REG_PQTX2PF_51_RT_OFFSET                                     29954
2186 #define QM_REG_PQTX2PF_52_RT_OFFSET                                     29955
2187 #define QM_REG_PQTX2PF_53_RT_OFFSET                                     29956
2188 #define QM_REG_PQTX2PF_54_RT_OFFSET                                     29957
2189 #define QM_REG_PQTX2PF_55_RT_OFFSET                                     29958
2190 #define QM_REG_PQTX2PF_56_RT_OFFSET                                     29959
2191 #define QM_REG_PQTX2PF_57_RT_OFFSET                                     29960
2192 #define QM_REG_PQTX2PF_58_RT_OFFSET                                     29961
2193 #define QM_REG_PQTX2PF_59_RT_OFFSET                                     29962
2194 #define QM_REG_PQTX2PF_60_RT_OFFSET                                     29963
2195 #define QM_REG_PQTX2PF_61_RT_OFFSET                                     29964
2196 #define QM_REG_PQTX2PF_62_RT_OFFSET                                     29965
2197 #define QM_REG_PQTX2PF_63_RT_OFFSET                                     29966
2198 #define QM_REG_PQOTHER2PF_0_RT_OFFSET                                   29967
2199 #define QM_REG_PQOTHER2PF_1_RT_OFFSET                                   29968
2200 #define QM_REG_PQOTHER2PF_2_RT_OFFSET                                   29969
2201 #define QM_REG_PQOTHER2PF_3_RT_OFFSET                                   29970
2202 #define QM_REG_PQOTHER2PF_4_RT_OFFSET                                   29971
2203 #define QM_REG_PQOTHER2PF_5_RT_OFFSET                                   29972
2204 #define QM_REG_PQOTHER2PF_6_RT_OFFSET                                   29973
2205 #define QM_REG_PQOTHER2PF_7_RT_OFFSET                                   29974
2206 #define QM_REG_PQOTHER2PF_8_RT_OFFSET                                   29975
2207 #define QM_REG_PQOTHER2PF_9_RT_OFFSET                                   29976
2208 #define QM_REG_PQOTHER2PF_10_RT_OFFSET                                  29977
2209 #define QM_REG_PQOTHER2PF_11_RT_OFFSET                                  29978
2210 #define QM_REG_PQOTHER2PF_12_RT_OFFSET                                  29979
2211 #define QM_REG_PQOTHER2PF_13_RT_OFFSET                                  29980
2212 #define QM_REG_PQOTHER2PF_14_RT_OFFSET                                  29981
2213 #define QM_REG_PQOTHER2PF_15_RT_OFFSET                                  29982
2214 #define QM_REG_RLGLBLPERIOD_0_RT_OFFSET                                 29983
2215 #define QM_REG_RLGLBLPERIOD_1_RT_OFFSET                                 29984
2216 #define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET                            29985
2217 #define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET                            29986
2218 #define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET                              29987
2219 #define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET                              29988
2220 #define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET                              29989
2221 #define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET                              29990
2222 #define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET                              29991
2223 #define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET                              29992
2224 #define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET                              29993
2225 #define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET                              29994
2226 #define QM_REG_RLGLBLINCVAL_RT_OFFSET                                   29995
2227 #define QM_REG_RLGLBLINCVAL_RT_SIZE                                     256
2228 #define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET                               30251
2229 #define QM_REG_RLGLBLUPPERBOUND_RT_SIZE                                 256
2230 #define QM_REG_RLGLBLCRD_RT_OFFSET                                      30507
2231 #define QM_REG_RLGLBLCRD_RT_SIZE                                        256
2232 #define QM_REG_RLGLBLENABLE_RT_OFFSET                                   30763
2233 #define QM_REG_RLPFPERIOD_RT_OFFSET                                     30764
2234 #define QM_REG_RLPFPERIODTIMER_RT_OFFSET                                30765
2235 #define QM_REG_RLPFINCVAL_RT_OFFSET                                     30766
2236 #define QM_REG_RLPFINCVAL_RT_SIZE                                       16
2237 #define QM_REG_RLPFUPPERBOUND_RT_OFFSET                                 30782
2238 #define QM_REG_RLPFUPPERBOUND_RT_SIZE                                   16
2239 #define QM_REG_RLPFCRD_RT_OFFSET                                        30798
2240 #define QM_REG_RLPFCRD_RT_SIZE                                          16
2241 #define QM_REG_RLPFENABLE_RT_OFFSET                                     30814
2242 #define QM_REG_RLPFVOQENABLE_RT_OFFSET                                  30815
2243 #define QM_REG_WFQPFWEIGHT_RT_OFFSET                                    30816
2244 #define QM_REG_WFQPFWEIGHT_RT_SIZE                                      16
2245 #define QM_REG_WFQPFUPPERBOUND_RT_OFFSET                                30832
2246 #define QM_REG_WFQPFUPPERBOUND_RT_SIZE                                  16
2247 #define QM_REG_WFQPFCRD_RT_OFFSET                                       30848
2248 #define QM_REG_WFQPFCRD_RT_SIZE                                         160
2249 #define QM_REG_WFQPFENABLE_RT_OFFSET                                    31008
2250 #define QM_REG_WFQVPENABLE_RT_OFFSET                                    31009
2251 #define QM_REG_BASEADDRTXPQ_RT_OFFSET                                   31010
2252 #define QM_REG_BASEADDRTXPQ_RT_SIZE                                     512
2253 #define QM_REG_TXPQMAP_RT_OFFSET                                        31522
2254 #define QM_REG_TXPQMAP_RT_SIZE                                          512
2255 #define QM_REG_WFQVPWEIGHT_RT_OFFSET                                    32034
2256 #define QM_REG_WFQVPWEIGHT_RT_SIZE                                      512
2257 #define QM_REG_WFQVPCRD_RT_OFFSET                                       32546
2258 #define QM_REG_WFQVPCRD_RT_SIZE                                         512
2259 #define QM_REG_WFQVPMAP_RT_OFFSET                                       33058
2260 #define QM_REG_WFQVPMAP_RT_SIZE                                         512
2261 #define QM_REG_WFQPFCRD_MSB_RT_OFFSET                                   33570
2262 #define QM_REG_WFQPFCRD_MSB_RT_SIZE                                     160
2263 #define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET                               33730
2264 #define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET                         33731
2265 #define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET                         33732
2266 #define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET                         33733
2267 #define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET                         33734
2268 #define NIG_REG_OUTER_TAG_VALUE_MASK_RT_OFFSET                          33735
2269 #define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET                      33736
2270 #define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET                               33737
2271 #define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE                                 4
2272 #define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_OFFSET                          33741
2273 #define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_SIZE                            4
2274 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET                            33745
2275 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE                              4
2276 #define NIG_REG_LLH_FUNC_NO_TAG_RT_OFFSET                               33749
2277 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET                         33750
2278 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE                           32
2279 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET                            33782
2280 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE                              16
2281 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET                          33798
2282 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE                            16
2283 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET                 33814
2284 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE                   16
2285 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET                       33830
2286 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE                         16
2287 #define NIG_REG_TX_EDPM_CTRL_RT_OFFSET                                  33846
2288 #define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET                               33847
2289 #define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET                               33848
2290 #define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET                               33849
2291 #define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET                           33850
2292 #define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET                           33851
2293 #define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET                           33852
2294 #define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET                           33853
2295 #define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET                        33854
2296 #define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET                        33855
2297 #define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET                        33856
2298 #define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET                        33857
2299 #define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET                            33858
2300 #define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET                         33859
2301 #define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET                               33860
2302 #define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET                          33861
2303 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET                        33862
2304 #define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET                           33863
2305 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET                    33864
2306 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET                        33865
2307 #define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET                           33866
2308 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET                    33867
2309 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET                        33868
2310 #define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET                           33869
2311 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET                    33870
2312 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET                        33871
2313 #define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET                           33872
2314 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET                    33873
2315 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET                        33874
2316 #define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET                           33875
2317 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET                    33876
2318 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET                        33877
2319 #define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET                           33878
2320 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET                    33879
2321 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET                        33880
2322 #define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET                           33881
2323 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET                    33882
2324 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET                        33883
2325 #define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET                           33884
2326 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET                    33885
2327 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET                        33886
2328 #define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET                           33887
2329 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET                    33888
2330 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET                        33889
2331 #define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET                           33890
2332 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET                    33891
2333 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET                       33892
2334 #define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET                          33893
2335 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET                   33894
2336 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET                       33895
2337 #define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET                          33896
2338 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET                   33897
2339 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET                       33898
2340 #define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET                          33899
2341 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET                   33900
2342 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET                       33901
2343 #define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET                          33902
2344 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET                   33903
2345 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET                       33904
2346 #define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET                          33905
2347 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET                   33906
2348 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET                       33907
2349 #define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET                          33908
2350 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET                   33909
2351 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET                       33910
2352 #define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET                          33911
2353 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET                   33912
2354 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET                       33913
2355 #define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET                          33914
2356 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET                   33915
2357 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET                       33916
2358 #define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET                          33917
2359 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET                   33918
2360 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET                       33919
2361 #define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET                          33920
2362 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET                   33921
2363 #define XCM_REG_CON_PHY_Q3_RT_OFFSET                                    33922
2364
2365 #define RUNTIME_ARRAY_SIZE 33923
2366
2367 /* The eth storm context for the Tstorm */
2368 struct tstorm_eth_conn_st_ctx {
2369         __le32 reserved[4];
2370 };
2371
2372 /* The eth storm context for the Pstorm */
2373 struct pstorm_eth_conn_st_ctx {
2374         __le32 reserved[8];
2375 };
2376
2377 /* The eth storm context for the Xstorm */
2378 struct xstorm_eth_conn_st_ctx {
2379         __le32 reserved[60];
2380 };
2381
2382 struct xstorm_eth_conn_ag_ctx {
2383         u8      reserved0 /* cdu_validation */;
2384         u8      eth_state /* state */;
2385         u8      flags0;
2386 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK            0x1
2387 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT           0
2388 #define XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK               0x1
2389 #define XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT              1
2390 #define XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK               0x1
2391 #define XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT              2
2392 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK            0x1
2393 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT           3
2394 #define XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK               0x1 /* bit4 */
2395 #define XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT              4
2396 #define XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK               0x1
2397 #define XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT              5
2398 #define XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK               0x1 /* bit6 */
2399 #define XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT              6
2400 #define XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK               0x1 /* bit7 */
2401 #define XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT              7
2402         u8 flags1;
2403 #define XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK               0x1 /* bit8 */
2404 #define XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT              0
2405 #define XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK               0x1 /* bit9 */
2406 #define XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT              1
2407 #define XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK               0x1 /* bit10 */
2408 #define XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT              2
2409 #define XSTORM_ETH_CONN_AG_CTX_BIT11_MASK                   0x1 /* bit11 */
2410 #define XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT                  3
2411 #define XSTORM_ETH_CONN_AG_CTX_BIT12_MASK                   0x1 /* bit12 */
2412 #define XSTORM_ETH_CONN_AG_CTX_BIT12_SHIFT                  4
2413 #define XSTORM_ETH_CONN_AG_CTX_BIT13_MASK                   0x1 /* bit13 */
2414 #define XSTORM_ETH_CONN_AG_CTX_BIT13_SHIFT                  5
2415 #define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK          0x1 /* bit14 */
2416 #define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT         6
2417 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK            0x1 /* bit15 */
2418 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT           7
2419         u8 flags2;
2420 #define XSTORM_ETH_CONN_AG_CTX_CF0_MASK                     0x3 /* timer0cf */
2421 #define XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT                    0
2422 #define XSTORM_ETH_CONN_AG_CTX_CF1_MASK                     0x3 /* timer1cf */
2423 #define XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT                    2
2424 #define XSTORM_ETH_CONN_AG_CTX_CF2_MASK                     0x3 /* timer2cf */
2425 #define XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT                    4
2426 #define XSTORM_ETH_CONN_AG_CTX_CF3_MASK                     0x3
2427 #define XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT                    6
2428         u8 flags3;
2429 #define XSTORM_ETH_CONN_AG_CTX_CF4_MASK                     0x3 /* cf4 */
2430 #define XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT                    0
2431 #define XSTORM_ETH_CONN_AG_CTX_CF5_MASK                     0x3 /* cf5 */
2432 #define XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT                    2
2433 #define XSTORM_ETH_CONN_AG_CTX_CF6_MASK                     0x3 /* cf6 */
2434 #define XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT                    4
2435 #define XSTORM_ETH_CONN_AG_CTX_CF7_MASK                     0x3 /* cf7 */
2436 #define XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT                    6
2437         u8 flags4;
2438 #define XSTORM_ETH_CONN_AG_CTX_CF8_MASK                     0x3 /* cf8 */
2439 #define XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT                    0
2440 #define XSTORM_ETH_CONN_AG_CTX_CF9_MASK                     0x3 /* cf9 */
2441 #define XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT                    2
2442 #define XSTORM_ETH_CONN_AG_CTX_CF10_MASK                    0x3 /* cf10 */
2443 #define XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT                   4
2444 #define XSTORM_ETH_CONN_AG_CTX_CF11_MASK                    0x3 /* cf11 */
2445 #define XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT                   6
2446         u8 flags5;
2447 #define XSTORM_ETH_CONN_AG_CTX_CF12_MASK                    0x3 /* cf12 */
2448 #define XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT                   0
2449 #define XSTORM_ETH_CONN_AG_CTX_CF13_MASK                    0x3 /* cf13 */
2450 #define XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT                   2
2451 #define XSTORM_ETH_CONN_AG_CTX_CF14_MASK                    0x3 /* cf14 */
2452 #define XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT                   4
2453 #define XSTORM_ETH_CONN_AG_CTX_CF15_MASK                    0x3 /* cf15 */
2454 #define XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT                   6
2455         u8 flags6;
2456 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK        0x3 /* cf16 */
2457 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT       0
2458 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK        0x3
2459 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT       2
2460 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK                   0x3 /* cf18 */
2461 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT                  4
2462 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK            0x3 /* cf19 */
2463 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT           6
2464         u8 flags7;
2465 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK                0x3 /* cf20 */
2466 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT               0
2467 #define XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK              0x3 /* cf21 */
2468 #define XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT             2
2469 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK               0x3 /* cf22 */
2470 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT              4
2471 #define XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK                   0x1 /* cf0en */
2472 #define XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT                  6
2473 #define XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK                   0x1 /* cf1en */
2474 #define XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT                  7
2475         u8 flags8;
2476 #define XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK                   0x1 /* cf2en */
2477 #define XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT                  0
2478 #define XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK                   0x1 /* cf3en */
2479 #define XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT                  1
2480 #define XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK                   0x1 /* cf4en */
2481 #define XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT                  2
2482 #define XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK                   0x1 /* cf5en */
2483 #define XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT                  3
2484 #define XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK                   0x1 /* cf6en */
2485 #define XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT                  4
2486 #define XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK                   0x1 /* cf7en */
2487 #define XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT                  5
2488 #define XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK                   0x1 /* cf8en */
2489 #define XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT                  6
2490 #define XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK                   0x1 /* cf9en */
2491 #define XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT                  7
2492         u8 flags9;
2493 #define XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK                  0x1 /* cf10en */
2494 #define XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT                 0
2495 #define XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK                  0x1 /* cf11en */
2496 #define XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT                 1
2497 #define XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK                  0x1 /* cf12en */
2498 #define XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT                 2
2499 #define XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK                  0x1 /* cf13en */
2500 #define XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT                 3
2501 #define XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK                  0x1 /* cf14en */
2502 #define XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT                 4
2503 #define XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK                  0x1 /* cf15en */
2504 #define XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT                 5
2505 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK     0x1 /* cf16en */
2506 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT    6
2507 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK     0x1
2508 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT    7
2509         u8 flags10;
2510 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK                0x1 /* cf18en */
2511 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT               0
2512 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK         0x1 /* cf19en */
2513 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT        1
2514 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK             0x1 /* cf20en */
2515 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT            2
2516 #define XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK              0x1 /* cf21en */
2517 #define XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT             3
2518 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK            0x1 /* cf22en */
2519 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT           4
2520 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK  0x1 /* cf23en */
2521 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
2522 #define XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK              0x1 /* rule0en */
2523 #define XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT             6
2524 #define XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK              0x1 /* rule1en */
2525 #define XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT             7
2526         u8 flags11;
2527 #define XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK              0x1 /* rule2en */
2528 #define XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT             0
2529 #define XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK              0x1 /* rule3en */
2530 #define XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT             1
2531 #define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK          0x1 /* rule4en */
2532 #define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT         2
2533 #define XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK                 0x1 /* rule5en */
2534 #define XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT                3
2535 #define XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK                 0x1 /* rule6en */
2536 #define XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT                4
2537 #define XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK                 0x1 /* rule7en */
2538 #define XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT                5
2539 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK            0x1 /* rule8en */
2540 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT           6
2541 #define XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK                 0x1 /* rule9en */
2542 #define XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT                7
2543         u8 flags12;
2544 #define XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK                0x1 /* rule10en */
2545 #define XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT               0
2546 #define XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK                0x1 /* rule11en */
2547 #define XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT               1
2548 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK            0x1 /* rule12en */
2549 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT           2
2550 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK            0x1 /* rule13en */
2551 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT           3
2552 #define XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK                0x1 /* rule14en */
2553 #define XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT               4
2554 #define XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK                0x1 /* rule15en */
2555 #define XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT               5
2556 #define XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK                0x1 /* rule16en */
2557 #define XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT               6
2558 #define XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK                0x1 /* rule17en */
2559 #define XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT               7
2560         u8 flags13;
2561 #define XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK                0x1 /* rule18en */
2562 #define XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT               0
2563 #define XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK                0x1 /* rule19en */
2564 #define XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT               1
2565 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK            0x1 /* rule20en */
2566 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT           2
2567 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK            0x1 /* rule21en */
2568 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT           3
2569 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK            0x1 /* rule22en */
2570 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT           4
2571 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK            0x1 /* rule23en */
2572 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT           5
2573 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK            0x1 /* rule24en */
2574 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT           6
2575 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK            0x1 /* rule25en */
2576 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT           7
2577         u8 flags14;
2578 #define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK        0x1 /* bit16 */
2579 #define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT       0
2580 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK      0x1 /* bit17 */
2581 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT     1
2582 #define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK    0x1 /* bit18 */
2583 #define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT   2
2584 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK    0x1 /* bit19 */
2585 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT   3
2586 #define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK          0x1 /* bit20 */
2587 #define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT         4
2588 #define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK        0x1 /* bit21 */
2589 #define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT       5
2590 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK              0x3 /* cf23 */
2591 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT             6
2592         u8      edpm_event_id /* byte2 */;
2593         __le16  physical_q0 /* physical_q0 */;
2594         __le16  word1 /* physical_q1 */;
2595         __le16  edpm_num_bds /* physical_q2 */;
2596         __le16  tx_bd_cons /* word3 */;
2597         __le16  tx_bd_prod /* word4 */;
2598         __le16  go_to_bd_cons /* word5 */;
2599         __le16  conn_dpi /* conn_dpi */;
2600         u8      byte3 /* byte3 */;
2601         u8      byte4 /* byte4 */;
2602         u8      byte5 /* byte5 */;
2603         u8      byte6 /* byte6 */;
2604         __le32  reg0 /* reg0 */;
2605         __le32  reg1 /* reg1 */;
2606         __le32  reg2 /* reg2 */;
2607         __le32  reg3 /* reg3 */;
2608         __le32  reg4 /* reg4 */;
2609         __le32  reg5 /* cf_array0 */;
2610         __le32  reg6 /* cf_array1 */;
2611         __le16  word7 /* word7 */;
2612         __le16  word8 /* word8 */;
2613         __le16  word9 /* word9 */;
2614         __le16  word10 /* word10 */;
2615         __le32  reg7 /* reg7 */;
2616         __le32  reg8 /* reg8 */;
2617         __le32  reg9 /* reg9 */;
2618         u8      byte7 /* byte7 */;
2619         u8      byte8 /* byte8 */;
2620         u8      byte9 /* byte9 */;
2621         u8      byte10 /* byte10 */;
2622         u8      byte11 /* byte11 */;
2623         u8      byte12 /* byte12 */;
2624         u8      byte13 /* byte13 */;
2625         u8      byte14 /* byte14 */;
2626         u8      byte15 /* byte15 */;
2627         u8      byte16 /* byte16 */;
2628         __le16  word11 /* word11 */;
2629         __le32  reg10 /* reg10 */;
2630         __le32  reg11 /* reg11 */;
2631         __le32  reg12 /* reg12 */;
2632         __le32  reg13 /* reg13 */;
2633         __le32  reg14 /* reg14 */;
2634         __le32  reg15 /* reg15 */;
2635         __le32  reg16 /* reg16 */;
2636         __le32  reg17 /* reg17 */;
2637         __le32  reg18 /* reg18 */;
2638         __le32  reg19 /* reg19 */;
2639         __le16  word12 /* word12 */;
2640         __le16  word13 /* word13 */;
2641         __le16  word14 /* word14 */;
2642         __le16  word15 /* word15 */;
2643 };
2644
2645 /* The eth storm context for the Ystorm */
2646 struct ystorm_eth_conn_st_ctx {
2647         __le32 reserved[8];
2648 };
2649
2650 struct ystorm_eth_conn_ag_ctx {
2651         u8      byte0 /* cdu_validation */;
2652         u8      byte1 /* state */;
2653         u8      flags0;
2654 #define YSTORM_ETH_CONN_AG_CTX_BIT0_MASK                  0x1 /* exist_in_qm0 */
2655 #define YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT                 0
2656 #define YSTORM_ETH_CONN_AG_CTX_BIT1_MASK                  0x1 /* exist_in_qm1 */
2657 #define YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT                 1
2658 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK     0x3   /* cf0 */
2659 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT    2
2660 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK      0x3   /* cf1 */
2661 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT     4
2662 #define YSTORM_ETH_CONN_AG_CTX_CF2_MASK                   0x3   /* cf2 */
2663 #define YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT                  6
2664         u8 flags1;
2665 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK  0x1   /* cf0en */
2666 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 0
2667 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK   0x1   /* cf1en */
2668 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT  1
2669 #define YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK                 0x1   /* cf2en */
2670 #define YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT                2
2671 #define YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK               0x1   /* rule0en */
2672 #define YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT              3
2673 #define YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK               0x1   /* rule1en */
2674 #define YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT              4
2675 #define YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK               0x1   /* rule2en */
2676 #define YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT              5
2677 #define YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK               0x1   /* rule3en */
2678 #define YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT              6
2679 #define YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK               0x1   /* rule4en */
2680 #define YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT              7
2681         u8      byte2 /* byte2 */;
2682         u8      byte3 /* byte3 */;
2683         __le16  word0 /* word0 */;
2684         __le32  terminate_spqe /* reg0 */;
2685         __le32  reg1 /* reg1 */;
2686         __le16  tx_bd_cons_upd /* word1 */;
2687         __le16  word2 /* word2 */;
2688         __le16  word3 /* word3 */;
2689         __le16  word4 /* word4 */;
2690         __le32  reg2 /* reg2 */;
2691         __le32  reg3 /* reg3 */;
2692 };
2693
2694 struct tstorm_eth_conn_ag_ctx {
2695         u8      byte0 /* cdu_validation */;
2696         u8      byte1 /* state */;
2697         u8      flags0;
2698 #define TSTORM_ETH_CONN_AG_CTX_BIT0_MASK      0x1       /* exist_in_qm0 */
2699 #define TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT     0
2700 #define TSTORM_ETH_CONN_AG_CTX_BIT1_MASK      0x1       /* exist_in_qm1 */
2701 #define TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT     1
2702 #define TSTORM_ETH_CONN_AG_CTX_BIT2_MASK      0x1       /* bit2 */
2703 #define TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT     2
2704 #define TSTORM_ETH_CONN_AG_CTX_BIT3_MASK      0x1       /* bit3 */
2705 #define TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT     3
2706 #define TSTORM_ETH_CONN_AG_CTX_BIT4_MASK      0x1       /* bit4 */
2707 #define TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT     4
2708 #define TSTORM_ETH_CONN_AG_CTX_BIT5_MASK      0x1       /* bit5 */
2709 #define TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT     5
2710 #define TSTORM_ETH_CONN_AG_CTX_CF0_MASK       0x3       /* timer0cf */
2711 #define TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT      6
2712         u8 flags1;
2713 #define TSTORM_ETH_CONN_AG_CTX_CF1_MASK       0x3       /* timer1cf */
2714 #define TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT      0
2715 #define TSTORM_ETH_CONN_AG_CTX_CF2_MASK       0x3       /* timer2cf */
2716 #define TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT      2
2717 #define TSTORM_ETH_CONN_AG_CTX_CF3_MASK       0x3       /* timer_stop_all */
2718 #define TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT      4
2719 #define TSTORM_ETH_CONN_AG_CTX_CF4_MASK       0x3       /* cf4 */
2720 #define TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT      6
2721         u8 flags2;
2722 #define TSTORM_ETH_CONN_AG_CTX_CF5_MASK       0x3       /* cf5 */
2723 #define TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT      0
2724 #define TSTORM_ETH_CONN_AG_CTX_CF6_MASK       0x3       /* cf6 */
2725 #define TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT      2
2726 #define TSTORM_ETH_CONN_AG_CTX_CF7_MASK       0x3       /* cf7 */
2727 #define TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT      4
2728 #define TSTORM_ETH_CONN_AG_CTX_CF8_MASK       0x3       /* cf8 */
2729 #define TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT      6
2730         u8 flags3;
2731 #define TSTORM_ETH_CONN_AG_CTX_CF9_MASK       0x3       /* cf9 */
2732 #define TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT      0
2733 #define TSTORM_ETH_CONN_AG_CTX_CF10_MASK      0x3       /* cf10 */
2734 #define TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT     2
2735 #define TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK     0x1       /* cf0en */
2736 #define TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT    4
2737 #define TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK     0x1       /* cf1en */
2738 #define TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT    5
2739 #define TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK     0x1       /* cf2en */
2740 #define TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT    6
2741 #define TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK     0x1       /* cf3en */
2742 #define TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT    7
2743         u8 flags4;
2744 #define TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK     0x1       /* cf4en */
2745 #define TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT    0
2746 #define TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK     0x1       /* cf5en */
2747 #define TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT    1
2748 #define TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK     0x1       /* cf6en */
2749 #define TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT    2
2750 #define TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK     0x1       /* cf7en */
2751 #define TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT    3
2752 #define TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK     0x1       /* cf8en */
2753 #define TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT    4
2754 #define TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK     0x1       /* cf9en */
2755 #define TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT    5
2756 #define TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK    0x1       /* cf10en */
2757 #define TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT   6
2758 #define TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK   0x1       /* rule0en */
2759 #define TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT  7
2760         u8 flags5;
2761 #define TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK   0x1       /* rule1en */
2762 #define TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT  0
2763 #define TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK   0x1       /* rule2en */
2764 #define TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT  1
2765 #define TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK   0x1       /* rule3en */
2766 #define TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT  2
2767 #define TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK   0x1       /* rule4en */
2768 #define TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT  3
2769 #define TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK   0x1       /* rule5en */
2770 #define TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT  4
2771 #define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK  0x1       /* rule6en */
2772 #define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5
2773 #define TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK   0x1       /* rule7en */
2774 #define TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT  6
2775 #define TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK   0x1       /* rule8en */
2776 #define TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT  7
2777         __le32  reg0 /* reg0 */;
2778         __le32  reg1 /* reg1 */;
2779         __le32  reg2 /* reg2 */;
2780         __le32  reg3 /* reg3 */;
2781         __le32  reg4 /* reg4 */;
2782         __le32  reg5 /* reg5 */;
2783         __le32  reg6 /* reg6 */;
2784         __le32  reg7 /* reg7 */;
2785         __le32  reg8 /* reg8 */;
2786         u8      byte2 /* byte2 */;
2787         u8      byte3 /* byte3 */;
2788         __le16  rx_bd_cons /* word0 */;
2789         u8      byte4 /* byte4 */;
2790         u8      byte5 /* byte5 */;
2791         __le16  rx_bd_prod /* word1 */;
2792         __le16  word2 /* conn_dpi */;
2793         __le16  word3 /* word3 */;
2794         __le32  reg9 /* reg9 */;
2795         __le32  reg10 /* reg10 */;
2796 };
2797
2798 struct ustorm_eth_conn_ag_ctx {
2799         u8      byte0 /* cdu_validation */;
2800         u8      byte1 /* state */;
2801         u8      flags0;
2802 #define USTORM_ETH_CONN_AG_CTX_BIT0_MASK                  0x1 /* exist_in_qm0 */
2803 #define USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT                 0
2804 #define USTORM_ETH_CONN_AG_CTX_BIT1_MASK                  0x1 /* exist_in_qm1 */
2805 #define USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT                 1
2806 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK   0x3 /* timer0cf */
2807 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT  2
2808 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK   0x3 /* timer1cf */
2809 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT  4
2810 #define USTORM_ETH_CONN_AG_CTX_CF2_MASK                   0x3 /* timer2cf */
2811 #define USTORM_ETH_CONN_AG_CTX_CF2_SHIFT                  6
2812         u8 flags1;
2813 #define USTORM_ETH_CONN_AG_CTX_CF3_MASK                 0x3 /* timer_stop_all */
2814 #define USTORM_ETH_CONN_AG_CTX_CF3_SHIFT                0
2815 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK           0x3 /* cf4 */
2816 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT          2
2817 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK           0x3 /* cf5 */
2818 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT          4
2819 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK   0x3 /* cf6 */
2820 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT  6
2821         u8 flags2;
2822 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK  0x1 /* cf0en */
2823 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0
2824 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK  0x1 /* cf1en */
2825 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT 1
2826 #define USTORM_ETH_CONN_AG_CTX_CF2EN_MASK                   0x1 /* cf2en */
2827 #define USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT                  2
2828 #define USTORM_ETH_CONN_AG_CTX_CF3EN_MASK                   0x1 /* cf3en */
2829 #define USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT                  3
2830 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK            0x1 /* cf4en */
2831 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT           4
2832 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK            0x1 /* cf5en */
2833 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT           5
2834 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK    0x1 /* cf6en */
2835 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT   6
2836 #define USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK                 0x1 /* rule0en */
2837 #define USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT                7
2838         u8 flags3;
2839 #define USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK                 0x1 /* rule1en */
2840 #define USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT                0
2841 #define USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK                 0x1 /* rule2en */
2842 #define USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT                1
2843 #define USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK                 0x1 /* rule3en */
2844 #define USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT                2
2845 #define USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK                 0x1 /* rule4en */
2846 #define USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT                3
2847 #define USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK                 0x1 /* rule5en */
2848 #define USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT                4
2849 #define USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK                 0x1 /* rule6en */
2850 #define USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT                5
2851 #define USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK                 0x1 /* rule7en */
2852 #define USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT                6
2853 #define USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK                 0x1 /* rule8en */
2854 #define USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT                7
2855         u8      byte2 /* byte2 */;
2856         u8      byte3 /* byte3 */;
2857         __le16  word0 /* conn_dpi */;
2858         __le16  tx_bd_cons /* word1 */;
2859         __le32  reg0 /* reg0 */;
2860         __le32  reg1 /* reg1 */;
2861         __le32  reg2 /* reg2 */;
2862         __le32  tx_int_coallecing_timeset /* reg3 */;
2863         __le16  tx_drv_bd_cons /* word2 */;
2864         __le16  rx_drv_cqe_cons /* word3 */;
2865 };
2866
2867 /* The eth storm context for the Ustorm */
2868 struct ustorm_eth_conn_st_ctx {
2869         __le32 reserved[40];
2870 };
2871
2872 /* The eth storm context for the Mstorm */
2873 struct mstorm_eth_conn_st_ctx {
2874         __le32 reserved[8];
2875 };
2876
2877 /* eth connection context */
2878 struct eth_conn_context {
2879         struct tstorm_eth_conn_st_ctx   tstorm_st_context;
2880         struct regpair                  tstorm_st_padding[2];
2881         struct pstorm_eth_conn_st_ctx   pstorm_st_context;
2882         struct xstorm_eth_conn_st_ctx   xstorm_st_context;
2883         struct xstorm_eth_conn_ag_ctx   xstorm_ag_context;
2884         struct ystorm_eth_conn_st_ctx   ystorm_st_context;
2885         struct ystorm_eth_conn_ag_ctx   ystorm_ag_context;
2886         struct tstorm_eth_conn_ag_ctx   tstorm_ag_context;
2887         struct ustorm_eth_conn_ag_ctx   ustorm_ag_context;
2888         struct ustorm_eth_conn_st_ctx   ustorm_st_context;
2889         struct mstorm_eth_conn_st_ctx   mstorm_st_context;
2890 };
2891
2892 enum eth_filter_action {
2893         ETH_FILTER_ACTION_REMOVE,
2894         ETH_FILTER_ACTION_ADD,
2895         ETH_FILTER_ACTION_REMOVE_ALL,
2896         MAX_ETH_FILTER_ACTION
2897 };
2898
2899 struct eth_filter_cmd {
2900         u8      type /* Filter Type (MAC/VLAN/Pair/VNI) */;
2901         u8      vport_id /* the vport id */;
2902         u8      action /* filter command action: add/remove/replace */;
2903         u8      reserved0;
2904         __le32  vni;
2905         __le16  mac_lsb;
2906         __le16  mac_mid;
2907         __le16  mac_msb;
2908         __le16  vlan_id;
2909 };
2910
2911 struct eth_filter_cmd_header {
2912         u8      rx;
2913         u8      tx;
2914         u8      cmd_cnt;
2915         u8      assert_on_error;
2916         u8      reserved1[4];
2917 };
2918
2919 enum eth_filter_type {
2920         ETH_FILTER_TYPE_MAC,
2921         ETH_FILTER_TYPE_VLAN,
2922         ETH_FILTER_TYPE_PAIR,
2923         ETH_FILTER_TYPE_INNER_MAC,
2924         ETH_FILTER_TYPE_INNER_VLAN,
2925         ETH_FILTER_TYPE_INNER_PAIR,
2926         ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR,
2927         ETH_FILTER_TYPE_MAC_VNI_PAIR,
2928         ETH_FILTER_TYPE_VNI,
2929         MAX_ETH_FILTER_TYPE
2930 };
2931
2932 enum eth_ramrod_cmd_id {
2933         ETH_RAMROD_UNUSED,
2934         ETH_RAMROD_VPORT_START /* VPort Start Ramrod */,
2935         ETH_RAMROD_VPORT_UPDATE /* VPort Update Ramrod */,
2936         ETH_RAMROD_VPORT_STOP /* VPort Stop Ramrod */,
2937         ETH_RAMROD_RX_QUEUE_START /* RX Queue Start Ramrod */,
2938         ETH_RAMROD_RX_QUEUE_STOP /* RX Queue Stop Ramrod */,
2939         ETH_RAMROD_TX_QUEUE_START /* TX Queue Start Ramrod */,
2940         ETH_RAMROD_TX_QUEUE_STOP /* TX Queue Stop Ramrod */,
2941         ETH_RAMROD_FILTERS_UPDATE /* Add or Remove Mac/Vlan/Pair filters */,
2942         ETH_RAMROD_RX_QUEUE_UPDATE /* RX Queue Update Ramrod */,
2943         ETH_RAMROD_RESERVED,
2944         ETH_RAMROD_RESERVED2,
2945         ETH_RAMROD_RESERVED3,
2946         ETH_RAMROD_RESERVED4,
2947         ETH_RAMROD_RESERVED5,
2948         ETH_RAMROD_RESERVED6,
2949         ETH_RAMROD_RESERVED7,
2950         ETH_RAMROD_RESERVED8,
2951         MAX_ETH_RAMROD_CMD_ID
2952 };
2953
2954 enum eth_tx_err {
2955         ETH_TX_ERR_DROP /* Drop erronous packet. */,
2956         ETH_TX_ERR_ASSERT_MALICIOUS,
2957         MAX_ETH_TX_ERR
2958 };
2959
2960 struct eth_tx_err_vals {
2961         __le16 values;
2962 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_MASK            0x1
2963 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_SHIFT           0
2964 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_MASK             0x1
2965 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_SHIFT            1
2966 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_MASK            0x1
2967 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_SHIFT           2
2968 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_MASK          0x1
2969 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_SHIFT         3
2970 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_MASK  0x1
2971 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_SHIFT 4
2972 #define ETH_TX_ERR_VALS_MTU_VIOLATION_MASK                0x1
2973 #define ETH_TX_ERR_VALS_MTU_VIOLATION_SHIFT               5
2974 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_MASK        0x1
2975 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_SHIFT       6
2976 #define ETH_TX_ERR_VALS_RESERVED_MASK                     0x1FF
2977 #define ETH_TX_ERR_VALS_RESERVED_SHIFT                    7
2978 };
2979
2980 struct eth_vport_rss_config {
2981         __le16 capabilities;
2982 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_MASK       0x1
2983 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_SHIFT       0
2984 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_MASK       0x1
2985 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_SHIFT       1
2986 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_MASK    0x1
2987 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_SHIFT   2
2988 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_MASK    0x1
2989 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_SHIFT   3
2990 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_MASK    0x1
2991 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_SHIFT   4
2992 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_MASK    0x1
2993 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_SHIFT   5
2994 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_MASK  0x1
2995 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_SHIFT 6
2996 #define ETH_VPORT_RSS_CONFIG_RESERVED0_MASK           0x1FF
2997 #define ETH_VPORT_RSS_CONFIG_RESERVED0_SHIFT         7
2998         u8      rss_id;
2999         u8      rss_mode;
3000         u8      update_rss_key;
3001         u8      update_rss_ind_table;
3002         u8      update_rss_capabilities;
3003         u8      tbl_size;
3004         __le32  reserved2[2];
3005         __le16  indirection_table[ETH_RSS_IND_TABLE_ENTRIES_NUM];
3006         __le32  rss_key[ETH_RSS_KEY_SIZE_REGS];
3007         __le32  reserved3[2];
3008 };
3009
3010 enum eth_vport_rss_mode {
3011         ETH_VPORT_RSS_MODE_DISABLED,
3012         ETH_VPORT_RSS_MODE_REGULAR,
3013         MAX_ETH_VPORT_RSS_MODE
3014 };
3015
3016 struct eth_vport_rx_mode {
3017         __le16 state;
3018 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_MASK     0x1
3019 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_SHIFT   0
3020 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
3021 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_SHIFT       1
3022 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_MASK  0x1
3023 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_SHIFT 2
3024 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_MASK     0x1
3025 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_SHIFT   3
3026 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
3027 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_SHIFT       4
3028 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
3029 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_SHIFT       5
3030 #define ETH_VPORT_RX_MODE_RESERVED1_MASK               0x3FF
3031 #define ETH_VPORT_RX_MODE_RESERVED1_SHIFT             6
3032         __le16 reserved2[3];
3033 };
3034
3035 struct eth_vport_tpa_param {
3036         u8      tpa_ipv4_en_flg;
3037         u8      tpa_ipv6_en_flg;
3038         u8      tpa_ipv4_tunn_en_flg;
3039         u8      tpa_ipv6_tunn_en_flg;
3040         u8      tpa_pkt_split_flg;
3041         u8      tpa_hdr_data_split_flg;
3042         u8      tpa_gro_consistent_flg;
3043         u8      tpa_max_aggs_num;
3044         u16     tpa_max_size;
3045         u16     tpa_min_size_to_start;
3046         u16     tpa_min_size_to_cont;
3047         u8      max_buff_num;
3048         u8      reserved;
3049 };
3050
3051 struct eth_vport_tx_mode {
3052         __le16 state;
3053 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_MASK    0x1
3054 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_SHIFT   0
3055 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_MASK  0x1
3056 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_SHIFT 1
3057 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_MASK    0x1
3058 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_SHIFT   2
3059 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_MASK  0x1
3060 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_SHIFT 3
3061 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_MASK  0x1
3062 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_SHIFT 4
3063 #define ETH_VPORT_TX_MODE_RESERVED1_MASK         0x7FF
3064 #define ETH_VPORT_TX_MODE_RESERVED1_SHIFT       5
3065         __le16 reserved2[3];
3066 };
3067
3068 struct rx_queue_start_ramrod_data {
3069         __le16    rx_queue_id;
3070         __le16    num_of_pbl_pages;
3071         __le16    bd_max_bytes;
3072         __le16    sb_id;
3073         u8            sb_index;
3074         u8            vport_id;
3075         u8            default_rss_queue_flg;
3076         u8            complete_cqe_flg;
3077         u8            complete_event_flg;
3078         u8            stats_counter_id;
3079         u8            pin_context;
3080         u8            pxp_tph_valid_bd;
3081         u8            pxp_tph_valid_pkt;
3082         u8            pxp_st_hint;
3083         __le16    pxp_st_index;
3084         u8              pmd_mode;
3085         u8              notify_en;
3086         u8              toggle_val;
3087         u8              reserved[7];
3088         __le16          reserved1;
3089         struct regpair  cqe_pbl_addr;
3090         struct regpair  bd_base;
3091         struct regpair  reserved2;
3092 };
3093
3094 struct rx_queue_stop_ramrod_data {
3095         __le16  rx_queue_id;
3096         u8      complete_cqe_flg;
3097         u8      complete_event_flg;
3098         u8      vport_id;
3099         u8      reserved[3];
3100 };
3101
3102 struct rx_queue_update_ramrod_data {
3103         __le16  rx_queue_id;
3104         u8      complete_cqe_flg;
3105         u8      complete_event_flg;
3106         u8      vport_id;
3107         u8      reserved[4];
3108         u8      reserved1;
3109         u8      reserved2;
3110         u8      reserved3;
3111         __le16  reserved4;
3112         __le16  reserved5;
3113         struct regpair reserved6;
3114 };
3115
3116 struct tx_queue_start_ramrod_data {
3117         __le16  sb_id;
3118         u8      sb_index;
3119         u8      vport_id;
3120         u8      reserved0;
3121         u8      stats_counter_id;
3122         __le16  qm_pq_id;
3123         u8      flags;
3124 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_MASK  0x1
3125 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT 0
3126 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK      0x1
3127 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_SHIFT     1
3128 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_MASK      0x1
3129 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_SHIFT     2
3130 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_MASK               0x1
3131 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_SHIFT              3
3132 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_MASK              0x1
3133 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_SHIFT             4
3134 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_MASK            0x1
3135 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_SHIFT           5
3136 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK              0x3
3137 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_SHIFT             6
3138         u8      pxp_st_hint;
3139         u8      pxp_tph_valid_bd;
3140         u8      pxp_tph_valid_pkt;
3141         __le16  pxp_st_index;
3142         __le16  comp_agg_size;
3143         __le16  queue_zone_id;
3144         __le16  test_dup_count;
3145         __le16  pbl_size;
3146         __le16  tx_queue_id;
3147         struct regpair  pbl_base_addr;
3148         struct regpair  bd_cons_address;
3149 };
3150
3151 struct tx_queue_stop_ramrod_data {
3152         __le16 reserved[4];
3153 };
3154
3155 struct vport_filter_update_ramrod_data {
3156         struct eth_filter_cmd_header    filter_cmd_hdr;
3157         struct eth_filter_cmd      filter_cmds[ETH_FILTER_RULES_COUNT];
3158 };
3159
3160 struct vport_start_ramrod_data {
3161         u8                            vport_id;
3162         u8                            sw_fid;
3163         __le16                    mtu;
3164         u8                            drop_ttl0_en;
3165         u8                            inner_vlan_removal_en;
3166         struct eth_vport_rx_mode        rx_mode;
3167         struct eth_vport_tx_mode        tx_mode;
3168         struct eth_vport_tpa_param      tpa_param;
3169         __le16                          default_vlan;
3170         u8                              tx_switching_en;
3171         u8                              anti_spoofing_en;
3172         u8                              default_vlan_en;
3173         u8                              handle_ptp_pkts;
3174         u8                              silent_vlan_removal_en;
3175         u8                              untagged;
3176         struct eth_tx_err_vals          tx_err_behav;
3177         u8                              zero_placement_offset;
3178         u8                              reserved[7];
3179 };
3180
3181 struct vport_stop_ramrod_data {
3182         u8      vport_id;
3183         u8      reserved[7];
3184 };
3185
3186 struct vport_update_ramrod_data_cmn {
3187         u8      vport_id;
3188         u8      update_rx_active_flg;
3189         u8      rx_active_flg;
3190         u8      update_tx_active_flg;
3191         u8      tx_active_flg;
3192         u8      update_rx_mode_flg;
3193         u8      update_tx_mode_flg;
3194         u8      update_approx_mcast_flg;
3195         u8      update_rss_flg;
3196         u8      update_inner_vlan_removal_en_flg;
3197         u8      inner_vlan_removal_en;
3198         u8      update_tpa_param_flg;
3199         u8      update_tpa_en_flg;
3200         u8      update_tx_switching_en_flg;
3201         u8      tx_switching_en;
3202         u8      update_anti_spoofing_en_flg;
3203         u8      anti_spoofing_en;
3204         u8      update_handle_ptp_pkts;
3205         u8      handle_ptp_pkts;
3206         u8      update_default_vlan_en_flg;
3207         u8      default_vlan_en;
3208         u8      update_default_vlan_flg;
3209         __le16  default_vlan;
3210         u8      update_accept_any_vlan_flg;
3211         u8      accept_any_vlan;
3212         u8      silent_vlan_removal_en;
3213         u8      update_mtu_flg;
3214         __le16  mtu;
3215         u8      reserved[2];
3216 };
3217
3218 struct vport_update_ramrod_mcast {
3219         __le32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
3220 };
3221
3222 struct vport_update_ramrod_data {
3223         struct vport_update_ramrod_data_cmn     common;
3224         struct eth_vport_rx_mode                rx_mode;
3225         struct eth_vport_tx_mode                tx_mode;
3226         struct eth_vport_tpa_param            tpa_param;
3227         struct vport_update_ramrod_mcast        approx_mcast;
3228         struct eth_vport_rss_config          rss_config;
3229 };
3230
3231 #define VF_MAX_STATIC 192       /* In case of K2 */
3232
3233 #define MCP_GLOB_PATH_MAX       2
3234 #define MCP_PORT_MAX            2       /* Global */
3235 #define MCP_GLOB_PORT_MAX       4       /* Global */
3236 #define MCP_GLOB_FUNC_MAX       16      /* Global */
3237
3238 typedef u32 offsize_t;                  /* In DWORDS !!! */
3239 /* Offset from the beginning of the MCP scratchpad */
3240 #define OFFSIZE_OFFSET_SHIFT    0
3241 #define OFFSIZE_OFFSET_MASK     0x0000ffff
3242 /* Size of specific element (not the whole array if any) */
3243 #define OFFSIZE_SIZE_SHIFT      16
3244 #define OFFSIZE_SIZE_MASK       0xffff0000
3245
3246 /* SECTION_OFFSET is calculating the offset in bytes out of offsize */
3247 #define SECTION_OFFSET(_offsize)        ((((_offsize &              \
3248                                             OFFSIZE_OFFSET_MASK) >> \
3249                                            OFFSIZE_OFFSET_SHIFT) << 2))
3250
3251 /* QED_SECTION_SIZE is calculating the size in bytes out of offsize */
3252 #define QED_SECTION_SIZE(_offsize)              (((_offsize &            \
3253                                                    OFFSIZE_SIZE_MASK) >> \
3254                                                   OFFSIZE_SIZE_SHIFT) << 2)
3255
3256 /* SECTION_ADDR returns the GRC addr of a section, given offsize and index
3257  * within section.
3258  */
3259 #define SECTION_ADDR(_offsize, idx)     (MCP_REG_SCRATCH +          \
3260                                          SECTION_OFFSET(_offsize) + \
3261                                          (QED_SECTION_SIZE(_offsize) * idx))
3262
3263 /* SECTION_OFFSIZE_ADDR returns the GRC addr to the offsize address.
3264  * Use offsetof, since the OFFSETUP collide with the firmware definition
3265  */
3266 #define SECTION_OFFSIZE_ADDR(_pub_base, _section) (_pub_base +               \
3267                                                    offsetof(struct           \
3268                                                             mcp_public_data, \
3269                                                             sections[_section]))
3270 /* PHY configuration */
3271 struct pmm_phy_cfg {
3272         u32     speed;
3273 #define PMM_SPEED_AUTONEG   0
3274
3275         u32     pause;  /* bitmask */
3276 #define PMM_PAUSE_NONE          0x0
3277 #define PMM_PAUSE_AUTONEG       0x1
3278 #define PMM_PAUSE_RX            0x2
3279 #define PMM_PAUSE_TX            0x4
3280
3281         u32     adv_speed;  /* Default should be the speed_cap_mask */
3282         u32     loopback_mode;
3283 #define PMM_LOOPBACK_NONE               0
3284 #define PMM_LOOPBACK_INT_PHY    1
3285 #define PMM_LOOPBACK_EXT_PHY    2
3286 #define PMM_LOOPBACK_EXT                3
3287 #define PMM_LOOPBACK_MAC                4
3288
3289         /* features */
3290         u32 feature_config_flags;
3291 };
3292
3293 struct port_mf_cfg {
3294         u32     dynamic_cfg; /* device control channel */
3295 #define PORT_MF_CFG_OV_TAG_MASK              0x0000ffff
3296 #define PORT_MF_CFG_OV_TAG_SHIFT             0
3297 #define PORT_MF_CFG_OV_TAG_DEFAULT         PORT_MF_CFG_OV_TAG_MASK
3298
3299         u32     reserved[1];
3300 };
3301
3302 /* DO NOT add new fields in the middle
3303  * MUST be synced with struct pmm_stats_map
3304  */
3305 struct pmm_stats {
3306         u64     r64;    /* 0x00 (Offset 0x00 ) RX 64-byte frame counter*/
3307         u64     r127;   /* 0x01 (Offset 0x08 ) RX 65 to 127 byte frame counter*/
3308         u64     r255;
3309         u64     r511;
3310         u64     r1023;
3311         u64     r1518;
3312         u64     r1522;
3313         u64     r2047;
3314         u64     r4095;
3315         u64     r9216;
3316         u64     r16383;
3317         u64     rfcs;   /* 0x0F (Offset 0x58 ) RX FCS error frame counter*/
3318         u64     rxcf;   /* 0x10 (Offset 0x60 ) RX control frame counter*/
3319         u64     rxpf;   /* 0x11 (Offset 0x68 ) RX pause frame counter*/
3320         u64     rxpp;   /* 0x12 (Offset 0x70 ) RX PFC frame counter*/
3321         u64     raln;   /* 0x16 (Offset 0x78 ) RX alignment error counter*/
3322         u64     rfcr;   /* 0x19 (Offset 0x80 ) RX false carrier counter */
3323         u64     rovr;   /* 0x1A (Offset 0x88 ) RX oversized frame counter*/
3324         u64     rjbr;   /* 0x1B (Offset 0x90 ) RX jabber frame counter */
3325         u64     rund;   /* 0x34 (Offset 0x98 ) RX undersized frame counter */
3326         u64     rfrg;   /* 0x35 (Offset 0xa0 ) RX fragment counter */
3327         u64     t64;    /* 0x40 (Offset 0xa8 ) TX 64-byte frame counter */
3328         u64     t127;
3329         u64     t255;
3330         u64     t511;
3331         u64     t1023;
3332         u64     t1518;
3333         u64     t2047;
3334         u64     t4095;
3335         u64     t9216;
3336         u64     t16383;
3337         u64     txpf;   /* 0x50 (Offset 0xf8 ) TX pause frame counter */
3338         u64     txpp;   /* 0x51 (Offset 0x100) TX PFC frame counter */
3339         u64     tlpiec;
3340         u64     tncl;
3341         u64     rbyte;  /* 0x3d (Offset 0x118) RX byte counter */
3342         u64     rxuca;  /* 0x0c (Offset 0x120) RX UC frame counter */
3343         u64     rxmca;  /* 0x0d (Offset 0x128) RX MC frame counter */
3344         u64     rxbca;  /* 0x0e (Offset 0x130) RX BC frame counter */
3345         u64     rxpok;
3346         u64     tbyte;  /* 0x6f (Offset 0x140) TX byte counter */
3347         u64     txuca;  /* 0x4d (Offset 0x148) TX UC frame counter */
3348         u64     txmca;  /* 0x4e (Offset 0x150) TX MC frame counter */
3349         u64     txbca;  /* 0x4f (Offset 0x158) TX BC frame counter */
3350         u64     txcf;   /* 0x54 (Offset 0x160) TX control frame counter */
3351 };
3352
3353 struct brb_stats {
3354         u64     brb_truncate[8];
3355         u64     brb_discard[8];
3356 };
3357
3358 struct port_stats {
3359         struct brb_stats        brb;
3360         struct pmm_stats        pmm;
3361 };
3362
3363 #define CMT_TEAM0 0
3364 #define CMT_TEAM1 1
3365 #define CMT_TEAM_MAX 2
3366
3367 struct couple_mode_teaming {
3368         u8 port_cmt[MCP_GLOB_PORT_MAX];
3369 #define PORT_CMT_IN_TEAM                BIT(0)
3370
3371 #define PORT_CMT_PORT_ROLE              BIT(1)
3372 #define PORT_CMT_PORT_INACTIVE      (0 << 1)
3373 #define PORT_CMT_PORT_ACTIVE            BIT(1)
3374
3375 #define PORT_CMT_TEAM_MASK              BIT(2)
3376 #define PORT_CMT_TEAM0              (0 << 2)
3377 #define PORT_CMT_TEAM1                  BIT(2)
3378 };
3379
3380 /**************************************
3381 *     LLDP and DCBX HSI structures
3382 **************************************/
3383 #define LLDP_CHASSIS_ID_STAT_LEN 4
3384 #define LLDP_PORT_ID_STAT_LEN 4
3385 #define DCBX_MAX_APP_PROTOCOL           32
3386 #define MAX_SYSTEM_LLDP_TLV_DATA    32
3387
3388 enum lldp_agent_e {
3389         LLDP_NEAREST_BRIDGE = 0,
3390         LLDP_NEAREST_NON_TPMR_BRIDGE,
3391         LLDP_NEAREST_CUSTOMER_BRIDGE,
3392         LLDP_MAX_LLDP_AGENTS
3393 };
3394
3395 struct lldp_config_params_s {
3396         u32 config;
3397 #define LLDP_CONFIG_TX_INTERVAL_MASK        0x000000ff
3398 #define LLDP_CONFIG_TX_INTERVAL_SHIFT       0
3399 #define LLDP_CONFIG_HOLD_MASK               0x00000f00
3400 #define LLDP_CONFIG_HOLD_SHIFT              8
3401 #define LLDP_CONFIG_MAX_CREDIT_MASK         0x0000f000
3402 #define LLDP_CONFIG_MAX_CREDIT_SHIFT        12
3403 #define LLDP_CONFIG_ENABLE_RX_MASK          0x40000000
3404 #define LLDP_CONFIG_ENABLE_RX_SHIFT         30
3405 #define LLDP_CONFIG_ENABLE_TX_MASK          0x80000000
3406 #define LLDP_CONFIG_ENABLE_TX_SHIFT         31
3407         u32     local_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
3408         u32     local_port_id[LLDP_PORT_ID_STAT_LEN];
3409 };
3410
3411 struct lldp_status_params_s {
3412         u32     prefix_seq_num;
3413         u32     status; /* TBD */
3414
3415         /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */
3416         u32     peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
3417
3418         /* Holds remote Port ID TLV header, subtype and 9B of payload. */
3419         u32     peer_port_id[LLDP_PORT_ID_STAT_LEN];
3420         u32     suffix_seq_num;
3421 };
3422
3423 struct dcbx_ets_feature {
3424         u32 flags;
3425 #define DCBX_ETS_ENABLED_MASK                   0x00000001
3426 #define DCBX_ETS_ENABLED_SHIFT                  0
3427 #define DCBX_ETS_WILLING_MASK                   0x00000002
3428 #define DCBX_ETS_WILLING_SHIFT                  1
3429 #define DCBX_ETS_ERROR_MASK                     0x00000004
3430 #define DCBX_ETS_ERROR_SHIFT                    2
3431 #define DCBX_ETS_CBS_MASK                       0x00000008
3432 #define DCBX_ETS_CBS_SHIFT                      3
3433 #define DCBX_ETS_MAX_TCS_MASK                   0x000000f0
3434 #define DCBX_ETS_MAX_TCS_SHIFT                  4
3435         u32     pri_tc_tbl[1];
3436 #define DCBX_ISCSI_OOO_TC                       4
3437 #define NIG_ETS_ISCSI_OOO_CLIENT_OFFSET         (DCBX_ISCSI_OOO_TC + 1)
3438         u32     tc_bw_tbl[2];
3439         u32     tc_tsa_tbl[2];
3440 #define DCBX_ETS_TSA_STRICT                     0
3441 #define DCBX_ETS_TSA_CBS                        1
3442 #define DCBX_ETS_TSA_ETS                        2
3443 };
3444
3445 struct dcbx_app_priority_entry {
3446         u32 entry;
3447 #define DCBX_APP_PRI_MAP_MASK       0x000000ff
3448 #define DCBX_APP_PRI_MAP_SHIFT      0
3449 #define DCBX_APP_PRI_0              0x01
3450 #define DCBX_APP_PRI_1              0x02
3451 #define DCBX_APP_PRI_2              0x04
3452 #define DCBX_APP_PRI_3              0x08
3453 #define DCBX_APP_PRI_4              0x10
3454 #define DCBX_APP_PRI_5              0x20
3455 #define DCBX_APP_PRI_6              0x40
3456 #define DCBX_APP_PRI_7              0x80
3457 #define DCBX_APP_SF_MASK            0x00000300
3458 #define DCBX_APP_SF_SHIFT           8
3459 #define DCBX_APP_SF_ETHTYPE         0
3460 #define DCBX_APP_SF_PORT            1
3461 #define DCBX_APP_PROTOCOL_ID_MASK   0xffff0000
3462 #define DCBX_APP_PROTOCOL_ID_SHIFT  16
3463 };
3464
3465 /* FW structure in BE */
3466 struct dcbx_app_priority_feature {
3467         u32 flags;
3468 #define DCBX_APP_ENABLED_MASK           0x00000001
3469 #define DCBX_APP_ENABLED_SHIFT          0
3470 #define DCBX_APP_WILLING_MASK           0x00000002
3471 #define DCBX_APP_WILLING_SHIFT          1
3472 #define DCBX_APP_ERROR_MASK             0x00000004
3473 #define DCBX_APP_ERROR_SHIFT            2
3474 /* Not in use
3475  * #define DCBX_APP_DEFAULT_PRI_MASK       0x00000f00
3476  * #define DCBX_APP_DEFAULT_PRI_SHIFT      8
3477  */
3478 #define DCBX_APP_MAX_TCS_MASK           0x0000f000
3479 #define DCBX_APP_MAX_TCS_SHIFT          12
3480 #define DCBX_APP_NUM_ENTRIES_MASK       0x00ff0000
3481 #define DCBX_APP_NUM_ENTRIES_SHIFT      16
3482         struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
3483 };
3484
3485 /* FW structure in BE */
3486 struct dcbx_features {
3487         /* PG feature */
3488         struct dcbx_ets_feature ets;
3489
3490         /* PFC feature */
3491         u32                     pfc;
3492 #define DCBX_PFC_PRI_EN_BITMAP_MASK             0x000000ff
3493 #define DCBX_PFC_PRI_EN_BITMAP_SHIFT            0
3494 #define DCBX_PFC_PRI_EN_BITMAP_PRI_0            0x01
3495 #define DCBX_PFC_PRI_EN_BITMAP_PRI_1            0x02
3496 #define DCBX_PFC_PRI_EN_BITMAP_PRI_2            0x04
3497 #define DCBX_PFC_PRI_EN_BITMAP_PRI_3            0x08
3498 #define DCBX_PFC_PRI_EN_BITMAP_PRI_4            0x10
3499 #define DCBX_PFC_PRI_EN_BITMAP_PRI_5            0x20
3500 #define DCBX_PFC_PRI_EN_BITMAP_PRI_6            0x40
3501 #define DCBX_PFC_PRI_EN_BITMAP_PRI_7            0x80
3502
3503 #define DCBX_PFC_FLAGS_MASK                     0x0000ff00
3504 #define DCBX_PFC_FLAGS_SHIFT                    8
3505 #define DCBX_PFC_CAPS_MASK                      0x00000f00
3506 #define DCBX_PFC_CAPS_SHIFT                     8
3507 #define DCBX_PFC_MBC_MASK                       0x00004000
3508 #define DCBX_PFC_MBC_SHIFT                      14
3509 #define DCBX_PFC_WILLING_MASK                   0x00008000
3510 #define DCBX_PFC_WILLING_SHIFT                  15
3511 #define DCBX_PFC_ENABLED_MASK                   0x00010000
3512 #define DCBX_PFC_ENABLED_SHIFT                  16
3513 #define DCBX_PFC_ERROR_MASK                     0x00020000
3514 #define DCBX_PFC_ERROR_SHIFT                    17
3515
3516         /* APP feature */
3517         struct dcbx_app_priority_feature app;
3518 };
3519
3520 struct dcbx_local_params {
3521         u32 config;
3522 #define DCBX_CONFIG_VERSION_MASK            0x00000003
3523 #define DCBX_CONFIG_VERSION_SHIFT           0
3524 #define DCBX_CONFIG_VERSION_DISABLED        0
3525 #define DCBX_CONFIG_VERSION_IEEE            1
3526 #define DCBX_CONFIG_VERSION_CEE             2
3527
3528         u32                     flags;
3529         struct dcbx_features    features;
3530 };
3531
3532 struct dcbx_mib {
3533         u32     prefix_seq_num;
3534         u32     flags;
3535         struct dcbx_features    features;
3536         u32                     suffix_seq_num;
3537 };
3538
3539 struct lldp_system_tlvs_buffer_s {
3540         u16     valid;
3541         u16     length;
3542         u32     data[MAX_SYSTEM_LLDP_TLV_DATA];
3543 };
3544
3545 /**************************************/
3546 /*                                    */
3547 /*     P U B L I C      G L O B A L   */
3548 /*                                    */
3549 /**************************************/
3550 struct public_global {
3551         u32                             max_path;
3552 #define MAX_PATH_BIG_BEAR       2
3553 #define MAX_PATH_K2             1
3554         u32                             max_ports;
3555 #define MODE_1P 1
3556 #define MODE_2P 2
3557 #define MODE_3P 3
3558 #define MODE_4P 4
3559         u32                             debug_mb_offset;
3560         u32                             phymod_dbg_mb_offset;
3561         struct couple_mode_teaming      cmt;
3562         s32                             internal_temperature;
3563         u32                             mfw_ver;
3564         u32                             running_bundle_id;
3565 };
3566
3567 /**************************************/
3568 /*                                    */
3569 /*     P U B L I C      P A T H       */
3570 /*                                    */
3571 /**************************************/
3572
3573 /****************************************************************************
3574 * Shared Memory 2 Region                                                   *
3575 ****************************************************************************/
3576 /* The fw_flr_ack is actually built in the following way:                   */
3577 /* 8 bit:  PF ack                                                           */
3578 /* 128 bit: VF ack                                                           */
3579 /* 8 bit:  ios_dis_ack                                                      */
3580 /* In order to maintain endianity in the mailbox hsi, we want to keep using */
3581 /* u32. The fw must have the VF right after the PF since this is how it     */
3582 /* access arrays(it expects always the VF to reside after the PF, and that  */
3583 /* makes the calculation much easier for it. )                              */
3584 /* In order to answer both limitations, and keep the struct small, the code */
3585 /* will abuse the structure defined here to achieve the actual partition    */
3586 /* above                                                                    */
3587 /****************************************************************************/
3588 struct fw_flr_mb {
3589         u32     aggint;
3590         u32     opgen_addr;
3591         u32     accum_ack;  /* 0..15:PF, 16..207:VF, 256..271:IOV_DIS */
3592 #define ACCUM_ACK_PF_BASE       0
3593 #define ACCUM_ACK_PF_SHIFT      0
3594
3595 #define ACCUM_ACK_VF_BASE       8
3596 #define ACCUM_ACK_VF_SHIFT      3
3597
3598 #define ACCUM_ACK_IOV_DIS_BASE  256
3599 #define ACCUM_ACK_IOV_DIS_SHIFT 8
3600 };
3601
3602 struct public_path {
3603         struct fw_flr_mb        flr_mb;
3604         u32                     mcp_vf_disabled[VF_MAX_STATIC / 32];
3605
3606         u32                     process_kill;
3607 #define PROCESS_KILL_COUNTER_MASK               0x0000ffff
3608 #define PROCESS_KILL_COUNTER_SHIFT              0
3609 #define PROCESS_KILL_GLOB_AEU_BIT_MASK          0xffff0000
3610 #define PROCESS_KILL_GLOB_AEU_BIT_SHIFT         16
3611 #define GLOBAL_AEU_BIT(aeu_reg_id, aeu_bit) (aeu_reg_id * 32 + aeu_bit)
3612 };
3613
3614 /**************************************/
3615 /*                                    */
3616 /*     P U B L I C      P O R T       */
3617 /*                                    */
3618 /**************************************/
3619
3620 /****************************************************************************
3621 * Driver <-> FW Mailbox                                                    *
3622 ****************************************************************************/
3623
3624 struct public_port {
3625         u32 validity_map;   /* 0x0 (4*2 = 0x8) */
3626
3627         /* validity bits */
3628 #define MCP_VALIDITY_PCI_CFG                    0x00100000
3629 #define MCP_VALIDITY_MB                         0x00200000
3630 #define MCP_VALIDITY_DEV_INFO                   0x00400000
3631 #define MCP_VALIDITY_RESERVED                   0x00000007
3632
3633         /* One licensing bit should be set */
3634 #define MCP_VALIDITY_LIC_KEY_IN_EFFECT_MASK     0x00000038
3635 #define MCP_VALIDITY_LIC_MANUF_KEY_IN_EFFECT    0x00000008
3636 #define MCP_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT  0x00000010
3637 #define MCP_VALIDITY_LIC_NO_KEY_IN_EFFECT       0x00000020
3638
3639         /* Active MFW */
3640 #define MCP_VALIDITY_ACTIVE_MFW_UNKNOWN         0x00000000
3641 #define MCP_VALIDITY_ACTIVE_MFW_MASK            0x000001c0
3642 #define MCP_VALIDITY_ACTIVE_MFW_NCSI            0x00000040
3643 #define MCP_VALIDITY_ACTIVE_MFW_NONE            0x000001c0
3644
3645         u32 link_status;
3646 #define LINK_STATUS_LINK_UP \
3647         0x00000001
3648 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK                       0x0000001e
3649 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD            BIT(1)
3650 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD            (2 << 1)
3651 #define LINK_STATUS_SPEED_AND_DUPLEX_10G                        (3 << 1)
3652 #define LINK_STATUS_SPEED_AND_DUPLEX_20G                        (4 << 1)
3653 #define LINK_STATUS_SPEED_AND_DUPLEX_40G                        (5 << 1)
3654 #define LINK_STATUS_SPEED_AND_DUPLEX_50G                        (6 << 1)
3655 #define LINK_STATUS_SPEED_AND_DUPLEX_100G                       (7 << 1)
3656 #define LINK_STATUS_SPEED_AND_DUPLEX_25G                        (8 << 1)
3657
3658 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED                      0x00000020
3659
3660 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE                     0x00000040
3661 #define LINK_STATUS_PARALLEL_DETECTION_USED                     0x00000080
3662
3663 #define LINK_STATUS_PFC_ENABLED \
3664         0x00000100
3665 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE        0x00000200
3666 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE        0x00000400
3667 #define LINK_STATUS_LINK_PARTNER_10G_CAPABLE            0x00000800
3668 #define LINK_STATUS_LINK_PARTNER_20G_CAPABLE            0x00001000
3669 #define LINK_STATUS_LINK_PARTNER_40G_CAPABLE            0x00002000
3670 #define LINK_STATUS_LINK_PARTNER_50G_CAPABLE            0x00004000
3671 #define LINK_STATUS_LINK_PARTNER_100G_CAPABLE           0x00008000
3672 #define LINK_STATUS_LINK_PARTNER_25G_CAPABLE            0x00010000
3673
3674 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK      0x000C0000
3675 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE      (0 << 18)
3676 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE        BIT(18)
3677 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE       (2 << 18)
3678 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE                     (3 << 18)
3679
3680 #define LINK_STATUS_SFP_TX_FAULT \
3681         0x00100000
3682 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED                     0x00200000
3683 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED                     0x00400000
3684
3685         u32                     link_status1;
3686         u32                     ext_phy_fw_version;
3687         u32                     drv_phy_cfg_addr;
3688
3689         u32                     port_stx;
3690
3691         u32                     stat_nig_timer;
3692
3693         struct port_mf_cfg      port_mf_config;
3694         struct port_stats       stats;
3695
3696         u32                     media_type;
3697 #define MEDIA_UNSPECIFIED       0x0
3698 #define MEDIA_SFPP_10G_FIBER    0x1
3699 #define MEDIA_XFP_FIBER         0x2
3700 #define MEDIA_DA_TWINAX         0x3
3701 #define MEDIA_BASE_T            0x4
3702 #define MEDIA_SFP_1G_FIBER      0x5
3703 #define MEDIA_MODULE_FIBER      0x6
3704 #define MEDIA_KR                0xf0
3705 #define MEDIA_NOT_PRESENT       0xff
3706
3707         u32 lfa_status;
3708 #define LFA_LINK_FLAP_REASON_OFFSET             0
3709 #define LFA_LINK_FLAP_REASON_MASK               0x000000ff
3710 #define LFA_NO_REASON                                   (0 << 0)
3711 #define LFA_LINK_DOWN                                   BIT(0)
3712 #define LFA_FORCE_INIT                                  BIT(1)
3713 #define LFA_LOOPBACK_MISMATCH                           BIT(2)
3714 #define LFA_SPEED_MISMATCH                              BIT(3)
3715 #define LFA_FLOW_CTRL_MISMATCH                          BIT(4)
3716 #define LFA_ADV_SPEED_MISMATCH                          BIT(5)
3717 #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET        8
3718 #define LINK_FLAP_AVOIDANCE_COUNT_MASK          0x0000ff00
3719 #define LINK_FLAP_COUNT_OFFSET                  16
3720 #define LINK_FLAP_COUNT_MASK                    0x00ff0000
3721
3722         u32                                     link_change_count;
3723
3724         /* LLDP params */
3725         struct lldp_config_params_s             lldp_config_params[
3726                 LLDP_MAX_LLDP_AGENTS];
3727         struct lldp_status_params_s             lldp_status_params[
3728                 LLDP_MAX_LLDP_AGENTS];
3729         struct lldp_system_tlvs_buffer_s        system_lldp_tlvs_buf;
3730
3731         /* DCBX related MIB */
3732         struct dcbx_local_params                local_admin_dcbx_mib;
3733         struct dcbx_mib                         remote_dcbx_mib;
3734         struct dcbx_mib                         operational_dcbx_mib;
3735
3736         u32                                     fc_npiv_nvram_tbl_addr;
3737         u32                                     fc_npiv_nvram_tbl_size;
3738         u32                                     transceiver_data;
3739 #define PMM_TRANSCEIVER_STATE_MASK              0x000000FF
3740 #define PMM_TRANSCEIVER_STATE_SHIFT             0x00000000
3741 #define PMM_TRANSCEIVER_STATE_PRESENT           0x00000001
3742 };
3743
3744 /**************************************/
3745 /*                                    */
3746 /*     P U B L I C      F U N C       */
3747 /*                                    */
3748 /**************************************/
3749
3750 struct public_func {
3751         u32     iscsi_boot_signature;
3752         u32     iscsi_boot_block_offset;
3753
3754         u32     mtu_size;
3755         u32     c2s_pcp_map_lower;
3756         u32     c2s_pcp_map_upper;
3757         u32     c2s_pcp_map_default;
3758         u32     reserved[4];
3759
3760         u32     config;
3761
3762         /* E/R/I/D */
3763         /* function 0 of each port cannot be hidden */
3764 #define FUNC_MF_CFG_FUNC_HIDE                   0x00000001
3765 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING          0x00000002
3766 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING_SHIFT    0x00000001
3767
3768 #define FUNC_MF_CFG_PROTOCOL_MASK               0x000000f0
3769 #define FUNC_MF_CFG_PROTOCOL_SHIFT              4
3770 #define FUNC_MF_CFG_PROTOCOL_ETHERNET           0x00000000
3771 #define FUNC_MF_CFG_PROTOCOL_ISCSI              0x00000010
3772 #define FUNC_MF_CFG_PROTOCOL_FCOE               0x00000020
3773 #define FUNC_MF_CFG_PROTOCOL_ROCE               0x00000030
3774 #define FUNC_MF_CFG_PROTOCOL_MAX                0x00000030
3775
3776         /* MINBW, MAXBW */
3777         /* value range - 0..100, increments in 1 %  */
3778 #define FUNC_MF_CFG_MIN_BW_MASK                 0x0000ff00
3779 #define FUNC_MF_CFG_MIN_BW_SHIFT                8
3780 #define FUNC_MF_CFG_MIN_BW_DEFAULT              0x00000000
3781 #define FUNC_MF_CFG_MAX_BW_MASK                 0x00ff0000
3782 #define FUNC_MF_CFG_MAX_BW_SHIFT                16
3783 #define FUNC_MF_CFG_MAX_BW_DEFAULT              0x00640000
3784
3785         u32     status;
3786 #define FUNC_STATUS_VLINK_DOWN                  0x00000001
3787
3788         u32     mac_upper;  /* MAC */
3789 #define FUNC_MF_CFG_UPPERMAC_MASK               0x0000ffff
3790 #define FUNC_MF_CFG_UPPERMAC_SHIFT              0
3791 #define FUNC_MF_CFG_UPPERMAC_DEFAULT            FUNC_MF_CFG_UPPERMAC_MASK
3792         u32     mac_lower;
3793 #define FUNC_MF_CFG_LOWERMAC_DEFAULT            0xffffffff
3794
3795         u32     fcoe_wwn_port_name_upper;
3796         u32     fcoe_wwn_port_name_lower;
3797
3798         u32     fcoe_wwn_node_name_upper;
3799         u32     fcoe_wwn_node_name_lower;
3800
3801         u32     ovlan_stag; /* tags */
3802 #define FUNC_MF_CFG_OV_STAG_MASK              0x0000ffff
3803 #define FUNC_MF_CFG_OV_STAG_SHIFT             0
3804 #define FUNC_MF_CFG_OV_STAG_DEFAULT           FUNC_MF_CFG_OV_STAG_MASK
3805
3806         u32     pf_allocation;  /* vf per pf */
3807
3808         u32     preserve_data;  /* Will be used bt CCM */
3809
3810         u32     driver_last_activity_ts;
3811
3812         u32     drv_ack_vf_disabled[VF_MAX_STATIC / 32]; /* 0x0044 */
3813
3814         u32     drv_id;
3815 #define DRV_ID_PDA_COMP_VER_MASK        0x0000ffff
3816 #define DRV_ID_PDA_COMP_VER_SHIFT       0
3817
3818 #define DRV_ID_MCP_HSI_VER_MASK         0x00ff0000
3819 #define DRV_ID_MCP_HSI_VER_SHIFT        16
3820 #define DRV_ID_MCP_HSI_VER_CURRENT      BIT(DRV_ID_MCP_HSI_VER_SHIFT)
3821
3822 #define DRV_ID_DRV_TYPE_MASK            0x7f000000
3823 #define DRV_ID_DRV_TYPE_SHIFT           24
3824 #define DRV_ID_DRV_TYPE_UNKNOWN         (0 << DRV_ID_DRV_TYPE_SHIFT)
3825 #define DRV_ID_DRV_TYPE_LINUX           (1 << DRV_ID_DRV_TYPE_SHIFT)
3826 #define DRV_ID_DRV_TYPE_WINDOWS         (2 << DRV_ID_DRV_TYPE_SHIFT)
3827 #define DRV_ID_DRV_TYPE_DIAG            (3 << DRV_ID_DRV_TYPE_SHIFT)
3828 #define DRV_ID_DRV_TYPE_PREBOOT         (4 << DRV_ID_DRV_TYPE_SHIFT)
3829 #define DRV_ID_DRV_TYPE_SOLARIS         (5 << DRV_ID_DRV_TYPE_SHIFT)
3830 #define DRV_ID_DRV_TYPE_VMWARE          (6 << DRV_ID_DRV_TYPE_SHIFT)
3831 #define DRV_ID_DRV_TYPE_FREEBSD         (7 << DRV_ID_DRV_TYPE_SHIFT)
3832 #define DRV_ID_DRV_TYPE_AIX             (8 << DRV_ID_DRV_TYPE_SHIFT)
3833
3834 #define DRV_ID_DRV_INIT_HW_MASK         0x80000000
3835 #define DRV_ID_DRV_INIT_HW_SHIFT        31
3836 #define DRV_ID_DRV_INIT_HW_FLAG         BIT(DRV_ID_DRV_INIT_HW_SHIFT)
3837 };
3838
3839 /**************************************/
3840 /*                                    */
3841 /*     P U B L I C       M B          */
3842 /*                                    */
3843 /**************************************/
3844 /* This is the only section that the driver can write to, and each */
3845 /* Basically each driver request to set feature parameters,
3846  * will be done using a different command, which will be linked
3847  * to a specific data structure from the union below.
3848  * For huge strucuture, the common blank structure should be used.
3849  */
3850
3851 struct mcp_mac {
3852         u32     mac_upper;  /* Upper 16 bits are always zeroes */
3853         u32     mac_lower;
3854 };
3855
3856 struct mcp_val64 {
3857         u32     lo;
3858         u32     hi;
3859 };
3860
3861 struct mcp_file_att {
3862         u32     nvm_start_addr;
3863         u32     len;
3864 };
3865
3866 #define MCP_DRV_VER_STR_SIZE 16
3867 #define MCP_DRV_VER_STR_SIZE_DWORD (MCP_DRV_VER_STR_SIZE / sizeof(u32))
3868 #define MCP_DRV_NVM_BUF_LEN 32
3869 struct drv_version_stc {
3870         u32     version;
3871         u8      name[MCP_DRV_VER_STR_SIZE - 4];
3872 };
3873
3874 union drv_union_data {
3875         u32                     ver_str[MCP_DRV_VER_STR_SIZE_DWORD];
3876         struct mcp_mac          wol_mac;
3877
3878         struct pmm_phy_cfg      drv_phy_cfg;
3879
3880         struct mcp_val64        val64; /* For PHY / AVS commands */
3881
3882         u8                      raw_data[MCP_DRV_NVM_BUF_LEN];
3883
3884         struct mcp_file_att     file_att;
3885
3886         u32                     ack_vf_disabled[VF_MAX_STATIC / 32];
3887
3888         struct drv_version_stc  drv_version;
3889 };
3890
3891 struct public_drv_mb {
3892         u32 drv_mb_header;
3893 #define DRV_MSG_CODE_MASK                       0xffff0000
3894 #define DRV_MSG_CODE_LOAD_REQ                   0x10000000
3895 #define DRV_MSG_CODE_LOAD_DONE                  0x11000000
3896 #define DRV_MSG_CODE_INIT_HW                    0x12000000
3897 #define DRV_MSG_CODE_UNLOAD_REQ                 0x20000000
3898 #define DRV_MSG_CODE_UNLOAD_DONE                0x21000000
3899 #define DRV_MSG_CODE_INIT_PHY                   0x22000000
3900         /* Params - FORCE - Reinitialize the link regardless of LFA */
3901         /*        - DONT_CARE - Don't flap the link if up */
3902 #define DRV_MSG_CODE_LINK_RESET                 0x23000000
3903
3904 #define DRV_MSG_CODE_SET_LLDP                   0x24000000
3905 #define DRV_MSG_CODE_SET_DCBX                   0x25000000
3906 #define DRV_MSG_CODE_BW_UPDATE_ACK              0x32000000
3907 #define DRV_MSG_CODE_NIG_DRAIN                  0x30000000
3908
3909 #define DRV_MSG_CODE_INITIATE_FLR               0x02000000
3910 #define DRV_MSG_CODE_VF_DISABLED_DONE           0xc0000000
3911 #define DRV_MSG_CODE_CFG_VF_MSIX                0xc0010000
3912 #define DRV_MSG_CODE_NVM_PUT_FILE_BEGIN         0x00010000
3913 #define DRV_MSG_CODE_NVM_PUT_FILE_DATA          0x00020000
3914 #define DRV_MSG_CODE_NVM_GET_FILE_ATT           0x00030000
3915 #define DRV_MSG_CODE_NVM_READ_NVRAM             0x00050000
3916 #define DRV_MSG_CODE_NVM_WRITE_NVRAM            0x00060000
3917 #define DRV_MSG_CODE_NVM_DEL_FILE               0x00080000
3918 #define DRV_MSG_CODE_MCP_RESET                  0x00090000
3919 #define DRV_MSG_CODE_SET_SECURE_MODE            0x000a0000
3920 #define DRV_MSG_CODE_PHY_RAW_READ               0x000b0000
3921 #define DRV_MSG_CODE_PHY_RAW_WRITE              0x000c0000
3922 #define DRV_MSG_CODE_PHY_CORE_READ              0x000d0000
3923 #define DRV_MSG_CODE_PHY_CORE_WRITE             0x000e0000
3924 #define DRV_MSG_CODE_SET_VERSION                0x000f0000
3925
3926 #define DRV_MSG_CODE_BIST_TEST                  0x001e0000
3927 #define DRV_MSG_CODE_SET_LED_MODE               0x00200000
3928
3929 #define DRV_MSG_SEQ_NUMBER_MASK                 0x0000ffff
3930
3931         u32 drv_mb_param;
3932
3933         /* UNLOAD_REQ params */
3934 #define DRV_MB_PARAM_UNLOAD_WOL_UNKNOWN         0x00000000
3935 #define DRV_MB_PARAM_UNLOAD_WOL_MCP             0x00000001
3936 #define DRV_MB_PARAM_UNLOAD_WOL_DISABLED        0x00000002
3937 #define DRV_MB_PARAM_UNLOAD_WOL_ENABLED         0x00000003
3938
3939         /* UNLOAD_DONE_params */
3940 #define DRV_MB_PARAM_UNLOAD_NON_D3_POWER        0x00000001
3941
3942         /* INIT_PHY params */
3943 #define DRV_MB_PARAM_INIT_PHY_FORCE             0x00000001
3944 #define DRV_MB_PARAM_INIT_PHY_DONT_CARE         0x00000002
3945
3946         /* LLDP / DCBX params*/
3947 #define DRV_MB_PARAM_LLDP_SEND_MASK             0x00000001
3948 #define DRV_MB_PARAM_LLDP_SEND_SHIFT            0
3949 #define DRV_MB_PARAM_LLDP_AGENT_MASK            0x00000006
3950 #define DRV_MB_PARAM_LLDP_AGENT_SHIFT           1
3951 #define DRV_MB_PARAM_DCBX_NOTIFY_MASK           0x00000008
3952 #define DRV_MB_PARAM_DCBX_NOTIFY_SHIFT          3
3953
3954 #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_MASK   0x000000FF
3955 #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_SHIFT  0
3956
3957 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MFW     0x1
3958 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_IMAGE   0x2
3959
3960 #define DRV_MB_PARAM_NVM_OFFSET_SHIFT           0
3961 #define DRV_MB_PARAM_NVM_OFFSET_MASK            0x00FFFFFF
3962 #define DRV_MB_PARAM_NVM_LEN_SHIFT              24
3963 #define DRV_MB_PARAM_NVM_LEN_MASK               0xFF000000
3964
3965 #define DRV_MB_PARAM_PHY_ADDR_SHIFT             0
3966 #define DRV_MB_PARAM_PHY_ADDR_MASK              0x1FF0FFFF
3967 #define DRV_MB_PARAM_PHY_LANE_SHIFT             16
3968 #define DRV_MB_PARAM_PHY_LANE_MASK              0x000F0000
3969 #define DRV_MB_PARAM_PHY_SELECT_PORT_SHIFT      29
3970 #define DRV_MB_PARAM_PHY_SELECT_PORT_MASK       0x20000000
3971 #define DRV_MB_PARAM_PHY_PORT_SHIFT             30
3972 #define DRV_MB_PARAM_PHY_PORT_MASK              0xc0000000
3973
3974 /* configure vf MSIX params*/
3975 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT    0
3976 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK     0x000000FF
3977 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT   8
3978 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK    0x0000FF00
3979
3980 #define DRV_MB_PARAM_SET_LED_MODE_OPER          0x0
3981 #define DRV_MB_PARAM_SET_LED_MODE_ON            0x1
3982 #define DRV_MB_PARAM_SET_LED_MODE_OFF           0x2
3983
3984 #define DRV_MB_PARAM_BIST_UNKNOWN_TEST          0
3985 #define DRV_MB_PARAM_BIST_REGISTER_TEST         1
3986 #define DRV_MB_PARAM_BIST_CLOCK_TEST            2
3987
3988 #define DRV_MB_PARAM_BIST_RC_UNKNOWN            0
3989 #define DRV_MB_PARAM_BIST_RC_PASSED             1
3990 #define DRV_MB_PARAM_BIST_RC_FAILED             2
3991 #define DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER          3
3992
3993 #define DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT      0
3994 #define DRV_MB_PARAM_BIST_TEST_INDEX_MASK       0x000000FF
3995
3996         u32 fw_mb_header;
3997 #define FW_MSG_CODE_MASK                        0xffff0000
3998 #define FW_MSG_CODE_DRV_LOAD_ENGINE             0x10100000
3999 #define FW_MSG_CODE_DRV_LOAD_PORT               0x10110000
4000 #define FW_MSG_CODE_DRV_LOAD_FUNCTION           0x10120000
4001 #define FW_MSG_CODE_DRV_LOAD_REFUSED_PDA        0x10200000
4002 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI        0x10210000
4003 #define FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG       0x10220000
4004 #define FW_MSG_CODE_DRV_LOAD_DONE               0x11100000
4005 #define FW_MSG_CODE_DRV_UNLOAD_ENGINE           0x20110000
4006 #define FW_MSG_CODE_DRV_UNLOAD_PORT             0x20120000
4007 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION         0x20130000
4008 #define FW_MSG_CODE_DRV_UNLOAD_DONE             0x21100000
4009 #define FW_MSG_CODE_INIT_PHY_DONE               0x21200000
4010 #define FW_MSG_CODE_INIT_PHY_ERR_INVALID_ARGS   0x21300000
4011 #define FW_MSG_CODE_LINK_RESET_DONE             0x23000000
4012 #define FW_MSG_CODE_SET_LLDP_DONE               0x24000000
4013 #define FW_MSG_CODE_SET_LLDP_UNSUPPORTED_AGENT  0x24010000
4014 #define FW_MSG_CODE_SET_DCBX_DONE               0x25000000
4015 #define FW_MSG_CODE_NIG_DRAIN_DONE              0x30000000
4016 #define FW_MSG_CODE_VF_DISABLED_DONE            0xb0000000
4017 #define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE        0xb0010000
4018 #define FW_MSG_CODE_FLR_ACK                     0x02000000
4019 #define FW_MSG_CODE_FLR_NACK                    0x02100000
4020
4021 #define FW_MSG_CODE_NVM_OK                      0x00010000
4022 #define FW_MSG_CODE_NVM_INVALID_MODE            0x00020000
4023 #define FW_MSG_CODE_NVM_PREV_CMD_WAS_NOT_FINISHED       0x00030000
4024 #define FW_MSG_CODE_NVM_FAILED_TO_ALLOCATE_PAGE 0x00040000
4025 #define FW_MSG_CODE_NVM_INVALID_DIR_FOUND       0x00050000
4026 #define FW_MSG_CODE_NVM_PAGE_NOT_FOUND          0x00060000
4027 #define FW_MSG_CODE_NVM_FAILED_PARSING_BNDLE_HEADER 0x00070000
4028 #define FW_MSG_CODE_NVM_FAILED_PARSING_IMAGE_HEADER 0x00080000
4029 #define FW_MSG_CODE_NVM_PARSING_OUT_OF_SYNC     0x00090000
4030 #define FW_MSG_CODE_NVM_FAILED_UPDATING_DIR     0x000a0000
4031 #define FW_MSG_CODE_NVM_FAILED_TO_FREE_PAGE     0x000b0000
4032 #define FW_MSG_CODE_NVM_FILE_NOT_FOUND          0x000c0000
4033 #define FW_MSG_CODE_NVM_OPERATION_FAILED        0x000d0000
4034 #define FW_MSG_CODE_NVM_FAILED_UNALIGNED        0x000e0000
4035 #define FW_MSG_CODE_NVM_BAD_OFFSET              0x000f0000
4036 #define FW_MSG_CODE_NVM_BAD_SIGNATURE           0x00100000
4037 #define FW_MSG_CODE_NVM_FILE_READ_ONLY          0x00200000
4038 #define FW_MSG_CODE_NVM_UNKNOWN_FILE            0x00300000
4039 #define FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK      0x00400000
4040 #define FW_MSG_CODE_MCP_RESET_REJECT            0x00600000
4041 #define FW_MSG_CODE_PHY_OK                      0x00110000
4042 #define FW_MSG_CODE_PHY_ERROR                   0x00120000
4043 #define FW_MSG_CODE_SET_SECURE_MODE_ERROR       0x00130000
4044 #define FW_MSG_CODE_SET_SECURE_MODE_OK          0x00140000
4045 #define FW_MSG_MODE_PHY_PRIVILEGE_ERROR         0x00150000
4046 #define FW_MSG_CODE_OK                          0x00160000
4047
4048 #define FW_MSG_SEQ_NUMBER_MASK                  0x0000ffff
4049
4050         u32     fw_mb_param;
4051
4052         u32     drv_pulse_mb;
4053 #define DRV_PULSE_SEQ_MASK                      0x00007fff
4054 #define DRV_PULSE_SYSTEM_TIME_MASK              0xffff0000
4055 #define DRV_PULSE_ALWAYS_ALIVE                  0x00008000
4056         u32 mcp_pulse_mb;
4057 #define MCP_PULSE_SEQ_MASK                      0x00007fff
4058 #define MCP_PULSE_ALWAYS_ALIVE                  0x00008000
4059 #define MCP_EVENT_MASK                          0xffff0000
4060 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ        0x00010000
4061
4062         union drv_union_data union_data;
4063 };
4064
4065 /* MFW - DRV MB */
4066 /**********************************************************************
4067 * Description
4068 *   Incremental Aggregative
4069 *   8-bit MFW counter per message
4070 *   8-bit ack-counter per message
4071 * Capabilities
4072 *   Provides up to 256 aggregative message per type
4073 *   Provides 4 message types in dword
4074 *   Message type pointers to byte offset
4075 *   Backward Compatibility by using sizeof for the counters.
4076 *   No lock requires for 32bit messages
4077 * Limitations:
4078 * In case of messages greater than 32bit, a dedicated mechanism(e.g lock)
4079 * is required to prevent data corruption.
4080 **********************************************************************/
4081 enum MFW_DRV_MSG_TYPE {
4082         MFW_DRV_MSG_LINK_CHANGE,
4083         MFW_DRV_MSG_FLR_FW_ACK_FAILED,
4084         MFW_DRV_MSG_VF_DISABLED,
4085         MFW_DRV_MSG_LLDP_DATA_UPDATED,
4086         MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED,
4087         MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED,
4088         MFW_DRV_MSG_ERROR_RECOVERY,
4089         MFW_DRV_MSG_BW_UPDATE,
4090         MFW_DRV_MSG_S_TAG_UPDATE,
4091         MFW_DRV_MSG_GET_LAN_STATS,
4092         MFW_DRV_MSG_GET_FCOE_STATS,
4093         MFW_DRV_MSG_GET_ISCSI_STATS,
4094         MFW_DRV_MSG_GET_RDMA_STATS,
4095         MFW_DRV_MSG_FAILURE_DETECTED,
4096         MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE,
4097         MFW_DRV_MSG_MAX
4098 };
4099
4100 #define MFW_DRV_MSG_MAX_DWORDS(msgs)    (((msgs - 1) >> 2) + 1)
4101 #define MFW_DRV_MSG_DWORD(msg_id)       (msg_id >> 2)
4102 #define MFW_DRV_MSG_OFFSET(msg_id)      ((msg_id & 0x3) << 3)
4103 #define MFW_DRV_MSG_MASK(msg_id)        (0xff << MFW_DRV_MSG_OFFSET(msg_id))
4104
4105 struct public_mfw_mb {
4106         u32     sup_msgs;
4107         u32     msg[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
4108         u32     ack[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
4109 };
4110
4111 /**************************************/
4112 /*                                    */
4113 /*     P U B L I C       D A T A      */
4114 /*                                    */
4115 /**************************************/
4116 enum public_sections {
4117         PUBLIC_DRV_MB,          /* Points to the first drv_mb of path0 */
4118         PUBLIC_MFW_MB,          /* Points to the first mfw_mb of path0 */
4119         PUBLIC_GLOBAL,
4120         PUBLIC_PATH,
4121         PUBLIC_PORT,
4122         PUBLIC_FUNC,
4123         PUBLIC_MAX_SECTIONS
4124 };
4125
4126 struct drv_ver_info_stc {
4127         u32     ver;
4128         u8      name[32];
4129 };
4130
4131 struct mcp_public_data {
4132         /* The sections fields is an array */
4133         u32                     num_sections;
4134         offsize_t               sections[PUBLIC_MAX_SECTIONS];
4135         struct public_drv_mb    drv_mb[MCP_GLOB_FUNC_MAX];
4136         struct public_mfw_mb    mfw_mb[MCP_GLOB_FUNC_MAX];
4137         struct public_global    global;
4138         struct public_path      path[MCP_GLOB_PATH_MAX];
4139         struct public_port      port[MCP_GLOB_PORT_MAX];
4140         struct public_func      func[MCP_GLOB_FUNC_MAX];
4141         struct drv_ver_info_stc drv_info;
4142 };
4143
4144 struct nvm_cfg_mac_address {
4145         u32     mac_addr_hi;
4146 #define NVM_CFG_MAC_ADDRESS_HI_MASK                             0x0000FFFF
4147 #define NVM_CFG_MAC_ADDRESS_HI_OFFSET                           0
4148
4149         u32     mac_addr_lo;
4150 };
4151
4152 /******************************************
4153 * nvm_cfg1 structs
4154 ******************************************/
4155
4156 struct nvm_cfg1_glob {
4157         u32 generic_cont0;                                      /* 0x0 */
4158 #define NVM_CFG1_GLOB_BOARD_SWAP_MASK                           0x0000000F
4159 #define NVM_CFG1_GLOB_BOARD_SWAP_OFFSET                         0
4160 #define NVM_CFG1_GLOB_BOARD_SWAP_NONE                           0x0
4161 #define NVM_CFG1_GLOB_BOARD_SWAP_PATH                           0x1
4162 #define NVM_CFG1_GLOB_BOARD_SWAP_PORT                           0x2
4163 #define NVM_CFG1_GLOB_BOARD_SWAP_BOTH                           0x3
4164 #define NVM_CFG1_GLOB_MF_MODE_MASK                              0x00000FF0
4165 #define NVM_CFG1_GLOB_MF_MODE_OFFSET                            4
4166 #define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED                        0x0
4167 #define NVM_CFG1_GLOB_MF_MODE_DEFAULT                           0x1
4168 #define NVM_CFG1_GLOB_MF_MODE_SPIO4                             0x2
4169 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_0                           0x3
4170 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_5                           0x4
4171 #define NVM_CFG1_GLOB_MF_MODE_NPAR2_0                           0x5
4172 #define NVM_CFG1_GLOB_MF_MODE_BD                                0x6
4173 #define NVM_CFG1_GLOB_MF_MODE_UFP                               0x7
4174 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_MASK              0x00001000
4175 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_OFFSET            12
4176 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_DISABLED          0x0
4177 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_ENABLED           0x1
4178 #define NVM_CFG1_GLOB_AVS_MARGIN_LOW_MASK                       0x001FE000
4179 #define NVM_CFG1_GLOB_AVS_MARGIN_LOW_OFFSET                     13
4180 #define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_MASK                      0x1FE00000
4181 #define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_OFFSET                    21
4182 #define NVM_CFG1_GLOB_ENABLE_SRIOV_MASK                         0x20000000
4183 #define NVM_CFG1_GLOB_ENABLE_SRIOV_OFFSET                       29
4184 #define NVM_CFG1_GLOB_ENABLE_SRIOV_DISABLED                     0x0
4185 #define NVM_CFG1_GLOB_ENABLE_SRIOV_ENABLED                      0x1
4186 #define NVM_CFG1_GLOB_ENABLE_ATC_MASK                           0x40000000
4187 #define NVM_CFG1_GLOB_ENABLE_ATC_OFFSET                         30
4188 #define NVM_CFG1_GLOB_ENABLE_ATC_DISABLED                       0x0
4189 #define NVM_CFG1_GLOB_ENABLE_ATC_ENABLED                        0x1
4190 #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_MASK                       0x80000000
4191 #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_OFFSET                     31
4192 #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_DISABLED                   0x0
4193 #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_ENABLED                    0x1
4194
4195         u32     engineering_change[3];                          /* 0x4 */
4196
4197         u32     manufacturing_id;                               /* 0x10 */
4198
4199         u32     serial_number[4];                               /* 0x14 */
4200
4201         u32     pcie_cfg;                                       /* 0x24 */
4202 #define NVM_CFG1_GLOB_PCI_GEN_MASK                              0x00000003
4203 #define NVM_CFG1_GLOB_PCI_GEN_OFFSET                            0
4204 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN1                          0x0
4205 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN2                          0x1
4206 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN3                          0x2
4207 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_MASK                   0x00000004
4208 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_OFFSET                 2
4209 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_DISABLED               0x0
4210 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_ENABLED                0x1
4211 #define NVM_CFG1_GLOB_ASPM_SUPPORT_MASK                         0x00000018
4212 #define NVM_CFG1_GLOB_ASPM_SUPPORT_OFFSET                       3
4213 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_ENABLED               0x0
4214 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_DISABLED                 0x1
4215 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L1_DISABLED                  0x2
4216 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_DISABLED              0x3
4217 #define NVM_CFG1_GLOB_PREVENT_PCIE_L1_MENTRY_MASK               0x00000020
4218 #define NVM_CFG1_GLOB_PREVENT_PCIE_L1_MENTRY_OFFSET             5
4219 #define NVM_CFG1_GLOB_PREVENT_PCIE_L1_MENTRY_DISABLED           0x0
4220 #define NVM_CFG1_GLOB_PREVENT_PCIE_L1_MENTRY_ENABLED            0x1
4221 #define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_MASK                 0x000003C0
4222 #define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_OFFSET               6
4223 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_MASK                     0x00001C00
4224 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_OFFSET                   10
4225 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_HW                       0x0
4226 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_0DB                      0x1
4227 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_3_5DB                    0x2
4228 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_6_0DB                    0x3
4229 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_MASK                     0x001FE000
4230 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_OFFSET                   13
4231 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_MASK                     0x1FE00000
4232 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_OFFSET                   21
4233 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_MASK                      0x60000000
4234 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_OFFSET                    29
4235
4236         u32 mgmt_traffic;                                       /* 0x28 */
4237 #define NVM_CFG1_GLOB_RESERVED60_MASK                           0x00000001
4238 #define NVM_CFG1_GLOB_RESERVED60_OFFSET                         0
4239 #define NVM_CFG1_GLOB_RESERVED60_100KHZ                         0x0
4240 #define NVM_CFG1_GLOB_RESERVED60_400KHZ                         0x1
4241 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_MASK                     0x000001FE
4242 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_OFFSET                   1
4243 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_MASK                     0x0001FE00
4244 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_OFFSET                   9
4245 #define NVM_CFG1_GLOB_SMBUS_ADDRESS_MASK                        0x01FE0000
4246 #define NVM_CFG1_GLOB_SMBUS_ADDRESS_OFFSET                      17
4247 #define NVM_CFG1_GLOB_SIDEBAND_MODE_MASK                        0x06000000
4248 #define NVM_CFG1_GLOB_SIDEBAND_MODE_OFFSET                      25
4249 #define NVM_CFG1_GLOB_SIDEBAND_MODE_DISABLED                    0x0
4250 #define NVM_CFG1_GLOB_SIDEBAND_MODE_RMII                        0x1
4251 #define NVM_CFG1_GLOB_SIDEBAND_MODE_SGMII                       0x2
4252
4253         u32 core_cfg;                                           /* 0x2C */
4254 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK                    0x000000FF
4255 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET                  0
4256 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X40G                0x0
4257 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X50G                0x1
4258 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X100G               0x2
4259 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_F              0x3
4260 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_E              0x4
4261 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X20G                0x5
4262 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X40G                0xB
4263 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X25G                0xC
4264 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X25G                0xD
4265 #define NVM_CFG1_GLOB_EAGLE_ENFORCE_TX_FIR_CFG_MASK             0x00000100
4266 #define NVM_CFG1_GLOB_EAGLE_ENFORCE_TX_FIR_CFG_OFFSET           8
4267 #define NVM_CFG1_GLOB_EAGLE_ENFORCE_TX_FIR_CFG_DISABLED         0x0
4268 #define NVM_CFG1_GLOB_EAGLE_ENFORCE_TX_FIR_CFG_ENABLED          0x1
4269 #define NVM_CFG1_GLOB_FALCON_ENFORCE_TX_FIR_CFG_MASK            0x00000200
4270 #define NVM_CFG1_GLOB_FALCON_ENFORCE_TX_FIR_CFG_OFFSET          9
4271 #define NVM_CFG1_GLOB_FALCON_ENFORCE_TX_FIR_CFG_DISABLED        0x0
4272 #define NVM_CFG1_GLOB_FALCON_ENFORCE_TX_FIR_CFG_ENABLED         0x1
4273 #define NVM_CFG1_GLOB_EAGLE_CORE_ADDR_MASK                      0x0003FC00
4274 #define NVM_CFG1_GLOB_EAGLE_CORE_ADDR_OFFSET                    10
4275 #define NVM_CFG1_GLOB_FALCON_CORE_ADDR_MASK                     0x03FC0000
4276 #define NVM_CFG1_GLOB_FALCON_CORE_ADDR_OFFSET                   18
4277 #define NVM_CFG1_GLOB_AVS_MODE_MASK                             0x1C000000
4278 #define NVM_CFG1_GLOB_AVS_MODE_OFFSET                           26
4279 #define NVM_CFG1_GLOB_AVS_MODE_CLOSE_LOOP                       0x0
4280 #define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP                        0x1
4281 #define NVM_CFG1_GLOB_AVS_MODE_DISABLED                         0x3
4282 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_MASK                 0x60000000
4283 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_OFFSET               29
4284 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_DISABLED             0x0
4285 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_ENABLED              0x1
4286
4287         u32 e_lane_cfg1;                                        /* 0x30 */
4288 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK                        0x0000000F
4289 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET                      0
4290 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK                        0x000000F0
4291 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET                      4
4292 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK                        0x00000F00
4293 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET                      8
4294 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK                        0x0000F000
4295 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET                      12
4296 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK                        0x000F0000
4297 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET                      16
4298 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK                        0x00F00000
4299 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET                      20
4300 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK                        0x0F000000
4301 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET                      24
4302 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK                        0xF0000000
4303 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET                      28
4304
4305         u32 e_lane_cfg2;                                        /* 0x34 */
4306 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK                    0x00000001
4307 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET                  0
4308 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK                    0x00000002
4309 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET                  1
4310 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK                    0x00000004
4311 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET                  2
4312 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK                    0x00000008
4313 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET                  3
4314 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK                    0x00000010
4315 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET                  4
4316 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK                    0x00000020
4317 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET                  5
4318 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK                    0x00000040
4319 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET                  6
4320 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK                    0x00000080
4321 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET                  7
4322 #define NVM_CFG1_GLOB_SMBUS_MODE_MASK                           0x00000F00
4323 #define NVM_CFG1_GLOB_SMBUS_MODE_OFFSET                         8
4324 #define NVM_CFG1_GLOB_SMBUS_MODE_DISABLED                       0x0
4325 #define NVM_CFG1_GLOB_SMBUS_MODE_100KHZ                         0x1
4326 #define NVM_CFG1_GLOB_SMBUS_MODE_400KHZ                         0x2
4327 #define NVM_CFG1_GLOB_NCSI_MASK                                 0x0000F000
4328 #define NVM_CFG1_GLOB_NCSI_OFFSET                               12
4329 #define NVM_CFG1_GLOB_NCSI_DISABLED                             0x0
4330 #define NVM_CFG1_GLOB_NCSI_ENABLED                              0x1
4331
4332         u32 f_lane_cfg1;                                        /* 0x38 */
4333 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK                        0x0000000F
4334 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET                      0
4335 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK                        0x000000F0
4336 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET                      4
4337 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK                        0x00000F00
4338 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET                      8
4339 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK                        0x0000F000
4340 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET                      12
4341 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK                        0x000F0000
4342 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET                      16
4343 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK                        0x00F00000
4344 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET                      20
4345 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK                        0x0F000000
4346 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET                      24
4347 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK                        0xF0000000
4348 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET                      28
4349
4350         u32 f_lane_cfg2;                                        /* 0x3C */
4351 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK                    0x00000001
4352 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET                  0
4353 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK                    0x00000002
4354 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET                  1
4355 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK                    0x00000004
4356 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET                  2
4357 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK                    0x00000008
4358 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET                  3
4359 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK                    0x00000010
4360 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET                  4
4361 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK                    0x00000020
4362 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET                  5
4363 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK                    0x00000040
4364 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET                  6
4365 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK                    0x00000080
4366 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET                  7
4367
4368         u32 eagle_preemphasis;                                  /* 0x40 */
4369 #define NVM_CFG1_GLOB_LANE0_PREEMP_MASK                         0x000000FF
4370 #define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET                       0
4371 #define NVM_CFG1_GLOB_LANE1_PREEMP_MASK                         0x0000FF00
4372 #define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET                       8
4373 #define NVM_CFG1_GLOB_LANE2_PREEMP_MASK                         0x00FF0000
4374 #define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET                       16
4375 #define NVM_CFG1_GLOB_LANE3_PREEMP_MASK                         0xFF000000
4376 #define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET                       24
4377
4378         u32 eagle_driver_current;                               /* 0x44 */
4379 #define NVM_CFG1_GLOB_LANE0_AMP_MASK                            0x000000FF
4380 #define NVM_CFG1_GLOB_LANE0_AMP_OFFSET                          0
4381 #define NVM_CFG1_GLOB_LANE1_AMP_MASK                            0x0000FF00
4382 #define NVM_CFG1_GLOB_LANE1_AMP_OFFSET                          8
4383 #define NVM_CFG1_GLOB_LANE2_AMP_MASK                            0x00FF0000
4384 #define NVM_CFG1_GLOB_LANE2_AMP_OFFSET                          16
4385 #define NVM_CFG1_GLOB_LANE3_AMP_MASK                            0xFF000000
4386 #define NVM_CFG1_GLOB_LANE3_AMP_OFFSET                          24
4387
4388         u32 falcon_preemphasis;                                 /* 0x48 */
4389 #define NVM_CFG1_GLOB_LANE0_PREEMP_MASK                         0x000000FF
4390 #define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET                       0
4391 #define NVM_CFG1_GLOB_LANE1_PREEMP_MASK                         0x0000FF00
4392 #define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET                       8
4393 #define NVM_CFG1_GLOB_LANE2_PREEMP_MASK                         0x00FF0000
4394 #define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET                       16
4395 #define NVM_CFG1_GLOB_LANE3_PREEMP_MASK                         0xFF000000
4396 #define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET                       24
4397
4398         u32 falcon_driver_current;                              /* 0x4C */
4399 #define NVM_CFG1_GLOB_LANE0_AMP_MASK                            0x000000FF
4400 #define NVM_CFG1_GLOB_LANE0_AMP_OFFSET                          0
4401 #define NVM_CFG1_GLOB_LANE1_AMP_MASK                            0x0000FF00
4402 #define NVM_CFG1_GLOB_LANE1_AMP_OFFSET                          8
4403 #define NVM_CFG1_GLOB_LANE2_AMP_MASK                            0x00FF0000
4404 #define NVM_CFG1_GLOB_LANE2_AMP_OFFSET                          16
4405 #define NVM_CFG1_GLOB_LANE3_AMP_MASK                            0xFF000000
4406 #define NVM_CFG1_GLOB_LANE3_AMP_OFFSET                          24
4407
4408         u32     pci_id;                                         /* 0x50 */
4409 #define NVM_CFG1_GLOB_VENDOR_ID_MASK                            0x0000FFFF
4410 #define NVM_CFG1_GLOB_VENDOR_ID_OFFSET                          0
4411
4412         u32     pci_subsys_id;                                  /* 0x54 */
4413 #define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_MASK                  0x0000FFFF
4414 #define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_OFFSET                0
4415 #define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_MASK                  0xFFFF0000
4416 #define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_OFFSET                16
4417
4418         u32     bar;                                            /* 0x58 */
4419 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_MASK                   0x0000000F
4420 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_OFFSET                 0
4421 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_DISABLED               0x0
4422 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2K                     0x1
4423 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4K                     0x2
4424 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8K                     0x3
4425 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16K                    0x4
4426 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32K                    0x5
4427 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_64K                    0x6
4428 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_128K                   0x7
4429 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_256K                   0x8
4430 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_512K                   0x9
4431 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_1M                     0xA
4432 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2M                     0xB
4433 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4M                     0xC
4434 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8M                     0xD
4435 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16M                    0xE
4436 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32M                    0xF
4437 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_MASK                     0x000000F0
4438 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_OFFSET                   4
4439 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_DISABLED                 0x0
4440 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4K                       0x1
4441 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8K                       0x2
4442 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16K                      0x3
4443 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32K                      0x4
4444 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64K                      0x5
4445 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_128K                     0x6
4446 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_256K                     0x7
4447 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_512K                     0x8
4448 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_1M                       0x9
4449 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_2M                       0xA
4450 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4M                       0xB
4451 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8M                       0xC
4452 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16M                      0xD
4453 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32M                      0xE
4454 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64M                      0xF
4455 #define NVM_CFG1_GLOB_BAR2_SIZE_MASK                            0x00000F00
4456 #define NVM_CFG1_GLOB_BAR2_SIZE_OFFSET                          8
4457 #define NVM_CFG1_GLOB_BAR2_SIZE_DISABLED                        0x0
4458 #define NVM_CFG1_GLOB_BAR2_SIZE_64K                             0x1
4459 #define NVM_CFG1_GLOB_BAR2_SIZE_128K                            0x2
4460 #define NVM_CFG1_GLOB_BAR2_SIZE_256K                            0x3
4461 #define NVM_CFG1_GLOB_BAR2_SIZE_512K                            0x4
4462 #define NVM_CFG1_GLOB_BAR2_SIZE_1M                              0x5
4463 #define NVM_CFG1_GLOB_BAR2_SIZE_2M                              0x6
4464 #define NVM_CFG1_GLOB_BAR2_SIZE_4M                              0x7
4465 #define NVM_CFG1_GLOB_BAR2_SIZE_8M                              0x8
4466 #define NVM_CFG1_GLOB_BAR2_SIZE_16M                             0x9
4467 #define NVM_CFG1_GLOB_BAR2_SIZE_32M                             0xA
4468 #define NVM_CFG1_GLOB_BAR2_SIZE_64M                             0xB
4469 #define NVM_CFG1_GLOB_BAR2_SIZE_128M                            0xC
4470 #define NVM_CFG1_GLOB_BAR2_SIZE_256M                            0xD
4471 #define NVM_CFG1_GLOB_BAR2_SIZE_512M                            0xE
4472 #define NVM_CFG1_GLOB_BAR2_SIZE_1G                              0xF
4473
4474         u32 eagle_txfir_main;                                   /* 0x5C */
4475 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK                     0x000000FF
4476 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET                   0
4477 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK                     0x0000FF00
4478 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET                   8
4479 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK                     0x00FF0000
4480 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET                   16
4481 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK                     0xFF000000
4482 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET                   24
4483
4484         u32 eagle_txfir_post;                                   /* 0x60 */
4485 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK                     0x000000FF
4486 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET                   0
4487 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK                     0x0000FF00
4488 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET                   8
4489 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK                     0x00FF0000
4490 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET                   16
4491 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK                     0xFF000000
4492 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET                   24
4493
4494         u32 falcon_txfir_main;                                  /* 0x64 */
4495 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK                     0x000000FF
4496 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET                   0
4497 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK                     0x0000FF00
4498 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET                   8
4499 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK                     0x00FF0000
4500 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET                   16
4501 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK                     0xFF000000
4502 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET                   24
4503
4504         u32 falcon_txfir_post;                                  /* 0x68 */
4505 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK                     0x000000FF
4506 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET                   0
4507 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK                     0x0000FF00
4508 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET                   8
4509 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK                     0x00FF0000
4510 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET                   16
4511 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK                     0xFF000000
4512 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET                   24
4513
4514         u32 manufacture_ver;                                    /* 0x6C */
4515 #define NVM_CFG1_GLOB_MANUF0_VER_MASK                           0x0000003F
4516 #define NVM_CFG1_GLOB_MANUF0_VER_OFFSET                         0
4517 #define NVM_CFG1_GLOB_MANUF1_VER_MASK                           0x00000FC0
4518 #define NVM_CFG1_GLOB_MANUF1_VER_OFFSET                         6
4519 #define NVM_CFG1_GLOB_MANUF2_VER_MASK                           0x0003F000
4520 #define NVM_CFG1_GLOB_MANUF2_VER_OFFSET                         12
4521 #define NVM_CFG1_GLOB_MANUF3_VER_MASK                           0x00FC0000
4522 #define NVM_CFG1_GLOB_MANUF3_VER_OFFSET                         18
4523 #define NVM_CFG1_GLOB_MANUF4_VER_MASK                           0x3F000000
4524 #define NVM_CFG1_GLOB_MANUF4_VER_OFFSET                         24
4525
4526         u32 manufacture_time;                                   /* 0x70 */
4527 #define NVM_CFG1_GLOB_MANUF0_TIME_MASK                          0x0000003F
4528 #define NVM_CFG1_GLOB_MANUF0_TIME_OFFSET                        0
4529 #define NVM_CFG1_GLOB_MANUF1_TIME_MASK                          0x00000FC0
4530 #define NVM_CFG1_GLOB_MANUF1_TIME_OFFSET                        6
4531 #define NVM_CFG1_GLOB_MANUF2_TIME_MASK                          0x0003F000
4532 #define NVM_CFG1_GLOB_MANUF2_TIME_OFFSET                        12
4533
4534         u32 led_global_settings;                                /* 0x74 */
4535 #define NVM_CFG1_GLOB_LED_SWAP_0_MASK                           0x0000000F
4536 #define NVM_CFG1_GLOB_LED_SWAP_0_OFFSET                         0
4537 #define NVM_CFG1_GLOB_LED_SWAP_1_MASK                           0x000000F0
4538 #define NVM_CFG1_GLOB_LED_SWAP_1_OFFSET                         4
4539 #define NVM_CFG1_GLOB_LED_SWAP_2_MASK                           0x00000F00
4540 #define NVM_CFG1_GLOB_LED_SWAP_2_OFFSET                         8
4541 #define NVM_CFG1_GLOB_LED_SWAP_3_MASK                           0x0000F000
4542 #define NVM_CFG1_GLOB_LED_SWAP_3_OFFSET                         12
4543
4544         u32     generic_cont1;                                  /* 0x78 */
4545 #define NVM_CFG1_GLOB_AVS_DAC_CODE_MASK                         0x000003FF
4546 #define NVM_CFG1_GLOB_AVS_DAC_CODE_OFFSET                       0
4547
4548         u32     mbi_version;                                    /* 0x7C */
4549 #define NVM_CFG1_GLOB_MBI_VERSION_0_MASK                        0x000000FF
4550 #define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET                      0
4551 #define NVM_CFG1_GLOB_MBI_VERSION_1_MASK                        0x0000FF00
4552 #define NVM_CFG1_GLOB_MBI_VERSION_1_OFFSET                      8
4553 #define NVM_CFG1_GLOB_MBI_VERSION_2_MASK                        0x00FF0000
4554 #define NVM_CFG1_GLOB_MBI_VERSION_2_OFFSET                      16
4555
4556         u32     mbi_date;                                       /* 0x80 */
4557
4558         u32     misc_sig;                                       /* 0x84 */
4559
4560         /*  Define the GPIO mapping to switch i2c mux */
4561 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_MASK                   0x000000FF
4562 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_OFFSET                 0
4563 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_MASK                   0x0000FF00
4564 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_OFFSET                 8
4565 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__NA                      0x0
4566 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO0                   0x1
4567 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO1                   0x2
4568 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO2                   0x3
4569 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO3                   0x4
4570 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO4                   0x5
4571 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO5                   0x6
4572 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO6                   0x7
4573 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO7                   0x8
4574 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO8                   0x9
4575 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO9                   0xA
4576 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO10                  0xB
4577 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO11                  0xC
4578 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO12                  0xD
4579 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO13                  0xE
4580 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO14                  0xF
4581 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO15                  0x10
4582 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO16                  0x11
4583 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO17                  0x12
4584 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO18                  0x13
4585 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO19                  0x14
4586 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO20                  0x15
4587 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO21                  0x16
4588 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO22                  0x17
4589 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO23                  0x18
4590 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO24                  0x19
4591 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO25                  0x1A
4592 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO26                  0x1B
4593 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO27                  0x1C
4594 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO28                  0x1D
4595 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO29                  0x1E
4596 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO30                  0x1F
4597 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO31                  0x20
4598         u32     device_capabilities;                            /* 0x88 */
4599 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET              0x1
4600         u32     power_dissipated;                               /* 0x8C */
4601         u32 power_consumed;                                     /* 0x90 */
4602         u32     efi_version;                                    /* 0x94 */
4603         u32     reserved[42];                                   /* 0x98 */
4604 };
4605
4606 struct nvm_cfg1_path {
4607         u32 reserved[30];                                       /* 0x0 */
4608 };
4609
4610 struct nvm_cfg1_port {
4611         u32     reserved__m_relocated_to_option_123;           /* 0x0 */
4612         u32     reserved__m_relocated_to_option_124;           /* 0x4 */
4613         u32 generic_cont0;                                      /* 0x8 */
4614 #define NVM_CFG1_PORT_LED_MODE_MASK                             0x000000FF
4615 #define NVM_CFG1_PORT_LED_MODE_OFFSET                           0
4616 #define NVM_CFG1_PORT_LED_MODE_MAC1                             0x0
4617 #define NVM_CFG1_PORT_LED_MODE_PHY1                             0x1
4618 #define NVM_CFG1_PORT_LED_MODE_PHY2                             0x2
4619 #define NVM_CFG1_PORT_LED_MODE_PHY3                             0x3
4620 #define NVM_CFG1_PORT_LED_MODE_MAC2                             0x4
4621 #define NVM_CFG1_PORT_LED_MODE_PHY4                             0x5
4622 #define NVM_CFG1_PORT_LED_MODE_PHY5                             0x6
4623 #define NVM_CFG1_PORT_LED_MODE_PHY6                             0x7
4624 #define NVM_CFG1_PORT_LED_MODE_MAC3                             0x8
4625 #define NVM_CFG1_PORT_LED_MODE_PHY7                             0x9
4626 #define NVM_CFG1_PORT_LED_MODE_PHY8                             0xA
4627 #define NVM_CFG1_PORT_LED_MODE_PHY9                             0xB
4628 #define NVM_CFG1_PORT_LED_MODE_MAC4                             0xC
4629 #define NVM_CFG1_PORT_LED_MODE_PHY10                            0xD
4630 #define NVM_CFG1_PORT_LED_MODE_PHY11                            0xE
4631 #define NVM_CFG1_PORT_LED_MODE_PHY12                            0xF
4632 #define NVM_CFG1_PORT_ROCE_PRIORITY_MASK                        0x0000FF00
4633 #define NVM_CFG1_PORT_ROCE_PRIORITY_OFFSET                      8
4634 #define NVM_CFG1_PORT_DCBX_MODE_MASK                            0x000F0000
4635 #define NVM_CFG1_PORT_DCBX_MODE_OFFSET                          16
4636 #define NVM_CFG1_PORT_DCBX_MODE_DISABLED                        0x0
4637 #define NVM_CFG1_PORT_DCBX_MODE_IEEE                            0x1
4638 #define NVM_CFG1_PORT_DCBX_MODE_CEE                             0x2
4639 #define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC                         0x3
4640 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK            0x00F00000
4641 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_OFFSET          20
4642 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET        0x1
4643         u32     pcie_cfg;                                       /* 0xC */
4644 #define NVM_CFG1_PORT_RESERVED15_MASK                           0x00000007
4645 #define NVM_CFG1_PORT_RESERVED15_OFFSET                         0
4646
4647         u32     features;                                       /* 0x10 */
4648 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_MASK           0x00000001
4649 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_OFFSET         0
4650 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_DISABLED       0x0
4651 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_ENABLED        0x1
4652 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_MASK                     0x00000002
4653 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_OFFSET                   1
4654 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_DISABLED                 0x0
4655 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_ENABLED                  0x1
4656
4657         u32 speed_cap_mask;                                     /* 0x14 */
4658 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK            0x0000FFFF
4659 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET          0
4660 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G              0x1
4661 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G             0x2
4662 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G             0x8
4663 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G             0x10
4664 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G             0x20
4665 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_100G            0x40
4666 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_MASK            0xFFFF0000
4667 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_OFFSET          16
4668 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_1G              0x1
4669 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_10G             0x2
4670 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_25G             0x8
4671 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_40G             0x10
4672 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_50G             0x20
4673 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_100G            0x40
4674
4675         u32 link_settings;                                      /* 0x18 */
4676 #define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK                       0x0000000F
4677 #define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET                     0
4678 #define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG                    0x0
4679 #define NVM_CFG1_PORT_DRV_LINK_SPEED_1G                         0x1
4680 #define NVM_CFG1_PORT_DRV_LINK_SPEED_10G                        0x2
4681 #define NVM_CFG1_PORT_DRV_LINK_SPEED_25G                        0x4
4682 #define NVM_CFG1_PORT_DRV_LINK_SPEED_40G                        0x5
4683 #define NVM_CFG1_PORT_DRV_LINK_SPEED_50G                        0x6
4684 #define NVM_CFG1_PORT_DRV_LINK_SPEED_100G                       0x7
4685 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK                     0x00000070
4686 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET                   4
4687 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG                  0x1
4688 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX                       0x2
4689 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX                       0x4
4690 #define NVM_CFG1_PORT_MFW_LINK_SPEED_MASK                       0x00000780
4691 #define NVM_CFG1_PORT_MFW_LINK_SPEED_OFFSET                     7
4692 #define NVM_CFG1_PORT_MFW_LINK_SPEED_AUTONEG                    0x0
4693 #define NVM_CFG1_PORT_MFW_LINK_SPEED_1G                         0x1
4694 #define NVM_CFG1_PORT_MFW_LINK_SPEED_10G                        0x2
4695 #define NVM_CFG1_PORT_MFW_LINK_SPEED_25G                        0x4
4696 #define NVM_CFG1_PORT_MFW_LINK_SPEED_40G                        0x5
4697 #define NVM_CFG1_PORT_MFW_LINK_SPEED_50G                        0x6
4698 #define NVM_CFG1_PORT_MFW_LINK_SPEED_100G                       0x7
4699 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_MASK                     0x00003800
4700 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_OFFSET                   11
4701 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_AUTONEG                  0x1
4702 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_RX                       0x2
4703 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_TX                       0x4
4704 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_MASK      0x00004000
4705 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_OFFSET    14
4706 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_DISABLED  0x0
4707 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_ENABLED   0x1
4708
4709         u32 phy_cfg;                                            /* 0x1C */
4710 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_MASK                  0x0000FFFF
4711 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_OFFSET                0
4712 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_HIGIG                 0x1
4713 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_SCRAMBLER             0x2
4714 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_FIBER                 0x4
4715 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_CL72_AN       0x8
4716 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_FEC_AN        0x10
4717 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_MASK                 0x00FF0000
4718 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_OFFSET               16
4719 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_BYPASS               0x0
4720 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR                   0x2
4721 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR2                  0x3
4722 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR4                  0x4
4723 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XFI                  0x8
4724 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SFI                  0x9
4725 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_1000X                0xB
4726 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SGMII                0xC
4727 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLAUI                0x11
4728 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLPPI                0x12
4729 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CAUI                 0x21
4730 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CPPI                 0x22
4731 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_25GAUI               0x31
4732 #define NVM_CFG1_PORT_AN_MODE_MASK                              0xFF000000
4733 #define NVM_CFG1_PORT_AN_MODE_OFFSET                            24
4734 #define NVM_CFG1_PORT_AN_MODE_NONE                              0x0
4735 #define NVM_CFG1_PORT_AN_MODE_CL73                              0x1
4736 #define NVM_CFG1_PORT_AN_MODE_CL37                              0x2
4737 #define NVM_CFG1_PORT_AN_MODE_CL73_BAM                          0x3
4738 #define NVM_CFG1_PORT_AN_MODE_CL37_BAM                          0x4
4739 #define NVM_CFG1_PORT_AN_MODE_HPAM                              0x5
4740 #define NVM_CFG1_PORT_AN_MODE_SGMII                             0x6
4741
4742         u32 mgmt_traffic;                                       /* 0x20 */
4743 #define NVM_CFG1_PORT_RESERVED61_MASK                           0x0000000F
4744 #define NVM_CFG1_PORT_RESERVED61_OFFSET                         0
4745
4746         u32 ext_phy;                                            /* 0x24 */
4747 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_MASK                    0x000000FF
4748 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_OFFSET                  0
4749 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_NONE                    0x0
4750 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_BCM84844                0x1
4751 #define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_MASK                 0x0000FF00
4752 #define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_OFFSET               8
4753
4754         u32 mba_cfg1;                                           /* 0x28 */
4755 #define NVM_CFG1_PORT_PREBOOT_OPROM_MASK                        0x00000001
4756 #define NVM_CFG1_PORT_PREBOOT_OPROM_OFFSET                      0
4757 #define NVM_CFG1_PORT_PREBOOT_OPROM_DISABLED                    0x0
4758 #define NVM_CFG1_PORT_PREBOOT_OPROM_ENABLED                     0x1
4759 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_MASK            0x00000006
4760 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_OFFSET          1
4761 #define NVM_CFG1_PORT_MBA_DELAY_TIME_MASK                       0x00000078
4762 #define NVM_CFG1_PORT_MBA_DELAY_TIME_OFFSET                     3
4763 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_MASK                    0x00000080
4764 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_OFFSET                  7
4765 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_S                  0x0
4766 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_B                  0x1
4767 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_MASK                0x00000100
4768 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_OFFSET              8
4769 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_DISABLED            0x0
4770 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_ENABLED             0x1
4771 #define NVM_CFG1_PORT_RESERVED5_MASK                            0x0001FE00
4772 #define NVM_CFG1_PORT_RESERVED5_OFFSET                          9
4773 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_MASK                   0x001E0000
4774 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_OFFSET                 17
4775 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_AUTONEG                0x0
4776 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_1G                     0x1
4777 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_10G                    0x2
4778 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_25G                    0x4
4779 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_40G                    0x5
4780 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_50G                    0x6
4781 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_100G                   0x7
4782 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_SMARTLINQ              0x8
4783 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_MASK     0x00E00000
4784 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_OFFSET   21
4785
4786         u32     mba_cfg2;                                       /* 0x2C */
4787 #define NVM_CFG1_PORT_RESERVED65_MASK                           0x0000FFFF
4788 #define NVM_CFG1_PORT_RESERVED65_OFFSET                         0
4789 #define NVM_CFG1_PORT_RESERVED66_MASK                           0x00010000
4790 #define NVM_CFG1_PORT_RESERVED66_OFFSET                         16
4791
4792         u32     vf_cfg;                                         /* 0x30 */
4793 #define NVM_CFG1_PORT_RESERVED8_MASK                            0x0000FFFF
4794 #define NVM_CFG1_PORT_RESERVED8_OFFSET                          0
4795 #define NVM_CFG1_PORT_RESERVED6_MASK                            0x000F0000
4796 #define NVM_CFG1_PORT_RESERVED6_OFFSET                          16
4797
4798         struct nvm_cfg_mac_address      lldp_mac_address;       /* 0x34 */
4799
4800         u32                             led_port_settings;      /* 0x3C */
4801 #define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_MASK                   0x000000FF
4802 #define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_OFFSET                 0
4803 #define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_MASK                   0x0000FF00
4804 #define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_OFFSET                 8
4805 #define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_MASK                   0x00FF0000
4806 #define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_OFFSET                 16
4807 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_1G                      0x1
4808 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_10G                     0x2
4809 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_25G                     0x8
4810 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_40G                     0x10
4811 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_50G                     0x20
4812 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_100G                    0x40
4813
4814         u32 transceiver_00;                                     /* 0x40 */
4815
4816         /*  Define for mapping of transceiver signal module absent */
4817 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_MASK                     0x000000FF
4818 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_OFFSET                   0
4819 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_NA                       0x0
4820 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO0                    0x1
4821 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO1                    0x2
4822 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO2                    0x3
4823 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO3                    0x4
4824 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO4                    0x5
4825 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO5                    0x6
4826 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO6                    0x7
4827 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO7                    0x8
4828 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO8                    0x9
4829 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO9                    0xA
4830 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO10                   0xB
4831 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO11                   0xC
4832 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO12                   0xD
4833 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO13                   0xE
4834 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO14                   0xF
4835 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO15                   0x10
4836 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO16                   0x11
4837 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO17                   0x12
4838 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO18                   0x13
4839 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO19                   0x14
4840 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO20                   0x15
4841 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO21                   0x16
4842 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO22                   0x17
4843 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO23                   0x18
4844 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO24                   0x19
4845 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO25                   0x1A
4846 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO26                   0x1B
4847 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO27                   0x1C
4848 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO28                   0x1D
4849 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO29                   0x1E
4850 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO30                   0x1F
4851 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO31                   0x20
4852         /*  Define the GPIO mux settings  to switch i2c mux to this port */
4853 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_MASK                  0x00000F00
4854 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_OFFSET                8
4855 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_MASK                  0x0000F000
4856 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_OFFSET                12
4857
4858         u32 reserved[133];                                      /* 0x44 */
4859 };
4860
4861 struct nvm_cfg1_func {
4862         struct nvm_cfg_mac_address      mac_address;            /* 0x0 */
4863
4864         u32                             rsrv1;                  /* 0x8 */
4865 #define NVM_CFG1_FUNC_RESERVED1_MASK                            0x0000FFFF
4866 #define NVM_CFG1_FUNC_RESERVED1_OFFSET                          0
4867 #define NVM_CFG1_FUNC_RESERVED2_MASK                            0xFFFF0000
4868 #define NVM_CFG1_FUNC_RESERVED2_OFFSET                          16
4869
4870         u32                             rsrv2;                  /* 0xC */
4871 #define NVM_CFG1_FUNC_RESERVED3_MASK                            0x0000FFFF
4872 #define NVM_CFG1_FUNC_RESERVED3_OFFSET                          0
4873 #define NVM_CFG1_FUNC_RESERVED4_MASK                            0xFFFF0000
4874 #define NVM_CFG1_FUNC_RESERVED4_OFFSET                          16
4875
4876         u32                             device_id;              /* 0x10 */
4877 #define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_MASK                  0x0000FFFF
4878 #define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_OFFSET                0
4879 #define NVM_CFG1_FUNC_RESERVED77_MASK                           0xFFFF0000
4880 #define NVM_CFG1_FUNC_RESERVED77_OFFSET                         16
4881
4882         u32                             cmn_cfg;                /* 0x14 */
4883 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_MASK                0x00000007
4884 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_OFFSET              0
4885 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_PXE                 0x0
4886 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_ISCSI_BOOT          0x3
4887 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_FCOE_BOOT           0x4
4888 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_NONE                0x7
4889 #define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_MASK                     0x0007FFF8
4890 #define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_OFFSET                   3
4891 #define NVM_CFG1_FUNC_PERSONALITY_MASK                          0x00780000
4892 #define NVM_CFG1_FUNC_PERSONALITY_OFFSET                        19
4893 #define NVM_CFG1_FUNC_PERSONALITY_ETHERNET                      0x0
4894 #define NVM_CFG1_FUNC_PERSONALITY_ISCSI                         0x1
4895 #define NVM_CFG1_FUNC_PERSONALITY_FCOE                          0x2
4896 #define NVM_CFG1_FUNC_PERSONALITY_ROCE                          0x3
4897 #define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_MASK                     0x7F800000
4898 #define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_OFFSET                   23
4899 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_MASK                   0x80000000
4900 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_OFFSET                 31
4901 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_DISABLED               0x0
4902 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_ENABLED                0x1
4903
4904         u32 pci_cfg;                                            /* 0x18 */
4905 #define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_MASK                 0x0000007F
4906 #define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_OFFSET               0
4907 #define NVM_CFG1_FUNC_RESERVESD12_MASK                          0x00003F80
4908 #define NVM_CFG1_FUNC_RESERVESD12_OFFSET                        7
4909 #define NVM_CFG1_FUNC_BAR1_SIZE_MASK                            0x0003C000
4910 #define NVM_CFG1_FUNC_BAR1_SIZE_OFFSET                          14
4911 #define NVM_CFG1_FUNC_BAR1_SIZE_DISABLED                        0x0
4912 #define NVM_CFG1_FUNC_BAR1_SIZE_64K                             0x1
4913 #define NVM_CFG1_FUNC_BAR1_SIZE_128K                            0x2
4914 #define NVM_CFG1_FUNC_BAR1_SIZE_256K                            0x3
4915 #define NVM_CFG1_FUNC_BAR1_SIZE_512K                            0x4
4916 #define NVM_CFG1_FUNC_BAR1_SIZE_1M                              0x5
4917 #define NVM_CFG1_FUNC_BAR1_SIZE_2M                              0x6
4918 #define NVM_CFG1_FUNC_BAR1_SIZE_4M                              0x7
4919 #define NVM_CFG1_FUNC_BAR1_SIZE_8M                              0x8
4920 #define NVM_CFG1_FUNC_BAR1_SIZE_16M                             0x9
4921 #define NVM_CFG1_FUNC_BAR1_SIZE_32M                             0xA
4922 #define NVM_CFG1_FUNC_BAR1_SIZE_64M                             0xB
4923 #define NVM_CFG1_FUNC_BAR1_SIZE_128M                            0xC
4924 #define NVM_CFG1_FUNC_BAR1_SIZE_256M                            0xD
4925 #define NVM_CFG1_FUNC_BAR1_SIZE_512M                            0xE
4926 #define NVM_CFG1_FUNC_BAR1_SIZE_1G                              0xF
4927 #define NVM_CFG1_FUNC_MAX_BANDWIDTH_MASK                        0x03FC0000
4928 #define NVM_CFG1_FUNC_MAX_BANDWIDTH_OFFSET                      18
4929
4930         struct nvm_cfg_mac_address      fcoe_node_wwn_mac_addr; /* 0x1C */
4931
4932         struct nvm_cfg_mac_address      fcoe_port_wwn_mac_addr; /* 0x24 */
4933         u32                             preboot_generic_cfg;    /* 0x2C */
4934         u32                             reserved[8];            /* 0x30 */
4935 };
4936
4937 struct nvm_cfg1 {
4938         struct nvm_cfg1_glob    glob;                           /* 0x0 */
4939
4940         struct nvm_cfg1_path    path[MCP_GLOB_PATH_MAX];        /* 0x140 */
4941
4942         struct nvm_cfg1_port    port[MCP_GLOB_PORT_MAX];        /* 0x230 */
4943
4944         struct nvm_cfg1_func    func[MCP_GLOB_FUNC_MAX];        /* 0xB90 */
4945 };
4946
4947 /******************************************
4948 * nvm_cfg structs
4949 ******************************************/
4950
4951 enum nvm_cfg_sections {
4952         NVM_CFG_SECTION_NVM_CFG1,
4953         NVM_CFG_SECTION_MAX
4954 };
4955
4956 struct nvm_cfg {
4957         u32             num_sections;
4958         u32             sections_offset[NVM_CFG_SECTION_MAX];
4959         struct nvm_cfg1 cfg1;
4960 };
4961
4962 #define PORT_0          0
4963 #define PORT_1          1
4964 #define PORT_2          2
4965 #define PORT_3          3
4966
4967 extern struct spad_layout g_spad;
4968
4969 #define MCP_SPAD_SIZE                       0x00028000  /* 160 KB */
4970
4971 #define SPAD_OFFSET(addr) (((u32)addr - (u32)CPU_SPAD_BASE))
4972
4973 #define TO_OFFSIZE(_offset, _size)                              \
4974         (u32)((((u32)(_offset) >> 2) << OFFSIZE_OFFSET_SHIFT) | \
4975               (((u32)(_size) >> 2) << OFFSIZE_SIZE_SHIFT))
4976
4977 enum spad_sections {
4978         SPAD_SECTION_TRACE,
4979         SPAD_SECTION_NVM_CFG,
4980         SPAD_SECTION_PUBLIC,
4981         SPAD_SECTION_PRIVATE,
4982         SPAD_SECTION_MAX
4983 };
4984
4985 struct spad_layout {
4986         struct nvm_cfg          nvm_cfg;
4987         struct mcp_public_data  public_data;
4988 };
4989
4990 #define CRC_MAGIC_VALUE                     0xDEBB20E3
4991 #define CRC32_POLYNOMIAL                    0xEDB88320
4992 #define NVM_CRC_SIZE                            (sizeof(u32))
4993
4994 enum nvm_sw_arbitrator {
4995         NVM_SW_ARB_HOST,
4996         NVM_SW_ARB_MCP,
4997         NVM_SW_ARB_UART,
4998         NVM_SW_ARB_RESERVED
4999 };
5000
5001 /****************************************************************************
5002 * Boot Strap Region                                                        *
5003 ****************************************************************************/
5004 struct legacy_bootstrap_region {
5005         u32     magic_value;
5006 #define NVM_MAGIC_VALUE          0x669955aa
5007         u32     sram_start_addr;
5008         u32     code_len;               /* boot code length (in dwords) */
5009         u32     code_start_addr;
5010         u32     crc;                    /* 32-bit CRC */
5011 };
5012
5013 /****************************************************************************
5014 * Directories Region                                                       *
5015 ****************************************************************************/
5016 struct nvm_code_entry {
5017         u32     image_type;             /* Image type */
5018         u32     nvm_start_addr;         /* NVM address of the image */
5019         u32     len;                    /* Include CRC */
5020         u32     sram_start_addr;
5021         u32     sram_run_addr;          /* Relevant in case of MIM only */
5022 };
5023
5024 enum nvm_image_type {
5025         NVM_TYPE_TIM1           = 0x01,
5026         NVM_TYPE_TIM2           = 0x02,
5027         NVM_TYPE_MIM1           = 0x03,
5028         NVM_TYPE_MIM2           = 0x04,
5029         NVM_TYPE_MBA            = 0x05,
5030         NVM_TYPE_MODULES_PN     = 0x06,
5031         NVM_TYPE_VPD            = 0x07,
5032         NVM_TYPE_MFW_TRACE1     = 0x08,
5033         NVM_TYPE_MFW_TRACE2     = 0x09,
5034         NVM_TYPE_NVM_CFG1       = 0x0a,
5035         NVM_TYPE_L2B            = 0x0b,
5036         NVM_TYPE_DIR1           = 0x0c,
5037         NVM_TYPE_EAGLE_FW1      = 0x0d,
5038         NVM_TYPE_FALCON_FW1     = 0x0e,
5039         NVM_TYPE_PCIE_FW1       = 0x0f,
5040         NVM_TYPE_HW_SET         = 0x10,
5041         NVM_TYPE_LIM            = 0x11,
5042         NVM_TYPE_AVS_FW1        = 0x12,
5043         NVM_TYPE_DIR2           = 0x13,
5044         NVM_TYPE_CCM            = 0x14,
5045         NVM_TYPE_EAGLE_FW2      = 0x15,
5046         NVM_TYPE_FALCON_FW2     = 0x16,
5047         NVM_TYPE_PCIE_FW2       = 0x17,
5048         NVM_TYPE_AVS_FW2        = 0x18,
5049
5050         NVM_TYPE_MAX,
5051 };
5052
5053 #define MAX_NVM_DIR_ENTRIES 200
5054
5055 struct nvm_dir {
5056         s32 seq;
5057 #define NVM_DIR_NEXT_MFW_MASK   0x00000001
5058 #define NVM_DIR_SEQ_MASK        0xfffffffe
5059 #define NVM_DIR_NEXT_MFW(seq) ((seq) & NVM_DIR_NEXT_MFW_MASK)
5060
5061 #define IS_DIR_SEQ_VALID(seq) ((seq & NVM_DIR_SEQ_MASK) != NVM_DIR_SEQ_MASK)
5062
5063         u32                     num_images;
5064         u32                     rsrv;
5065         struct nvm_code_entry   code[1]; /* Up to MAX_NVM_DIR_ENTRIES */
5066 };
5067
5068 #define NVM_DIR_SIZE(_num_images) (sizeof(struct nvm_dir) +              \
5069                                    (_num_images -                        \
5070                                     1) * sizeof(struct nvm_code_entry) + \
5071                                    NVM_CRC_SIZE)
5072
5073 struct nvm_vpd_image {
5074         u32     format_revision;
5075 #define VPD_IMAGE_VERSION        1
5076
5077         /* This array length depends on the number of VPD fields */
5078         u8      vpd_data[1];
5079 };
5080
5081 /****************************************************************************
5082 * NVRAM FULL MAP                                                           *
5083 ****************************************************************************/
5084 #define DIR_ID_1    (0)
5085 #define DIR_ID_2    (1)
5086 #define MAX_DIR_IDS (2)
5087
5088 #define MFW_BUNDLE_1    (0)
5089 #define MFW_BUNDLE_2    (1)
5090 #define MAX_MFW_BUNDLES (2)
5091
5092 #define FLASH_PAGE_SIZE 0x1000
5093 #define NVM_DIR_MAX_SIZE    (FLASH_PAGE_SIZE)           /* 4Kb */
5094 #define ASIC_MIM_MAX_SIZE   (300 * FLASH_PAGE_SIZE)     /* 1.2Mb */
5095 #define FPGA_MIM_MAX_SIZE   (25 * FLASH_PAGE_SIZE)      /* 60Kb */
5096
5097 #define LIM_MAX_SIZE        ((2 *                                     \
5098                               FLASH_PAGE_SIZE) -                      \
5099                              sizeof(struct legacy_bootstrap_region) - \
5100                              NVM_RSV_SIZE)
5101 #define LIM_OFFSET          (NVM_OFFSET(lim_image))
5102 #define NVM_RSV_SIZE            (44)
5103 #define MIM_MAX_SIZE(is_asic) ((is_asic) ? ASIC_MIM_MAX_SIZE : \
5104                                FPGA_MIM_MAX_SIZE)
5105 #define MIM_OFFSET(idx, is_asic) (NVM_OFFSET(dir[MAX_MFW_BUNDLES]) + \
5106                                   ((idx ==                           \
5107                                     NVM_TYPE_MIM2) ? MIM_MAX_SIZE(is_asic) : 0))
5108 #define NVM_FIXED_AREA_SIZE(is_asic) (sizeof(struct nvm_image) + \
5109                                       MIM_MAX_SIZE(is_asic) * 2)
5110
5111 union nvm_dir_union {
5112         struct nvm_dir  dir;
5113         u8              page[FLASH_PAGE_SIZE];
5114 };
5115
5116 /*                        Address
5117  *  +-------------------+ 0x000000
5118  *  |    Bootstrap:     |
5119  *  | magic_number      |
5120  *  | sram_start_addr   |
5121  *  | code_len          |
5122  *  | code_start_addr   |
5123  *  | crc               |
5124  *  +-------------------+ 0x000014
5125  *  | rsrv              |
5126  *  +-------------------+ 0x000040
5127  *  | LIM               |
5128  *  +-------------------+ 0x002000
5129  *  | Dir1              |
5130  *  +-------------------+ 0x003000
5131  *  | Dir2              |
5132  *  +-------------------+ 0x004000
5133  *  | MIM1              |
5134  *  +-------------------+ 0x130000
5135  *  | MIM2              |
5136  *  +-------------------+ 0x25C000
5137  *  | Rest Images:      |
5138  *  | TIM1/2            |
5139  *  | MFW_TRACE1/2      |
5140  *  | Eagle/Falcon FW   |
5141  *  | PCIE/AVS FW       |
5142  *  | MBA/CCM/L2B       |
5143  *  | VPD               |
5144  *  | optic_modules     |
5145  *  |  ...              |
5146  *  +-------------------+ 0x400000
5147  */
5148 struct nvm_image {
5149 /*********** !!!  FIXED SECTIONS  !!! DO NOT MODIFY !!! **********************/
5150         /* NVM Offset  (size) */
5151         struct legacy_bootstrap_region  bootstrap;
5152         u8                              rsrv[NVM_RSV_SIZE];
5153         u8                              lim_image[LIM_MAX_SIZE];
5154         union nvm_dir_union             dir[MAX_MFW_BUNDLES];
5155
5156         /* MIM1_IMAGE                              0x004000 (0x12c000) */
5157         /* MIM2_IMAGE                              0x130000 (0x12c000) */
5158 /*********** !!!  FIXED SECTIONS  !!! DO NOT MODIFY !!! **********************/
5159 };                              /* 0x134 */
5160
5161 #define NVM_OFFSET(f)   ((u32_t)((int_ptr_t)(&(((struct nvm_image *)0)->f))))
5162
5163 struct hw_set_info {
5164         u32     reg_type;
5165 #define GRC_REG_TYPE 1
5166 #define PHY_REG_TYPE 2
5167 #define PCI_REG_TYPE 4
5168
5169         u32     bank_num;
5170         u32     pf_num;
5171         u32     operation;
5172 #define READ_OP     1
5173 #define WRITE_OP    2
5174 #define RMW_SET_OP  3
5175 #define RMW_CLR_OP  4
5176
5177         u32     reg_addr;
5178         u32     reg_data;
5179
5180         u32     reset_type;
5181 #define POR_RESET_TYPE  BIT(0)
5182 #define HARD_RESET_TYPE BIT(1)
5183 #define CORE_RESET_TYPE BIT(2)
5184 #define MCP_RESET_TYPE  BIT(3)
5185 #define PERSET_ASSERT   BIT(4)
5186 #define PERSET_DEASSERT BIT(5)
5187 };
5188
5189 struct hw_set_image {
5190         u32                     format_version;
5191 #define HW_SET_IMAGE_VERSION        1
5192         u32                     no_hw_sets;
5193
5194         /* This array length depends on the no_hw_sets */
5195         struct hw_set_info      hw_sets[1];
5196 };
5197
5198 int qed_init_pf_wfq(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
5199                     u8 pf_id, u16 pf_wfq);
5200 int qed_init_vport_wfq(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
5201                        u16 first_tx_pq_id[NUM_OF_TCS], u16 vport_wfq);
5202 #endif