1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
9 #include <linux/stddef.h>
10 #include <linux/pci.h>
11 #include <linux/kernel.h>
12 #include <linux/slab.h>
13 #include <linux/version.h>
14 #include <linux/delay.h>
15 #include <asm/byteorder.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/string.h>
18 #include <linux/module.h>
19 #include <linux/interrupt.h>
20 #include <linux/workqueue.h>
21 #include <linux/ethtool.h>
22 #include <linux/etherdevice.h>
23 #include <linux/vmalloc.h>
24 #include <linux/qed/qed_if.h>
27 #include "qed_sriov.h"
29 #include "qed_dev_api.h"
32 #include "qed_selftest.h"
34 static char version[] =
35 "QLogic FastLinQ 4xxxx Core Module qed " DRV_MODULE_VERSION "\n";
37 MODULE_DESCRIPTION("QLogic FastLinQ 4xxxx Core Module");
38 MODULE_LICENSE("GPL");
39 MODULE_VERSION(DRV_MODULE_VERSION);
41 #define FW_FILE_VERSION \
42 __stringify(FW_MAJOR_VERSION) "." \
43 __stringify(FW_MINOR_VERSION) "." \
44 __stringify(FW_REVISION_VERSION) "." \
45 __stringify(FW_ENGINEERING_VERSION)
47 #define QED_FW_FILE_NAME \
48 "qed/qed_init_values_zipped-" FW_FILE_VERSION ".bin"
50 MODULE_FIRMWARE(QED_FW_FILE_NAME);
52 static int __init qed_init(void)
54 pr_info("%s", version);
59 static void __exit qed_cleanup(void)
61 pr_notice("qed_cleanup called\n");
64 module_init(qed_init);
65 module_exit(qed_cleanup);
67 /* Check if the DMA controller on the machine can properly handle the DMA
68 * addressing required by the device.
70 static int qed_set_coherency_mask(struct qed_dev *cdev)
72 struct device *dev = &cdev->pdev->dev;
74 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
75 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
77 "Can't request 64-bit consistent allocations\n");
80 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
81 DP_NOTICE(cdev, "Can't request 64b/32b DMA addresses\n");
88 static void qed_free_pci(struct qed_dev *cdev)
90 struct pci_dev *pdev = cdev->pdev;
93 iounmap(cdev->doorbells);
95 iounmap(cdev->regview);
96 if (atomic_read(&pdev->enable_cnt) == 1)
97 pci_release_regions(pdev);
99 pci_disable_device(pdev);
102 #define PCI_REVISION_ID_ERROR_VAL 0xff
104 /* Performs PCI initializations as well as initializing PCI-related parameters
105 * in the device structrue. Returns 0 in case of success.
107 static int qed_init_pci(struct qed_dev *cdev, struct pci_dev *pdev)
114 rc = pci_enable_device(pdev);
116 DP_NOTICE(cdev, "Cannot enable PCI device\n");
120 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
121 DP_NOTICE(cdev, "No memory region found in bar #0\n");
126 if (IS_PF(cdev) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
127 DP_NOTICE(cdev, "No memory region found in bar #2\n");
132 if (atomic_read(&pdev->enable_cnt) == 1) {
133 rc = pci_request_regions(pdev, "qed");
136 "Failed to request PCI memory resources\n");
139 pci_set_master(pdev);
140 pci_save_state(pdev);
143 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
144 if (rev_id == PCI_REVISION_ID_ERROR_VAL) {
146 "Detected PCI device error [rev_id 0x%x]. Probably due to prior indication. Aborting.\n",
151 if (!pci_is_pcie(pdev)) {
152 DP_NOTICE(cdev, "The bus is not PCI Express\n");
157 cdev->pci_params.pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
158 if (IS_PF(cdev) && !cdev->pci_params.pm_cap)
159 DP_NOTICE(cdev, "Cannot find power management capability\n");
161 rc = qed_set_coherency_mask(cdev);
165 cdev->pci_params.mem_start = pci_resource_start(pdev, 0);
166 cdev->pci_params.mem_end = pci_resource_end(pdev, 0);
167 cdev->pci_params.irq = pdev->irq;
169 cdev->regview = pci_ioremap_bar(pdev, 0);
170 if (!cdev->regview) {
171 DP_NOTICE(cdev, "Cannot map register space, aborting\n");
177 cdev->db_phys_addr = pci_resource_start(cdev->pdev, 2);
178 cdev->db_size = pci_resource_len(cdev->pdev, 2);
179 cdev->doorbells = ioremap_wc(cdev->db_phys_addr, cdev->db_size);
180 if (!cdev->doorbells) {
181 DP_NOTICE(cdev, "Cannot map doorbell space\n");
189 pci_release_regions(pdev);
191 pci_disable_device(pdev);
196 int qed_fill_dev_info(struct qed_dev *cdev,
197 struct qed_dev_info *dev_info)
201 memset(dev_info, 0, sizeof(struct qed_dev_info));
203 dev_info->num_hwfns = cdev->num_hwfns;
204 dev_info->pci_mem_start = cdev->pci_params.mem_start;
205 dev_info->pci_mem_end = cdev->pci_params.mem_end;
206 dev_info->pci_irq = cdev->pci_params.irq;
207 dev_info->rdma_supported =
208 (cdev->hwfns[0].hw_info.personality == QED_PCI_ETH_ROCE);
209 dev_info->is_mf_default = IS_MF_DEFAULT(&cdev->hwfns[0]);
210 ether_addr_copy(dev_info->hw_mac, cdev->hwfns[0].hw_info.hw_mac_addr);
213 dev_info->fw_major = FW_MAJOR_VERSION;
214 dev_info->fw_minor = FW_MINOR_VERSION;
215 dev_info->fw_rev = FW_REVISION_VERSION;
216 dev_info->fw_eng = FW_ENGINEERING_VERSION;
217 dev_info->mf_mode = cdev->mf_mode;
218 dev_info->tx_switching = true;
220 qed_vf_get_fw_version(&cdev->hwfns[0], &dev_info->fw_major,
221 &dev_info->fw_minor, &dev_info->fw_rev,
226 ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev));
228 qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev), ptt,
229 &dev_info->mfw_rev, NULL);
231 qed_mcp_get_flash_size(QED_LEADING_HWFN(cdev), ptt,
232 &dev_info->flash_size);
234 qed_ptt_release(QED_LEADING_HWFN(cdev), ptt);
237 qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev), NULL,
238 &dev_info->mfw_rev, NULL);
244 static void qed_free_cdev(struct qed_dev *cdev)
249 static struct qed_dev *qed_alloc_cdev(struct pci_dev *pdev)
251 struct qed_dev *cdev;
253 cdev = kzalloc(sizeof(*cdev), GFP_KERNEL);
257 qed_init_struct(cdev);
262 /* Sets the requested power state */
263 static int qed_set_power_state(struct qed_dev *cdev, pci_power_t state)
268 DP_VERBOSE(cdev, NETIF_MSG_DRV, "Omitting Power state change\n");
273 static struct qed_dev *qed_probe(struct pci_dev *pdev,
274 struct qed_probe_params *params)
276 struct qed_dev *cdev;
279 cdev = qed_alloc_cdev(pdev);
283 cdev->protocol = params->protocol;
286 cdev->b_is_vf = true;
288 qed_init_dp(cdev, params->dp_module, params->dp_level);
290 rc = qed_init_pci(cdev, pdev);
292 DP_ERR(cdev, "init pci failed\n");
295 DP_INFO(cdev, "PCI init completed successfully\n");
297 rc = qed_hw_prepare(cdev, QED_PCI_DEFAULT);
299 DP_ERR(cdev, "hw prepare failed\n");
303 DP_INFO(cdev, "qed_probe completed successffuly\n");
315 static void qed_remove(struct qed_dev *cdev)
324 qed_set_power_state(cdev, PCI_D3hot);
329 static void qed_disable_msix(struct qed_dev *cdev)
331 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
332 pci_disable_msix(cdev->pdev);
333 kfree(cdev->int_params.msix_table);
334 } else if (cdev->int_params.out.int_mode == QED_INT_MODE_MSI) {
335 pci_disable_msi(cdev->pdev);
338 memset(&cdev->int_params.out, 0, sizeof(struct qed_int_param));
341 static int qed_enable_msix(struct qed_dev *cdev,
342 struct qed_int_params *int_params)
346 cnt = int_params->in.num_vectors;
348 for (i = 0; i < cnt; i++)
349 int_params->msix_table[i].entry = i;
351 rc = pci_enable_msix_range(cdev->pdev, int_params->msix_table,
352 int_params->in.min_msix_cnt, cnt);
353 if (rc < cnt && rc >= int_params->in.min_msix_cnt &&
354 (rc % cdev->num_hwfns)) {
355 pci_disable_msix(cdev->pdev);
357 /* If fastpath is initialized, we need at least one interrupt
358 * per hwfn [and the slow path interrupts]. New requested number
359 * should be a multiple of the number of hwfns.
361 cnt = (rc / cdev->num_hwfns) * cdev->num_hwfns;
363 "Trying to enable MSI-X with less vectors (%d out of %d)\n",
364 cnt, int_params->in.num_vectors);
365 rc = pci_enable_msix_exact(cdev->pdev, int_params->msix_table,
372 /* MSI-x configuration was achieved */
373 int_params->out.int_mode = QED_INT_MODE_MSIX;
374 int_params->out.num_vectors = rc;
378 "Failed to enable MSI-X [Requested %d vectors][rc %d]\n",
385 /* This function outputs the int mode and the number of enabled msix vector */
386 static int qed_set_int_mode(struct qed_dev *cdev, bool force_mode)
388 struct qed_int_params *int_params = &cdev->int_params;
389 struct msix_entry *tbl;
392 switch (int_params->in.int_mode) {
393 case QED_INT_MODE_MSIX:
394 /* Allocate MSIX table */
395 cnt = int_params->in.num_vectors;
396 int_params->msix_table = kcalloc(cnt, sizeof(*tbl), GFP_KERNEL);
397 if (!int_params->msix_table) {
403 rc = qed_enable_msix(cdev, int_params);
407 DP_NOTICE(cdev, "Failed to enable MSI-X\n");
408 kfree(int_params->msix_table);
413 case QED_INT_MODE_MSI:
414 if (cdev->num_hwfns == 1) {
415 rc = pci_enable_msi(cdev->pdev);
417 int_params->out.int_mode = QED_INT_MODE_MSI;
421 DP_NOTICE(cdev, "Failed to enable MSI\n");
427 case QED_INT_MODE_INTA:
428 int_params->out.int_mode = QED_INT_MODE_INTA;
432 DP_NOTICE(cdev, "Unknown int_mode value %d\n",
433 int_params->in.int_mode);
439 DP_INFO(cdev, "Using %s interrupts\n",
440 int_params->out.int_mode == QED_INT_MODE_INTA ?
441 "INTa" : int_params->out.int_mode == QED_INT_MODE_MSI ?
443 cdev->int_coalescing_mode = QED_COAL_MODE_ENABLE;
448 static void qed_simd_handler_config(struct qed_dev *cdev, void *token,
449 int index, void(*handler)(void *))
451 struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns];
452 int relative_idx = index / cdev->num_hwfns;
454 hwfn->simd_proto_handler[relative_idx].func = handler;
455 hwfn->simd_proto_handler[relative_idx].token = token;
458 static void qed_simd_handler_clean(struct qed_dev *cdev, int index)
460 struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns];
461 int relative_idx = index / cdev->num_hwfns;
463 memset(&hwfn->simd_proto_handler[relative_idx], 0,
464 sizeof(struct qed_simd_fp_handler));
467 static irqreturn_t qed_msix_sp_int(int irq, void *tasklet)
469 tasklet_schedule((struct tasklet_struct *)tasklet);
473 static irqreturn_t qed_single_int(int irq, void *dev_instance)
475 struct qed_dev *cdev = (struct qed_dev *)dev_instance;
476 struct qed_hwfn *hwfn;
477 irqreturn_t rc = IRQ_NONE;
481 for (i = 0; i < cdev->num_hwfns; i++) {
482 status = qed_int_igu_read_sisr_reg(&cdev->hwfns[i]);
487 hwfn = &cdev->hwfns[i];
489 /* Slowpath interrupt */
490 if (unlikely(status & 0x1)) {
491 tasklet_schedule(hwfn->sp_dpc);
496 /* Fastpath interrupts */
497 for (j = 0; j < 64; j++) {
498 if ((0x2ULL << j) & status) {
499 hwfn->simd_proto_handler[j].func(
500 hwfn->simd_proto_handler[j].token);
501 status &= ~(0x2ULL << j);
506 if (unlikely(status))
507 DP_VERBOSE(hwfn, NETIF_MSG_INTR,
508 "got an unknown interrupt status 0x%llx\n",
515 int qed_slowpath_irq_req(struct qed_hwfn *hwfn)
517 struct qed_dev *cdev = hwfn->cdev;
522 int_mode = cdev->int_params.out.int_mode;
523 if (int_mode == QED_INT_MODE_MSIX) {
525 snprintf(hwfn->name, NAME_SIZE, "sp-%d-%02x:%02x.%02x",
526 id, cdev->pdev->bus->number,
527 PCI_SLOT(cdev->pdev->devfn), hwfn->abs_pf_id);
528 rc = request_irq(cdev->int_params.msix_table[id].vector,
529 qed_msix_sp_int, 0, hwfn->name, hwfn->sp_dpc);
531 unsigned long flags = 0;
533 snprintf(cdev->name, NAME_SIZE, "%02x:%02x.%02x",
534 cdev->pdev->bus->number, PCI_SLOT(cdev->pdev->devfn),
535 PCI_FUNC(cdev->pdev->devfn));
537 if (cdev->int_params.out.int_mode == QED_INT_MODE_INTA)
538 flags |= IRQF_SHARED;
540 rc = request_irq(cdev->pdev->irq, qed_single_int,
541 flags, cdev->name, cdev);
545 DP_NOTICE(cdev, "request_irq failed, rc = %d\n", rc);
547 DP_VERBOSE(hwfn, (NETIF_MSG_INTR | QED_MSG_SP),
548 "Requested slowpath %s\n",
549 (int_mode == QED_INT_MODE_MSIX) ? "MSI-X" : "IRQ");
554 static void qed_slowpath_irq_free(struct qed_dev *cdev)
558 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
559 for_each_hwfn(cdev, i) {
560 if (!cdev->hwfns[i].b_int_requested)
562 synchronize_irq(cdev->int_params.msix_table[i].vector);
563 free_irq(cdev->int_params.msix_table[i].vector,
564 cdev->hwfns[i].sp_dpc);
567 if (QED_LEADING_HWFN(cdev)->b_int_requested)
568 free_irq(cdev->pdev->irq, cdev);
570 qed_int_disable_post_isr_release(cdev);
573 static int qed_nic_stop(struct qed_dev *cdev)
577 rc = qed_hw_stop(cdev);
579 for (i = 0; i < cdev->num_hwfns; i++) {
580 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
582 if (p_hwfn->b_sp_dpc_enabled) {
583 tasklet_disable(p_hwfn->sp_dpc);
584 p_hwfn->b_sp_dpc_enabled = false;
585 DP_VERBOSE(cdev, NETIF_MSG_IFDOWN,
586 "Disabled sp taskelt [hwfn %d] at %p\n",
594 static int qed_nic_reset(struct qed_dev *cdev)
598 rc = qed_hw_reset(cdev);
607 static int qed_nic_setup(struct qed_dev *cdev)
611 rc = qed_resc_alloc(cdev);
615 DP_INFO(cdev, "Allocated qed resources\n");
617 qed_resc_setup(cdev);
622 static int qed_set_int_fp(struct qed_dev *cdev, u16 cnt)
626 /* Mark the fastpath as free/used */
627 cdev->int_params.fp_initialized = cnt ? true : false;
629 if (cdev->int_params.out.int_mode != QED_INT_MODE_MSIX)
630 limit = cdev->num_hwfns * 63;
631 else if (cdev->int_params.fp_msix_cnt)
632 limit = cdev->int_params.fp_msix_cnt;
637 return min_t(int, cnt, limit);
640 static int qed_get_int_fp(struct qed_dev *cdev, struct qed_int_info *info)
642 memset(info, 0, sizeof(struct qed_int_info));
644 if (!cdev->int_params.fp_initialized) {
646 "Protocol driver requested interrupt information, but its support is not yet configured\n");
650 /* Need to expose only MSI-X information; Single IRQ is handled solely
653 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
654 int msix_base = cdev->int_params.fp_msix_base;
656 info->msix_cnt = cdev->int_params.fp_msix_cnt;
657 info->msix = &cdev->int_params.msix_table[msix_base];
663 static int qed_slowpath_setup_int(struct qed_dev *cdev,
664 enum qed_int_mode int_mode)
666 struct qed_sb_cnt_info sb_cnt_info;
670 if ((int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
671 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
675 memset(&cdev->int_params, 0, sizeof(struct qed_int_params));
676 cdev->int_params.in.int_mode = int_mode;
677 for_each_hwfn(cdev, i) {
678 memset(&sb_cnt_info, 0, sizeof(sb_cnt_info));
679 qed_int_get_num_sbs(&cdev->hwfns[i], &sb_cnt_info);
680 cdev->int_params.in.num_vectors += sb_cnt_info.sb_cnt;
681 cdev->int_params.in.num_vectors++; /* slowpath */
684 /* We want a minimum of one slowpath and one fastpath vector per hwfn */
685 cdev->int_params.in.min_msix_cnt = cdev->num_hwfns * 2;
687 rc = qed_set_int_mode(cdev, false);
689 DP_ERR(cdev, "qed_slowpath_setup_int ERR\n");
693 cdev->int_params.fp_msix_base = cdev->num_hwfns;
694 cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors -
700 static int qed_slowpath_vf_setup_int(struct qed_dev *cdev)
704 memset(&cdev->int_params, 0, sizeof(struct qed_int_params));
705 cdev->int_params.in.int_mode = QED_INT_MODE_MSIX;
707 qed_vf_get_num_rxqs(QED_LEADING_HWFN(cdev),
708 &cdev->int_params.in.num_vectors);
709 if (cdev->num_hwfns > 1) {
712 qed_vf_get_num_rxqs(&cdev->hwfns[1], &vectors);
713 cdev->int_params.in.num_vectors += vectors;
716 /* We want a minimum of one fastpath vector per vf hwfn */
717 cdev->int_params.in.min_msix_cnt = cdev->num_hwfns;
719 rc = qed_set_int_mode(cdev, true);
723 cdev->int_params.fp_msix_base = 0;
724 cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors;
729 u32 qed_unzip_data(struct qed_hwfn *p_hwfn, u32 input_len,
730 u8 *input_buf, u32 max_size, u8 *unzip_buf)
734 p_hwfn->stream->next_in = input_buf;
735 p_hwfn->stream->avail_in = input_len;
736 p_hwfn->stream->next_out = unzip_buf;
737 p_hwfn->stream->avail_out = max_size;
739 rc = zlib_inflateInit2(p_hwfn->stream, MAX_WBITS);
742 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "zlib init failed, rc = %d\n",
747 rc = zlib_inflate(p_hwfn->stream, Z_FINISH);
748 zlib_inflateEnd(p_hwfn->stream);
750 if (rc != Z_OK && rc != Z_STREAM_END) {
751 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "FW unzip error: %s, rc=%d\n",
752 p_hwfn->stream->msg, rc);
756 return p_hwfn->stream->total_out / 4;
759 static int qed_alloc_stream_mem(struct qed_dev *cdev)
764 for_each_hwfn(cdev, i) {
765 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
767 p_hwfn->stream = kzalloc(sizeof(*p_hwfn->stream), GFP_KERNEL);
771 workspace = vzalloc(zlib_inflate_workspacesize());
774 p_hwfn->stream->workspace = workspace;
780 static void qed_free_stream_mem(struct qed_dev *cdev)
784 for_each_hwfn(cdev, i) {
785 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
790 vfree(p_hwfn->stream->workspace);
791 kfree(p_hwfn->stream);
795 static void qed_update_pf_params(struct qed_dev *cdev,
796 struct qed_pf_params *params)
800 for (i = 0; i < cdev->num_hwfns; i++) {
801 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
803 p_hwfn->pf_params = *params;
807 static int qed_slowpath_start(struct qed_dev *cdev,
808 struct qed_slowpath_params *params)
810 struct qed_tunn_start_params tunn_info;
811 struct qed_mcp_drv_version drv_version;
812 const u8 *data = NULL;
813 struct qed_hwfn *hwfn;
816 if (qed_iov_wq_start(cdev))
820 rc = request_firmware(&cdev->firmware, QED_FW_FILE_NAME,
824 "Failed to find fw file - /lib/firmware/%s\n",
830 rc = qed_nic_setup(cdev);
835 rc = qed_slowpath_setup_int(cdev, params->int_mode);
837 rc = qed_slowpath_vf_setup_int(cdev);
842 /* Allocate stream for unzipping */
843 rc = qed_alloc_stream_mem(cdev);
845 DP_NOTICE(cdev, "Failed to allocate stream memory\n");
849 /* First Dword used to diffrentiate between various sources */
850 data = cdev->firmware->data + sizeof(u32);
853 memset(&tunn_info, 0, sizeof(tunn_info));
854 tunn_info.tunn_mode |= 1 << QED_MODE_VXLAN_TUNN |
855 1 << QED_MODE_L2GRE_TUNN |
856 1 << QED_MODE_IPGRE_TUNN |
857 1 << QED_MODE_L2GENEVE_TUNN |
858 1 << QED_MODE_IPGENEVE_TUNN;
860 tunn_info.tunn_clss_vxlan = QED_TUNN_CLSS_MAC_VLAN;
861 tunn_info.tunn_clss_l2gre = QED_TUNN_CLSS_MAC_VLAN;
862 tunn_info.tunn_clss_ipgre = QED_TUNN_CLSS_MAC_VLAN;
864 /* Start the slowpath */
865 rc = qed_hw_init(cdev, &tunn_info, true,
866 cdev->int_params.out.int_mode,
872 "HW initialization and function start completed successfully\n");
875 hwfn = QED_LEADING_HWFN(cdev);
876 drv_version.version = (params->drv_major << 24) |
877 (params->drv_minor << 16) |
878 (params->drv_rev << 8) |
880 strlcpy(drv_version.name, params->name,
881 MCP_DRV_VER_STR_SIZE - 4);
882 rc = qed_mcp_send_drv_version(hwfn, hwfn->p_main_ptt,
885 DP_NOTICE(cdev, "Failed sending drv version command\n");
890 qed_reset_vport_stats(cdev);
895 qed_hw_timers_stop_all(cdev);
897 qed_slowpath_irq_free(cdev);
898 qed_free_stream_mem(cdev);
899 qed_disable_msix(cdev);
904 release_firmware(cdev->firmware);
906 qed_iov_wq_stop(cdev, false);
911 static int qed_slowpath_stop(struct qed_dev *cdev)
917 qed_free_stream_mem(cdev);
918 if (IS_QED_ETH_IF(cdev))
919 qed_sriov_disable(cdev, true);
922 qed_slowpath_irq_free(cdev);
925 qed_disable_msix(cdev);
928 qed_iov_wq_stop(cdev, true);
931 release_firmware(cdev->firmware);
936 static void qed_set_id(struct qed_dev *cdev, char name[NAME_SIZE],
937 char ver_str[VER_SIZE])
941 memcpy(cdev->name, name, NAME_SIZE);
942 for_each_hwfn(cdev, i)
943 snprintf(cdev->hwfns[i].name, NAME_SIZE, "%s-%d", name, i);
945 memcpy(cdev->ver_str, ver_str, VER_SIZE);
946 cdev->drv_type = DRV_ID_DRV_TYPE_LINUX;
949 static u32 qed_sb_init(struct qed_dev *cdev,
950 struct qed_sb_info *sb_info,
952 dma_addr_t sb_phy_addr, u16 sb_id,
953 enum qed_sb_type type)
955 struct qed_hwfn *p_hwfn;
961 /* RoCE uses single engine and CMT uses two engines. When using both
962 * we force only a single engine. Storage uses only engine 0 too.
964 if (type == QED_SB_TYPE_L2_QUEUE)
965 n_hwfns = cdev->num_hwfns;
969 hwfn_index = sb_id % n_hwfns;
970 p_hwfn = &cdev->hwfns[hwfn_index];
971 rel_sb_id = sb_id / n_hwfns;
973 DP_VERBOSE(cdev, NETIF_MSG_INTR,
974 "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n",
975 hwfn_index, rel_sb_id, sb_id);
977 rc = qed_int_sb_init(p_hwfn, p_hwfn->p_main_ptt, sb_info,
978 sb_virt_addr, sb_phy_addr, rel_sb_id);
983 static u32 qed_sb_release(struct qed_dev *cdev,
984 struct qed_sb_info *sb_info, u16 sb_id)
986 struct qed_hwfn *p_hwfn;
991 hwfn_index = sb_id % cdev->num_hwfns;
992 p_hwfn = &cdev->hwfns[hwfn_index];
993 rel_sb_id = sb_id / cdev->num_hwfns;
995 DP_VERBOSE(cdev, NETIF_MSG_INTR,
996 "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n",
997 hwfn_index, rel_sb_id, sb_id);
999 rc = qed_int_sb_release(p_hwfn, sb_info, rel_sb_id);
1004 static bool qed_can_link_change(struct qed_dev *cdev)
1009 static int qed_set_link(struct qed_dev *cdev, struct qed_link_params *params)
1011 struct qed_hwfn *hwfn;
1012 struct qed_mcp_link_params *link_params;
1013 struct qed_ptt *ptt;
1022 /* The link should be set only once per PF */
1023 hwfn = &cdev->hwfns[0];
1025 ptt = qed_ptt_acquire(hwfn);
1029 link_params = qed_mcp_get_link_params(hwfn);
1030 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_AUTONEG)
1031 link_params->speed.autoneg = params->autoneg;
1032 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS) {
1033 link_params->speed.advertised_speeds = 0;
1034 if ((params->adv_speeds & QED_LM_1000baseT_Half_BIT) ||
1035 (params->adv_speeds & QED_LM_1000baseT_Full_BIT))
1036 link_params->speed.advertised_speeds |=
1037 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G;
1038 if (params->adv_speeds & QED_LM_10000baseKR_Full_BIT)
1039 link_params->speed.advertised_speeds |=
1040 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G;
1041 if (params->adv_speeds & QED_LM_25000baseKR_Full_BIT)
1042 link_params->speed.advertised_speeds |=
1043 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G;
1044 if (params->adv_speeds & QED_LM_40000baseLR4_Full_BIT)
1045 link_params->speed.advertised_speeds |=
1046 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G;
1047 if (params->adv_speeds & QED_LM_50000baseKR2_Full_BIT)
1048 link_params->speed.advertised_speeds |=
1049 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G;
1050 if (params->adv_speeds & QED_LM_100000baseKR4_Full_BIT)
1051 link_params->speed.advertised_speeds |=
1052 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G;
1054 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_FORCED_SPEED)
1055 link_params->speed.forced_speed = params->forced_speed;
1056 if (params->override_flags & QED_LINK_OVERRIDE_PAUSE_CONFIG) {
1057 if (params->pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
1058 link_params->pause.autoneg = true;
1060 link_params->pause.autoneg = false;
1061 if (params->pause_config & QED_LINK_PAUSE_RX_ENABLE)
1062 link_params->pause.forced_rx = true;
1064 link_params->pause.forced_rx = false;
1065 if (params->pause_config & QED_LINK_PAUSE_TX_ENABLE)
1066 link_params->pause.forced_tx = true;
1068 link_params->pause.forced_tx = false;
1070 if (params->override_flags & QED_LINK_OVERRIDE_LOOPBACK_MODE) {
1071 switch (params->loopback_mode) {
1072 case QED_LINK_LOOPBACK_INT_PHY:
1073 link_params->loopback_mode = ETH_LOOPBACK_INT_PHY;
1075 case QED_LINK_LOOPBACK_EXT_PHY:
1076 link_params->loopback_mode = ETH_LOOPBACK_EXT_PHY;
1078 case QED_LINK_LOOPBACK_EXT:
1079 link_params->loopback_mode = ETH_LOOPBACK_EXT;
1081 case QED_LINK_LOOPBACK_MAC:
1082 link_params->loopback_mode = ETH_LOOPBACK_MAC;
1085 link_params->loopback_mode = ETH_LOOPBACK_NONE;
1090 rc = qed_mcp_set_link(hwfn, ptt, params->link_up);
1092 qed_ptt_release(hwfn, ptt);
1097 static int qed_get_port_type(u32 media_type)
1101 switch (media_type) {
1102 case MEDIA_SFPP_10G_FIBER:
1103 case MEDIA_SFP_1G_FIBER:
1104 case MEDIA_XFP_FIBER:
1105 case MEDIA_MODULE_FIBER:
1107 port_type = PORT_FIBRE;
1109 case MEDIA_DA_TWINAX:
1110 port_type = PORT_DA;
1113 port_type = PORT_TP;
1115 case MEDIA_NOT_PRESENT:
1116 port_type = PORT_NONE;
1118 case MEDIA_UNSPECIFIED:
1120 port_type = PORT_OTHER;
1126 static int qed_get_link_data(struct qed_hwfn *hwfn,
1127 struct qed_mcp_link_params *params,
1128 struct qed_mcp_link_state *link,
1129 struct qed_mcp_link_capabilities *link_caps)
1133 if (!IS_PF(hwfn->cdev)) {
1134 qed_vf_get_link_params(hwfn, params);
1135 qed_vf_get_link_state(hwfn, link);
1136 qed_vf_get_link_caps(hwfn, link_caps);
1141 p = qed_mcp_get_link_params(hwfn);
1144 memcpy(params, p, sizeof(*params));
1146 p = qed_mcp_get_link_state(hwfn);
1149 memcpy(link, p, sizeof(*link));
1151 p = qed_mcp_get_link_capabilities(hwfn);
1154 memcpy(link_caps, p, sizeof(*link_caps));
1159 static void qed_fill_link(struct qed_hwfn *hwfn,
1160 struct qed_link_output *if_link)
1162 struct qed_mcp_link_params params;
1163 struct qed_mcp_link_state link;
1164 struct qed_mcp_link_capabilities link_caps;
1167 memset(if_link, 0, sizeof(*if_link));
1169 /* Prepare source inputs */
1170 if (qed_get_link_data(hwfn, ¶ms, &link, &link_caps)) {
1171 dev_warn(&hwfn->cdev->pdev->dev, "no link data available\n");
1175 /* Set the link parameters to pass to protocol driver */
1177 if_link->link_up = true;
1179 /* TODO - at the moment assume supported and advertised speed equal */
1180 if_link->supported_caps = QED_LM_FIBRE_BIT;
1181 if (params.speed.autoneg)
1182 if_link->supported_caps |= QED_LM_Autoneg_BIT;
1183 if (params.pause.autoneg ||
1184 (params.pause.forced_rx && params.pause.forced_tx))
1185 if_link->supported_caps |= QED_LM_Asym_Pause_BIT;
1186 if (params.pause.autoneg || params.pause.forced_rx ||
1187 params.pause.forced_tx)
1188 if_link->supported_caps |= QED_LM_Pause_BIT;
1190 if_link->advertised_caps = if_link->supported_caps;
1191 if (params.speed.advertised_speeds &
1192 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1193 if_link->advertised_caps |= QED_LM_1000baseT_Half_BIT |
1194 QED_LM_1000baseT_Full_BIT;
1195 if (params.speed.advertised_speeds &
1196 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1197 if_link->advertised_caps |= QED_LM_10000baseKR_Full_BIT;
1198 if (params.speed.advertised_speeds &
1199 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1200 if_link->advertised_caps |= QED_LM_25000baseKR_Full_BIT;
1201 if (params.speed.advertised_speeds &
1202 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1203 if_link->advertised_caps |= QED_LM_40000baseLR4_Full_BIT;
1204 if (params.speed.advertised_speeds &
1205 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1206 if_link->advertised_caps |= QED_LM_50000baseKR2_Full_BIT;
1207 if (params.speed.advertised_speeds &
1208 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1209 if_link->advertised_caps |= QED_LM_100000baseKR4_Full_BIT;
1211 if (link_caps.speed_capabilities &
1212 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1213 if_link->supported_caps |= QED_LM_1000baseT_Half_BIT |
1214 QED_LM_1000baseT_Full_BIT;
1215 if (link_caps.speed_capabilities &
1216 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1217 if_link->supported_caps |= QED_LM_10000baseKR_Full_BIT;
1218 if (link_caps.speed_capabilities &
1219 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1220 if_link->supported_caps |= QED_LM_25000baseKR_Full_BIT;
1221 if (link_caps.speed_capabilities &
1222 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1223 if_link->supported_caps |= QED_LM_40000baseLR4_Full_BIT;
1224 if (link_caps.speed_capabilities &
1225 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1226 if_link->supported_caps |= QED_LM_50000baseKR2_Full_BIT;
1227 if (link_caps.speed_capabilities &
1228 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1229 if_link->supported_caps |= QED_LM_100000baseKR4_Full_BIT;
1232 if_link->speed = link.speed;
1234 /* TODO - fill duplex properly */
1235 if_link->duplex = DUPLEX_FULL;
1236 qed_mcp_get_media_type(hwfn->cdev, &media_type);
1237 if_link->port = qed_get_port_type(media_type);
1239 if_link->autoneg = params.speed.autoneg;
1241 if (params.pause.autoneg)
1242 if_link->pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
1243 if (params.pause.forced_rx)
1244 if_link->pause_config |= QED_LINK_PAUSE_RX_ENABLE;
1245 if (params.pause.forced_tx)
1246 if_link->pause_config |= QED_LINK_PAUSE_TX_ENABLE;
1248 /* Link partner capabilities */
1249 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_1G_HD)
1250 if_link->lp_caps |= QED_LM_1000baseT_Half_BIT;
1251 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_1G_FD)
1252 if_link->lp_caps |= QED_LM_1000baseT_Full_BIT;
1253 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_10G)
1254 if_link->lp_caps |= QED_LM_10000baseKR_Full_BIT;
1255 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_25G)
1256 if_link->lp_caps |= QED_LM_25000baseKR_Full_BIT;
1257 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_40G)
1258 if_link->lp_caps |= QED_LM_40000baseLR4_Full_BIT;
1259 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_50G)
1260 if_link->lp_caps |= QED_LM_50000baseKR2_Full_BIT;
1261 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_100G)
1262 if_link->lp_caps |= QED_LM_100000baseKR4_Full_BIT;
1264 if (link.an_complete)
1265 if_link->lp_caps |= QED_LM_Autoneg_BIT;
1267 if (link.partner_adv_pause)
1268 if_link->lp_caps |= QED_LM_Pause_BIT;
1269 if (link.partner_adv_pause == QED_LINK_PARTNER_ASYMMETRIC_PAUSE ||
1270 link.partner_adv_pause == QED_LINK_PARTNER_BOTH_PAUSE)
1271 if_link->lp_caps |= QED_LM_Asym_Pause_BIT;
1274 static void qed_get_current_link(struct qed_dev *cdev,
1275 struct qed_link_output *if_link)
1279 qed_fill_link(&cdev->hwfns[0], if_link);
1281 for_each_hwfn(cdev, i)
1282 qed_inform_vf_link_state(&cdev->hwfns[i]);
1285 void qed_link_update(struct qed_hwfn *hwfn)
1287 void *cookie = hwfn->cdev->ops_cookie;
1288 struct qed_common_cb_ops *op = hwfn->cdev->protocol_ops.common;
1289 struct qed_link_output if_link;
1291 qed_fill_link(hwfn, &if_link);
1292 qed_inform_vf_link_state(hwfn);
1294 if (IS_LEAD_HWFN(hwfn) && cookie)
1295 op->link_update(cookie, &if_link);
1298 static int qed_drain(struct qed_dev *cdev)
1300 struct qed_hwfn *hwfn;
1301 struct qed_ptt *ptt;
1307 for_each_hwfn(cdev, i) {
1308 hwfn = &cdev->hwfns[i];
1309 ptt = qed_ptt_acquire(hwfn);
1311 DP_NOTICE(hwfn, "Failed to drain NIG; No PTT\n");
1314 rc = qed_mcp_drain(hwfn, ptt);
1317 qed_ptt_release(hwfn, ptt);
1323 static void qed_get_coalesce(struct qed_dev *cdev, u16 *rx_coal, u16 *tx_coal)
1325 *rx_coal = cdev->rx_coalesce_usecs;
1326 *tx_coal = cdev->tx_coalesce_usecs;
1329 static int qed_set_coalesce(struct qed_dev *cdev, u16 rx_coal, u16 tx_coal,
1332 struct qed_hwfn *hwfn;
1333 struct qed_ptt *ptt;
1337 hwfn_index = qid % cdev->num_hwfns;
1338 hwfn = &cdev->hwfns[hwfn_index];
1339 ptt = qed_ptt_acquire(hwfn);
1343 status = qed_set_rxq_coalesce(hwfn, ptt, rx_coal,
1344 qid / cdev->num_hwfns, sb_id);
1347 status = qed_set_txq_coalesce(hwfn, ptt, tx_coal,
1348 qid / cdev->num_hwfns, sb_id);
1350 qed_ptt_release(hwfn, ptt);
1355 static int qed_set_led(struct qed_dev *cdev, enum qed_led_mode mode)
1357 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
1358 struct qed_ptt *ptt;
1361 ptt = qed_ptt_acquire(hwfn);
1365 status = qed_mcp_set_led(hwfn, ptt, mode);
1367 qed_ptt_release(hwfn, ptt);
1372 struct qed_selftest_ops qed_selftest_ops_pass = {
1373 .selftest_memory = &qed_selftest_memory,
1374 .selftest_interrupt = &qed_selftest_interrupt,
1375 .selftest_register = &qed_selftest_register,
1376 .selftest_clock = &qed_selftest_clock,
1379 const struct qed_common_ops qed_common_ops_pass = {
1380 .selftest = &qed_selftest_ops_pass,
1381 .probe = &qed_probe,
1382 .remove = &qed_remove,
1383 .set_power_state = &qed_set_power_state,
1384 .set_id = &qed_set_id,
1385 .update_pf_params = &qed_update_pf_params,
1386 .slowpath_start = &qed_slowpath_start,
1387 .slowpath_stop = &qed_slowpath_stop,
1388 .set_fp_int = &qed_set_int_fp,
1389 .get_fp_int = &qed_get_int_fp,
1390 .sb_init = &qed_sb_init,
1391 .sb_release = &qed_sb_release,
1392 .simd_handler_config = &qed_simd_handler_config,
1393 .simd_handler_clean = &qed_simd_handler_clean,
1394 .can_link_change = &qed_can_link_change,
1395 .set_link = &qed_set_link,
1396 .get_link = &qed_get_current_link,
1397 .drain = &qed_drain,
1398 .update_msglvl = &qed_init_dp,
1399 .chain_alloc = &qed_chain_alloc,
1400 .chain_free = &qed_chain_free,
1401 .get_coalesce = &qed_get_coalesce,
1402 .set_coalesce = &qed_set_coalesce,
1403 .set_led = &qed_set_led,
1406 void qed_get_protocol_stats(struct qed_dev *cdev,
1407 enum qed_mcp_protocol_type type,
1408 union qed_mcp_protocol_stats *stats)
1410 struct qed_eth_stats eth_stats;
1412 memset(stats, 0, sizeof(*stats));
1415 case QED_MCP_LAN_STATS:
1416 qed_get_vport_stats(cdev, ð_stats);
1417 stats->lan_stats.ucast_rx_pkts = eth_stats.rx_ucast_pkts;
1418 stats->lan_stats.ucast_tx_pkts = eth_stats.tx_ucast_pkts;
1419 stats->lan_stats.fcs_err = -1;
1422 DP_ERR(cdev, "Invalid protocol type = %d\n", type);