1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
9 #include <linux/types.h>
10 #include <asm/byteorder.h>
11 #include <linux/delay.h>
12 #include <linux/errno.h>
13 #include <linux/kernel.h>
14 #include <linux/slab.h>
15 #include <linux/spinlock.h>
16 #include <linux/string.h>
22 #include "qed_reg_addr.h"
23 #include "qed_sriov.h"
25 #define CHIP_MCP_RESP_ITER_US 10
27 #define QED_DRV_MB_MAX_RETRIES (500 * 1000) /* Account for 5 sec */
28 #define QED_MCP_RESET_RETRIES (50 * 1000) /* Account for 500 msec */
30 #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \
31 qed_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \
34 #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \
35 qed_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset))
37 #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \
38 DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \
39 offsetof(struct public_drv_mb, _field), _val)
41 #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \
42 DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \
43 offsetof(struct public_drv_mb, _field))
45 #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \
46 DRV_ID_PDA_COMP_VER_SHIFT)
48 #define MCP_BYTES_PER_MBIT_SHIFT 17
50 bool qed_mcp_is_init(struct qed_hwfn *p_hwfn)
52 if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base)
57 void qed_mcp_cmd_port_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
59 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
61 u32 mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, addr);
63 p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize,
65 DP_VERBOSE(p_hwfn, QED_MSG_SP,
66 "port_addr = 0x%x, port_id 0x%02x\n",
67 p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn));
70 void qed_mcp_read_mb(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
72 u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length);
75 if (!p_hwfn->mcp_info->public_base)
78 for (i = 0; i < length; i++) {
79 tmp = qed_rd(p_hwfn, p_ptt,
80 p_hwfn->mcp_info->mfw_mb_addr +
81 (i << 2) + sizeof(u32));
83 /* The MB data is actually BE; Need to force it to cpu */
84 ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] =
85 be32_to_cpu((__force __be32)tmp);
89 int qed_mcp_free(struct qed_hwfn *p_hwfn)
91 if (p_hwfn->mcp_info) {
92 kfree(p_hwfn->mcp_info->mfw_mb_cur);
93 kfree(p_hwfn->mcp_info->mfw_mb_shadow);
95 kfree(p_hwfn->mcp_info);
100 static int qed_load_mcp_offsets(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
102 struct qed_mcp_info *p_info = p_hwfn->mcp_info;
103 u32 drv_mb_offsize, mfw_mb_offsize;
104 u32 mcp_pf_id = MCP_PF_ID(p_hwfn);
106 p_info->public_base = qed_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR);
107 if (!p_info->public_base)
110 p_info->public_base |= GRCBASE_MCP;
112 /* Calculate the driver and MFW mailbox address */
113 drv_mb_offsize = qed_rd(p_hwfn, p_ptt,
114 SECTION_OFFSIZE_ADDR(p_info->public_base,
116 p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id);
117 DP_VERBOSE(p_hwfn, QED_MSG_SP,
118 "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x mcp_pf_id = 0x%x\n",
119 drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id);
121 /* Set the MFW MB address */
122 mfw_mb_offsize = qed_rd(p_hwfn, p_ptt,
123 SECTION_OFFSIZE_ADDR(p_info->public_base,
125 p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id);
126 p_info->mfw_mb_length = (u16)qed_rd(p_hwfn, p_ptt, p_info->mfw_mb_addr);
128 /* Get the current driver mailbox sequence before sending
131 p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
132 DRV_MSG_SEQ_NUMBER_MASK;
134 /* Get current FW pulse sequence */
135 p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) &
138 p_info->mcp_hist = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
143 int qed_mcp_cmd_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
145 struct qed_mcp_info *p_info;
148 /* Allocate mcp_info structure */
149 p_hwfn->mcp_info = kzalloc(sizeof(*p_hwfn->mcp_info), GFP_KERNEL);
150 if (!p_hwfn->mcp_info)
152 p_info = p_hwfn->mcp_info;
154 if (qed_load_mcp_offsets(p_hwfn, p_ptt) != 0) {
155 DP_NOTICE(p_hwfn, "MCP is not initialized\n");
156 /* Do not free mcp_info here, since public_base indicate that
157 * the MCP is not initialized
162 size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32);
163 p_info->mfw_mb_cur = kzalloc(size, GFP_KERNEL);
164 p_info->mfw_mb_shadow = kzalloc(size, GFP_KERNEL);
165 if (!p_info->mfw_mb_shadow || !p_info->mfw_mb_addr)
168 /* Initialize the MFW spinlock */
169 spin_lock_init(&p_info->lock);
174 qed_mcp_free(p_hwfn);
178 /* Locks the MFW mailbox of a PF to ensure a single access.
179 * The lock is achieved in most cases by holding a spinlock, causing other
180 * threads to wait till a previous access is done.
181 * In some cases (currently when a [UN]LOAD_REQ commands are sent), the single
182 * access is achieved by setting a blocking flag, which will fail other
183 * competing contexts to send their mailboxes.
185 static int qed_mcp_mb_lock(struct qed_hwfn *p_hwfn, u32 cmd)
187 spin_lock_bh(&p_hwfn->mcp_info->lock);
189 /* The spinlock shouldn't be acquired when the mailbox command is
190 * [UN]LOAD_REQ, since the engine is locked by the MFW, and a parallel
191 * pending [UN]LOAD_REQ command of another PF together with a spinlock
192 * (i.e. interrupts are disabled) - can lead to a deadlock.
193 * It is assumed that for a single PF, no other mailbox commands can be
194 * sent from another context while sending LOAD_REQ, and that any
195 * parallel commands to UNLOAD_REQ can be cancelled.
197 if (cmd == DRV_MSG_CODE_LOAD_DONE || cmd == DRV_MSG_CODE_UNLOAD_DONE)
198 p_hwfn->mcp_info->block_mb_sending = false;
200 if (p_hwfn->mcp_info->block_mb_sending) {
202 "Trying to send a MFW mailbox command [0x%x] in parallel to [UN]LOAD_REQ. Aborting.\n",
204 spin_unlock_bh(&p_hwfn->mcp_info->lock);
208 if (cmd == DRV_MSG_CODE_LOAD_REQ || cmd == DRV_MSG_CODE_UNLOAD_REQ) {
209 p_hwfn->mcp_info->block_mb_sending = true;
210 spin_unlock_bh(&p_hwfn->mcp_info->lock);
216 static void qed_mcp_mb_unlock(struct qed_hwfn *p_hwfn, u32 cmd)
218 if (cmd != DRV_MSG_CODE_LOAD_REQ && cmd != DRV_MSG_CODE_UNLOAD_REQ)
219 spin_unlock_bh(&p_hwfn->mcp_info->lock);
222 int qed_mcp_reset(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
224 u32 seq = ++p_hwfn->mcp_info->drv_mb_seq;
225 u8 delay = CHIP_MCP_RESP_ITER_US;
226 u32 org_mcp_reset_seq, cnt = 0;
229 /* Ensure that only a single thread is accessing the mailbox at a
232 rc = qed_mcp_mb_lock(p_hwfn, DRV_MSG_CODE_MCP_RESET);
236 /* Set drv command along with the updated sequence */
237 org_mcp_reset_seq = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
238 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header,
239 (DRV_MSG_CODE_MCP_RESET | seq));
242 /* Wait for MFW response */
244 /* Give the FW up to 500 second (50*1000*10usec) */
245 } while ((org_mcp_reset_seq == qed_rd(p_hwfn, p_ptt,
246 MISCS_REG_GENERIC_POR_0)) &&
247 (cnt++ < QED_MCP_RESET_RETRIES));
249 if (org_mcp_reset_seq !=
250 qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
251 DP_VERBOSE(p_hwfn, QED_MSG_SP,
252 "MCP was reset after %d usec\n", cnt * delay);
254 DP_ERR(p_hwfn, "Failed to reset MCP\n");
258 qed_mcp_mb_unlock(p_hwfn, DRV_MSG_CODE_MCP_RESET);
263 static int qed_do_mcp_cmd(struct qed_hwfn *p_hwfn,
264 struct qed_ptt *p_ptt,
270 u8 delay = CHIP_MCP_RESP_ITER_US;
271 u32 seq, cnt = 1, actual_mb_seq;
274 /* Get actual driver mailbox sequence */
275 actual_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
276 DRV_MSG_SEQ_NUMBER_MASK;
278 /* Use MCP history register to check if MCP reset occurred between
281 if (p_hwfn->mcp_info->mcp_hist !=
282 qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
283 DP_VERBOSE(p_hwfn, QED_MSG_SP, "Rereading MCP offsets\n");
284 qed_load_mcp_offsets(p_hwfn, p_ptt);
285 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
287 seq = ++p_hwfn->mcp_info->drv_mb_seq;
290 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, param);
292 /* Set drv command along with the updated sequence */
293 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (cmd | seq));
295 DP_VERBOSE(p_hwfn, QED_MSG_SP,
296 "wrote command (%x) to MFW MB param 0x%08x\n",
300 /* Wait for MFW response */
302 *o_mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header);
304 /* Give the FW up to 5 second (500*10ms) */
305 } while ((seq != (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) &&
306 (cnt++ < QED_DRV_MB_MAX_RETRIES));
308 DP_VERBOSE(p_hwfn, QED_MSG_SP,
309 "[after %d ms] read (%x) seq is (%x) from FW MB\n",
310 cnt * delay, *o_mcp_resp, seq);
312 /* Is this a reply to our command? */
313 if (seq == (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) {
314 *o_mcp_resp &= FW_MSG_CODE_MASK;
315 /* Get the MCP param */
316 *o_mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param);
319 DP_ERR(p_hwfn, "MFW failed to respond [cmd 0x%x param 0x%x]\n",
327 static int qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn,
328 struct qed_ptt *p_ptt,
329 struct qed_mcp_mb_params *p_mb_params)
334 /* MCP not initialized */
335 if (!qed_mcp_is_init(p_hwfn)) {
336 DP_NOTICE(p_hwfn, "MFW is not initialized!\n");
340 union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
341 offsetof(struct public_drv_mb, union_data);
343 /* Ensure that only a single thread is accessing the mailbox at a
346 rc = qed_mcp_mb_lock(p_hwfn, p_mb_params->cmd);
350 if (p_mb_params->p_data_src != NULL)
351 qed_memcpy_to(p_hwfn, p_ptt, union_data_addr,
352 p_mb_params->p_data_src,
353 sizeof(*p_mb_params->p_data_src));
355 rc = qed_do_mcp_cmd(p_hwfn, p_ptt, p_mb_params->cmd,
356 p_mb_params->param, &p_mb_params->mcp_resp,
357 &p_mb_params->mcp_param);
359 if (p_mb_params->p_data_dst != NULL)
360 qed_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst,
362 sizeof(*p_mb_params->p_data_dst));
364 qed_mcp_mb_unlock(p_hwfn, p_mb_params->cmd);
369 int qed_mcp_cmd(struct qed_hwfn *p_hwfn,
370 struct qed_ptt *p_ptt,
376 struct qed_mcp_mb_params mb_params;
379 memset(&mb_params, 0, sizeof(mb_params));
381 mb_params.param = param;
382 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
386 *o_mcp_resp = mb_params.mcp_resp;
387 *o_mcp_param = mb_params.mcp_param;
392 int qed_mcp_load_req(struct qed_hwfn *p_hwfn,
393 struct qed_ptt *p_ptt, u32 *p_load_code)
395 struct qed_dev *cdev = p_hwfn->cdev;
396 struct qed_mcp_mb_params mb_params;
397 union drv_union_data union_data;
400 memset(&mb_params, 0, sizeof(mb_params));
402 mb_params.cmd = DRV_MSG_CODE_LOAD_REQ;
403 mb_params.param = PDA_COMP | DRV_ID_MCP_HSI_VER_CURRENT |
405 memcpy(&union_data.ver_str, cdev->ver_str, MCP_DRV_VER_STR_SIZE);
406 mb_params.p_data_src = &union_data;
407 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
409 /* if mcp fails to respond we must abort */
411 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
415 *p_load_code = mb_params.mcp_resp;
417 /* If MFW refused (e.g. other port is in diagnostic mode) we
418 * must abort. This can happen in the following cases:
419 * - Other port is in diagnostic mode
420 * - Previously loaded function on the engine is not compliant with
422 * - MFW cannot cope with the requester's DRV_MFW_HSI_VERSION.
425 if (!(*p_load_code) ||
426 ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI) ||
427 ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_PDA) ||
428 ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG)) {
429 DP_ERR(p_hwfn, "MCP refused load request, aborting\n");
436 static void qed_mcp_handle_vf_flr(struct qed_hwfn *p_hwfn,
437 struct qed_ptt *p_ptt)
439 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
441 u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr);
442 u32 path_addr = SECTION_ADDR(mfw_path_offsize,
443 QED_PATH_ID(p_hwfn));
444 u32 disabled_vfs[VF_MAX_STATIC / 32];
449 "Reading Disabled VF information from [offset %08x], path_addr %08x\n",
450 mfw_path_offsize, path_addr);
452 for (i = 0; i < (VF_MAX_STATIC / 32); i++) {
453 disabled_vfs[i] = qed_rd(p_hwfn, p_ptt,
455 offsetof(struct public_path,
458 DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV),
459 "FLR-ed VFs [%08x,...,%08x] - %08x\n",
460 i * 32, (i + 1) * 32 - 1, disabled_vfs[i]);
463 if (qed_iov_mark_vf_flr(p_hwfn, disabled_vfs))
464 qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG);
467 int qed_mcp_ack_vf_flr(struct qed_hwfn *p_hwfn,
468 struct qed_ptt *p_ptt, u32 *vfs_to_ack)
470 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
472 u32 mfw_func_offsize = qed_rd(p_hwfn, p_ptt, addr);
473 u32 func_addr = SECTION_ADDR(mfw_func_offsize,
475 struct qed_mcp_mb_params mb_params;
476 union drv_union_data union_data;
480 for (i = 0; i < (VF_MAX_STATIC / 32); i++)
481 DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV),
482 "Acking VFs [%08x,...,%08x] - %08x\n",
483 i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]);
485 memset(&mb_params, 0, sizeof(mb_params));
486 mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE;
487 memcpy(&union_data.ack_vf_disabled, vfs_to_ack, VF_MAX_STATIC / 8);
488 mb_params.p_data_src = &union_data;
489 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
491 DP_NOTICE(p_hwfn, "Failed to pass ACK for VF flr to MFW\n");
495 /* Clear the ACK bits */
496 for (i = 0; i < (VF_MAX_STATIC / 32); i++)
497 qed_wr(p_hwfn, p_ptt,
499 offsetof(struct public_func, drv_ack_vf_disabled) +
505 static void qed_mcp_handle_transceiver_change(struct qed_hwfn *p_hwfn,
506 struct qed_ptt *p_ptt)
508 u32 transceiver_state;
510 transceiver_state = qed_rd(p_hwfn, p_ptt,
511 p_hwfn->mcp_info->port_addr +
512 offsetof(struct public_port,
516 (NETIF_MSG_HW | QED_MSG_SP),
517 "Received transceiver state update [0x%08x] from mfw [Addr 0x%x]\n",
519 (u32)(p_hwfn->mcp_info->port_addr +
520 offsetof(struct public_port, transceiver_data)));
522 transceiver_state = GET_FIELD(transceiver_state,
523 ETH_TRANSCEIVER_STATE);
525 if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT)
526 DP_NOTICE(p_hwfn, "Transceiver is present.\n");
528 DP_NOTICE(p_hwfn, "Transceiver is unplugged.\n");
531 static void qed_mcp_handle_link_change(struct qed_hwfn *p_hwfn,
532 struct qed_ptt *p_ptt, bool b_reset)
534 struct qed_mcp_link_state *p_link;
538 p_link = &p_hwfn->mcp_info->link_output;
539 memset(p_link, 0, sizeof(*p_link));
541 status = qed_rd(p_hwfn, p_ptt,
542 p_hwfn->mcp_info->port_addr +
543 offsetof(struct public_port, link_status));
544 DP_VERBOSE(p_hwfn, (NETIF_MSG_LINK | QED_MSG_SP),
545 "Received link update [0x%08x] from mfw [Addr 0x%x]\n",
547 (u32)(p_hwfn->mcp_info->port_addr +
548 offsetof(struct public_port, link_status)));
550 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
551 "Resetting link indications\n");
555 if (p_hwfn->b_drv_link_init)
556 p_link->link_up = !!(status & LINK_STATUS_LINK_UP);
558 p_link->link_up = false;
560 p_link->full_duplex = true;
561 switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) {
562 case LINK_STATUS_SPEED_AND_DUPLEX_100G:
563 p_link->speed = 100000;
565 case LINK_STATUS_SPEED_AND_DUPLEX_50G:
566 p_link->speed = 50000;
568 case LINK_STATUS_SPEED_AND_DUPLEX_40G:
569 p_link->speed = 40000;
571 case LINK_STATUS_SPEED_AND_DUPLEX_25G:
572 p_link->speed = 25000;
574 case LINK_STATUS_SPEED_AND_DUPLEX_20G:
575 p_link->speed = 20000;
577 case LINK_STATUS_SPEED_AND_DUPLEX_10G:
578 p_link->speed = 10000;
580 case LINK_STATUS_SPEED_AND_DUPLEX_1000THD:
581 p_link->full_duplex = false;
583 case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD:
584 p_link->speed = 1000;
590 if (p_link->link_up && p_link->speed)
591 p_link->line_speed = p_link->speed;
593 p_link->line_speed = 0;
595 max_bw = p_hwfn->mcp_info->func_info.bandwidth_max;
596 min_bw = p_hwfn->mcp_info->func_info.bandwidth_min;
598 /* Max bandwidth configuration */
599 __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, p_link, max_bw);
601 /* Min bandwidth configuration */
602 __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, p_link, min_bw);
603 qed_configure_vp_wfq_on_link_change(p_hwfn->cdev, p_link->min_pf_rate);
605 p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED);
606 p_link->an_complete = !!(status &
607 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE);
608 p_link->parallel_detection = !!(status &
609 LINK_STATUS_PARALLEL_DETECTION_USED);
610 p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED);
612 p_link->partner_adv_speed |=
613 (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ?
614 QED_LINK_PARTNER_SPEED_1G_FD : 0;
615 p_link->partner_adv_speed |=
616 (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ?
617 QED_LINK_PARTNER_SPEED_1G_HD : 0;
618 p_link->partner_adv_speed |=
619 (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ?
620 QED_LINK_PARTNER_SPEED_10G : 0;
621 p_link->partner_adv_speed |=
622 (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ?
623 QED_LINK_PARTNER_SPEED_20G : 0;
624 p_link->partner_adv_speed |=
625 (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ?
626 QED_LINK_PARTNER_SPEED_25G : 0;
627 p_link->partner_adv_speed |=
628 (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ?
629 QED_LINK_PARTNER_SPEED_40G : 0;
630 p_link->partner_adv_speed |=
631 (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ?
632 QED_LINK_PARTNER_SPEED_50G : 0;
633 p_link->partner_adv_speed |=
634 (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ?
635 QED_LINK_PARTNER_SPEED_100G : 0;
637 p_link->partner_tx_flow_ctrl_en =
638 !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED);
639 p_link->partner_rx_flow_ctrl_en =
640 !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
642 switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) {
643 case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE:
644 p_link->partner_adv_pause = QED_LINK_PARTNER_SYMMETRIC_PAUSE;
646 case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE:
647 p_link->partner_adv_pause = QED_LINK_PARTNER_ASYMMETRIC_PAUSE;
649 case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE:
650 p_link->partner_adv_pause = QED_LINK_PARTNER_BOTH_PAUSE;
653 p_link->partner_adv_pause = 0;
656 p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT);
658 qed_link_update(p_hwfn);
661 int qed_mcp_set_link(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, bool b_up)
663 struct qed_mcp_link_params *params = &p_hwfn->mcp_info->link_input;
664 struct qed_mcp_mb_params mb_params;
665 union drv_union_data union_data;
666 struct eth_phy_cfg *phy_cfg;
670 /* Set the shmem configuration according to params */
671 phy_cfg = &union_data.drv_phy_cfg;
672 memset(phy_cfg, 0, sizeof(*phy_cfg));
673 cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET;
674 if (!params->speed.autoneg)
675 phy_cfg->speed = params->speed.forced_speed;
676 phy_cfg->pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0;
677 phy_cfg->pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0;
678 phy_cfg->pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0;
679 phy_cfg->adv_speed = params->speed.advertised_speeds;
680 phy_cfg->loopback_mode = params->loopback_mode;
682 p_hwfn->b_drv_link_init = b_up;
685 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
686 "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x, features 0x%08x\n",
690 phy_cfg->loopback_mode,
691 phy_cfg->feature_config_flags);
693 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
697 memset(&mb_params, 0, sizeof(mb_params));
699 mb_params.p_data_src = &union_data;
700 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
702 /* if mcp fails to respond we must abort */
704 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
708 /* Reset the link status if needed */
710 qed_mcp_handle_link_change(p_hwfn, p_ptt, true);
715 static void qed_mcp_send_protocol_stats(struct qed_hwfn *p_hwfn,
716 struct qed_ptt *p_ptt,
717 enum MFW_DRV_MSG_TYPE type)
719 enum qed_mcp_protocol_type stats_type;
720 union qed_mcp_protocol_stats stats;
721 struct qed_mcp_mb_params mb_params;
722 union drv_union_data union_data;
726 case MFW_DRV_MSG_GET_LAN_STATS:
727 stats_type = QED_MCP_LAN_STATS;
728 hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN;
730 case MFW_DRV_MSG_GET_FCOE_STATS:
731 stats_type = QED_MCP_FCOE_STATS;
732 hsi_param = DRV_MSG_CODE_STATS_TYPE_FCOE;
734 case MFW_DRV_MSG_GET_ISCSI_STATS:
735 stats_type = QED_MCP_ISCSI_STATS;
736 hsi_param = DRV_MSG_CODE_STATS_TYPE_ISCSI;
738 case MFW_DRV_MSG_GET_RDMA_STATS:
739 stats_type = QED_MCP_RDMA_STATS;
740 hsi_param = DRV_MSG_CODE_STATS_TYPE_RDMA;
743 DP_NOTICE(p_hwfn, "Invalid protocol type %d\n", type);
747 qed_get_protocol_stats(p_hwfn->cdev, stats_type, &stats);
749 memset(&mb_params, 0, sizeof(mb_params));
750 mb_params.cmd = DRV_MSG_CODE_GET_STATS;
751 mb_params.param = hsi_param;
752 memcpy(&union_data, &stats, sizeof(stats));
753 mb_params.p_data_src = &union_data;
754 qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
757 static void qed_read_pf_bandwidth(struct qed_hwfn *p_hwfn,
758 struct public_func *p_shmem_info)
760 struct qed_mcp_function_info *p_info;
762 p_info = &p_hwfn->mcp_info->func_info;
764 p_info->bandwidth_min = (p_shmem_info->config &
765 FUNC_MF_CFG_MIN_BW_MASK) >>
766 FUNC_MF_CFG_MIN_BW_SHIFT;
767 if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) {
769 "bandwidth minimum out of bounds [%02x]. Set to 1\n",
770 p_info->bandwidth_min);
771 p_info->bandwidth_min = 1;
774 p_info->bandwidth_max = (p_shmem_info->config &
775 FUNC_MF_CFG_MAX_BW_MASK) >>
776 FUNC_MF_CFG_MAX_BW_SHIFT;
777 if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) {
779 "bandwidth maximum out of bounds [%02x]. Set to 100\n",
780 p_info->bandwidth_max);
781 p_info->bandwidth_max = 100;
785 static u32 qed_mcp_get_shmem_func(struct qed_hwfn *p_hwfn,
786 struct qed_ptt *p_ptt,
787 struct public_func *p_data, int pfid)
789 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
791 u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr);
792 u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid);
795 memset(p_data, 0, sizeof(*p_data));
797 size = min_t(u32, sizeof(*p_data), QED_SECTION_SIZE(mfw_path_offsize));
798 for (i = 0; i < size / sizeof(u32); i++)
799 ((u32 *)p_data)[i] = qed_rd(p_hwfn, p_ptt,
800 func_addr + (i << 2));
804 static void qed_mcp_update_bw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
806 struct qed_mcp_function_info *p_info;
807 struct public_func shmem_info;
808 u32 resp = 0, param = 0;
810 qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
812 qed_read_pf_bandwidth(p_hwfn, &shmem_info);
814 p_info = &p_hwfn->mcp_info->func_info;
816 qed_configure_pf_min_bandwidth(p_hwfn->cdev, p_info->bandwidth_min);
817 qed_configure_pf_max_bandwidth(p_hwfn->cdev, p_info->bandwidth_max);
819 /* Acknowledge the MFW */
820 qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp,
824 int qed_mcp_handle_events(struct qed_hwfn *p_hwfn,
825 struct qed_ptt *p_ptt)
827 struct qed_mcp_info *info = p_hwfn->mcp_info;
832 DP_VERBOSE(p_hwfn, QED_MSG_SP, "Received message from MFW\n");
834 /* Read Messages from MFW */
835 qed_mcp_read_mb(p_hwfn, p_ptt);
837 /* Compare current messages to old ones */
838 for (i = 0; i < info->mfw_mb_length; i++) {
839 if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i])
844 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
845 "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n",
846 i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]);
849 case MFW_DRV_MSG_LINK_CHANGE:
850 qed_mcp_handle_link_change(p_hwfn, p_ptt, false);
852 case MFW_DRV_MSG_VF_DISABLED:
853 qed_mcp_handle_vf_flr(p_hwfn, p_ptt);
855 case MFW_DRV_MSG_LLDP_DATA_UPDATED:
856 qed_dcbx_mib_update_event(p_hwfn, p_ptt,
857 QED_DCBX_REMOTE_LLDP_MIB);
859 case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED:
860 qed_dcbx_mib_update_event(p_hwfn, p_ptt,
861 QED_DCBX_REMOTE_MIB);
863 case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED:
864 qed_dcbx_mib_update_event(p_hwfn, p_ptt,
865 QED_DCBX_OPERATIONAL_MIB);
867 case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE:
868 qed_mcp_handle_transceiver_change(p_hwfn, p_ptt);
870 case MFW_DRV_MSG_GET_LAN_STATS:
871 case MFW_DRV_MSG_GET_FCOE_STATS:
872 case MFW_DRV_MSG_GET_ISCSI_STATS:
873 case MFW_DRV_MSG_GET_RDMA_STATS:
874 qed_mcp_send_protocol_stats(p_hwfn, p_ptt, i);
876 case MFW_DRV_MSG_BW_UPDATE:
877 qed_mcp_update_bw(p_hwfn, p_ptt);
880 DP_NOTICE(p_hwfn, "Unimplemented MFW message %d\n", i);
886 for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) {
887 __be32 val = cpu_to_be32(((u32 *)info->mfw_mb_cur)[i]);
889 /* MFW expect answer in BE, so we force write in that format */
890 qed_wr(p_hwfn, p_ptt,
891 info->mfw_mb_addr + sizeof(u32) +
892 MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) *
893 sizeof(u32) + i * sizeof(u32),
899 "Received an MFW message indication but no new message!\n");
903 /* Copy the new mfw messages into the shadow */
904 memcpy(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length);
909 int qed_mcp_get_mfw_ver(struct qed_hwfn *p_hwfn,
910 struct qed_ptt *p_ptt,
911 u32 *p_mfw_ver, u32 *p_running_bundle_id)
915 if (IS_VF(p_hwfn->cdev)) {
916 if (p_hwfn->vf_iov_info) {
917 struct pfvf_acquire_resp_tlv *p_resp;
919 p_resp = &p_hwfn->vf_iov_info->acquire_resp;
920 *p_mfw_ver = p_resp->pfdev_info.mfw_ver;
925 "VF requested MFW version prior to ACQUIRE\n");
930 global_offsize = qed_rd(p_hwfn, p_ptt,
931 SECTION_OFFSIZE_ADDR(p_hwfn->
932 mcp_info->public_base,
935 qed_rd(p_hwfn, p_ptt,
936 SECTION_ADDR(global_offsize,
937 0) + offsetof(struct public_global, mfw_ver));
939 if (p_running_bundle_id != NULL) {
940 *p_running_bundle_id = qed_rd(p_hwfn, p_ptt,
941 SECTION_ADDR(global_offsize, 0) +
942 offsetof(struct public_global,
949 int qed_mcp_get_media_type(struct qed_dev *cdev, u32 *p_media_type)
951 struct qed_hwfn *p_hwfn = &cdev->hwfns[0];
952 struct qed_ptt *p_ptt;
957 if (!qed_mcp_is_init(p_hwfn)) {
958 DP_NOTICE(p_hwfn, "MFW is not initialized!\n");
962 *p_media_type = MEDIA_UNSPECIFIED;
964 p_ptt = qed_ptt_acquire(p_hwfn);
968 *p_media_type = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
969 offsetof(struct public_port, media_type));
971 qed_ptt_release(p_hwfn, p_ptt);
977 qed_mcp_get_shmem_proto(struct qed_hwfn *p_hwfn,
978 struct public_func *p_info,
979 enum qed_pci_personality *p_proto)
983 switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) {
984 case FUNC_MF_CFG_PROTOCOL_ETHERNET:
985 if (test_bit(QED_DEV_CAP_ROCE,
986 &p_hwfn->hw_info.device_capabilities))
987 *p_proto = QED_PCI_ETH_ROCE;
989 *p_proto = QED_PCI_ETH;
991 case FUNC_MF_CFG_PROTOCOL_ISCSI:
992 *p_proto = QED_PCI_ISCSI;
994 case FUNC_MF_CFG_PROTOCOL_ROCE:
995 DP_NOTICE(p_hwfn, "RoCE personality is not a valid value!\n");
1005 int qed_mcp_fill_shmem_func_info(struct qed_hwfn *p_hwfn,
1006 struct qed_ptt *p_ptt)
1008 struct qed_mcp_function_info *info;
1009 struct public_func shmem_info;
1011 qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1012 info = &p_hwfn->mcp_info->func_info;
1014 info->pause_on_host = (shmem_info.config &
1015 FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0;
1017 if (qed_mcp_get_shmem_proto(p_hwfn, &shmem_info, &info->protocol)) {
1018 DP_ERR(p_hwfn, "Unknown personality %08x\n",
1019 (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK));
1023 qed_read_pf_bandwidth(p_hwfn, &shmem_info);
1025 if (shmem_info.mac_upper || shmem_info.mac_lower) {
1026 info->mac[0] = (u8)(shmem_info.mac_upper >> 8);
1027 info->mac[1] = (u8)(shmem_info.mac_upper);
1028 info->mac[2] = (u8)(shmem_info.mac_lower >> 24);
1029 info->mac[3] = (u8)(shmem_info.mac_lower >> 16);
1030 info->mac[4] = (u8)(shmem_info.mac_lower >> 8);
1031 info->mac[5] = (u8)(shmem_info.mac_lower);
1033 DP_NOTICE(p_hwfn, "MAC is 0 in shmem\n");
1036 info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_upper |
1037 (((u64)shmem_info.fcoe_wwn_port_name_lower) << 32);
1038 info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_upper |
1039 (((u64)shmem_info.fcoe_wwn_node_name_lower) << 32);
1041 info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK);
1043 DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_IFUP),
1044 "Read configuration from shmem: pause_on_host %02x protocol %02x BW [%02x - %02x] MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %llx node %llx ovlan %04x\n",
1045 info->pause_on_host, info->protocol,
1046 info->bandwidth_min, info->bandwidth_max,
1047 info->mac[0], info->mac[1], info->mac[2],
1048 info->mac[3], info->mac[4], info->mac[5],
1049 info->wwn_port, info->wwn_node, info->ovlan);
1054 struct qed_mcp_link_params
1055 *qed_mcp_get_link_params(struct qed_hwfn *p_hwfn)
1057 if (!p_hwfn || !p_hwfn->mcp_info)
1059 return &p_hwfn->mcp_info->link_input;
1062 struct qed_mcp_link_state
1063 *qed_mcp_get_link_state(struct qed_hwfn *p_hwfn)
1065 if (!p_hwfn || !p_hwfn->mcp_info)
1067 return &p_hwfn->mcp_info->link_output;
1070 struct qed_mcp_link_capabilities
1071 *qed_mcp_get_link_capabilities(struct qed_hwfn *p_hwfn)
1073 if (!p_hwfn || !p_hwfn->mcp_info)
1075 return &p_hwfn->mcp_info->link_capabilities;
1078 int qed_mcp_drain(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1080 u32 resp = 0, param = 0;
1083 rc = qed_mcp_cmd(p_hwfn, p_ptt,
1084 DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, ¶m);
1086 /* Wait for the drain to complete before returning */
1092 int qed_mcp_get_flash_size(struct qed_hwfn *p_hwfn,
1093 struct qed_ptt *p_ptt, u32 *p_flash_size)
1097 if (IS_VF(p_hwfn->cdev))
1100 flash_size = qed_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4);
1101 flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >>
1102 MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT;
1103 flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT));
1105 *p_flash_size = flash_size;
1110 int qed_mcp_config_vf_msix(struct qed_hwfn *p_hwfn,
1111 struct qed_ptt *p_ptt, u8 vf_id, u8 num)
1113 u32 resp = 0, param = 0, rc_param = 0;
1116 /* Only Leader can configure MSIX, and need to take CMT into account */
1117 if (!IS_LEAD_HWFN(p_hwfn))
1119 num *= p_hwfn->cdev->num_hwfns;
1121 param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) &
1122 DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK;
1123 param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) &
1124 DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK;
1126 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param,
1129 if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) {
1130 DP_NOTICE(p_hwfn, "VF[%d]: MFW failed to set MSI-X\n", vf_id);
1133 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
1134 "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n",
1142 qed_mcp_send_drv_version(struct qed_hwfn *p_hwfn,
1143 struct qed_ptt *p_ptt,
1144 struct qed_mcp_drv_version *p_ver)
1146 struct drv_version_stc *p_drv_version;
1147 struct qed_mcp_mb_params mb_params;
1148 union drv_union_data union_data;
1153 p_drv_version = &union_data.drv_version;
1154 p_drv_version->version = p_ver->version;
1156 for (i = 0; i < MCP_DRV_VER_STR_SIZE - 1; i += 4) {
1157 val = cpu_to_be32(p_ver->name[i]);
1158 *(__be32 *)&p_drv_version->name[i * sizeof(u32)] = val;
1161 memset(&mb_params, 0, sizeof(mb_params));
1162 mb_params.cmd = DRV_MSG_CODE_SET_VERSION;
1163 mb_params.p_data_src = &union_data;
1164 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1166 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1171 int qed_mcp_set_led(struct qed_hwfn *p_hwfn,
1172 struct qed_ptt *p_ptt, enum qed_led_mode mode)
1174 u32 resp = 0, param = 0, drv_mb_param;
1178 case QED_LED_MODE_ON:
1179 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON;
1181 case QED_LED_MODE_OFF:
1182 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF;
1184 case QED_LED_MODE_RESTORE:
1185 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER;
1188 DP_NOTICE(p_hwfn, "Invalid LED mode %d\n", mode);
1192 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE,
1193 drv_mb_param, &resp, ¶m);
1198 int qed_mcp_bist_register_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1200 u32 drv_mb_param = 0, rsp, param;
1203 drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST <<
1204 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
1206 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
1207 drv_mb_param, &rsp, ¶m);
1212 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
1213 (param != DRV_MB_PARAM_BIST_RC_PASSED))
1219 int qed_mcp_bist_clock_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1221 u32 drv_mb_param, rsp, param;
1224 drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST <<
1225 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
1227 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
1228 drv_mb_param, &rsp, ¶m);
1233 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
1234 (param != DRV_MB_PARAM_BIST_RC_PASSED))