1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015-2016 QLogic Corporation
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 #include <linux/types.h>
33 #include <asm/byteorder.h>
34 #include <linux/bitops.h>
35 #include <linux/delay.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/errno.h>
38 #include <linux/etherdevice.h>
39 #include <linux/if_ether.h>
40 #include <linux/if_vlan.h>
43 #include <linux/ipv6.h>
44 #include <linux/kernel.h>
45 #include <linux/list.h>
46 #include <linux/module.h>
47 #include <linux/mutex.h>
48 #include <linux/pci.h>
49 #include <linux/slab.h>
50 #include <linux/spinlock.h>
51 #include <linux/string.h>
52 #include <linux/tcp.h>
53 #include <linux/bitops.h>
54 #include <linux/qed/qed_roce_if.h>
55 #include <linux/qed/qed_roce_if.h>
60 #include "qed_init_ops.h"
64 #include "qed_reg_addr.h"
68 void qed_async_roce_event(struct qed_hwfn *p_hwfn,
69 struct event_ring_entry *p_eqe)
71 struct qed_rdma_info *p_rdma_info = p_hwfn->p_rdma_info;
73 p_rdma_info->events.affiliated_event(p_rdma_info->events.context,
74 p_eqe->opcode, &p_eqe->data);
77 static int qed_rdma_bmap_alloc(struct qed_hwfn *p_hwfn,
78 struct qed_bmap *bmap, u32 max_count)
80 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "max_count = %08x\n", max_count);
82 bmap->max_count = max_count;
84 bmap->bitmap = kzalloc(BITS_TO_LONGS(max_count) * sizeof(long),
88 "qed bmap alloc failed: cannot allocate memory (bitmap)\n");
92 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocated bitmap %p\n",
97 static int qed_rdma_bmap_alloc_id(struct qed_hwfn *p_hwfn,
98 struct qed_bmap *bmap, u32 *id_num)
100 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "bmap = %p\n", bmap);
102 *id_num = find_first_zero_bit(bmap->bitmap, bmap->max_count);
104 if (*id_num >= bmap->max_count) {
105 DP_NOTICE(p_hwfn, "no id available max_count=%d\n",
110 __set_bit(*id_num, bmap->bitmap);
115 static void qed_bmap_release_id(struct qed_hwfn *p_hwfn,
116 struct qed_bmap *bmap, u32 id_num)
120 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "id_num = %08x", id_num);
121 if (id_num >= bmap->max_count)
124 b_acquired = test_and_clear_bit(id_num, bmap->bitmap);
126 DP_NOTICE(p_hwfn, "ID %d already released\n", id_num);
131 u32 qed_rdma_get_sb_id(void *p_hwfn, u32 rel_sb_id)
133 /* First sb id for RoCE is after all the l2 sb */
134 return FEAT_NUM((struct qed_hwfn *)p_hwfn, QED_PF_L2_QUE) + rel_sb_id;
137 u32 qed_rdma_query_cau_timer_res(void *rdma_cxt)
139 return QED_CAU_DEF_RX_TIMER_RES;
142 static int qed_rdma_alloc(struct qed_hwfn *p_hwfn,
143 struct qed_ptt *p_ptt,
144 struct qed_rdma_start_in_params *params)
146 struct qed_rdma_info *p_rdma_info;
147 u32 num_cons, num_tasks;
150 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocating RDMA\n");
152 /* Allocate a struct with current pf rdma info */
153 p_rdma_info = kzalloc(sizeof(*p_rdma_info), GFP_KERNEL);
156 "qed rdma alloc failed: cannot allocate memory (rdma info). rc = %d\n",
161 p_hwfn->p_rdma_info = p_rdma_info;
162 p_rdma_info->proto = PROTOCOLID_ROCE;
164 num_cons = qed_cxt_get_proto_cid_count(p_hwfn, p_rdma_info->proto, 0);
166 p_rdma_info->num_qps = num_cons / 2;
168 num_tasks = qed_cxt_get_proto_tid_count(p_hwfn, PROTOCOLID_ROCE);
170 /* Each MR uses a single task */
171 p_rdma_info->num_mrs = num_tasks;
173 /* Queue zone lines are shared between RoCE and L2 in such a way that
174 * they can be used by each without obstructing the other.
176 p_rdma_info->queue_zone_base = (u16)FEAT_NUM(p_hwfn, QED_L2_QUEUE);
178 /* Allocate a struct with device params and fill it */
179 p_rdma_info->dev = kzalloc(sizeof(*p_rdma_info->dev), GFP_KERNEL);
180 if (!p_rdma_info->dev) {
182 "qed rdma alloc failed: cannot allocate memory (rdma info dev). rc = %d\n",
187 /* Allocate a struct with port params and fill it */
188 p_rdma_info->port = kzalloc(sizeof(*p_rdma_info->port), GFP_KERNEL);
189 if (!p_rdma_info->port) {
191 "qed rdma alloc failed: cannot allocate memory (rdma info port). rc = %d\n",
196 /* Allocate bit map for pd's */
197 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->pd_map, RDMA_MAX_PDS);
199 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
200 "Failed to allocate pd_map, rc = %d\n",
205 /* Allocate DPI bitmap */
206 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->dpi_map,
209 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
210 "Failed to allocate DPI bitmap, rc = %d\n", rc);
214 /* Allocate bitmap for cq's. The maximum number of CQs is bounded to
215 * twice the number of QPs.
217 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->cq_map,
218 p_rdma_info->num_qps * 2);
220 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
221 "Failed to allocate cq bitmap, rc = %d\n", rc);
225 /* Allocate bitmap for toggle bit for cq icids
226 * We toggle the bit every time we create or resize cq for a given icid.
227 * The maximum number of CQs is bounded to twice the number of QPs.
229 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->toggle_bits,
230 p_rdma_info->num_qps * 2);
232 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
233 "Failed to allocate toogle bits, rc = %d\n", rc);
237 /* Allocate bitmap for itids */
238 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->tid_map,
239 p_rdma_info->num_mrs);
241 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
242 "Failed to allocate itids bitmaps, rc = %d\n", rc);
243 goto free_toggle_map;
246 /* Allocate bitmap for cids used for qps. */
247 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->cid_map, num_cons);
249 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
250 "Failed to allocate cid bitmap, rc = %d\n", rc);
254 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocation successful\n");
258 kfree(p_rdma_info->tid_map.bitmap);
260 kfree(p_rdma_info->toggle_bits.bitmap);
262 kfree(p_rdma_info->cq_map.bitmap);
264 kfree(p_rdma_info->dpi_map.bitmap);
266 kfree(p_rdma_info->pd_map.bitmap);
268 kfree(p_rdma_info->port);
270 kfree(p_rdma_info->dev);
277 void qed_rdma_resc_free(struct qed_hwfn *p_hwfn)
279 struct qed_rdma_info *p_rdma_info = p_hwfn->p_rdma_info;
281 kfree(p_rdma_info->cid_map.bitmap);
282 kfree(p_rdma_info->tid_map.bitmap);
283 kfree(p_rdma_info->toggle_bits.bitmap);
284 kfree(p_rdma_info->cq_map.bitmap);
285 kfree(p_rdma_info->dpi_map.bitmap);
286 kfree(p_rdma_info->pd_map.bitmap);
288 kfree(p_rdma_info->port);
289 kfree(p_rdma_info->dev);
294 static void qed_rdma_free(struct qed_hwfn *p_hwfn)
296 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Freeing RDMA\n");
298 qed_rdma_resc_free(p_hwfn);
301 static void qed_rdma_get_guid(struct qed_hwfn *p_hwfn, u8 *guid)
303 guid[0] = p_hwfn->hw_info.hw_mac_addr[0] ^ 2;
304 guid[1] = p_hwfn->hw_info.hw_mac_addr[1];
305 guid[2] = p_hwfn->hw_info.hw_mac_addr[2];
308 guid[5] = p_hwfn->hw_info.hw_mac_addr[3];
309 guid[6] = p_hwfn->hw_info.hw_mac_addr[4];
310 guid[7] = p_hwfn->hw_info.hw_mac_addr[5];
313 static void qed_rdma_init_events(struct qed_hwfn *p_hwfn,
314 struct qed_rdma_start_in_params *params)
316 struct qed_rdma_events *events;
318 events = &p_hwfn->p_rdma_info->events;
320 events->unaffiliated_event = params->events->unaffiliated_event;
321 events->affiliated_event = params->events->affiliated_event;
322 events->context = params->events->context;
325 static void qed_rdma_init_devinfo(struct qed_hwfn *p_hwfn,
326 struct qed_rdma_start_in_params *params)
328 struct qed_rdma_device *dev = p_hwfn->p_rdma_info->dev;
329 struct qed_dev *cdev = p_hwfn->cdev;
330 u32 pci_status_control;
333 /* Vendor specific information */
334 dev->vendor_id = cdev->vendor_id;
335 dev->vendor_part_id = cdev->device_id;
337 dev->fw_ver = (FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) |
338 (FW_REVISION_VERSION << 8) | (FW_ENGINEERING_VERSION);
340 qed_rdma_get_guid(p_hwfn, (u8 *)&dev->sys_image_guid);
341 dev->node_guid = dev->sys_image_guid;
343 dev->max_sge = min_t(u32, RDMA_MAX_SGE_PER_SQ_WQE,
344 RDMA_MAX_SGE_PER_RQ_WQE);
346 if (cdev->rdma_max_sge)
347 dev->max_sge = min_t(u32, cdev->rdma_max_sge, dev->max_sge);
349 dev->max_inline = ROCE_REQ_MAX_INLINE_DATA_SIZE;
351 dev->max_inline = (cdev->rdma_max_inline) ?
352 min_t(u32, cdev->rdma_max_inline, dev->max_inline) :
355 dev->max_wqe = QED_RDMA_MAX_WQE;
356 dev->max_cnq = (u8)FEAT_NUM(p_hwfn, QED_RDMA_CNQ);
358 /* The number of QPs may be higher than QED_ROCE_MAX_QPS, because
359 * it is up-aligned to 16 and then to ILT page size within qed cxt.
360 * This is OK in terms of ILT but we don't want to configure the FW
361 * above its abilities
363 num_qps = ROCE_MAX_QPS;
364 num_qps = min_t(u64, num_qps, p_hwfn->p_rdma_info->num_qps);
365 dev->max_qp = num_qps;
367 /* CQs uses the same icids that QPs use hence they are limited by the
368 * number of icids. There are two icids per QP.
370 dev->max_cq = num_qps * 2;
372 /* The number of mrs is smaller by 1 since the first is reserved */
373 dev->max_mr = p_hwfn->p_rdma_info->num_mrs - 1;
374 dev->max_mr_size = QED_RDMA_MAX_MR_SIZE;
376 /* The maximum CQE capacity per CQ supported.
377 * max number of cqes will be in two layer pbl,
378 * 8 is the pointer size in bytes
379 * 32 is the size of cq element in bytes
381 if (params->cq_mode == QED_RDMA_CQ_MODE_32_BITS)
382 dev->max_cqe = QED_RDMA_MAX_CQE_32_BIT;
384 dev->max_cqe = QED_RDMA_MAX_CQE_16_BIT;
387 dev->max_fmr = QED_RDMA_MAX_FMR;
388 dev->max_mr_mw_fmr_pbl = (PAGE_SIZE / 8) * (PAGE_SIZE / 8);
389 dev->max_mr_mw_fmr_size = dev->max_mr_mw_fmr_pbl * PAGE_SIZE;
390 dev->max_pkey = QED_RDMA_MAX_P_KEY;
392 dev->max_qp_resp_rd_atomic_resc = RDMA_RING_PAGE_SIZE /
393 (RDMA_RESP_RD_ATOMIC_ELM_SIZE * 2);
394 dev->max_qp_req_rd_atomic_resc = RDMA_RING_PAGE_SIZE /
395 RDMA_REQ_RD_ATOMIC_ELM_SIZE;
396 dev->max_dev_resp_rd_atomic_resc = dev->max_qp_resp_rd_atomic_resc *
397 p_hwfn->p_rdma_info->num_qps;
398 dev->page_size_caps = QED_RDMA_PAGE_SIZE_CAPS;
399 dev->dev_ack_delay = QED_RDMA_ACK_DELAY;
400 dev->max_pd = RDMA_MAX_PDS;
401 dev->max_ah = p_hwfn->p_rdma_info->num_qps;
402 dev->max_stats_queues = (u8)RESC_NUM(p_hwfn, QED_RDMA_STATS_QUEUE);
404 /* Set capablities */
406 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_RNR_NAK, 1);
407 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_PORT_ACTIVE_EVENT, 1);
408 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_PORT_CHANGE_EVENT, 1);
409 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_RESIZE_CQ, 1);
410 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_BASE_MEMORY_EXT, 1);
411 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_BASE_QUEUE_EXT, 1);
412 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_ZBVA, 1);
413 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_LOCAL_INV_FENCE, 1);
415 /* Check atomic operations support in PCI configuration space. */
416 pci_read_config_dword(cdev->pdev,
417 cdev->pdev->pcie_cap + PCI_EXP_DEVCTL2,
418 &pci_status_control);
420 if (pci_status_control & PCI_EXP_DEVCTL2_LTR_EN)
421 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_ATOMIC_OP, 1);
424 static void qed_rdma_init_port(struct qed_hwfn *p_hwfn)
426 struct qed_rdma_port *port = p_hwfn->p_rdma_info->port;
427 struct qed_rdma_device *dev = p_hwfn->p_rdma_info->dev;
429 port->port_state = p_hwfn->mcp_info->link_output.link_up ?
430 QED_RDMA_PORT_UP : QED_RDMA_PORT_DOWN;
432 port->max_msg_size = min_t(u64,
433 (dev->max_mr_mw_fmr_size *
434 p_hwfn->cdev->rdma_max_sge),
437 port->pkey_bad_counter = 0;
440 static int qed_rdma_init_hw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
442 u32 ll2_ethertype_en;
444 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Initializing HW\n");
445 p_hwfn->b_rdma_enabled_in_prs = false;
447 qed_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF, 0);
449 p_hwfn->rdma_prs_search_reg = PRS_REG_SEARCH_ROCE;
451 /* We delay writing to this reg until first cid is allocated. See
452 * qed_cxt_dynamic_ilt_alloc function for more details
454 ll2_ethertype_en = qed_rd(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN);
455 qed_wr(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN,
456 (ll2_ethertype_en | 0x01));
458 if (qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_ROCE) % 2) {
459 DP_NOTICE(p_hwfn, "The first RoCE's cid should be even\n");
463 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Initializing HW - Done\n");
467 static int qed_rdma_start_fw(struct qed_hwfn *p_hwfn,
468 struct qed_rdma_start_in_params *params,
469 struct qed_ptt *p_ptt)
471 struct rdma_init_func_ramrod_data *p_ramrod;
472 struct qed_rdma_cnq_params *p_cnq_pbl_list;
473 struct rdma_init_func_hdr *p_params_header;
474 struct rdma_cnq_params *p_cnq_params;
475 struct qed_sp_init_data init_data;
476 struct qed_spq_entry *p_ent;
480 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Starting FW\n");
482 /* Save the number of cnqs for the function close ramrod */
483 p_hwfn->p_rdma_info->num_cnqs = params->desired_cnq;
486 memset(&init_data, 0, sizeof(init_data));
487 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
488 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
490 rc = qed_sp_init_request(p_hwfn, &p_ent, RDMA_RAMROD_FUNC_INIT,
491 p_hwfn->p_rdma_info->proto, &init_data);
495 p_ramrod = &p_ent->ramrod.roce_init_func.rdma;
497 p_params_header = &p_ramrod->params_header;
498 p_params_header->cnq_start_offset = (u8)RESC_START(p_hwfn,
500 p_params_header->num_cnqs = params->desired_cnq;
502 if (params->cq_mode == QED_RDMA_CQ_MODE_16_BITS)
503 p_params_header->cq_ring_mode = 1;
505 p_params_header->cq_ring_mode = 0;
507 for (cnq_id = 0; cnq_id < params->desired_cnq; cnq_id++) {
508 sb_id = qed_rdma_get_sb_id(p_hwfn, cnq_id);
509 p_cnq_params = &p_ramrod->cnq_params[cnq_id];
510 p_cnq_pbl_list = ¶ms->cnq_pbl_list[cnq_id];
511 p_cnq_params->sb_num =
512 cpu_to_le16(p_hwfn->sbs_info[sb_id]->igu_sb_id);
514 p_cnq_params->sb_index = p_hwfn->pf_params.rdma_pf_params.gl_pi;
515 p_cnq_params->num_pbl_pages = p_cnq_pbl_list->num_pbl_pages;
517 DMA_REGPAIR_LE(p_cnq_params->pbl_base_addr,
518 p_cnq_pbl_list->pbl_ptr);
520 /* we assume here that cnq_id and qz_offset are the same */
521 p_cnq_params->queue_zone_num =
522 cpu_to_le16(p_hwfn->p_rdma_info->queue_zone_base +
526 return qed_spq_post(p_hwfn, p_ent, NULL);
529 static int qed_rdma_reserve_lkey(struct qed_hwfn *p_hwfn)
531 struct qed_rdma_device *dev = p_hwfn->p_rdma_info->dev;
533 /* The first DPI is reserved for the Kernel */
534 __set_bit(0, p_hwfn->p_rdma_info->dpi_map.bitmap);
536 /* Tid 0 will be used as the key for "reserved MR".
537 * The driver should allocate memory for it so it can be loaded but no
538 * ramrod should be passed on it.
540 qed_rdma_alloc_tid(p_hwfn, &dev->reserved_lkey);
541 if (dev->reserved_lkey != RDMA_RESERVED_LKEY) {
543 "Reserved lkey should be equal to RDMA_RESERVED_LKEY\n");
550 static int qed_rdma_setup(struct qed_hwfn *p_hwfn,
551 struct qed_ptt *p_ptt,
552 struct qed_rdma_start_in_params *params)
556 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA setup\n");
558 spin_lock_init(&p_hwfn->p_rdma_info->lock);
560 qed_rdma_init_devinfo(p_hwfn, params);
561 qed_rdma_init_port(p_hwfn);
562 qed_rdma_init_events(p_hwfn, params);
564 rc = qed_rdma_reserve_lkey(p_hwfn);
568 rc = qed_rdma_init_hw(p_hwfn, p_ptt);
572 return qed_rdma_start_fw(p_hwfn, params, p_ptt);
575 int qed_rdma_stop(void *rdma_cxt)
577 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
578 struct rdma_close_func_ramrod_data *p_ramrod;
579 struct qed_sp_init_data init_data;
580 struct qed_spq_entry *p_ent;
581 struct qed_ptt *p_ptt;
582 u32 ll2_ethertype_en;
585 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA stop\n");
587 p_ptt = qed_ptt_acquire(p_hwfn);
589 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Failed to acquire PTT\n");
593 /* Disable RoCE search */
594 qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 0);
595 p_hwfn->b_rdma_enabled_in_prs = false;
597 qed_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF, 0);
599 ll2_ethertype_en = qed_rd(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN);
601 qed_wr(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN,
602 (ll2_ethertype_en & 0xFFFE));
604 qed_ptt_release(p_hwfn, p_ptt);
607 memset(&init_data, 0, sizeof(init_data));
608 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
609 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
612 rc = qed_sp_init_request(p_hwfn, &p_ent, RDMA_RAMROD_FUNC_CLOSE,
613 p_hwfn->p_rdma_info->proto, &init_data);
617 p_ramrod = &p_ent->ramrod.rdma_close_func;
619 p_ramrod->num_cnqs = p_hwfn->p_rdma_info->num_cnqs;
620 p_ramrod->cnq_start_offset = (u8)RESC_START(p_hwfn, QED_RDMA_CNQ_RAM);
622 rc = qed_spq_post(p_hwfn, p_ent, NULL);
625 qed_rdma_free(p_hwfn);
627 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA stop done, rc = %d\n", rc);
631 int qed_rdma_add_user(void *rdma_cxt,
632 struct qed_rdma_add_user_out_params *out_params)
634 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
635 u32 dpi_start_offset;
639 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Adding User\n");
642 spin_lock_bh(&p_hwfn->p_rdma_info->lock);
643 rc = qed_rdma_bmap_alloc_id(p_hwfn, &p_hwfn->p_rdma_info->dpi_map,
645 spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
647 out_params->dpi = (u16)returned_id;
649 /* Calculate the corresponding DPI address */
650 dpi_start_offset = p_hwfn->dpi_start_offset;
652 out_params->dpi_addr = (u64)((u8 __iomem *)p_hwfn->doorbells +
654 ((out_params->dpi) * p_hwfn->dpi_size));
656 out_params->dpi_phys_addr = p_hwfn->cdev->db_phys_addr +
658 ((out_params->dpi) * p_hwfn->dpi_size);
660 out_params->dpi_size = p_hwfn->dpi_size;
662 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Adding user - done, rc = %d\n", rc);
666 struct qed_rdma_port *qed_rdma_query_port(void *rdma_cxt)
668 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
669 struct qed_rdma_port *p_port = p_hwfn->p_rdma_info->port;
671 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA Query port\n");
673 /* Link may have changed */
674 p_port->port_state = p_hwfn->mcp_info->link_output.link_up ?
675 QED_RDMA_PORT_UP : QED_RDMA_PORT_DOWN;
677 p_port->link_speed = p_hwfn->mcp_info->link_output.speed;
682 struct qed_rdma_device *qed_rdma_query_device(void *rdma_cxt)
684 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
686 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Query device\n");
688 /* Return struct with device parameters */
689 return p_hwfn->p_rdma_info->dev;
692 int qed_rdma_alloc_tid(void *rdma_cxt, u32 *itid)
694 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
697 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocate TID\n");
699 spin_lock_bh(&p_hwfn->p_rdma_info->lock);
700 rc = qed_rdma_bmap_alloc_id(p_hwfn,
701 &p_hwfn->p_rdma_info->tid_map, itid);
702 spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
706 rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_TASK, *itid);
708 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocate TID - done, rc = %d\n", rc);
712 void qed_rdma_cnq_prod_update(void *rdma_cxt, u8 qz_offset, u16 prod)
714 struct qed_hwfn *p_hwfn;
718 p_hwfn = (struct qed_hwfn *)rdma_cxt;
719 qz_num = p_hwfn->p_rdma_info->queue_zone_base + qz_offset;
720 addr = GTT_BAR0_MAP_REG_USDM_RAM +
721 USTORM_COMMON_QUEUE_CONS_OFFSET(qz_num);
723 REG_WR16(p_hwfn, addr, prod);
725 /* keep prod updates ordered */
729 static int qed_fill_rdma_dev_info(struct qed_dev *cdev,
730 struct qed_dev_rdma_info *info)
732 memset(info, 0, sizeof(*info));
734 info->rdma_type = QED_RDMA_TYPE_ROCE;
736 qed_fill_dev_info(cdev, &info->common);
741 static int qed_rdma_get_sb_start(struct qed_dev *cdev)
745 if (cdev->num_hwfns > 1)
746 feat_num = FEAT_NUM(QED_LEADING_HWFN(cdev), QED_PF_L2_QUE);
748 feat_num = FEAT_NUM(QED_LEADING_HWFN(cdev), QED_PF_L2_QUE) *
754 static int qed_rdma_get_min_cnq_msix(struct qed_dev *cdev)
756 int n_cnq = FEAT_NUM(QED_LEADING_HWFN(cdev), QED_RDMA_CNQ);
757 int n_msix = cdev->int_params.rdma_msix_cnt;
759 return min_t(int, n_cnq, n_msix);
762 static int qed_rdma_set_int(struct qed_dev *cdev, u16 cnt)
766 /* Mark the fastpath as free/used */
767 cdev->int_params.fp_initialized = cnt ? true : false;
769 if (cdev->int_params.out.int_mode != QED_INT_MODE_MSIX) {
771 "qed roce supports only MSI-X interrupts (detected %d).\n",
772 cdev->int_params.out.int_mode);
774 } else if (cdev->int_params.fp_msix_cnt) {
775 limit = cdev->int_params.rdma_msix_cnt;
781 return min_t(int, cnt, limit);
784 static int qed_rdma_get_int(struct qed_dev *cdev, struct qed_int_info *info)
786 memset(info, 0, sizeof(*info));
788 if (!cdev->int_params.fp_initialized) {
790 "Protocol driver requested interrupt information, but its support is not yet configured\n");
794 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
795 int msix_base = cdev->int_params.rdma_msix_base;
797 info->msix_cnt = cdev->int_params.rdma_msix_cnt;
798 info->msix = &cdev->int_params.msix_table[msix_base];
800 DP_VERBOSE(cdev, QED_MSG_RDMA, "msix_cnt = %d msix_base=%d\n",
801 info->msix_cnt, msix_base);
807 int qed_rdma_alloc_pd(void *rdma_cxt, u16 *pd)
809 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
813 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Alloc PD\n");
815 /* Allocates an unused protection domain */
816 spin_lock_bh(&p_hwfn->p_rdma_info->lock);
817 rc = qed_rdma_bmap_alloc_id(p_hwfn,
818 &p_hwfn->p_rdma_info->pd_map, &returned_id);
819 spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
821 *pd = (u16)returned_id;
823 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Alloc PD - done, rc = %d\n", rc);
827 void qed_rdma_free_pd(void *rdma_cxt, u16 pd)
829 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
831 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "pd = %08x\n", pd);
833 /* Returns a previously allocated protection domain for reuse */
834 spin_lock_bh(&p_hwfn->p_rdma_info->lock);
835 qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->pd_map, pd);
836 spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
839 static enum qed_rdma_toggle_bit
840 qed_rdma_toggle_bit_create_resize_cq(struct qed_hwfn *p_hwfn, u16 icid)
842 struct qed_rdma_info *p_info = p_hwfn->p_rdma_info;
843 enum qed_rdma_toggle_bit toggle_bit;
846 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", icid);
848 /* the function toggle the bit that is related to a given icid
849 * and returns the new toggle bit's value
851 bmap_id = icid - qed_cxt_get_proto_cid_start(p_hwfn, p_info->proto);
853 spin_lock_bh(&p_info->lock);
854 toggle_bit = !test_and_change_bit(bmap_id,
855 p_info->toggle_bits.bitmap);
856 spin_unlock_bh(&p_info->lock);
858 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "QED_RDMA_TOGGLE_BIT_= %d\n",
864 int qed_rdma_create_cq(void *rdma_cxt,
865 struct qed_rdma_create_cq_in_params *params, u16 *icid)
867 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
868 struct qed_rdma_info *p_info = p_hwfn->p_rdma_info;
869 struct rdma_create_cq_ramrod_data *p_ramrod;
870 enum qed_rdma_toggle_bit toggle_bit;
871 struct qed_sp_init_data init_data;
872 struct qed_spq_entry *p_ent;
873 u32 returned_id, start_cid;
876 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "cq_handle = %08x%08x\n",
877 params->cq_handle_hi, params->cq_handle_lo);
880 spin_lock_bh(&p_info->lock);
881 rc = qed_rdma_bmap_alloc_id(p_hwfn,
882 &p_info->cq_map, &returned_id);
883 spin_unlock_bh(&p_info->lock);
886 DP_NOTICE(p_hwfn, "Can't create CQ, rc = %d\n", rc);
890 start_cid = qed_cxt_get_proto_cid_start(p_hwfn,
892 *icid = returned_id + start_cid;
894 /* Check if icid requires a page allocation */
895 rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_CXT, *icid);
900 memset(&init_data, 0, sizeof(init_data));
901 init_data.cid = *icid;
902 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
903 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
905 /* Send create CQ ramrod */
906 rc = qed_sp_init_request(p_hwfn, &p_ent,
907 RDMA_RAMROD_CREATE_CQ,
908 p_info->proto, &init_data);
912 p_ramrod = &p_ent->ramrod.rdma_create_cq;
914 p_ramrod->cq_handle.hi = cpu_to_le32(params->cq_handle_hi);
915 p_ramrod->cq_handle.lo = cpu_to_le32(params->cq_handle_lo);
916 p_ramrod->dpi = cpu_to_le16(params->dpi);
917 p_ramrod->is_two_level_pbl = params->pbl_two_level;
918 p_ramrod->max_cqes = cpu_to_le32(params->cq_size);
919 DMA_REGPAIR_LE(p_ramrod->pbl_addr, params->pbl_ptr);
920 p_ramrod->pbl_num_pages = cpu_to_le16(params->pbl_num_pages);
921 p_ramrod->cnq_id = (u8)RESC_START(p_hwfn, QED_RDMA_CNQ_RAM) +
923 p_ramrod->int_timeout = params->int_timeout;
925 /* toggle the bit for every resize or create cq for a given icid */
926 toggle_bit = qed_rdma_toggle_bit_create_resize_cq(p_hwfn, *icid);
928 p_ramrod->toggle_bit = toggle_bit;
930 rc = qed_spq_post(p_hwfn, p_ent, NULL);
932 /* restore toggle bit */
933 qed_rdma_toggle_bit_create_resize_cq(p_hwfn, *icid);
937 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Created CQ, rc = %d\n", rc);
941 /* release allocated icid */
942 qed_bmap_release_id(p_hwfn, &p_info->cq_map, returned_id);
943 DP_NOTICE(p_hwfn, "Create CQ failed, rc = %d\n", rc);
948 int qed_rdma_resize_cq(void *rdma_cxt,
949 struct qed_rdma_resize_cq_in_params *in_params,
950 struct qed_rdma_resize_cq_out_params *out_params)
952 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
953 struct rdma_resize_cq_output_params *p_ramrod_res;
954 struct rdma_resize_cq_ramrod_data *p_ramrod;
955 enum qed_rdma_toggle_bit toggle_bit;
956 struct qed_sp_init_data init_data;
957 struct qed_spq_entry *p_ent;
958 dma_addr_t ramrod_res_phys;
962 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", in_params->icid);
965 (struct rdma_resize_cq_output_params *)
966 dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
967 sizeof(struct rdma_resize_cq_output_params),
968 &ramrod_res_phys, GFP_KERNEL);
971 "qed resize cq failed: cannot allocate memory (ramrod)\n");
976 memset(&init_data, 0, sizeof(init_data));
977 init_data.cid = in_params->icid;
978 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
979 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
981 rc = qed_sp_init_request(p_hwfn, &p_ent,
982 RDMA_RAMROD_RESIZE_CQ,
983 p_hwfn->p_rdma_info->proto, &init_data);
987 p_ramrod = &p_ent->ramrod.rdma_resize_cq;
991 /* toggle the bit for every resize or create cq for a given icid */
992 toggle_bit = qed_rdma_toggle_bit_create_resize_cq(p_hwfn,
995 SET_FIELD(p_ramrod->flags,
996 RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT, toggle_bit);
998 SET_FIELD(p_ramrod->flags,
999 RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL,
1000 in_params->pbl_two_level);
1002 p_ramrod->pbl_log_page_size = in_params->pbl_page_size_log - 12;
1003 p_ramrod->pbl_num_pages = cpu_to_le16(in_params->pbl_num_pages);
1004 p_ramrod->max_cqes = cpu_to_le32(in_params->cq_size);
1005 DMA_REGPAIR_LE(p_ramrod->pbl_addr, in_params->pbl_ptr);
1006 DMA_REGPAIR_LE(p_ramrod->output_params_addr, ramrod_res_phys);
1008 rc = qed_spq_post(p_hwfn, p_ent, &fw_return_code);
1012 if (fw_return_code != RDMA_RETURN_OK) {
1013 DP_NOTICE(p_hwfn, "fw_return_code = %d\n", fw_return_code);
1018 out_params->prod = le32_to_cpu(p_ramrod_res->old_cq_prod);
1019 out_params->cons = le32_to_cpu(p_ramrod_res->old_cq_cons);
1021 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
1022 sizeof(struct rdma_resize_cq_output_params),
1023 p_ramrod_res, ramrod_res_phys);
1025 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Resized CQ, rc = %d\n", rc);
1029 err: dma_free_coherent(&p_hwfn->cdev->pdev->dev,
1030 sizeof(struct rdma_resize_cq_output_params),
1031 p_ramrod_res, ramrod_res_phys);
1032 DP_NOTICE(p_hwfn, "Resized CQ, Failed - rc = %d\n", rc);
1037 int qed_rdma_destroy_cq(void *rdma_cxt,
1038 struct qed_rdma_destroy_cq_in_params *in_params,
1039 struct qed_rdma_destroy_cq_out_params *out_params)
1041 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
1042 struct rdma_destroy_cq_output_params *p_ramrod_res;
1043 struct rdma_destroy_cq_ramrod_data *p_ramrod;
1044 struct qed_sp_init_data init_data;
1045 struct qed_spq_entry *p_ent;
1046 dma_addr_t ramrod_res_phys;
1049 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", in_params->icid);
1052 (struct rdma_destroy_cq_output_params *)
1053 dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
1054 sizeof(struct rdma_destroy_cq_output_params),
1055 &ramrod_res_phys, GFP_KERNEL);
1056 if (!p_ramrod_res) {
1058 "qed destroy cq failed: cannot allocate memory (ramrod)\n");
1063 memset(&init_data, 0, sizeof(init_data));
1064 init_data.cid = in_params->icid;
1065 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1066 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1068 /* Send destroy CQ ramrod */
1069 rc = qed_sp_init_request(p_hwfn, &p_ent,
1070 RDMA_RAMROD_DESTROY_CQ,
1071 p_hwfn->p_rdma_info->proto, &init_data);
1075 p_ramrod = &p_ent->ramrod.rdma_destroy_cq;
1076 DMA_REGPAIR_LE(p_ramrod->output_params_addr, ramrod_res_phys);
1078 rc = qed_spq_post(p_hwfn, p_ent, NULL);
1082 out_params->num_cq_notif = le16_to_cpu(p_ramrod_res->cnq_num);
1084 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
1085 sizeof(struct rdma_destroy_cq_output_params),
1086 p_ramrod_res, ramrod_res_phys);
1089 spin_lock_bh(&p_hwfn->p_rdma_info->lock);
1091 qed_bmap_release_id(p_hwfn,
1092 &p_hwfn->p_rdma_info->cq_map,
1094 qed_cxt_get_proto_cid_start(p_hwfn,
1096 p_rdma_info->proto)));
1098 spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
1100 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Destroyed CQ, rc = %d\n", rc);
1103 err: dma_free_coherent(&p_hwfn->cdev->pdev->dev,
1104 sizeof(struct rdma_destroy_cq_output_params),
1105 p_ramrod_res, ramrod_res_phys);
1110 static void qed_rdma_set_fw_mac(u16 *p_fw_mac, u8 *p_qed_mac)
1112 p_fw_mac[0] = cpu_to_le16((p_qed_mac[0] << 8) + p_qed_mac[1]);
1113 p_fw_mac[1] = cpu_to_le16((p_qed_mac[2] << 8) + p_qed_mac[3]);
1114 p_fw_mac[2] = cpu_to_le16((p_qed_mac[4] << 8) + p_qed_mac[5]);
1117 static void qed_rdma_copy_gids(struct qed_rdma_qp *qp, __le32 *src_gid,
1122 if (qp->roce_mode == ROCE_V2_IPV4) {
1123 /* The IPv4 addresses shall be aligned to the highest word.
1124 * The lower words must be zero.
1126 memset(src_gid, 0, sizeof(union qed_gid));
1127 memset(dst_gid, 0, sizeof(union qed_gid));
1128 src_gid[3] = cpu_to_le32(qp->sgid.ipv4_addr);
1129 dst_gid[3] = cpu_to_le32(qp->dgid.ipv4_addr);
1131 /* GIDs and IPv6 addresses coincide in location and size */
1132 for (i = 0; i < ARRAY_SIZE(qp->sgid.dwords); i++) {
1133 src_gid[i] = cpu_to_le32(qp->sgid.dwords[i]);
1134 dst_gid[i] = cpu_to_le32(qp->dgid.dwords[i]);
1139 static enum roce_flavor qed_roce_mode_to_flavor(enum roce_mode roce_mode)
1141 enum roce_flavor flavor;
1143 switch (roce_mode) {
1145 flavor = PLAIN_ROCE;
1148 flavor = RROCE_IPV4;
1151 flavor = ROCE_V2_IPV6;
1154 flavor = MAX_ROCE_MODE;
1160 int qed_roce_alloc_cid(struct qed_hwfn *p_hwfn, u16 *cid)
1162 struct qed_rdma_info *p_rdma_info = p_hwfn->p_rdma_info;
1167 spin_lock_bh(&p_hwfn->p_rdma_info->lock);
1168 rc = qed_rdma_bmap_alloc_id(p_hwfn, &p_rdma_info->cid_map,
1171 spin_unlock_bh(&p_rdma_info->lock);
1175 rc = qed_rdma_bmap_alloc_id(p_hwfn, &p_rdma_info->cid_map,
1178 spin_unlock_bh(&p_rdma_info->lock);
1182 /* the two icid's should be adjacent */
1183 if ((requester_icid - responder_icid) != 1) {
1184 DP_NOTICE(p_hwfn, "Failed to allocate two adjacent qp's'\n");
1189 responder_icid += qed_cxt_get_proto_cid_start(p_hwfn,
1190 p_rdma_info->proto);
1191 requester_icid += qed_cxt_get_proto_cid_start(p_hwfn,
1192 p_rdma_info->proto);
1194 /* If these icids require a new ILT line allocate DMA-able context for
1197 rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_CXT, responder_icid);
1201 rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_CXT, requester_icid);
1205 *cid = (u16)responder_icid;
1209 spin_lock_bh(&p_rdma_info->lock);
1210 qed_bmap_release_id(p_hwfn, &p_rdma_info->cid_map, responder_icid);
1211 qed_bmap_release_id(p_hwfn, &p_rdma_info->cid_map, requester_icid);
1213 spin_unlock_bh(&p_rdma_info->lock);
1214 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
1215 "Allocate CID - failed, rc = %d\n", rc);
1219 static int qed_roce_sp_create_responder(struct qed_hwfn *p_hwfn,
1220 struct qed_rdma_qp *qp)
1222 struct roce_create_qp_resp_ramrod_data *p_ramrod;
1223 struct qed_sp_init_data init_data;
1224 union qed_qm_pq_params qm_params;
1225 enum roce_flavor roce_flavor;
1226 struct qed_spq_entry *p_ent;
1227 u16 physical_queue0 = 0;
1230 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid);
1232 /* Allocate DMA-able memory for IRQ */
1233 qp->irq_num_pages = 1;
1234 qp->irq = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
1235 RDMA_RING_PAGE_SIZE,
1236 &qp->irq_phys_addr, GFP_KERNEL);
1240 "qed create responder failed: cannot allocate memory (irq). rc = %d\n",
1246 memset(&init_data, 0, sizeof(init_data));
1247 init_data.cid = qp->icid;
1248 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1249 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1251 rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_CREATE_QP,
1252 PROTOCOLID_ROCE, &init_data);
1256 p_ramrod = &p_ent->ramrod.roce_create_qp_resp;
1258 p_ramrod->flags = 0;
1260 roce_flavor = qed_roce_mode_to_flavor(qp->roce_mode);
1261 SET_FIELD(p_ramrod->flags,
1262 ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR, roce_flavor);
1264 SET_FIELD(p_ramrod->flags,
1265 ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN,
1266 qp->incoming_rdma_read_en);
1268 SET_FIELD(p_ramrod->flags,
1269 ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN,
1270 qp->incoming_rdma_write_en);
1272 SET_FIELD(p_ramrod->flags,
1273 ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN,
1274 qp->incoming_atomic_en);
1276 SET_FIELD(p_ramrod->flags,
1277 ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN,
1278 qp->e2e_flow_control_en);
1280 SET_FIELD(p_ramrod->flags,
1281 ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG, qp->use_srq);
1283 SET_FIELD(p_ramrod->flags,
1284 ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN,
1285 qp->fmr_and_reserved_lkey);
1287 SET_FIELD(p_ramrod->flags,
1288 ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER,
1289 qp->min_rnr_nak_timer);
1291 p_ramrod->max_ird = qp->max_rd_atomic_resp;
1292 p_ramrod->traffic_class = qp->traffic_class_tos;
1293 p_ramrod->hop_limit = qp->hop_limit_ttl;
1294 p_ramrod->irq_num_pages = qp->irq_num_pages;
1295 p_ramrod->p_key = cpu_to_le16(qp->pkey);
1296 p_ramrod->flow_label = cpu_to_le32(qp->flow_label);
1297 p_ramrod->dst_qp_id = cpu_to_le32(qp->dest_qp);
1298 p_ramrod->mtu = cpu_to_le16(qp->mtu);
1299 p_ramrod->initial_psn = cpu_to_le32(qp->rq_psn);
1300 p_ramrod->pd = cpu_to_le16(qp->pd);
1301 p_ramrod->rq_num_pages = cpu_to_le16(qp->rq_num_pages);
1302 DMA_REGPAIR_LE(p_ramrod->rq_pbl_addr, qp->rq_pbl_ptr);
1303 DMA_REGPAIR_LE(p_ramrod->irq_pbl_addr, qp->irq_phys_addr);
1304 qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid);
1305 p_ramrod->qp_handle_for_async.hi = cpu_to_le32(qp->qp_handle_async.hi);
1306 p_ramrod->qp_handle_for_async.lo = cpu_to_le32(qp->qp_handle_async.lo);
1307 p_ramrod->qp_handle_for_cqe.hi = cpu_to_le32(qp->qp_handle.hi);
1308 p_ramrod->qp_handle_for_cqe.lo = cpu_to_le32(qp->qp_handle.lo);
1309 p_ramrod->stats_counter_id = p_hwfn->rel_pf_id;
1310 p_ramrod->cq_cid = cpu_to_le32((p_hwfn->hw_info.opaque_fid << 16) |
1313 memset(&qm_params, 0, sizeof(qm_params));
1314 qm_params.roce.qpid = qp->icid >> 1;
1315 physical_queue0 = qed_get_qm_pq(p_hwfn, PROTOCOLID_ROCE, &qm_params);
1317 p_ramrod->physical_queue0 = cpu_to_le16(physical_queue0);
1318 p_ramrod->dpi = cpu_to_le16(qp->dpi);
1320 qed_rdma_set_fw_mac(p_ramrod->remote_mac_addr, qp->remote_mac_addr);
1321 qed_rdma_set_fw_mac(p_ramrod->local_mac_addr, qp->local_mac_addr);
1323 p_ramrod->udp_src_port = qp->udp_src_port;
1324 p_ramrod->vlan_id = cpu_to_le16(qp->vlan_id);
1325 p_ramrod->srq_id.srq_idx = cpu_to_le16(qp->srq_id);
1326 p_ramrod->srq_id.opaque_fid = cpu_to_le16(p_hwfn->hw_info.opaque_fid);
1328 p_ramrod->stats_counter_id = RESC_START(p_hwfn, QED_RDMA_STATS_QUEUE) +
1331 rc = qed_spq_post(p_hwfn, p_ent, NULL);
1333 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d physical_queue0 = 0x%x\n",
1334 rc, physical_queue0);
1339 qp->resp_offloaded = true;
1344 DP_NOTICE(p_hwfn, "create responder - failed, rc = %d\n", rc);
1345 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
1346 qp->irq_num_pages * RDMA_RING_PAGE_SIZE,
1347 qp->irq, qp->irq_phys_addr);
1352 static int qed_roce_sp_create_requester(struct qed_hwfn *p_hwfn,
1353 struct qed_rdma_qp *qp)
1355 struct roce_create_qp_req_ramrod_data *p_ramrod;
1356 struct qed_sp_init_data init_data;
1357 union qed_qm_pq_params qm_params;
1358 enum roce_flavor roce_flavor;
1359 struct qed_spq_entry *p_ent;
1360 u16 physical_queue0 = 0;
1363 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid);
1365 /* Allocate DMA-able memory for ORQ */
1366 qp->orq_num_pages = 1;
1367 qp->orq = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
1368 RDMA_RING_PAGE_SIZE,
1369 &qp->orq_phys_addr, GFP_KERNEL);
1373 "qed create requester failed: cannot allocate memory (orq). rc = %d\n",
1379 memset(&init_data, 0, sizeof(init_data));
1380 init_data.cid = qp->icid + 1;
1381 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1382 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1384 rc = qed_sp_init_request(p_hwfn, &p_ent,
1385 ROCE_RAMROD_CREATE_QP,
1386 PROTOCOLID_ROCE, &init_data);
1390 p_ramrod = &p_ent->ramrod.roce_create_qp_req;
1392 p_ramrod->flags = 0;
1394 roce_flavor = qed_roce_mode_to_flavor(qp->roce_mode);
1395 SET_FIELD(p_ramrod->flags,
1396 ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR, roce_flavor);
1398 SET_FIELD(p_ramrod->flags,
1399 ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN,
1400 qp->fmr_and_reserved_lkey);
1402 SET_FIELD(p_ramrod->flags,
1403 ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP, qp->signal_all);
1405 SET_FIELD(p_ramrod->flags,
1406 ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT, qp->retry_cnt);
1408 SET_FIELD(p_ramrod->flags,
1409 ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT,
1412 p_ramrod->max_ord = qp->max_rd_atomic_req;
1413 p_ramrod->traffic_class = qp->traffic_class_tos;
1414 p_ramrod->hop_limit = qp->hop_limit_ttl;
1415 p_ramrod->orq_num_pages = qp->orq_num_pages;
1416 p_ramrod->p_key = cpu_to_le16(qp->pkey);
1417 p_ramrod->flow_label = cpu_to_le32(qp->flow_label);
1418 p_ramrod->dst_qp_id = cpu_to_le32(qp->dest_qp);
1419 p_ramrod->ack_timeout_val = cpu_to_le32(qp->ack_timeout);
1420 p_ramrod->mtu = cpu_to_le16(qp->mtu);
1421 p_ramrod->initial_psn = cpu_to_le32(qp->sq_psn);
1422 p_ramrod->pd = cpu_to_le16(qp->pd);
1423 p_ramrod->sq_num_pages = cpu_to_le16(qp->sq_num_pages);
1424 DMA_REGPAIR_LE(p_ramrod->sq_pbl_addr, qp->sq_pbl_ptr);
1425 DMA_REGPAIR_LE(p_ramrod->orq_pbl_addr, qp->orq_phys_addr);
1426 qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid);
1427 p_ramrod->qp_handle_for_async.hi = cpu_to_le32(qp->qp_handle_async.hi);
1428 p_ramrod->qp_handle_for_async.lo = cpu_to_le32(qp->qp_handle_async.lo);
1429 p_ramrod->qp_handle_for_cqe.hi = cpu_to_le32(qp->qp_handle.hi);
1430 p_ramrod->qp_handle_for_cqe.lo = cpu_to_le32(qp->qp_handle.lo);
1431 p_ramrod->stats_counter_id = p_hwfn->rel_pf_id;
1432 p_ramrod->cq_cid = cpu_to_le32((p_hwfn->hw_info.opaque_fid << 16) |
1435 memset(&qm_params, 0, sizeof(qm_params));
1436 qm_params.roce.qpid = qp->icid >> 1;
1437 physical_queue0 = qed_get_qm_pq(p_hwfn, PROTOCOLID_ROCE, &qm_params);
1439 p_ramrod->physical_queue0 = cpu_to_le16(physical_queue0);
1440 p_ramrod->dpi = cpu_to_le16(qp->dpi);
1442 qed_rdma_set_fw_mac(p_ramrod->remote_mac_addr, qp->remote_mac_addr);
1443 qed_rdma_set_fw_mac(p_ramrod->local_mac_addr, qp->local_mac_addr);
1445 p_ramrod->udp_src_port = qp->udp_src_port;
1446 p_ramrod->vlan_id = cpu_to_le16(qp->vlan_id);
1447 p_ramrod->stats_counter_id = RESC_START(p_hwfn, QED_RDMA_STATS_QUEUE) +
1450 rc = qed_spq_post(p_hwfn, p_ent, NULL);
1452 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc);
1457 qp->req_offloaded = true;
1462 DP_NOTICE(p_hwfn, "Create requested - failed, rc = %d\n", rc);
1463 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
1464 qp->orq_num_pages * RDMA_RING_PAGE_SIZE,
1465 qp->orq, qp->orq_phys_addr);
1469 static int qed_roce_sp_modify_responder(struct qed_hwfn *p_hwfn,
1470 struct qed_rdma_qp *qp,
1471 bool move_to_err, u32 modify_flags)
1473 struct roce_modify_qp_resp_ramrod_data *p_ramrod;
1474 struct qed_sp_init_data init_data;
1475 struct qed_spq_entry *p_ent;
1478 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid);
1480 if (move_to_err && !qp->resp_offloaded)
1484 memset(&init_data, 0, sizeof(init_data));
1485 init_data.cid = qp->icid;
1486 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1487 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1489 rc = qed_sp_init_request(p_hwfn, &p_ent,
1490 ROCE_EVENT_MODIFY_QP,
1491 PROTOCOLID_ROCE, &init_data);
1493 DP_NOTICE(p_hwfn, "rc = %d\n", rc);
1497 p_ramrod = &p_ent->ramrod.roce_modify_qp_resp;
1499 p_ramrod->flags = 0;
1501 SET_FIELD(p_ramrod->flags,
1502 ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG, move_to_err);
1504 SET_FIELD(p_ramrod->flags,
1505 ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN,
1506 qp->incoming_rdma_read_en);
1508 SET_FIELD(p_ramrod->flags,
1509 ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN,
1510 qp->incoming_rdma_write_en);
1512 SET_FIELD(p_ramrod->flags,
1513 ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN,
1514 qp->incoming_atomic_en);
1516 SET_FIELD(p_ramrod->flags,
1517 ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN,
1518 qp->e2e_flow_control_en);
1520 SET_FIELD(p_ramrod->flags,
1521 ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG,
1522 GET_FIELD(modify_flags,
1523 QED_RDMA_MODIFY_QP_VALID_RDMA_OPS_EN));
1525 SET_FIELD(p_ramrod->flags,
1526 ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG,
1527 GET_FIELD(modify_flags, QED_ROCE_MODIFY_QP_VALID_PKEY));
1529 SET_FIELD(p_ramrod->flags,
1530 ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG,
1531 GET_FIELD(modify_flags,
1532 QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR));
1534 SET_FIELD(p_ramrod->flags,
1535 ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG,
1536 GET_FIELD(modify_flags,
1537 QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_RESP));
1539 SET_FIELD(p_ramrod->flags,
1540 ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG,
1541 GET_FIELD(modify_flags,
1542 QED_ROCE_MODIFY_QP_VALID_MIN_RNR_NAK_TIMER));
1544 p_ramrod->fields = 0;
1545 SET_FIELD(p_ramrod->fields,
1546 ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER,
1547 qp->min_rnr_nak_timer);
1549 p_ramrod->max_ird = qp->max_rd_atomic_resp;
1550 p_ramrod->traffic_class = qp->traffic_class_tos;
1551 p_ramrod->hop_limit = qp->hop_limit_ttl;
1552 p_ramrod->p_key = cpu_to_le16(qp->pkey);
1553 p_ramrod->flow_label = cpu_to_le32(qp->flow_label);
1554 p_ramrod->mtu = cpu_to_le16(qp->mtu);
1555 qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid);
1556 rc = qed_spq_post(p_hwfn, p_ent, NULL);
1558 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Modify responder, rc = %d\n", rc);
1562 static int qed_roce_sp_modify_requester(struct qed_hwfn *p_hwfn,
1563 struct qed_rdma_qp *qp,
1565 bool move_to_err, u32 modify_flags)
1567 struct roce_modify_qp_req_ramrod_data *p_ramrod;
1568 struct qed_sp_init_data init_data;
1569 struct qed_spq_entry *p_ent;
1572 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid);
1574 if (move_to_err && !(qp->req_offloaded))
1578 memset(&init_data, 0, sizeof(init_data));
1579 init_data.cid = qp->icid + 1;
1580 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1581 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1583 rc = qed_sp_init_request(p_hwfn, &p_ent,
1584 ROCE_EVENT_MODIFY_QP,
1585 PROTOCOLID_ROCE, &init_data);
1587 DP_NOTICE(p_hwfn, "rc = %d\n", rc);
1591 p_ramrod = &p_ent->ramrod.roce_modify_qp_req;
1593 p_ramrod->flags = 0;
1595 SET_FIELD(p_ramrod->flags,
1596 ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG, move_to_err);
1598 SET_FIELD(p_ramrod->flags,
1599 ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG, move_to_sqd);
1601 SET_FIELD(p_ramrod->flags,
1602 ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY,
1605 SET_FIELD(p_ramrod->flags,
1606 ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG,
1607 GET_FIELD(modify_flags, QED_ROCE_MODIFY_QP_VALID_PKEY));
1609 SET_FIELD(p_ramrod->flags,
1610 ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG,
1611 GET_FIELD(modify_flags,
1612 QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR));
1614 SET_FIELD(p_ramrod->flags,
1615 ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG,
1616 GET_FIELD(modify_flags,
1617 QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_REQ));
1619 SET_FIELD(p_ramrod->flags,
1620 ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG,
1621 GET_FIELD(modify_flags,
1622 QED_ROCE_MODIFY_QP_VALID_RNR_RETRY_CNT));
1624 SET_FIELD(p_ramrod->flags,
1625 ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG,
1626 GET_FIELD(modify_flags, QED_ROCE_MODIFY_QP_VALID_RETRY_CNT));
1628 SET_FIELD(p_ramrod->flags,
1629 ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG,
1630 GET_FIELD(modify_flags,
1631 QED_ROCE_MODIFY_QP_VALID_ACK_TIMEOUT));
1633 p_ramrod->fields = 0;
1634 SET_FIELD(p_ramrod->fields,
1635 ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT, qp->retry_cnt);
1637 SET_FIELD(p_ramrod->fields,
1638 ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT,
1641 p_ramrod->max_ord = qp->max_rd_atomic_req;
1642 p_ramrod->traffic_class = qp->traffic_class_tos;
1643 p_ramrod->hop_limit = qp->hop_limit_ttl;
1644 p_ramrod->p_key = cpu_to_le16(qp->pkey);
1645 p_ramrod->flow_label = cpu_to_le32(qp->flow_label);
1646 p_ramrod->ack_timeout_val = cpu_to_le32(qp->ack_timeout);
1647 p_ramrod->mtu = cpu_to_le16(qp->mtu);
1648 qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid);
1649 rc = qed_spq_post(p_hwfn, p_ent, NULL);
1651 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Modify requester, rc = %d\n", rc);
1655 static int qed_roce_sp_destroy_qp_responder(struct qed_hwfn *p_hwfn,
1656 struct qed_rdma_qp *qp,
1657 u32 *num_invalidated_mw)
1659 struct roce_destroy_qp_resp_output_params *p_ramrod_res;
1660 struct roce_destroy_qp_resp_ramrod_data *p_ramrod;
1661 struct qed_sp_init_data init_data;
1662 struct qed_spq_entry *p_ent;
1663 dma_addr_t ramrod_res_phys;
1666 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid);
1668 if (!qp->resp_offloaded)
1672 memset(&init_data, 0, sizeof(init_data));
1673 init_data.cid = qp->icid;
1674 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1675 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1677 rc = qed_sp_init_request(p_hwfn, &p_ent,
1678 ROCE_RAMROD_DESTROY_QP,
1679 PROTOCOLID_ROCE, &init_data);
1683 p_ramrod = &p_ent->ramrod.roce_destroy_qp_resp;
1685 p_ramrod_res = (struct roce_destroy_qp_resp_output_params *)
1686 dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_ramrod_res),
1687 &ramrod_res_phys, GFP_KERNEL);
1689 if (!p_ramrod_res) {
1692 "qed destroy responder failed: cannot allocate memory (ramrod). rc = %d\n",
1697 DMA_REGPAIR_LE(p_ramrod->output_params_addr, ramrod_res_phys);
1699 rc = qed_spq_post(p_hwfn, p_ent, NULL);
1703 *num_invalidated_mw = le32_to_cpu(p_ramrod_res->num_invalidated_mw);
1705 /* Free IRQ - only if ramrod succeeded, in case FW is still using it */
1706 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
1707 qp->irq_num_pages * RDMA_RING_PAGE_SIZE,
1708 qp->irq, qp->irq_phys_addr);
1710 qp->resp_offloaded = false;
1712 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Destroy responder, rc = %d\n", rc);
1715 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
1716 sizeof(struct roce_destroy_qp_resp_output_params),
1717 p_ramrod_res, ramrod_res_phys);
1722 static int qed_roce_sp_destroy_qp_requester(struct qed_hwfn *p_hwfn,
1723 struct qed_rdma_qp *qp,
1726 struct roce_destroy_qp_req_output_params *p_ramrod_res;
1727 struct roce_destroy_qp_req_ramrod_data *p_ramrod;
1728 struct qed_sp_init_data init_data;
1729 struct qed_spq_entry *p_ent;
1730 dma_addr_t ramrod_res_phys;
1733 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid);
1735 if (!qp->req_offloaded)
1738 p_ramrod_res = (struct roce_destroy_qp_req_output_params *)
1739 dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
1740 sizeof(*p_ramrod_res),
1741 &ramrod_res_phys, GFP_KERNEL);
1742 if (!p_ramrod_res) {
1744 "qed destroy requester failed: cannot allocate memory (ramrod)\n");
1749 memset(&init_data, 0, sizeof(init_data));
1750 init_data.cid = qp->icid + 1;
1751 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1752 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1754 rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_DESTROY_QP,
1755 PROTOCOLID_ROCE, &init_data);
1759 p_ramrod = &p_ent->ramrod.roce_destroy_qp_req;
1760 DMA_REGPAIR_LE(p_ramrod->output_params_addr, ramrod_res_phys);
1762 rc = qed_spq_post(p_hwfn, p_ent, NULL);
1766 *num_bound_mw = le32_to_cpu(p_ramrod_res->num_bound_mw);
1768 /* Free ORQ - only if ramrod succeeded, in case FW is still using it */
1769 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
1770 qp->orq_num_pages * RDMA_RING_PAGE_SIZE,
1771 qp->orq, qp->orq_phys_addr);
1773 qp->req_offloaded = false;
1775 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Destroy requester, rc = %d\n", rc);
1778 dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_ramrod_res),
1779 p_ramrod_res, ramrod_res_phys);
1784 int qed_roce_query_qp(struct qed_hwfn *p_hwfn,
1785 struct qed_rdma_qp *qp,
1786 struct qed_rdma_query_qp_out_params *out_params)
1788 struct roce_query_qp_resp_output_params *p_resp_ramrod_res;
1789 struct roce_query_qp_req_output_params *p_req_ramrod_res;
1790 struct roce_query_qp_resp_ramrod_data *p_resp_ramrod;
1791 struct roce_query_qp_req_ramrod_data *p_req_ramrod;
1792 struct qed_sp_init_data init_data;
1793 dma_addr_t resp_ramrod_res_phys;
1794 dma_addr_t req_ramrod_res_phys;
1795 struct qed_spq_entry *p_ent;
1801 if ((!(qp->resp_offloaded)) && (!(qp->req_offloaded))) {
1802 /* We can't send ramrod to the fw since this qp wasn't offloaded
1805 out_params->draining = false;
1806 out_params->rq_psn = qp->rq_psn;
1807 out_params->sq_psn = qp->sq_psn;
1808 out_params->state = qp->cur_state;
1810 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "No QPs as no offload\n");
1814 if (!(qp->resp_offloaded)) {
1816 "The responder's qp should be offloded before requester's\n");
1820 /* Send a query responder ramrod to FW to get RQ-PSN and state */
1821 p_resp_ramrod_res = (struct roce_query_qp_resp_output_params *)
1822 dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
1823 sizeof(*p_resp_ramrod_res),
1824 &resp_ramrod_res_phys, GFP_KERNEL);
1825 if (!p_resp_ramrod_res) {
1827 "qed query qp failed: cannot allocate memory (ramrod)\n");
1832 memset(&init_data, 0, sizeof(init_data));
1833 init_data.cid = qp->icid;
1834 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1835 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1836 rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_QUERY_QP,
1837 PROTOCOLID_ROCE, &init_data);
1841 p_resp_ramrod = &p_ent->ramrod.roce_query_qp_resp;
1842 DMA_REGPAIR_LE(p_resp_ramrod->output_params_addr, resp_ramrod_res_phys);
1844 rc = qed_spq_post(p_hwfn, p_ent, NULL);
1848 dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_resp_ramrod_res),
1849 p_resp_ramrod_res, resp_ramrod_res_phys);
1851 out_params->rq_psn = le32_to_cpu(p_resp_ramrod_res->psn);
1852 rq_err_state = GET_FIELD(le32_to_cpu(p_resp_ramrod_res->err_flag),
1853 ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG);
1855 if (!(qp->req_offloaded)) {
1856 /* Don't send query qp for the requester */
1857 out_params->sq_psn = qp->sq_psn;
1858 out_params->draining = false;
1861 qp->cur_state = QED_ROCE_QP_STATE_ERR;
1863 out_params->state = qp->cur_state;
1868 /* Send a query requester ramrod to FW to get SQ-PSN and state */
1869 p_req_ramrod_res = (struct roce_query_qp_req_output_params *)
1870 dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
1871 sizeof(*p_req_ramrod_res),
1872 &req_ramrod_res_phys,
1874 if (!p_req_ramrod_res) {
1877 "qed query qp failed: cannot allocate memory (ramrod)\n");
1882 init_data.cid = qp->icid + 1;
1883 rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_QUERY_QP,
1884 PROTOCOLID_ROCE, &init_data);
1888 p_req_ramrod = &p_ent->ramrod.roce_query_qp_req;
1889 DMA_REGPAIR_LE(p_req_ramrod->output_params_addr, req_ramrod_res_phys);
1891 rc = qed_spq_post(p_hwfn, p_ent, NULL);
1895 dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_req_ramrod_res),
1896 p_req_ramrod_res, req_ramrod_res_phys);
1898 out_params->sq_psn = le32_to_cpu(p_req_ramrod_res->psn);
1899 sq_err_state = GET_FIELD(le32_to_cpu(p_req_ramrod_res->flags),
1900 ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG);
1902 GET_FIELD(le32_to_cpu(p_req_ramrod_res->flags),
1903 ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG);
1905 out_params->draining = false;
1908 qp->cur_state = QED_ROCE_QP_STATE_ERR;
1909 else if (sq_err_state)
1910 qp->cur_state = QED_ROCE_QP_STATE_SQE;
1911 else if (sq_draining)
1912 out_params->draining = true;
1913 out_params->state = qp->cur_state;
1918 dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_req_ramrod_res),
1919 p_req_ramrod_res, req_ramrod_res_phys);
1922 dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_resp_ramrod_res),
1923 p_resp_ramrod_res, resp_ramrod_res_phys);
1927 int qed_roce_destroy_qp(struct qed_hwfn *p_hwfn, struct qed_rdma_qp *qp)
1929 u32 num_invalidated_mw = 0;
1930 u32 num_bound_mw = 0;
1934 /* Destroys the specified QP */
1935 if ((qp->cur_state != QED_ROCE_QP_STATE_RESET) &&
1936 (qp->cur_state != QED_ROCE_QP_STATE_ERR) &&
1937 (qp->cur_state != QED_ROCE_QP_STATE_INIT)) {
1939 "QP must be in error, reset or init state before destroying it\n");
1943 rc = qed_roce_sp_destroy_qp_responder(p_hwfn, qp, &num_invalidated_mw);
1947 /* Send destroy requester ramrod */
1948 rc = qed_roce_sp_destroy_qp_requester(p_hwfn, qp, &num_bound_mw);
1952 if (num_invalidated_mw != num_bound_mw) {
1954 "number of invalidate memory windows is different from bounded ones\n");
1958 spin_lock_bh(&p_hwfn->p_rdma_info->lock);
1960 start_cid = qed_cxt_get_proto_cid_start(p_hwfn,
1961 p_hwfn->p_rdma_info->proto);
1963 /* Release responder's icid */
1964 qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->cid_map,
1965 qp->icid - start_cid);
1967 /* Release requester's icid */
1968 qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->cid_map,
1969 qp->icid + 1 - start_cid);
1971 spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
1976 int qed_rdma_query_qp(void *rdma_cxt,
1977 struct qed_rdma_qp *qp,
1978 struct qed_rdma_query_qp_out_params *out_params)
1980 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
1983 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid);
1985 /* The following fields are filled in from qp and not FW as they can't
1988 out_params->mtu = qp->mtu;
1989 out_params->dest_qp = qp->dest_qp;
1990 out_params->incoming_atomic_en = qp->incoming_atomic_en;
1991 out_params->e2e_flow_control_en = qp->e2e_flow_control_en;
1992 out_params->incoming_rdma_read_en = qp->incoming_rdma_read_en;
1993 out_params->incoming_rdma_write_en = qp->incoming_rdma_write_en;
1994 out_params->dgid = qp->dgid;
1995 out_params->flow_label = qp->flow_label;
1996 out_params->hop_limit_ttl = qp->hop_limit_ttl;
1997 out_params->traffic_class_tos = qp->traffic_class_tos;
1998 out_params->timeout = qp->ack_timeout;
1999 out_params->rnr_retry = qp->rnr_retry_cnt;
2000 out_params->retry_cnt = qp->retry_cnt;
2001 out_params->min_rnr_nak_timer = qp->min_rnr_nak_timer;
2002 out_params->pkey_index = 0;
2003 out_params->max_rd_atomic = qp->max_rd_atomic_req;
2004 out_params->max_dest_rd_atomic = qp->max_rd_atomic_resp;
2005 out_params->sqd_async = qp->sqd_async;
2007 rc = qed_roce_query_qp(p_hwfn, qp, out_params);
2009 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Query QP, rc = %d\n", rc);
2013 int qed_rdma_destroy_qp(void *rdma_cxt, struct qed_rdma_qp *qp)
2015 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
2018 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid);
2020 rc = qed_roce_destroy_qp(p_hwfn, qp);
2022 /* free qp params struct */
2025 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "QP destroyed\n");
2029 struct qed_rdma_qp *
2030 qed_rdma_create_qp(void *rdma_cxt,
2031 struct qed_rdma_create_qp_in_params *in_params,
2032 struct qed_rdma_create_qp_out_params *out_params)
2034 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
2035 struct qed_rdma_qp *qp;
2036 u8 max_stats_queues;
2039 if (!rdma_cxt || !in_params || !out_params || !p_hwfn->p_rdma_info) {
2040 DP_ERR(p_hwfn->cdev,
2041 "qed roce create qp failed due to NULL entry (rdma_cxt=%p, in=%p, out=%p, roce_info=?\n",
2042 rdma_cxt, in_params, out_params);
2046 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
2047 "qed rdma create qp called with qp_handle = %08x%08x\n",
2048 in_params->qp_handle_hi, in_params->qp_handle_lo);
2050 /* Some sanity checks... */
2051 max_stats_queues = p_hwfn->p_rdma_info->dev->max_stats_queues;
2052 if (in_params->stats_queue >= max_stats_queues) {
2053 DP_ERR(p_hwfn->cdev,
2054 "qed rdma create qp failed due to invalid statistics queue %d. maximum is %d\n",
2055 in_params->stats_queue, max_stats_queues);
2059 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2061 DP_NOTICE(p_hwfn, "Failed to allocate qed_rdma_qp\n");
2065 rc = qed_roce_alloc_cid(p_hwfn, &qp->icid);
2066 qp->qpid = ((0xFF << 16) | qp->icid);
2068 DP_INFO(p_hwfn, "ROCE qpid=%x\n", qp->qpid);
2075 qp->cur_state = QED_ROCE_QP_STATE_RESET;
2076 qp->qp_handle.hi = cpu_to_le32(in_params->qp_handle_hi);
2077 qp->qp_handle.lo = cpu_to_le32(in_params->qp_handle_lo);
2078 qp->qp_handle_async.hi = cpu_to_le32(in_params->qp_handle_async_hi);
2079 qp->qp_handle_async.lo = cpu_to_le32(in_params->qp_handle_async_lo);
2080 qp->use_srq = in_params->use_srq;
2081 qp->signal_all = in_params->signal_all;
2082 qp->fmr_and_reserved_lkey = in_params->fmr_and_reserved_lkey;
2083 qp->pd = in_params->pd;
2084 qp->dpi = in_params->dpi;
2085 qp->sq_cq_id = in_params->sq_cq_id;
2086 qp->sq_num_pages = in_params->sq_num_pages;
2087 qp->sq_pbl_ptr = in_params->sq_pbl_ptr;
2088 qp->rq_cq_id = in_params->rq_cq_id;
2089 qp->rq_num_pages = in_params->rq_num_pages;
2090 qp->rq_pbl_ptr = in_params->rq_pbl_ptr;
2091 qp->srq_id = in_params->srq_id;
2092 qp->req_offloaded = false;
2093 qp->resp_offloaded = false;
2094 qp->e2e_flow_control_en = qp->use_srq ? false : true;
2095 qp->stats_queue = in_params->stats_queue;
2097 out_params->icid = qp->icid;
2098 out_params->qp_id = qp->qpid;
2100 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Create QP, rc = %d\n", rc);
2104 static int qed_roce_modify_qp(struct qed_hwfn *p_hwfn,
2105 struct qed_rdma_qp *qp,
2106 enum qed_roce_qp_state prev_state,
2107 struct qed_rdma_modify_qp_in_params *params)
2109 u32 num_invalidated_mw = 0, num_bound_mw = 0;
2112 /* Perform additional operations according to the current state and the
2115 if (((prev_state == QED_ROCE_QP_STATE_INIT) ||
2116 (prev_state == QED_ROCE_QP_STATE_RESET)) &&
2117 (qp->cur_state == QED_ROCE_QP_STATE_RTR)) {
2118 /* Init->RTR or Reset->RTR */
2119 rc = qed_roce_sp_create_responder(p_hwfn, qp);
2121 } else if ((prev_state == QED_ROCE_QP_STATE_RTR) &&
2122 (qp->cur_state == QED_ROCE_QP_STATE_RTS)) {
2124 rc = qed_roce_sp_create_requester(p_hwfn, qp);
2128 /* Send modify responder ramrod */
2129 rc = qed_roce_sp_modify_responder(p_hwfn, qp, false,
2130 params->modify_flags);
2132 } else if ((prev_state == QED_ROCE_QP_STATE_RTS) &&
2133 (qp->cur_state == QED_ROCE_QP_STATE_RTS)) {
2135 rc = qed_roce_sp_modify_responder(p_hwfn, qp, false,
2136 params->modify_flags);
2140 rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, false,
2141 params->modify_flags);
2143 } else if ((prev_state == QED_ROCE_QP_STATE_RTS) &&
2144 (qp->cur_state == QED_ROCE_QP_STATE_SQD)) {
2146 rc = qed_roce_sp_modify_requester(p_hwfn, qp, true, false,
2147 params->modify_flags);
2149 } else if ((prev_state == QED_ROCE_QP_STATE_SQD) &&
2150 (qp->cur_state == QED_ROCE_QP_STATE_SQD)) {
2152 rc = qed_roce_sp_modify_responder(p_hwfn, qp, false,
2153 params->modify_flags);
2157 rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, false,
2158 params->modify_flags);
2160 } else if ((prev_state == QED_ROCE_QP_STATE_SQD) &&
2161 (qp->cur_state == QED_ROCE_QP_STATE_RTS)) {
2163 rc = qed_roce_sp_modify_responder(p_hwfn, qp, false,
2164 params->modify_flags);
2168 rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, false,
2169 params->modify_flags);
2172 } else if (qp->cur_state == QED_ROCE_QP_STATE_ERR ||
2173 qp->cur_state == QED_ROCE_QP_STATE_SQE) {
2175 rc = qed_roce_sp_modify_responder(p_hwfn, qp, true,
2176 params->modify_flags);
2180 rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, true,
2181 params->modify_flags);
2183 } else if (qp->cur_state == QED_ROCE_QP_STATE_RESET) {
2184 /* Any state -> RESET */
2186 rc = qed_roce_sp_destroy_qp_responder(p_hwfn, qp,
2187 &num_invalidated_mw);
2191 rc = qed_roce_sp_destroy_qp_requester(p_hwfn, qp,
2194 if (num_invalidated_mw != num_bound_mw) {
2196 "number of invalidate memory windows is different from bounded ones\n");
2200 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "0\n");
2206 int qed_rdma_modify_qp(void *rdma_cxt,
2207 struct qed_rdma_qp *qp,
2208 struct qed_rdma_modify_qp_in_params *params)
2210 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
2211 enum qed_roce_qp_state prev_state;
2214 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x params->new_state=%d\n",
2215 qp->icid, params->new_state);
2218 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc);
2222 if (GET_FIELD(params->modify_flags,
2223 QED_RDMA_MODIFY_QP_VALID_RDMA_OPS_EN)) {
2224 qp->incoming_rdma_read_en = params->incoming_rdma_read_en;
2225 qp->incoming_rdma_write_en = params->incoming_rdma_write_en;
2226 qp->incoming_atomic_en = params->incoming_atomic_en;
2229 /* Update QP structure with the updated values */
2230 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_ROCE_MODE))
2231 qp->roce_mode = params->roce_mode;
2232 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_PKEY))
2233 qp->pkey = params->pkey;
2234 if (GET_FIELD(params->modify_flags,
2235 QED_ROCE_MODIFY_QP_VALID_E2E_FLOW_CONTROL_EN))
2236 qp->e2e_flow_control_en = params->e2e_flow_control_en;
2237 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_DEST_QP))
2238 qp->dest_qp = params->dest_qp;
2239 if (GET_FIELD(params->modify_flags,
2240 QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR)) {
2241 /* Indicates that the following parameters have changed:
2242 * Traffic class, flow label, hop limit, source GID,
2243 * destination GID, loopback indicator
2245 qp->traffic_class_tos = params->traffic_class_tos;
2246 qp->flow_label = params->flow_label;
2247 qp->hop_limit_ttl = params->hop_limit_ttl;
2249 qp->sgid = params->sgid;
2250 qp->dgid = params->dgid;
2251 qp->udp_src_port = 0;
2252 qp->vlan_id = params->vlan_id;
2253 qp->mtu = params->mtu;
2254 qp->lb_indication = params->lb_indication;
2255 memcpy((u8 *)&qp->remote_mac_addr[0],
2256 (u8 *)¶ms->remote_mac_addr[0], ETH_ALEN);
2257 if (params->use_local_mac) {
2258 memcpy((u8 *)&qp->local_mac_addr[0],
2259 (u8 *)¶ms->local_mac_addr[0], ETH_ALEN);
2261 memcpy((u8 *)&qp->local_mac_addr[0],
2262 (u8 *)&p_hwfn->hw_info.hw_mac_addr, ETH_ALEN);
2265 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_RQ_PSN))
2266 qp->rq_psn = params->rq_psn;
2267 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_SQ_PSN))
2268 qp->sq_psn = params->sq_psn;
2269 if (GET_FIELD(params->modify_flags,
2270 QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_REQ))
2271 qp->max_rd_atomic_req = params->max_rd_atomic_req;
2272 if (GET_FIELD(params->modify_flags,
2273 QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_RESP))
2274 qp->max_rd_atomic_resp = params->max_rd_atomic_resp;
2275 if (GET_FIELD(params->modify_flags,
2276 QED_ROCE_MODIFY_QP_VALID_ACK_TIMEOUT))
2277 qp->ack_timeout = params->ack_timeout;
2278 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_RETRY_CNT))
2279 qp->retry_cnt = params->retry_cnt;
2280 if (GET_FIELD(params->modify_flags,
2281 QED_ROCE_MODIFY_QP_VALID_RNR_RETRY_CNT))
2282 qp->rnr_retry_cnt = params->rnr_retry_cnt;
2283 if (GET_FIELD(params->modify_flags,
2284 QED_ROCE_MODIFY_QP_VALID_MIN_RNR_NAK_TIMER))
2285 qp->min_rnr_nak_timer = params->min_rnr_nak_timer;
2287 qp->sqd_async = params->sqd_async;
2289 prev_state = qp->cur_state;
2290 if (GET_FIELD(params->modify_flags,
2291 QED_RDMA_MODIFY_QP_VALID_NEW_STATE)) {
2292 qp->cur_state = params->new_state;
2293 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "qp->cur_state=%d\n",
2297 rc = qed_roce_modify_qp(p_hwfn, qp, prev_state, params);
2299 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Modify QP, rc = %d\n", rc);
2303 static void *qed_rdma_get_rdma_ctx(struct qed_dev *cdev)
2305 return QED_LEADING_HWFN(cdev);
2308 static void qed_rdma_dpm_conf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2312 val = (p_hwfn->dcbx_no_edpm || p_hwfn->db_bar_no_edpm) ? 0 : 1;
2314 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPM_ENABLE, val);
2315 DP_VERBOSE(p_hwfn, (QED_MSG_DCB | QED_MSG_RDMA),
2316 "Changing DPM_EN state to %d (DCBX=%d, DB_BAR=%d)\n",
2317 val, p_hwfn->dcbx_no_edpm, p_hwfn->db_bar_no_edpm);
2320 void qed_rdma_dpm_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2322 p_hwfn->db_bar_no_edpm = true;
2324 qed_rdma_dpm_conf(p_hwfn, p_ptt);
2327 int qed_rdma_start(void *rdma_cxt, struct qed_rdma_start_in_params *params)
2329 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
2330 struct qed_ptt *p_ptt;
2333 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
2334 "desired_cnq = %08x\n", params->desired_cnq);
2336 p_ptt = qed_ptt_acquire(p_hwfn);
2340 rc = qed_rdma_alloc(p_hwfn, p_ptt, params);
2344 rc = qed_rdma_setup(p_hwfn, p_ptt, params);
2348 qed_ptt_release(p_hwfn, p_ptt);
2353 qed_rdma_free(p_hwfn);
2355 qed_ptt_release(p_hwfn, p_ptt);
2357 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA start - error, rc = %d\n", rc);
2361 static int qed_rdma_init(struct qed_dev *cdev,
2362 struct qed_rdma_start_in_params *params)
2364 return qed_rdma_start(QED_LEADING_HWFN(cdev), params);
2367 void qed_rdma_remove_user(void *rdma_cxt, u16 dpi)
2369 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
2371 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "dpi = %08x\n", dpi);
2373 spin_lock_bh(&p_hwfn->p_rdma_info->lock);
2374 qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->dpi_map, dpi);
2375 spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
2378 static const struct qed_rdma_ops qed_rdma_ops_pass = {
2379 .common = &qed_common_ops_pass,
2380 .fill_dev_info = &qed_fill_rdma_dev_info,
2381 .rdma_get_rdma_ctx = &qed_rdma_get_rdma_ctx,
2382 .rdma_init = &qed_rdma_init,
2383 .rdma_add_user = &qed_rdma_add_user,
2384 .rdma_remove_user = &qed_rdma_remove_user,
2385 .rdma_stop = &qed_rdma_stop,
2386 .rdma_query_port = &qed_rdma_query_port,
2387 .rdma_query_device = &qed_rdma_query_device,
2388 .rdma_get_start_sb = &qed_rdma_get_sb_start,
2389 .rdma_get_rdma_int = &qed_rdma_get_int,
2390 .rdma_set_rdma_int = &qed_rdma_set_int,
2391 .rdma_get_min_cnq_msix = &qed_rdma_get_min_cnq_msix,
2392 .rdma_cnq_prod_update = &qed_rdma_cnq_prod_update,
2393 .rdma_alloc_pd = &qed_rdma_alloc_pd,
2394 .rdma_dealloc_pd = &qed_rdma_free_pd,
2395 .rdma_create_cq = &qed_rdma_create_cq,
2396 .rdma_destroy_cq = &qed_rdma_destroy_cq,
2397 .rdma_create_qp = &qed_rdma_create_qp,
2398 .rdma_modify_qp = &qed_rdma_modify_qp,
2399 .rdma_query_qp = &qed_rdma_query_qp,
2400 .rdma_destroy_qp = &qed_rdma_destroy_qp,
2403 const struct qed_rdma_ops *qed_get_rdma_ops()
2405 return &qed_rdma_ops_pass;
2407 EXPORT_SYMBOL(qed_get_rdma_ops);