drivers/net/ethernet/qlogic/qed/qed_roce.c

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015-2016  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32 #include <linux/types.h>
  33 #include <asm/byteorder.h>
  34 #include <linux/bitops.h>
  35 #include <linux/delay.h>
  36 #include <linux/dma-mapping.h>
  37 #include <linux/errno.h>
  38 #include <linux/etherdevice.h>
  39 #include <linux/if_ether.h>
  40 #include <linux/if_vlan.h>
  41 #include <linux/io.h>
  42 #include <linux/ip.h>
  43 #include <linux/ipv6.h>
  44 #include <linux/kernel.h>
  45 #include <linux/list.h>
  46 #include <linux/module.h>
  47 #include <linux/mutex.h>
  48 #include <linux/pci.h>
  49 #include <linux/slab.h>
  50 #include <linux/spinlock.h>
  51 #include <linux/string.h>
  52 #include <linux/tcp.h>
  53 #include <linux/bitops.h>
  54 #include <linux/qed/qed_roce_if.h>
  55 #include <linux/qed/qed_roce_if.h>
  56 #include "qed.h"
  57 #include "qed_cxt.h"
  58 #include "qed_hsi.h"
  59 #include "qed_hw.h"
  60 #include "qed_init_ops.h"
  61 #include "qed_int.h"
  62 #include "qed_ll2.h"
  63 #include "qed_mcp.h"
  64 #include "qed_reg_addr.h"
  65 #include "qed_sp.h"
  66 #include "qed_roce.h"
  67
  68 void qed_async_roce_event(struct qed_hwfn *p_hwfn,
  69                           struct event_ring_entry *p_eqe)
  70 {
  71         struct qed_rdma_info *p_rdma_info = p_hwfn->p_rdma_info;
  72
  73         p_rdma_info->events.affiliated_event(p_rdma_info->events.context,
  74                                              p_eqe->opcode, &p_eqe->data);
  75 }
  76
  77 static int qed_rdma_bmap_alloc(struct qed_hwfn *p_hwfn,
  78                                struct qed_bmap *bmap, u32 max_count)
  79 {
  80         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "max_count = %08x\n", max_count);
  81
  82         bmap->max_count = max_count;
  83
  84         bmap->bitmap = kzalloc(BITS_TO_LONGS(max_count) * sizeof(long),
  85                                GFP_KERNEL);
  86         if (!bmap->bitmap) {
  87                 DP_NOTICE(p_hwfn,
  88                           "qed bmap alloc failed: cannot allocate memory (bitmap)\n");
  89                 return -ENOMEM;
  90         }
  91
  92         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocated bitmap %p\n",
  93                    bmap->bitmap);
  94         return 0;
  95 }
  96
  97 static int qed_rdma_bmap_alloc_id(struct qed_hwfn *p_hwfn,
  98                                   struct qed_bmap *bmap, u32 *id_num)
  99 {
 100         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "bmap = %p\n", bmap);
 101
 102         *id_num = find_first_zero_bit(bmap->bitmap, bmap->max_count);
 103
 104         if (*id_num >= bmap->max_count) {
 105                 DP_NOTICE(p_hwfn, "no id available max_count=%d\n",
 106                           bmap->max_count);
 107                 return -EINVAL;
 108         }
 109
 110         __set_bit(*id_num, bmap->bitmap);
 111
 112         return 0;
 113 }
 114
 115 static void qed_bmap_release_id(struct qed_hwfn *p_hwfn,
 116                                 struct qed_bmap *bmap, u32 id_num)
 117 {
 118         bool b_acquired;
 119
 120         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "id_num = %08x", id_num);
 121         if (id_num >= bmap->max_count)
 122                 return;
 123
 124         b_acquired = test_and_clear_bit(id_num, bmap->bitmap);
 125         if (!b_acquired) {
 126                 DP_NOTICE(p_hwfn, "ID %d already released\n", id_num);
 127                 return;
 128         }
 129 }
 130
 131 u32 qed_rdma_get_sb_id(void *p_hwfn, u32 rel_sb_id)
 132 {
 133         /* First sb id for RoCE is after all the l2 sb */
 134         return FEAT_NUM((struct qed_hwfn *)p_hwfn, QED_PF_L2_QUE) + rel_sb_id;
 135 }
 136
 137 u32 qed_rdma_query_cau_timer_res(void *rdma_cxt)
 138 {
 139         return QED_CAU_DEF_RX_TIMER_RES;
 140 }
 141
 142 static int qed_rdma_alloc(struct qed_hwfn *p_hwfn,
 143                           struct qed_ptt *p_ptt,
 144                           struct qed_rdma_start_in_params *params)
 145 {
 146         struct qed_rdma_info *p_rdma_info;
 147         u32 num_cons, num_tasks;
 148         int rc = -ENOMEM;
 149
 150         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocating RDMA\n");
 151
 152         /* Allocate a struct with current pf rdma info */
 153         p_rdma_info = kzalloc(sizeof(*p_rdma_info), GFP_KERNEL);
 154         if (!p_rdma_info) {
 155                 DP_NOTICE(p_hwfn,
 156                           "qed rdma alloc failed: cannot allocate memory (rdma info). rc = %d\n",
 157                           rc);
 158                 return rc;
 159         }
 160
 161         p_hwfn->p_rdma_info = p_rdma_info;
 162         p_rdma_info->proto = PROTOCOLID_ROCE;
 163
 164         num_cons = qed_cxt_get_proto_cid_count(p_hwfn, p_rdma_info->proto, 0);
 165
 166         p_rdma_info->num_qps = num_cons / 2;
 167
 168         num_tasks = qed_cxt_get_proto_tid_count(p_hwfn, PROTOCOLID_ROCE);
 169
 170         /* Each MR uses a single task */
 171         p_rdma_info->num_mrs = num_tasks;
 172
 173         /* Queue zone lines are shared between RoCE and L2 in such a way that
 174          * they can be used by each without obstructing the other.
 175          */
 176         p_rdma_info->queue_zone_base = (u16)FEAT_NUM(p_hwfn, QED_L2_QUEUE);
 177
 178         /* Allocate a struct with device params and fill it */
 179         p_rdma_info->dev = kzalloc(sizeof(*p_rdma_info->dev), GFP_KERNEL);
 180         if (!p_rdma_info->dev) {
 181                 DP_NOTICE(p_hwfn,
 182                           "qed rdma alloc failed: cannot allocate memory (rdma info dev). rc = %d\n",
 183                           rc);
 184                 goto free_rdma_info;
 185         }
 186
 187         /* Allocate a struct with port params and fill it */
 188         p_rdma_info->port = kzalloc(sizeof(*p_rdma_info->port), GFP_KERNEL);
 189         if (!p_rdma_info->port) {
 190                 DP_NOTICE(p_hwfn,
 191                           "qed rdma alloc failed: cannot allocate memory (rdma info port). rc = %d\n",
 192                           rc);
 193                 goto free_rdma_dev;
 194         }
 195
 196         /* Allocate bit map for pd's */
 197         rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->pd_map, RDMA_MAX_PDS);
 198         if (rc) {
 199                 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
 200                            "Failed to allocate pd_map, rc = %d\n",
 201                            rc);
 202                 goto free_rdma_port;
 203         }
 204
 205         /* Allocate DPI bitmap */
 206         rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->dpi_map,
 207                                  p_hwfn->dpi_count);
 208         if (rc) {
 209                 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
 210                            "Failed to allocate DPI bitmap, rc = %d\n", rc);
 211                 goto free_pd_map;
 212         }
 213
 214         /* Allocate bitmap for cq's. The maximum number of CQs is bounded to
 215          * twice the number of QPs.
 216          */
 217         rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->cq_map,
 218                                  p_rdma_info->num_qps * 2);
 219         if (rc) {
 220                 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
 221                            "Failed to allocate cq bitmap, rc = %d\n", rc);
 222                 goto free_dpi_map;
 223         }
 224
 225         /* Allocate bitmap for toggle bit for cq icids
 226          * We toggle the bit every time we create or resize cq for a given icid.
 227          * The maximum number of CQs is bounded to  twice the number of QPs.
 228          */
 229         rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->toggle_bits,
 230                                  p_rdma_info->num_qps * 2);
 231         if (rc) {
 232                 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
 233                            "Failed to allocate toogle bits, rc = %d\n", rc);
 234                 goto free_cq_map;
 235         }
 236
 237         /* Allocate bitmap for itids */
 238         rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->tid_map,
 239                                  p_rdma_info->num_mrs);
 240         if (rc) {
 241                 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
 242                            "Failed to allocate itids bitmaps, rc = %d\n", rc);
 243                 goto free_toggle_map;
 244         }
 245
 246         /* Allocate bitmap for cids used for qps. */
 247         rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->cid_map, num_cons);
 248         if (rc) {
 249                 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
 250                            "Failed to allocate cid bitmap, rc = %d\n", rc);
 251                 goto free_tid_map;
 252         }
 253
 254         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocation successful\n");
 255         return 0;
 256
 257 free_tid_map:
 258         kfree(p_rdma_info->tid_map.bitmap);
 259 free_toggle_map:
 260         kfree(p_rdma_info->toggle_bits.bitmap);
 261 free_cq_map:
 262         kfree(p_rdma_info->cq_map.bitmap);
 263 free_dpi_map:
 264         kfree(p_rdma_info->dpi_map.bitmap);
 265 free_pd_map:
 266         kfree(p_rdma_info->pd_map.bitmap);
 267 free_rdma_port:
 268         kfree(p_rdma_info->port);
 269 free_rdma_dev:
 270         kfree(p_rdma_info->dev);
 271 free_rdma_info:
 272         kfree(p_rdma_info);
 273
 274         return rc;
 275 }
 276
 277 void qed_rdma_resc_free(struct qed_hwfn *p_hwfn)
 278 {
 279         struct qed_rdma_info *p_rdma_info = p_hwfn->p_rdma_info;
 280
 281         kfree(p_rdma_info->cid_map.bitmap);
 282         kfree(p_rdma_info->tid_map.bitmap);
 283         kfree(p_rdma_info->toggle_bits.bitmap);
 284         kfree(p_rdma_info->cq_map.bitmap);
 285         kfree(p_rdma_info->dpi_map.bitmap);
 286         kfree(p_rdma_info->pd_map.bitmap);
 287
 288         kfree(p_rdma_info->port);
 289         kfree(p_rdma_info->dev);
 290
 291         kfree(p_rdma_info);
 292 }
 293
 294 static void qed_rdma_free(struct qed_hwfn *p_hwfn)
 295 {
 296         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Freeing RDMA\n");
 297
 298         qed_rdma_resc_free(p_hwfn);
 299 }
 300
 301 static void qed_rdma_get_guid(struct qed_hwfn *p_hwfn, u8 *guid)
 302 {
 303         guid[0] = p_hwfn->hw_info.hw_mac_addr[0] ^ 2;
 304         guid[1] = p_hwfn->hw_info.hw_mac_addr[1];
 305         guid[2] = p_hwfn->hw_info.hw_mac_addr[2];
 306         guid[3] = 0xff;
 307         guid[4] = 0xfe;
 308         guid[5] = p_hwfn->hw_info.hw_mac_addr[3];
 309         guid[6] = p_hwfn->hw_info.hw_mac_addr[4];
 310         guid[7] = p_hwfn->hw_info.hw_mac_addr[5];
 311 }
 312
 313 static void qed_rdma_init_events(struct qed_hwfn *p_hwfn,
 314                                  struct qed_rdma_start_in_params *params)
 315 {
 316         struct qed_rdma_events *events;
 317
 318         events = &p_hwfn->p_rdma_info->events;
 319
 320         events->unaffiliated_event = params->events->unaffiliated_event;
 321         events->affiliated_event = params->events->affiliated_event;
 322         events->context = params->events->context;
 323 }
 324
 325 static void qed_rdma_init_devinfo(struct qed_hwfn *p_hwfn,
 326                                   struct qed_rdma_start_in_params *params)
 327 {
 328         struct qed_rdma_device *dev = p_hwfn->p_rdma_info->dev;
 329         struct qed_dev *cdev = p_hwfn->cdev;
 330         u32 pci_status_control;
 331         u32 num_qps;
 332
 333         /* Vendor specific information */
 334         dev->vendor_id = cdev->vendor_id;
 335         dev->vendor_part_id = cdev->device_id;
 336         dev->hw_ver = 0;
 337         dev->fw_ver = (FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) |
 338                       (FW_REVISION_VERSION << 8) | (FW_ENGINEERING_VERSION);
 339
 340         qed_rdma_get_guid(p_hwfn, (u8 *)&dev->sys_image_guid);
 341         dev->node_guid = dev->sys_image_guid;
 342
 343         dev->max_sge = min_t(u32, RDMA_MAX_SGE_PER_SQ_WQE,
 344                              RDMA_MAX_SGE_PER_RQ_WQE);
 345
 346         if (cdev->rdma_max_sge)
 347                 dev->max_sge = min_t(u32, cdev->rdma_max_sge, dev->max_sge);
 348
 349         dev->max_inline = ROCE_REQ_MAX_INLINE_DATA_SIZE;
 350
 351         dev->max_inline = (cdev->rdma_max_inline) ?
 352                           min_t(u32, cdev->rdma_max_inline, dev->max_inline) :
 353                           dev->max_inline;
 354
 355         dev->max_wqe = QED_RDMA_MAX_WQE;
 356         dev->max_cnq = (u8)FEAT_NUM(p_hwfn, QED_RDMA_CNQ);
 357
 358         /* The number of QPs may be higher than QED_ROCE_MAX_QPS, because
 359          * it is up-aligned to 16 and then to ILT page size within qed cxt.
 360          * This is OK in terms of ILT but we don't want to configure the FW
 361          * above its abilities
 362          */
 363         num_qps = ROCE_MAX_QPS;
 364         num_qps = min_t(u64, num_qps, p_hwfn->p_rdma_info->num_qps);
 365         dev->max_qp = num_qps;
 366
 367         /* CQs uses the same icids that QPs use hence they are limited by the
 368          * number of icids. There are two icids per QP.
 369          */
 370         dev->max_cq = num_qps * 2;
 371
 372         /* The number of mrs is smaller by 1 since the first is reserved */
 373         dev->max_mr = p_hwfn->p_rdma_info->num_mrs - 1;
 374         dev->max_mr_size = QED_RDMA_MAX_MR_SIZE;
 375
 376         /* The maximum CQE capacity per CQ supported.
 377          * max number of cqes will be in two layer pbl,
 378          * 8 is the pointer size in bytes
 379          * 32 is the size of cq element in bytes
 380          */
 381         if (params->cq_mode == QED_RDMA_CQ_MODE_32_BITS)
 382                 dev->max_cqe = QED_RDMA_MAX_CQE_32_BIT;
 383         else
 384                 dev->max_cqe = QED_RDMA_MAX_CQE_16_BIT;
 385
 386         dev->max_mw = 0;
 387         dev->max_fmr = QED_RDMA_MAX_FMR;
 388         dev->max_mr_mw_fmr_pbl = (PAGE_SIZE / 8) * (PAGE_SIZE / 8);
 389         dev->max_mr_mw_fmr_size = dev->max_mr_mw_fmr_pbl * PAGE_SIZE;
 390         dev->max_pkey = QED_RDMA_MAX_P_KEY;
 391
 392         dev->max_qp_resp_rd_atomic_resc = RDMA_RING_PAGE_SIZE /
 393                                           (RDMA_RESP_RD_ATOMIC_ELM_SIZE * 2);
 394         dev->max_qp_req_rd_atomic_resc = RDMA_RING_PAGE_SIZE /
 395                                          RDMA_REQ_RD_ATOMIC_ELM_SIZE;
 396         dev->max_dev_resp_rd_atomic_resc = dev->max_qp_resp_rd_atomic_resc *
 397                                            p_hwfn->p_rdma_info->num_qps;
 398         dev->page_size_caps = QED_RDMA_PAGE_SIZE_CAPS;
 399         dev->dev_ack_delay = QED_RDMA_ACK_DELAY;
 400         dev->max_pd = RDMA_MAX_PDS;
 401         dev->max_ah = p_hwfn->p_rdma_info->num_qps;
 402         dev->max_stats_queues = (u8)RESC_NUM(p_hwfn, QED_RDMA_STATS_QUEUE);
 403
 404         /* Set capablities */
 405         dev->dev_caps = 0;
 406         SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_RNR_NAK, 1);
 407         SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_PORT_ACTIVE_EVENT, 1);
 408         SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_PORT_CHANGE_EVENT, 1);
 409         SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_RESIZE_CQ, 1);
 410         SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_BASE_MEMORY_EXT, 1);
 411         SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_BASE_QUEUE_EXT, 1);
 412         SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_ZBVA, 1);
 413         SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_LOCAL_INV_FENCE, 1);
 414
 415         /* Check atomic operations support in PCI configuration space. */
 416         pci_read_config_dword(cdev->pdev,
 417                               cdev->pdev->pcie_cap + PCI_EXP_DEVCTL2,
 418                               &pci_status_control);
 419
 420         if (pci_status_control & PCI_EXP_DEVCTL2_LTR_EN)
 421                 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_ATOMIC_OP, 1);
 422 }
 423
 424 static void qed_rdma_init_port(struct qed_hwfn *p_hwfn)
 425 {
 426         struct qed_rdma_port *port = p_hwfn->p_rdma_info->port;
 427         struct qed_rdma_device *dev = p_hwfn->p_rdma_info->dev;
 428
 429         port->port_state = p_hwfn->mcp_info->link_output.link_up ?
 430                            QED_RDMA_PORT_UP : QED_RDMA_PORT_DOWN;
 431
 432         port->max_msg_size = min_t(u64,
 433                                    (dev->max_mr_mw_fmr_size *
 434                                     p_hwfn->cdev->rdma_max_sge),
 435                                    BIT(31));
 436
 437         port->pkey_bad_counter = 0;
 438 }
 439
 440 static int qed_rdma_init_hw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 441 {
 442         u32 ll2_ethertype_en;
 443
 444         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Initializing HW\n");
 445         p_hwfn->b_rdma_enabled_in_prs = false;
 446
 447         qed_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF, 0);
 448
 449         p_hwfn->rdma_prs_search_reg = PRS_REG_SEARCH_ROCE;
 450
 451         /* We delay writing to this reg until first cid is allocated. See
 452          * qed_cxt_dynamic_ilt_alloc function for more details
 453          */
 454         ll2_ethertype_en = qed_rd(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN);
 455         qed_wr(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN,
 456                (ll2_ethertype_en | 0x01));
 457
 458         if (qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_ROCE) % 2) {
 459                 DP_NOTICE(p_hwfn, "The first RoCE's cid should be even\n");
 460                 return -EINVAL;
 461         }
 462
 463         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Initializing HW - Done\n");
 464         return 0;
 465 }
 466
 467 static int qed_rdma_start_fw(struct qed_hwfn *p_hwfn,
 468                              struct qed_rdma_start_in_params *params,
 469                              struct qed_ptt *p_ptt)
 470 {
 471         struct rdma_init_func_ramrod_data *p_ramrod;
 472         struct qed_rdma_cnq_params *p_cnq_pbl_list;
 473         struct rdma_init_func_hdr *p_params_header;
 474         struct rdma_cnq_params *p_cnq_params;
 475         struct qed_sp_init_data init_data;
 476         struct qed_spq_entry *p_ent;
 477         u32 cnq_id, sb_id;
 478         int rc;
 479
 480         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Starting FW\n");
 481
 482         /* Save the number of cnqs for the function close ramrod */
 483         p_hwfn->p_rdma_info->num_cnqs = params->desired_cnq;
 484
 485         /* Get SPQ entry */
 486         memset(&init_data, 0, sizeof(init_data));
 487         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
 488         init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
 489
 490         rc = qed_sp_init_request(p_hwfn, &p_ent, RDMA_RAMROD_FUNC_INIT,
 491                                  p_hwfn->p_rdma_info->proto, &init_data);
 492         if (rc)
 493                 return rc;
 494
 495         p_ramrod = &p_ent->ramrod.roce_init_func.rdma;
 496
 497         p_params_header = &p_ramrod->params_header;
 498         p_params_header->cnq_start_offset = (u8)RESC_START(p_hwfn,
 499                                                            QED_RDMA_CNQ_RAM);
 500         p_params_header->num_cnqs = params->desired_cnq;
 501
 502         if (params->cq_mode == QED_RDMA_CQ_MODE_16_BITS)
 503                 p_params_header->cq_ring_mode = 1;
 504         else
 505                 p_params_header->cq_ring_mode = 0;
 506
 507         for (cnq_id = 0; cnq_id < params->desired_cnq; cnq_id++) {
 508                 sb_id = qed_rdma_get_sb_id(p_hwfn, cnq_id);
 509                 p_cnq_params = &p_ramrod->cnq_params[cnq_id];
 510                 p_cnq_pbl_list = &params->cnq_pbl_list[cnq_id];
 511                 p_cnq_params->sb_num =
 512                         cpu_to_le16(p_hwfn->sbs_info[sb_id]->igu_sb_id);
 513
 514                 p_cnq_params->sb_index = p_hwfn->pf_params.rdma_pf_params.gl_pi;
 515                 p_cnq_params->num_pbl_pages = p_cnq_pbl_list->num_pbl_pages;
 516
 517                 DMA_REGPAIR_LE(p_cnq_params->pbl_base_addr,
 518                                p_cnq_pbl_list->pbl_ptr);
 519
 520                 /* we assume here that cnq_id and qz_offset are the same */
 521                 p_cnq_params->queue_zone_num =
 522                         cpu_to_le16(p_hwfn->p_rdma_info->queue_zone_base +
 523                                     cnq_id);
 524         }
 525
 526         return qed_spq_post(p_hwfn, p_ent, NULL);
 527 }
 528
 529 static int qed_rdma_reserve_lkey(struct qed_hwfn *p_hwfn)
 530 {
 531         struct qed_rdma_device *dev = p_hwfn->p_rdma_info->dev;
 532
 533         /* The first DPI is reserved for the Kernel */
 534         __set_bit(0, p_hwfn->p_rdma_info->dpi_map.bitmap);
 535
 536         /* Tid 0 will be used as the key for "reserved MR".
 537          * The driver should allocate memory for it so it can be loaded but no
 538          * ramrod should be passed on it.
 539          */
 540         qed_rdma_alloc_tid(p_hwfn, &dev->reserved_lkey);
 541         if (dev->reserved_lkey != RDMA_RESERVED_LKEY) {
 542                 DP_NOTICE(p_hwfn,
 543                           "Reserved lkey should be equal to RDMA_RESERVED_LKEY\n");
 544                 return -EINVAL;
 545         }
 546
 547         return 0;
 548 }
 549
 550 static int qed_rdma_setup(struct qed_hwfn *p_hwfn,
 551                           struct qed_ptt *p_ptt,
 552                           struct qed_rdma_start_in_params *params)
 553 {
 554         int rc;
 555
 556         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA setup\n");
 557
 558         spin_lock_init(&p_hwfn->p_rdma_info->lock);
 559
 560         qed_rdma_init_devinfo(p_hwfn, params);
 561         qed_rdma_init_port(p_hwfn);
 562         qed_rdma_init_events(p_hwfn, params);
 563
 564         rc = qed_rdma_reserve_lkey(p_hwfn);
 565         if (rc)
 566                 return rc;
 567
 568         rc = qed_rdma_init_hw(p_hwfn, p_ptt);
 569         if (rc)
 570                 return rc;
 571
 572         return qed_rdma_start_fw(p_hwfn, params, p_ptt);
 573 }
 574
 575 int qed_rdma_stop(void *rdma_cxt)
 576 {
 577         struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
 578         struct rdma_close_func_ramrod_data *p_ramrod;
 579         struct qed_sp_init_data init_data;
 580         struct qed_spq_entry *p_ent;
 581         struct qed_ptt *p_ptt;
 582         u32 ll2_ethertype_en;
 583         int rc = -EBUSY;
 584
 585         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA stop\n");
 586
 587         p_ptt = qed_ptt_acquire(p_hwfn);
 588         if (!p_ptt) {
 589                 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Failed to acquire PTT\n");
 590                 return rc;
 591         }
 592
 593         /* Disable RoCE search */
 594         qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 0);
 595         p_hwfn->b_rdma_enabled_in_prs = false;
 596
 597         qed_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF, 0);
 598
 599         ll2_ethertype_en = qed_rd(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN);
 600
 601         qed_wr(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN,
 602                (ll2_ethertype_en & 0xFFFE));
 603
 604         qed_ptt_release(p_hwfn, p_ptt);
 605
 606         /* Get SPQ entry */
 607         memset(&init_data, 0, sizeof(init_data));
 608         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
 609         init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
 610
 611         /* Stop RoCE */
 612         rc = qed_sp_init_request(p_hwfn, &p_ent, RDMA_RAMROD_FUNC_CLOSE,
 613                                  p_hwfn->p_rdma_info->proto, &init_data);
 614         if (rc)
 615                 goto out;
 616
 617         p_ramrod = &p_ent->ramrod.rdma_close_func;
 618
 619         p_ramrod->num_cnqs = p_hwfn->p_rdma_info->num_cnqs;
 620         p_ramrod->cnq_start_offset = (u8)RESC_START(p_hwfn, QED_RDMA_CNQ_RAM);
 621
 622         rc = qed_spq_post(p_hwfn, p_ent, NULL);
 623
 624 out:
 625         qed_rdma_free(p_hwfn);
 626
 627         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA stop done, rc = %d\n", rc);
 628         return rc;
 629 }
 630
 631 int qed_rdma_add_user(void *rdma_cxt,
 632                       struct qed_rdma_add_user_out_params *out_params)
 633 {
 634         struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
 635         u32 dpi_start_offset;
 636         u32 returned_id = 0;
 637         int rc;
 638
 639         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Adding User\n");
 640
 641         /* Allocate DPI */
 642         spin_lock_bh(&p_hwfn->p_rdma_info->lock);
 643         rc = qed_rdma_bmap_alloc_id(p_hwfn, &p_hwfn->p_rdma_info->dpi_map,
 644                                     &returned_id);
 645         spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
 646
 647         out_params->dpi = (u16)returned_id;
 648
 649         /* Calculate the corresponding DPI address */
 650         dpi_start_offset = p_hwfn->dpi_start_offset;
 651
 652         out_params->dpi_addr = (u64)((u8 __iomem *)p_hwfn->doorbells +
 653                                      dpi_start_offset +
 654                                      ((out_params->dpi) * p_hwfn->dpi_size));
 655
 656         out_params->dpi_phys_addr = p_hwfn->cdev->db_phys_addr +
 657                                     dpi_start_offset +
 658                                     ((out_params->dpi) * p_hwfn->dpi_size);
 659
 660         out_params->dpi_size = p_hwfn->dpi_size;
 661
 662         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Adding user - done, rc = %d\n", rc);
 663         return rc;
 664 }
 665
 666 struct qed_rdma_port *qed_rdma_query_port(void *rdma_cxt)
 667 {
 668         struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
 669         struct qed_rdma_port *p_port = p_hwfn->p_rdma_info->port;
 670
 671         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA Query port\n");
 672
 673         /* Link may have changed */
 674         p_port->port_state = p_hwfn->mcp_info->link_output.link_up ?
 675                              QED_RDMA_PORT_UP : QED_RDMA_PORT_DOWN;
 676
 677         p_port->link_speed = p_hwfn->mcp_info->link_output.speed;
 678
 679         return p_port;
 680 }
 681
 682 struct qed_rdma_device *qed_rdma_query_device(void *rdma_cxt)
 683 {
 684         struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
 685
 686         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Query device\n");
 687
 688         /* Return struct with device parameters */
 689         return p_hwfn->p_rdma_info->dev;
 690 }
 691
 692 void qed_rdma_free_tid(void *rdma_cxt, u32 itid)
 693 {
 694         struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
 695
 696         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "itid = %08x\n", itid);
 697
 698         spin_lock_bh(&p_hwfn->p_rdma_info->lock);
 699         qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->tid_map, itid);
 700         spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
 701 }
 702
 703 int qed_rdma_alloc_tid(void *rdma_cxt, u32 *itid)
 704 {
 705         struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
 706         int rc;
 707
 708         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocate TID\n");
 709
 710         spin_lock_bh(&p_hwfn->p_rdma_info->lock);
 711         rc = qed_rdma_bmap_alloc_id(p_hwfn,
 712                                     &p_hwfn->p_rdma_info->tid_map, itid);
 713         spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
 714         if (rc)
 715                 goto out;
 716
 717         rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_TASK, *itid);
 718 out:
 719         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocate TID - done, rc = %d\n", rc);
 720         return rc;
 721 }
 722
 723 void qed_rdma_cnq_prod_update(void *rdma_cxt, u8 qz_offset, u16 prod)
 724 {
 725         struct qed_hwfn *p_hwfn;
 726         u16 qz_num;
 727         u32 addr;
 728
 729         p_hwfn = (struct qed_hwfn *)rdma_cxt;
 730         qz_num = p_hwfn->p_rdma_info->queue_zone_base + qz_offset;
 731         addr = GTT_BAR0_MAP_REG_USDM_RAM +
 732                USTORM_COMMON_QUEUE_CONS_OFFSET(qz_num);
 733
 734         REG_WR16(p_hwfn, addr, prod);
 735
 736         /* keep prod updates ordered */
 737         wmb();
 738 }
 739
 740 static int qed_fill_rdma_dev_info(struct qed_dev *cdev,
 741                                   struct qed_dev_rdma_info *info)
 742 {
 743         memset(info, 0, sizeof(*info));
 744
 745         info->rdma_type = QED_RDMA_TYPE_ROCE;
 746
 747         qed_fill_dev_info(cdev, &info->common);
 748
 749         return 0;
 750 }
 751
 752 static int qed_rdma_get_sb_start(struct qed_dev *cdev)
 753 {
 754         int feat_num;
 755
 756         if (cdev->num_hwfns > 1)
 757                 feat_num = FEAT_NUM(QED_LEADING_HWFN(cdev), QED_PF_L2_QUE);
 758         else
 759                 feat_num = FEAT_NUM(QED_LEADING_HWFN(cdev), QED_PF_L2_QUE) *
 760                            cdev->num_hwfns;
 761
 762         return feat_num;
 763 }
 764
 765 static int qed_rdma_get_min_cnq_msix(struct qed_dev *cdev)
 766 {
 767         int n_cnq = FEAT_NUM(QED_LEADING_HWFN(cdev), QED_RDMA_CNQ);
 768         int n_msix = cdev->int_params.rdma_msix_cnt;
 769
 770         return min_t(int, n_cnq, n_msix);
 771 }
 772
 773 static int qed_rdma_set_int(struct qed_dev *cdev, u16 cnt)
 774 {
 775         int limit = 0;
 776
 777         /* Mark the fastpath as free/used */
 778         cdev->int_params.fp_initialized = cnt ? true : false;
 779
 780         if (cdev->int_params.out.int_mode != QED_INT_MODE_MSIX) {
 781                 DP_ERR(cdev,
 782                        "qed roce supports only MSI-X interrupts (detected %d).\n",
 783                        cdev->int_params.out.int_mode);
 784                 return -EINVAL;
 785         } else if (cdev->int_params.fp_msix_cnt) {
 786                 limit = cdev->int_params.rdma_msix_cnt;
 787         }
 788
 789         if (!limit)
 790                 return -ENOMEM;
 791
 792         return min_t(int, cnt, limit);
 793 }
 794
 795 static int qed_rdma_get_int(struct qed_dev *cdev, struct qed_int_info *info)
 796 {
 797         memset(info, 0, sizeof(*info));
 798
 799         if (!cdev->int_params.fp_initialized) {
 800                 DP_INFO(cdev,
 801                         "Protocol driver requested interrupt information, but its support is not yet configured\n");
 802                 return -EINVAL;
 803         }
 804
 805         if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
 806                 int msix_base = cdev->int_params.rdma_msix_base;
 807
 808                 info->msix_cnt = cdev->int_params.rdma_msix_cnt;
 809                 info->msix = &cdev->int_params.msix_table[msix_base];
 810
 811                 DP_VERBOSE(cdev, QED_MSG_RDMA, "msix_cnt = %d msix_base=%d\n",
 812                            info->msix_cnt, msix_base);
 813         }
 814
 815         return 0;
 816 }
 817
 818 int qed_rdma_alloc_pd(void *rdma_cxt, u16 *pd)
 819 {
 820         struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
 821         u32 returned_id;
 822         int rc;
 823
 824         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Alloc PD\n");
 825
 826         /* Allocates an unused protection domain */
 827         spin_lock_bh(&p_hwfn->p_rdma_info->lock);
 828         rc = qed_rdma_bmap_alloc_id(p_hwfn,
 829                                     &p_hwfn->p_rdma_info->pd_map, &returned_id);
 830         spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
 831
 832         *pd = (u16)returned_id;
 833
 834         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Alloc PD - done, rc = %d\n", rc);
 835         return rc;
 836 }
 837
 838 void qed_rdma_free_pd(void *rdma_cxt, u16 pd)
 839 {
 840         struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
 841
 842         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "pd = %08x\n", pd);
 843
 844         /* Returns a previously allocated protection domain for reuse */
 845         spin_lock_bh(&p_hwfn->p_rdma_info->lock);
 846         qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->pd_map, pd);
 847         spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
 848 }
 849
 850 static enum qed_rdma_toggle_bit
 851 qed_rdma_toggle_bit_create_resize_cq(struct qed_hwfn *p_hwfn, u16 icid)
 852 {
 853         struct qed_rdma_info *p_info = p_hwfn->p_rdma_info;
 854         enum qed_rdma_toggle_bit toggle_bit;
 855         u32 bmap_id;
 856
 857         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", icid);
 858
 859         /* the function toggle the bit that is related to a given icid
 860          * and returns the new toggle bit's value
 861          */
 862         bmap_id = icid - qed_cxt_get_proto_cid_start(p_hwfn, p_info->proto);
 863
 864         spin_lock_bh(&p_info->lock);
 865         toggle_bit = !test_and_change_bit(bmap_id,
 866                                           p_info->toggle_bits.bitmap);
 867         spin_unlock_bh(&p_info->lock);
 868
 869         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "QED_RDMA_TOGGLE_BIT_= %d\n",
 870                    toggle_bit);
 871
 872         return toggle_bit;
 873 }
 874
 875 int qed_rdma_create_cq(void *rdma_cxt,
 876                        struct qed_rdma_create_cq_in_params *params, u16 *icid)
 877 {
 878         struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
 879         struct qed_rdma_info *p_info = p_hwfn->p_rdma_info;
 880         struct rdma_create_cq_ramrod_data *p_ramrod;
 881         enum qed_rdma_toggle_bit toggle_bit;
 882         struct qed_sp_init_data init_data;
 883         struct qed_spq_entry *p_ent;
 884         u32 returned_id, start_cid;
 885         int rc;
 886
 887         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "cq_handle = %08x%08x\n",
 888                    params->cq_handle_hi, params->cq_handle_lo);
 889
 890         /* Allocate icid */
 891         spin_lock_bh(&p_info->lock);
 892         rc = qed_rdma_bmap_alloc_id(p_hwfn,
 893                                     &p_info->cq_map, &returned_id);
 894         spin_unlock_bh(&p_info->lock);
 895
 896         if (rc) {
 897                 DP_NOTICE(p_hwfn, "Can't create CQ, rc = %d\n", rc);
 898                 return rc;
 899         }
 900
 901         start_cid = qed_cxt_get_proto_cid_start(p_hwfn,
 902                                                 p_info->proto);
 903         *icid = returned_id + start_cid;
 904
 905         /* Check if icid requires a page allocation */
 906         rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_CXT, *icid);
 907         if (rc)
 908                 goto err;
 909
 910         /* Get SPQ entry */
 911         memset(&init_data, 0, sizeof(init_data));
 912         init_data.cid = *icid;
 913         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
 914         init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
 915
 916         /* Send create CQ ramrod */
 917         rc = qed_sp_init_request(p_hwfn, &p_ent,
 918                                  RDMA_RAMROD_CREATE_CQ,
 919                                  p_info->proto, &init_data);
 920         if (rc)
 921                 goto err;
 922
 923         p_ramrod = &p_ent->ramrod.rdma_create_cq;
 924
 925         p_ramrod->cq_handle.hi = cpu_to_le32(params->cq_handle_hi);
 926         p_ramrod->cq_handle.lo = cpu_to_le32(params->cq_handle_lo);
 927         p_ramrod->dpi = cpu_to_le16(params->dpi);
 928         p_ramrod->is_two_level_pbl = params->pbl_two_level;
 929         p_ramrod->max_cqes = cpu_to_le32(params->cq_size);
 930         DMA_REGPAIR_LE(p_ramrod->pbl_addr, params->pbl_ptr);
 931         p_ramrod->pbl_num_pages = cpu_to_le16(params->pbl_num_pages);
 932         p_ramrod->cnq_id = (u8)RESC_START(p_hwfn, QED_RDMA_CNQ_RAM) +
 933                            params->cnq_id;
 934         p_ramrod->int_timeout = params->int_timeout;
 935
 936         /* toggle the bit for every resize or create cq for a given icid */
 937         toggle_bit = qed_rdma_toggle_bit_create_resize_cq(p_hwfn, *icid);
 938
 939         p_ramrod->toggle_bit = toggle_bit;
 940
 941         rc = qed_spq_post(p_hwfn, p_ent, NULL);
 942         if (rc) {
 943                 /* restore toggle bit */
 944                 qed_rdma_toggle_bit_create_resize_cq(p_hwfn, *icid);
 945                 goto err;
 946         }
 947
 948         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Created CQ, rc = %d\n", rc);
 949         return rc;
 950
 951 err:
 952         /* release allocated icid */
 953         qed_bmap_release_id(p_hwfn, &p_info->cq_map, returned_id);
 954         DP_NOTICE(p_hwfn, "Create CQ failed, rc = %d\n", rc);
 955
 956         return rc;
 957 }
 958
 959 int qed_rdma_resize_cq(void *rdma_cxt,
 960                        struct qed_rdma_resize_cq_in_params *in_params,
 961                        struct qed_rdma_resize_cq_out_params *out_params)
 962 {
 963         struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
 964         struct rdma_resize_cq_output_params *p_ramrod_res;
 965         struct rdma_resize_cq_ramrod_data *p_ramrod;
 966         enum qed_rdma_toggle_bit toggle_bit;
 967         struct qed_sp_init_data init_data;
 968         struct qed_spq_entry *p_ent;
 969         dma_addr_t ramrod_res_phys;
 970         u8 fw_return_code;
 971         int rc = -ENOMEM;
 972
 973         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", in_params->icid);
 974
 975         p_ramrod_res =
 976             (struct rdma_resize_cq_output_params *)
 977             dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
 978                                sizeof(struct rdma_resize_cq_output_params),
 979                                &ramrod_res_phys, GFP_KERNEL);
 980         if (!p_ramrod_res) {
 981                 DP_NOTICE(p_hwfn,
 982                           "qed resize cq failed: cannot allocate memory (ramrod)\n");
 983                 return rc;
 984         }
 985
 986         /* Get SPQ entry */
 987         memset(&init_data, 0, sizeof(init_data));
 988         init_data.cid = in_params->icid;
 989         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
 990         init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
 991
 992         rc = qed_sp_init_request(p_hwfn, &p_ent,
 993                                  RDMA_RAMROD_RESIZE_CQ,
 994                                  p_hwfn->p_rdma_info->proto, &init_data);
 995         if (rc)
 996                 goto err;
 997
 998         p_ramrod = &p_ent->ramrod.rdma_resize_cq;
 999
1000         p_ramrod->flags = 0;
1001
1002         /* toggle the bit for every resize or create cq for a given icid */
1003         toggle_bit = qed_rdma_toggle_bit_create_resize_cq(p_hwfn,
1004                                                           in_params->icid);
1005
1006         SET_FIELD(p_ramrod->flags,
1007                   RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT, toggle_bit);
1008
1009         SET_FIELD(p_ramrod->flags,
1010                   RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL,
1011                   in_params->pbl_two_level);
1012
1013         p_ramrod->pbl_log_page_size = in_params->pbl_page_size_log - 12;
1014         p_ramrod->pbl_num_pages = cpu_to_le16(in_params->pbl_num_pages);
1015         p_ramrod->max_cqes = cpu_to_le32(in_params->cq_size);
1016         DMA_REGPAIR_LE(p_ramrod->pbl_addr, in_params->pbl_ptr);
1017         DMA_REGPAIR_LE(p_ramrod->output_params_addr, ramrod_res_phys);
1018
1019         rc = qed_spq_post(p_hwfn, p_ent, &fw_return_code);
1020         if (rc)
1021                 goto err;
1022
1023         if (fw_return_code != RDMA_RETURN_OK) {
1024                 DP_NOTICE(p_hwfn, "fw_return_code = %d\n", fw_return_code);
1025                 rc = -EINVAL;
1026                 goto err;
1027         }
1028
1029         out_params->prod = le32_to_cpu(p_ramrod_res->old_cq_prod);
1030         out_params->cons = le32_to_cpu(p_ramrod_res->old_cq_cons);
1031
1032         dma_free_coherent(&p_hwfn->cdev->pdev->dev,
1033                           sizeof(struct rdma_resize_cq_output_params),
1034                           p_ramrod_res, ramrod_res_phys);
1035
1036         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Resized CQ, rc = %d\n", rc);
1037
1038         return rc;
1039
1040 err:    dma_free_coherent(&p_hwfn->cdev->pdev->dev,
1041                           sizeof(struct rdma_resize_cq_output_params),
1042                           p_ramrod_res, ramrod_res_phys);
1043         DP_NOTICE(p_hwfn, "Resized CQ, Failed - rc = %d\n", rc);
1044
1045         return rc;
1046 }
1047
1048 int qed_rdma_destroy_cq(void *rdma_cxt,
1049                         struct qed_rdma_destroy_cq_in_params *in_params,
1050                         struct qed_rdma_destroy_cq_out_params *out_params)
1051 {
1052         struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
1053         struct rdma_destroy_cq_output_params *p_ramrod_res;
1054         struct rdma_destroy_cq_ramrod_data *p_ramrod;
1055         struct qed_sp_init_data init_data;
1056         struct qed_spq_entry *p_ent;
1057         dma_addr_t ramrod_res_phys;
1058         int rc = -ENOMEM;
1059
1060         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", in_params->icid);
1061
1062         p_ramrod_res =
1063             (struct rdma_destroy_cq_output_params *)
1064             dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
1065                                sizeof(struct rdma_destroy_cq_output_params),
1066                                &ramrod_res_phys, GFP_KERNEL);
1067         if (!p_ramrod_res) {
1068                 DP_NOTICE(p_hwfn,
1069                           "qed destroy cq failed: cannot allocate memory (ramrod)\n");
1070                 return rc;
1071         }
1072
1073         /* Get SPQ entry */
1074         memset(&init_data, 0, sizeof(init_data));
1075         init_data.cid = in_params->icid;
1076         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1077         init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1078
1079         /* Send destroy CQ ramrod */
1080         rc = qed_sp_init_request(p_hwfn, &p_ent,
1081                                  RDMA_RAMROD_DESTROY_CQ,
1082                                  p_hwfn->p_rdma_info->proto, &init_data);
1083         if (rc)
1084                 goto err;
1085
1086         p_ramrod = &p_ent->ramrod.rdma_destroy_cq;
1087         DMA_REGPAIR_LE(p_ramrod->output_params_addr, ramrod_res_phys);
1088
1089         rc = qed_spq_post(p_hwfn, p_ent, NULL);
1090         if (rc)
1091                 goto err;
1092
1093         out_params->num_cq_notif = le16_to_cpu(p_ramrod_res->cnq_num);
1094
1095         dma_free_coherent(&p_hwfn->cdev->pdev->dev,
1096                           sizeof(struct rdma_destroy_cq_output_params),
1097                           p_ramrod_res, ramrod_res_phys);
1098
1099         /* Free icid */
1100         spin_lock_bh(&p_hwfn->p_rdma_info->lock);
1101
1102         qed_bmap_release_id(p_hwfn,
1103                             &p_hwfn->p_rdma_info->cq_map,
1104                             (in_params->icid -
1105                              qed_cxt_get_proto_cid_start(p_hwfn,
1106                                                          p_hwfn->
1107                                                          p_rdma_info->proto)));
1108
1109         spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
1110
1111         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Destroyed CQ, rc = %d\n", rc);
1112         return rc;
1113
1114 err:    dma_free_coherent(&p_hwfn->cdev->pdev->dev,
1115                           sizeof(struct rdma_destroy_cq_output_params),
1116                           p_ramrod_res, ramrod_res_phys);
1117
1118         return rc;
1119 }
1120
1121 static void qed_rdma_set_fw_mac(u16 *p_fw_mac, u8 *p_qed_mac)
1122 {
1123         p_fw_mac[0] = cpu_to_le16((p_qed_mac[0] << 8) + p_qed_mac[1]);
1124         p_fw_mac[1] = cpu_to_le16((p_qed_mac[2] << 8) + p_qed_mac[3]);
1125         p_fw_mac[2] = cpu_to_le16((p_qed_mac[4] << 8) + p_qed_mac[5]);
1126 }
1127
1128 static void qed_rdma_copy_gids(struct qed_rdma_qp *qp, __le32 *src_gid,
1129                                __le32 *dst_gid)
1130 {
1131         u32 i;
1132
1133         if (qp->roce_mode == ROCE_V2_IPV4) {
1134                 /* The IPv4 addresses shall be aligned to the highest word.
1135                  * The lower words must be zero.
1136                  */
1137                 memset(src_gid, 0, sizeof(union qed_gid));
1138                 memset(dst_gid, 0, sizeof(union qed_gid));
1139                 src_gid[3] = cpu_to_le32(qp->sgid.ipv4_addr);
1140                 dst_gid[3] = cpu_to_le32(qp->dgid.ipv4_addr);
1141         } else {
1142                 /* GIDs and IPv6 addresses coincide in location and size */
1143                 for (i = 0; i < ARRAY_SIZE(qp->sgid.dwords); i++) {
1144                         src_gid[i] = cpu_to_le32(qp->sgid.dwords[i]);
1145                         dst_gid[i] = cpu_to_le32(qp->dgid.dwords[i]);
1146                 }
1147         }
1148 }
1149
1150 static enum roce_flavor qed_roce_mode_to_flavor(enum roce_mode roce_mode)
1151 {
1152         enum roce_flavor flavor;
1153
1154         switch (roce_mode) {
1155         case ROCE_V1:
1156                 flavor = PLAIN_ROCE;
1157                 break;
1158         case ROCE_V2_IPV4:
1159                 flavor = RROCE_IPV4;
1160                 break;
1161         case ROCE_V2_IPV6:
1162                 flavor = ROCE_V2_IPV6;
1163                 break;
1164         default:
1165                 flavor = MAX_ROCE_MODE;
1166                 break;
1167         }
1168         return flavor;
1169 }
1170
1171 int qed_roce_alloc_cid(struct qed_hwfn *p_hwfn, u16 *cid)
1172 {
1173         struct qed_rdma_info *p_rdma_info = p_hwfn->p_rdma_info;
1174         u32 responder_icid;
1175         u32 requester_icid;
1176         int rc;
1177
1178         spin_lock_bh(&p_hwfn->p_rdma_info->lock);
1179         rc = qed_rdma_bmap_alloc_id(p_hwfn, &p_rdma_info->cid_map,
1180                                     &responder_icid);
1181         if (rc) {
1182                 spin_unlock_bh(&p_rdma_info->lock);
1183                 return rc;
1184         }
1185
1186         rc = qed_rdma_bmap_alloc_id(p_hwfn, &p_rdma_info->cid_map,
1187                                     &requester_icid);
1188
1189         spin_unlock_bh(&p_rdma_info->lock);
1190         if (rc)
1191                 goto err;
1192
1193         /* the two icid's should be adjacent */
1194         if ((requester_icid - responder_icid) != 1) {
1195                 DP_NOTICE(p_hwfn, "Failed to allocate two adjacent qp's'\n");
1196                 rc = -EINVAL;
1197                 goto err;
1198         }
1199
1200         responder_icid += qed_cxt_get_proto_cid_start(p_hwfn,
1201                                                       p_rdma_info->proto);
1202         requester_icid += qed_cxt_get_proto_cid_start(p_hwfn,
1203                                                       p_rdma_info->proto);
1204
1205         /* If these icids require a new ILT line allocate DMA-able context for
1206          * an ILT page
1207          */
1208         rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_CXT, responder_icid);
1209         if (rc)
1210                 goto err;
1211
1212         rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_CXT, requester_icid);
1213         if (rc)
1214                 goto err;
1215
1216         *cid = (u16)responder_icid;
1217         return rc;
1218
1219 err:
1220         spin_lock_bh(&p_rdma_info->lock);
1221         qed_bmap_release_id(p_hwfn, &p_rdma_info->cid_map, responder_icid);
1222         qed_bmap_release_id(p_hwfn, &p_rdma_info->cid_map, requester_icid);
1223
1224         spin_unlock_bh(&p_rdma_info->lock);
1225         DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
1226                    "Allocate CID - failed, rc = %d\n", rc);
1227         return rc;
1228 }
1229
1230 static int qed_roce_sp_create_responder(struct qed_hwfn *p_hwfn,
1231                                         struct qed_rdma_qp *qp)
1232 {
1233         struct roce_create_qp_resp_ramrod_data *p_ramrod;
1234         struct qed_sp_init_data init_data;
1235         union qed_qm_pq_params qm_params;
1236         enum roce_flavor roce_flavor;
1237         struct qed_spq_entry *p_ent;
1238         u16 physical_queue0 = 0;
1239         int rc;
1240
1241         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid);
1242
1243         /* Allocate DMA-able memory for IRQ */
1244         qp->irq_num_pages = 1;
1245         qp->irq = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
1246                                      RDMA_RING_PAGE_SIZE,
1247                                      &qp->irq_phys_addr, GFP_KERNEL);
1248         if (!qp->irq) {
1249                 rc = -ENOMEM;
1250                 DP_NOTICE(p_hwfn,
1251                           "qed create responder failed: cannot allocate memory (irq). rc = %d\n",
1252                           rc);
1253                 return rc;
1254         }
1255
1256         /* Get SPQ entry */
1257         memset(&init_data, 0, sizeof(init_data));
1258         init_data.cid = qp->icid;
1259         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1260         init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1261
1262         rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_CREATE_QP,
1263                                  PROTOCOLID_ROCE, &init_data);
1264         if (rc)
1265                 goto err;
1266
1267         p_ramrod = &p_ent->ramrod.roce_create_qp_resp;
1268
1269         p_ramrod->flags = 0;
1270
1271         roce_flavor = qed_roce_mode_to_flavor(qp->roce_mode);
1272         SET_FIELD(p_ramrod->flags,
1273                   ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR, roce_flavor);
1274
1275         SET_FIELD(p_ramrod->flags,
1276                   ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN,
1277                   qp->incoming_rdma_read_en);
1278
1279         SET_FIELD(p_ramrod->flags,
1280                   ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN,
1281                   qp->incoming_rdma_write_en);
1282
1283         SET_FIELD(p_ramrod->flags,
1284                   ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN,
1285                   qp->incoming_atomic_en);
1286
1287         SET_FIELD(p_ramrod->flags,
1288                   ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN,
1289                   qp->e2e_flow_control_en);
1290
1291         SET_FIELD(p_ramrod->flags,
1292                   ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG, qp->use_srq);
1293
1294         SET_FIELD(p_ramrod->flags,
1295                   ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN,
1296                   qp->fmr_and_reserved_lkey);
1297
1298         SET_FIELD(p_ramrod->flags,
1299                   ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER,
1300                   qp->min_rnr_nak_timer);
1301
1302         p_ramrod->max_ird = qp->max_rd_atomic_resp;
1303         p_ramrod->traffic_class = qp->traffic_class_tos;
1304         p_ramrod->hop_limit = qp->hop_limit_ttl;
1305         p_ramrod->irq_num_pages = qp->irq_num_pages;
1306         p_ramrod->p_key = cpu_to_le16(qp->pkey);
1307         p_ramrod->flow_label = cpu_to_le32(qp->flow_label);
1308         p_ramrod->dst_qp_id = cpu_to_le32(qp->dest_qp);
1309         p_ramrod->mtu = cpu_to_le16(qp->mtu);
1310         p_ramrod->initial_psn = cpu_to_le32(qp->rq_psn);
1311         p_ramrod->pd = cpu_to_le16(qp->pd);
1312         p_ramrod->rq_num_pages = cpu_to_le16(qp->rq_num_pages);
1313         DMA_REGPAIR_LE(p_ramrod->rq_pbl_addr, qp->rq_pbl_ptr);
1314         DMA_REGPAIR_LE(p_ramrod->irq_pbl_addr, qp->irq_phys_addr);
1315         qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid);
1316         p_ramrod->qp_handle_for_async.hi = cpu_to_le32(qp->qp_handle_async.hi);
1317         p_ramrod->qp_handle_for_async.lo = cpu_to_le32(qp->qp_handle_async.lo);
1318         p_ramrod->qp_handle_for_cqe.hi = cpu_to_le32(qp->qp_handle.hi);
1319         p_ramrod->qp_handle_for_cqe.lo = cpu_to_le32(qp->qp_handle.lo);
1320         p_ramrod->stats_counter_id = p_hwfn->rel_pf_id;
1321         p_ramrod->cq_cid = cpu_to_le32((p_hwfn->hw_info.opaque_fid << 16) |
1322                                        qp->rq_cq_id);
1323
1324         memset(&qm_params, 0, sizeof(qm_params));
1325         qm_params.roce.qpid = qp->icid >> 1;
1326         physical_queue0 = qed_get_qm_pq(p_hwfn, PROTOCOLID_ROCE, &qm_params);
1327
1328         p_ramrod->physical_queue0 = cpu_to_le16(physical_queue0);
1329         p_ramrod->dpi = cpu_to_le16(qp->dpi);
1330
1331         qed_rdma_set_fw_mac(p_ramrod->remote_mac_addr, qp->remote_mac_addr);
1332         qed_rdma_set_fw_mac(p_ramrod->local_mac_addr, qp->local_mac_addr);
1333
1334         p_ramrod->udp_src_port = qp->udp_src_port;
1335         p_ramrod->vlan_id = cpu_to_le16(qp->vlan_id);
1336         p_ramrod->srq_id.srq_idx = cpu_to_le16(qp->srq_id);
1337         p_ramrod->srq_id.opaque_fid = cpu_to_le16(p_hwfn->hw_info.opaque_fid);
1338
1339         p_ramrod->stats_counter_id = RESC_START(p_hwfn, QED_RDMA_STATS_QUEUE) +
1340                                      qp->stats_queue;
1341
1342         rc = qed_spq_post(p_hwfn, p_ent, NULL);
1343
1344         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d physical_queue0 = 0x%x\n",
1345                    rc, physical_queue0);
1346
1347         if (rc)
1348                 goto err;
1349
1350         qp->resp_offloaded = true;
1351
1352         return rc;
1353
1354 err:
1355         DP_NOTICE(p_hwfn, "create responder - failed, rc = %d\n", rc);
1356         dma_free_coherent(&p_hwfn->cdev->pdev->dev,
1357                           qp->irq_num_pages * RDMA_RING_PAGE_SIZE,
1358                           qp->irq, qp->irq_phys_addr);
1359
1360         return rc;
1361 }
1362
1363 static int qed_roce_sp_create_requester(struct qed_hwfn *p_hwfn,
1364                                         struct qed_rdma_qp *qp)
1365 {
1366         struct roce_create_qp_req_ramrod_data *p_ramrod;
1367         struct qed_sp_init_data init_data;
1368         union qed_qm_pq_params qm_params;
1369         enum roce_flavor roce_flavor;
1370         struct qed_spq_entry *p_ent;
1371         u16 physical_queue0 = 0;
1372         int rc;
1373
1374         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid);
1375
1376         /* Allocate DMA-able memory for ORQ */
1377         qp->orq_num_pages = 1;
1378         qp->orq = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
1379                                      RDMA_RING_PAGE_SIZE,
1380                                      &qp->orq_phys_addr, GFP_KERNEL);
1381         if (!qp->orq) {
1382                 rc = -ENOMEM;
1383                 DP_NOTICE(p_hwfn,
1384                           "qed create requester failed: cannot allocate memory (orq). rc = %d\n",
1385                           rc);
1386                 return rc;
1387         }
1388
1389         /* Get SPQ entry */
1390         memset(&init_data, 0, sizeof(init_data));
1391         init_data.cid = qp->icid + 1;
1392         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1393         init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1394
1395         rc = qed_sp_init_request(p_hwfn, &p_ent,
1396                                  ROCE_RAMROD_CREATE_QP,
1397                                  PROTOCOLID_ROCE, &init_data);
1398         if (rc)
1399                 goto err;
1400
1401         p_ramrod = &p_ent->ramrod.roce_create_qp_req;
1402
1403         p_ramrod->flags = 0;
1404
1405         roce_flavor = qed_roce_mode_to_flavor(qp->roce_mode);
1406         SET_FIELD(p_ramrod->flags,
1407                   ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR, roce_flavor);
1408
1409         SET_FIELD(p_ramrod->flags,
1410                   ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN,
1411                   qp->fmr_and_reserved_lkey);
1412
1413         SET_FIELD(p_ramrod->flags,
1414                   ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP, qp->signal_all);
1415
1416         SET_FIELD(p_ramrod->flags,
1417                   ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT, qp->retry_cnt);
1418
1419         SET_FIELD(p_ramrod->flags,
1420                   ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT,
1421                   qp->rnr_retry_cnt);
1422
1423         p_ramrod->max_ord = qp->max_rd_atomic_req;
1424         p_ramrod->traffic_class = qp->traffic_class_tos;
1425         p_ramrod->hop_limit = qp->hop_limit_ttl;
1426         p_ramrod->orq_num_pages = qp->orq_num_pages;
1427         p_ramrod->p_key = cpu_to_le16(qp->pkey);
1428         p_ramrod->flow_label = cpu_to_le32(qp->flow_label);
1429         p_ramrod->dst_qp_id = cpu_to_le32(qp->dest_qp);
1430         p_ramrod->ack_timeout_val = cpu_to_le32(qp->ack_timeout);
1431         p_ramrod->mtu = cpu_to_le16(qp->mtu);
1432         p_ramrod->initial_psn = cpu_to_le32(qp->sq_psn);
1433         p_ramrod->pd = cpu_to_le16(qp->pd);
1434         p_ramrod->sq_num_pages = cpu_to_le16(qp->sq_num_pages);
1435         DMA_REGPAIR_LE(p_ramrod->sq_pbl_addr, qp->sq_pbl_ptr);
1436         DMA_REGPAIR_LE(p_ramrod->orq_pbl_addr, qp->orq_phys_addr);
1437         qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid);
1438         p_ramrod->qp_handle_for_async.hi = cpu_to_le32(qp->qp_handle_async.hi);
1439         p_ramrod->qp_handle_for_async.lo = cpu_to_le32(qp->qp_handle_async.lo);
1440         p_ramrod->qp_handle_for_cqe.hi = cpu_to_le32(qp->qp_handle.hi);
1441         p_ramrod->qp_handle_for_cqe.lo = cpu_to_le32(qp->qp_handle.lo);
1442         p_ramrod->stats_counter_id = p_hwfn->rel_pf_id;
1443         p_ramrod->cq_cid = cpu_to_le32((p_hwfn->hw_info.opaque_fid << 16) |
1444                                        qp->sq_cq_id);
1445
1446         memset(&qm_params, 0, sizeof(qm_params));
1447         qm_params.roce.qpid = qp->icid >> 1;
1448         physical_queue0 = qed_get_qm_pq(p_hwfn, PROTOCOLID_ROCE, &qm_params);
1449
1450         p_ramrod->physical_queue0 = cpu_to_le16(physical_queue0);
1451         p_ramrod->dpi = cpu_to_le16(qp->dpi);
1452
1453         qed_rdma_set_fw_mac(p_ramrod->remote_mac_addr, qp->remote_mac_addr);
1454         qed_rdma_set_fw_mac(p_ramrod->local_mac_addr, qp->local_mac_addr);
1455
1456         p_ramrod->udp_src_port = qp->udp_src_port;
1457         p_ramrod->vlan_id = cpu_to_le16(qp->vlan_id);
1458         p_ramrod->stats_counter_id = RESC_START(p_hwfn, QED_RDMA_STATS_QUEUE) +
1459                                      qp->stats_queue;
1460
1461         rc = qed_spq_post(p_hwfn, p_ent, NULL);
1462
1463         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc);
1464
1465         if (rc)
1466                 goto err;
1467
1468         qp->req_offloaded = true;
1469
1470         return rc;
1471
1472 err:
1473         DP_NOTICE(p_hwfn, "Create requested - failed, rc = %d\n", rc);
1474         dma_free_coherent(&p_hwfn->cdev->pdev->dev,
1475                           qp->orq_num_pages * RDMA_RING_PAGE_SIZE,
1476                           qp->orq, qp->orq_phys_addr);
1477         return rc;
1478 }
1479
1480 static int qed_roce_sp_modify_responder(struct qed_hwfn *p_hwfn,
1481                                         struct qed_rdma_qp *qp,
1482                                         bool move_to_err, u32 modify_flags)
1483 {
1484         struct roce_modify_qp_resp_ramrod_data *p_ramrod;
1485         struct qed_sp_init_data init_data;
1486         struct qed_spq_entry *p_ent;
1487         int rc;
1488
1489         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid);
1490
1491         if (move_to_err && !qp->resp_offloaded)
1492                 return 0;
1493
1494         /* Get SPQ entry */
1495         memset(&init_data, 0, sizeof(init_data));
1496         init_data.cid = qp->icid;
1497         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1498         init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1499
1500         rc = qed_sp_init_request(p_hwfn, &p_ent,
1501                                  ROCE_EVENT_MODIFY_QP,
1502                                  PROTOCOLID_ROCE, &init_data);
1503         if (rc) {
1504                 DP_NOTICE(p_hwfn, "rc = %d\n", rc);
1505                 return rc;
1506         }
1507
1508         p_ramrod = &p_ent->ramrod.roce_modify_qp_resp;
1509
1510         p_ramrod->flags = 0;
1511
1512         SET_FIELD(p_ramrod->flags,
1513                   ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG, move_to_err);
1514
1515         SET_FIELD(p_ramrod->flags,
1516                   ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN,
1517                   qp->incoming_rdma_read_en);
1518
1519         SET_FIELD(p_ramrod->flags,
1520                   ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN,
1521                   qp->incoming_rdma_write_en);
1522
1523         SET_FIELD(p_ramrod->flags,
1524                   ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN,
1525                   qp->incoming_atomic_en);
1526
1527         SET_FIELD(p_ramrod->flags,
1528                   ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN,
1529                   qp->e2e_flow_control_en);
1530
1531         SET_FIELD(p_ramrod->flags,
1532                   ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG,
1533                   GET_FIELD(modify_flags,
1534                             QED_RDMA_MODIFY_QP_VALID_RDMA_OPS_EN));
1535
1536         SET_FIELD(p_ramrod->flags,
1537                   ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG,
1538                   GET_FIELD(modify_flags, QED_ROCE_MODIFY_QP_VALID_PKEY));
1539
1540         SET_FIELD(p_ramrod->flags,
1541                   ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG,
1542                   GET_FIELD(modify_flags,
1543                             QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR));
1544
1545         SET_FIELD(p_ramrod->flags,
1546                   ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG,
1547                   GET_FIELD(modify_flags,
1548                             QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_RESP));
1549
1550         SET_FIELD(p_ramrod->flags,
1551                   ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG,
1552                   GET_FIELD(modify_flags,
1553                             QED_ROCE_MODIFY_QP_VALID_MIN_RNR_NAK_TIMER));
1554
1555         p_ramrod->fields = 0;
1556         SET_FIELD(p_ramrod->fields,
1557                   ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER,
1558                   qp->min_rnr_nak_timer);
1559
1560         p_ramrod->max_ird = qp->max_rd_atomic_resp;
1561         p_ramrod->traffic_class = qp->traffic_class_tos;
1562         p_ramrod->hop_limit = qp->hop_limit_ttl;
1563         p_ramrod->p_key = cpu_to_le16(qp->pkey);
1564         p_ramrod->flow_label = cpu_to_le32(qp->flow_label);
1565         p_ramrod->mtu = cpu_to_le16(qp->mtu);
1566         qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid);
1567         rc = qed_spq_post(p_hwfn, p_ent, NULL);
1568
1569         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Modify responder, rc = %d\n", rc);
1570         return rc;
1571 }
1572
1573 static int qed_roce_sp_modify_requester(struct qed_hwfn *p_hwfn,
1574                                         struct qed_rdma_qp *qp,
1575                                         bool move_to_sqd,
1576                                         bool move_to_err, u32 modify_flags)
1577 {
1578         struct roce_modify_qp_req_ramrod_data *p_ramrod;
1579         struct qed_sp_init_data init_data;
1580         struct qed_spq_entry *p_ent;
1581         int rc;
1582
1583         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid);
1584
1585         if (move_to_err && !(qp->req_offloaded))
1586                 return 0;
1587
1588         /* Get SPQ entry */
1589         memset(&init_data, 0, sizeof(init_data));
1590         init_data.cid = qp->icid + 1;
1591         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1592         init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1593
1594         rc = qed_sp_init_request(p_hwfn, &p_ent,
1595                                  ROCE_EVENT_MODIFY_QP,
1596                                  PROTOCOLID_ROCE, &init_data);
1597         if (rc) {
1598                 DP_NOTICE(p_hwfn, "rc = %d\n", rc);
1599                 return rc;
1600         }
1601
1602         p_ramrod = &p_ent->ramrod.roce_modify_qp_req;
1603
1604         p_ramrod->flags = 0;
1605
1606         SET_FIELD(p_ramrod->flags,
1607                   ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG, move_to_err);
1608
1609         SET_FIELD(p_ramrod->flags,
1610                   ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG, move_to_sqd);
1611
1612         SET_FIELD(p_ramrod->flags,
1613                   ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY,
1614                   qp->sqd_async);
1615
1616         SET_FIELD(p_ramrod->flags,
1617                   ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG,
1618                   GET_FIELD(modify_flags, QED_ROCE_MODIFY_QP_VALID_PKEY));
1619
1620         SET_FIELD(p_ramrod->flags,
1621                   ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG,
1622                   GET_FIELD(modify_flags,
1623                             QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR));
1624
1625         SET_FIELD(p_ramrod->flags,
1626                   ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG,
1627                   GET_FIELD(modify_flags,
1628                             QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_REQ));
1629
1630         SET_FIELD(p_ramrod->flags,
1631                   ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG,
1632                   GET_FIELD(modify_flags,
1633                             QED_ROCE_MODIFY_QP_VALID_RNR_RETRY_CNT));
1634
1635         SET_FIELD(p_ramrod->flags,
1636                   ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG,
1637                   GET_FIELD(modify_flags, QED_ROCE_MODIFY_QP_VALID_RETRY_CNT));
1638
1639         SET_FIELD(p_ramrod->flags,
1640                   ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG,
1641                   GET_FIELD(modify_flags,
1642                             QED_ROCE_MODIFY_QP_VALID_ACK_TIMEOUT));
1643
1644         p_ramrod->fields = 0;
1645         SET_FIELD(p_ramrod->fields,
1646                   ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT, qp->retry_cnt);
1647
1648         SET_FIELD(p_ramrod->fields,
1649                   ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT,
1650                   qp->rnr_retry_cnt);
1651
1652         p_ramrod->max_ord = qp->max_rd_atomic_req;
1653         p_ramrod->traffic_class = qp->traffic_class_tos;
1654         p_ramrod->hop_limit = qp->hop_limit_ttl;
1655         p_ramrod->p_key = cpu_to_le16(qp->pkey);
1656         p_ramrod->flow_label = cpu_to_le32(qp->flow_label);
1657         p_ramrod->ack_timeout_val = cpu_to_le32(qp->ack_timeout);
1658         p_ramrod->mtu = cpu_to_le16(qp->mtu);
1659         qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid);
1660         rc = qed_spq_post(p_hwfn, p_ent, NULL);
1661
1662         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Modify requester, rc = %d\n", rc);
1663         return rc;
1664 }
1665
1666 static int qed_roce_sp_destroy_qp_responder(struct qed_hwfn *p_hwfn,
1667                                             struct qed_rdma_qp *qp,
1668                                             u32 *num_invalidated_mw)
1669 {
1670         struct roce_destroy_qp_resp_output_params *p_ramrod_res;
1671         struct roce_destroy_qp_resp_ramrod_data *p_ramrod;
1672         struct qed_sp_init_data init_data;
1673         struct qed_spq_entry *p_ent;
1674         dma_addr_t ramrod_res_phys;
1675         int rc;
1676
1677         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid);
1678
1679         if (!qp->resp_offloaded)
1680                 return 0;
1681
1682         /* Get SPQ entry */
1683         memset(&init_data, 0, sizeof(init_data));
1684         init_data.cid = qp->icid;
1685         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1686         init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1687
1688         rc = qed_sp_init_request(p_hwfn, &p_ent,
1689                                  ROCE_RAMROD_DESTROY_QP,
1690                                  PROTOCOLID_ROCE, &init_data);
1691         if (rc)
1692                 return rc;
1693
1694         p_ramrod = &p_ent->ramrod.roce_destroy_qp_resp;
1695
1696         p_ramrod_res = (struct roce_destroy_qp_resp_output_params *)
1697             dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_ramrod_res),
1698                                &ramrod_res_phys, GFP_KERNEL);
1699
1700         if (!p_ramrod_res) {
1701                 rc = -ENOMEM;
1702                 DP_NOTICE(p_hwfn,
1703                           "qed destroy responder failed: cannot allocate memory (ramrod). rc = %d\n",
1704                           rc);
1705                 return rc;
1706         }
1707
1708         DMA_REGPAIR_LE(p_ramrod->output_params_addr, ramrod_res_phys);
1709
1710         rc = qed_spq_post(p_hwfn, p_ent, NULL);
1711         if (rc)
1712                 goto err;
1713
1714         *num_invalidated_mw = le32_to_cpu(p_ramrod_res->num_invalidated_mw);
1715
1716         /* Free IRQ - only if ramrod succeeded, in case FW is still using it */
1717         dma_free_coherent(&p_hwfn->cdev->pdev->dev,
1718                           qp->irq_num_pages * RDMA_RING_PAGE_SIZE,
1719                           qp->irq, qp->irq_phys_addr);
1720
1721         qp->resp_offloaded = false;
1722
1723         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Destroy responder, rc = %d\n", rc);
1724
1725 err:
1726         dma_free_coherent(&p_hwfn->cdev->pdev->dev,
1727                           sizeof(struct roce_destroy_qp_resp_output_params),
1728                           p_ramrod_res, ramrod_res_phys);
1729
1730         return rc;
1731 }
1732
1733 static int qed_roce_sp_destroy_qp_requester(struct qed_hwfn *p_hwfn,
1734                                             struct qed_rdma_qp *qp,
1735                                             u32 *num_bound_mw)
1736 {
1737         struct roce_destroy_qp_req_output_params *p_ramrod_res;
1738         struct roce_destroy_qp_req_ramrod_data *p_ramrod;
1739         struct qed_sp_init_data init_data;
1740         struct qed_spq_entry *p_ent;
1741         dma_addr_t ramrod_res_phys;
1742         int rc = -ENOMEM;
1743
1744         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid);
1745
1746         if (!qp->req_offloaded)
1747                 return 0;
1748
1749         p_ramrod_res = (struct roce_destroy_qp_req_output_params *)
1750                        dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
1751                                           sizeof(*p_ramrod_res),
1752                                           &ramrod_res_phys, GFP_KERNEL);
1753         if (!p_ramrod_res) {
1754                 DP_NOTICE(p_hwfn,
1755                           "qed destroy requester failed: cannot allocate memory (ramrod)\n");
1756                 return rc;
1757         }
1758
1759         /* Get SPQ entry */
1760         memset(&init_data, 0, sizeof(init_data));
1761         init_data.cid = qp->icid + 1;
1762         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1763         init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1764
1765         rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_DESTROY_QP,
1766                                  PROTOCOLID_ROCE, &init_data);
1767         if (rc)
1768                 goto err;
1769
1770         p_ramrod = &p_ent->ramrod.roce_destroy_qp_req;
1771         DMA_REGPAIR_LE(p_ramrod->output_params_addr, ramrod_res_phys);
1772
1773         rc = qed_spq_post(p_hwfn, p_ent, NULL);
1774         if (rc)
1775                 goto err;
1776
1777         *num_bound_mw = le32_to_cpu(p_ramrod_res->num_bound_mw);
1778
1779         /* Free ORQ - only if ramrod succeeded, in case FW is still using it */
1780         dma_free_coherent(&p_hwfn->cdev->pdev->dev,
1781                           qp->orq_num_pages * RDMA_RING_PAGE_SIZE,
1782                           qp->orq, qp->orq_phys_addr);
1783
1784         qp->req_offloaded = false;
1785
1786         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Destroy requester, rc = %d\n", rc);
1787
1788 err:
1789         dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_ramrod_res),
1790                           p_ramrod_res, ramrod_res_phys);
1791
1792         return rc;
1793 }
1794
1795 int qed_roce_query_qp(struct qed_hwfn *p_hwfn,
1796                       struct qed_rdma_qp *qp,
1797                       struct qed_rdma_query_qp_out_params *out_params)
1798 {
1799         struct roce_query_qp_resp_output_params *p_resp_ramrod_res;
1800         struct roce_query_qp_req_output_params *p_req_ramrod_res;
1801         struct roce_query_qp_resp_ramrod_data *p_resp_ramrod;
1802         struct roce_query_qp_req_ramrod_data *p_req_ramrod;
1803         struct qed_sp_init_data init_data;
1804         dma_addr_t resp_ramrod_res_phys;
1805         dma_addr_t req_ramrod_res_phys;
1806         struct qed_spq_entry *p_ent;
1807         bool rq_err_state;
1808         bool sq_err_state;
1809         bool sq_draining;
1810         int rc = -ENOMEM;
1811
1812         if ((!(qp->resp_offloaded)) && (!(qp->req_offloaded))) {
1813                 /* We can't send ramrod to the fw since this qp wasn't offloaded
1814                  * to the fw yet
1815                  */
1816                 out_params->draining = false;
1817                 out_params->rq_psn = qp->rq_psn;
1818                 out_params->sq_psn = qp->sq_psn;
1819                 out_params->state = qp->cur_state;
1820
1821                 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "No QPs as no offload\n");
1822                 return 0;
1823         }
1824
1825         if (!(qp->resp_offloaded)) {
1826                 DP_NOTICE(p_hwfn,
1827                           "The responder's qp should be offloded before requester's\n");
1828                 return -EINVAL;
1829         }
1830
1831         /* Send a query responder ramrod to FW to get RQ-PSN and state */
1832         p_resp_ramrod_res = (struct roce_query_qp_resp_output_params *)
1833             dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
1834                                sizeof(*p_resp_ramrod_res),
1835                                &resp_ramrod_res_phys, GFP_KERNEL);
1836         if (!p_resp_ramrod_res) {
1837                 DP_NOTICE(p_hwfn,
1838                           "qed query qp failed: cannot allocate memory (ramrod)\n");
1839                 return rc;
1840         }
1841
1842         /* Get SPQ entry */
1843         memset(&init_data, 0, sizeof(init_data));
1844         init_data.cid = qp->icid;
1845         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1846         init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1847         rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_QUERY_QP,
1848                                  PROTOCOLID_ROCE, &init_data);
1849         if (rc)
1850                 goto err_resp;
1851
1852         p_resp_ramrod = &p_ent->ramrod.roce_query_qp_resp;
1853         DMA_REGPAIR_LE(p_resp_ramrod->output_params_addr, resp_ramrod_res_phys);
1854
1855         rc = qed_spq_post(p_hwfn, p_ent, NULL);
1856         if (rc)
1857                 goto err_resp;
1858
1859         dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_resp_ramrod_res),
1860                           p_resp_ramrod_res, resp_ramrod_res_phys);
1861
1862         out_params->rq_psn = le32_to_cpu(p_resp_ramrod_res->psn);
1863         rq_err_state = GET_FIELD(le32_to_cpu(p_resp_ramrod_res->err_flag),
1864                                  ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG);
1865
1866         if (!(qp->req_offloaded)) {
1867                 /* Don't send query qp for the requester */
1868                 out_params->sq_psn = qp->sq_psn;
1869                 out_params->draining = false;
1870
1871                 if (rq_err_state)
1872                         qp->cur_state = QED_ROCE_QP_STATE_ERR;
1873
1874                 out_params->state = qp->cur_state;
1875
1876                 return 0;
1877         }
1878
1879         /* Send a query requester ramrod to FW to get SQ-PSN and state */
1880         p_req_ramrod_res = (struct roce_query_qp_req_output_params *)
1881                            dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
1882                                               sizeof(*p_req_ramrod_res),
1883                                               &req_ramrod_res_phys,
1884                                               GFP_KERNEL);
1885         if (!p_req_ramrod_res) {
1886                 rc = -ENOMEM;
1887                 DP_NOTICE(p_hwfn,
1888                           "qed query qp failed: cannot allocate memory (ramrod)\n");
1889                 return rc;
1890         }
1891
1892         /* Get SPQ entry */
1893         init_data.cid = qp->icid + 1;
1894         rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_QUERY_QP,
1895                                  PROTOCOLID_ROCE, &init_data);
1896         if (rc)
1897                 goto err_req;
1898
1899         p_req_ramrod = &p_ent->ramrod.roce_query_qp_req;
1900         DMA_REGPAIR_LE(p_req_ramrod->output_params_addr, req_ramrod_res_phys);
1901
1902         rc = qed_spq_post(p_hwfn, p_ent, NULL);
1903         if (rc)
1904                 goto err_req;
1905
1906         dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_req_ramrod_res),
1907                           p_req_ramrod_res, req_ramrod_res_phys);
1908
1909         out_params->sq_psn = le32_to_cpu(p_req_ramrod_res->psn);
1910         sq_err_state = GET_FIELD(le32_to_cpu(p_req_ramrod_res->flags),
1911                                  ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG);
1912         sq_draining =
1913                 GET_FIELD(le32_to_cpu(p_req_ramrod_res->flags),
1914                           ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG);
1915
1916         out_params->draining = false;
1917
1918         if (rq_err_state)
1919                 qp->cur_state = QED_ROCE_QP_STATE_ERR;
1920         else if (sq_err_state)
1921                 qp->cur_state = QED_ROCE_QP_STATE_SQE;
1922         else if (sq_draining)
1923                 out_params->draining = true;
1924         out_params->state = qp->cur_state;
1925
1926         return 0;
1927
1928 err_req:
1929         dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_req_ramrod_res),
1930                           p_req_ramrod_res, req_ramrod_res_phys);
1931         return rc;
1932 err_resp:
1933         dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_resp_ramrod_res),
1934                           p_resp_ramrod_res, resp_ramrod_res_phys);
1935         return rc;
1936 }
1937
1938 int qed_roce_destroy_qp(struct qed_hwfn *p_hwfn, struct qed_rdma_qp *qp)
1939 {
1940         u32 num_invalidated_mw = 0;
1941         u32 num_bound_mw = 0;
1942         u32 start_cid;
1943         int rc;
1944
1945         /* Destroys the specified QP */
1946         if ((qp->cur_state != QED_ROCE_QP_STATE_RESET) &&
1947             (qp->cur_state != QED_ROCE_QP_STATE_ERR) &&
1948             (qp->cur_state != QED_ROCE_QP_STATE_INIT)) {
1949                 DP_NOTICE(p_hwfn,
1950                           "QP must be in error, reset or init state before destroying it\n");
1951                 return -EINVAL;
1952         }
1953
1954         rc = qed_roce_sp_destroy_qp_responder(p_hwfn, qp, &num_invalidated_mw);
1955         if (rc)
1956                 return rc;
1957
1958         /* Send destroy requester ramrod */
1959         rc = qed_roce_sp_destroy_qp_requester(p_hwfn, qp, &num_bound_mw);
1960         if (rc)
1961                 return rc;
1962
1963         if (num_invalidated_mw != num_bound_mw) {
1964                 DP_NOTICE(p_hwfn,
1965                           "number of invalidate memory windows is different from bounded ones\n");
1966                 return -EINVAL;
1967         }
1968
1969         spin_lock_bh(&p_hwfn->p_rdma_info->lock);
1970
1971         start_cid = qed_cxt_get_proto_cid_start(p_hwfn,
1972                                                 p_hwfn->p_rdma_info->proto);
1973
1974         /* Release responder's icid */
1975         qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->cid_map,
1976                             qp->icid - start_cid);
1977
1978         /* Release requester's icid */
1979         qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->cid_map,
1980                             qp->icid + 1 - start_cid);
1981
1982         spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
1983
1984         return 0;
1985 }
1986
1987 int qed_rdma_query_qp(void *rdma_cxt,
1988                       struct qed_rdma_qp *qp,
1989                       struct qed_rdma_query_qp_out_params *out_params)
1990 {
1991         struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
1992         int rc;
1993
1994         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid);
1995
1996         /* The following fields are filled in from qp and not FW as they can't
1997          * be modified by FW
1998          */
1999         out_params->mtu = qp->mtu;
2000         out_params->dest_qp = qp->dest_qp;
2001         out_params->incoming_atomic_en = qp->incoming_atomic_en;
2002         out_params->e2e_flow_control_en = qp->e2e_flow_control_en;
2003         out_params->incoming_rdma_read_en = qp->incoming_rdma_read_en;
2004         out_params->incoming_rdma_write_en = qp->incoming_rdma_write_en;
2005         out_params->dgid = qp->dgid;
2006         out_params->flow_label = qp->flow_label;
2007         out_params->hop_limit_ttl = qp->hop_limit_ttl;
2008         out_params->traffic_class_tos = qp->traffic_class_tos;
2009         out_params->timeout = qp->ack_timeout;
2010         out_params->rnr_retry = qp->rnr_retry_cnt;
2011         out_params->retry_cnt = qp->retry_cnt;
2012         out_params->min_rnr_nak_timer = qp->min_rnr_nak_timer;
2013         out_params->pkey_index = 0;
2014         out_params->max_rd_atomic = qp->max_rd_atomic_req;
2015         out_params->max_dest_rd_atomic = qp->max_rd_atomic_resp;
2016         out_params->sqd_async = qp->sqd_async;
2017
2018         rc = qed_roce_query_qp(p_hwfn, qp, out_params);
2019
2020         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Query QP, rc = %d\n", rc);
2021         return rc;
2022 }
2023
2024 int qed_rdma_destroy_qp(void *rdma_cxt, struct qed_rdma_qp *qp)
2025 {
2026         struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
2027         int rc = 0;
2028
2029         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid);
2030
2031         rc = qed_roce_destroy_qp(p_hwfn, qp);
2032
2033         /* free qp params struct */
2034         kfree(qp);
2035
2036         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "QP destroyed\n");
2037         return rc;
2038 }
2039
2040 struct qed_rdma_qp *
2041 qed_rdma_create_qp(void *rdma_cxt,
2042                    struct qed_rdma_create_qp_in_params *in_params,
2043                    struct qed_rdma_create_qp_out_params *out_params)
2044 {
2045         struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
2046         struct qed_rdma_qp *qp;
2047         u8 max_stats_queues;
2048         int rc;
2049
2050         if (!rdma_cxt || !in_params || !out_params || !p_hwfn->p_rdma_info) {
2051                 DP_ERR(p_hwfn->cdev,
2052                        "qed roce create qp failed due to NULL entry (rdma_cxt=%p, in=%p, out=%p, roce_info=?\n",
2053                        rdma_cxt, in_params, out_params);
2054                 return NULL;
2055         }
2056
2057         DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
2058                    "qed rdma create qp called with qp_handle = %08x%08x\n",
2059                    in_params->qp_handle_hi, in_params->qp_handle_lo);
2060
2061         /* Some sanity checks... */
2062         max_stats_queues = p_hwfn->p_rdma_info->dev->max_stats_queues;
2063         if (in_params->stats_queue >= max_stats_queues) {
2064                 DP_ERR(p_hwfn->cdev,
2065                        "qed rdma create qp failed due to invalid statistics queue %d. maximum is %d\n",
2066                        in_params->stats_queue, max_stats_queues);
2067                 return NULL;
2068         }
2069
2070         qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2071         if (!qp) {
2072                 DP_NOTICE(p_hwfn, "Failed to allocate qed_rdma_qp\n");
2073                 return NULL;
2074         }
2075
2076         rc = qed_roce_alloc_cid(p_hwfn, &qp->icid);
2077         qp->qpid = ((0xFF << 16) | qp->icid);
2078
2079         DP_INFO(p_hwfn, "ROCE qpid=%x\n", qp->qpid);
2080
2081         if (rc) {
2082                 kfree(qp);
2083                 return NULL;
2084         }
2085
2086         qp->cur_state = QED_ROCE_QP_STATE_RESET;
2087         qp->qp_handle.hi = cpu_to_le32(in_params->qp_handle_hi);
2088         qp->qp_handle.lo = cpu_to_le32(in_params->qp_handle_lo);
2089         qp->qp_handle_async.hi = cpu_to_le32(in_params->qp_handle_async_hi);
2090         qp->qp_handle_async.lo = cpu_to_le32(in_params->qp_handle_async_lo);
2091         qp->use_srq = in_params->use_srq;
2092         qp->signal_all = in_params->signal_all;
2093         qp->fmr_and_reserved_lkey = in_params->fmr_and_reserved_lkey;
2094         qp->pd = in_params->pd;
2095         qp->dpi = in_params->dpi;
2096         qp->sq_cq_id = in_params->sq_cq_id;
2097         qp->sq_num_pages = in_params->sq_num_pages;
2098         qp->sq_pbl_ptr = in_params->sq_pbl_ptr;
2099         qp->rq_cq_id = in_params->rq_cq_id;
2100         qp->rq_num_pages = in_params->rq_num_pages;
2101         qp->rq_pbl_ptr = in_params->rq_pbl_ptr;
2102         qp->srq_id = in_params->srq_id;
2103         qp->req_offloaded = false;
2104         qp->resp_offloaded = false;
2105         qp->e2e_flow_control_en = qp->use_srq ? false : true;
2106         qp->stats_queue = in_params->stats_queue;
2107
2108         out_params->icid = qp->icid;
2109         out_params->qp_id = qp->qpid;
2110
2111         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Create QP, rc = %d\n", rc);
2112         return qp;
2113 }
2114
2115 static int qed_roce_modify_qp(struct qed_hwfn *p_hwfn,
2116                               struct qed_rdma_qp *qp,
2117                               enum qed_roce_qp_state prev_state,
2118                               struct qed_rdma_modify_qp_in_params *params)
2119 {
2120         u32 num_invalidated_mw = 0, num_bound_mw = 0;
2121         int rc = 0;
2122
2123         /* Perform additional operations according to the current state and the
2124          * next state
2125          */
2126         if (((prev_state == QED_ROCE_QP_STATE_INIT) ||
2127              (prev_state == QED_ROCE_QP_STATE_RESET)) &&
2128             (qp->cur_state == QED_ROCE_QP_STATE_RTR)) {
2129                 /* Init->RTR or Reset->RTR */
2130                 rc = qed_roce_sp_create_responder(p_hwfn, qp);
2131                 return rc;
2132         } else if ((prev_state == QED_ROCE_QP_STATE_RTR) &&
2133                    (qp->cur_state == QED_ROCE_QP_STATE_RTS)) {
2134                 /* RTR-> RTS */
2135                 rc = qed_roce_sp_create_requester(p_hwfn, qp);
2136                 if (rc)
2137                         return rc;
2138
2139                 /* Send modify responder ramrod */
2140                 rc = qed_roce_sp_modify_responder(p_hwfn, qp, false,
2141                                                   params->modify_flags);
2142                 return rc;
2143         } else if ((prev_state == QED_ROCE_QP_STATE_RTS) &&
2144                    (qp->cur_state == QED_ROCE_QP_STATE_RTS)) {
2145                 /* RTS->RTS */
2146                 rc = qed_roce_sp_modify_responder(p_hwfn, qp, false,
2147                                                   params->modify_flags);
2148                 if (rc)
2149                         return rc;
2150
2151                 rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, false,
2152                                                   params->modify_flags);
2153                 return rc;
2154         } else if ((prev_state == QED_ROCE_QP_STATE_RTS) &&
2155                    (qp->cur_state == QED_ROCE_QP_STATE_SQD)) {
2156                 /* RTS->SQD */
2157                 rc = qed_roce_sp_modify_requester(p_hwfn, qp, true, false,
2158                                                   params->modify_flags);
2159                 return rc;
2160         } else if ((prev_state == QED_ROCE_QP_STATE_SQD) &&
2161                    (qp->cur_state == QED_ROCE_QP_STATE_SQD)) {
2162                 /* SQD->SQD */
2163                 rc = qed_roce_sp_modify_responder(p_hwfn, qp, false,
2164                                                   params->modify_flags);
2165                 if (rc)
2166                         return rc;
2167
2168                 rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, false,
2169                                                   params->modify_flags);
2170                 return rc;
2171         } else if ((prev_state == QED_ROCE_QP_STATE_SQD) &&
2172                    (qp->cur_state == QED_ROCE_QP_STATE_RTS)) {
2173                 /* SQD->RTS */
2174                 rc = qed_roce_sp_modify_responder(p_hwfn, qp, false,
2175                                                   params->modify_flags);
2176                 if (rc)
2177                         return rc;
2178
2179                 rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, false,
2180                                                   params->modify_flags);
2181
2182                 return rc;
2183         } else if (qp->cur_state == QED_ROCE_QP_STATE_ERR ||
2184                    qp->cur_state == QED_ROCE_QP_STATE_SQE) {
2185                 /* ->ERR */
2186                 rc = qed_roce_sp_modify_responder(p_hwfn, qp, true,
2187                                                   params->modify_flags);
2188                 if (rc)
2189                         return rc;
2190
2191                 rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, true,
2192                                                   params->modify_flags);
2193                 return rc;
2194         } else if (qp->cur_state == QED_ROCE_QP_STATE_RESET) {
2195                 /* Any state -> RESET */
2196
2197                 rc = qed_roce_sp_destroy_qp_responder(p_hwfn, qp,
2198                                                       &num_invalidated_mw);
2199                 if (rc)
2200                         return rc;
2201
2202                 rc = qed_roce_sp_destroy_qp_requester(p_hwfn, qp,
2203                                                       &num_bound_mw);
2204
2205                 if (num_invalidated_mw != num_bound_mw) {
2206                         DP_NOTICE(p_hwfn,
2207                                   "number of invalidate memory windows is different from bounded ones\n");
2208                         return -EINVAL;
2209                 }
2210         } else {
2211                 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "0\n");
2212         }
2213
2214         return rc;
2215 }
2216
2217 int qed_rdma_modify_qp(void *rdma_cxt,
2218                        struct qed_rdma_qp *qp,
2219                        struct qed_rdma_modify_qp_in_params *params)
2220 {
2221         struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
2222         enum qed_roce_qp_state prev_state;
2223         int rc = 0;
2224
2225         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x params->new_state=%d\n",
2226                    qp->icid, params->new_state);
2227
2228         if (rc) {
2229                 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc);
2230                 return rc;
2231         }
2232
2233         if (GET_FIELD(params->modify_flags,
2234                       QED_RDMA_MODIFY_QP_VALID_RDMA_OPS_EN)) {
2235                 qp->incoming_rdma_read_en = params->incoming_rdma_read_en;
2236                 qp->incoming_rdma_write_en = params->incoming_rdma_write_en;
2237                 qp->incoming_atomic_en = params->incoming_atomic_en;
2238         }
2239
2240         /* Update QP structure with the updated values */
2241         if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_ROCE_MODE))
2242                 qp->roce_mode = params->roce_mode;
2243         if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_PKEY))
2244                 qp->pkey = params->pkey;
2245         if (GET_FIELD(params->modify_flags,
2246                       QED_ROCE_MODIFY_QP_VALID_E2E_FLOW_CONTROL_EN))
2247                 qp->e2e_flow_control_en = params->e2e_flow_control_en;
2248         if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_DEST_QP))
2249                 qp->dest_qp = params->dest_qp;
2250         if (GET_FIELD(params->modify_flags,
2251                       QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR)) {
2252                 /* Indicates that the following parameters have changed:
2253                  * Traffic class, flow label, hop limit, source GID,
2254                  * destination GID, loopback indicator
2255                  */
2256                 qp->traffic_class_tos = params->traffic_class_tos;
2257                 qp->flow_label = params->flow_label;
2258                 qp->hop_limit_ttl = params->hop_limit_ttl;
2259
2260                 qp->sgid = params->sgid;
2261                 qp->dgid = params->dgid;
2262                 qp->udp_src_port = 0;
2263                 qp->vlan_id = params->vlan_id;
2264                 qp->mtu = params->mtu;
2265                 qp->lb_indication = params->lb_indication;
2266                 memcpy((u8 *)&qp->remote_mac_addr[0],
2267                        (u8 *)&params->remote_mac_addr[0], ETH_ALEN);
2268                 if (params->use_local_mac) {
2269                         memcpy((u8 *)&qp->local_mac_addr[0],
2270                                (u8 *)&params->local_mac_addr[0], ETH_ALEN);
2271                 } else {
2272                         memcpy((u8 *)&qp->local_mac_addr[0],
2273                                (u8 *)&p_hwfn->hw_info.hw_mac_addr, ETH_ALEN);
2274                 }
2275         }
2276         if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_RQ_PSN))
2277                 qp->rq_psn = params->rq_psn;
2278         if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_SQ_PSN))
2279                 qp->sq_psn = params->sq_psn;
2280         if (GET_FIELD(params->modify_flags,
2281                       QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_REQ))
2282                 qp->max_rd_atomic_req = params->max_rd_atomic_req;
2283         if (GET_FIELD(params->modify_flags,
2284                       QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_RESP))
2285                 qp->max_rd_atomic_resp = params->max_rd_atomic_resp;
2286         if (GET_FIELD(params->modify_flags,
2287                       QED_ROCE_MODIFY_QP_VALID_ACK_TIMEOUT))
2288                 qp->ack_timeout = params->ack_timeout;
2289         if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_RETRY_CNT))
2290                 qp->retry_cnt = params->retry_cnt;
2291         if (GET_FIELD(params->modify_flags,
2292                       QED_ROCE_MODIFY_QP_VALID_RNR_RETRY_CNT))
2293                 qp->rnr_retry_cnt = params->rnr_retry_cnt;
2294         if (GET_FIELD(params->modify_flags,
2295                       QED_ROCE_MODIFY_QP_VALID_MIN_RNR_NAK_TIMER))
2296                 qp->min_rnr_nak_timer = params->min_rnr_nak_timer;
2297
2298         qp->sqd_async = params->sqd_async;
2299
2300         prev_state = qp->cur_state;
2301         if (GET_FIELD(params->modify_flags,
2302                       QED_RDMA_MODIFY_QP_VALID_NEW_STATE)) {
2303                 qp->cur_state = params->new_state;
2304                 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "qp->cur_state=%d\n",
2305                            qp->cur_state);
2306         }
2307
2308         rc = qed_roce_modify_qp(p_hwfn, qp, prev_state, params);
2309
2310         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Modify QP, rc = %d\n", rc);
2311         return rc;
2312 }
2313
2314 int qed_rdma_register_tid(void *rdma_cxt,
2315                           struct qed_rdma_register_tid_in_params *params)
2316 {
2317         struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
2318         struct rdma_register_tid_ramrod_data *p_ramrod;
2319         struct qed_sp_init_data init_data;
2320         struct qed_spq_entry *p_ent;
2321         enum rdma_tid_type tid_type;
2322         u8 fw_return_code;
2323         int rc;
2324
2325         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "itid = %08x\n", params->itid);
2326
2327         /* Get SPQ entry */
2328         memset(&init_data, 0, sizeof(init_data));
2329         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
2330         init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
2331
2332         rc = qed_sp_init_request(p_hwfn, &p_ent, RDMA_RAMROD_REGISTER_MR,
2333                                  p_hwfn->p_rdma_info->proto, &init_data);
2334         if (rc) {
2335                 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc);
2336                 return rc;
2337         }
2338
2339         if (p_hwfn->p_rdma_info->last_tid < params->itid)
2340                 p_hwfn->p_rdma_info->last_tid = params->itid;
2341
2342         p_ramrod = &p_ent->ramrod.rdma_register_tid;
2343
2344         p_ramrod->flags = 0;
2345         SET_FIELD(p_ramrod->flags,
2346                   RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL,
2347                   params->pbl_two_level);
2348
2349         SET_FIELD(p_ramrod->flags,
2350                   RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED, params->zbva);
2351
2352         SET_FIELD(p_ramrod->flags,
2353                   RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR, params->phy_mr);
2354
2355         /* Don't initialize D/C field, as it may override other bits. */
2356         if (!(params->tid_type == QED_RDMA_TID_FMR) && !(params->dma_mr))
2357                 SET_FIELD(p_ramrod->flags,
2358                           RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG,
2359                           params->page_size_log - 12);
2360
2361         SET_FIELD(p_ramrod->flags,
2362                   RDMA_REGISTER_TID_RAMROD_DATA_MAX_ID,
2363                   p_hwfn->p_rdma_info->last_tid);
2364
2365         SET_FIELD(p_ramrod->flags,
2366                   RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ,
2367                   params->remote_read);
2368
2369         SET_FIELD(p_ramrod->flags,
2370                   RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE,
2371                   params->remote_write);
2372
2373         SET_FIELD(p_ramrod->flags,
2374                   RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC,
2375                   params->remote_atomic);
2376
2377         SET_FIELD(p_ramrod->flags,
2378                   RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE,
2379                   params->local_write);
2380
2381         SET_FIELD(p_ramrod->flags,
2382                   RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ, params->local_read);
2383
2384         SET_FIELD(p_ramrod->flags,
2385                   RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND,
2386                   params->mw_bind);
2387
2388         SET_FIELD(p_ramrod->flags1,
2389                   RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG,
2390                   params->pbl_page_size_log - 12);
2391
2392         SET_FIELD(p_ramrod->flags2,
2393                   RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR, params->dma_mr);
2394
2395         switch (params->tid_type) {
2396         case QED_RDMA_TID_REGISTERED_MR:
2397                 tid_type = RDMA_TID_REGISTERED_MR;
2398                 break;
2399         case QED_RDMA_TID_FMR:
2400                 tid_type = RDMA_TID_FMR;
2401                 break;
2402         case QED_RDMA_TID_MW_TYPE1:
2403                 tid_type = RDMA_TID_MW_TYPE1;
2404                 break;
2405         case QED_RDMA_TID_MW_TYPE2A:
2406                 tid_type = RDMA_TID_MW_TYPE2A;
2407                 break;
2408         default:
2409                 rc = -EINVAL;
2410                 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc);
2411                 return rc;
2412         }
2413         SET_FIELD(p_ramrod->flags1,
2414                   RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE, tid_type);
2415
2416         p_ramrod->itid = cpu_to_le32(params->itid);
2417         p_ramrod->key = params->key;
2418         p_ramrod->pd = cpu_to_le16(params->pd);
2419         p_ramrod->length_hi = (u8)(params->length >> 32);
2420         p_ramrod->length_lo = DMA_LO_LE(params->length);
2421         if (params->zbva) {
2422                 /* Lower 32 bits of the registered MR address.
2423                  * In case of zero based MR, will hold FBO
2424                  */
2425                 p_ramrod->va.hi = 0;
2426                 p_ramrod->va.lo = cpu_to_le32(params->fbo);
2427         } else {
2428                 DMA_REGPAIR_LE(p_ramrod->va, params->vaddr);
2429         }
2430         DMA_REGPAIR_LE(p_ramrod->pbl_base, params->pbl_ptr);
2431
2432         /* DIF */
2433         if (params->dif_enabled) {
2434                 SET_FIELD(p_ramrod->flags2,
2435                           RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG, 1);
2436                 DMA_REGPAIR_LE(p_ramrod->dif_error_addr,
2437                                params->dif_error_addr);
2438                 DMA_REGPAIR_LE(p_ramrod->dif_runt_addr, params->dif_runt_addr);
2439         }
2440
2441         rc = qed_spq_post(p_hwfn, p_ent, &fw_return_code);
2442
2443         if (fw_return_code != RDMA_RETURN_OK) {
2444                 DP_NOTICE(p_hwfn, "fw_return_code = %d\n", fw_return_code);
2445                 return -EINVAL;
2446         }
2447
2448         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Register TID, rc = %d\n", rc);
2449         return rc;
2450 }
2451
2452 int qed_rdma_deregister_tid(void *rdma_cxt, u32 itid)
2453 {
2454         struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
2455         struct rdma_deregister_tid_ramrod_data *p_ramrod;
2456         struct qed_sp_init_data init_data;
2457         struct qed_spq_entry *p_ent;
2458         struct qed_ptt *p_ptt;
2459         u8 fw_return_code;
2460         int rc;
2461
2462         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "itid = %08x\n", itid);
2463
2464         /* Get SPQ entry */
2465         memset(&init_data, 0, sizeof(init_data));
2466         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
2467         init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
2468
2469         rc = qed_sp_init_request(p_hwfn, &p_ent, RDMA_RAMROD_DEREGISTER_MR,
2470                                  p_hwfn->p_rdma_info->proto, &init_data);
2471         if (rc) {
2472                 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc);
2473                 return rc;
2474         }
2475
2476         p_ramrod = &p_ent->ramrod.rdma_deregister_tid;
2477         p_ramrod->itid = cpu_to_le32(itid);
2478
2479         rc = qed_spq_post(p_hwfn, p_ent, &fw_return_code);
2480         if (rc) {
2481                 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc);
2482                 return rc;
2483         }
2484
2485         if (fw_return_code == RDMA_RETURN_DEREGISTER_MR_BAD_STATE_ERR) {
2486                 DP_NOTICE(p_hwfn, "fw_return_code = %d\n", fw_return_code);
2487                 return -EINVAL;
2488         } else if (fw_return_code == RDMA_RETURN_NIG_DRAIN_REQ) {
2489                 /* Bit indicating that the TID is in use and a nig drain is
2490                  * required before sending the ramrod again
2491                  */
2492                 p_ptt = qed_ptt_acquire(p_hwfn);
2493                 if (!p_ptt) {
2494                         rc = -EBUSY;
2495                         DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
2496                                    "Failed to acquire PTT\n");
2497                         return rc;
2498                 }
2499
2500                 rc = qed_mcp_drain(p_hwfn, p_ptt);
2501                 if (rc) {
2502                         qed_ptt_release(p_hwfn, p_ptt);
2503                         DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
2504                                    "Drain failed\n");
2505                         return rc;
2506                 }
2507
2508                 qed_ptt_release(p_hwfn, p_ptt);
2509
2510                 /* Resend the ramrod */
2511                 rc = qed_sp_init_request(p_hwfn, &p_ent,
2512                                          RDMA_RAMROD_DEREGISTER_MR,
2513                                          p_hwfn->p_rdma_info->proto,
2514                                          &init_data);
2515                 if (rc) {
2516                         DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
2517                                    "Failed to init sp-element\n");
2518                         return rc;
2519                 }
2520
2521                 rc = qed_spq_post(p_hwfn, p_ent, &fw_return_code);
2522                 if (rc) {
2523                         DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
2524                                    "Ramrod failed\n");
2525                         return rc;
2526                 }
2527
2528                 if (fw_return_code != RDMA_RETURN_OK) {
2529                         DP_NOTICE(p_hwfn, "fw_return_code = %d\n",
2530                                   fw_return_code);
2531                         return rc;
2532                 }
2533         }
2534
2535         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "De-registered TID, rc = %d\n", rc);
2536         return rc;
2537 }
2538
2539 static void *qed_rdma_get_rdma_ctx(struct qed_dev *cdev)
2540 {
2541         return QED_LEADING_HWFN(cdev);
2542 }
2543
2544 static void qed_rdma_dpm_conf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2545 {
2546         u32 val;
2547
2548         val = (p_hwfn->dcbx_no_edpm || p_hwfn->db_bar_no_edpm) ? 0 : 1;
2549
2550         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPM_ENABLE, val);
2551         DP_VERBOSE(p_hwfn, (QED_MSG_DCB | QED_MSG_RDMA),
2552                    "Changing DPM_EN state to %d (DCBX=%d, DB_BAR=%d)\n",
2553                    val, p_hwfn->dcbx_no_edpm, p_hwfn->db_bar_no_edpm);
2554 }
2555
2556 void qed_rdma_dpm_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2557 {
2558         p_hwfn->db_bar_no_edpm = true;
2559
2560         qed_rdma_dpm_conf(p_hwfn, p_ptt);
2561 }
2562
2563 int qed_rdma_start(void *rdma_cxt, struct qed_rdma_start_in_params *params)
2564 {
2565         struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
2566         struct qed_ptt *p_ptt;
2567         int rc = -EBUSY;
2568
2569         DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
2570                    "desired_cnq = %08x\n", params->desired_cnq);
2571
2572         p_ptt = qed_ptt_acquire(p_hwfn);
2573         if (!p_ptt)
2574                 goto err;
2575
2576         rc = qed_rdma_alloc(p_hwfn, p_ptt, params);
2577         if (rc)
2578                 goto err1;
2579
2580         rc = qed_rdma_setup(p_hwfn, p_ptt, params);
2581         if (rc)
2582                 goto err2;
2583
2584         qed_ptt_release(p_hwfn, p_ptt);
2585
2586         return rc;
2587
2588 err2:
2589         qed_rdma_free(p_hwfn);
2590 err1:
2591         qed_ptt_release(p_hwfn, p_ptt);
2592 err:
2593         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA start - error, rc = %d\n", rc);
2594         return rc;
2595 }
2596
2597 static int qed_rdma_init(struct qed_dev *cdev,
2598                          struct qed_rdma_start_in_params *params)
2599 {
2600         return qed_rdma_start(QED_LEADING_HWFN(cdev), params);
2601 }
2602
2603 void qed_rdma_remove_user(void *rdma_cxt, u16 dpi)
2604 {
2605         struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
2606
2607         DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "dpi = %08x\n", dpi);
2608
2609         spin_lock_bh(&p_hwfn->p_rdma_info->lock);
2610         qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->dpi_map, dpi);
2611         spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
2612 }
2613
2614 static const struct qed_rdma_ops qed_rdma_ops_pass = {
2615         .common = &qed_common_ops_pass,
2616         .fill_dev_info = &qed_fill_rdma_dev_info,
2617         .rdma_get_rdma_ctx = &qed_rdma_get_rdma_ctx,
2618         .rdma_init = &qed_rdma_init,
2619         .rdma_add_user = &qed_rdma_add_user,
2620         .rdma_remove_user = &qed_rdma_remove_user,
2621         .rdma_stop = &qed_rdma_stop,
2622         .rdma_query_port = &qed_rdma_query_port,
2623         .rdma_query_device = &qed_rdma_query_device,
2624         .rdma_get_start_sb = &qed_rdma_get_sb_start,
2625         .rdma_get_rdma_int = &qed_rdma_get_int,
2626         .rdma_set_rdma_int = &qed_rdma_set_int,
2627         .rdma_get_min_cnq_msix = &qed_rdma_get_min_cnq_msix,
2628         .rdma_cnq_prod_update = &qed_rdma_cnq_prod_update,
2629         .rdma_alloc_pd = &qed_rdma_alloc_pd,
2630         .rdma_dealloc_pd = &qed_rdma_free_pd,
2631         .rdma_create_cq = &qed_rdma_create_cq,
2632         .rdma_destroy_cq = &qed_rdma_destroy_cq,
2633         .rdma_create_qp = &qed_rdma_create_qp,
2634         .rdma_modify_qp = &qed_rdma_modify_qp,
2635         .rdma_query_qp = &qed_rdma_query_qp,
2636         .rdma_destroy_qp = &qed_rdma_destroy_qp,
2637         .rdma_alloc_tid = &qed_rdma_alloc_tid,
2638         .rdma_free_tid = &qed_rdma_free_tid,
2639         .rdma_register_tid = &qed_rdma_register_tid,
2640         .rdma_deregister_tid = &qed_rdma_deregister_tid,
2641 };
2642
2643 const struct qed_rdma_ops *qed_get_rdma_ops()
2644 {
2645         return &qed_rdma_ops_pass;
2646 }
2647 EXPORT_SYMBOL(qed_get_rdma_ops);