drivers/net/ethernet/renesas/sh_eth.c

   1 /*  SuperH Ethernet device driver
   2  *
   3  *  Copyright (C) 2014  Renesas Electronics Corporation
   4  *  Copyright (C) 2006-2012 Nobuhiro Iwamatsu
   5  *  Copyright (C) 2008-2014 Renesas Solutions Corp.
   6  *  Copyright (C) 2013-2014 Cogent Embedded, Inc.
   7  *  Copyright (C) 2014 Codethink Limited
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms and conditions of the GNU General Public License,
  11  *  version 2, as published by the Free Software Foundation.
  12  *
  13  *  This program is distributed in the hope it will be useful, but WITHOUT
  14  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  16  *  more details.
  17  *
  18  *  The full GNU General Public License is included in this distribution in
  19  *  the file called "COPYING".
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/etherdevice.h>
  28 #include <linux/delay.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/mdio-bitbang.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/of.h>
  33 #include <linux/of_device.h>
  34 #include <linux/of_irq.h>
  35 #include <linux/of_net.h>
  36 #include <linux/phy.h>
  37 #include <linux/cache.h>
  38 #include <linux/io.h>
  39 #include <linux/pm_runtime.h>
  40 #include <linux/slab.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/clk.h>
  44 #include <linux/sh_eth.h>
  45 #include <linux/of_mdio.h>
  46
  47 #include "sh_eth.h"
  48
  49 #define SH_ETH_DEF_MSG_ENABLE \
  50                 (NETIF_MSG_LINK | \
  51                 NETIF_MSG_TIMER | \
  52                 NETIF_MSG_RX_ERR| \
  53                 NETIF_MSG_TX_ERR)
  54
  55 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
  56         [EDSR]          = 0x0000,
  57         [EDMR]          = 0x0400,
  58         [EDTRR]         = 0x0408,
  59         [EDRRR]         = 0x0410,
  60         [EESR]          = 0x0428,
  61         [EESIPR]        = 0x0430,
  62         [TDLAR]         = 0x0010,
  63         [TDFAR]         = 0x0014,
  64         [TDFXR]         = 0x0018,
  65         [TDFFR]         = 0x001c,
  66         [RDLAR]         = 0x0030,
  67         [RDFAR]         = 0x0034,
  68         [RDFXR]         = 0x0038,
  69         [RDFFR]         = 0x003c,
  70         [TRSCER]        = 0x0438,
  71         [RMFCR]         = 0x0440,
  72         [TFTR]          = 0x0448,
  73         [FDR]           = 0x0450,
  74         [RMCR]          = 0x0458,
  75         [RPADIR]        = 0x0460,
  76         [FCFTR]         = 0x0468,
  77         [CSMR]          = 0x04E4,
  78
  79         [ECMR]          = 0x0500,
  80         [ECSR]          = 0x0510,
  81         [ECSIPR]        = 0x0518,
  82         [PIR]           = 0x0520,
  83         [PSR]           = 0x0528,
  84         [PIPR]          = 0x052c,
  85         [RFLR]          = 0x0508,
  86         [APR]           = 0x0554,
  87         [MPR]           = 0x0558,
  88         [PFTCR]         = 0x055c,
  89         [PFRCR]         = 0x0560,
  90         [TPAUSER]       = 0x0564,
  91         [GECMR]         = 0x05b0,
  92         [BCULR]         = 0x05b4,
  93         [MAHR]          = 0x05c0,
  94         [MALR]          = 0x05c8,
  95         [TROCR]         = 0x0700,
  96         [CDCR]          = 0x0708,
  97         [LCCR]          = 0x0710,
  98         [CEFCR]         = 0x0740,
  99         [FRECR]         = 0x0748,
 100         [TSFRCR]        = 0x0750,
 101         [TLFRCR]        = 0x0758,
 102         [RFCR]          = 0x0760,
 103         [CERCR]         = 0x0768,
 104         [CEECR]         = 0x0770,
 105         [MAFCR]         = 0x0778,
 106         [RMII_MII]      = 0x0790,
 107
 108         [ARSTR]         = 0x0000,
 109         [TSU_CTRST]     = 0x0004,
 110         [TSU_FWEN0]     = 0x0010,
 111         [TSU_FWEN1]     = 0x0014,
 112         [TSU_FCM]       = 0x0018,
 113         [TSU_BSYSL0]    = 0x0020,
 114         [TSU_BSYSL1]    = 0x0024,
 115         [TSU_PRISL0]    = 0x0028,
 116         [TSU_PRISL1]    = 0x002c,
 117         [TSU_FWSL0]     = 0x0030,
 118         [TSU_FWSL1]     = 0x0034,
 119         [TSU_FWSLC]     = 0x0038,
 120         [TSU_QTAG0]     = 0x0040,
 121         [TSU_QTAG1]     = 0x0044,
 122         [TSU_FWSR]      = 0x0050,
 123         [TSU_FWINMK]    = 0x0054,
 124         [TSU_ADQT0]     = 0x0048,
 125         [TSU_ADQT1]     = 0x004c,
 126         [TSU_VTAG0]     = 0x0058,
 127         [TSU_VTAG1]     = 0x005c,
 128         [TSU_ADSBSY]    = 0x0060,
 129         [TSU_TEN]       = 0x0064,
 130         [TSU_POST1]     = 0x0070,
 131         [TSU_POST2]     = 0x0074,
 132         [TSU_POST3]     = 0x0078,
 133         [TSU_POST4]     = 0x007c,
 134         [TSU_ADRH0]     = 0x0100,
 135         [TSU_ADRL0]     = 0x0104,
 136         [TSU_ADRH31]    = 0x01f8,
 137         [TSU_ADRL31]    = 0x01fc,
 138
 139         [TXNLCR0]       = 0x0080,
 140         [TXALCR0]       = 0x0084,
 141         [RXNLCR0]       = 0x0088,
 142         [RXALCR0]       = 0x008c,
 143         [FWNLCR0]       = 0x0090,
 144         [FWALCR0]       = 0x0094,
 145         [TXNLCR1]       = 0x00a0,
 146         [TXALCR1]       = 0x00a0,
 147         [RXNLCR1]       = 0x00a8,
 148         [RXALCR1]       = 0x00ac,
 149         [FWNLCR1]       = 0x00b0,
 150         [FWALCR1]       = 0x00b4,
 151 };
 152
 153 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
 154         [EDSR]          = 0x0000,
 155         [EDMR]          = 0x0400,
 156         [EDTRR]         = 0x0408,
 157         [EDRRR]         = 0x0410,
 158         [EESR]          = 0x0428,
 159         [EESIPR]        = 0x0430,
 160         [TDLAR]         = 0x0010,
 161         [TDFAR]         = 0x0014,
 162         [TDFXR]         = 0x0018,
 163         [TDFFR]         = 0x001c,
 164         [RDLAR]         = 0x0030,
 165         [RDFAR]         = 0x0034,
 166         [RDFXR]         = 0x0038,
 167         [RDFFR]         = 0x003c,
 168         [TRSCER]        = 0x0438,
 169         [RMFCR]         = 0x0440,
 170         [TFTR]          = 0x0448,
 171         [FDR]           = 0x0450,
 172         [RMCR]          = 0x0458,
 173         [RPADIR]        = 0x0460,
 174         [FCFTR]         = 0x0468,
 175         [CSMR]          = 0x04E4,
 176
 177         [ECMR]          = 0x0500,
 178         [RFLR]          = 0x0508,
 179         [ECSR]          = 0x0510,
 180         [ECSIPR]        = 0x0518,
 181         [PIR]           = 0x0520,
 182         [APR]           = 0x0554,
 183         [MPR]           = 0x0558,
 184         [PFTCR]         = 0x055c,
 185         [PFRCR]         = 0x0560,
 186         [TPAUSER]       = 0x0564,
 187         [MAHR]          = 0x05c0,
 188         [MALR]          = 0x05c8,
 189         [CEFCR]         = 0x0740,
 190         [FRECR]         = 0x0748,
 191         [TSFRCR]        = 0x0750,
 192         [TLFRCR]        = 0x0758,
 193         [RFCR]          = 0x0760,
 194         [MAFCR]         = 0x0778,
 195
 196         [ARSTR]         = 0x0000,
 197         [TSU_CTRST]     = 0x0004,
 198         [TSU_VTAG0]     = 0x0058,
 199         [TSU_ADSBSY]    = 0x0060,
 200         [TSU_TEN]       = 0x0064,
 201         [TSU_ADRH0]     = 0x0100,
 202         [TSU_ADRL0]     = 0x0104,
 203         [TSU_ADRH31]    = 0x01f8,
 204         [TSU_ADRL31]    = 0x01fc,
 205
 206         [TXNLCR0]       = 0x0080,
 207         [TXALCR0]       = 0x0084,
 208         [RXNLCR0]       = 0x0088,
 209         [RXALCR0]       = 0x008C,
 210 };
 211
 212 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
 213         [ECMR]          = 0x0300,
 214         [RFLR]          = 0x0308,
 215         [ECSR]          = 0x0310,
 216         [ECSIPR]        = 0x0318,
 217         [PIR]           = 0x0320,
 218         [PSR]           = 0x0328,
 219         [RDMLR]         = 0x0340,
 220         [IPGR]          = 0x0350,
 221         [APR]           = 0x0354,
 222         [MPR]           = 0x0358,
 223         [RFCF]          = 0x0360,
 224         [TPAUSER]       = 0x0364,
 225         [TPAUSECR]      = 0x0368,
 226         [MAHR]          = 0x03c0,
 227         [MALR]          = 0x03c8,
 228         [TROCR]         = 0x03d0,
 229         [CDCR]          = 0x03d4,
 230         [LCCR]          = 0x03d8,
 231         [CNDCR]         = 0x03dc,
 232         [CEFCR]         = 0x03e4,
 233         [FRECR]         = 0x03e8,
 234         [TSFRCR]        = 0x03ec,
 235         [TLFRCR]        = 0x03f0,
 236         [RFCR]          = 0x03f4,
 237         [MAFCR]         = 0x03f8,
 238
 239         [EDMR]          = 0x0200,
 240         [EDTRR]         = 0x0208,
 241         [EDRRR]         = 0x0210,
 242         [TDLAR]         = 0x0218,
 243         [RDLAR]         = 0x0220,
 244         [EESR]          = 0x0228,
 245         [EESIPR]        = 0x0230,
 246         [TRSCER]        = 0x0238,
 247         [RMFCR]         = 0x0240,
 248         [TFTR]          = 0x0248,
 249         [FDR]           = 0x0250,
 250         [RMCR]          = 0x0258,
 251         [TFUCR]         = 0x0264,
 252         [RFOCR]         = 0x0268,
 253         [RMIIMODE]      = 0x026c,
 254         [FCFTR]         = 0x0270,
 255         [TRIMD]         = 0x027c,
 256 };
 257
 258 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 259         [ECMR]          = 0x0100,
 260         [RFLR]          = 0x0108,
 261         [ECSR]          = 0x0110,
 262         [ECSIPR]        = 0x0118,
 263         [PIR]           = 0x0120,
 264         [PSR]           = 0x0128,
 265         [RDMLR]         = 0x0140,
 266         [IPGR]          = 0x0150,
 267         [APR]           = 0x0154,
 268         [MPR]           = 0x0158,
 269         [TPAUSER]       = 0x0164,
 270         [RFCF]          = 0x0160,
 271         [TPAUSECR]      = 0x0168,
 272         [BCFRR]         = 0x016c,
 273         [MAHR]          = 0x01c0,
 274         [MALR]          = 0x01c8,
 275         [TROCR]         = 0x01d0,
 276         [CDCR]          = 0x01d4,
 277         [LCCR]          = 0x01d8,
 278         [CNDCR]         = 0x01dc,
 279         [CEFCR]         = 0x01e4,
 280         [FRECR]         = 0x01e8,
 281         [TSFRCR]        = 0x01ec,
 282         [TLFRCR]        = 0x01f0,
 283         [RFCR]          = 0x01f4,
 284         [MAFCR]         = 0x01f8,
 285         [RTRATE]        = 0x01fc,
 286
 287         [EDMR]          = 0x0000,
 288         [EDTRR]         = 0x0008,
 289         [EDRRR]         = 0x0010,
 290         [TDLAR]         = 0x0018,
 291         [RDLAR]         = 0x0020,
 292         [EESR]          = 0x0028,
 293         [EESIPR]        = 0x0030,
 294         [TRSCER]        = 0x0038,
 295         [RMFCR]         = 0x0040,
 296         [TFTR]          = 0x0048,
 297         [FDR]           = 0x0050,
 298         [RMCR]          = 0x0058,
 299         [TFUCR]         = 0x0064,
 300         [RFOCR]         = 0x0068,
 301         [FCFTR]         = 0x0070,
 302         [RPADIR]        = 0x0078,
 303         [TRIMD]         = 0x007c,
 304         [RBWAR]         = 0x00c8,
 305         [RDFAR]         = 0x00cc,
 306         [TBRAR]         = 0x00d4,
 307         [TDFAR]         = 0x00d8,
 308 };
 309
 310 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
 311         [EDMR]          = 0x0000,
 312         [EDTRR]         = 0x0004,
 313         [EDRRR]         = 0x0008,
 314         [TDLAR]         = 0x000c,
 315         [RDLAR]         = 0x0010,
 316         [EESR]          = 0x0014,
 317         [EESIPR]        = 0x0018,
 318         [TRSCER]        = 0x001c,
 319         [RMFCR]         = 0x0020,
 320         [TFTR]          = 0x0024,
 321         [FDR]           = 0x0028,
 322         [RMCR]          = 0x002c,
 323         [EDOCR]         = 0x0030,
 324         [FCFTR]         = 0x0034,
 325         [RPADIR]        = 0x0038,
 326         [TRIMD]         = 0x003c,
 327         [RBWAR]         = 0x0040,
 328         [RDFAR]         = 0x0044,
 329         [TBRAR]         = 0x004c,
 330         [TDFAR]         = 0x0050,
 331
 332         [ECMR]          = 0x0160,
 333         [ECSR]          = 0x0164,
 334         [ECSIPR]        = 0x0168,
 335         [PIR]           = 0x016c,
 336         [MAHR]          = 0x0170,
 337         [MALR]          = 0x0174,
 338         [RFLR]          = 0x0178,
 339         [PSR]           = 0x017c,
 340         [TROCR]         = 0x0180,
 341         [CDCR]          = 0x0184,
 342         [LCCR]          = 0x0188,
 343         [CNDCR]         = 0x018c,
 344         [CEFCR]         = 0x0194,
 345         [FRECR]         = 0x0198,
 346         [TSFRCR]        = 0x019c,
 347         [TLFRCR]        = 0x01a0,
 348         [RFCR]          = 0x01a4,
 349         [MAFCR]         = 0x01a8,
 350         [IPGR]          = 0x01b4,
 351         [APR]           = 0x01b8,
 352         [MPR]           = 0x01bc,
 353         [TPAUSER]       = 0x01c4,
 354         [BCFR]          = 0x01cc,
 355
 356         [ARSTR]         = 0x0000,
 357         [TSU_CTRST]     = 0x0004,
 358         [TSU_FWEN0]     = 0x0010,
 359         [TSU_FWEN1]     = 0x0014,
 360         [TSU_FCM]       = 0x0018,
 361         [TSU_BSYSL0]    = 0x0020,
 362         [TSU_BSYSL1]    = 0x0024,
 363         [TSU_PRISL0]    = 0x0028,
 364         [TSU_PRISL1]    = 0x002c,
 365         [TSU_FWSL0]     = 0x0030,
 366         [TSU_FWSL1]     = 0x0034,
 367         [TSU_FWSLC]     = 0x0038,
 368         [TSU_QTAGM0]    = 0x0040,
 369         [TSU_QTAGM1]    = 0x0044,
 370         [TSU_ADQT0]     = 0x0048,
 371         [TSU_ADQT1]     = 0x004c,
 372         [TSU_FWSR]      = 0x0050,
 373         [TSU_FWINMK]    = 0x0054,
 374         [TSU_ADSBSY]    = 0x0060,
 375         [TSU_TEN]       = 0x0064,
 376         [TSU_POST1]     = 0x0070,
 377         [TSU_POST2]     = 0x0074,
 378         [TSU_POST3]     = 0x0078,
 379         [TSU_POST4]     = 0x007c,
 380
 381         [TXNLCR0]       = 0x0080,
 382         [TXALCR0]       = 0x0084,
 383         [RXNLCR0]       = 0x0088,
 384         [RXALCR0]       = 0x008c,
 385         [FWNLCR0]       = 0x0090,
 386         [FWALCR0]       = 0x0094,
 387         [TXNLCR1]       = 0x00a0,
 388         [TXALCR1]       = 0x00a0,
 389         [RXNLCR1]       = 0x00a8,
 390         [RXALCR1]       = 0x00ac,
 391         [FWNLCR1]       = 0x00b0,
 392         [FWALCR1]       = 0x00b4,
 393
 394         [TSU_ADRH0]     = 0x0100,
 395         [TSU_ADRL0]     = 0x0104,
 396         [TSU_ADRL31]    = 0x01fc,
 397 };
 398
 399 static bool sh_eth_is_gether(struct sh_eth_private *mdp)
 400 {
 401         return mdp->reg_offset == sh_eth_offset_gigabit;
 402 }
 403
 404 static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
 405 {
 406         return mdp->reg_offset == sh_eth_offset_fast_rz;
 407 }
 408
 409 static void sh_eth_select_mii(struct net_device *ndev)
 410 {
 411         u32 value = 0x0;
 412         struct sh_eth_private *mdp = netdev_priv(ndev);
 413
 414         switch (mdp->phy_interface) {
 415         case PHY_INTERFACE_MODE_GMII:
 416                 value = 0x2;
 417                 break;
 418         case PHY_INTERFACE_MODE_MII:
 419                 value = 0x1;
 420                 break;
 421         case PHY_INTERFACE_MODE_RMII:
 422                 value = 0x0;
 423                 break;
 424         default:
 425                 netdev_warn(ndev,
 426                             "PHY interface mode was not setup. Set to MII.\n");
 427                 value = 0x1;
 428                 break;
 429         }
 430
 431         sh_eth_write(ndev, value, RMII_MII);
 432 }
 433
 434 static void sh_eth_set_duplex(struct net_device *ndev)
 435 {
 436         struct sh_eth_private *mdp = netdev_priv(ndev);
 437
 438         if (mdp->duplex) /* Full */
 439                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
 440         else            /* Half */
 441                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
 442 }
 443
 444 /* There is CPU dependent code */
 445 static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
 446 {
 447         struct sh_eth_private *mdp = netdev_priv(ndev);
 448
 449         switch (mdp->speed) {
 450         case 10: /* 10BASE */
 451                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
 452                 break;
 453         case 100:/* 100BASE */
 454                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
 455                 break;
 456         default:
 457                 break;
 458         }
 459 }
 460
 461 /* R8A7778/9 */
 462 static struct sh_eth_cpu_data r8a777x_data = {
 463         .set_duplex     = sh_eth_set_duplex,
 464         .set_rate       = sh_eth_set_rate_r8a777x,
 465
 466         .register_type  = SH_ETH_REG_FAST_RCAR,
 467
 468         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 469         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 470         .eesipr_value   = 0x01ff009f,
 471
 472         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 473         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 474                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 475                           EESR_ECI,
 476         .fdr_value      = 0x00000f0f,
 477
 478         .apr            = 1,
 479         .mpr            = 1,
 480         .tpauser        = 1,
 481         .hw_swap        = 1,
 482 };
 483
 484 /* R8A7790/1 */
 485 static struct sh_eth_cpu_data r8a779x_data = {
 486         .set_duplex     = sh_eth_set_duplex,
 487         .set_rate       = sh_eth_set_rate_r8a777x,
 488
 489         .register_type  = SH_ETH_REG_FAST_RCAR,
 490
 491         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 492         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 493         .eesipr_value   = 0x01ff009f,
 494
 495         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 496         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 497                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 498                           EESR_ECI,
 499         .fdr_value      = 0x00000f0f,
 500
 501         .trscer_err_mask = DESC_I_RINT8,
 502
 503         .apr            = 1,
 504         .mpr            = 1,
 505         .tpauser        = 1,
 506         .hw_swap        = 1,
 507         .rmiimode       = 1,
 508         .shift_rd0      = 1,
 509 };
 510
 511 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
 512 {
 513         struct sh_eth_private *mdp = netdev_priv(ndev);
 514
 515         switch (mdp->speed) {
 516         case 10: /* 10BASE */
 517                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
 518                 break;
 519         case 100:/* 100BASE */
 520                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
 521                 break;
 522         default:
 523                 break;
 524         }
 525 }
 526
 527 /* SH7724 */
 528 static struct sh_eth_cpu_data sh7724_data = {
 529         .set_duplex     = sh_eth_set_duplex,
 530         .set_rate       = sh_eth_set_rate_sh7724,
 531
 532         .register_type  = SH_ETH_REG_FAST_SH4,
 533
 534         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 535         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 536         .eesipr_value   = 0x01ff009f,
 537
 538         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 539         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 540                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 541                           EESR_ECI,
 542
 543         .apr            = 1,
 544         .mpr            = 1,
 545         .tpauser        = 1,
 546         .hw_swap        = 1,
 547         .rpadir         = 1,
 548         .rpadir_value   = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
 549 };
 550
 551 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
 552 {
 553         struct sh_eth_private *mdp = netdev_priv(ndev);
 554
 555         switch (mdp->speed) {
 556         case 10: /* 10BASE */
 557                 sh_eth_write(ndev, 0, RTRATE);
 558                 break;
 559         case 100:/* 100BASE */
 560                 sh_eth_write(ndev, 1, RTRATE);
 561                 break;
 562         default:
 563                 break;
 564         }
 565 }
 566
 567 /* SH7757 */
 568 static struct sh_eth_cpu_data sh7757_data = {
 569         .set_duplex     = sh_eth_set_duplex,
 570         .set_rate       = sh_eth_set_rate_sh7757,
 571
 572         .register_type  = SH_ETH_REG_FAST_SH4,
 573
 574         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 575
 576         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 577         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 578                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 579                           EESR_ECI,
 580
 581         .irq_flags      = IRQF_SHARED,
 582         .apr            = 1,
 583         .mpr            = 1,
 584         .tpauser        = 1,
 585         .hw_swap        = 1,
 586         .no_ade         = 1,
 587         .rpadir         = 1,
 588         .rpadir_value   = 2 << 16,
 589 };
 590
 591 #define SH_GIGA_ETH_BASE        0xfee00000UL
 592 #define GIGA_MALR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
 593 #define GIGA_MAHR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
 594 static void sh_eth_chip_reset_giga(struct net_device *ndev)
 595 {
 596         int i;
 597         unsigned long mahr[2], malr[2];
 598
 599         /* save MAHR and MALR */
 600         for (i = 0; i < 2; i++) {
 601                 malr[i] = ioread32((void *)GIGA_MALR(i));
 602                 mahr[i] = ioread32((void *)GIGA_MAHR(i));
 603         }
 604
 605         /* reset device */
 606         iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
 607         mdelay(1);
 608
 609         /* restore MAHR and MALR */
 610         for (i = 0; i < 2; i++) {
 611                 iowrite32(malr[i], (void *)GIGA_MALR(i));
 612                 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
 613         }
 614 }
 615
 616 static void sh_eth_set_rate_giga(struct net_device *ndev)
 617 {
 618         struct sh_eth_private *mdp = netdev_priv(ndev);
 619
 620         switch (mdp->speed) {
 621         case 10: /* 10BASE */
 622                 sh_eth_write(ndev, 0x00000000, GECMR);
 623                 break;
 624         case 100:/* 100BASE */
 625                 sh_eth_write(ndev, 0x00000010, GECMR);
 626                 break;
 627         case 1000: /* 1000BASE */
 628                 sh_eth_write(ndev, 0x00000020, GECMR);
 629                 break;
 630         default:
 631                 break;
 632         }
 633 }
 634
 635 /* SH7757(GETHERC) */
 636 static struct sh_eth_cpu_data sh7757_data_giga = {
 637         .chip_reset     = sh_eth_chip_reset_giga,
 638         .set_duplex     = sh_eth_set_duplex,
 639         .set_rate       = sh_eth_set_rate_giga,
 640
 641         .register_type  = SH_ETH_REG_GIGABIT,
 642
 643         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 644         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 645         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 646
 647         .tx_check       = EESR_TC1 | EESR_FTC,
 648         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 649                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 650                           EESR_TDE | EESR_ECI,
 651         .fdr_value      = 0x0000072f,
 652
 653         .irq_flags      = IRQF_SHARED,
 654         .apr            = 1,
 655         .mpr            = 1,
 656         .tpauser        = 1,
 657         .bculr          = 1,
 658         .hw_swap        = 1,
 659         .rpadir         = 1,
 660         .rpadir_value   = 2 << 16,
 661         .no_trimd       = 1,
 662         .no_ade         = 1,
 663         .tsu            = 1,
 664 };
 665
 666 static void sh_eth_chip_reset(struct net_device *ndev)
 667 {
 668         struct sh_eth_private *mdp = netdev_priv(ndev);
 669
 670         /* reset device */
 671         sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
 672         mdelay(1);
 673 }
 674
 675 static void sh_eth_set_rate_gether(struct net_device *ndev)
 676 {
 677         struct sh_eth_private *mdp = netdev_priv(ndev);
 678
 679         switch (mdp->speed) {
 680         case 10: /* 10BASE */
 681                 sh_eth_write(ndev, GECMR_10, GECMR);
 682                 break;
 683         case 100:/* 100BASE */
 684                 sh_eth_write(ndev, GECMR_100, GECMR);
 685                 break;
 686         case 1000: /* 1000BASE */
 687                 sh_eth_write(ndev, GECMR_1000, GECMR);
 688                 break;
 689         default:
 690                 break;
 691         }
 692 }
 693
 694 /* SH7734 */
 695 static struct sh_eth_cpu_data sh7734_data = {
 696         .chip_reset     = sh_eth_chip_reset,
 697         .set_duplex     = sh_eth_set_duplex,
 698         .set_rate       = sh_eth_set_rate_gether,
 699
 700         .register_type  = SH_ETH_REG_GIGABIT,
 701
 702         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 703         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 704         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 705
 706         .tx_check       = EESR_TC1 | EESR_FTC,
 707         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 708                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 709                           EESR_TDE | EESR_ECI,
 710
 711         .apr            = 1,
 712         .mpr            = 1,
 713         .tpauser        = 1,
 714         .bculr          = 1,
 715         .hw_swap        = 1,
 716         .no_trimd       = 1,
 717         .no_ade         = 1,
 718         .tsu            = 1,
 719         .hw_crc         = 1,
 720         .select_mii     = 1,
 721 };
 722
 723 /* SH7763 */
 724 static struct sh_eth_cpu_data sh7763_data = {
 725         .chip_reset     = sh_eth_chip_reset,
 726         .set_duplex     = sh_eth_set_duplex,
 727         .set_rate       = sh_eth_set_rate_gether,
 728
 729         .register_type  = SH_ETH_REG_GIGABIT,
 730
 731         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 732         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 733         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 734
 735         .tx_check       = EESR_TC1 | EESR_FTC,
 736         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 737                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 738                           EESR_ECI,
 739
 740         .apr            = 1,
 741         .mpr            = 1,
 742         .tpauser        = 1,
 743         .bculr          = 1,
 744         .hw_swap        = 1,
 745         .no_trimd       = 1,
 746         .no_ade         = 1,
 747         .tsu            = 1,
 748         .irq_flags      = IRQF_SHARED,
 749 };
 750
 751 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
 752 {
 753         struct sh_eth_private *mdp = netdev_priv(ndev);
 754
 755         /* reset device */
 756         sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
 757         mdelay(1);
 758
 759         sh_eth_select_mii(ndev);
 760 }
 761
 762 /* R8A7740 */
 763 static struct sh_eth_cpu_data r8a7740_data = {
 764         .chip_reset     = sh_eth_chip_reset_r8a7740,
 765         .set_duplex     = sh_eth_set_duplex,
 766         .set_rate       = sh_eth_set_rate_gether,
 767
 768         .register_type  = SH_ETH_REG_GIGABIT,
 769
 770         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 771         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 772         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 773
 774         .tx_check       = EESR_TC1 | EESR_FTC,
 775         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 776                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 777                           EESR_TDE | EESR_ECI,
 778         .fdr_value      = 0x0000070f,
 779
 780         .apr            = 1,
 781         .mpr            = 1,
 782         .tpauser        = 1,
 783         .bculr          = 1,
 784         .hw_swap        = 1,
 785         .rpadir         = 1,
 786         .rpadir_value   = 2 << 16,
 787         .no_trimd       = 1,
 788         .no_ade         = 1,
 789         .tsu            = 1,
 790         .select_mii     = 1,
 791         .shift_rd0      = 1,
 792 };
 793
 794 /* R7S72100 */
 795 static struct sh_eth_cpu_data r7s72100_data = {
 796         .chip_reset     = sh_eth_chip_reset,
 797         .set_duplex     = sh_eth_set_duplex,
 798
 799         .register_type  = SH_ETH_REG_FAST_RZ,
 800
 801         .ecsr_value     = ECSR_ICD,
 802         .ecsipr_value   = ECSIPR_ICDIP,
 803         .eesipr_value   = 0xff7f009f,
 804
 805         .tx_check       = EESR_TC1 | EESR_FTC,
 806         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 807                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 808                           EESR_TDE | EESR_ECI,
 809         .fdr_value      = 0x0000070f,
 810
 811         .no_psr         = 1,
 812         .apr            = 1,
 813         .mpr            = 1,
 814         .tpauser        = 1,
 815         .hw_swap        = 1,
 816         .rpadir         = 1,
 817         .rpadir_value   = 2 << 16,
 818         .no_trimd       = 1,
 819         .no_ade         = 1,
 820         .hw_crc         = 1,
 821         .tsu            = 1,
 822         .shift_rd0      = 1,
 823 };
 824
 825 static struct sh_eth_cpu_data sh7619_data = {
 826         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
 827
 828         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 829
 830         .apr            = 1,
 831         .mpr            = 1,
 832         .tpauser        = 1,
 833         .hw_swap        = 1,
 834 };
 835
 836 static struct sh_eth_cpu_data sh771x_data = {
 837         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
 838
 839         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 840         .tsu            = 1,
 841 };
 842
 843 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
 844 {
 845         if (!cd->ecsr_value)
 846                 cd->ecsr_value = DEFAULT_ECSR_INIT;
 847
 848         if (!cd->ecsipr_value)
 849                 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
 850
 851         if (!cd->fcftr_value)
 852                 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
 853                                   DEFAULT_FIFO_F_D_RFD;
 854
 855         if (!cd->fdr_value)
 856                 cd->fdr_value = DEFAULT_FDR_INIT;
 857
 858         if (!cd->tx_check)
 859                 cd->tx_check = DEFAULT_TX_CHECK;
 860
 861         if (!cd->eesr_err_check)
 862                 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
 863
 864         if (!cd->trscer_err_mask)
 865                 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
 866 }
 867
 868 static int sh_eth_check_reset(struct net_device *ndev)
 869 {
 870         int ret = 0;
 871         int cnt = 100;
 872
 873         while (cnt > 0) {
 874                 if (!(sh_eth_read(ndev, EDMR) & 0x3))
 875                         break;
 876                 mdelay(1);
 877                 cnt--;
 878         }
 879         if (cnt <= 0) {
 880                 netdev_err(ndev, "Device reset failed\n");
 881                 ret = -ETIMEDOUT;
 882         }
 883         return ret;
 884 }
 885
 886 static int sh_eth_reset(struct net_device *ndev)
 887 {
 888         struct sh_eth_private *mdp = netdev_priv(ndev);
 889         int ret = 0;
 890
 891         if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
 892                 sh_eth_write(ndev, EDSR_ENALL, EDSR);
 893                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
 894                              EDMR);
 895
 896                 ret = sh_eth_check_reset(ndev);
 897                 if (ret)
 898                         return ret;
 899
 900                 /* Table Init */
 901                 sh_eth_write(ndev, 0x0, TDLAR);
 902                 sh_eth_write(ndev, 0x0, TDFAR);
 903                 sh_eth_write(ndev, 0x0, TDFXR);
 904                 sh_eth_write(ndev, 0x0, TDFFR);
 905                 sh_eth_write(ndev, 0x0, RDLAR);
 906                 sh_eth_write(ndev, 0x0, RDFAR);
 907                 sh_eth_write(ndev, 0x0, RDFXR);
 908                 sh_eth_write(ndev, 0x0, RDFFR);
 909
 910                 /* Reset HW CRC register */
 911                 if (mdp->cd->hw_crc)
 912                         sh_eth_write(ndev, 0x0, CSMR);
 913
 914                 /* Select MII mode */
 915                 if (mdp->cd->select_mii)
 916                         sh_eth_select_mii(ndev);
 917         } else {
 918                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
 919                              EDMR);
 920                 mdelay(3);
 921                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
 922                              EDMR);
 923         }
 924
 925         return ret;
 926 }
 927
 928 static void sh_eth_set_receive_align(struct sk_buff *skb)
 929 {
 930         uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
 931
 932         if (reserve)
 933                 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
 934 }
 935
 936
 937 /* CPU <-> EDMAC endian convert */
 938 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
 939 {
 940         switch (mdp->edmac_endian) {
 941         case EDMAC_LITTLE_ENDIAN:
 942                 return cpu_to_le32(x);
 943         case EDMAC_BIG_ENDIAN:
 944                 return cpu_to_be32(x);
 945         }
 946         return x;
 947 }
 948
 949 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
 950 {
 951         switch (mdp->edmac_endian) {
 952         case EDMAC_LITTLE_ENDIAN:
 953                 return le32_to_cpu(x);
 954         case EDMAC_BIG_ENDIAN:
 955                 return be32_to_cpu(x);
 956         }
 957         return x;
 958 }
 959
 960 /* Program the hardware MAC address from dev->dev_addr. */
 961 static void update_mac_address(struct net_device *ndev)
 962 {
 963         sh_eth_write(ndev,
 964                      (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
 965                      (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
 966         sh_eth_write(ndev,
 967                      (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
 968 }
 969
 970 /* Get MAC address from SuperH MAC address register
 971  *
 972  * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
 973  * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
 974  * When you want use this device, you must set MAC address in bootloader.
 975  *
 976  */
 977 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
 978 {
 979         if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
 980                 memcpy(ndev->dev_addr, mac, ETH_ALEN);
 981         } else {
 982                 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
 983                 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
 984                 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
 985                 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
 986                 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
 987                 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
 988         }
 989 }
 990
 991 static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
 992 {
 993         if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
 994                 return EDTRR_TRNS_GETHER;
 995         else
 996                 return EDTRR_TRNS_ETHER;
 997 }
 998
 999 struct bb_info {
1000         void (*set_gate)(void *addr);
1001         struct mdiobb_ctrl ctrl;
1002         void *addr;
1003         u32 mmd_msk;/* MMD */
1004         u32 mdo_msk;
1005         u32 mdi_msk;
1006         u32 mdc_msk;
1007 };
1008
1009 /* PHY bit set */
1010 static void bb_set(void *addr, u32 msk)
1011 {
1012         iowrite32(ioread32(addr) | msk, addr);
1013 }
1014
1015 /* PHY bit clear */
1016 static void bb_clr(void *addr, u32 msk)
1017 {
1018         iowrite32((ioread32(addr) & ~msk), addr);
1019 }
1020
1021 /* PHY bit read */
1022 static int bb_read(void *addr, u32 msk)
1023 {
1024         return (ioread32(addr) & msk) != 0;
1025 }
1026
1027 /* Data I/O pin control */
1028 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1029 {
1030         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1031
1032         if (bitbang->set_gate)
1033                 bitbang->set_gate(bitbang->addr);
1034
1035         if (bit)
1036                 bb_set(bitbang->addr, bitbang->mmd_msk);
1037         else
1038                 bb_clr(bitbang->addr, bitbang->mmd_msk);
1039 }
1040
1041 /* Set bit data*/
1042 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1043 {
1044         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1045
1046         if (bitbang->set_gate)
1047                 bitbang->set_gate(bitbang->addr);
1048
1049         if (bit)
1050                 bb_set(bitbang->addr, bitbang->mdo_msk);
1051         else
1052                 bb_clr(bitbang->addr, bitbang->mdo_msk);
1053 }
1054
1055 /* Get bit data*/
1056 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1057 {
1058         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1059
1060         if (bitbang->set_gate)
1061                 bitbang->set_gate(bitbang->addr);
1062
1063         return bb_read(bitbang->addr, bitbang->mdi_msk);
1064 }
1065
1066 /* MDC pin control */
1067 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1068 {
1069         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1070
1071         if (bitbang->set_gate)
1072                 bitbang->set_gate(bitbang->addr);
1073
1074         if (bit)
1075                 bb_set(bitbang->addr, bitbang->mdc_msk);
1076         else
1077                 bb_clr(bitbang->addr, bitbang->mdc_msk);
1078 }
1079
1080 /* mdio bus control struct */
1081 static struct mdiobb_ops bb_ops = {
1082         .owner = THIS_MODULE,
1083         .set_mdc = sh_mdc_ctrl,
1084         .set_mdio_dir = sh_mmd_ctrl,
1085         .set_mdio_data = sh_set_mdio,
1086         .get_mdio_data = sh_get_mdio,
1087 };
1088
1089 /* free skb and descriptor buffer */
1090 static void sh_eth_ring_free(struct net_device *ndev)
1091 {
1092         struct sh_eth_private *mdp = netdev_priv(ndev);
1093         int i;
1094
1095         /* Free Rx skb ringbuffer */
1096         if (mdp->rx_skbuff) {
1097                 for (i = 0; i < mdp->num_rx_ring; i++)
1098                         dev_kfree_skb(mdp->rx_skbuff[i]);
1099         }
1100         kfree(mdp->rx_skbuff);
1101         mdp->rx_skbuff = NULL;
1102
1103         /* Free Tx skb ringbuffer */
1104         if (mdp->tx_skbuff) {
1105                 for (i = 0; i < mdp->num_tx_ring; i++)
1106                         dev_kfree_skb(mdp->tx_skbuff[i]);
1107         }
1108         kfree(mdp->tx_skbuff);
1109         mdp->tx_skbuff = NULL;
1110 }
1111
1112 /* format skb and descriptor buffer */
1113 static void sh_eth_ring_format(struct net_device *ndev)
1114 {
1115         struct sh_eth_private *mdp = netdev_priv(ndev);
1116         int i;
1117         struct sk_buff *skb;
1118         struct sh_eth_rxdesc *rxdesc = NULL;
1119         struct sh_eth_txdesc *txdesc = NULL;
1120         int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1121         int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1122         int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN - 1;
1123
1124         mdp->cur_rx = 0;
1125         mdp->cur_tx = 0;
1126         mdp->dirty_rx = 0;
1127         mdp->dirty_tx = 0;
1128
1129         memset(mdp->rx_ring, 0, rx_ringsize);
1130
1131         /* build Rx ring buffer */
1132         for (i = 0; i < mdp->num_rx_ring; i++) {
1133                 /* skb */
1134                 mdp->rx_skbuff[i] = NULL;
1135                 skb = netdev_alloc_skb(ndev, skbuff_size);
1136                 mdp->rx_skbuff[i] = skb;
1137                 if (skb == NULL)
1138                         break;
1139                 sh_eth_set_receive_align(skb);
1140
1141                 /* RX descriptor */
1142                 rxdesc = &mdp->rx_ring[i];
1143                 /* The size of the buffer is a multiple of 16 bytes. */
1144                 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1145                 dma_map_single(&ndev->dev, skb->data, rxdesc->buffer_length,
1146                                DMA_FROM_DEVICE);
1147                 rxdesc->addr = virt_to_phys(skb->data);
1148                 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1149
1150                 /* Rx descriptor address set */
1151                 if (i == 0) {
1152                         sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1153                         if (sh_eth_is_gether(mdp) ||
1154                             sh_eth_is_rz_fast_ether(mdp))
1155                                 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1156                 }
1157         }
1158
1159         mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1160
1161         /* Mark the last entry as wrapping the ring. */
1162         rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
1163
1164         memset(mdp->tx_ring, 0, tx_ringsize);
1165
1166         /* build Tx ring buffer */
1167         for (i = 0; i < mdp->num_tx_ring; i++) {
1168                 mdp->tx_skbuff[i] = NULL;
1169                 txdesc = &mdp->tx_ring[i];
1170                 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1171                 txdesc->buffer_length = 0;
1172                 if (i == 0) {
1173                         /* Tx descriptor address set */
1174                         sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1175                         if (sh_eth_is_gether(mdp) ||
1176                             sh_eth_is_rz_fast_ether(mdp))
1177                                 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1178                 }
1179         }
1180
1181         txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1182 }
1183
1184 /* Get skb and descriptor buffer */
1185 static int sh_eth_ring_init(struct net_device *ndev)
1186 {
1187         struct sh_eth_private *mdp = netdev_priv(ndev);
1188         int rx_ringsize, tx_ringsize, ret = 0;
1189
1190         /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1191          * card needs room to do 8 byte alignment, +2 so we can reserve
1192          * the first 2 bytes, and +16 gets room for the status word from the
1193          * card.
1194          */
1195         mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1196                           (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1197         if (mdp->cd->rpadir)
1198                 mdp->rx_buf_sz += NET_IP_ALIGN;
1199
1200         /* Allocate RX and TX skb rings */
1201         mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring,
1202                                        sizeof(*mdp->rx_skbuff), GFP_KERNEL);
1203         if (!mdp->rx_skbuff) {
1204                 ret = -ENOMEM;
1205                 return ret;
1206         }
1207
1208         mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring,
1209                                        sizeof(*mdp->tx_skbuff), GFP_KERNEL);
1210         if (!mdp->tx_skbuff) {
1211                 ret = -ENOMEM;
1212                 goto skb_ring_free;
1213         }
1214
1215         /* Allocate all Rx descriptors. */
1216         rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1217         mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1218                                           GFP_KERNEL);
1219         if (!mdp->rx_ring) {
1220                 ret = -ENOMEM;
1221                 goto desc_ring_free;
1222         }
1223
1224         mdp->dirty_rx = 0;
1225
1226         /* Allocate all Tx descriptors. */
1227         tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1228         mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1229                                           GFP_KERNEL);
1230         if (!mdp->tx_ring) {
1231                 ret = -ENOMEM;
1232                 goto desc_ring_free;
1233         }
1234         return ret;
1235
1236 desc_ring_free:
1237         /* free DMA buffer */
1238         dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1239
1240 skb_ring_free:
1241         /* Free Rx and Tx skb ring buffer */
1242         sh_eth_ring_free(ndev);
1243         mdp->tx_ring = NULL;
1244         mdp->rx_ring = NULL;
1245
1246         return ret;
1247 }
1248
1249 static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp)
1250 {
1251         int ringsize;
1252
1253         if (mdp->rx_ring) {
1254                 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1255                 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1256                                   mdp->rx_desc_dma);
1257                 mdp->rx_ring = NULL;
1258         }
1259
1260         if (mdp->tx_ring) {
1261                 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1262                 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1263                                   mdp->tx_desc_dma);
1264                 mdp->tx_ring = NULL;
1265         }
1266 }
1267
1268 static int sh_eth_dev_init(struct net_device *ndev, bool start)
1269 {
1270         int ret = 0;
1271         struct sh_eth_private *mdp = netdev_priv(ndev);
1272         u32 val;
1273
1274         /* Soft Reset */
1275         ret = sh_eth_reset(ndev);
1276         if (ret)
1277                 return ret;
1278
1279         if (mdp->cd->rmiimode)
1280                 sh_eth_write(ndev, 0x1, RMIIMODE);
1281
1282         /* Descriptor format */
1283         sh_eth_ring_format(ndev);
1284         if (mdp->cd->rpadir)
1285                 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1286
1287         /* all sh_eth int mask */
1288         sh_eth_write(ndev, 0, EESIPR);
1289
1290 #if defined(__LITTLE_ENDIAN)
1291         if (mdp->cd->hw_swap)
1292                 sh_eth_write(ndev, EDMR_EL, EDMR);
1293         else
1294 #endif
1295                 sh_eth_write(ndev, 0, EDMR);
1296
1297         /* FIFO size set */
1298         sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1299         sh_eth_write(ndev, 0, TFTR);
1300
1301         /* Frame recv control (enable multiple-packets per rx irq) */
1302         sh_eth_write(ndev, RMCR_RNC, RMCR);
1303
1304         sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
1305
1306         if (mdp->cd->bculr)
1307                 sh_eth_write(ndev, 0x800, BCULR);       /* Burst sycle set */
1308
1309         sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1310
1311         if (!mdp->cd->no_trimd)
1312                 sh_eth_write(ndev, 0, TRIMD);
1313
1314         /* Recv frame limit set register */
1315         sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1316                      RFLR);
1317
1318         sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
1319         if (start) {
1320                 mdp->irq_enabled = true;
1321                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1322         }
1323
1324         /* PAUSE Prohibition */
1325         val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
1326                 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1327
1328         sh_eth_write(ndev, val, ECMR);
1329
1330         if (mdp->cd->set_rate)
1331                 mdp->cd->set_rate(ndev);
1332
1333         /* E-MAC Status Register clear */
1334         sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1335
1336         /* E-MAC Interrupt Enable register */
1337         if (start)
1338                 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1339
1340         /* Set MAC address */
1341         update_mac_address(ndev);
1342
1343         /* mask reset */
1344         if (mdp->cd->apr)
1345                 sh_eth_write(ndev, APR_AP, APR);
1346         if (mdp->cd->mpr)
1347                 sh_eth_write(ndev, MPR_MP, MPR);
1348         if (mdp->cd->tpauser)
1349                 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1350
1351         if (start) {
1352                 /* Setting the Rx mode will start the Rx process. */
1353                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1354
1355                 netif_start_queue(ndev);
1356         }
1357
1358         return ret;
1359 }
1360
1361 /* free Tx skb function */
1362 static int sh_eth_txfree(struct net_device *ndev)
1363 {
1364         struct sh_eth_private *mdp = netdev_priv(ndev);
1365         struct sh_eth_txdesc *txdesc;
1366         int free_num = 0;
1367         int entry = 0;
1368
1369         for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1370                 entry = mdp->dirty_tx % mdp->num_tx_ring;
1371                 txdesc = &mdp->tx_ring[entry];
1372                 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
1373                         break;
1374                 /* Free the original skb. */
1375                 if (mdp->tx_skbuff[entry]) {
1376                         dma_unmap_single(&ndev->dev, txdesc->addr,
1377                                          txdesc->buffer_length, DMA_TO_DEVICE);
1378                         dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1379                         mdp->tx_skbuff[entry] = NULL;
1380                         free_num++;
1381                 }
1382                 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1383                 if (entry >= mdp->num_tx_ring - 1)
1384                         txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1385
1386                 ndev->stats.tx_packets++;
1387                 ndev->stats.tx_bytes += txdesc->buffer_length;
1388         }
1389         return free_num;
1390 }
1391
1392 /* Packet receive function */
1393 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1394 {
1395         struct sh_eth_private *mdp = netdev_priv(ndev);
1396         struct sh_eth_rxdesc *rxdesc;
1397
1398         int entry = mdp->cur_rx % mdp->num_rx_ring;
1399         int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1400         int limit;
1401         struct sk_buff *skb;
1402         u16 pkt_len = 0;
1403         u32 desc_status;
1404         int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN - 1;
1405
1406         boguscnt = min(boguscnt, *quota);
1407         limit = boguscnt;
1408         rxdesc = &mdp->rx_ring[entry];
1409         while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1410                 desc_status = edmac_to_cpu(mdp, rxdesc->status);
1411                 pkt_len = rxdesc->frame_length;
1412
1413                 if (--boguscnt < 0)
1414                         break;
1415
1416                 if (!(desc_status & RDFEND))
1417                         ndev->stats.rx_length_errors++;
1418
1419                 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1420                  * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1421                  * bit 0. However, in case of the R8A7740, R8A779x, and
1422                  * R7S72100 the RFS bits are from bit 25 to bit 16. So, the
1423                  * driver needs right shifting by 16.
1424                  */
1425                 if (mdp->cd->shift_rd0)
1426                         desc_status >>= 16;
1427
1428                 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1429                                    RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1430                         ndev->stats.rx_errors++;
1431                         if (desc_status & RD_RFS1)
1432                                 ndev->stats.rx_crc_errors++;
1433                         if (desc_status & RD_RFS2)
1434                                 ndev->stats.rx_frame_errors++;
1435                         if (desc_status & RD_RFS3)
1436                                 ndev->stats.rx_length_errors++;
1437                         if (desc_status & RD_RFS4)
1438                                 ndev->stats.rx_length_errors++;
1439                         if (desc_status & RD_RFS6)
1440                                 ndev->stats.rx_missed_errors++;
1441                         if (desc_status & RD_RFS10)
1442                                 ndev->stats.rx_over_errors++;
1443                 } else {
1444                         if (!mdp->cd->hw_swap)
1445                                 sh_eth_soft_swap(
1446                                         phys_to_virt(ALIGN(rxdesc->addr, 4)),
1447                                         pkt_len + 2);
1448                         skb = mdp->rx_skbuff[entry];
1449                         mdp->rx_skbuff[entry] = NULL;
1450                         if (mdp->cd->rpadir)
1451                                 skb_reserve(skb, NET_IP_ALIGN);
1452                         dma_sync_single_for_cpu(&ndev->dev, rxdesc->addr,
1453                                                 ALIGN(mdp->rx_buf_sz, 16),
1454                                                 DMA_FROM_DEVICE);
1455                         skb_put(skb, pkt_len);
1456                         skb->protocol = eth_type_trans(skb, ndev);
1457                         netif_receive_skb(skb);
1458                         ndev->stats.rx_packets++;
1459                         ndev->stats.rx_bytes += pkt_len;
1460                 }
1461                 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1462                 rxdesc = &mdp->rx_ring[entry];
1463         }
1464
1465         /* Refill the Rx ring buffers. */
1466         for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1467                 entry = mdp->dirty_rx % mdp->num_rx_ring;
1468                 rxdesc = &mdp->rx_ring[entry];
1469                 /* The size of the buffer is 16 byte boundary. */
1470                 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1471
1472                 if (mdp->rx_skbuff[entry] == NULL) {
1473                         skb = netdev_alloc_skb(ndev, skbuff_size);
1474                         mdp->rx_skbuff[entry] = skb;
1475                         if (skb == NULL)
1476                                 break;  /* Better luck next round. */
1477                         sh_eth_set_receive_align(skb);
1478                         dma_map_single(&ndev->dev, skb->data,
1479                                        rxdesc->buffer_length, DMA_FROM_DEVICE);
1480
1481                         skb_checksum_none_assert(skb);
1482                         rxdesc->addr = virt_to_phys(skb->data);
1483                 }
1484                 if (entry >= mdp->num_rx_ring - 1)
1485                         rxdesc->status |=
1486                                 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
1487                 else
1488                         rxdesc->status |=
1489                                 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1490         }
1491
1492         /* Restart Rx engine if stopped. */
1493         /* If we don't need to check status, don't. -KDU */
1494         if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1495                 /* fix the values for the next receiving if RDE is set */
1496                 if (intr_status & EESR_RDE) {
1497                         u32 count = (sh_eth_read(ndev, RDFAR) -
1498                                      sh_eth_read(ndev, RDLAR)) >> 4;
1499
1500                         mdp->cur_rx = count;
1501                         mdp->dirty_rx = count;
1502                 }
1503                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1504         }
1505
1506         *quota -= limit - boguscnt - 1;
1507
1508         return *quota <= 0;
1509 }
1510
1511 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1512 {
1513         /* disable tx and rx */
1514         sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1515                 ~(ECMR_RE | ECMR_TE), ECMR);
1516 }
1517
1518 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1519 {
1520         /* enable tx and rx */
1521         sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1522                 (ECMR_RE | ECMR_TE), ECMR);
1523 }
1524
1525 /* error control function */
1526 static void sh_eth_error(struct net_device *ndev, int intr_status)
1527 {
1528         struct sh_eth_private *mdp = netdev_priv(ndev);
1529         u32 felic_stat;
1530         u32 link_stat;
1531         u32 mask;
1532
1533         if (intr_status & EESR_ECI) {
1534                 felic_stat = sh_eth_read(ndev, ECSR);
1535                 sh_eth_write(ndev, felic_stat, ECSR);   /* clear int */
1536                 if (felic_stat & ECSR_ICD)
1537                         ndev->stats.tx_carrier_errors++;
1538                 if (felic_stat & ECSR_LCHNG) {
1539                         /* Link Changed */
1540                         if (mdp->cd->no_psr || mdp->no_ether_link) {
1541                                 goto ignore_link;
1542                         } else {
1543                                 link_stat = (sh_eth_read(ndev, PSR));
1544                                 if (mdp->ether_link_active_low)
1545                                         link_stat = ~link_stat;
1546                         }
1547                         if (!(link_stat & PHY_ST_LINK)) {
1548                                 sh_eth_rcv_snd_disable(ndev);
1549                         } else {
1550                                 /* Link Up */
1551                                 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1552                                                    ~DMAC_M_ECI, EESIPR);
1553                                 /* clear int */
1554                                 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1555                                              ECSR);
1556                                 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1557                                                    DMAC_M_ECI, EESIPR);
1558                                 /* enable tx and rx */
1559                                 sh_eth_rcv_snd_enable(ndev);
1560                         }
1561                 }
1562         }
1563
1564 ignore_link:
1565         if (intr_status & EESR_TWB) {
1566                 /* Unused write back interrupt */
1567                 if (intr_status & EESR_TABT) {  /* Transmit Abort int */
1568                         ndev->stats.tx_aborted_errors++;
1569                         netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1570                 }
1571         }
1572
1573         if (intr_status & EESR_RABT) {
1574                 /* Receive Abort int */
1575                 if (intr_status & EESR_RFRMER) {
1576                         /* Receive Frame Overflow int */
1577                         ndev->stats.rx_frame_errors++;
1578                         netif_err(mdp, rx_err, ndev, "Receive Abort\n");
1579                 }
1580         }
1581
1582         if (intr_status & EESR_TDE) {
1583                 /* Transmit Descriptor Empty int */
1584                 ndev->stats.tx_fifo_errors++;
1585                 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1586         }
1587
1588         if (intr_status & EESR_TFE) {
1589                 /* FIFO under flow */
1590                 ndev->stats.tx_fifo_errors++;
1591                 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1592         }
1593
1594         if (intr_status & EESR_RDE) {
1595                 /* Receive Descriptor Empty int */
1596                 ndev->stats.rx_over_errors++;
1597                 netif_err(mdp, rx_err, ndev, "Receive Descriptor Empty\n");
1598         }
1599
1600         if (intr_status & EESR_RFE) {
1601                 /* Receive FIFO Overflow int */
1602                 ndev->stats.rx_fifo_errors++;
1603                 netif_err(mdp, rx_err, ndev, "Receive FIFO Overflow\n");
1604         }
1605
1606         if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1607                 /* Address Error */
1608                 ndev->stats.tx_fifo_errors++;
1609                 netif_err(mdp, tx_err, ndev, "Address Error\n");
1610         }
1611
1612         mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1613         if (mdp->cd->no_ade)
1614                 mask &= ~EESR_ADE;
1615         if (intr_status & mask) {
1616                 /* Tx error */
1617                 u32 edtrr = sh_eth_read(ndev, EDTRR);
1618
1619                 /* dmesg */
1620                 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1621                            intr_status, mdp->cur_tx, mdp->dirty_tx,
1622                            (u32)ndev->state, edtrr);
1623                 /* dirty buffer free */
1624                 sh_eth_txfree(ndev);
1625
1626                 /* SH7712 BUG */
1627                 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1628                         /* tx dma start */
1629                         sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1630                 }
1631                 /* wakeup */
1632                 netif_wake_queue(ndev);
1633         }
1634 }
1635
1636 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1637 {
1638         struct net_device *ndev = netdev;
1639         struct sh_eth_private *mdp = netdev_priv(ndev);
1640         struct sh_eth_cpu_data *cd = mdp->cd;
1641         irqreturn_t ret = IRQ_NONE;
1642         unsigned long intr_status, intr_enable;
1643
1644         spin_lock(&mdp->lock);
1645
1646         /* Get interrupt status */
1647         intr_status = sh_eth_read(ndev, EESR);
1648         /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1649          * enabled since it's the one that  comes thru regardless of the mask,
1650          * and we need to fully handle it in sh_eth_error() in order to quench
1651          * it as it doesn't get cleared by just writing 1 to the ECI bit...
1652          */
1653         intr_enable = sh_eth_read(ndev, EESIPR);
1654         intr_status &= intr_enable | DMAC_M_ECI;
1655         if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
1656                 ret = IRQ_HANDLED;
1657         else
1658                 goto out;
1659
1660         if (!likely(mdp->irq_enabled)) {
1661                 sh_eth_write(ndev, 0, EESIPR);
1662                 goto out;
1663         }
1664
1665         if (intr_status & EESR_RX_CHECK) {
1666                 if (napi_schedule_prep(&mdp->napi)) {
1667                         /* Mask Rx interrupts */
1668                         sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1669                                      EESIPR);
1670                         __napi_schedule(&mdp->napi);
1671                 } else {
1672                         netdev_warn(ndev,
1673                                     "ignoring interrupt, status 0x%08lx, mask 0x%08lx.\n",
1674                                     intr_status, intr_enable);
1675                 }
1676         }
1677
1678         /* Tx Check */
1679         if (intr_status & cd->tx_check) {
1680                 /* Clear Tx interrupts */
1681                 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1682
1683                 sh_eth_txfree(ndev);
1684                 netif_wake_queue(ndev);
1685         }
1686
1687         if (intr_status & cd->eesr_err_check) {
1688                 /* Clear error interrupts */
1689                 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1690
1691                 sh_eth_error(ndev, intr_status);
1692         }
1693
1694 out:
1695         spin_unlock(&mdp->lock);
1696
1697         return ret;
1698 }
1699
1700 static int sh_eth_poll(struct napi_struct *napi, int budget)
1701 {
1702         struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1703                                                   napi);
1704         struct net_device *ndev = napi->dev;
1705         int quota = budget;
1706         unsigned long intr_status;
1707
1708         for (;;) {
1709                 intr_status = sh_eth_read(ndev, EESR);
1710                 if (!(intr_status & EESR_RX_CHECK))
1711                         break;
1712                 /* Clear Rx interrupts */
1713                 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1714
1715                 if (sh_eth_rx(ndev, intr_status, &quota))
1716                         goto out;
1717         }
1718
1719         napi_complete(napi);
1720
1721         /* Reenable Rx interrupts */
1722         if (mdp->irq_enabled)
1723                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1724 out:
1725         return budget - quota;
1726 }
1727
1728 /* PHY state control function */
1729 static void sh_eth_adjust_link(struct net_device *ndev)
1730 {
1731         struct sh_eth_private *mdp = netdev_priv(ndev);
1732         struct phy_device *phydev = mdp->phydev;
1733         int new_state = 0;
1734
1735         if (phydev->link) {
1736                 if (phydev->duplex != mdp->duplex) {
1737                         new_state = 1;
1738                         mdp->duplex = phydev->duplex;
1739                         if (mdp->cd->set_duplex)
1740                                 mdp->cd->set_duplex(ndev);
1741                 }
1742
1743                 if (phydev->speed != mdp->speed) {
1744                         new_state = 1;
1745                         mdp->speed = phydev->speed;
1746                         if (mdp->cd->set_rate)
1747                                 mdp->cd->set_rate(ndev);
1748                 }
1749                 if (!mdp->link) {
1750                         sh_eth_write(ndev,
1751                                      sh_eth_read(ndev, ECMR) & ~ECMR_TXF,
1752                                      ECMR);
1753                         new_state = 1;
1754                         mdp->link = phydev->link;
1755                         if (mdp->cd->no_psr || mdp->no_ether_link)
1756                                 sh_eth_rcv_snd_enable(ndev);
1757                 }
1758         } else if (mdp->link) {
1759                 new_state = 1;
1760                 mdp->link = 0;
1761                 mdp->speed = 0;
1762                 mdp->duplex = -1;
1763                 if (mdp->cd->no_psr || mdp->no_ether_link)
1764                         sh_eth_rcv_snd_disable(ndev);
1765         }
1766
1767         if (new_state && netif_msg_link(mdp))
1768                 phy_print_status(phydev);
1769 }
1770
1771 /* PHY init function */
1772 static int sh_eth_phy_init(struct net_device *ndev)
1773 {
1774         struct device_node *np = ndev->dev.parent->of_node;
1775         struct sh_eth_private *mdp = netdev_priv(ndev);
1776         struct phy_device *phydev = NULL;
1777
1778         mdp->link = 0;
1779         mdp->speed = 0;
1780         mdp->duplex = -1;
1781
1782         /* Try connect to PHY */
1783         if (np) {
1784                 struct device_node *pn;
1785
1786                 pn = of_parse_phandle(np, "phy-handle", 0);
1787                 phydev = of_phy_connect(ndev, pn,
1788                                         sh_eth_adjust_link, 0,
1789                                         mdp->phy_interface);
1790
1791                 if (!phydev)
1792                         phydev = ERR_PTR(-ENOENT);
1793         } else {
1794                 char phy_id[MII_BUS_ID_SIZE + 3];
1795
1796                 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1797                          mdp->mii_bus->id, mdp->phy_id);
1798
1799                 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1800                                      mdp->phy_interface);
1801         }
1802
1803         if (IS_ERR(phydev)) {
1804                 netdev_err(ndev, "failed to connect PHY\n");
1805                 return PTR_ERR(phydev);
1806         }
1807
1808         netdev_info(ndev, "attached PHY %d (IRQ %d) to driver %s\n",
1809                     phydev->addr, phydev->irq, phydev->drv->name);
1810
1811         mdp->phydev = phydev;
1812
1813         return 0;
1814 }
1815
1816 /* PHY control start function */
1817 static int sh_eth_phy_start(struct net_device *ndev)
1818 {
1819         struct sh_eth_private *mdp = netdev_priv(ndev);
1820         int ret;
1821
1822         ret = sh_eth_phy_init(ndev);
1823         if (ret)
1824                 return ret;
1825
1826         phy_start(mdp->phydev);
1827
1828         return 0;
1829 }
1830
1831 static int sh_eth_get_settings(struct net_device *ndev,
1832                                struct ethtool_cmd *ecmd)
1833 {
1834         struct sh_eth_private *mdp = netdev_priv(ndev);
1835         unsigned long flags;
1836         int ret;
1837
1838         if (!mdp->phydev)
1839                 return -ENODEV;
1840
1841         spin_lock_irqsave(&mdp->lock, flags);
1842         ret = phy_ethtool_gset(mdp->phydev, ecmd);
1843         spin_unlock_irqrestore(&mdp->lock, flags);
1844
1845         return ret;
1846 }
1847
1848 static int sh_eth_set_settings(struct net_device *ndev,
1849                                struct ethtool_cmd *ecmd)
1850 {
1851         struct sh_eth_private *mdp = netdev_priv(ndev);
1852         unsigned long flags;
1853         int ret;
1854
1855         if (!mdp->phydev)
1856                 return -ENODEV;
1857
1858         spin_lock_irqsave(&mdp->lock, flags);
1859
1860         /* disable tx and rx */
1861         sh_eth_rcv_snd_disable(ndev);
1862
1863         ret = phy_ethtool_sset(mdp->phydev, ecmd);
1864         if (ret)
1865                 goto error_exit;
1866
1867         if (ecmd->duplex == DUPLEX_FULL)
1868                 mdp->duplex = 1;
1869         else
1870                 mdp->duplex = 0;
1871
1872         if (mdp->cd->set_duplex)
1873                 mdp->cd->set_duplex(ndev);
1874
1875 error_exit:
1876         mdelay(1);
1877
1878         /* enable tx and rx */
1879         sh_eth_rcv_snd_enable(ndev);
1880
1881         spin_unlock_irqrestore(&mdp->lock, flags);
1882
1883         return ret;
1884 }
1885
1886 static int sh_eth_nway_reset(struct net_device *ndev)
1887 {
1888         struct sh_eth_private *mdp = netdev_priv(ndev);
1889         unsigned long flags;
1890         int ret;
1891
1892         if (!mdp->phydev)
1893                 return -ENODEV;
1894
1895         spin_lock_irqsave(&mdp->lock, flags);
1896         ret = phy_start_aneg(mdp->phydev);
1897         spin_unlock_irqrestore(&mdp->lock, flags);
1898
1899         return ret;
1900 }
1901
1902 static u32 sh_eth_get_msglevel(struct net_device *ndev)
1903 {
1904         struct sh_eth_private *mdp = netdev_priv(ndev);
1905         return mdp->msg_enable;
1906 }
1907
1908 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1909 {
1910         struct sh_eth_private *mdp = netdev_priv(ndev);
1911         mdp->msg_enable = value;
1912 }
1913
1914 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1915         "rx_current", "tx_current",
1916         "rx_dirty", "tx_dirty",
1917 };
1918 #define SH_ETH_STATS_LEN  ARRAY_SIZE(sh_eth_gstrings_stats)
1919
1920 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1921 {
1922         switch (sset) {
1923         case ETH_SS_STATS:
1924                 return SH_ETH_STATS_LEN;
1925         default:
1926                 return -EOPNOTSUPP;
1927         }
1928 }
1929
1930 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
1931                                      struct ethtool_stats *stats, u64 *data)
1932 {
1933         struct sh_eth_private *mdp = netdev_priv(ndev);
1934         int i = 0;
1935
1936         /* device-specific stats */
1937         data[i++] = mdp->cur_rx;
1938         data[i++] = mdp->cur_tx;
1939         data[i++] = mdp->dirty_rx;
1940         data[i++] = mdp->dirty_tx;
1941 }
1942
1943 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1944 {
1945         switch (stringset) {
1946         case ETH_SS_STATS:
1947                 memcpy(data, *sh_eth_gstrings_stats,
1948                        sizeof(sh_eth_gstrings_stats));
1949                 break;
1950         }
1951 }
1952
1953 static void sh_eth_get_ringparam(struct net_device *ndev,
1954                                  struct ethtool_ringparam *ring)
1955 {
1956         struct sh_eth_private *mdp = netdev_priv(ndev);
1957
1958         ring->rx_max_pending = RX_RING_MAX;
1959         ring->tx_max_pending = TX_RING_MAX;
1960         ring->rx_pending = mdp->num_rx_ring;
1961         ring->tx_pending = mdp->num_tx_ring;
1962 }
1963
1964 static int sh_eth_set_ringparam(struct net_device *ndev,
1965                                 struct ethtool_ringparam *ring)
1966 {
1967         struct sh_eth_private *mdp = netdev_priv(ndev);
1968         int ret;
1969
1970         if (ring->tx_pending > TX_RING_MAX ||
1971             ring->rx_pending > RX_RING_MAX ||
1972             ring->tx_pending < TX_RING_MIN ||
1973             ring->rx_pending < RX_RING_MIN)
1974                 return -EINVAL;
1975         if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1976                 return -EINVAL;
1977
1978         if (netif_running(ndev)) {
1979                 netif_device_detach(ndev);
1980                 netif_tx_disable(ndev);
1981
1982                 /* Serialise with the interrupt handler and NAPI, then
1983                  * disable interrupts.  We have to clear the
1984                  * irq_enabled flag first to ensure that interrupts
1985                  * won't be re-enabled.
1986                  */
1987                 mdp->irq_enabled = false;
1988                 synchronize_irq(ndev->irq);
1989                 napi_synchronize(&mdp->napi);
1990                 sh_eth_write(ndev, 0x0000, EESIPR);
1991
1992                 /* Stop the chip's Tx and Rx processes. */
1993                 sh_eth_write(ndev, 0, EDTRR);
1994                 sh_eth_write(ndev, 0, EDRRR);
1995
1996                 /* Free all the skbuffs in the Rx queue. */
1997                 sh_eth_ring_free(ndev);
1998                 /* Free DMA buffer */
1999                 sh_eth_free_dma_buffer(mdp);
2000         }
2001
2002         /* Set new parameters */
2003         mdp->num_rx_ring = ring->rx_pending;
2004         mdp->num_tx_ring = ring->tx_pending;
2005
2006         if (netif_running(ndev)) {
2007                 ret = sh_eth_ring_init(ndev);
2008                 if (ret < 0) {
2009                         netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2010                                    __func__);
2011                         return ret;
2012                 }
2013                 ret = sh_eth_dev_init(ndev, false);
2014                 if (ret < 0) {
2015                         netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2016                                    __func__);
2017                         return ret;
2018                 }
2019
2020                 mdp->irq_enabled = true;
2021                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
2022                 /* Setting the Rx mode will start the Rx process. */
2023                 sh_eth_write(ndev, EDRRR_R, EDRRR);
2024                 netif_device_attach(ndev);
2025         }
2026
2027         return 0;
2028 }
2029
2030 static const struct ethtool_ops sh_eth_ethtool_ops = {
2031         .get_settings   = sh_eth_get_settings,
2032         .set_settings   = sh_eth_set_settings,
2033         .nway_reset     = sh_eth_nway_reset,
2034         .get_msglevel   = sh_eth_get_msglevel,
2035         .set_msglevel   = sh_eth_set_msglevel,
2036         .get_link       = ethtool_op_get_link,
2037         .get_strings    = sh_eth_get_strings,
2038         .get_ethtool_stats  = sh_eth_get_ethtool_stats,
2039         .get_sset_count     = sh_eth_get_sset_count,
2040         .get_ringparam  = sh_eth_get_ringparam,
2041         .set_ringparam  = sh_eth_set_ringparam,
2042 };
2043
2044 /* network device open function */
2045 static int sh_eth_open(struct net_device *ndev)
2046 {
2047         int ret = 0;
2048         struct sh_eth_private *mdp = netdev_priv(ndev);
2049
2050         pm_runtime_get_sync(&mdp->pdev->dev);
2051
2052         napi_enable(&mdp->napi);
2053
2054         ret = request_irq(ndev->irq, sh_eth_interrupt,
2055                           mdp->cd->irq_flags, ndev->name, ndev);
2056         if (ret) {
2057                 netdev_err(ndev, "Can not assign IRQ number\n");
2058                 goto out_napi_off;
2059         }
2060
2061         /* Descriptor set */
2062         ret = sh_eth_ring_init(ndev);
2063         if (ret)
2064                 goto out_free_irq;
2065
2066         /* device init */
2067         ret = sh_eth_dev_init(ndev, true);
2068         if (ret)
2069                 goto out_free_irq;
2070
2071         /* PHY control start*/
2072         ret = sh_eth_phy_start(ndev);
2073         if (ret)
2074                 goto out_free_irq;
2075
2076         mdp->is_opened = 1;
2077
2078         return ret;
2079
2080 out_free_irq:
2081         free_irq(ndev->irq, ndev);
2082 out_napi_off:
2083         napi_disable(&mdp->napi);
2084         pm_runtime_put_sync(&mdp->pdev->dev);
2085         return ret;
2086 }
2087
2088 /* Timeout function */
2089 static void sh_eth_tx_timeout(struct net_device *ndev)
2090 {
2091         struct sh_eth_private *mdp = netdev_priv(ndev);
2092         struct sh_eth_rxdesc *rxdesc;
2093         int i;
2094
2095         netif_stop_queue(ndev);
2096
2097         netif_err(mdp, timer, ndev,
2098                   "transmit timed out, status %8.8x, resetting...\n",
2099                   (int)sh_eth_read(ndev, EESR));
2100
2101         /* tx_errors count up */
2102         ndev->stats.tx_errors++;
2103
2104         /* Free all the skbuffs in the Rx queue. */
2105         for (i = 0; i < mdp->num_rx_ring; i++) {
2106                 rxdesc = &mdp->rx_ring[i];
2107                 rxdesc->status = 0;
2108                 rxdesc->addr = 0xBADF00D0;
2109                 dev_kfree_skb(mdp->rx_skbuff[i]);
2110                 mdp->rx_skbuff[i] = NULL;
2111         }
2112         for (i = 0; i < mdp->num_tx_ring; i++) {
2113                 dev_kfree_skb(mdp->tx_skbuff[i]);
2114                 mdp->tx_skbuff[i] = NULL;
2115         }
2116
2117         /* device init */
2118         sh_eth_dev_init(ndev, true);
2119 }
2120
2121 /* Packet transmit function */
2122 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2123 {
2124         struct sh_eth_private *mdp = netdev_priv(ndev);
2125         struct sh_eth_txdesc *txdesc;
2126         u32 entry;
2127         unsigned long flags;
2128
2129         spin_lock_irqsave(&mdp->lock, flags);
2130         if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2131                 if (!sh_eth_txfree(ndev)) {
2132                         netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2133                         netif_stop_queue(ndev);
2134                         spin_unlock_irqrestore(&mdp->lock, flags);
2135                         return NETDEV_TX_BUSY;
2136                 }
2137         }
2138         spin_unlock_irqrestore(&mdp->lock, flags);
2139
2140         if (skb_padto(skb, ETH_ZLEN))
2141                 return NETDEV_TX_OK;
2142
2143         entry = mdp->cur_tx % mdp->num_tx_ring;
2144         mdp->tx_skbuff[entry] = skb;
2145         txdesc = &mdp->tx_ring[entry];
2146         /* soft swap. */
2147         if (!mdp->cd->hw_swap)
2148                 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
2149                                  skb->len + 2);
2150         txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2151                                       DMA_TO_DEVICE);
2152         txdesc->buffer_length = skb->len;
2153
2154         if (entry >= mdp->num_tx_ring - 1)
2155                 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
2156         else
2157                 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
2158
2159         mdp->cur_tx++;
2160
2161         if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2162                 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
2163
2164         return NETDEV_TX_OK;
2165 }
2166
2167 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2168 {
2169         struct sh_eth_private *mdp = netdev_priv(ndev);
2170
2171         if (sh_eth_is_rz_fast_ether(mdp))
2172                 return &ndev->stats;
2173
2174         if (!mdp->is_opened)
2175                 return &ndev->stats;
2176
2177         ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR);
2178         sh_eth_write(ndev, 0, TROCR);   /* (write clear) */
2179         ndev->stats.collisions += sh_eth_read(ndev, CDCR);
2180         sh_eth_write(ndev, 0, CDCR);    /* (write clear) */
2181         ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
2182         sh_eth_write(ndev, 0, LCCR);    /* (write clear) */
2183
2184         if (sh_eth_is_gether(mdp)) {
2185                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
2186                 sh_eth_write(ndev, 0, CERCR);   /* (write clear) */
2187                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
2188                 sh_eth_write(ndev, 0, CEECR);   /* (write clear) */
2189         } else {
2190                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
2191                 sh_eth_write(ndev, 0, CNDCR);   /* (write clear) */
2192         }
2193
2194         return &ndev->stats;
2195 }
2196
2197 /* device close function */
2198 static int sh_eth_close(struct net_device *ndev)
2199 {
2200         struct sh_eth_private *mdp = netdev_priv(ndev);
2201
2202         netif_stop_queue(ndev);
2203
2204         /* Serialise with the interrupt handler and NAPI, then disable
2205          * interrupts.  We have to clear the irq_enabled flag first to
2206          * ensure that interrupts won't be re-enabled.
2207          */
2208         mdp->irq_enabled = false;
2209         synchronize_irq(ndev->irq);
2210         napi_disable(&mdp->napi);
2211         sh_eth_write(ndev, 0x0000, EESIPR);
2212
2213         /* Stop the chip's Tx and Rx processes. */
2214         sh_eth_write(ndev, 0, EDTRR);
2215         sh_eth_write(ndev, 0, EDRRR);
2216
2217         sh_eth_get_stats(ndev);
2218         /* PHY Disconnect */
2219         if (mdp->phydev) {
2220                 phy_stop(mdp->phydev);
2221                 phy_disconnect(mdp->phydev);
2222                 mdp->phydev = NULL;
2223         }
2224
2225         free_irq(ndev->irq, ndev);
2226
2227         /* Free all the skbuffs in the Rx queue. */
2228         sh_eth_ring_free(ndev);
2229
2230         /* free DMA buffer */
2231         sh_eth_free_dma_buffer(mdp);
2232
2233         pm_runtime_put_sync(&mdp->pdev->dev);
2234
2235         mdp->is_opened = 0;
2236
2237         return 0;
2238 }
2239
2240 /* ioctl to device function */
2241 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2242 {
2243         struct sh_eth_private *mdp = netdev_priv(ndev);
2244         struct phy_device *phydev = mdp->phydev;
2245
2246         if (!netif_running(ndev))
2247                 return -EINVAL;
2248
2249         if (!phydev)
2250                 return -ENODEV;
2251
2252         return phy_mii_ioctl(phydev, rq, cmd);
2253 }
2254
2255 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2256 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2257                                             int entry)
2258 {
2259         return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2260 }
2261
2262 static u32 sh_eth_tsu_get_post_mask(int entry)
2263 {
2264         return 0x0f << (28 - ((entry % 8) * 4));
2265 }
2266
2267 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2268 {
2269         return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2270 }
2271
2272 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2273                                              int entry)
2274 {
2275         struct sh_eth_private *mdp = netdev_priv(ndev);
2276         u32 tmp;
2277         void *reg_offset;
2278
2279         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2280         tmp = ioread32(reg_offset);
2281         iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2282 }
2283
2284 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2285                                               int entry)
2286 {
2287         struct sh_eth_private *mdp = netdev_priv(ndev);
2288         u32 post_mask, ref_mask, tmp;
2289         void *reg_offset;
2290
2291         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2292         post_mask = sh_eth_tsu_get_post_mask(entry);
2293         ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2294
2295         tmp = ioread32(reg_offset);
2296         iowrite32(tmp & ~post_mask, reg_offset);
2297
2298         /* If other port enables, the function returns "true" */
2299         return tmp & ref_mask;
2300 }
2301
2302 static int sh_eth_tsu_busy(struct net_device *ndev)
2303 {
2304         int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2305         struct sh_eth_private *mdp = netdev_priv(ndev);
2306
2307         while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2308                 udelay(10);
2309                 timeout--;
2310                 if (timeout <= 0) {
2311                         netdev_err(ndev, "%s: timeout\n", __func__);
2312                         return -ETIMEDOUT;
2313                 }
2314         }
2315
2316         return 0;
2317 }
2318
2319 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2320                                   const u8 *addr)
2321 {
2322         u32 val;
2323
2324         val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2325         iowrite32(val, reg);
2326         if (sh_eth_tsu_busy(ndev) < 0)
2327                 return -EBUSY;
2328
2329         val = addr[4] << 8 | addr[5];
2330         iowrite32(val, reg + 4);
2331         if (sh_eth_tsu_busy(ndev) < 0)
2332                 return -EBUSY;
2333
2334         return 0;
2335 }
2336
2337 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2338 {
2339         u32 val;
2340
2341         val = ioread32(reg);
2342         addr[0] = (val >> 24) & 0xff;
2343         addr[1] = (val >> 16) & 0xff;
2344         addr[2] = (val >> 8) & 0xff;
2345         addr[3] = val & 0xff;
2346         val = ioread32(reg + 4);
2347         addr[4] = (val >> 8) & 0xff;
2348         addr[5] = val & 0xff;
2349 }
2350
2351
2352 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2353 {
2354         struct sh_eth_private *mdp = netdev_priv(ndev);
2355         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2356         int i;
2357         u8 c_addr[ETH_ALEN];
2358
2359         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2360                 sh_eth_tsu_read_entry(reg_offset, c_addr);
2361                 if (ether_addr_equal(addr, c_addr))
2362                         return i;
2363         }
2364
2365         return -ENOENT;
2366 }
2367
2368 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2369 {
2370         u8 blank[ETH_ALEN];
2371         int entry;
2372
2373         memset(blank, 0, sizeof(blank));
2374         entry = sh_eth_tsu_find_entry(ndev, blank);
2375         return (entry < 0) ? -ENOMEM : entry;
2376 }
2377
2378 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2379                                               int entry)
2380 {
2381         struct sh_eth_private *mdp = netdev_priv(ndev);
2382         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2383         int ret;
2384         u8 blank[ETH_ALEN];
2385
2386         sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2387                          ~(1 << (31 - entry)), TSU_TEN);
2388
2389         memset(blank, 0, sizeof(blank));
2390         ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2391         if (ret < 0)
2392                 return ret;
2393         return 0;
2394 }
2395
2396 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2397 {
2398         struct sh_eth_private *mdp = netdev_priv(ndev);
2399         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2400         int i, ret;
2401
2402         if (!mdp->cd->tsu)
2403                 return 0;
2404
2405         i = sh_eth_tsu_find_entry(ndev, addr);
2406         if (i < 0) {
2407                 /* No entry found, create one */
2408                 i = sh_eth_tsu_find_empty(ndev);
2409                 if (i < 0)
2410                         return -ENOMEM;
2411                 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2412                 if (ret < 0)
2413                         return ret;
2414
2415                 /* Enable the entry */
2416                 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2417                                  (1 << (31 - i)), TSU_TEN);
2418         }
2419
2420         /* Entry found or created, enable POST */
2421         sh_eth_tsu_enable_cam_entry_post(ndev, i);
2422
2423         return 0;
2424 }
2425
2426 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2427 {
2428         struct sh_eth_private *mdp = netdev_priv(ndev);
2429         int i, ret;
2430
2431         if (!mdp->cd->tsu)
2432                 return 0;
2433
2434         i = sh_eth_tsu_find_entry(ndev, addr);
2435         if (i) {
2436                 /* Entry found */
2437                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2438                         goto done;
2439
2440                 /* Disable the entry if both ports was disabled */
2441                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2442                 if (ret < 0)
2443                         return ret;
2444         }
2445 done:
2446         return 0;
2447 }
2448
2449 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2450 {
2451         struct sh_eth_private *mdp = netdev_priv(ndev);
2452         int i, ret;
2453
2454         if (!mdp->cd->tsu)
2455                 return 0;
2456
2457         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2458                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2459                         continue;
2460
2461                 /* Disable the entry if both ports was disabled */
2462                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2463                 if (ret < 0)
2464                         return ret;
2465         }
2466
2467         return 0;
2468 }
2469
2470 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2471 {
2472         struct sh_eth_private *mdp = netdev_priv(ndev);
2473         u8 addr[ETH_ALEN];
2474         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2475         int i;
2476
2477         if (!mdp->cd->tsu)
2478                 return;
2479
2480         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2481                 sh_eth_tsu_read_entry(reg_offset, addr);
2482                 if (is_multicast_ether_addr(addr))
2483                         sh_eth_tsu_del_entry(ndev, addr);
2484         }
2485 }
2486
2487 /* Update promiscuous flag and multicast filter */
2488 static void sh_eth_set_rx_mode(struct net_device *ndev)
2489 {
2490         struct sh_eth_private *mdp = netdev_priv(ndev);
2491         u32 ecmr_bits;
2492         int mcast_all = 0;
2493         unsigned long flags;
2494
2495         spin_lock_irqsave(&mdp->lock, flags);
2496         /* Initial condition is MCT = 1, PRM = 0.
2497          * Depending on ndev->flags, set PRM or clear MCT
2498          */
2499         ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2500         if (mdp->cd->tsu)
2501                 ecmr_bits |= ECMR_MCT;
2502
2503         if (!(ndev->flags & IFF_MULTICAST)) {
2504                 sh_eth_tsu_purge_mcast(ndev);
2505                 mcast_all = 1;
2506         }
2507         if (ndev->flags & IFF_ALLMULTI) {
2508                 sh_eth_tsu_purge_mcast(ndev);
2509                 ecmr_bits &= ~ECMR_MCT;
2510                 mcast_all = 1;
2511         }
2512
2513         if (ndev->flags & IFF_PROMISC) {
2514                 sh_eth_tsu_purge_all(ndev);
2515                 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2516         } else if (mdp->cd->tsu) {
2517                 struct netdev_hw_addr *ha;
2518                 netdev_for_each_mc_addr(ha, ndev) {
2519                         if (mcast_all && is_multicast_ether_addr(ha->addr))
2520                                 continue;
2521
2522                         if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2523                                 if (!mcast_all) {
2524                                         sh_eth_tsu_purge_mcast(ndev);
2525                                         ecmr_bits &= ~ECMR_MCT;
2526                                         mcast_all = 1;
2527                                 }
2528                         }
2529                 }
2530         }
2531
2532         /* update the ethernet mode */
2533         sh_eth_write(ndev, ecmr_bits, ECMR);
2534
2535         spin_unlock_irqrestore(&mdp->lock, flags);
2536 }
2537
2538 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2539 {
2540         if (!mdp->port)
2541                 return TSU_VTAG0;
2542         else
2543                 return TSU_VTAG1;
2544 }
2545
2546 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2547                                   __be16 proto, u16 vid)
2548 {
2549         struct sh_eth_private *mdp = netdev_priv(ndev);
2550         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2551
2552         if (unlikely(!mdp->cd->tsu))
2553                 return -EPERM;
2554
2555         /* No filtering if vid = 0 */
2556         if (!vid)
2557                 return 0;
2558
2559         mdp->vlan_num_ids++;
2560
2561         /* The controller has one VLAN tag HW filter. So, if the filter is
2562          * already enabled, the driver disables it and the filte
2563          */
2564         if (mdp->vlan_num_ids > 1) {
2565                 /* disable VLAN filter */
2566                 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2567                 return 0;
2568         }
2569
2570         sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2571                          vtag_reg_index);
2572
2573         return 0;
2574 }
2575
2576 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2577                                    __be16 proto, u16 vid)
2578 {
2579         struct sh_eth_private *mdp = netdev_priv(ndev);
2580         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2581
2582         if (unlikely(!mdp->cd->tsu))
2583                 return -EPERM;
2584
2585         /* No filtering if vid = 0 */
2586         if (!vid)
2587                 return 0;
2588
2589         mdp->vlan_num_ids--;
2590         sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2591
2592         return 0;
2593 }
2594
2595 /* SuperH's TSU register init function */
2596 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2597 {
2598         if (sh_eth_is_rz_fast_ether(mdp)) {
2599                 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2600                 return;
2601         }
2602
2603         sh_eth_tsu_write(mdp, 0, TSU_FWEN0);    /* Disable forward(0->1) */
2604         sh_eth_tsu_write(mdp, 0, TSU_FWEN1);    /* Disable forward(1->0) */
2605         sh_eth_tsu_write(mdp, 0, TSU_FCM);      /* forward fifo 3k-3k */
2606         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2607         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2608         sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2609         sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2610         sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2611         sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2612         sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2613         if (sh_eth_is_gether(mdp)) {
2614                 sh_eth_tsu_write(mdp, 0, TSU_QTAG0);    /* Disable QTAG(0->1) */
2615                 sh_eth_tsu_write(mdp, 0, TSU_QTAG1);    /* Disable QTAG(1->0) */
2616         } else {
2617                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0);   /* Disable QTAG(0->1) */
2618                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1);   /* Disable QTAG(1->0) */
2619         }
2620         sh_eth_tsu_write(mdp, 0, TSU_FWSR);     /* all interrupt status clear */
2621         sh_eth_tsu_write(mdp, 0, TSU_FWINMK);   /* Disable all interrupt */
2622         sh_eth_tsu_write(mdp, 0, TSU_TEN);      /* Disable all CAM entry */
2623         sh_eth_tsu_write(mdp, 0, TSU_POST1);    /* Disable CAM entry [ 0- 7] */
2624         sh_eth_tsu_write(mdp, 0, TSU_POST2);    /* Disable CAM entry [ 8-15] */
2625         sh_eth_tsu_write(mdp, 0, TSU_POST3);    /* Disable CAM entry [16-23] */
2626         sh_eth_tsu_write(mdp, 0, TSU_POST4);    /* Disable CAM entry [24-31] */
2627 }
2628
2629 /* MDIO bus release function */
2630 static int sh_mdio_release(struct sh_eth_private *mdp)
2631 {
2632         /* unregister mdio bus */
2633         mdiobus_unregister(mdp->mii_bus);
2634
2635         /* free bitbang info */
2636         free_mdio_bitbang(mdp->mii_bus);
2637
2638         return 0;
2639 }
2640
2641 /* MDIO bus init function */
2642 static int sh_mdio_init(struct sh_eth_private *mdp,
2643                         struct sh_eth_plat_data *pd)
2644 {
2645         int ret, i;
2646         struct bb_info *bitbang;
2647         struct platform_device *pdev = mdp->pdev;
2648         struct device *dev = &mdp->pdev->dev;
2649
2650         /* create bit control struct for PHY */
2651         bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
2652         if (!bitbang)
2653                 return -ENOMEM;
2654
2655         /* bitbang init */
2656         bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2657         bitbang->set_gate = pd->set_mdio_gate;
2658         bitbang->mdi_msk = PIR_MDI;
2659         bitbang->mdo_msk = PIR_MDO;
2660         bitbang->mmd_msk = PIR_MMD;
2661         bitbang->mdc_msk = PIR_MDC;
2662         bitbang->ctrl.ops = &bb_ops;
2663
2664         /* MII controller setting */
2665         mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2666         if (!mdp->mii_bus)
2667                 return -ENOMEM;
2668
2669         /* Hook up MII support for ethtool */
2670         mdp->mii_bus->name = "sh_mii";
2671         mdp->mii_bus->parent = dev;
2672         snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2673                  pdev->name, pdev->id);
2674
2675         /* PHY IRQ */
2676         mdp->mii_bus->irq = devm_kmalloc_array(dev, PHY_MAX_ADDR, sizeof(int),
2677                                                GFP_KERNEL);
2678         if (!mdp->mii_bus->irq) {
2679                 ret = -ENOMEM;
2680                 goto out_free_bus;
2681         }
2682
2683         /* register MDIO bus */
2684         if (dev->of_node) {
2685                 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
2686         } else {
2687                 for (i = 0; i < PHY_MAX_ADDR; i++)
2688                         mdp->mii_bus->irq[i] = PHY_POLL;
2689                 if (pd->phy_irq > 0)
2690                         mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2691
2692                 ret = mdiobus_register(mdp->mii_bus);
2693         }
2694
2695         if (ret)
2696                 goto out_free_bus;
2697
2698         return 0;
2699
2700 out_free_bus:
2701         free_mdio_bitbang(mdp->mii_bus);
2702         return ret;
2703 }
2704
2705 static const u16 *sh_eth_get_register_offset(int register_type)
2706 {
2707         const u16 *reg_offset = NULL;
2708
2709         switch (register_type) {
2710         case SH_ETH_REG_GIGABIT:
2711                 reg_offset = sh_eth_offset_gigabit;
2712                 break;
2713         case SH_ETH_REG_FAST_RZ:
2714                 reg_offset = sh_eth_offset_fast_rz;
2715                 break;
2716         case SH_ETH_REG_FAST_RCAR:
2717                 reg_offset = sh_eth_offset_fast_rcar;
2718                 break;
2719         case SH_ETH_REG_FAST_SH4:
2720                 reg_offset = sh_eth_offset_fast_sh4;
2721                 break;
2722         case SH_ETH_REG_FAST_SH3_SH2:
2723                 reg_offset = sh_eth_offset_fast_sh3_sh2;
2724                 break;
2725         default:
2726                 break;
2727         }
2728
2729         return reg_offset;
2730 }
2731
2732 static const struct net_device_ops sh_eth_netdev_ops = {
2733         .ndo_open               = sh_eth_open,
2734         .ndo_stop               = sh_eth_close,
2735         .ndo_start_xmit         = sh_eth_start_xmit,
2736         .ndo_get_stats          = sh_eth_get_stats,
2737         .ndo_set_rx_mode        = sh_eth_set_rx_mode,
2738         .ndo_tx_timeout         = sh_eth_tx_timeout,
2739         .ndo_do_ioctl           = sh_eth_do_ioctl,
2740         .ndo_validate_addr      = eth_validate_addr,
2741         .ndo_set_mac_address    = eth_mac_addr,
2742         .ndo_change_mtu         = eth_change_mtu,
2743 };
2744
2745 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2746         .ndo_open               = sh_eth_open,
2747         .ndo_stop               = sh_eth_close,
2748         .ndo_start_xmit         = sh_eth_start_xmit,
2749         .ndo_get_stats          = sh_eth_get_stats,
2750         .ndo_set_rx_mode        = sh_eth_set_rx_mode,
2751         .ndo_vlan_rx_add_vid    = sh_eth_vlan_rx_add_vid,
2752         .ndo_vlan_rx_kill_vid   = sh_eth_vlan_rx_kill_vid,
2753         .ndo_tx_timeout         = sh_eth_tx_timeout,
2754         .ndo_do_ioctl           = sh_eth_do_ioctl,
2755         .ndo_validate_addr      = eth_validate_addr,
2756         .ndo_set_mac_address    = eth_mac_addr,
2757         .ndo_change_mtu         = eth_change_mtu,
2758 };
2759
2760 #ifdef CONFIG_OF
2761 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2762 {
2763         struct device_node *np = dev->of_node;
2764         struct sh_eth_plat_data *pdata;
2765         const char *mac_addr;
2766
2767         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2768         if (!pdata)
2769                 return NULL;
2770
2771         pdata->phy_interface = of_get_phy_mode(np);
2772
2773         mac_addr = of_get_mac_address(np);
2774         if (mac_addr)
2775                 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
2776
2777         pdata->no_ether_link =
2778                 of_property_read_bool(np, "renesas,no-ether-link");
2779         pdata->ether_link_active_low =
2780                 of_property_read_bool(np, "renesas,ether-link-active-low");
2781
2782         return pdata;
2783 }
2784
2785 static const struct of_device_id sh_eth_match_table[] = {
2786         { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
2787         { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
2788         { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
2789         { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
2790         { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
2791         { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data },
2792         { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
2793         { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
2794         { }
2795 };
2796 MODULE_DEVICE_TABLE(of, sh_eth_match_table);
2797 #else
2798 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2799 {
2800         return NULL;
2801 }
2802 #endif
2803
2804 static int sh_eth_drv_probe(struct platform_device *pdev)
2805 {
2806         int ret, devno = 0;
2807         struct resource *res;
2808         struct net_device *ndev = NULL;
2809         struct sh_eth_private *mdp = NULL;
2810         struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
2811         const struct platform_device_id *id = platform_get_device_id(pdev);
2812
2813         /* get base addr */
2814         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2815
2816         ndev = alloc_etherdev(sizeof(struct sh_eth_private));
2817         if (!ndev)
2818                 return -ENOMEM;
2819
2820         pm_runtime_enable(&pdev->dev);
2821         pm_runtime_get_sync(&pdev->dev);
2822
2823         devno = pdev->id;
2824         if (devno < 0)
2825                 devno = 0;
2826
2827         ndev->dma = -1;
2828         ret = platform_get_irq(pdev, 0);
2829         if (ret < 0) {
2830                 ret = -ENODEV;
2831                 goto out_release;
2832         }
2833         ndev->irq = ret;
2834
2835         SET_NETDEV_DEV(ndev, &pdev->dev);
2836
2837         mdp = netdev_priv(ndev);
2838         mdp->num_tx_ring = TX_RING_SIZE;
2839         mdp->num_rx_ring = RX_RING_SIZE;
2840         mdp->addr = devm_ioremap_resource(&pdev->dev, res);
2841         if (IS_ERR(mdp->addr)) {
2842                 ret = PTR_ERR(mdp->addr);
2843                 goto out_release;
2844         }
2845
2846         ndev->base_addr = res->start;
2847
2848         spin_lock_init(&mdp->lock);
2849         mdp->pdev = pdev;
2850
2851         if (pdev->dev.of_node)
2852                 pd = sh_eth_parse_dt(&pdev->dev);
2853         if (!pd) {
2854                 dev_err(&pdev->dev, "no platform data\n");
2855                 ret = -EINVAL;
2856                 goto out_release;
2857         }
2858
2859         /* get PHY ID */
2860         mdp->phy_id = pd->phy;
2861         mdp->phy_interface = pd->phy_interface;
2862         /* EDMAC endian */
2863         mdp->edmac_endian = pd->edmac_endian;
2864         mdp->no_ether_link = pd->no_ether_link;
2865         mdp->ether_link_active_low = pd->ether_link_active_low;
2866
2867         /* set cpu data */
2868         if (id) {
2869                 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
2870         } else  {
2871                 const struct of_device_id *match;
2872
2873                 match = of_match_device(of_match_ptr(sh_eth_match_table),
2874                                         &pdev->dev);
2875                 mdp->cd = (struct sh_eth_cpu_data *)match->data;
2876         }
2877         mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
2878         if (!mdp->reg_offset) {
2879                 dev_err(&pdev->dev, "Unknown register type (%d)\n",
2880                         mdp->cd->register_type);
2881                 ret = -EINVAL;
2882                 goto out_release;
2883         }
2884         sh_eth_set_default_cpu_data(mdp->cd);
2885
2886         /* set function */
2887         if (mdp->cd->tsu)
2888                 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
2889         else
2890                 ndev->netdev_ops = &sh_eth_netdev_ops;
2891         ndev->ethtool_ops = &sh_eth_ethtool_ops;
2892         ndev->watchdog_timeo = TX_TIMEOUT;
2893
2894         /* debug message level */
2895         mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
2896
2897         /* read and set MAC address */
2898         read_mac_address(ndev, pd->mac_addr);
2899         if (!is_valid_ether_addr(ndev->dev_addr)) {
2900                 dev_warn(&pdev->dev,
2901                          "no valid MAC address supplied, using a random one.\n");
2902                 eth_hw_addr_random(ndev);
2903         }
2904
2905         /* ioremap the TSU registers */
2906         if (mdp->cd->tsu) {
2907                 struct resource *rtsu;
2908                 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2909                 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
2910                 if (IS_ERR(mdp->tsu_addr)) {
2911                         ret = PTR_ERR(mdp->tsu_addr);
2912                         goto out_release;
2913                 }
2914                 mdp->port = devno % 2;
2915                 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
2916         }
2917
2918         /* initialize first or needed device */
2919         if (!devno || pd->needs_init) {
2920                 if (mdp->cd->chip_reset)
2921                         mdp->cd->chip_reset(ndev);
2922
2923                 if (mdp->cd->tsu) {
2924                         /* TSU init (Init only)*/
2925                         sh_eth_tsu_init(mdp);
2926                 }
2927         }
2928
2929         if (mdp->cd->rmiimode)
2930                 sh_eth_write(ndev, 0x1, RMIIMODE);
2931
2932         /* MDIO bus init */
2933         ret = sh_mdio_init(mdp, pd);
2934         if (ret) {
2935                 dev_err(&ndev->dev, "failed to initialise MDIO\n");
2936                 goto out_release;
2937         }
2938
2939         netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
2940
2941         /* network device register */
2942         ret = register_netdev(ndev);
2943         if (ret)
2944                 goto out_napi_del;
2945
2946         /* print device information */
2947         netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
2948                     (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2949
2950         pm_runtime_put(&pdev->dev);
2951         platform_set_drvdata(pdev, ndev);
2952
2953         return ret;
2954
2955 out_napi_del:
2956         netif_napi_del(&mdp->napi);
2957         sh_mdio_release(mdp);
2958
2959 out_release:
2960         /* net_dev free */
2961         if (ndev)
2962                 free_netdev(ndev);
2963
2964         pm_runtime_put(&pdev->dev);
2965         pm_runtime_disable(&pdev->dev);
2966         return ret;
2967 }
2968
2969 static int sh_eth_drv_remove(struct platform_device *pdev)
2970 {
2971         struct net_device *ndev = platform_get_drvdata(pdev);
2972         struct sh_eth_private *mdp = netdev_priv(ndev);
2973
2974         unregister_netdev(ndev);
2975         netif_napi_del(&mdp->napi);
2976         sh_mdio_release(mdp);
2977         pm_runtime_disable(&pdev->dev);
2978         free_netdev(ndev);
2979
2980         return 0;
2981 }
2982
2983 #ifdef CONFIG_PM
2984 static int sh_eth_runtime_nop(struct device *dev)
2985 {
2986         /* Runtime PM callback shared between ->runtime_suspend()
2987          * and ->runtime_resume(). Simply returns success.
2988          *
2989          * This driver re-initializes all registers after
2990          * pm_runtime_get_sync() anyway so there is no need
2991          * to save and restore registers here.
2992          */
2993         return 0;
2994 }
2995
2996 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
2997         .runtime_suspend = sh_eth_runtime_nop,
2998         .runtime_resume = sh_eth_runtime_nop,
2999 };
3000 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3001 #else
3002 #define SH_ETH_PM_OPS NULL
3003 #endif
3004
3005 static struct platform_device_id sh_eth_id_table[] = {
3006         { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
3007         { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
3008         { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
3009         { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
3010         { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3011         { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
3012         { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
3013         { "r7s72100-ether", (kernel_ulong_t)&r7s72100_data },
3014         { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data },
3015         { "r8a777x-ether", (kernel_ulong_t)&r8a777x_data },
3016         { "r8a7790-ether", (kernel_ulong_t)&r8a779x_data },
3017         { "r8a7791-ether", (kernel_ulong_t)&r8a779x_data },
3018         { "r8a7793-ether", (kernel_ulong_t)&r8a779x_data },
3019         { "r8a7794-ether", (kernel_ulong_t)&r8a779x_data },
3020         { }
3021 };
3022 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3023
3024 static struct platform_driver sh_eth_driver = {
3025         .probe = sh_eth_drv_probe,
3026         .remove = sh_eth_drv_remove,
3027         .id_table = sh_eth_id_table,
3028         .driver = {
3029                    .name = CARDNAME,
3030                    .pm = SH_ETH_PM_OPS,
3031                    .of_match_table = of_match_ptr(sh_eth_match_table),
3032         },
3033 };
3034
3035 module_platform_driver(sh_eth_driver);
3036
3037 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3038 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3039 MODULE_LICENSE("GPL v2");