drivers/net/ethernet/renesas/sh_eth.c

   1 /*  SuperH Ethernet device driver
   2  *
   3  *  Copyright (C) 2014  Renesas Electronics Corporation
   4  *  Copyright (C) 2006-2012 Nobuhiro Iwamatsu
   5  *  Copyright (C) 2008-2014 Renesas Solutions Corp.
   6  *  Copyright (C) 2013-2016 Cogent Embedded, Inc.
   7  *  Copyright (C) 2014 Codethink Limited
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms and conditions of the GNU General Public License,
  11  *  version 2, as published by the Free Software Foundation.
  12  *
  13  *  This program is distributed in the hope it will be useful, but WITHOUT
  14  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  16  *  more details.
  17  *
  18  *  The full GNU General Public License is included in this distribution in
  19  *  the file called "COPYING".
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/etherdevice.h>
  28 #include <linux/delay.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/mdio-bitbang.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/of.h>
  33 #include <linux/of_device.h>
  34 #include <linux/of_irq.h>
  35 #include <linux/of_net.h>
  36 #include <linux/phy.h>
  37 #include <linux/cache.h>
  38 #include <linux/io.h>
  39 #include <linux/pm_runtime.h>
  40 #include <linux/slab.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/clk.h>
  44 #include <linux/sh_eth.h>
  45 #include <linux/of_mdio.h>
  46
  47 #include "sh_eth.h"
  48
  49 #define SH_ETH_DEF_MSG_ENABLE \
  50                 (NETIF_MSG_LINK | \
  51                 NETIF_MSG_TIMER | \
  52                 NETIF_MSG_RX_ERR| \
  53                 NETIF_MSG_TX_ERR)
  54
  55 #define SH_ETH_OFFSET_INVALID   ((u16)~0)
  56
  57 #define SH_ETH_OFFSET_DEFAULTS                  \
  58         [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
  59
  60 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
  61         SH_ETH_OFFSET_DEFAULTS,
  62
  63         [EDSR]          = 0x0000,
  64         [EDMR]          = 0x0400,
  65         [EDTRR]         = 0x0408,
  66         [EDRRR]         = 0x0410,
  67         [EESR]          = 0x0428,
  68         [EESIPR]        = 0x0430,
  69         [TDLAR]         = 0x0010,
  70         [TDFAR]         = 0x0014,
  71         [TDFXR]         = 0x0018,
  72         [TDFFR]         = 0x001c,
  73         [RDLAR]         = 0x0030,
  74         [RDFAR]         = 0x0034,
  75         [RDFXR]         = 0x0038,
  76         [RDFFR]         = 0x003c,
  77         [TRSCER]        = 0x0438,
  78         [RMFCR]         = 0x0440,
  79         [TFTR]          = 0x0448,
  80         [FDR]           = 0x0450,
  81         [RMCR]          = 0x0458,
  82         [RPADIR]        = 0x0460,
  83         [FCFTR]         = 0x0468,
  84         [CSMR]          = 0x04E4,
  85
  86         [ECMR]          = 0x0500,
  87         [ECSR]          = 0x0510,
  88         [ECSIPR]        = 0x0518,
  89         [PIR]           = 0x0520,
  90         [PSR]           = 0x0528,
  91         [PIPR]          = 0x052c,
  92         [RFLR]          = 0x0508,
  93         [APR]           = 0x0554,
  94         [MPR]           = 0x0558,
  95         [PFTCR]         = 0x055c,
  96         [PFRCR]         = 0x0560,
  97         [TPAUSER]       = 0x0564,
  98         [GECMR]         = 0x05b0,
  99         [BCULR]         = 0x05b4,
 100         [MAHR]          = 0x05c0,
 101         [MALR]          = 0x05c8,
 102         [TROCR]         = 0x0700,
 103         [CDCR]          = 0x0708,
 104         [LCCR]          = 0x0710,
 105         [CEFCR]         = 0x0740,
 106         [FRECR]         = 0x0748,
 107         [TSFRCR]        = 0x0750,
 108         [TLFRCR]        = 0x0758,
 109         [RFCR]          = 0x0760,
 110         [CERCR]         = 0x0768,
 111         [CEECR]         = 0x0770,
 112         [MAFCR]         = 0x0778,
 113         [RMII_MII]      = 0x0790,
 114
 115         [ARSTR]         = 0x0000,
 116         [TSU_CTRST]     = 0x0004,
 117         [TSU_FWEN0]     = 0x0010,
 118         [TSU_FWEN1]     = 0x0014,
 119         [TSU_FCM]       = 0x0018,
 120         [TSU_BSYSL0]    = 0x0020,
 121         [TSU_BSYSL1]    = 0x0024,
 122         [TSU_PRISL0]    = 0x0028,
 123         [TSU_PRISL1]    = 0x002c,
 124         [TSU_FWSL0]     = 0x0030,
 125         [TSU_FWSL1]     = 0x0034,
 126         [TSU_FWSLC]     = 0x0038,
 127         [TSU_QTAG0]     = 0x0040,
 128         [TSU_QTAG1]     = 0x0044,
 129         [TSU_FWSR]      = 0x0050,
 130         [TSU_FWINMK]    = 0x0054,
 131         [TSU_ADQT0]     = 0x0048,
 132         [TSU_ADQT1]     = 0x004c,
 133         [TSU_VTAG0]     = 0x0058,
 134         [TSU_VTAG1]     = 0x005c,
 135         [TSU_ADSBSY]    = 0x0060,
 136         [TSU_TEN]       = 0x0064,
 137         [TSU_POST1]     = 0x0070,
 138         [TSU_POST2]     = 0x0074,
 139         [TSU_POST3]     = 0x0078,
 140         [TSU_POST4]     = 0x007c,
 141         [TSU_ADRH0]     = 0x0100,
 142
 143         [TXNLCR0]       = 0x0080,
 144         [TXALCR0]       = 0x0084,
 145         [RXNLCR0]       = 0x0088,
 146         [RXALCR0]       = 0x008c,
 147         [FWNLCR0]       = 0x0090,
 148         [FWALCR0]       = 0x0094,
 149         [TXNLCR1]       = 0x00a0,
 150         [TXALCR1]       = 0x00a0,
 151         [RXNLCR1]       = 0x00a8,
 152         [RXALCR1]       = 0x00ac,
 153         [FWNLCR1]       = 0x00b0,
 154         [FWALCR1]       = 0x00b4,
 155 };
 156
 157 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
 158         SH_ETH_OFFSET_DEFAULTS,
 159
 160         [EDSR]          = 0x0000,
 161         [EDMR]          = 0x0400,
 162         [EDTRR]         = 0x0408,
 163         [EDRRR]         = 0x0410,
 164         [EESR]          = 0x0428,
 165         [EESIPR]        = 0x0430,
 166         [TDLAR]         = 0x0010,
 167         [TDFAR]         = 0x0014,
 168         [TDFXR]         = 0x0018,
 169         [TDFFR]         = 0x001c,
 170         [RDLAR]         = 0x0030,
 171         [RDFAR]         = 0x0034,
 172         [RDFXR]         = 0x0038,
 173         [RDFFR]         = 0x003c,
 174         [TRSCER]        = 0x0438,
 175         [RMFCR]         = 0x0440,
 176         [TFTR]          = 0x0448,
 177         [FDR]           = 0x0450,
 178         [RMCR]          = 0x0458,
 179         [RPADIR]        = 0x0460,
 180         [FCFTR]         = 0x0468,
 181         [CSMR]          = 0x04E4,
 182
 183         [ECMR]          = 0x0500,
 184         [RFLR]          = 0x0508,
 185         [ECSR]          = 0x0510,
 186         [ECSIPR]        = 0x0518,
 187         [PIR]           = 0x0520,
 188         [APR]           = 0x0554,
 189         [MPR]           = 0x0558,
 190         [PFTCR]         = 0x055c,
 191         [PFRCR]         = 0x0560,
 192         [TPAUSER]       = 0x0564,
 193         [MAHR]          = 0x05c0,
 194         [MALR]          = 0x05c8,
 195         [CEFCR]         = 0x0740,
 196         [FRECR]         = 0x0748,
 197         [TSFRCR]        = 0x0750,
 198         [TLFRCR]        = 0x0758,
 199         [RFCR]          = 0x0760,
 200         [MAFCR]         = 0x0778,
 201
 202         [ARSTR]         = 0x0000,
 203         [TSU_CTRST]     = 0x0004,
 204         [TSU_VTAG0]     = 0x0058,
 205         [TSU_ADSBSY]    = 0x0060,
 206         [TSU_TEN]       = 0x0064,
 207         [TSU_ADRH0]     = 0x0100,
 208
 209         [TXNLCR0]       = 0x0080,
 210         [TXALCR0]       = 0x0084,
 211         [RXNLCR0]       = 0x0088,
 212         [RXALCR0]       = 0x008C,
 213 };
 214
 215 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
 216         SH_ETH_OFFSET_DEFAULTS,
 217
 218         [ECMR]          = 0x0300,
 219         [RFLR]          = 0x0308,
 220         [ECSR]          = 0x0310,
 221         [ECSIPR]        = 0x0318,
 222         [PIR]           = 0x0320,
 223         [PSR]           = 0x0328,
 224         [RDMLR]         = 0x0340,
 225         [IPGR]          = 0x0350,
 226         [APR]           = 0x0354,
 227         [MPR]           = 0x0358,
 228         [RFCF]          = 0x0360,
 229         [TPAUSER]       = 0x0364,
 230         [TPAUSECR]      = 0x0368,
 231         [MAHR]          = 0x03c0,
 232         [MALR]          = 0x03c8,
 233         [TROCR]         = 0x03d0,
 234         [CDCR]          = 0x03d4,
 235         [LCCR]          = 0x03d8,
 236         [CNDCR]         = 0x03dc,
 237         [CEFCR]         = 0x03e4,
 238         [FRECR]         = 0x03e8,
 239         [TSFRCR]        = 0x03ec,
 240         [TLFRCR]        = 0x03f0,
 241         [RFCR]          = 0x03f4,
 242         [MAFCR]         = 0x03f8,
 243
 244         [EDMR]          = 0x0200,
 245         [EDTRR]         = 0x0208,
 246         [EDRRR]         = 0x0210,
 247         [TDLAR]         = 0x0218,
 248         [RDLAR]         = 0x0220,
 249         [EESR]          = 0x0228,
 250         [EESIPR]        = 0x0230,
 251         [TRSCER]        = 0x0238,
 252         [RMFCR]         = 0x0240,
 253         [TFTR]          = 0x0248,
 254         [FDR]           = 0x0250,
 255         [RMCR]          = 0x0258,
 256         [TFUCR]         = 0x0264,
 257         [RFOCR]         = 0x0268,
 258         [RMIIMODE]      = 0x026c,
 259         [FCFTR]         = 0x0270,
 260         [TRIMD]         = 0x027c,
 261 };
 262
 263 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 264         SH_ETH_OFFSET_DEFAULTS,
 265
 266         [ECMR]          = 0x0100,
 267         [RFLR]          = 0x0108,
 268         [ECSR]          = 0x0110,
 269         [ECSIPR]        = 0x0118,
 270         [PIR]           = 0x0120,
 271         [PSR]           = 0x0128,
 272         [RDMLR]         = 0x0140,
 273         [IPGR]          = 0x0150,
 274         [APR]           = 0x0154,
 275         [MPR]           = 0x0158,
 276         [TPAUSER]       = 0x0164,
 277         [RFCF]          = 0x0160,
 278         [TPAUSECR]      = 0x0168,
 279         [BCFRR]         = 0x016c,
 280         [MAHR]          = 0x01c0,
 281         [MALR]          = 0x01c8,
 282         [TROCR]         = 0x01d0,
 283         [CDCR]          = 0x01d4,
 284         [LCCR]          = 0x01d8,
 285         [CNDCR]         = 0x01dc,
 286         [CEFCR]         = 0x01e4,
 287         [FRECR]         = 0x01e8,
 288         [TSFRCR]        = 0x01ec,
 289         [TLFRCR]        = 0x01f0,
 290         [RFCR]          = 0x01f4,
 291         [MAFCR]         = 0x01f8,
 292         [RTRATE]        = 0x01fc,
 293
 294         [EDMR]          = 0x0000,
 295         [EDTRR]         = 0x0008,
 296         [EDRRR]         = 0x0010,
 297         [TDLAR]         = 0x0018,
 298         [RDLAR]         = 0x0020,
 299         [EESR]          = 0x0028,
 300         [EESIPR]        = 0x0030,
 301         [TRSCER]        = 0x0038,
 302         [RMFCR]         = 0x0040,
 303         [TFTR]          = 0x0048,
 304         [FDR]           = 0x0050,
 305         [RMCR]          = 0x0058,
 306         [TFUCR]         = 0x0064,
 307         [RFOCR]         = 0x0068,
 308         [FCFTR]         = 0x0070,
 309         [RPADIR]        = 0x0078,
 310         [TRIMD]         = 0x007c,
 311         [RBWAR]         = 0x00c8,
 312         [RDFAR]         = 0x00cc,
 313         [TBRAR]         = 0x00d4,
 314         [TDFAR]         = 0x00d8,
 315 };
 316
 317 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
 318         SH_ETH_OFFSET_DEFAULTS,
 319
 320         [EDMR]          = 0x0000,
 321         [EDTRR]         = 0x0004,
 322         [EDRRR]         = 0x0008,
 323         [TDLAR]         = 0x000c,
 324         [RDLAR]         = 0x0010,
 325         [EESR]          = 0x0014,
 326         [EESIPR]        = 0x0018,
 327         [TRSCER]        = 0x001c,
 328         [RMFCR]         = 0x0020,
 329         [TFTR]          = 0x0024,
 330         [FDR]           = 0x0028,
 331         [RMCR]          = 0x002c,
 332         [EDOCR]         = 0x0030,
 333         [FCFTR]         = 0x0034,
 334         [RPADIR]        = 0x0038,
 335         [TRIMD]         = 0x003c,
 336         [RBWAR]         = 0x0040,
 337         [RDFAR]         = 0x0044,
 338         [TBRAR]         = 0x004c,
 339         [TDFAR]         = 0x0050,
 340
 341         [ECMR]          = 0x0160,
 342         [ECSR]          = 0x0164,
 343         [ECSIPR]        = 0x0168,
 344         [PIR]           = 0x016c,
 345         [MAHR]          = 0x0170,
 346         [MALR]          = 0x0174,
 347         [RFLR]          = 0x0178,
 348         [PSR]           = 0x017c,
 349         [TROCR]         = 0x0180,
 350         [CDCR]          = 0x0184,
 351         [LCCR]          = 0x0188,
 352         [CNDCR]         = 0x018c,
 353         [CEFCR]         = 0x0194,
 354         [FRECR]         = 0x0198,
 355         [TSFRCR]        = 0x019c,
 356         [TLFRCR]        = 0x01a0,
 357         [RFCR]          = 0x01a4,
 358         [MAFCR]         = 0x01a8,
 359         [IPGR]          = 0x01b4,
 360         [APR]           = 0x01b8,
 361         [MPR]           = 0x01bc,
 362         [TPAUSER]       = 0x01c4,
 363         [BCFR]          = 0x01cc,
 364
 365         [ARSTR]         = 0x0000,
 366         [TSU_CTRST]     = 0x0004,
 367         [TSU_FWEN0]     = 0x0010,
 368         [TSU_FWEN1]     = 0x0014,
 369         [TSU_FCM]       = 0x0018,
 370         [TSU_BSYSL0]    = 0x0020,
 371         [TSU_BSYSL1]    = 0x0024,
 372         [TSU_PRISL0]    = 0x0028,
 373         [TSU_PRISL1]    = 0x002c,
 374         [TSU_FWSL0]     = 0x0030,
 375         [TSU_FWSL1]     = 0x0034,
 376         [TSU_FWSLC]     = 0x0038,
 377         [TSU_QTAGM0]    = 0x0040,
 378         [TSU_QTAGM1]    = 0x0044,
 379         [TSU_ADQT0]     = 0x0048,
 380         [TSU_ADQT1]     = 0x004c,
 381         [TSU_FWSR]      = 0x0050,
 382         [TSU_FWINMK]    = 0x0054,
 383         [TSU_ADSBSY]    = 0x0060,
 384         [TSU_TEN]       = 0x0064,
 385         [TSU_POST1]     = 0x0070,
 386         [TSU_POST2]     = 0x0074,
 387         [TSU_POST3]     = 0x0078,
 388         [TSU_POST4]     = 0x007c,
 389
 390         [TXNLCR0]       = 0x0080,
 391         [TXALCR0]       = 0x0084,
 392         [RXNLCR0]       = 0x0088,
 393         [RXALCR0]       = 0x008c,
 394         [FWNLCR0]       = 0x0090,
 395         [FWALCR0]       = 0x0094,
 396         [TXNLCR1]       = 0x00a0,
 397         [TXALCR1]       = 0x00a0,
 398         [RXNLCR1]       = 0x00a8,
 399         [RXALCR1]       = 0x00ac,
 400         [FWNLCR1]       = 0x00b0,
 401         [FWALCR1]       = 0x00b4,
 402
 403         [TSU_ADRH0]     = 0x0100,
 404 };
 405
 406 static void sh_eth_rcv_snd_disable(struct net_device *ndev);
 407 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
 408
 409 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
 410 {
 411         struct sh_eth_private *mdp = netdev_priv(ndev);
 412         u16 offset = mdp->reg_offset[enum_index];
 413
 414         if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
 415                 return;
 416
 417         iowrite32(data, mdp->addr + offset);
 418 }
 419
 420 static u32 sh_eth_read(struct net_device *ndev, int enum_index)
 421 {
 422         struct sh_eth_private *mdp = netdev_priv(ndev);
 423         u16 offset = mdp->reg_offset[enum_index];
 424
 425         if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
 426                 return ~0U;
 427
 428         return ioread32(mdp->addr + offset);
 429 }
 430
 431 static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear,
 432                           u32 set)
 433 {
 434         sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set,
 435                      enum_index);
 436 }
 437
 438 static bool sh_eth_is_gether(struct sh_eth_private *mdp)
 439 {
 440         return mdp->reg_offset == sh_eth_offset_gigabit;
 441 }
 442
 443 static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
 444 {
 445         return mdp->reg_offset == sh_eth_offset_fast_rz;
 446 }
 447
 448 static void sh_eth_select_mii(struct net_device *ndev)
 449 {
 450         struct sh_eth_private *mdp = netdev_priv(ndev);
 451         u32 value;
 452
 453         switch (mdp->phy_interface) {
 454         case PHY_INTERFACE_MODE_GMII:
 455                 value = 0x2;
 456                 break;
 457         case PHY_INTERFACE_MODE_MII:
 458                 value = 0x1;
 459                 break;
 460         case PHY_INTERFACE_MODE_RMII:
 461                 value = 0x0;
 462                 break;
 463         default:
 464                 netdev_warn(ndev,
 465                             "PHY interface mode was not setup. Set to MII.\n");
 466                 value = 0x1;
 467                 break;
 468         }
 469
 470         sh_eth_write(ndev, value, RMII_MII);
 471 }
 472
 473 static void sh_eth_set_duplex(struct net_device *ndev)
 474 {
 475         struct sh_eth_private *mdp = netdev_priv(ndev);
 476
 477         sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0);
 478 }
 479
 480 static void sh_eth_chip_reset(struct net_device *ndev)
 481 {
 482         struct sh_eth_private *mdp = netdev_priv(ndev);
 483
 484         /* reset device */
 485         sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR);
 486         mdelay(1);
 487 }
 488
 489 static void sh_eth_set_rate_gether(struct net_device *ndev)
 490 {
 491         struct sh_eth_private *mdp = netdev_priv(ndev);
 492
 493         switch (mdp->speed) {
 494         case 10: /* 10BASE */
 495                 sh_eth_write(ndev, GECMR_10, GECMR);
 496                 break;
 497         case 100:/* 100BASE */
 498                 sh_eth_write(ndev, GECMR_100, GECMR);
 499                 break;
 500         case 1000: /* 1000BASE */
 501                 sh_eth_write(ndev, GECMR_1000, GECMR);
 502                 break;
 503         }
 504 }
 505
 506 #ifdef CONFIG_OF
 507 /* R7S72100 */
 508 static struct sh_eth_cpu_data r7s72100_data = {
 509         .chip_reset     = sh_eth_chip_reset,
 510         .set_duplex     = sh_eth_set_duplex,
 511
 512         .register_type  = SH_ETH_REG_FAST_RZ,
 513
 514         .ecsr_value     = ECSR_ICD,
 515         .ecsipr_value   = ECSIPR_ICDIP,
 516         .eesipr_value   = 0xff7f009f,
 517
 518         .tx_check       = EESR_TC1 | EESR_FTC,
 519         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 520                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 521                           EESR_TDE | EESR_ECI,
 522         .fdr_value      = 0x0000070f,
 523
 524         .no_psr         = 1,
 525         .apr            = 1,
 526         .mpr            = 1,
 527         .tpauser        = 1,
 528         .hw_swap        = 1,
 529         .rpadir         = 1,
 530         .rpadir_value   = 2 << 16,
 531         .no_trimd       = 1,
 532         .no_ade         = 1,
 533         .hw_crc         = 1,
 534         .tsu            = 1,
 535         .shift_rd0      = 1,
 536 };
 537
 538 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
 539 {
 540         sh_eth_chip_reset(ndev);
 541
 542         sh_eth_select_mii(ndev);
 543 }
 544
 545 /* R8A7740 */
 546 static struct sh_eth_cpu_data r8a7740_data = {
 547         .chip_reset     = sh_eth_chip_reset_r8a7740,
 548         .set_duplex     = sh_eth_set_duplex,
 549         .set_rate       = sh_eth_set_rate_gether,
 550
 551         .register_type  = SH_ETH_REG_GIGABIT,
 552
 553         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 554         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 555         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 556
 557         .tx_check       = EESR_TC1 | EESR_FTC,
 558         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 559                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 560                           EESR_TDE | EESR_ECI,
 561         .fdr_value      = 0x0000070f,
 562
 563         .apr            = 1,
 564         .mpr            = 1,
 565         .tpauser        = 1,
 566         .bculr          = 1,
 567         .hw_swap        = 1,
 568         .rpadir         = 1,
 569         .rpadir_value   = 2 << 16,
 570         .no_trimd       = 1,
 571         .no_ade         = 1,
 572         .tsu            = 1,
 573         .select_mii     = 1,
 574         .shift_rd0      = 1,
 575 };
 576
 577 /* There is CPU dependent code */
 578 static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
 579 {
 580         struct sh_eth_private *mdp = netdev_priv(ndev);
 581
 582         switch (mdp->speed) {
 583         case 10: /* 10BASE */
 584                 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0);
 585                 break;
 586         case 100:/* 100BASE */
 587                 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB);
 588                 break;
 589         }
 590 }
 591
 592 /* R8A7778/9 */
 593 static struct sh_eth_cpu_data r8a777x_data = {
 594         .set_duplex     = sh_eth_set_duplex,
 595         .set_rate       = sh_eth_set_rate_r8a777x,
 596
 597         .register_type  = SH_ETH_REG_FAST_RCAR,
 598
 599         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 600         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 601         .eesipr_value   = 0x01ff009f,
 602
 603         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 604         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 605                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 606                           EESR_ECI,
 607         .fdr_value      = 0x00000f0f,
 608
 609         .apr            = 1,
 610         .mpr            = 1,
 611         .tpauser        = 1,
 612         .hw_swap        = 1,
 613 };
 614
 615 /* R8A7790/1 */
 616 static struct sh_eth_cpu_data r8a779x_data = {
 617         .set_duplex     = sh_eth_set_duplex,
 618         .set_rate       = sh_eth_set_rate_r8a777x,
 619
 620         .register_type  = SH_ETH_REG_FAST_RCAR,
 621
 622         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 623         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 624         .eesipr_value   = 0x01ff009f,
 625
 626         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 627         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 628                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 629                           EESR_ECI,
 630         .fdr_value      = 0x00000f0f,
 631
 632         .trscer_err_mask = DESC_I_RINT8,
 633
 634         .apr            = 1,
 635         .mpr            = 1,
 636         .tpauser        = 1,
 637         .hw_swap        = 1,
 638         .rmiimode       = 1,
 639 };
 640 #endif /* CONFIG_OF */
 641
 642 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
 643 {
 644         struct sh_eth_private *mdp = netdev_priv(ndev);
 645
 646         switch (mdp->speed) {
 647         case 10: /* 10BASE */
 648                 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0);
 649                 break;
 650         case 100:/* 100BASE */
 651                 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM);
 652                 break;
 653         }
 654 }
 655
 656 /* SH7724 */
 657 static struct sh_eth_cpu_data sh7724_data = {
 658         .set_duplex     = sh_eth_set_duplex,
 659         .set_rate       = sh_eth_set_rate_sh7724,
 660
 661         .register_type  = SH_ETH_REG_FAST_SH4,
 662
 663         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 664         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 665         .eesipr_value   = 0x01ff009f,
 666
 667         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 668         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 669                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 670                           EESR_ECI,
 671
 672         .apr            = 1,
 673         .mpr            = 1,
 674         .tpauser        = 1,
 675         .hw_swap        = 1,
 676         .rpadir         = 1,
 677         .rpadir_value   = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
 678 };
 679
 680 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
 681 {
 682         struct sh_eth_private *mdp = netdev_priv(ndev);
 683
 684         switch (mdp->speed) {
 685         case 10: /* 10BASE */
 686                 sh_eth_write(ndev, 0, RTRATE);
 687                 break;
 688         case 100:/* 100BASE */
 689                 sh_eth_write(ndev, 1, RTRATE);
 690                 break;
 691         }
 692 }
 693
 694 /* SH7757 */
 695 static struct sh_eth_cpu_data sh7757_data = {
 696         .set_duplex     = sh_eth_set_duplex,
 697         .set_rate       = sh_eth_set_rate_sh7757,
 698
 699         .register_type  = SH_ETH_REG_FAST_SH4,
 700
 701         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 702
 703         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 704         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 705                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 706                           EESR_ECI,
 707
 708         .irq_flags      = IRQF_SHARED,
 709         .apr            = 1,
 710         .mpr            = 1,
 711         .tpauser        = 1,
 712         .hw_swap        = 1,
 713         .no_ade         = 1,
 714         .rpadir         = 1,
 715         .rpadir_value   = 2 << 16,
 716         .rtrate         = 1,
 717 };
 718
 719 #define SH_GIGA_ETH_BASE        0xfee00000UL
 720 #define GIGA_MALR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
 721 #define GIGA_MAHR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
 722 static void sh_eth_chip_reset_giga(struct net_device *ndev)
 723 {
 724         u32 mahr[2], malr[2];
 725         int i;
 726
 727         /* save MAHR and MALR */
 728         for (i = 0; i < 2; i++) {
 729                 malr[i] = ioread32((void *)GIGA_MALR(i));
 730                 mahr[i] = ioread32((void *)GIGA_MAHR(i));
 731         }
 732
 733         sh_eth_chip_reset(ndev);
 734
 735         /* restore MAHR and MALR */
 736         for (i = 0; i < 2; i++) {
 737                 iowrite32(malr[i], (void *)GIGA_MALR(i));
 738                 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
 739         }
 740 }
 741
 742 static void sh_eth_set_rate_giga(struct net_device *ndev)
 743 {
 744         struct sh_eth_private *mdp = netdev_priv(ndev);
 745
 746         switch (mdp->speed) {
 747         case 10: /* 10BASE */
 748                 sh_eth_write(ndev, 0x00000000, GECMR);
 749                 break;
 750         case 100:/* 100BASE */
 751                 sh_eth_write(ndev, 0x00000010, GECMR);
 752                 break;
 753         case 1000: /* 1000BASE */
 754                 sh_eth_write(ndev, 0x00000020, GECMR);
 755                 break;
 756         }
 757 }
 758
 759 /* SH7757(GETHERC) */
 760 static struct sh_eth_cpu_data sh7757_data_giga = {
 761         .chip_reset     = sh_eth_chip_reset_giga,
 762         .set_duplex     = sh_eth_set_duplex,
 763         .set_rate       = sh_eth_set_rate_giga,
 764
 765         .register_type  = SH_ETH_REG_GIGABIT,
 766
 767         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 768         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 769         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 770
 771         .tx_check       = EESR_TC1 | EESR_FTC,
 772         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 773                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 774                           EESR_TDE | EESR_ECI,
 775         .fdr_value      = 0x0000072f,
 776
 777         .irq_flags      = IRQF_SHARED,
 778         .apr            = 1,
 779         .mpr            = 1,
 780         .tpauser        = 1,
 781         .bculr          = 1,
 782         .hw_swap        = 1,
 783         .rpadir         = 1,
 784         .rpadir_value   = 2 << 16,
 785         .no_trimd       = 1,
 786         .no_ade         = 1,
 787         .tsu            = 1,
 788 };
 789
 790 /* SH7734 */
 791 static struct sh_eth_cpu_data sh7734_data = {
 792         .chip_reset     = sh_eth_chip_reset,
 793         .set_duplex     = sh_eth_set_duplex,
 794         .set_rate       = sh_eth_set_rate_gether,
 795
 796         .register_type  = SH_ETH_REG_GIGABIT,
 797
 798         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 799         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 800         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 801
 802         .tx_check       = EESR_TC1 | EESR_FTC,
 803         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 804                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 805                           EESR_TDE | EESR_ECI,
 806
 807         .apr            = 1,
 808         .mpr            = 1,
 809         .tpauser        = 1,
 810         .bculr          = 1,
 811         .hw_swap        = 1,
 812         .no_trimd       = 1,
 813         .no_ade         = 1,
 814         .tsu            = 1,
 815         .hw_crc         = 1,
 816         .select_mii     = 1,
 817 };
 818
 819 /* SH7763 */
 820 static struct sh_eth_cpu_data sh7763_data = {
 821         .chip_reset     = sh_eth_chip_reset,
 822         .set_duplex     = sh_eth_set_duplex,
 823         .set_rate       = sh_eth_set_rate_gether,
 824
 825         .register_type  = SH_ETH_REG_GIGABIT,
 826
 827         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 828         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 829         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 830
 831         .tx_check       = EESR_TC1 | EESR_FTC,
 832         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 833                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 834                           EESR_ECI,
 835
 836         .apr            = 1,
 837         .mpr            = 1,
 838         .tpauser        = 1,
 839         .bculr          = 1,
 840         .hw_swap        = 1,
 841         .no_trimd       = 1,
 842         .no_ade         = 1,
 843         .tsu            = 1,
 844         .irq_flags      = IRQF_SHARED,
 845 };
 846
 847 static struct sh_eth_cpu_data sh7619_data = {
 848         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
 849
 850         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 851
 852         .apr            = 1,
 853         .mpr            = 1,
 854         .tpauser        = 1,
 855         .hw_swap        = 1,
 856 };
 857
 858 static struct sh_eth_cpu_data sh771x_data = {
 859         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
 860
 861         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 862         .tsu            = 1,
 863 };
 864
 865 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
 866 {
 867         if (!cd->ecsr_value)
 868                 cd->ecsr_value = DEFAULT_ECSR_INIT;
 869
 870         if (!cd->ecsipr_value)
 871                 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
 872
 873         if (!cd->fcftr_value)
 874                 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
 875                                   DEFAULT_FIFO_F_D_RFD;
 876
 877         if (!cd->fdr_value)
 878                 cd->fdr_value = DEFAULT_FDR_INIT;
 879
 880         if (!cd->tx_check)
 881                 cd->tx_check = DEFAULT_TX_CHECK;
 882
 883         if (!cd->eesr_err_check)
 884                 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
 885
 886         if (!cd->trscer_err_mask)
 887                 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
 888 }
 889
 890 static int sh_eth_check_reset(struct net_device *ndev)
 891 {
 892         int ret = 0;
 893         int cnt = 100;
 894
 895         while (cnt > 0) {
 896                 if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER))
 897                         break;
 898                 mdelay(1);
 899                 cnt--;
 900         }
 901         if (cnt <= 0) {
 902                 netdev_err(ndev, "Device reset failed\n");
 903                 ret = -ETIMEDOUT;
 904         }
 905         return ret;
 906 }
 907
 908 static int sh_eth_reset(struct net_device *ndev)
 909 {
 910         struct sh_eth_private *mdp = netdev_priv(ndev);
 911         int ret = 0;
 912
 913         if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
 914                 sh_eth_write(ndev, EDSR_ENALL, EDSR);
 915                 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER);
 916
 917                 ret = sh_eth_check_reset(ndev);
 918                 if (ret)
 919                         return ret;
 920
 921                 /* Table Init */
 922                 sh_eth_write(ndev, 0x0, TDLAR);
 923                 sh_eth_write(ndev, 0x0, TDFAR);
 924                 sh_eth_write(ndev, 0x0, TDFXR);
 925                 sh_eth_write(ndev, 0x0, TDFFR);
 926                 sh_eth_write(ndev, 0x0, RDLAR);
 927                 sh_eth_write(ndev, 0x0, RDFAR);
 928                 sh_eth_write(ndev, 0x0, RDFXR);
 929                 sh_eth_write(ndev, 0x0, RDFFR);
 930
 931                 /* Reset HW CRC register */
 932                 if (mdp->cd->hw_crc)
 933                         sh_eth_write(ndev, 0x0, CSMR);
 934
 935                 /* Select MII mode */
 936                 if (mdp->cd->select_mii)
 937                         sh_eth_select_mii(ndev);
 938         } else {
 939                 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER);
 940                 mdelay(3);
 941                 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0);
 942         }
 943
 944         return ret;
 945 }
 946
 947 static void sh_eth_set_receive_align(struct sk_buff *skb)
 948 {
 949         uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
 950
 951         if (reserve)
 952                 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
 953 }
 954
 955 /* Program the hardware MAC address from dev->dev_addr. */
 956 static void update_mac_address(struct net_device *ndev)
 957 {
 958         sh_eth_write(ndev,
 959                      (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
 960                      (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
 961         sh_eth_write(ndev,
 962                      (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
 963 }
 964
 965 /* Get MAC address from SuperH MAC address register
 966  *
 967  * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
 968  * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
 969  * When you want use this device, you must set MAC address in bootloader.
 970  *
 971  */
 972 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
 973 {
 974         if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
 975                 memcpy(ndev->dev_addr, mac, ETH_ALEN);
 976         } else {
 977                 u32 mahr = sh_eth_read(ndev, MAHR);
 978                 u32 malr = sh_eth_read(ndev, MALR);
 979
 980                 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
 981                 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
 982                 ndev->dev_addr[2] = (mahr >>  8) & 0xFF;
 983                 ndev->dev_addr[3] = (mahr >>  0) & 0xFF;
 984                 ndev->dev_addr[4] = (malr >>  8) & 0xFF;
 985                 ndev->dev_addr[5] = (malr >>  0) & 0xFF;
 986         }
 987 }
 988
 989 static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
 990 {
 991         if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
 992                 return EDTRR_TRNS_GETHER;
 993         else
 994                 return EDTRR_TRNS_ETHER;
 995 }
 996
 997 struct bb_info {
 998         void (*set_gate)(void *addr);
 999         struct mdiobb_ctrl ctrl;
1000         void *addr;
1001 };
1002
1003 static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
1004 {
1005         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1006         u32 pir;
1007
1008         if (bitbang->set_gate)
1009                 bitbang->set_gate(bitbang->addr);
1010
1011         pir = ioread32(bitbang->addr);
1012         if (set)
1013                 pir |=  mask;
1014         else
1015                 pir &= ~mask;
1016         iowrite32(pir, bitbang->addr);
1017 }
1018
1019 /* Data I/O pin control */
1020 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1021 {
1022         sh_mdio_ctrl(ctrl, PIR_MMD, bit);
1023 }
1024
1025 /* Set bit data*/
1026 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1027 {
1028         sh_mdio_ctrl(ctrl, PIR_MDO, bit);
1029 }
1030
1031 /* Get bit data*/
1032 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1033 {
1034         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1035
1036         if (bitbang->set_gate)
1037                 bitbang->set_gate(bitbang->addr);
1038
1039         return (ioread32(bitbang->addr) & PIR_MDI) != 0;
1040 }
1041
1042 /* MDC pin control */
1043 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1044 {
1045         sh_mdio_ctrl(ctrl, PIR_MDC, bit);
1046 }
1047
1048 /* mdio bus control struct */
1049 static struct mdiobb_ops bb_ops = {
1050         .owner = THIS_MODULE,
1051         .set_mdc = sh_mdc_ctrl,
1052         .set_mdio_dir = sh_mmd_ctrl,
1053         .set_mdio_data = sh_set_mdio,
1054         .get_mdio_data = sh_get_mdio,
1055 };
1056
1057 /* free skb and descriptor buffer */
1058 static void sh_eth_ring_free(struct net_device *ndev)
1059 {
1060         struct sh_eth_private *mdp = netdev_priv(ndev);
1061         int ringsize, i;
1062
1063         /* Free Rx skb ringbuffer */
1064         if (mdp->rx_skbuff) {
1065                 for (i = 0; i < mdp->num_rx_ring; i++)
1066                         dev_kfree_skb(mdp->rx_skbuff[i]);
1067         }
1068         kfree(mdp->rx_skbuff);
1069         mdp->rx_skbuff = NULL;
1070
1071         /* Free Tx skb ringbuffer */
1072         if (mdp->tx_skbuff) {
1073                 for (i = 0; i < mdp->num_tx_ring; i++)
1074                         dev_kfree_skb(mdp->tx_skbuff[i]);
1075         }
1076         kfree(mdp->tx_skbuff);
1077         mdp->tx_skbuff = NULL;
1078
1079         if (mdp->rx_ring) {
1080                 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1081                 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1082                                   mdp->rx_desc_dma);
1083                 mdp->rx_ring = NULL;
1084         }
1085
1086         if (mdp->tx_ring) {
1087                 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1088                 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1089                                   mdp->tx_desc_dma);
1090                 mdp->tx_ring = NULL;
1091         }
1092 }
1093
1094 /* format skb and descriptor buffer */
1095 static void sh_eth_ring_format(struct net_device *ndev)
1096 {
1097         struct sh_eth_private *mdp = netdev_priv(ndev);
1098         int i;
1099         struct sk_buff *skb;
1100         struct sh_eth_rxdesc *rxdesc = NULL;
1101         struct sh_eth_txdesc *txdesc = NULL;
1102         int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1103         int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1104         int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1105         dma_addr_t dma_addr;
1106         u32 buf_len;
1107
1108         mdp->cur_rx = 0;
1109         mdp->cur_tx = 0;
1110         mdp->dirty_rx = 0;
1111         mdp->dirty_tx = 0;
1112
1113         memset(mdp->rx_ring, 0, rx_ringsize);
1114
1115         /* build Rx ring buffer */
1116         for (i = 0; i < mdp->num_rx_ring; i++) {
1117                 /* skb */
1118                 mdp->rx_skbuff[i] = NULL;
1119                 skb = netdev_alloc_skb(ndev, skbuff_size);
1120                 if (skb == NULL)
1121                         break;
1122                 sh_eth_set_receive_align(skb);
1123
1124                 /* The size of the buffer is a multiple of 32 bytes. */
1125                 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1126                 dma_addr = dma_map_single(&ndev->dev, skb->data, buf_len,
1127                                           DMA_FROM_DEVICE);
1128                 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1129                         kfree_skb(skb);
1130                         break;
1131                 }
1132                 mdp->rx_skbuff[i] = skb;
1133
1134                 /* RX descriptor */
1135                 rxdesc = &mdp->rx_ring[i];
1136                 rxdesc->len = cpu_to_le32(buf_len << 16);
1137                 rxdesc->addr = cpu_to_le32(dma_addr);
1138                 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP);
1139
1140                 /* Rx descriptor address set */
1141                 if (i == 0) {
1142                         sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1143                         if (sh_eth_is_gether(mdp) ||
1144                             sh_eth_is_rz_fast_ether(mdp))
1145                                 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1146                 }
1147         }
1148
1149         mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1150
1151         /* Mark the last entry as wrapping the ring. */
1152         if (rxdesc)
1153                 rxdesc->status |= cpu_to_le32(RD_RDLE);
1154
1155         memset(mdp->tx_ring, 0, tx_ringsize);
1156
1157         /* build Tx ring buffer */
1158         for (i = 0; i < mdp->num_tx_ring; i++) {
1159                 mdp->tx_skbuff[i] = NULL;
1160                 txdesc = &mdp->tx_ring[i];
1161                 txdesc->status = cpu_to_le32(TD_TFP);
1162                 txdesc->len = cpu_to_le32(0);
1163                 if (i == 0) {
1164                         /* Tx descriptor address set */
1165                         sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1166                         if (sh_eth_is_gether(mdp) ||
1167                             sh_eth_is_rz_fast_ether(mdp))
1168                                 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1169                 }
1170         }
1171
1172         txdesc->status |= cpu_to_le32(TD_TDLE);
1173 }
1174
1175 /* Get skb and descriptor buffer */
1176 static int sh_eth_ring_init(struct net_device *ndev)
1177 {
1178         struct sh_eth_private *mdp = netdev_priv(ndev);
1179         int rx_ringsize, tx_ringsize;
1180
1181         /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1182          * card needs room to do 8 byte alignment, +2 so we can reserve
1183          * the first 2 bytes, and +16 gets room for the status word from the
1184          * card.
1185          */
1186         mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1187                           (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1188         if (mdp->cd->rpadir)
1189                 mdp->rx_buf_sz += NET_IP_ALIGN;
1190
1191         /* Allocate RX and TX skb rings */
1192         mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1193                                  GFP_KERNEL);
1194         if (!mdp->rx_skbuff)
1195                 return -ENOMEM;
1196
1197         mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1198                                  GFP_KERNEL);
1199         if (!mdp->tx_skbuff)
1200                 goto ring_free;
1201
1202         /* Allocate all Rx descriptors. */
1203         rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1204         mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1205                                           GFP_KERNEL);
1206         if (!mdp->rx_ring)
1207                 goto ring_free;
1208
1209         mdp->dirty_rx = 0;
1210
1211         /* Allocate all Tx descriptors. */
1212         tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1213         mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1214                                           GFP_KERNEL);
1215         if (!mdp->tx_ring)
1216                 goto ring_free;
1217         return 0;
1218
1219 ring_free:
1220         /* Free Rx and Tx skb ring buffer and DMA buffer */
1221         sh_eth_ring_free(ndev);
1222
1223         return -ENOMEM;
1224 }
1225
1226 static int sh_eth_dev_init(struct net_device *ndev)
1227 {
1228         struct sh_eth_private *mdp = netdev_priv(ndev);
1229         int ret;
1230
1231         /* Soft Reset */
1232         ret = sh_eth_reset(ndev);
1233         if (ret)
1234                 return ret;
1235
1236         if (mdp->cd->rmiimode)
1237                 sh_eth_write(ndev, 0x1, RMIIMODE);
1238
1239         /* Descriptor format */
1240         sh_eth_ring_format(ndev);
1241         if (mdp->cd->rpadir)
1242                 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1243
1244         /* all sh_eth int mask */
1245         sh_eth_write(ndev, 0, EESIPR);
1246
1247 #if defined(__LITTLE_ENDIAN)
1248         if (mdp->cd->hw_swap)
1249                 sh_eth_write(ndev, EDMR_EL, EDMR);
1250         else
1251 #endif
1252                 sh_eth_write(ndev, 0, EDMR);
1253
1254         /* FIFO size set */
1255         sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1256         sh_eth_write(ndev, 0, TFTR);
1257
1258         /* Frame recv control (enable multiple-packets per rx irq) */
1259         sh_eth_write(ndev, RMCR_RNC, RMCR);
1260
1261         sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
1262
1263         if (mdp->cd->bculr)
1264                 sh_eth_write(ndev, 0x800, BCULR);       /* Burst sycle set */
1265
1266         sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1267
1268         if (!mdp->cd->no_trimd)
1269                 sh_eth_write(ndev, 0, TRIMD);
1270
1271         /* Recv frame limit set register */
1272         sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1273                      RFLR);
1274
1275         sh_eth_modify(ndev, EESR, 0, 0);
1276         mdp->irq_enabled = true;
1277         sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1278
1279         /* PAUSE Prohibition */
1280         sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) |
1281                      ECMR_TE | ECMR_RE, ECMR);
1282
1283         if (mdp->cd->set_rate)
1284                 mdp->cd->set_rate(ndev);
1285
1286         /* E-MAC Status Register clear */
1287         sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1288
1289         /* E-MAC Interrupt Enable register */
1290         sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1291
1292         /* Set MAC address */
1293         update_mac_address(ndev);
1294
1295         /* mask reset */
1296         if (mdp->cd->apr)
1297                 sh_eth_write(ndev, APR_AP, APR);
1298         if (mdp->cd->mpr)
1299                 sh_eth_write(ndev, MPR_MP, MPR);
1300         if (mdp->cd->tpauser)
1301                 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1302
1303         /* Setting the Rx mode will start the Rx process. */
1304         sh_eth_write(ndev, EDRRR_R, EDRRR);
1305
1306         return ret;
1307 }
1308
1309 static void sh_eth_dev_exit(struct net_device *ndev)
1310 {
1311         struct sh_eth_private *mdp = netdev_priv(ndev);
1312         int i;
1313
1314         /* Deactivate all TX descriptors, so DMA should stop at next
1315          * packet boundary if it's currently running
1316          */
1317         for (i = 0; i < mdp->num_tx_ring; i++)
1318                 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT);
1319
1320         /* Disable TX FIFO egress to MAC */
1321         sh_eth_rcv_snd_disable(ndev);
1322
1323         /* Stop RX DMA at next packet boundary */
1324         sh_eth_write(ndev, 0, EDRRR);
1325
1326         /* Aside from TX DMA, we can't tell when the hardware is
1327          * really stopped, so we need to reset to make sure.
1328          * Before doing that, wait for long enough to *probably*
1329          * finish transmitting the last packet and poll stats.
1330          */
1331         msleep(2); /* max frame time at 10 Mbps < 1250 us */
1332         sh_eth_get_stats(ndev);
1333         sh_eth_reset(ndev);
1334
1335         /* Set MAC address again */
1336         update_mac_address(ndev);
1337 }
1338
1339 /* free Tx skb function */
1340 static int sh_eth_txfree(struct net_device *ndev)
1341 {
1342         struct sh_eth_private *mdp = netdev_priv(ndev);
1343         struct sh_eth_txdesc *txdesc;
1344         int free_num = 0;
1345         int entry;
1346
1347         for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1348                 entry = mdp->dirty_tx % mdp->num_tx_ring;
1349                 txdesc = &mdp->tx_ring[entry];
1350                 if (txdesc->status & cpu_to_le32(TD_TACT))
1351                         break;
1352                 /* TACT bit must be checked before all the following reads */
1353                 dma_rmb();
1354                 netif_info(mdp, tx_done, ndev,
1355                            "tx entry %d status 0x%08x\n",
1356                            entry, le32_to_cpu(txdesc->status));
1357                 /* Free the original skb. */
1358                 if (mdp->tx_skbuff[entry]) {
1359                         dma_unmap_single(&ndev->dev, le32_to_cpu(txdesc->addr),
1360                                          le32_to_cpu(txdesc->len) >> 16,
1361                                          DMA_TO_DEVICE);
1362                         dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1363                         mdp->tx_skbuff[entry] = NULL;
1364                         free_num++;
1365                 }
1366                 txdesc->status = cpu_to_le32(TD_TFP);
1367                 if (entry >= mdp->num_tx_ring - 1)
1368                         txdesc->status |= cpu_to_le32(TD_TDLE);
1369
1370                 ndev->stats.tx_packets++;
1371                 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16;
1372         }
1373         return free_num;
1374 }
1375
1376 /* Packet receive function */
1377 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1378 {
1379         struct sh_eth_private *mdp = netdev_priv(ndev);
1380         struct sh_eth_rxdesc *rxdesc;
1381
1382         int entry = mdp->cur_rx % mdp->num_rx_ring;
1383         int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1384         int limit;
1385         struct sk_buff *skb;
1386         u32 desc_status;
1387         int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1388         dma_addr_t dma_addr;
1389         u16 pkt_len;
1390         u32 buf_len;
1391
1392         boguscnt = min(boguscnt, *quota);
1393         limit = boguscnt;
1394         rxdesc = &mdp->rx_ring[entry];
1395         while (!(rxdesc->status & cpu_to_le32(RD_RACT))) {
1396                 /* RACT bit must be checked before all the following reads */
1397                 dma_rmb();
1398                 desc_status = le32_to_cpu(rxdesc->status);
1399                 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL;
1400
1401                 if (--boguscnt < 0)
1402                         break;
1403
1404                 netif_info(mdp, rx_status, ndev,
1405                            "rx entry %d status 0x%08x len %d\n",
1406                            entry, desc_status, pkt_len);
1407
1408                 if (!(desc_status & RDFEND))
1409                         ndev->stats.rx_length_errors++;
1410
1411                 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1412                  * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1413                  * bit 0. However, in case of the R8A7740 and R7S72100
1414                  * the RFS bits are from bit 25 to bit 16. So, the
1415                  * driver needs right shifting by 16.
1416                  */
1417                 if (mdp->cd->shift_rd0)
1418                         desc_status >>= 16;
1419
1420                 skb = mdp->rx_skbuff[entry];
1421                 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1422                                    RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1423                         ndev->stats.rx_errors++;
1424                         if (desc_status & RD_RFS1)
1425                                 ndev->stats.rx_crc_errors++;
1426                         if (desc_status & RD_RFS2)
1427                                 ndev->stats.rx_frame_errors++;
1428                         if (desc_status & RD_RFS3)
1429                                 ndev->stats.rx_length_errors++;
1430                         if (desc_status & RD_RFS4)
1431                                 ndev->stats.rx_length_errors++;
1432                         if (desc_status & RD_RFS6)
1433                                 ndev->stats.rx_missed_errors++;
1434                         if (desc_status & RD_RFS10)
1435                                 ndev->stats.rx_over_errors++;
1436                 } else  if (skb) {
1437                         dma_addr = le32_to_cpu(rxdesc->addr);
1438                         if (!mdp->cd->hw_swap)
1439                                 sh_eth_soft_swap(
1440                                         phys_to_virt(ALIGN(dma_addr, 4)),
1441                                         pkt_len + 2);
1442                         mdp->rx_skbuff[entry] = NULL;
1443                         if (mdp->cd->rpadir)
1444                                 skb_reserve(skb, NET_IP_ALIGN);
1445                         dma_unmap_single(&ndev->dev, dma_addr,
1446                                          ALIGN(mdp->rx_buf_sz, 32),
1447                                          DMA_FROM_DEVICE);
1448                         skb_put(skb, pkt_len);
1449                         skb->protocol = eth_type_trans(skb, ndev);
1450                         netif_receive_skb(skb);
1451                         ndev->stats.rx_packets++;
1452                         ndev->stats.rx_bytes += pkt_len;
1453                         if (desc_status & RD_RFS8)
1454                                 ndev->stats.multicast++;
1455                 }
1456                 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1457                 rxdesc = &mdp->rx_ring[entry];
1458         }
1459
1460         /* Refill the Rx ring buffers. */
1461         for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1462                 entry = mdp->dirty_rx % mdp->num_rx_ring;
1463                 rxdesc = &mdp->rx_ring[entry];
1464                 /* The size of the buffer is 32 byte boundary. */
1465                 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1466                 rxdesc->len = cpu_to_le32(buf_len << 16);
1467
1468                 if (mdp->rx_skbuff[entry] == NULL) {
1469                         skb = netdev_alloc_skb(ndev, skbuff_size);
1470                         if (skb == NULL)
1471                                 break;  /* Better luck next round. */
1472                         sh_eth_set_receive_align(skb);
1473                         dma_addr = dma_map_single(&ndev->dev, skb->data,
1474                                                   buf_len, DMA_FROM_DEVICE);
1475                         if (dma_mapping_error(&ndev->dev, dma_addr)) {
1476                                 kfree_skb(skb);
1477                                 break;
1478                         }
1479                         mdp->rx_skbuff[entry] = skb;
1480
1481                         skb_checksum_none_assert(skb);
1482                         rxdesc->addr = cpu_to_le32(dma_addr);
1483                 }
1484                 dma_wmb(); /* RACT bit must be set after all the above writes */
1485                 if (entry >= mdp->num_rx_ring - 1)
1486                         rxdesc->status |=
1487                                 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE);
1488                 else
1489                         rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP);
1490         }
1491
1492         /* Restart Rx engine if stopped. */
1493         /* If we don't need to check status, don't. -KDU */
1494         if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1495                 /* fix the values for the next receiving if RDE is set */
1496                 if (intr_status & EESR_RDE &&
1497                     mdp->reg_offset[RDFAR] != SH_ETH_OFFSET_INVALID) {
1498                         u32 count = (sh_eth_read(ndev, RDFAR) -
1499                                      sh_eth_read(ndev, RDLAR)) >> 4;
1500
1501                         mdp->cur_rx = count;
1502                         mdp->dirty_rx = count;
1503                 }
1504                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1505         }
1506
1507         *quota -= limit - boguscnt - 1;
1508
1509         return *quota <= 0;
1510 }
1511
1512 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1513 {
1514         /* disable tx and rx */
1515         sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
1516 }
1517
1518 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1519 {
1520         /* enable tx and rx */
1521         sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
1522 }
1523
1524 /* error control function */
1525 static void sh_eth_error(struct net_device *ndev, u32 intr_status)
1526 {
1527         struct sh_eth_private *mdp = netdev_priv(ndev);
1528         u32 felic_stat;
1529         u32 link_stat;
1530         u32 mask;
1531
1532         if (intr_status & EESR_ECI) {
1533                 felic_stat = sh_eth_read(ndev, ECSR);
1534                 sh_eth_write(ndev, felic_stat, ECSR);   /* clear int */
1535                 if (felic_stat & ECSR_ICD)
1536                         ndev->stats.tx_carrier_errors++;
1537                 if (felic_stat & ECSR_LCHNG) {
1538                         /* Link Changed */
1539                         if (mdp->cd->no_psr || mdp->no_ether_link) {
1540                                 goto ignore_link;
1541                         } else {
1542                                 link_stat = (sh_eth_read(ndev, PSR));
1543                                 if (mdp->ether_link_active_low)
1544                                         link_stat = ~link_stat;
1545                         }
1546                         if (!(link_stat & PHY_ST_LINK)) {
1547                                 sh_eth_rcv_snd_disable(ndev);
1548                         } else {
1549                                 /* Link Up */
1550                                 sh_eth_modify(ndev, EESIPR, DMAC_M_ECI, 0);
1551                                 /* clear int */
1552                                 sh_eth_modify(ndev, ECSR, 0, 0);
1553                                 sh_eth_modify(ndev, EESIPR, DMAC_M_ECI,
1554                                               DMAC_M_ECI);
1555                                 /* enable tx and rx */
1556                                 sh_eth_rcv_snd_enable(ndev);
1557                         }
1558                 }
1559         }
1560
1561 ignore_link:
1562         if (intr_status & EESR_TWB) {
1563                 /* Unused write back interrupt */
1564                 if (intr_status & EESR_TABT) {  /* Transmit Abort int */
1565                         ndev->stats.tx_aborted_errors++;
1566                         netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1567                 }
1568         }
1569
1570         if (intr_status & EESR_RABT) {
1571                 /* Receive Abort int */
1572                 if (intr_status & EESR_RFRMER) {
1573                         /* Receive Frame Overflow int */
1574                         ndev->stats.rx_frame_errors++;
1575                 }
1576         }
1577
1578         if (intr_status & EESR_TDE) {
1579                 /* Transmit Descriptor Empty int */
1580                 ndev->stats.tx_fifo_errors++;
1581                 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1582         }
1583
1584         if (intr_status & EESR_TFE) {
1585                 /* FIFO under flow */
1586                 ndev->stats.tx_fifo_errors++;
1587                 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1588         }
1589
1590         if (intr_status & EESR_RDE) {
1591                 /* Receive Descriptor Empty int */
1592                 ndev->stats.rx_over_errors++;
1593         }
1594
1595         if (intr_status & EESR_RFE) {
1596                 /* Receive FIFO Overflow int */
1597                 ndev->stats.rx_fifo_errors++;
1598         }
1599
1600         if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1601                 /* Address Error */
1602                 ndev->stats.tx_fifo_errors++;
1603                 netif_err(mdp, tx_err, ndev, "Address Error\n");
1604         }
1605
1606         mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1607         if (mdp->cd->no_ade)
1608                 mask &= ~EESR_ADE;
1609         if (intr_status & mask) {
1610                 /* Tx error */
1611                 u32 edtrr = sh_eth_read(ndev, EDTRR);
1612
1613                 /* dmesg */
1614                 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1615                            intr_status, mdp->cur_tx, mdp->dirty_tx,
1616                            (u32)ndev->state, edtrr);
1617                 /* dirty buffer free */
1618                 sh_eth_txfree(ndev);
1619
1620                 /* SH7712 BUG */
1621                 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1622                         /* tx dma start */
1623                         sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1624                 }
1625                 /* wakeup */
1626                 netif_wake_queue(ndev);
1627         }
1628 }
1629
1630 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1631 {
1632         struct net_device *ndev = netdev;
1633         struct sh_eth_private *mdp = netdev_priv(ndev);
1634         struct sh_eth_cpu_data *cd = mdp->cd;
1635         irqreturn_t ret = IRQ_NONE;
1636         u32 intr_status, intr_enable;
1637
1638         spin_lock(&mdp->lock);
1639
1640         /* Get interrupt status */
1641         intr_status = sh_eth_read(ndev, EESR);
1642         /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1643          * enabled since it's the one that  comes thru regardless of the mask,
1644          * and we need to fully handle it in sh_eth_error() in order to quench
1645          * it as it doesn't get cleared by just writing 1 to the ECI bit...
1646          */
1647         intr_enable = sh_eth_read(ndev, EESIPR);
1648         intr_status &= intr_enable | DMAC_M_ECI;
1649         if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
1650                 ret = IRQ_HANDLED;
1651         else
1652                 goto out;
1653
1654         if (!likely(mdp->irq_enabled)) {
1655                 sh_eth_write(ndev, 0, EESIPR);
1656                 goto out;
1657         }
1658
1659         if (intr_status & EESR_RX_CHECK) {
1660                 if (napi_schedule_prep(&mdp->napi)) {
1661                         /* Mask Rx interrupts */
1662                         sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1663                                      EESIPR);
1664                         __napi_schedule(&mdp->napi);
1665                 } else {
1666                         netdev_warn(ndev,
1667                                     "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
1668                                     intr_status, intr_enable);
1669                 }
1670         }
1671
1672         /* Tx Check */
1673         if (intr_status & cd->tx_check) {
1674                 /* Clear Tx interrupts */
1675                 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1676
1677                 sh_eth_txfree(ndev);
1678                 netif_wake_queue(ndev);
1679         }
1680
1681         if (intr_status & cd->eesr_err_check) {
1682                 /* Clear error interrupts */
1683                 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1684
1685                 sh_eth_error(ndev, intr_status);
1686         }
1687
1688 out:
1689         spin_unlock(&mdp->lock);
1690
1691         return ret;
1692 }
1693
1694 static int sh_eth_poll(struct napi_struct *napi, int budget)
1695 {
1696         struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1697                                                   napi);
1698         struct net_device *ndev = napi->dev;
1699         int quota = budget;
1700         u32 intr_status;
1701
1702         for (;;) {
1703                 intr_status = sh_eth_read(ndev, EESR);
1704                 if (!(intr_status & EESR_RX_CHECK))
1705                         break;
1706                 /* Clear Rx interrupts */
1707                 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1708
1709                 if (sh_eth_rx(ndev, intr_status, &quota))
1710                         goto out;
1711         }
1712
1713         napi_complete(napi);
1714
1715         /* Reenable Rx interrupts */
1716         if (mdp->irq_enabled)
1717                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1718 out:
1719         return budget - quota;
1720 }
1721
1722 /* PHY state control function */
1723 static void sh_eth_adjust_link(struct net_device *ndev)
1724 {
1725         struct sh_eth_private *mdp = netdev_priv(ndev);
1726         struct phy_device *phydev = mdp->phydev;
1727         int new_state = 0;
1728
1729         if (phydev->link) {
1730                 if (phydev->duplex != mdp->duplex) {
1731                         new_state = 1;
1732                         mdp->duplex = phydev->duplex;
1733                         if (mdp->cd->set_duplex)
1734                                 mdp->cd->set_duplex(ndev);
1735                 }
1736
1737                 if (phydev->speed != mdp->speed) {
1738                         new_state = 1;
1739                         mdp->speed = phydev->speed;
1740                         if (mdp->cd->set_rate)
1741                                 mdp->cd->set_rate(ndev);
1742                 }
1743                 if (!mdp->link) {
1744                         sh_eth_modify(ndev, ECMR, ECMR_TXF, 0);
1745                         new_state = 1;
1746                         mdp->link = phydev->link;
1747                         if (mdp->cd->no_psr || mdp->no_ether_link)
1748                                 sh_eth_rcv_snd_enable(ndev);
1749                 }
1750         } else if (mdp->link) {
1751                 new_state = 1;
1752                 mdp->link = 0;
1753                 mdp->speed = 0;
1754                 mdp->duplex = -1;
1755                 if (mdp->cd->no_psr || mdp->no_ether_link)
1756                         sh_eth_rcv_snd_disable(ndev);
1757         }
1758
1759         if (new_state && netif_msg_link(mdp))
1760                 phy_print_status(phydev);
1761 }
1762
1763 /* PHY init function */
1764 static int sh_eth_phy_init(struct net_device *ndev)
1765 {
1766         struct device_node *np = ndev->dev.parent->of_node;
1767         struct sh_eth_private *mdp = netdev_priv(ndev);
1768         struct phy_device *phydev;
1769
1770         mdp->link = 0;
1771         mdp->speed = 0;
1772         mdp->duplex = -1;
1773
1774         /* Try connect to PHY */
1775         if (np) {
1776                 struct device_node *pn;
1777
1778                 pn = of_parse_phandle(np, "phy-handle", 0);
1779                 phydev = of_phy_connect(ndev, pn,
1780                                         sh_eth_adjust_link, 0,
1781                                         mdp->phy_interface);
1782
1783                 of_node_put(pn);
1784                 if (!phydev)
1785                         phydev = ERR_PTR(-ENOENT);
1786         } else {
1787                 char phy_id[MII_BUS_ID_SIZE + 3];
1788
1789                 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1790                          mdp->mii_bus->id, mdp->phy_id);
1791
1792                 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1793                                      mdp->phy_interface);
1794         }
1795
1796         if (IS_ERR(phydev)) {
1797                 netdev_err(ndev, "failed to connect PHY\n");
1798                 return PTR_ERR(phydev);
1799         }
1800
1801         phy_attached_info(phydev);
1802
1803         mdp->phydev = phydev;
1804
1805         return 0;
1806 }
1807
1808 /* PHY control start function */
1809 static int sh_eth_phy_start(struct net_device *ndev)
1810 {
1811         struct sh_eth_private *mdp = netdev_priv(ndev);
1812         int ret;
1813
1814         ret = sh_eth_phy_init(ndev);
1815         if (ret)
1816                 return ret;
1817
1818         phy_start(mdp->phydev);
1819
1820         return 0;
1821 }
1822
1823 static int sh_eth_get_settings(struct net_device *ndev,
1824                                struct ethtool_cmd *ecmd)
1825 {
1826         struct sh_eth_private *mdp = netdev_priv(ndev);
1827         unsigned long flags;
1828         int ret;
1829
1830         if (!mdp->phydev)
1831                 return -ENODEV;
1832
1833         spin_lock_irqsave(&mdp->lock, flags);
1834         ret = phy_ethtool_gset(mdp->phydev, ecmd);
1835         spin_unlock_irqrestore(&mdp->lock, flags);
1836
1837         return ret;
1838 }
1839
1840 static int sh_eth_set_settings(struct net_device *ndev,
1841                                struct ethtool_cmd *ecmd)
1842 {
1843         struct sh_eth_private *mdp = netdev_priv(ndev);
1844         unsigned long flags;
1845         int ret;
1846
1847         if (!mdp->phydev)
1848                 return -ENODEV;
1849
1850         spin_lock_irqsave(&mdp->lock, flags);
1851
1852         /* disable tx and rx */
1853         sh_eth_rcv_snd_disable(ndev);
1854
1855         ret = phy_ethtool_sset(mdp->phydev, ecmd);
1856         if (ret)
1857                 goto error_exit;
1858
1859         if (ecmd->duplex == DUPLEX_FULL)
1860                 mdp->duplex = 1;
1861         else
1862                 mdp->duplex = 0;
1863
1864         if (mdp->cd->set_duplex)
1865                 mdp->cd->set_duplex(ndev);
1866
1867 error_exit:
1868         mdelay(1);
1869
1870         /* enable tx and rx */
1871         sh_eth_rcv_snd_enable(ndev);
1872
1873         spin_unlock_irqrestore(&mdp->lock, flags);
1874
1875         return ret;
1876 }
1877
1878 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
1879  * version must be bumped as well.  Just adding registers up to that
1880  * limit is fine, as long as the existing register indices don't
1881  * change.
1882  */
1883 #define SH_ETH_REG_DUMP_VERSION         1
1884 #define SH_ETH_REG_DUMP_MAX_REGS        256
1885
1886 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
1887 {
1888         struct sh_eth_private *mdp = netdev_priv(ndev);
1889         struct sh_eth_cpu_data *cd = mdp->cd;
1890         u32 *valid_map;
1891         size_t len;
1892
1893         BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
1894
1895         /* Dump starts with a bitmap that tells ethtool which
1896          * registers are defined for this chip.
1897          */
1898         len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
1899         if (buf) {
1900                 valid_map = buf;
1901                 buf += len;
1902         } else {
1903                 valid_map = NULL;
1904         }
1905
1906         /* Add a register to the dump, if it has a defined offset.
1907          * This automatically skips most undefined registers, but for
1908          * some it is also necessary to check a capability flag in
1909          * struct sh_eth_cpu_data.
1910          */
1911 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
1912 #define add_reg_from(reg, read_expr) do {                               \
1913                 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) {    \
1914                         if (buf) {                                      \
1915                                 mark_reg_valid(reg);                    \
1916                                 *buf++ = read_expr;                     \
1917                         }                                               \
1918                         ++len;                                          \
1919                 }                                                       \
1920         } while (0)
1921 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
1922 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
1923
1924         add_reg(EDSR);
1925         add_reg(EDMR);
1926         add_reg(EDTRR);
1927         add_reg(EDRRR);
1928         add_reg(EESR);
1929         add_reg(EESIPR);
1930         add_reg(TDLAR);
1931         add_reg(TDFAR);
1932         add_reg(TDFXR);
1933         add_reg(TDFFR);
1934         add_reg(RDLAR);
1935         add_reg(RDFAR);
1936         add_reg(RDFXR);
1937         add_reg(RDFFR);
1938         add_reg(TRSCER);
1939         add_reg(RMFCR);
1940         add_reg(TFTR);
1941         add_reg(FDR);
1942         add_reg(RMCR);
1943         add_reg(TFUCR);
1944         add_reg(RFOCR);
1945         if (cd->rmiimode)
1946                 add_reg(RMIIMODE);
1947         add_reg(FCFTR);
1948         if (cd->rpadir)
1949                 add_reg(RPADIR);
1950         if (!cd->no_trimd)
1951                 add_reg(TRIMD);
1952         add_reg(ECMR);
1953         add_reg(ECSR);
1954         add_reg(ECSIPR);
1955         add_reg(PIR);
1956         if (!cd->no_psr)
1957                 add_reg(PSR);
1958         add_reg(RDMLR);
1959         add_reg(RFLR);
1960         add_reg(IPGR);
1961         if (cd->apr)
1962                 add_reg(APR);
1963         if (cd->mpr)
1964                 add_reg(MPR);
1965         add_reg(RFCR);
1966         add_reg(RFCF);
1967         if (cd->tpauser)
1968                 add_reg(TPAUSER);
1969         add_reg(TPAUSECR);
1970         add_reg(GECMR);
1971         if (cd->bculr)
1972                 add_reg(BCULR);
1973         add_reg(MAHR);
1974         add_reg(MALR);
1975         add_reg(TROCR);
1976         add_reg(CDCR);
1977         add_reg(LCCR);
1978         add_reg(CNDCR);
1979         add_reg(CEFCR);
1980         add_reg(FRECR);
1981         add_reg(TSFRCR);
1982         add_reg(TLFRCR);
1983         add_reg(CERCR);
1984         add_reg(CEECR);
1985         add_reg(MAFCR);
1986         if (cd->rtrate)
1987                 add_reg(RTRATE);
1988         if (cd->hw_crc)
1989                 add_reg(CSMR);
1990         if (cd->select_mii)
1991                 add_reg(RMII_MII);
1992         add_reg(ARSTR);
1993         if (cd->tsu) {
1994                 add_tsu_reg(TSU_CTRST);
1995                 add_tsu_reg(TSU_FWEN0);
1996                 add_tsu_reg(TSU_FWEN1);
1997                 add_tsu_reg(TSU_FCM);
1998                 add_tsu_reg(TSU_BSYSL0);
1999                 add_tsu_reg(TSU_BSYSL1);
2000                 add_tsu_reg(TSU_PRISL0);
2001                 add_tsu_reg(TSU_PRISL1);
2002                 add_tsu_reg(TSU_FWSL0);
2003                 add_tsu_reg(TSU_FWSL1);
2004                 add_tsu_reg(TSU_FWSLC);
2005                 add_tsu_reg(TSU_QTAG0);
2006                 add_tsu_reg(TSU_QTAG1);
2007                 add_tsu_reg(TSU_QTAGM0);
2008                 add_tsu_reg(TSU_QTAGM1);
2009                 add_tsu_reg(TSU_FWSR);
2010                 add_tsu_reg(TSU_FWINMK);
2011                 add_tsu_reg(TSU_ADQT0);
2012                 add_tsu_reg(TSU_ADQT1);
2013                 add_tsu_reg(TSU_VTAG0);
2014                 add_tsu_reg(TSU_VTAG1);
2015                 add_tsu_reg(TSU_ADSBSY);
2016                 add_tsu_reg(TSU_TEN);
2017                 add_tsu_reg(TSU_POST1);
2018                 add_tsu_reg(TSU_POST2);
2019                 add_tsu_reg(TSU_POST3);
2020                 add_tsu_reg(TSU_POST4);
2021                 if (mdp->reg_offset[TSU_ADRH0] != SH_ETH_OFFSET_INVALID) {
2022                         /* This is the start of a table, not just a single
2023                          * register.
2024                          */
2025                         if (buf) {
2026                                 unsigned int i;
2027
2028                                 mark_reg_valid(TSU_ADRH0);
2029                                 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2030                                         *buf++ = ioread32(
2031                                                 mdp->tsu_addr +
2032                                                 mdp->reg_offset[TSU_ADRH0] +
2033                                                 i * 4);
2034                         }
2035                         len += SH_ETH_TSU_CAM_ENTRIES * 2;
2036                 }
2037         }
2038
2039 #undef mark_reg_valid
2040 #undef add_reg_from
2041 #undef add_reg
2042 #undef add_tsu_reg
2043
2044         return len * 4;
2045 }
2046
2047 static int sh_eth_get_regs_len(struct net_device *ndev)
2048 {
2049         return __sh_eth_get_regs(ndev, NULL);
2050 }
2051
2052 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2053                             void *buf)
2054 {
2055         struct sh_eth_private *mdp = netdev_priv(ndev);
2056
2057         regs->version = SH_ETH_REG_DUMP_VERSION;
2058
2059         pm_runtime_get_sync(&mdp->pdev->dev);
2060         __sh_eth_get_regs(ndev, buf);
2061         pm_runtime_put_sync(&mdp->pdev->dev);
2062 }
2063
2064 static int sh_eth_nway_reset(struct net_device *ndev)
2065 {
2066         struct sh_eth_private *mdp = netdev_priv(ndev);
2067         unsigned long flags;
2068         int ret;
2069
2070         if (!mdp->phydev)
2071                 return -ENODEV;
2072
2073         spin_lock_irqsave(&mdp->lock, flags);
2074         ret = phy_start_aneg(mdp->phydev);
2075         spin_unlock_irqrestore(&mdp->lock, flags);
2076
2077         return ret;
2078 }
2079
2080 static u32 sh_eth_get_msglevel(struct net_device *ndev)
2081 {
2082         struct sh_eth_private *mdp = netdev_priv(ndev);
2083         return mdp->msg_enable;
2084 }
2085
2086 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2087 {
2088         struct sh_eth_private *mdp = netdev_priv(ndev);
2089         mdp->msg_enable = value;
2090 }
2091
2092 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2093         "rx_current", "tx_current",
2094         "rx_dirty", "tx_dirty",
2095 };
2096 #define SH_ETH_STATS_LEN  ARRAY_SIZE(sh_eth_gstrings_stats)
2097
2098 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2099 {
2100         switch (sset) {
2101         case ETH_SS_STATS:
2102                 return SH_ETH_STATS_LEN;
2103         default:
2104                 return -EOPNOTSUPP;
2105         }
2106 }
2107
2108 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
2109                                      struct ethtool_stats *stats, u64 *data)
2110 {
2111         struct sh_eth_private *mdp = netdev_priv(ndev);
2112         int i = 0;
2113
2114         /* device-specific stats */
2115         data[i++] = mdp->cur_rx;
2116         data[i++] = mdp->cur_tx;
2117         data[i++] = mdp->dirty_rx;
2118         data[i++] = mdp->dirty_tx;
2119 }
2120
2121 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2122 {
2123         switch (stringset) {
2124         case ETH_SS_STATS:
2125                 memcpy(data, *sh_eth_gstrings_stats,
2126                        sizeof(sh_eth_gstrings_stats));
2127                 break;
2128         }
2129 }
2130
2131 static void sh_eth_get_ringparam(struct net_device *ndev,
2132                                  struct ethtool_ringparam *ring)
2133 {
2134         struct sh_eth_private *mdp = netdev_priv(ndev);
2135
2136         ring->rx_max_pending = RX_RING_MAX;
2137         ring->tx_max_pending = TX_RING_MAX;
2138         ring->rx_pending = mdp->num_rx_ring;
2139         ring->tx_pending = mdp->num_tx_ring;
2140 }
2141
2142 static int sh_eth_set_ringparam(struct net_device *ndev,
2143                                 struct ethtool_ringparam *ring)
2144 {
2145         struct sh_eth_private *mdp = netdev_priv(ndev);
2146         int ret;
2147
2148         if (ring->tx_pending > TX_RING_MAX ||
2149             ring->rx_pending > RX_RING_MAX ||
2150             ring->tx_pending < TX_RING_MIN ||
2151             ring->rx_pending < RX_RING_MIN)
2152                 return -EINVAL;
2153         if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2154                 return -EINVAL;
2155
2156         if (netif_running(ndev)) {
2157                 netif_device_detach(ndev);
2158                 netif_tx_disable(ndev);
2159
2160                 /* Serialise with the interrupt handler and NAPI, then
2161                  * disable interrupts.  We have to clear the
2162                  * irq_enabled flag first to ensure that interrupts
2163                  * won't be re-enabled.
2164                  */
2165                 mdp->irq_enabled = false;
2166                 synchronize_irq(ndev->irq);
2167                 napi_synchronize(&mdp->napi);
2168                 sh_eth_write(ndev, 0x0000, EESIPR);
2169
2170                 sh_eth_dev_exit(ndev);
2171
2172                 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
2173                 sh_eth_ring_free(ndev);
2174         }
2175
2176         /* Set new parameters */
2177         mdp->num_rx_ring = ring->rx_pending;
2178         mdp->num_tx_ring = ring->tx_pending;
2179
2180         if (netif_running(ndev)) {
2181                 ret = sh_eth_ring_init(ndev);
2182                 if (ret < 0) {
2183                         netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2184                                    __func__);
2185                         return ret;
2186                 }
2187                 ret = sh_eth_dev_init(ndev);
2188                 if (ret < 0) {
2189                         netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2190                                    __func__);
2191                         return ret;
2192                 }
2193
2194                 netif_device_attach(ndev);
2195         }
2196
2197         return 0;
2198 }
2199
2200 static const struct ethtool_ops sh_eth_ethtool_ops = {
2201         .get_settings   = sh_eth_get_settings,
2202         .set_settings   = sh_eth_set_settings,
2203         .get_regs_len   = sh_eth_get_regs_len,
2204         .get_regs       = sh_eth_get_regs,
2205         .nway_reset     = sh_eth_nway_reset,
2206         .get_msglevel   = sh_eth_get_msglevel,
2207         .set_msglevel   = sh_eth_set_msglevel,
2208         .get_link       = ethtool_op_get_link,
2209         .get_strings    = sh_eth_get_strings,
2210         .get_ethtool_stats  = sh_eth_get_ethtool_stats,
2211         .get_sset_count     = sh_eth_get_sset_count,
2212         .get_ringparam  = sh_eth_get_ringparam,
2213         .set_ringparam  = sh_eth_set_ringparam,
2214 };
2215
2216 /* network device open function */
2217 static int sh_eth_open(struct net_device *ndev)
2218 {
2219         struct sh_eth_private *mdp = netdev_priv(ndev);
2220         int ret;
2221
2222         pm_runtime_get_sync(&mdp->pdev->dev);
2223
2224         napi_enable(&mdp->napi);
2225
2226         ret = request_irq(ndev->irq, sh_eth_interrupt,
2227                           mdp->cd->irq_flags, ndev->name, ndev);
2228         if (ret) {
2229                 netdev_err(ndev, "Can not assign IRQ number\n");
2230                 goto out_napi_off;
2231         }
2232
2233         /* Descriptor set */
2234         ret = sh_eth_ring_init(ndev);
2235         if (ret)
2236                 goto out_free_irq;
2237
2238         /* device init */
2239         ret = sh_eth_dev_init(ndev);
2240         if (ret)
2241                 goto out_free_irq;
2242
2243         /* PHY control start*/
2244         ret = sh_eth_phy_start(ndev);
2245         if (ret)
2246                 goto out_free_irq;
2247
2248         netif_start_queue(ndev);
2249
2250         mdp->is_opened = 1;
2251
2252         return ret;
2253
2254 out_free_irq:
2255         free_irq(ndev->irq, ndev);
2256 out_napi_off:
2257         napi_disable(&mdp->napi);
2258         pm_runtime_put_sync(&mdp->pdev->dev);
2259         return ret;
2260 }
2261
2262 /* Timeout function */
2263 static void sh_eth_tx_timeout(struct net_device *ndev)
2264 {
2265         struct sh_eth_private *mdp = netdev_priv(ndev);
2266         struct sh_eth_rxdesc *rxdesc;
2267         int i;
2268
2269         netif_stop_queue(ndev);
2270
2271         netif_err(mdp, timer, ndev,
2272                   "transmit timed out, status %8.8x, resetting...\n",
2273                   sh_eth_read(ndev, EESR));
2274
2275         /* tx_errors count up */
2276         ndev->stats.tx_errors++;
2277
2278         /* Free all the skbuffs in the Rx queue. */
2279         for (i = 0; i < mdp->num_rx_ring; i++) {
2280                 rxdesc = &mdp->rx_ring[i];
2281                 rxdesc->status = cpu_to_le32(0);
2282                 rxdesc->addr = cpu_to_le32(0xBADF00D0);
2283                 dev_kfree_skb(mdp->rx_skbuff[i]);
2284                 mdp->rx_skbuff[i] = NULL;
2285         }
2286         for (i = 0; i < mdp->num_tx_ring; i++) {
2287                 dev_kfree_skb(mdp->tx_skbuff[i]);
2288                 mdp->tx_skbuff[i] = NULL;
2289         }
2290
2291         /* device init */
2292         sh_eth_dev_init(ndev);
2293
2294         netif_start_queue(ndev);
2295 }
2296
2297 /* Packet transmit function */
2298 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2299 {
2300         struct sh_eth_private *mdp = netdev_priv(ndev);
2301         struct sh_eth_txdesc *txdesc;
2302         dma_addr_t dma_addr;
2303         u32 entry;
2304         unsigned long flags;
2305
2306         spin_lock_irqsave(&mdp->lock, flags);
2307         if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2308                 if (!sh_eth_txfree(ndev)) {
2309                         netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2310                         netif_stop_queue(ndev);
2311                         spin_unlock_irqrestore(&mdp->lock, flags);
2312                         return NETDEV_TX_BUSY;
2313                 }
2314         }
2315         spin_unlock_irqrestore(&mdp->lock, flags);
2316
2317         if (skb_put_padto(skb, ETH_ZLEN))
2318                 return NETDEV_TX_OK;
2319
2320         entry = mdp->cur_tx % mdp->num_tx_ring;
2321         mdp->tx_skbuff[entry] = skb;
2322         txdesc = &mdp->tx_ring[entry];
2323         /* soft swap. */
2324         if (!mdp->cd->hw_swap)
2325                 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
2326         dma_addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2327                                   DMA_TO_DEVICE);
2328         if (dma_mapping_error(&ndev->dev, dma_addr)) {
2329                 kfree_skb(skb);
2330                 return NETDEV_TX_OK;
2331         }
2332         txdesc->addr = cpu_to_le32(dma_addr);
2333         txdesc->len  = cpu_to_le32(skb->len << 16);
2334
2335         dma_wmb(); /* TACT bit must be set after all the above writes */
2336         if (entry >= mdp->num_tx_ring - 1)
2337                 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE);
2338         else
2339                 txdesc->status |= cpu_to_le32(TD_TACT);
2340
2341         mdp->cur_tx++;
2342
2343         if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2344                 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
2345
2346         return NETDEV_TX_OK;
2347 }
2348
2349 /* The statistics registers have write-clear behaviour, which means we
2350  * will lose any increment between the read and write.  We mitigate
2351  * this by only clearing when we read a non-zero value, so we will
2352  * never falsely report a total of zero.
2353  */
2354 static void
2355 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2356 {
2357         u32 delta = sh_eth_read(ndev, reg);
2358
2359         if (delta) {
2360                 *stat += delta;
2361                 sh_eth_write(ndev, 0, reg);
2362         }
2363 }
2364
2365 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2366 {
2367         struct sh_eth_private *mdp = netdev_priv(ndev);
2368
2369         if (sh_eth_is_rz_fast_ether(mdp))
2370                 return &ndev->stats;
2371
2372         if (!mdp->is_opened)
2373                 return &ndev->stats;
2374
2375         sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2376         sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2377         sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
2378
2379         if (sh_eth_is_gether(mdp)) {
2380                 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2381                                    CERCR);
2382                 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2383                                    CEECR);
2384         } else {
2385                 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2386                                    CNDCR);
2387         }
2388
2389         return &ndev->stats;
2390 }
2391
2392 /* device close function */
2393 static int sh_eth_close(struct net_device *ndev)
2394 {
2395         struct sh_eth_private *mdp = netdev_priv(ndev);
2396
2397         netif_stop_queue(ndev);
2398
2399         /* Serialise with the interrupt handler and NAPI, then disable
2400          * interrupts.  We have to clear the irq_enabled flag first to
2401          * ensure that interrupts won't be re-enabled.
2402          */
2403         mdp->irq_enabled = false;
2404         synchronize_irq(ndev->irq);
2405         napi_disable(&mdp->napi);
2406         sh_eth_write(ndev, 0x0000, EESIPR);
2407
2408         sh_eth_dev_exit(ndev);
2409
2410         /* PHY Disconnect */
2411         if (mdp->phydev) {
2412                 phy_stop(mdp->phydev);
2413                 phy_disconnect(mdp->phydev);
2414                 mdp->phydev = NULL;
2415         }
2416
2417         free_irq(ndev->irq, ndev);
2418
2419         /* Free all the skbuffs in the Rx queue and the DMA buffer. */
2420         sh_eth_ring_free(ndev);
2421
2422         pm_runtime_put_sync(&mdp->pdev->dev);
2423
2424         mdp->is_opened = 0;
2425
2426         return 0;
2427 }
2428
2429 /* ioctl to device function */
2430 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2431 {
2432         struct sh_eth_private *mdp = netdev_priv(ndev);
2433         struct phy_device *phydev = mdp->phydev;
2434
2435         if (!netif_running(ndev))
2436                 return -EINVAL;
2437
2438         if (!phydev)
2439                 return -ENODEV;
2440
2441         return phy_mii_ioctl(phydev, rq, cmd);
2442 }
2443
2444 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2445 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2446                                             int entry)
2447 {
2448         return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2449 }
2450
2451 static u32 sh_eth_tsu_get_post_mask(int entry)
2452 {
2453         return 0x0f << (28 - ((entry % 8) * 4));
2454 }
2455
2456 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2457 {
2458         return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2459 }
2460
2461 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2462                                              int entry)
2463 {
2464         struct sh_eth_private *mdp = netdev_priv(ndev);
2465         u32 tmp;
2466         void *reg_offset;
2467
2468         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2469         tmp = ioread32(reg_offset);
2470         iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2471 }
2472
2473 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2474                                               int entry)
2475 {
2476         struct sh_eth_private *mdp = netdev_priv(ndev);
2477         u32 post_mask, ref_mask, tmp;
2478         void *reg_offset;
2479
2480         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2481         post_mask = sh_eth_tsu_get_post_mask(entry);
2482         ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2483
2484         tmp = ioread32(reg_offset);
2485         iowrite32(tmp & ~post_mask, reg_offset);
2486
2487         /* If other port enables, the function returns "true" */
2488         return tmp & ref_mask;
2489 }
2490
2491 static int sh_eth_tsu_busy(struct net_device *ndev)
2492 {
2493         int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2494         struct sh_eth_private *mdp = netdev_priv(ndev);
2495
2496         while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2497                 udelay(10);
2498                 timeout--;
2499                 if (timeout <= 0) {
2500                         netdev_err(ndev, "%s: timeout\n", __func__);
2501                         return -ETIMEDOUT;
2502                 }
2503         }
2504
2505         return 0;
2506 }
2507
2508 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2509                                   const u8 *addr)
2510 {
2511         u32 val;
2512
2513         val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2514         iowrite32(val, reg);
2515         if (sh_eth_tsu_busy(ndev) < 0)
2516                 return -EBUSY;
2517
2518         val = addr[4] << 8 | addr[5];
2519         iowrite32(val, reg + 4);
2520         if (sh_eth_tsu_busy(ndev) < 0)
2521                 return -EBUSY;
2522
2523         return 0;
2524 }
2525
2526 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2527 {
2528         u32 val;
2529
2530         val = ioread32(reg);
2531         addr[0] = (val >> 24) & 0xff;
2532         addr[1] = (val >> 16) & 0xff;
2533         addr[2] = (val >> 8) & 0xff;
2534         addr[3] = val & 0xff;
2535         val = ioread32(reg + 4);
2536         addr[4] = (val >> 8) & 0xff;
2537         addr[5] = val & 0xff;
2538 }
2539
2540
2541 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2542 {
2543         struct sh_eth_private *mdp = netdev_priv(ndev);
2544         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2545         int i;
2546         u8 c_addr[ETH_ALEN];
2547
2548         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2549                 sh_eth_tsu_read_entry(reg_offset, c_addr);
2550                 if (ether_addr_equal(addr, c_addr))
2551                         return i;
2552         }
2553
2554         return -ENOENT;
2555 }
2556
2557 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2558 {
2559         u8 blank[ETH_ALEN];
2560         int entry;
2561
2562         memset(blank, 0, sizeof(blank));
2563         entry = sh_eth_tsu_find_entry(ndev, blank);
2564         return (entry < 0) ? -ENOMEM : entry;
2565 }
2566
2567 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2568                                               int entry)
2569 {
2570         struct sh_eth_private *mdp = netdev_priv(ndev);
2571         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2572         int ret;
2573         u8 blank[ETH_ALEN];
2574
2575         sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2576                          ~(1 << (31 - entry)), TSU_TEN);
2577
2578         memset(blank, 0, sizeof(blank));
2579         ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2580         if (ret < 0)
2581                 return ret;
2582         return 0;
2583 }
2584
2585 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2586 {
2587         struct sh_eth_private *mdp = netdev_priv(ndev);
2588         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2589         int i, ret;
2590
2591         if (!mdp->cd->tsu)
2592                 return 0;
2593
2594         i = sh_eth_tsu_find_entry(ndev, addr);
2595         if (i < 0) {
2596                 /* No entry found, create one */
2597                 i = sh_eth_tsu_find_empty(ndev);
2598                 if (i < 0)
2599                         return -ENOMEM;
2600                 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2601                 if (ret < 0)
2602                         return ret;
2603
2604                 /* Enable the entry */
2605                 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2606                                  (1 << (31 - i)), TSU_TEN);
2607         }
2608
2609         /* Entry found or created, enable POST */
2610         sh_eth_tsu_enable_cam_entry_post(ndev, i);
2611
2612         return 0;
2613 }
2614
2615 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2616 {
2617         struct sh_eth_private *mdp = netdev_priv(ndev);
2618         int i, ret;
2619
2620         if (!mdp->cd->tsu)
2621                 return 0;
2622
2623         i = sh_eth_tsu_find_entry(ndev, addr);
2624         if (i) {
2625                 /* Entry found */
2626                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2627                         goto done;
2628
2629                 /* Disable the entry if both ports was disabled */
2630                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2631                 if (ret < 0)
2632                         return ret;
2633         }
2634 done:
2635         return 0;
2636 }
2637
2638 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2639 {
2640         struct sh_eth_private *mdp = netdev_priv(ndev);
2641         int i, ret;
2642
2643         if (!mdp->cd->tsu)
2644                 return 0;
2645
2646         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2647                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2648                         continue;
2649
2650                 /* Disable the entry if both ports was disabled */
2651                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2652                 if (ret < 0)
2653                         return ret;
2654         }
2655
2656         return 0;
2657 }
2658
2659 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2660 {
2661         struct sh_eth_private *mdp = netdev_priv(ndev);
2662         u8 addr[ETH_ALEN];
2663         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2664         int i;
2665
2666         if (!mdp->cd->tsu)
2667                 return;
2668
2669         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2670                 sh_eth_tsu_read_entry(reg_offset, addr);
2671                 if (is_multicast_ether_addr(addr))
2672                         sh_eth_tsu_del_entry(ndev, addr);
2673         }
2674 }
2675
2676 /* Update promiscuous flag and multicast filter */
2677 static void sh_eth_set_rx_mode(struct net_device *ndev)
2678 {
2679         struct sh_eth_private *mdp = netdev_priv(ndev);
2680         u32 ecmr_bits;
2681         int mcast_all = 0;
2682         unsigned long flags;
2683
2684         spin_lock_irqsave(&mdp->lock, flags);
2685         /* Initial condition is MCT = 1, PRM = 0.
2686          * Depending on ndev->flags, set PRM or clear MCT
2687          */
2688         ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2689         if (mdp->cd->tsu)
2690                 ecmr_bits |= ECMR_MCT;
2691
2692         if (!(ndev->flags & IFF_MULTICAST)) {
2693                 sh_eth_tsu_purge_mcast(ndev);
2694                 mcast_all = 1;
2695         }
2696         if (ndev->flags & IFF_ALLMULTI) {
2697                 sh_eth_tsu_purge_mcast(ndev);
2698                 ecmr_bits &= ~ECMR_MCT;
2699                 mcast_all = 1;
2700         }
2701
2702         if (ndev->flags & IFF_PROMISC) {
2703                 sh_eth_tsu_purge_all(ndev);
2704                 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2705         } else if (mdp->cd->tsu) {
2706                 struct netdev_hw_addr *ha;
2707                 netdev_for_each_mc_addr(ha, ndev) {
2708                         if (mcast_all && is_multicast_ether_addr(ha->addr))
2709                                 continue;
2710
2711                         if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2712                                 if (!mcast_all) {
2713                                         sh_eth_tsu_purge_mcast(ndev);
2714                                         ecmr_bits &= ~ECMR_MCT;
2715                                         mcast_all = 1;
2716                                 }
2717                         }
2718                 }
2719         }
2720
2721         /* update the ethernet mode */
2722         sh_eth_write(ndev, ecmr_bits, ECMR);
2723
2724         spin_unlock_irqrestore(&mdp->lock, flags);
2725 }
2726
2727 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2728 {
2729         if (!mdp->port)
2730                 return TSU_VTAG0;
2731         else
2732                 return TSU_VTAG1;
2733 }
2734
2735 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2736                                   __be16 proto, u16 vid)
2737 {
2738         struct sh_eth_private *mdp = netdev_priv(ndev);
2739         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2740
2741         if (unlikely(!mdp->cd->tsu))
2742                 return -EPERM;
2743
2744         /* No filtering if vid = 0 */
2745         if (!vid)
2746                 return 0;
2747
2748         mdp->vlan_num_ids++;
2749
2750         /* The controller has one VLAN tag HW filter. So, if the filter is
2751          * already enabled, the driver disables it and the filte
2752          */
2753         if (mdp->vlan_num_ids > 1) {
2754                 /* disable VLAN filter */
2755                 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2756                 return 0;
2757         }
2758
2759         sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2760                          vtag_reg_index);
2761
2762         return 0;
2763 }
2764
2765 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2766                                    __be16 proto, u16 vid)
2767 {
2768         struct sh_eth_private *mdp = netdev_priv(ndev);
2769         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2770
2771         if (unlikely(!mdp->cd->tsu))
2772                 return -EPERM;
2773
2774         /* No filtering if vid = 0 */
2775         if (!vid)
2776                 return 0;
2777
2778         mdp->vlan_num_ids--;
2779         sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2780
2781         return 0;
2782 }
2783
2784 /* SuperH's TSU register init function */
2785 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2786 {
2787         if (sh_eth_is_rz_fast_ether(mdp)) {
2788                 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2789                 return;
2790         }
2791
2792         sh_eth_tsu_write(mdp, 0, TSU_FWEN0);    /* Disable forward(0->1) */
2793         sh_eth_tsu_write(mdp, 0, TSU_FWEN1);    /* Disable forward(1->0) */
2794         sh_eth_tsu_write(mdp, 0, TSU_FCM);      /* forward fifo 3k-3k */
2795         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2796         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2797         sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2798         sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2799         sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2800         sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2801         sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2802         if (sh_eth_is_gether(mdp)) {
2803                 sh_eth_tsu_write(mdp, 0, TSU_QTAG0);    /* Disable QTAG(0->1) */
2804                 sh_eth_tsu_write(mdp, 0, TSU_QTAG1);    /* Disable QTAG(1->0) */
2805         } else {
2806                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0);   /* Disable QTAG(0->1) */
2807                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1);   /* Disable QTAG(1->0) */
2808         }
2809         sh_eth_tsu_write(mdp, 0, TSU_FWSR);     /* all interrupt status clear */
2810         sh_eth_tsu_write(mdp, 0, TSU_FWINMK);   /* Disable all interrupt */
2811         sh_eth_tsu_write(mdp, 0, TSU_TEN);      /* Disable all CAM entry */
2812         sh_eth_tsu_write(mdp, 0, TSU_POST1);    /* Disable CAM entry [ 0- 7] */
2813         sh_eth_tsu_write(mdp, 0, TSU_POST2);    /* Disable CAM entry [ 8-15] */
2814         sh_eth_tsu_write(mdp, 0, TSU_POST3);    /* Disable CAM entry [16-23] */
2815         sh_eth_tsu_write(mdp, 0, TSU_POST4);    /* Disable CAM entry [24-31] */
2816 }
2817
2818 /* MDIO bus release function */
2819 static int sh_mdio_release(struct sh_eth_private *mdp)
2820 {
2821         /* unregister mdio bus */
2822         mdiobus_unregister(mdp->mii_bus);
2823
2824         /* free bitbang info */
2825         free_mdio_bitbang(mdp->mii_bus);
2826
2827         return 0;
2828 }
2829
2830 /* MDIO bus init function */
2831 static int sh_mdio_init(struct sh_eth_private *mdp,
2832                         struct sh_eth_plat_data *pd)
2833 {
2834         int ret;
2835         struct bb_info *bitbang;
2836         struct platform_device *pdev = mdp->pdev;
2837         struct device *dev = &mdp->pdev->dev;
2838
2839         /* create bit control struct for PHY */
2840         bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
2841         if (!bitbang)
2842                 return -ENOMEM;
2843
2844         /* bitbang init */
2845         bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2846         bitbang->set_gate = pd->set_mdio_gate;
2847         bitbang->ctrl.ops = &bb_ops;
2848
2849         /* MII controller setting */
2850         mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2851         if (!mdp->mii_bus)
2852                 return -ENOMEM;
2853
2854         /* Hook up MII support for ethtool */
2855         mdp->mii_bus->name = "sh_mii";
2856         mdp->mii_bus->parent = dev;
2857         snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2858                  pdev->name, pdev->id);
2859
2860         /* register MDIO bus */
2861         if (dev->of_node) {
2862                 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
2863         } else {
2864                 if (pd->phy_irq > 0)
2865                         mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2866
2867                 ret = mdiobus_register(mdp->mii_bus);
2868         }
2869
2870         if (ret)
2871                 goto out_free_bus;
2872
2873         return 0;
2874
2875 out_free_bus:
2876         free_mdio_bitbang(mdp->mii_bus);
2877         return ret;
2878 }
2879
2880 static const u16 *sh_eth_get_register_offset(int register_type)
2881 {
2882         const u16 *reg_offset = NULL;
2883
2884         switch (register_type) {
2885         case SH_ETH_REG_GIGABIT:
2886                 reg_offset = sh_eth_offset_gigabit;
2887                 break;
2888         case SH_ETH_REG_FAST_RZ:
2889                 reg_offset = sh_eth_offset_fast_rz;
2890                 break;
2891         case SH_ETH_REG_FAST_RCAR:
2892                 reg_offset = sh_eth_offset_fast_rcar;
2893                 break;
2894         case SH_ETH_REG_FAST_SH4:
2895                 reg_offset = sh_eth_offset_fast_sh4;
2896                 break;
2897         case SH_ETH_REG_FAST_SH3_SH2:
2898                 reg_offset = sh_eth_offset_fast_sh3_sh2;
2899                 break;
2900         }
2901
2902         return reg_offset;
2903 }
2904
2905 static const struct net_device_ops sh_eth_netdev_ops = {
2906         .ndo_open               = sh_eth_open,
2907         .ndo_stop               = sh_eth_close,
2908         .ndo_start_xmit         = sh_eth_start_xmit,
2909         .ndo_get_stats          = sh_eth_get_stats,
2910         .ndo_set_rx_mode        = sh_eth_set_rx_mode,
2911         .ndo_tx_timeout         = sh_eth_tx_timeout,
2912         .ndo_do_ioctl           = sh_eth_do_ioctl,
2913         .ndo_validate_addr      = eth_validate_addr,
2914         .ndo_set_mac_address    = eth_mac_addr,
2915         .ndo_change_mtu         = eth_change_mtu,
2916 };
2917
2918 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2919         .ndo_open               = sh_eth_open,
2920         .ndo_stop               = sh_eth_close,
2921         .ndo_start_xmit         = sh_eth_start_xmit,
2922         .ndo_get_stats          = sh_eth_get_stats,
2923         .ndo_set_rx_mode        = sh_eth_set_rx_mode,
2924         .ndo_vlan_rx_add_vid    = sh_eth_vlan_rx_add_vid,
2925         .ndo_vlan_rx_kill_vid   = sh_eth_vlan_rx_kill_vid,
2926         .ndo_tx_timeout         = sh_eth_tx_timeout,
2927         .ndo_do_ioctl           = sh_eth_do_ioctl,
2928         .ndo_validate_addr      = eth_validate_addr,
2929         .ndo_set_mac_address    = eth_mac_addr,
2930         .ndo_change_mtu         = eth_change_mtu,
2931 };
2932
2933 #ifdef CONFIG_OF
2934 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2935 {
2936         struct device_node *np = dev->of_node;
2937         struct sh_eth_plat_data *pdata;
2938         const char *mac_addr;
2939
2940         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2941         if (!pdata)
2942                 return NULL;
2943
2944         pdata->phy_interface = of_get_phy_mode(np);
2945
2946         mac_addr = of_get_mac_address(np);
2947         if (mac_addr)
2948                 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
2949
2950         pdata->no_ether_link =
2951                 of_property_read_bool(np, "renesas,no-ether-link");
2952         pdata->ether_link_active_low =
2953                 of_property_read_bool(np, "renesas,ether-link-active-low");
2954
2955         return pdata;
2956 }
2957
2958 static const struct of_device_id sh_eth_match_table[] = {
2959         { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
2960         { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
2961         { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
2962         { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
2963         { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
2964         { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data },
2965         { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
2966         { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
2967         { }
2968 };
2969 MODULE_DEVICE_TABLE(of, sh_eth_match_table);
2970 #else
2971 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2972 {
2973         return NULL;
2974 }
2975 #endif
2976
2977 static int sh_eth_drv_probe(struct platform_device *pdev)
2978 {
2979         struct resource *res;
2980         struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
2981         const struct platform_device_id *id = platform_get_device_id(pdev);
2982         struct sh_eth_private *mdp;
2983         struct net_device *ndev;
2984         int ret, devno;
2985
2986         /* get base addr */
2987         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2988
2989         ndev = alloc_etherdev(sizeof(struct sh_eth_private));
2990         if (!ndev)
2991                 return -ENOMEM;
2992
2993         pm_runtime_enable(&pdev->dev);
2994         pm_runtime_get_sync(&pdev->dev);
2995
2996         devno = pdev->id;
2997         if (devno < 0)
2998                 devno = 0;
2999
3000         ret = platform_get_irq(pdev, 0);
3001         if (ret < 0)
3002                 goto out_release;
3003         ndev->irq = ret;
3004
3005         SET_NETDEV_DEV(ndev, &pdev->dev);
3006
3007         mdp = netdev_priv(ndev);
3008         mdp->num_tx_ring = TX_RING_SIZE;
3009         mdp->num_rx_ring = RX_RING_SIZE;
3010         mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3011         if (IS_ERR(mdp->addr)) {
3012                 ret = PTR_ERR(mdp->addr);
3013                 goto out_release;
3014         }
3015
3016         ndev->base_addr = res->start;
3017
3018         spin_lock_init(&mdp->lock);
3019         mdp->pdev = pdev;
3020
3021         if (pdev->dev.of_node)
3022                 pd = sh_eth_parse_dt(&pdev->dev);
3023         if (!pd) {
3024                 dev_err(&pdev->dev, "no platform data\n");
3025                 ret = -EINVAL;
3026                 goto out_release;
3027         }
3028
3029         /* get PHY ID */
3030         mdp->phy_id = pd->phy;
3031         mdp->phy_interface = pd->phy_interface;
3032         mdp->no_ether_link = pd->no_ether_link;
3033         mdp->ether_link_active_low = pd->ether_link_active_low;
3034
3035         /* set cpu data */
3036         if (id)
3037                 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
3038         else
3039                 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev);
3040
3041         mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
3042         if (!mdp->reg_offset) {
3043                 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3044                         mdp->cd->register_type);
3045                 ret = -EINVAL;
3046                 goto out_release;
3047         }
3048         sh_eth_set_default_cpu_data(mdp->cd);
3049
3050         /* set function */
3051         if (mdp->cd->tsu)
3052                 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3053         else
3054                 ndev->netdev_ops = &sh_eth_netdev_ops;
3055         ndev->ethtool_ops = &sh_eth_ethtool_ops;
3056         ndev->watchdog_timeo = TX_TIMEOUT;
3057
3058         /* debug message level */
3059         mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
3060
3061         /* read and set MAC address */
3062         read_mac_address(ndev, pd->mac_addr);
3063         if (!is_valid_ether_addr(ndev->dev_addr)) {
3064                 dev_warn(&pdev->dev,
3065                          "no valid MAC address supplied, using a random one.\n");
3066                 eth_hw_addr_random(ndev);
3067         }
3068
3069         /* ioremap the TSU registers */
3070         if (mdp->cd->tsu) {
3071                 struct resource *rtsu;
3072                 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3073                 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
3074                 if (IS_ERR(mdp->tsu_addr)) {
3075                         ret = PTR_ERR(mdp->tsu_addr);
3076                         goto out_release;
3077                 }
3078                 mdp->port = devno % 2;
3079                 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
3080         }
3081
3082         /* initialize first or needed device */
3083         if (!devno || pd->needs_init) {
3084                 if (mdp->cd->chip_reset)
3085                         mdp->cd->chip_reset(ndev);
3086
3087                 if (mdp->cd->tsu) {
3088                         /* TSU init (Init only)*/
3089                         sh_eth_tsu_init(mdp);
3090                 }
3091         }
3092
3093         if (mdp->cd->rmiimode)
3094                 sh_eth_write(ndev, 0x1, RMIIMODE);
3095
3096         /* MDIO bus init */
3097         ret = sh_mdio_init(mdp, pd);
3098         if (ret) {
3099                 dev_err(&ndev->dev, "failed to initialise MDIO\n");
3100                 goto out_release;
3101         }
3102
3103         netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3104
3105         /* network device register */
3106         ret = register_netdev(ndev);
3107         if (ret)
3108                 goto out_napi_del;
3109
3110         /* print device information */
3111         netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3112                     (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
3113
3114         pm_runtime_put(&pdev->dev);
3115         platform_set_drvdata(pdev, ndev);
3116
3117         return ret;
3118
3119 out_napi_del:
3120         netif_napi_del(&mdp->napi);
3121         sh_mdio_release(mdp);
3122
3123 out_release:
3124         /* net_dev free */
3125         if (ndev)
3126                 free_netdev(ndev);
3127
3128         pm_runtime_put(&pdev->dev);
3129         pm_runtime_disable(&pdev->dev);
3130         return ret;
3131 }
3132
3133 static int sh_eth_drv_remove(struct platform_device *pdev)
3134 {
3135         struct net_device *ndev = platform_get_drvdata(pdev);
3136         struct sh_eth_private *mdp = netdev_priv(ndev);
3137
3138         unregister_netdev(ndev);
3139         netif_napi_del(&mdp->napi);
3140         sh_mdio_release(mdp);
3141         pm_runtime_disable(&pdev->dev);
3142         free_netdev(ndev);
3143
3144         return 0;
3145 }
3146
3147 #ifdef CONFIG_PM
3148 #ifdef CONFIG_PM_SLEEP
3149 static int sh_eth_suspend(struct device *dev)
3150 {
3151         struct net_device *ndev = dev_get_drvdata(dev);
3152         int ret = 0;
3153
3154         if (netif_running(ndev)) {
3155                 netif_device_detach(ndev);
3156                 ret = sh_eth_close(ndev);
3157         }
3158
3159         return ret;
3160 }
3161
3162 static int sh_eth_resume(struct device *dev)
3163 {
3164         struct net_device *ndev = dev_get_drvdata(dev);
3165         int ret = 0;
3166
3167         if (netif_running(ndev)) {
3168                 ret = sh_eth_open(ndev);
3169                 if (ret < 0)
3170                         return ret;
3171                 netif_device_attach(ndev);
3172         }
3173
3174         return ret;
3175 }
3176 #endif
3177
3178 static int sh_eth_runtime_nop(struct device *dev)
3179 {
3180         /* Runtime PM callback shared between ->runtime_suspend()
3181          * and ->runtime_resume(). Simply returns success.
3182          *
3183          * This driver re-initializes all registers after
3184          * pm_runtime_get_sync() anyway so there is no need
3185          * to save and restore registers here.
3186          */
3187         return 0;
3188 }
3189
3190 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
3191         SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
3192         SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
3193 };
3194 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3195 #else
3196 #define SH_ETH_PM_OPS NULL
3197 #endif
3198
3199 static struct platform_device_id sh_eth_id_table[] = {
3200         { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
3201         { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
3202         { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
3203         { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
3204         { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3205         { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
3206         { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
3207         { }
3208 };
3209 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3210
3211 static struct platform_driver sh_eth_driver = {
3212         .probe = sh_eth_drv_probe,
3213         .remove = sh_eth_drv_remove,
3214         .id_table = sh_eth_id_table,
3215         .driver = {
3216                    .name = CARDNAME,
3217                    .pm = SH_ETH_PM_OPS,
3218                    .of_match_table = of_match_ptr(sh_eth_match_table),
3219         },
3220 };
3221
3222 module_platform_driver(sh_eth_driver);
3223
3224 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3225 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3226 MODULE_LICENSE("GPL v2");