drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

   1 /*******************************************************************************
   2   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
   3   ST Ethernet IPs are built around a Synopsys IP Core.
   4
   5         Copyright(C) 2007-2011 STMicroelectronics Ltd
   6
   7   This program is free software; you can redistribute it and/or modify it
   8   under the terms and conditions of the GNU General Public License,
   9   version 2, as published by the Free Software Foundation.
  10
  11   This program is distributed in the hope it will be useful, but WITHOUT
  12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14   more details.
  15
  16   You should have received a copy of the GNU General Public License along with
  17   this program; if not, write to the Free Software Foundation, Inc.,
  18   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19
  20   The full GNU General Public License is included in this distribution in
  21   the file called "COPYING".
  22
  23   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  24
  25   Documentation available at:
  26         http://www.stlinux.com
  27   Support available at:
  28         https://bugzilla.stlinux.com/
  29 *******************************************************************************/
  30
  31 #include <linux/clk.h>
  32 #include <linux/kernel.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/ip.h>
  35 #include <linux/tcp.h>
  36 #include <linux/skbuff.h>
  37 #include <linux/ethtool.h>
  38 #include <linux/if_ether.h>
  39 #include <linux/crc32.h>
  40 #include <linux/mii.h>
  41 #include <linux/if.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/dma-mapping.h>
  44 #include <linux/slab.h>
  45 #include <linux/prefetch.h>
  46 #include <linux/pinctrl/consumer.h>
  47 #ifdef CONFIG_DEBUG_FS
  48 #include <linux/debugfs.h>
  49 #include <linux/seq_file.h>
  50 #endif /* CONFIG_DEBUG_FS */
  51 #include <linux/net_tstamp.h>
  52 #include "stmmac_ptp.h"
  53 #include "stmmac.h"
  54 #include <linux/reset.h>
  55 #include <linux/of_mdio.h>
  56 #include "dwmac1000.h"
  57
  58 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
  59 #define TSO_MAX_BUFF_SIZE       (SZ_16K - 1)
  60
  61 /* Module parameters */
  62 #define TX_TIMEO        5000
  63 static int watchdog = TX_TIMEO;
  64 module_param(watchdog, int, S_IRUGO | S_IWUSR);
  65 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
  66
  67 static int debug = -1;
  68 module_param(debug, int, S_IRUGO | S_IWUSR);
  69 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
  70
  71 static int phyaddr = -1;
  72 module_param(phyaddr, int, S_IRUGO);
  73 MODULE_PARM_DESC(phyaddr, "Physical device address");
  74
  75 #define STMMAC_TX_THRESH        (DMA_TX_SIZE / 4)
  76 #define STMMAC_RX_THRESH        (DMA_RX_SIZE / 4)
  77
  78 static int flow_ctrl = FLOW_OFF;
  79 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
  80 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
  81
  82 static int pause = PAUSE_TIME;
  83 module_param(pause, int, S_IRUGO | S_IWUSR);
  84 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
  85
  86 #define TC_DEFAULT 64
  87 static int tc = TC_DEFAULT;
  88 module_param(tc, int, S_IRUGO | S_IWUSR);
  89 MODULE_PARM_DESC(tc, "DMA threshold control value");
  90
  91 #define DEFAULT_BUFSIZE 1536
  92 static int buf_sz = DEFAULT_BUFSIZE;
  93 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
  94 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
  95
  96 #define STMMAC_RX_COPYBREAK     256
  97
  98 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
  99                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
 100                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
 101
 102 #define STMMAC_DEFAULT_LPI_TIMER        1000
 103 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 104 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
 105 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
 106 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
 107
 108 /* By default the driver will use the ring mode to manage tx and rx descriptors
 109  * but passing this value so user can force to use the chain instead of the ring
 110  */
 111 static unsigned int chain_mode;
 112 module_param(chain_mode, int, S_IRUGO);
 113 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
 114
 115 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
 116
 117 #ifdef CONFIG_DEBUG_FS
 118 static int stmmac_init_fs(struct net_device *dev);
 119 static void stmmac_exit_fs(struct net_device *dev);
 120 #endif
 121
 122 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
 123
 124 /**
 125  * stmmac_verify_args - verify the driver parameters.
 126  * Description: it checks the driver parameters and set a default in case of
 127  * errors.
 128  */
 129 static void stmmac_verify_args(void)
 130 {
 131         if (unlikely(watchdog < 0))
 132                 watchdog = TX_TIMEO;
 133         if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
 134                 buf_sz = DEFAULT_BUFSIZE;
 135         if (unlikely(flow_ctrl > 1))
 136                 flow_ctrl = FLOW_AUTO;
 137         else if (likely(flow_ctrl < 0))
 138                 flow_ctrl = FLOW_OFF;
 139         if (unlikely((pause < 0) || (pause > 0xffff)))
 140                 pause = PAUSE_TIME;
 141         if (eee_timer < 0)
 142                 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 143 }
 144
 145 /**
 146  * stmmac_clk_csr_set - dynamically set the MDC clock
 147  * @priv: driver private structure
 148  * Description: this is to dynamically set the MDC clock according to the csr
 149  * clock input.
 150  * Note:
 151  *      If a specific clk_csr value is passed from the platform
 152  *      this means that the CSR Clock Range selection cannot be
 153  *      changed at run-time and it is fixed (as reported in the driver
 154  *      documentation). Viceversa the driver will try to set the MDC
 155  *      clock dynamically according to the actual clock input.
 156  */
 157 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
 158 {
 159         u32 clk_rate;
 160
 161         clk_rate = clk_get_rate(priv->stmmac_clk);
 162
 163         /* Platform provided default clk_csr would be assumed valid
 164          * for all other cases except for the below mentioned ones.
 165          * For values higher than the IEEE 802.3 specified frequency
 166          * we can not estimate the proper divider as it is not known
 167          * the frequency of clk_csr_i. So we do not change the default
 168          * divider.
 169          */
 170         if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
 171                 if (clk_rate < CSR_F_35M)
 172                         priv->clk_csr = STMMAC_CSR_20_35M;
 173                 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
 174                         priv->clk_csr = STMMAC_CSR_35_60M;
 175                 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
 176                         priv->clk_csr = STMMAC_CSR_60_100M;
 177                 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
 178                         priv->clk_csr = STMMAC_CSR_100_150M;
 179                 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
 180                         priv->clk_csr = STMMAC_CSR_150_250M;
 181                 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
 182                         priv->clk_csr = STMMAC_CSR_250_300M;
 183         }
 184 }
 185
 186 static void print_pkt(unsigned char *buf, int len)
 187 {
 188         pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
 189         print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
 190 }
 191
 192 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
 193 {
 194         unsigned avail;
 195
 196         if (priv->dirty_tx > priv->cur_tx)
 197                 avail = priv->dirty_tx - priv->cur_tx - 1;
 198         else
 199                 avail = DMA_TX_SIZE - priv->cur_tx + priv->dirty_tx - 1;
 200
 201         return avail;
 202 }
 203
 204 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv)
 205 {
 206         unsigned dirty;
 207
 208         if (priv->dirty_rx <= priv->cur_rx)
 209                 dirty = priv->cur_rx - priv->dirty_rx;
 210         else
 211                 dirty = DMA_RX_SIZE - priv->dirty_rx + priv->cur_rx;
 212
 213         return dirty;
 214 }
 215
 216 /**
 217  * stmmac_hw_fix_mac_speed - callback for speed selection
 218  * @priv: driver private structure
 219  * Description: on some platforms (e.g. ST), some HW system configuraton
 220  * registers have to be set according to the link speed negotiated.
 221  */
 222 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
 223 {
 224         struct phy_device *phydev = priv->phydev;
 225
 226         if (likely(priv->plat->fix_mac_speed))
 227                 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed);
 228 }
 229
 230 /**
 231  * stmmac_enable_eee_mode - check and enter in LPI mode
 232  * @priv: driver private structure
 233  * Description: this function is to verify and enter in LPI mode in case of
 234  * EEE.
 235  */
 236 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
 237 {
 238         /* Check and enter in LPI mode */
 239         if ((priv->dirty_tx == priv->cur_tx) &&
 240             (priv->tx_path_in_lpi_mode == false))
 241                 priv->hw->mac->set_eee_mode(priv->hw);
 242 }
 243
 244 /**
 245  * stmmac_disable_eee_mode - disable and exit from LPI mode
 246  * @priv: driver private structure
 247  * Description: this function is to exit and disable EEE in case of
 248  * LPI state is true. This is called by the xmit.
 249  */
 250 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
 251 {
 252         priv->hw->mac->reset_eee_mode(priv->hw);
 253         del_timer_sync(&priv->eee_ctrl_timer);
 254         priv->tx_path_in_lpi_mode = false;
 255 }
 256
 257 /**
 258  * stmmac_eee_ctrl_timer - EEE TX SW timer.
 259  * @arg : data hook
 260  * Description:
 261  *  if there is no data transfer and if we are not in LPI state,
 262  *  then MAC Transmitter can be moved to LPI state.
 263  */
 264 static void stmmac_eee_ctrl_timer(unsigned long arg)
 265 {
 266         struct stmmac_priv *priv = (struct stmmac_priv *)arg;
 267
 268         stmmac_enable_eee_mode(priv);
 269         mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
 270 }
 271
 272 /**
 273  * stmmac_eee_init - init EEE
 274  * @priv: driver private structure
 275  * Description:
 276  *  if the GMAC supports the EEE (from the HW cap reg) and the phy device
 277  *  can also manage EEE, this function enable the LPI state and start related
 278  *  timer.
 279  */
 280 bool stmmac_eee_init(struct stmmac_priv *priv)
 281 {
 282         unsigned long flags;
 283         bool ret = false;
 284
 285         /* Using PCS we cannot dial with the phy registers at this stage
 286          * so we do not support extra feature like EEE.
 287          */
 288         if ((priv->hw->pcs == STMMAC_PCS_RGMII) ||
 289             (priv->hw->pcs == STMMAC_PCS_TBI) ||
 290             (priv->hw->pcs == STMMAC_PCS_RTBI))
 291                 goto out;
 292
 293         /* MAC core supports the EEE feature. */
 294         if (priv->dma_cap.eee) {
 295                 int tx_lpi_timer = priv->tx_lpi_timer;
 296
 297                 /* Check if the PHY supports EEE */
 298                 if (phy_init_eee(priv->phydev, 1)) {
 299                         /* To manage at run-time if the EEE cannot be supported
 300                          * anymore (for example because the lp caps have been
 301                          * changed).
 302                          * In that case the driver disable own timers.
 303                          */
 304                         spin_lock_irqsave(&priv->lock, flags);
 305                         if (priv->eee_active) {
 306                                 pr_debug("stmmac: disable EEE\n");
 307                                 del_timer_sync(&priv->eee_ctrl_timer);
 308                                 priv->hw->mac->set_eee_timer(priv->hw, 0,
 309                                                              tx_lpi_timer);
 310                         }
 311                         priv->eee_active = 0;
 312                         spin_unlock_irqrestore(&priv->lock, flags);
 313                         goto out;
 314                 }
 315                 /* Activate the EEE and start timers */
 316                 spin_lock_irqsave(&priv->lock, flags);
 317                 if (!priv->eee_active) {
 318                         priv->eee_active = 1;
 319                         setup_timer(&priv->eee_ctrl_timer,
 320                                     stmmac_eee_ctrl_timer,
 321                                     (unsigned long)priv);
 322                         mod_timer(&priv->eee_ctrl_timer,
 323                                   STMMAC_LPI_T(eee_timer));
 324
 325                         priv->hw->mac->set_eee_timer(priv->hw,
 326                                                      STMMAC_DEFAULT_LIT_LS,
 327                                                      tx_lpi_timer);
 328                 }
 329                 /* Set HW EEE according to the speed */
 330                 priv->hw->mac->set_eee_pls(priv->hw, priv->phydev->link);
 331
 332                 ret = true;
 333                 spin_unlock_irqrestore(&priv->lock, flags);
 334
 335                 pr_debug("stmmac: Energy-Efficient Ethernet initialized\n");
 336         }
 337 out:
 338         return ret;
 339 }
 340
 341 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
 342  * @priv: driver private structure
 343  * @entry : descriptor index to be used.
 344  * @skb : the socket buffer
 345  * Description :
 346  * This function will read timestamp from the descriptor & pass it to stack.
 347  * and also perform some sanity checks.
 348  */
 349 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
 350                                    unsigned int entry, struct sk_buff *skb)
 351 {
 352         struct skb_shared_hwtstamps shhwtstamp;
 353         u64 ns;
 354         void *desc = NULL;
 355
 356         if (!priv->hwts_tx_en)
 357                 return;
 358
 359         /* exit if skb doesn't support hw tstamp */
 360         if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
 361                 return;
 362
 363         if (priv->adv_ts)
 364                 desc = (priv->dma_etx + entry);
 365         else
 366                 desc = (priv->dma_tx + entry);
 367
 368         /* check tx tstamp status */
 369         if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc))
 370                 return;
 371
 372         /* get the valid tstamp */
 373         ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
 374
 375         memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 376         shhwtstamp.hwtstamp = ns_to_ktime(ns);
 377         /* pass tstamp to stack */
 378         skb_tstamp_tx(skb, &shhwtstamp);
 379
 380         return;
 381 }
 382
 383 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
 384  * @priv: driver private structure
 385  * @entry : descriptor index to be used.
 386  * @skb : the socket buffer
 387  * Description :
 388  * This function will read received packet's timestamp from the descriptor
 389  * and pass it to stack. It also perform some sanity checks.
 390  */
 391 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv,
 392                                    unsigned int entry, struct sk_buff *skb)
 393 {
 394         struct skb_shared_hwtstamps *shhwtstamp = NULL;
 395         u64 ns;
 396         void *desc = NULL;
 397
 398         if (!priv->hwts_rx_en)
 399                 return;
 400
 401         if (priv->adv_ts)
 402                 desc = (priv->dma_erx + entry);
 403         else
 404                 desc = (priv->dma_rx + entry);
 405
 406         /* exit if rx tstamp is not valid */
 407         if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts))
 408                 return;
 409
 410         /* get valid tstamp */
 411         ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
 412         shhwtstamp = skb_hwtstamps(skb);
 413         memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 414         shhwtstamp->hwtstamp = ns_to_ktime(ns);
 415 }
 416
 417 /**
 418  *  stmmac_hwtstamp_ioctl - control hardware timestamping.
 419  *  @dev: device pointer.
 420  *  @ifr: An IOCTL specefic structure, that can contain a pointer to
 421  *  a proprietary structure used to pass information to the driver.
 422  *  Description:
 423  *  This function configures the MAC to enable/disable both outgoing(TX)
 424  *  and incoming(RX) packets time stamping based on user input.
 425  *  Return Value:
 426  *  0 on success and an appropriate -ve integer on failure.
 427  */
 428 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
 429 {
 430         struct stmmac_priv *priv = netdev_priv(dev);
 431         struct hwtstamp_config config;
 432         struct timespec64 now;
 433         u64 temp = 0;
 434         u32 ptp_v2 = 0;
 435         u32 tstamp_all = 0;
 436         u32 ptp_over_ipv4_udp = 0;
 437         u32 ptp_over_ipv6_udp = 0;
 438         u32 ptp_over_ethernet = 0;
 439         u32 snap_type_sel = 0;
 440         u32 ts_master_en = 0;
 441         u32 ts_event_en = 0;
 442         u32 value = 0;
 443         u32 sec_inc;
 444
 445         if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
 446                 netdev_alert(priv->dev, "No support for HW time stamping\n");
 447                 priv->hwts_tx_en = 0;
 448                 priv->hwts_rx_en = 0;
 449
 450                 return -EOPNOTSUPP;
 451         }
 452
 453         if (copy_from_user(&config, ifr->ifr_data,
 454                            sizeof(struct hwtstamp_config)))
 455                 return -EFAULT;
 456
 457         pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
 458                  __func__, config.flags, config.tx_type, config.rx_filter);
 459
 460         /* reserved for future extensions */
 461         if (config.flags)
 462                 return -EINVAL;
 463
 464         if (config.tx_type != HWTSTAMP_TX_OFF &&
 465             config.tx_type != HWTSTAMP_TX_ON)
 466                 return -ERANGE;
 467
 468         if (priv->adv_ts) {
 469                 switch (config.rx_filter) {
 470                 case HWTSTAMP_FILTER_NONE:
 471                         /* time stamp no incoming packet at all */
 472                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 473                         break;
 474
 475                 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 476                         /* PTP v1, UDP, any kind of event packet */
 477                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 478                         /* take time stamp for all event messages */
 479                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 480
 481                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 482                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 483                         break;
 484
 485                 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 486                         /* PTP v1, UDP, Sync packet */
 487                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
 488                         /* take time stamp for SYNC messages only */
 489                         ts_event_en = PTP_TCR_TSEVNTENA;
 490
 491                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 492                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 493                         break;
 494
 495                 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 496                         /* PTP v1, UDP, Delay_req packet */
 497                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
 498                         /* take time stamp for Delay_Req messages only */
 499                         ts_master_en = PTP_TCR_TSMSTRENA;
 500                         ts_event_en = PTP_TCR_TSEVNTENA;
 501
 502                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 503                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 504                         break;
 505
 506                 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 507                         /* PTP v2, UDP, any kind of event packet */
 508                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
 509                         ptp_v2 = PTP_TCR_TSVER2ENA;
 510                         /* take time stamp for all event messages */
 511                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 512
 513                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 514                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 515                         break;
 516
 517                 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 518                         /* PTP v2, UDP, Sync packet */
 519                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
 520                         ptp_v2 = PTP_TCR_TSVER2ENA;
 521                         /* take time stamp for SYNC messages only */
 522                         ts_event_en = PTP_TCR_TSEVNTENA;
 523
 524                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 525                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 526                         break;
 527
 528                 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 529                         /* PTP v2, UDP, Delay_req packet */
 530                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
 531                         ptp_v2 = PTP_TCR_TSVER2ENA;
 532                         /* take time stamp for Delay_Req messages only */
 533                         ts_master_en = PTP_TCR_TSMSTRENA;
 534                         ts_event_en = PTP_TCR_TSEVNTENA;
 535
 536                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 537                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 538                         break;
 539
 540                 case HWTSTAMP_FILTER_PTP_V2_EVENT:
 541                         /* PTP v2/802.AS1 any layer, any kind of event packet */
 542                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
 543                         ptp_v2 = PTP_TCR_TSVER2ENA;
 544                         /* take time stamp for all event messages */
 545                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 546
 547                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 548                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 549                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 550                         break;
 551
 552                 case HWTSTAMP_FILTER_PTP_V2_SYNC:
 553                         /* PTP v2/802.AS1, any layer, Sync packet */
 554                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
 555                         ptp_v2 = PTP_TCR_TSVER2ENA;
 556                         /* take time stamp for SYNC messages only */
 557                         ts_event_en = PTP_TCR_TSEVNTENA;
 558
 559                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 560                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 561                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 562                         break;
 563
 564                 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 565                         /* PTP v2/802.AS1, any layer, Delay_req packet */
 566                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
 567                         ptp_v2 = PTP_TCR_TSVER2ENA;
 568                         /* take time stamp for Delay_Req messages only */
 569                         ts_master_en = PTP_TCR_TSMSTRENA;
 570                         ts_event_en = PTP_TCR_TSEVNTENA;
 571
 572                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 573                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 574                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 575                         break;
 576
 577                 case HWTSTAMP_FILTER_ALL:
 578                         /* time stamp any incoming packet */
 579                         config.rx_filter = HWTSTAMP_FILTER_ALL;
 580                         tstamp_all = PTP_TCR_TSENALL;
 581                         break;
 582
 583                 default:
 584                         return -ERANGE;
 585                 }
 586         } else {
 587                 switch (config.rx_filter) {
 588                 case HWTSTAMP_FILTER_NONE:
 589                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 590                         break;
 591                 default:
 592                         /* PTP v1, UDP, any kind of event packet */
 593                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 594                         break;
 595                 }
 596         }
 597         priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
 598         priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
 599
 600         if (!priv->hwts_tx_en && !priv->hwts_rx_en)
 601                 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0);
 602         else {
 603                 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
 604                          tstamp_all | ptp_v2 | ptp_over_ethernet |
 605                          ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
 606                          ts_master_en | snap_type_sel);
 607                 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value);
 608
 609                 /* program Sub Second Increment reg */
 610                 sec_inc = priv->hw->ptp->config_sub_second_increment(
 611                         priv->ioaddr, priv->clk_ptp_rate);
 612                 temp = div_u64(1000000000ULL, sec_inc);
 613
 614                 /* calculate default added value:
 615                  * formula is :
 616                  * addend = (2^32)/freq_div_ratio;
 617                  * where, freq_div_ratio = 1e9ns/sec_inc
 618                  */
 619                 temp = (u64)(temp << 32);
 620                 priv->default_addend = div_u64(temp, priv->clk_ptp_rate);
 621                 priv->hw->ptp->config_addend(priv->ioaddr,
 622                                              priv->default_addend);
 623
 624                 /* initialize system time */
 625                 ktime_get_real_ts64(&now);
 626
 627                 /* lower 32 bits of tv_sec are safe until y2106 */
 628                 priv->hw->ptp->init_systime(priv->ioaddr, (u32)now.tv_sec,
 629                                             now.tv_nsec);
 630         }
 631
 632         return copy_to_user(ifr->ifr_data, &config,
 633                             sizeof(struct hwtstamp_config)) ? -EFAULT : 0;
 634 }
 635
 636 /**
 637  * stmmac_init_ptp - init PTP
 638  * @priv: driver private structure
 639  * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
 640  * This is done by looking at the HW cap. register.
 641  * This function also registers the ptp driver.
 642  */
 643 static int stmmac_init_ptp(struct stmmac_priv *priv)
 644 {
 645         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
 646                 return -EOPNOTSUPP;
 647
 648         /* Fall-back to main clock in case of no PTP ref is passed */
 649         priv->clk_ptp_ref = devm_clk_get(priv->device, "clk_ptp_ref");
 650         if (IS_ERR(priv->clk_ptp_ref)) {
 651                 priv->clk_ptp_rate = clk_get_rate(priv->stmmac_clk);
 652                 priv->clk_ptp_ref = NULL;
 653                 netdev_dbg(priv->dev, "PTP uses main clock\n");
 654         } else {
 655                 clk_prepare_enable(priv->clk_ptp_ref);
 656                 priv->clk_ptp_rate = clk_get_rate(priv->clk_ptp_ref);
 657                 netdev_dbg(priv->dev, "PTP rate %d\n", priv->clk_ptp_rate);
 658         }
 659
 660         priv->adv_ts = 0;
 661         /* Check if adv_ts can be enabled for dwmac 4.x core */
 662         if (priv->plat->has_gmac4 && priv->dma_cap.atime_stamp)
 663                 priv->adv_ts = 1;
 664         /* Dwmac 3.x core with extend_desc can support adv_ts */
 665         else if (priv->extend_desc && priv->dma_cap.atime_stamp)
 666                 priv->adv_ts = 1;
 667
 668         if (priv->dma_cap.time_stamp)
 669                 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n");
 670
 671         if (priv->adv_ts)
 672                 netdev_info(priv->dev,
 673                             "IEEE 1588-2008 Advanced Timestamp supported\n");
 674
 675         priv->hw->ptp = &stmmac_ptp;
 676         priv->hwts_tx_en = 0;
 677         priv->hwts_rx_en = 0;
 678
 679         stmmac_ptp_register(priv);
 680
 681         return 0;
 682 }
 683
 684 static void stmmac_release_ptp(struct stmmac_priv *priv)
 685 {
 686         if (priv->clk_ptp_ref)
 687                 clk_disable_unprepare(priv->clk_ptp_ref);
 688         stmmac_ptp_unregister(priv);
 689 }
 690
 691 /**
 692  * stmmac_adjust_link - adjusts the link parameters
 693  * @dev: net device structure
 694  * Description: this is the helper called by the physical abstraction layer
 695  * drivers to communicate the phy link status. According the speed and duplex
 696  * this driver can invoke registered glue-logic as well.
 697  * It also invoke the eee initialization because it could happen when switch
 698  * on different networks (that are eee capable).
 699  */
 700 static void stmmac_adjust_link(struct net_device *dev)
 701 {
 702         struct stmmac_priv *priv = netdev_priv(dev);
 703         struct phy_device *phydev = priv->phydev;
 704         unsigned long flags;
 705         int new_state = 0;
 706         unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
 707
 708         if (phydev == NULL)
 709                 return;
 710
 711         spin_lock_irqsave(&priv->lock, flags);
 712
 713         if (phydev->link) {
 714                 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
 715
 716                 /* Now we make sure that we can be in full duplex mode.
 717                  * If not, we operate in half-duplex mode. */
 718                 if (phydev->duplex != priv->oldduplex) {
 719                         new_state = 1;
 720                         if (!(phydev->duplex))
 721                                 ctrl &= ~priv->hw->link.duplex;
 722                         else
 723                                 ctrl |= priv->hw->link.duplex;
 724                         priv->oldduplex = phydev->duplex;
 725                 }
 726                 /* Flow Control operation */
 727                 if (phydev->pause)
 728                         priv->hw->mac->flow_ctrl(priv->hw, phydev->duplex,
 729                                                  fc, pause_time);
 730
 731                 if (phydev->speed != priv->speed) {
 732                         new_state = 1;
 733                         switch (phydev->speed) {
 734                         case 1000:
 735                                 if (likely((priv->plat->has_gmac) ||
 736                                            (priv->plat->has_gmac4)))
 737                                         ctrl &= ~priv->hw->link.port;
 738                                 stmmac_hw_fix_mac_speed(priv);
 739                                 break;
 740                         case 100:
 741                         case 10:
 742                                 if (likely((priv->plat->has_gmac) ||
 743                                            (priv->plat->has_gmac4))) {
 744                                         ctrl |= priv->hw->link.port;
 745                                         if (phydev->speed == SPEED_100) {
 746                                                 ctrl |= priv->hw->link.speed;
 747                                         } else {
 748                                                 ctrl &= ~(priv->hw->link.speed);
 749                                         }
 750                                 } else {
 751                                         ctrl &= ~priv->hw->link.port;
 752                                 }
 753                                 stmmac_hw_fix_mac_speed(priv);
 754                                 break;
 755                         default:
 756                                 if (netif_msg_link(priv))
 757                                         pr_warn("%s: Speed (%d) not 10/100\n",
 758                                                 dev->name, phydev->speed);
 759                                 break;
 760                         }
 761
 762                         priv->speed = phydev->speed;
 763                 }
 764
 765                 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
 766
 767                 if (!priv->oldlink) {
 768                         new_state = 1;
 769                         priv->oldlink = 1;
 770                 }
 771         } else if (priv->oldlink) {
 772                 new_state = 1;
 773                 priv->oldlink = 0;
 774                 priv->speed = 0;
 775                 priv->oldduplex = -1;
 776         }
 777
 778         if (new_state && netif_msg_link(priv))
 779                 phy_print_status(phydev);
 780
 781         spin_unlock_irqrestore(&priv->lock, flags);
 782
 783         if (phydev->is_pseudo_fixed_link)
 784                 /* Stop PHY layer to call the hook to adjust the link in case
 785                  * of a switch is attached to the stmmac driver.
 786                  */
 787                 phydev->irq = PHY_IGNORE_INTERRUPT;
 788         else
 789                 /* At this stage, init the EEE if supported.
 790                  * Never called in case of fixed_link.
 791                  */
 792                 priv->eee_enabled = stmmac_eee_init(priv);
 793 }
 794
 795 /**
 796  * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
 797  * @priv: driver private structure
 798  * Description: this is to verify if the HW supports the PCS.
 799  * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
 800  * configured for the TBI, RTBI, or SGMII PHY interface.
 801  */
 802 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
 803 {
 804         int interface = priv->plat->interface;
 805
 806         if (priv->dma_cap.pcs) {
 807                 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
 808                     (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
 809                     (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
 810                     (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
 811                         pr_debug("STMMAC: PCS RGMII support enable\n");
 812                         priv->hw->pcs = STMMAC_PCS_RGMII;
 813                 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
 814                         pr_debug("STMMAC: PCS SGMII support enable\n");
 815                         priv->hw->pcs = STMMAC_PCS_SGMII;
 816                 }
 817         }
 818 }
 819
 820 /**
 821  * stmmac_init_phy - PHY initialization
 822  * @dev: net device structure
 823  * Description: it initializes the driver's PHY state, and attaches the PHY
 824  * to the mac driver.
 825  *  Return value:
 826  *  0 on success
 827  */
 828 static int stmmac_init_phy(struct net_device *dev)
 829 {
 830         struct stmmac_priv *priv = netdev_priv(dev);
 831         struct phy_device *phydev;
 832         char phy_id_fmt[MII_BUS_ID_SIZE + 3];
 833         char bus_id[MII_BUS_ID_SIZE];
 834         int interface = priv->plat->interface;
 835         int max_speed = priv->plat->max_speed;
 836         priv->oldlink = 0;
 837         priv->speed = 0;
 838         priv->oldduplex = -1;
 839
 840         if (priv->plat->phy_node) {
 841                 phydev = of_phy_connect(dev, priv->plat->phy_node,
 842                                         &stmmac_adjust_link, 0, interface);
 843         } else {
 844                 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
 845                          priv->plat->bus_id);
 846
 847                 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
 848                          priv->plat->phy_addr);
 849                 pr_debug("stmmac_init_phy:  trying to attach to %s\n",
 850                          phy_id_fmt);
 851
 852                 phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link,
 853                                      interface);
 854         }
 855
 856         if (IS_ERR_OR_NULL(phydev)) {
 857                 pr_err("%s: Could not attach to PHY\n", dev->name);
 858                 if (!phydev)
 859                         return -ENODEV;
 860
 861                 return PTR_ERR(phydev);
 862         }
 863
 864         /* Stop Advertising 1000BASE Capability if interface is not GMII */
 865         if ((interface == PHY_INTERFACE_MODE_MII) ||
 866             (interface == PHY_INTERFACE_MODE_RMII) ||
 867                 (max_speed < 1000 && max_speed > 0))
 868                 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
 869                                          SUPPORTED_1000baseT_Full);
 870
 871         /*
 872          * Broken HW is sometimes missing the pull-up resistor on the
 873          * MDIO line, which results in reads to non-existent devices returning
 874          * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
 875          * device as well.
 876          * Note: phydev->phy_id is the result of reading the UID PHY registers.
 877          */
 878         if (!priv->plat->phy_node && phydev->phy_id == 0) {
 879                 phy_disconnect(phydev);
 880                 return -ENODEV;
 881         }
 882
 883         pr_debug("stmmac_init_phy:  %s: attached to PHY (UID 0x%x)"
 884                  " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
 885
 886         priv->phydev = phydev;
 887
 888         return 0;
 889 }
 890
 891 static void stmmac_display_rings(struct stmmac_priv *priv)
 892 {
 893         void *head_rx, *head_tx;
 894
 895         if (priv->extend_desc) {
 896                 head_rx = (void *)priv->dma_erx;
 897                 head_tx = (void *)priv->dma_etx;
 898         } else {
 899                 head_rx = (void *)priv->dma_rx;
 900                 head_tx = (void *)priv->dma_tx;
 901         }
 902
 903         /* Display Rx ring */
 904         priv->hw->desc->display_ring(head_rx, DMA_RX_SIZE, true);
 905         /* Display Tx ring */
 906         priv->hw->desc->display_ring(head_tx, DMA_TX_SIZE, false);
 907 }
 908
 909 static int stmmac_set_bfsize(int mtu, int bufsize)
 910 {
 911         int ret = bufsize;
 912
 913         if (mtu >= BUF_SIZE_4KiB)
 914                 ret = BUF_SIZE_8KiB;
 915         else if (mtu >= BUF_SIZE_2KiB)
 916                 ret = BUF_SIZE_4KiB;
 917         else if (mtu > DEFAULT_BUFSIZE)
 918                 ret = BUF_SIZE_2KiB;
 919         else
 920                 ret = DEFAULT_BUFSIZE;
 921
 922         return ret;
 923 }
 924
 925 /**
 926  * stmmac_clear_descriptors - clear descriptors
 927  * @priv: driver private structure
 928  * Description: this function is called to clear the tx and rx descriptors
 929  * in case of both basic and extended descriptors are used.
 930  */
 931 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
 932 {
 933         int i;
 934
 935         /* Clear the Rx/Tx descriptors */
 936         for (i = 0; i < DMA_RX_SIZE; i++)
 937                 if (priv->extend_desc)
 938                         priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic,
 939                                                      priv->use_riwt, priv->mode,
 940                                                      (i == DMA_RX_SIZE - 1));
 941                 else
 942                         priv->hw->desc->init_rx_desc(&priv->dma_rx[i],
 943                                                      priv->use_riwt, priv->mode,
 944                                                      (i == DMA_RX_SIZE - 1));
 945         for (i = 0; i < DMA_TX_SIZE; i++)
 946                 if (priv->extend_desc)
 947                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
 948                                                      priv->mode,
 949                                                      (i == DMA_TX_SIZE - 1));
 950                 else
 951                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
 952                                                      priv->mode,
 953                                                      (i == DMA_TX_SIZE - 1));
 954 }
 955
 956 /**
 957  * stmmac_init_rx_buffers - init the RX descriptor buffer.
 958  * @priv: driver private structure
 959  * @p: descriptor pointer
 960  * @i: descriptor index
 961  * @flags: gfp flag.
 962  * Description: this function is called to allocate a receive buffer, perform
 963  * the DMA mapping and init the descriptor.
 964  */
 965 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
 966                                   int i, gfp_t flags)
 967 {
 968         struct sk_buff *skb;
 969
 970         skb = __netdev_alloc_skb_ip_align(priv->dev, priv->dma_buf_sz, flags);
 971         if (!skb) {
 972                 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
 973                 return -ENOMEM;
 974         }
 975         priv->rx_skbuff[i] = skb;
 976         priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
 977                                                 priv->dma_buf_sz,
 978                                                 DMA_FROM_DEVICE);
 979         if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) {
 980                 pr_err("%s: DMA mapping error\n", __func__);
 981                 dev_kfree_skb_any(skb);
 982                 return -EINVAL;
 983         }
 984
 985         if (priv->synopsys_id >= DWMAC_CORE_4_00)
 986                 p->des0 = priv->rx_skbuff_dma[i];
 987         else
 988                 p->des2 = priv->rx_skbuff_dma[i];
 989
 990         if ((priv->hw->mode->init_desc3) &&
 991             (priv->dma_buf_sz == BUF_SIZE_16KiB))
 992                 priv->hw->mode->init_desc3(p);
 993
 994         return 0;
 995 }
 996
 997 static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i)
 998 {
 999         if (priv->rx_skbuff[i]) {
1000                 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
1001                                  priv->dma_buf_sz, DMA_FROM_DEVICE);
1002                 dev_kfree_skb_any(priv->rx_skbuff[i]);
1003         }
1004         priv->rx_skbuff[i] = NULL;
1005 }
1006
1007 /**
1008  * init_dma_desc_rings - init the RX/TX descriptor rings
1009  * @dev: net device structure
1010  * @flags: gfp flag.
1011  * Description: this function initializes the DMA RX/TX descriptors
1012  * and allocates the socket buffers. It suppors the chained and ring
1013  * modes.
1014  */
1015 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1016 {
1017         int i;
1018         struct stmmac_priv *priv = netdev_priv(dev);
1019         unsigned int bfsize = 0;
1020         int ret = -ENOMEM;
1021
1022         if (priv->hw->mode->set_16kib_bfsize)
1023                 bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu);
1024
1025         if (bfsize < BUF_SIZE_16KiB)
1026                 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1027
1028         priv->dma_buf_sz = bfsize;
1029
1030         if (netif_msg_probe(priv)) {
1031                 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__,
1032                          (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy);
1033
1034                 /* RX INITIALIZATION */
1035                 pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n");
1036         }
1037         for (i = 0; i < DMA_RX_SIZE; i++) {
1038                 struct dma_desc *p;
1039                 if (priv->extend_desc)
1040                         p = &((priv->dma_erx + i)->basic);
1041                 else
1042                         p = priv->dma_rx + i;
1043
1044                 ret = stmmac_init_rx_buffers(priv, p, i, flags);
1045                 if (ret)
1046                         goto err_init_rx_buffers;
1047
1048                 if (netif_msg_probe(priv))
1049                         pr_debug("[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
1050                                  priv->rx_skbuff[i]->data,
1051                                  (unsigned int)priv->rx_skbuff_dma[i]);
1052         }
1053         priv->cur_rx = 0;
1054         priv->dirty_rx = (unsigned int)(i - DMA_RX_SIZE);
1055         buf_sz = bfsize;
1056
1057         /* Setup the chained descriptor addresses */
1058         if (priv->mode == STMMAC_CHAIN_MODE) {
1059                 if (priv->extend_desc) {
1060                         priv->hw->mode->init(priv->dma_erx, priv->dma_rx_phy,
1061                                              DMA_RX_SIZE, 1);
1062                         priv->hw->mode->init(priv->dma_etx, priv->dma_tx_phy,
1063                                              DMA_TX_SIZE, 1);
1064                 } else {
1065                         priv->hw->mode->init(priv->dma_rx, priv->dma_rx_phy,
1066                                              DMA_RX_SIZE, 0);
1067                         priv->hw->mode->init(priv->dma_tx, priv->dma_tx_phy,
1068                                              DMA_TX_SIZE, 0);
1069                 }
1070         }
1071
1072         /* TX INITIALIZATION */
1073         for (i = 0; i < DMA_TX_SIZE; i++) {
1074                 struct dma_desc *p;
1075                 if (priv->extend_desc)
1076                         p = &((priv->dma_etx + i)->basic);
1077                 else
1078                         p = priv->dma_tx + i;
1079
1080                 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
1081                         p->des0 = 0;
1082                         p->des1 = 0;
1083                         p->des2 = 0;
1084                         p->des3 = 0;
1085                 } else {
1086                         p->des2 = 0;
1087                 }
1088
1089                 priv->tx_skbuff_dma[i].buf = 0;
1090                 priv->tx_skbuff_dma[i].map_as_page = false;
1091                 priv->tx_skbuff_dma[i].len = 0;
1092                 priv->tx_skbuff_dma[i].last_segment = false;
1093                 priv->tx_skbuff[i] = NULL;
1094         }
1095
1096         priv->dirty_tx = 0;
1097         priv->cur_tx = 0;
1098         netdev_reset_queue(priv->dev);
1099
1100         stmmac_clear_descriptors(priv);
1101
1102         if (netif_msg_hw(priv))
1103                 stmmac_display_rings(priv);
1104
1105         return 0;
1106 err_init_rx_buffers:
1107         while (--i >= 0)
1108                 stmmac_free_rx_buffers(priv, i);
1109         return ret;
1110 }
1111
1112 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
1113 {
1114         int i;
1115
1116         for (i = 0; i < DMA_RX_SIZE; i++)
1117                 stmmac_free_rx_buffers(priv, i);
1118 }
1119
1120 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
1121 {
1122         int i;
1123
1124         for (i = 0; i < DMA_TX_SIZE; i++) {
1125                 struct dma_desc *p;
1126
1127                 if (priv->extend_desc)
1128                         p = &((priv->dma_etx + i)->basic);
1129                 else
1130                         p = priv->dma_tx + i;
1131
1132                 if (priv->tx_skbuff_dma[i].buf) {
1133                         if (priv->tx_skbuff_dma[i].map_as_page)
1134                                 dma_unmap_page(priv->device,
1135                                                priv->tx_skbuff_dma[i].buf,
1136                                                priv->tx_skbuff_dma[i].len,
1137                                                DMA_TO_DEVICE);
1138                         else
1139                                 dma_unmap_single(priv->device,
1140                                                  priv->tx_skbuff_dma[i].buf,
1141                                                  priv->tx_skbuff_dma[i].len,
1142                                                  DMA_TO_DEVICE);
1143                 }
1144
1145                 if (priv->tx_skbuff[i] != NULL) {
1146                         dev_kfree_skb_any(priv->tx_skbuff[i]);
1147                         priv->tx_skbuff[i] = NULL;
1148                         priv->tx_skbuff_dma[i].buf = 0;
1149                         priv->tx_skbuff_dma[i].map_as_page = false;
1150                 }
1151         }
1152 }
1153
1154 /**
1155  * alloc_dma_desc_resources - alloc TX/RX resources.
1156  * @priv: private structure
1157  * Description: according to which descriptor can be used (extend or basic)
1158  * this function allocates the resources for TX and RX paths. In case of
1159  * reception, for example, it pre-allocated the RX socket buffer in order to
1160  * allow zero-copy mechanism.
1161  */
1162 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1163 {
1164         int ret = -ENOMEM;
1165
1166         priv->rx_skbuff_dma = kmalloc_array(DMA_RX_SIZE, sizeof(dma_addr_t),
1167                                             GFP_KERNEL);
1168         if (!priv->rx_skbuff_dma)
1169                 return -ENOMEM;
1170
1171         priv->rx_skbuff = kmalloc_array(DMA_RX_SIZE, sizeof(struct sk_buff *),
1172                                         GFP_KERNEL);
1173         if (!priv->rx_skbuff)
1174                 goto err_rx_skbuff;
1175
1176         priv->tx_skbuff_dma = kmalloc_array(DMA_TX_SIZE,
1177                                             sizeof(*priv->tx_skbuff_dma),
1178                                             GFP_KERNEL);
1179         if (!priv->tx_skbuff_dma)
1180                 goto err_tx_skbuff_dma;
1181
1182         priv->tx_skbuff = kmalloc_array(DMA_TX_SIZE, sizeof(struct sk_buff *),
1183                                         GFP_KERNEL);
1184         if (!priv->tx_skbuff)
1185                 goto err_tx_skbuff;
1186
1187         if (priv->extend_desc) {
1188                 priv->dma_erx = dma_zalloc_coherent(priv->device, DMA_RX_SIZE *
1189                                                     sizeof(struct
1190                                                            dma_extended_desc),
1191                                                     &priv->dma_rx_phy,
1192                                                     GFP_KERNEL);
1193                 if (!priv->dma_erx)
1194                         goto err_dma;
1195
1196                 priv->dma_etx = dma_zalloc_coherent(priv->device, DMA_TX_SIZE *
1197                                                     sizeof(struct
1198                                                            dma_extended_desc),
1199                                                     &priv->dma_tx_phy,
1200                                                     GFP_KERNEL);
1201                 if (!priv->dma_etx) {
1202                         dma_free_coherent(priv->device, DMA_RX_SIZE *
1203                                           sizeof(struct dma_extended_desc),
1204                                           priv->dma_erx, priv->dma_rx_phy);
1205                         goto err_dma;
1206                 }
1207         } else {
1208                 priv->dma_rx = dma_zalloc_coherent(priv->device, DMA_RX_SIZE *
1209                                                    sizeof(struct dma_desc),
1210                                                    &priv->dma_rx_phy,
1211                                                    GFP_KERNEL);
1212                 if (!priv->dma_rx)
1213                         goto err_dma;
1214
1215                 priv->dma_tx = dma_zalloc_coherent(priv->device, DMA_TX_SIZE *
1216                                                    sizeof(struct dma_desc),
1217                                                    &priv->dma_tx_phy,
1218                                                    GFP_KERNEL);
1219                 if (!priv->dma_tx) {
1220                         dma_free_coherent(priv->device, DMA_RX_SIZE *
1221                                           sizeof(struct dma_desc),
1222                                           priv->dma_rx, priv->dma_rx_phy);
1223                         goto err_dma;
1224                 }
1225         }
1226
1227         return 0;
1228
1229 err_dma:
1230         kfree(priv->tx_skbuff);
1231 err_tx_skbuff:
1232         kfree(priv->tx_skbuff_dma);
1233 err_tx_skbuff_dma:
1234         kfree(priv->rx_skbuff);
1235 err_rx_skbuff:
1236         kfree(priv->rx_skbuff_dma);
1237         return ret;
1238 }
1239
1240 static void free_dma_desc_resources(struct stmmac_priv *priv)
1241 {
1242         /* Release the DMA TX/RX socket buffers */
1243         dma_free_rx_skbufs(priv);
1244         dma_free_tx_skbufs(priv);
1245
1246         /* Free DMA regions of consistent memory previously allocated */
1247         if (!priv->extend_desc) {
1248                 dma_free_coherent(priv->device,
1249                                   DMA_TX_SIZE * sizeof(struct dma_desc),
1250                                   priv->dma_tx, priv->dma_tx_phy);
1251                 dma_free_coherent(priv->device,
1252                                   DMA_RX_SIZE * sizeof(struct dma_desc),
1253                                   priv->dma_rx, priv->dma_rx_phy);
1254         } else {
1255                 dma_free_coherent(priv->device, DMA_TX_SIZE *
1256                                   sizeof(struct dma_extended_desc),
1257                                   priv->dma_etx, priv->dma_tx_phy);
1258                 dma_free_coherent(priv->device, DMA_RX_SIZE *
1259                                   sizeof(struct dma_extended_desc),
1260                                   priv->dma_erx, priv->dma_rx_phy);
1261         }
1262         kfree(priv->rx_skbuff_dma);
1263         kfree(priv->rx_skbuff);
1264         kfree(priv->tx_skbuff_dma);
1265         kfree(priv->tx_skbuff);
1266 }
1267
1268 /**
1269  *  stmmac_dma_operation_mode - HW DMA operation mode
1270  *  @priv: driver private structure
1271  *  Description: it is used for configuring the DMA operation mode register in
1272  *  order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1273  */
1274 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1275 {
1276         int rxfifosz = priv->plat->rx_fifo_size;
1277
1278         if (priv->plat->force_thresh_dma_mode)
1279                 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc, rxfifosz);
1280         else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1281                 /*
1282                  * In case of GMAC, SF mode can be enabled
1283                  * to perform the TX COE in HW. This depends on:
1284                  * 1) TX COE if actually supported
1285                  * 2) There is no bugged Jumbo frame support
1286                  *    that needs to not insert csum in the TDES.
1287                  */
1288                 priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE,
1289                                         rxfifosz);
1290                 priv->xstats.threshold = SF_DMA_MODE;
1291         } else
1292                 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE,
1293                                         rxfifosz);
1294 }
1295
1296 /**
1297  * stmmac_tx_clean - to manage the transmission completion
1298  * @priv: driver private structure
1299  * Description: it reclaims the transmit resources after transmission completes.
1300  */
1301 static void stmmac_tx_clean(struct stmmac_priv *priv)
1302 {
1303         unsigned int bytes_compl = 0, pkts_compl = 0;
1304         unsigned int entry = priv->dirty_tx;
1305
1306         spin_lock(&priv->tx_lock);
1307
1308         priv->xstats.tx_clean++;
1309
1310         while (entry != priv->cur_tx) {
1311                 struct sk_buff *skb = priv->tx_skbuff[entry];
1312                 struct dma_desc *p;
1313                 int status;
1314
1315                 if (priv->extend_desc)
1316                         p = (struct dma_desc *)(priv->dma_etx + entry);
1317                 else
1318                         p = priv->dma_tx + entry;
1319
1320                 status = priv->hw->desc->tx_status(&priv->dev->stats,
1321                                                       &priv->xstats, p,
1322                                                       priv->ioaddr);
1323                 /* Check if the descriptor is owned by the DMA */
1324                 if (unlikely(status & tx_dma_own))
1325                         break;
1326
1327                 /* Just consider the last segment and ...*/
1328                 if (likely(!(status & tx_not_ls))) {
1329                         /* ... verify the status error condition */
1330                         if (unlikely(status & tx_err)) {
1331                                 priv->dev->stats.tx_errors++;
1332                         } else {
1333                                 priv->dev->stats.tx_packets++;
1334                                 priv->xstats.tx_pkt_n++;
1335                         }
1336                         stmmac_get_tx_hwtstamp(priv, entry, skb);
1337                 }
1338
1339                 if (likely(priv->tx_skbuff_dma[entry].buf)) {
1340                         if (priv->tx_skbuff_dma[entry].map_as_page)
1341                                 dma_unmap_page(priv->device,
1342                                                priv->tx_skbuff_dma[entry].buf,
1343                                                priv->tx_skbuff_dma[entry].len,
1344                                                DMA_TO_DEVICE);
1345                         else
1346                                 dma_unmap_single(priv->device,
1347                                                  priv->tx_skbuff_dma[entry].buf,
1348                                                  priv->tx_skbuff_dma[entry].len,
1349                                                  DMA_TO_DEVICE);
1350                         priv->tx_skbuff_dma[entry].buf = 0;
1351                         priv->tx_skbuff_dma[entry].len = 0;
1352                         priv->tx_skbuff_dma[entry].map_as_page = false;
1353                 }
1354
1355                 if (priv->hw->mode->clean_desc3)
1356                         priv->hw->mode->clean_desc3(priv, p);
1357
1358                 priv->tx_skbuff_dma[entry].last_segment = false;
1359                 priv->tx_skbuff_dma[entry].is_jumbo = false;
1360
1361                 if (likely(skb != NULL)) {
1362                         pkts_compl++;
1363                         bytes_compl += skb->len;
1364                         dev_consume_skb_any(skb);
1365                         priv->tx_skbuff[entry] = NULL;
1366                 }
1367
1368                 priv->hw->desc->release_tx_desc(p, priv->mode);
1369
1370                 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
1371         }
1372         priv->dirty_tx = entry;
1373
1374         netdev_completed_queue(priv->dev, pkts_compl, bytes_compl);
1375
1376         if (unlikely(netif_queue_stopped(priv->dev) &&
1377                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH)) {
1378                 netif_tx_lock(priv->dev);
1379                 if (netif_queue_stopped(priv->dev) &&
1380                     stmmac_tx_avail(priv) > STMMAC_TX_THRESH) {
1381                         if (netif_msg_tx_done(priv))
1382                                 pr_debug("%s: restart transmit\n", __func__);
1383                         netif_wake_queue(priv->dev);
1384                 }
1385                 netif_tx_unlock(priv->dev);
1386         }
1387
1388         if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1389                 stmmac_enable_eee_mode(priv);
1390                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1391         }
1392         spin_unlock(&priv->tx_lock);
1393 }
1394
1395 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv)
1396 {
1397         priv->hw->dma->enable_dma_irq(priv->ioaddr);
1398 }
1399
1400 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv)
1401 {
1402         priv->hw->dma->disable_dma_irq(priv->ioaddr);
1403 }
1404
1405 /**
1406  * stmmac_tx_err - to manage the tx error
1407  * @priv: driver private structure
1408  * Description: it cleans the descriptors and restarts the transmission
1409  * in case of transmission errors.
1410  */
1411 static void stmmac_tx_err(struct stmmac_priv *priv)
1412 {
1413         int i;
1414         netif_stop_queue(priv->dev);
1415
1416         priv->hw->dma->stop_tx(priv->ioaddr);
1417         dma_free_tx_skbufs(priv);
1418         for (i = 0; i < DMA_TX_SIZE; i++)
1419                 if (priv->extend_desc)
1420                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
1421                                                      priv->mode,
1422                                                      (i == DMA_TX_SIZE - 1));
1423                 else
1424                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
1425                                                      priv->mode,
1426                                                      (i == DMA_TX_SIZE - 1));
1427         priv->dirty_tx = 0;
1428         priv->cur_tx = 0;
1429         netdev_reset_queue(priv->dev);
1430         priv->hw->dma->start_tx(priv->ioaddr);
1431
1432         priv->dev->stats.tx_errors++;
1433         netif_wake_queue(priv->dev);
1434 }
1435
1436 /**
1437  * stmmac_dma_interrupt - DMA ISR
1438  * @priv: driver private structure
1439  * Description: this is the DMA ISR. It is called by the main ISR.
1440  * It calls the dwmac dma routine and schedule poll method in case of some
1441  * work can be done.
1442  */
1443 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
1444 {
1445         int status;
1446         int rxfifosz = priv->plat->rx_fifo_size;
1447
1448         status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
1449         if (likely((status & handle_rx)) || (status & handle_tx)) {
1450                 if (likely(napi_schedule_prep(&priv->napi))) {
1451                         stmmac_disable_dma_irq(priv);
1452                         __napi_schedule(&priv->napi);
1453                 }
1454         }
1455         if (unlikely(status & tx_hard_error_bump_tc)) {
1456                 /* Try to bump up the dma threshold on this failure */
1457                 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
1458                     (tc <= 256)) {
1459                         tc += 64;
1460                         if (priv->plat->force_thresh_dma_mode)
1461                                 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc,
1462                                                         rxfifosz);
1463                         else
1464                                 priv->hw->dma->dma_mode(priv->ioaddr, tc,
1465                                                         SF_DMA_MODE, rxfifosz);
1466                         priv->xstats.threshold = tc;
1467                 }
1468         } else if (unlikely(status == tx_hard_error))
1469                 stmmac_tx_err(priv);
1470 }
1471
1472 /**
1473  * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
1474  * @priv: driver private structure
1475  * Description: this masks the MMC irq, in fact, the counters are managed in SW.
1476  */
1477 static void stmmac_mmc_setup(struct stmmac_priv *priv)
1478 {
1479         unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
1480                             MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
1481
1482         if (priv->synopsys_id >= DWMAC_CORE_4_00)
1483                 priv->mmcaddr = priv->ioaddr + MMC_GMAC4_OFFSET;
1484         else
1485                 priv->mmcaddr = priv->ioaddr + MMC_GMAC3_X_OFFSET;
1486
1487         dwmac_mmc_intr_all_mask(priv->mmcaddr);
1488
1489         if (priv->dma_cap.rmon) {
1490                 dwmac_mmc_ctrl(priv->mmcaddr, mode);
1491                 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
1492         } else
1493                 pr_info(" No MAC Management Counters available\n");
1494 }
1495
1496 /**
1497  * stmmac_selec_desc_mode - to select among: normal/alternate/extend descriptors
1498  * @priv: driver private structure
1499  * Description: select the Enhanced/Alternate or Normal descriptors.
1500  * In case of Enhanced/Alternate, it checks if the extended descriptors are
1501  * supported by the HW capability register.
1502  */
1503 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
1504 {
1505         if (priv->plat->enh_desc) {
1506                 pr_info(" Enhanced/Alternate descriptors\n");
1507
1508                 /* GMAC older than 3.50 has no extended descriptors */
1509                 if (priv->synopsys_id >= DWMAC_CORE_3_50) {
1510                         pr_info("\tEnabled extended descriptors\n");
1511                         priv->extend_desc = 1;
1512                 } else
1513                         pr_warn("Extended descriptors not supported\n");
1514
1515                 priv->hw->desc = &enh_desc_ops;
1516         } else {
1517                 pr_info(" Normal descriptors\n");
1518                 priv->hw->desc = &ndesc_ops;
1519         }
1520 }
1521
1522 /**
1523  * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
1524  * @priv: driver private structure
1525  * Description:
1526  *  new GMAC chip generations have a new register to indicate the
1527  *  presence of the optional feature/functions.
1528  *  This can be also used to override the value passed through the
1529  *  platform and necessary for old MAC10/100 and GMAC chips.
1530  */
1531 static int stmmac_get_hw_features(struct stmmac_priv *priv)
1532 {
1533         u32 ret = 0;
1534
1535         if (priv->hw->dma->get_hw_feature) {
1536                 priv->hw->dma->get_hw_feature(priv->ioaddr,
1537                                               &priv->dma_cap);
1538                 ret = 1;
1539         }
1540
1541         return ret;
1542 }
1543
1544 /**
1545  * stmmac_check_ether_addr - check if the MAC addr is valid
1546  * @priv: driver private structure
1547  * Description:
1548  * it is to verify if the MAC address is valid, in case of failures it
1549  * generates a random MAC address
1550  */
1551 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
1552 {
1553         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
1554                 priv->hw->mac->get_umac_addr(priv->hw,
1555                                              priv->dev->dev_addr, 0);
1556                 if (!is_valid_ether_addr(priv->dev->dev_addr))
1557                         eth_hw_addr_random(priv->dev);
1558                 pr_info("%s: device MAC address %pM\n", priv->dev->name,
1559                         priv->dev->dev_addr);
1560         }
1561 }
1562
1563 /**
1564  * stmmac_init_dma_engine - DMA init.
1565  * @priv: driver private structure
1566  * Description:
1567  * It inits the DMA invoking the specific MAC/GMAC callback.
1568  * Some DMA parameters can be passed from the platform;
1569  * in case of these are not passed a default is kept for the MAC or GMAC.
1570  */
1571 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
1572 {
1573         int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, aal = 0;
1574         int mixed_burst = 0;
1575         int atds = 0;
1576         int ret = 0;
1577
1578         if (priv->plat->dma_cfg) {
1579                 pbl = priv->plat->dma_cfg->pbl;
1580                 fixed_burst = priv->plat->dma_cfg->fixed_burst;
1581                 mixed_burst = priv->plat->dma_cfg->mixed_burst;
1582                 aal = priv->plat->dma_cfg->aal;
1583         }
1584
1585         if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
1586                 atds = 1;
1587
1588         ret = priv->hw->dma->reset(priv->ioaddr);
1589         if (ret) {
1590                 dev_err(priv->device, "Failed to reset the dma\n");
1591                 return ret;
1592         }
1593
1594         priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst,
1595                             aal, priv->dma_tx_phy, priv->dma_rx_phy, atds);
1596
1597         if (priv->synopsys_id >= DWMAC_CORE_4_00) {
1598                 priv->rx_tail_addr = priv->dma_rx_phy +
1599                             (DMA_RX_SIZE * sizeof(struct dma_desc));
1600                 priv->hw->dma->set_rx_tail_ptr(priv->ioaddr, priv->rx_tail_addr,
1601                                                STMMAC_CHAN0);
1602
1603                 priv->tx_tail_addr = priv->dma_tx_phy +
1604                             (DMA_TX_SIZE * sizeof(struct dma_desc));
1605                 priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, priv->tx_tail_addr,
1606                                                STMMAC_CHAN0);
1607         }
1608
1609         if (priv->plat->axi && priv->hw->dma->axi)
1610                 priv->hw->dma->axi(priv->ioaddr, priv->plat->axi);
1611
1612         return ret;
1613 }
1614
1615 /**
1616  * stmmac_tx_timer - mitigation sw timer for tx.
1617  * @data: data pointer
1618  * Description:
1619  * This is the timer handler to directly invoke the stmmac_tx_clean.
1620  */
1621 static void stmmac_tx_timer(unsigned long data)
1622 {
1623         struct stmmac_priv *priv = (struct stmmac_priv *)data;
1624
1625         stmmac_tx_clean(priv);
1626 }
1627
1628 /**
1629  * stmmac_init_tx_coalesce - init tx mitigation options.
1630  * @priv: driver private structure
1631  * Description:
1632  * This inits the transmit coalesce parameters: i.e. timer rate,
1633  * timer handler and default threshold used for enabling the
1634  * interrupt on completion bit.
1635  */
1636 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
1637 {
1638         priv->tx_coal_frames = STMMAC_TX_FRAMES;
1639         priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
1640         init_timer(&priv->txtimer);
1641         priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
1642         priv->txtimer.data = (unsigned long)priv;
1643         priv->txtimer.function = stmmac_tx_timer;
1644         add_timer(&priv->txtimer);
1645 }
1646
1647 /**
1648  * stmmac_hw_setup - setup mac in a usable state.
1649  *  @dev : pointer to the device structure.
1650  *  Description:
1651  *  this is the main function to setup the HW in a usable state because the
1652  *  dma engine is reset, the core registers are configured (e.g. AXI,
1653  *  Checksum features, timers). The DMA is ready to start receiving and
1654  *  transmitting.
1655  *  Return value:
1656  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1657  *  file on failure.
1658  */
1659 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
1660 {
1661         struct stmmac_priv *priv = netdev_priv(dev);
1662         int ret;
1663
1664         /* DMA initialization and SW reset */
1665         ret = stmmac_init_dma_engine(priv);
1666         if (ret < 0) {
1667                 pr_err("%s: DMA engine initialization failed\n", __func__);
1668                 return ret;
1669         }
1670
1671         /* Copy the MAC addr into the HW  */
1672         priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0);
1673
1674         /* If required, perform hw setup of the bus. */
1675         if (priv->plat->bus_setup)
1676                 priv->plat->bus_setup(priv->ioaddr);
1677
1678         /* PS and related bits will be programmed according to the speed */
1679         if (priv->hw->pcs) {
1680                 int speed = priv->plat->mac_port_sel_speed;
1681
1682                 if ((speed == SPEED_10) || (speed == SPEED_100) ||
1683                     (speed == SPEED_1000)) {
1684                         priv->hw->ps = speed;
1685                 } else {
1686                         dev_warn(priv->device, "invalid port speed\n");
1687                         priv->hw->ps = 0;
1688                 }
1689         }
1690
1691         /* Initialize the MAC Core */
1692         priv->hw->mac->core_init(priv->hw, dev->mtu);
1693
1694         ret = priv->hw->mac->rx_ipc(priv->hw);
1695         if (!ret) {
1696                 pr_warn(" RX IPC Checksum Offload disabled\n");
1697                 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
1698                 priv->hw->rx_csum = 0;
1699         }
1700
1701         /* Enable the MAC Rx/Tx */
1702         if (priv->synopsys_id >= DWMAC_CORE_4_00)
1703                 stmmac_dwmac4_set_mac(priv->ioaddr, true);
1704         else
1705                 stmmac_set_mac(priv->ioaddr, true);
1706
1707         /* Set the HW DMA mode and the COE */
1708         stmmac_dma_operation_mode(priv);
1709
1710         stmmac_mmc_setup(priv);
1711
1712         if (init_ptp) {
1713                 ret = stmmac_init_ptp(priv);
1714                 if (ret)
1715                         netdev_warn(priv->dev, "fail to init PTP.\n");
1716         }
1717
1718 #ifdef CONFIG_DEBUG_FS
1719         ret = stmmac_init_fs(dev);
1720         if (ret < 0)
1721                 pr_warn("%s: failed debugFS registration\n", __func__);
1722 #endif
1723         /* Start the ball rolling... */
1724         pr_debug("%s: DMA RX/TX processes started...\n", dev->name);
1725         priv->hw->dma->start_tx(priv->ioaddr);
1726         priv->hw->dma->start_rx(priv->ioaddr);
1727
1728         /* Dump DMA/MAC registers */
1729         if (netif_msg_hw(priv)) {
1730                 priv->hw->mac->dump_regs(priv->hw);
1731                 priv->hw->dma->dump_regs(priv->ioaddr);
1732         }
1733         priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
1734
1735         if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1736                 priv->rx_riwt = MAX_DMA_RIWT;
1737                 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
1738         }
1739
1740         if (priv->hw->pcs && priv->hw->mac->pcs_ctrl_ane)
1741                 priv->hw->mac->pcs_ctrl_ane(priv->hw, 1, priv->hw->ps, 0);
1742
1743         /*  set TX ring length */
1744         if (priv->hw->dma->set_tx_ring_len)
1745                 priv->hw->dma->set_tx_ring_len(priv->ioaddr,
1746                                                (DMA_TX_SIZE - 1));
1747         /*  set RX ring length */
1748         if (priv->hw->dma->set_rx_ring_len)
1749                 priv->hw->dma->set_rx_ring_len(priv->ioaddr,
1750                                                (DMA_RX_SIZE - 1));
1751         /* Enable TSO */
1752         if (priv->tso)
1753                 priv->hw->dma->enable_tso(priv->ioaddr, 1, STMMAC_CHAN0);
1754
1755         return 0;
1756 }
1757
1758 /**
1759  *  stmmac_open - open entry point of the driver
1760  *  @dev : pointer to the device structure.
1761  *  Description:
1762  *  This function is the open entry point of the driver.
1763  *  Return value:
1764  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1765  *  file on failure.
1766  */
1767 static int stmmac_open(struct net_device *dev)
1768 {
1769         struct stmmac_priv *priv = netdev_priv(dev);
1770         int ret;
1771
1772         stmmac_check_ether_addr(priv);
1773
1774         if (priv->hw->pcs != STMMAC_PCS_RGMII &&
1775             priv->hw->pcs != STMMAC_PCS_TBI &&
1776             priv->hw->pcs != STMMAC_PCS_RTBI) {
1777                 ret = stmmac_init_phy(dev);
1778                 if (ret) {
1779                         pr_err("%s: Cannot attach to PHY (error: %d)\n",
1780                                __func__, ret);
1781                         return ret;
1782                 }
1783         }
1784
1785         /* Extra statistics */
1786         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1787         priv->xstats.threshold = tc;
1788
1789         priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1790         priv->rx_copybreak = STMMAC_RX_COPYBREAK;
1791
1792         ret = alloc_dma_desc_resources(priv);
1793         if (ret < 0) {
1794                 pr_err("%s: DMA descriptors allocation failed\n", __func__);
1795                 goto dma_desc_error;
1796         }
1797
1798         ret = init_dma_desc_rings(dev, GFP_KERNEL);
1799         if (ret < 0) {
1800                 pr_err("%s: DMA descriptors initialization failed\n", __func__);
1801                 goto init_error;
1802         }
1803
1804         ret = stmmac_hw_setup(dev, true);
1805         if (ret < 0) {
1806                 pr_err("%s: Hw setup failed\n", __func__);
1807                 goto init_error;
1808         }
1809
1810         stmmac_init_tx_coalesce(priv);
1811
1812         if (priv->phydev)
1813                 phy_start(priv->phydev);
1814
1815         /* Request the IRQ lines */
1816         ret = request_irq(dev->irq, stmmac_interrupt,
1817                           IRQF_SHARED, dev->name, dev);
1818         if (unlikely(ret < 0)) {
1819                 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1820                        __func__, dev->irq, ret);
1821                 goto init_error;
1822         }
1823
1824         /* Request the Wake IRQ in case of another line is used for WoL */
1825         if (priv->wol_irq != dev->irq) {
1826                 ret = request_irq(priv->wol_irq, stmmac_interrupt,
1827                                   IRQF_SHARED, dev->name, dev);
1828                 if (unlikely(ret < 0)) {
1829                         pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n",
1830                                __func__, priv->wol_irq, ret);
1831                         goto wolirq_error;
1832                 }
1833         }
1834
1835         /* Request the IRQ lines */
1836         if (priv->lpi_irq > 0) {
1837                 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
1838                                   dev->name, dev);
1839                 if (unlikely(ret < 0)) {
1840                         pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1841                                __func__, priv->lpi_irq, ret);
1842                         goto lpiirq_error;
1843                 }
1844         }
1845
1846         napi_enable(&priv->napi);
1847         netif_start_queue(dev);
1848
1849         return 0;
1850
1851 lpiirq_error:
1852         if (priv->wol_irq != dev->irq)
1853                 free_irq(priv->wol_irq, dev);
1854 wolirq_error:
1855         free_irq(dev->irq, dev);
1856
1857 init_error:
1858         free_dma_desc_resources(priv);
1859 dma_desc_error:
1860         if (priv->phydev)
1861                 phy_disconnect(priv->phydev);
1862
1863         return ret;
1864 }
1865
1866 /**
1867  *  stmmac_release - close entry point of the driver
1868  *  @dev : device pointer.
1869  *  Description:
1870  *  This is the stop entry point of the driver.
1871  */
1872 static int stmmac_release(struct net_device *dev)
1873 {
1874         struct stmmac_priv *priv = netdev_priv(dev);
1875
1876         if (priv->eee_enabled)
1877                 del_timer_sync(&priv->eee_ctrl_timer);
1878
1879         /* Stop and disconnect the PHY */
1880         if (priv->phydev) {
1881                 phy_stop(priv->phydev);
1882                 phy_disconnect(priv->phydev);
1883                 priv->phydev = NULL;
1884         }
1885
1886         netif_stop_queue(dev);
1887
1888         napi_disable(&priv->napi);
1889
1890         del_timer_sync(&priv->txtimer);
1891
1892         /* Free the IRQ lines */
1893         free_irq(dev->irq, dev);
1894         if (priv->wol_irq != dev->irq)
1895                 free_irq(priv->wol_irq, dev);
1896         if (priv->lpi_irq > 0)
1897                 free_irq(priv->lpi_irq, dev);
1898
1899         /* Stop TX/RX DMA and clear the descriptors */
1900         priv->hw->dma->stop_tx(priv->ioaddr);
1901         priv->hw->dma->stop_rx(priv->ioaddr);
1902
1903         /* Release and free the Rx/Tx resources */
1904         free_dma_desc_resources(priv);
1905
1906         /* Disable the MAC Rx/Tx */
1907         stmmac_set_mac(priv->ioaddr, false);
1908
1909         netif_carrier_off(dev);
1910
1911 #ifdef CONFIG_DEBUG_FS
1912         stmmac_exit_fs(dev);
1913 #endif
1914
1915         stmmac_release_ptp(priv);
1916
1917         return 0;
1918 }
1919
1920 /**
1921  *  stmmac_tso_allocator - close entry point of the driver
1922  *  @priv: driver private structure
1923  *  @des: buffer start address
1924  *  @total_len: total length to fill in descriptors
1925  *  @last_segmant: condition for the last descriptor
1926  *  Description:
1927  *  This function fills descriptor and request new descriptors according to
1928  *  buffer length to fill
1929  */
1930 static void stmmac_tso_allocator(struct stmmac_priv *priv, unsigned int des,
1931                                  int total_len, bool last_segment)
1932 {
1933         struct dma_desc *desc;
1934         int tmp_len;
1935         u32 buff_size;
1936
1937         tmp_len = total_len;
1938
1939         while (tmp_len > 0) {
1940                 priv->cur_tx = STMMAC_GET_ENTRY(priv->cur_tx, DMA_TX_SIZE);
1941                 desc = priv->dma_tx + priv->cur_tx;
1942
1943                 desc->des0 = des + (total_len - tmp_len);
1944                 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ?
1945                             TSO_MAX_BUFF_SIZE : tmp_len;
1946
1947                 priv->hw->desc->prepare_tso_tx_desc(desc, 0, buff_size,
1948                         0, 1,
1949                         (last_segment) && (buff_size < TSO_MAX_BUFF_SIZE),
1950                         0, 0);
1951
1952                 tmp_len -= TSO_MAX_BUFF_SIZE;
1953         }
1954 }
1955
1956 /**
1957  *  stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO)
1958  *  @skb : the socket buffer
1959  *  @dev : device pointer
1960  *  Description: this is the transmit function that is called on TSO frames
1961  *  (support available on GMAC4 and newer chips).
1962  *  Diagram below show the ring programming in case of TSO frames:
1963  *
1964  *  First Descriptor
1965  *   --------
1966  *   | DES0 |---> buffer1 = L2/L3/L4 header
1967  *   | DES1 |---> TCP Payload (can continue on next descr...)
1968  *   | DES2 |---> buffer 1 and 2 len
1969  *   | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0]
1970  *   --------
1971  *      |
1972  *     ...
1973  *      |
1974  *   --------
1975  *   | DES0 | --| Split TCP Payload on Buffers 1 and 2
1976  *   | DES1 | --|
1977  *   | DES2 | --> buffer 1 and 2 len
1978  *   | DES3 |
1979  *   --------
1980  *
1981  * mss is fixed when enable tso, so w/o programming the TDES3 ctx field.
1982  */
1983 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
1984 {
1985         u32 pay_len, mss;
1986         int tmp_pay_len = 0;
1987         struct stmmac_priv *priv = netdev_priv(dev);
1988         int nfrags = skb_shinfo(skb)->nr_frags;
1989         unsigned int first_entry, des;
1990         struct dma_desc *desc, *first, *mss_desc = NULL;
1991         u8 proto_hdr_len;
1992         int i;
1993
1994         spin_lock(&priv->tx_lock);
1995
1996         /* Compute header lengths */
1997         proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
1998
1999         /* Desc availability based on threshold should be enough safe */
2000         if (unlikely(stmmac_tx_avail(priv) <
2001                 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) {
2002                 if (!netif_queue_stopped(dev)) {
2003                         netif_stop_queue(dev);
2004                         /* This is a hard error, log it. */
2005                         pr_err("%s: Tx Ring full when queue awake\n", __func__);
2006                 }
2007                 spin_unlock(&priv->tx_lock);
2008                 return NETDEV_TX_BUSY;
2009         }
2010
2011         pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */
2012
2013         mss = skb_shinfo(skb)->gso_size;
2014
2015         /* set new MSS value if needed */
2016         if (mss != priv->mss) {
2017                 mss_desc = priv->dma_tx + priv->cur_tx;
2018                 priv->hw->desc->set_mss(mss_desc, mss);
2019                 priv->mss = mss;
2020                 priv->cur_tx = STMMAC_GET_ENTRY(priv->cur_tx, DMA_TX_SIZE);
2021         }
2022
2023         if (netif_msg_tx_queued(priv)) {
2024                 pr_info("%s: tcphdrlen %d, hdr_len %d, pay_len %d, mss %d\n",
2025                         __func__, tcp_hdrlen(skb), proto_hdr_len, pay_len, mss);
2026                 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len,
2027                         skb->data_len);
2028         }
2029
2030         first_entry = priv->cur_tx;
2031
2032         desc = priv->dma_tx + first_entry;
2033         first = desc;
2034
2035         /* first descriptor: fill Headers on Buf1 */
2036         des = dma_map_single(priv->device, skb->data, skb_headlen(skb),
2037                              DMA_TO_DEVICE);
2038         if (dma_mapping_error(priv->device, des))
2039                 goto dma_map_err;
2040
2041         priv->tx_skbuff_dma[first_entry].buf = des;
2042         priv->tx_skbuff_dma[first_entry].len = skb_headlen(skb);
2043         priv->tx_skbuff[first_entry] = skb;
2044
2045         first->des0 = des;
2046
2047         /* Fill start of payload in buff2 of first descriptor */
2048         if (pay_len)
2049                 first->des1 =  des + proto_hdr_len;
2050
2051         /* If needed take extra descriptors to fill the remaining payload */
2052         tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE;
2053
2054         stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0));
2055
2056         /* Prepare fragments */
2057         for (i = 0; i < nfrags; i++) {
2058                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2059
2060                 des = skb_frag_dma_map(priv->device, frag, 0,
2061                                        skb_frag_size(frag),
2062                                        DMA_TO_DEVICE);
2063
2064                 stmmac_tso_allocator(priv, des, skb_frag_size(frag),
2065                                      (i == nfrags - 1));
2066
2067                 priv->tx_skbuff_dma[priv->cur_tx].buf = des;
2068                 priv->tx_skbuff_dma[priv->cur_tx].len = skb_frag_size(frag);
2069                 priv->tx_skbuff[priv->cur_tx] = NULL;
2070                 priv->tx_skbuff_dma[priv->cur_tx].map_as_page = true;
2071         }
2072
2073         priv->tx_skbuff_dma[priv->cur_tx].last_segment = true;
2074
2075         priv->cur_tx = STMMAC_GET_ENTRY(priv->cur_tx, DMA_TX_SIZE);
2076
2077         if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
2078                 if (netif_msg_hw(priv))
2079                         pr_debug("%s: stop transmitted packets\n", __func__);
2080                 netif_stop_queue(dev);
2081         }
2082
2083         dev->stats.tx_bytes += skb->len;
2084         priv->xstats.tx_tso_frames++;
2085         priv->xstats.tx_tso_nfrags += nfrags;
2086
2087         /* Manage tx mitigation */
2088         priv->tx_count_frames += nfrags + 1;
2089         if (likely(priv->tx_coal_frames > priv->tx_count_frames)) {
2090                 mod_timer(&priv->txtimer,
2091                           STMMAC_COAL_TIMER(priv->tx_coal_timer));
2092         } else {
2093                 priv->tx_count_frames = 0;
2094                 priv->hw->desc->set_tx_ic(desc);
2095                 priv->xstats.tx_set_ic_bit++;
2096         }
2097
2098         if (!priv->hwts_tx_en)
2099                 skb_tx_timestamp(skb);
2100
2101         if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2102                      priv->hwts_tx_en)) {
2103                 /* declare that device is doing timestamping */
2104                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2105                 priv->hw->desc->enable_tx_timestamp(first);
2106         }
2107
2108         /* Complete the first descriptor before granting the DMA */
2109         priv->hw->desc->prepare_tso_tx_desc(first, 1,
2110                         proto_hdr_len,
2111                         pay_len,
2112                         1, priv->tx_skbuff_dma[first_entry].last_segment,
2113                         tcp_hdrlen(skb) / 4, (skb->len - proto_hdr_len));
2114
2115         /* If context desc is used to change MSS */
2116         if (mss_desc)
2117                 priv->hw->desc->set_tx_owner(mss_desc);
2118
2119         /* The own bit must be the latest setting done when prepare the
2120          * descriptor and then barrier is needed to make sure that
2121          * all is coherent before granting the DMA engine.
2122          */
2123         smp_wmb();
2124
2125         if (netif_msg_pktdata(priv)) {
2126                 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n",
2127                         __func__, priv->cur_tx, priv->dirty_tx, first_entry,
2128                         priv->cur_tx, first, nfrags);
2129
2130                 priv->hw->desc->display_ring((void *)priv->dma_tx, DMA_TX_SIZE,
2131                                              0);
2132
2133                 pr_info(">>> frame to be transmitted: ");
2134                 print_pkt(skb->data, skb_headlen(skb));
2135         }
2136
2137         netdev_sent_queue(dev, skb->len);
2138
2139         priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, priv->tx_tail_addr,
2140                                        STMMAC_CHAN0);
2141
2142         spin_unlock(&priv->tx_lock);
2143         return NETDEV_TX_OK;
2144
2145 dma_map_err:
2146         spin_unlock(&priv->tx_lock);
2147         dev_err(priv->device, "Tx dma map failed\n");
2148         dev_kfree_skb(skb);
2149         priv->dev->stats.tx_dropped++;
2150         return NETDEV_TX_OK;
2151 }
2152
2153 /**
2154  *  stmmac_xmit - Tx entry point of the driver
2155  *  @skb : the socket buffer
2156  *  @dev : device pointer
2157  *  Description : this is the tx entry point of the driver.
2158  *  It programs the chain or the ring and supports oversized frames
2159  *  and SG feature.
2160  */
2161 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
2162 {
2163         struct stmmac_priv *priv = netdev_priv(dev);
2164         unsigned int nopaged_len = skb_headlen(skb);
2165         int i, csum_insertion = 0, is_jumbo = 0;
2166         int nfrags = skb_shinfo(skb)->nr_frags;
2167         unsigned int entry, first_entry;
2168         struct dma_desc *desc, *first;
2169         unsigned int enh_desc;
2170         unsigned int des;
2171
2172         /* Manage oversized TCP frames for GMAC4 device */
2173         if (skb_is_gso(skb) && priv->tso) {
2174                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2175                         return stmmac_tso_xmit(skb, dev);
2176         }
2177
2178         spin_lock(&priv->tx_lock);
2179
2180         if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
2181                 spin_unlock(&priv->tx_lock);
2182                 if (!netif_queue_stopped(dev)) {
2183                         netif_stop_queue(dev);
2184                         /* This is a hard error, log it. */
2185                         pr_err("%s: Tx Ring full when queue awake\n", __func__);
2186                 }
2187                 return NETDEV_TX_BUSY;
2188         }
2189
2190         if (priv->tx_path_in_lpi_mode)
2191                 stmmac_disable_eee_mode(priv);
2192
2193         entry = priv->cur_tx;
2194         first_entry = entry;
2195
2196         csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
2197
2198         if (likely(priv->extend_desc))
2199                 desc = (struct dma_desc *)(priv->dma_etx + entry);
2200         else
2201                 desc = priv->dma_tx + entry;
2202
2203         first = desc;
2204
2205         priv->tx_skbuff[first_entry] = skb;
2206
2207         enh_desc = priv->plat->enh_desc;
2208         /* To program the descriptors according to the size of the frame */
2209         if (enh_desc)
2210                 is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc);
2211
2212         if (unlikely(is_jumbo) && likely(priv->synopsys_id <
2213                                          DWMAC_CORE_4_00)) {
2214                 entry = priv->hw->mode->jumbo_frm(priv, skb, csum_insertion);
2215                 if (unlikely(entry < 0))
2216                         goto dma_map_err;
2217         }
2218
2219         for (i = 0; i < nfrags; i++) {
2220                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2221                 int len = skb_frag_size(frag);
2222                 bool last_segment = (i == (nfrags - 1));
2223
2224                 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
2225
2226                 if (likely(priv->extend_desc))
2227                         desc = (struct dma_desc *)(priv->dma_etx + entry);
2228                 else
2229                         desc = priv->dma_tx + entry;
2230
2231                 des = skb_frag_dma_map(priv->device, frag, 0, len,
2232                                        DMA_TO_DEVICE);
2233                 if (dma_mapping_error(priv->device, des))
2234                         goto dma_map_err; /* should reuse desc w/o issues */
2235
2236                 priv->tx_skbuff[entry] = NULL;
2237
2238                 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) {
2239                         desc->des0 = des;
2240                         priv->tx_skbuff_dma[entry].buf = desc->des0;
2241                 } else {
2242                         desc->des2 = des;
2243                         priv->tx_skbuff_dma[entry].buf = desc->des2;
2244                 }
2245
2246                 priv->tx_skbuff_dma[entry].map_as_page = true;
2247                 priv->tx_skbuff_dma[entry].len = len;
2248                 priv->tx_skbuff_dma[entry].last_segment = last_segment;
2249
2250                 /* Prepare the descriptor and set the own bit too */
2251                 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion,
2252                                                 priv->mode, 1, last_segment);
2253         }
2254
2255         entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
2256
2257         priv->cur_tx = entry;
2258
2259         if (netif_msg_pktdata(priv)) {
2260                 void *tx_head;
2261
2262                 pr_debug("%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d",
2263                          __func__, priv->cur_tx, priv->dirty_tx, first_entry,
2264                          entry, first, nfrags);
2265
2266                 if (priv->extend_desc)
2267                         tx_head = (void *)priv->dma_etx;
2268                 else
2269                         tx_head = (void *)priv->dma_tx;
2270
2271                 priv->hw->desc->display_ring(tx_head, DMA_TX_SIZE, false);
2272
2273                 pr_debug(">>> frame to be transmitted: ");
2274                 print_pkt(skb->data, skb->len);
2275         }
2276
2277         if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
2278                 if (netif_msg_hw(priv))
2279                         pr_debug("%s: stop transmitted packets\n", __func__);
2280                 netif_stop_queue(dev);
2281         }
2282
2283         dev->stats.tx_bytes += skb->len;
2284
2285         /* According to the coalesce parameter the IC bit for the latest
2286          * segment is reset and the timer re-started to clean the tx status.
2287          * This approach takes care about the fragments: desc is the first
2288          * element in case of no SG.
2289          */
2290         priv->tx_count_frames += nfrags + 1;
2291         if (likely(priv->tx_coal_frames > priv->tx_count_frames)) {
2292                 mod_timer(&priv->txtimer,
2293                           STMMAC_COAL_TIMER(priv->tx_coal_timer));
2294         } else {
2295                 priv->tx_count_frames = 0;
2296                 priv->hw->desc->set_tx_ic(desc);
2297                 priv->xstats.tx_set_ic_bit++;
2298         }
2299
2300         if (!priv->hwts_tx_en)
2301                 skb_tx_timestamp(skb);
2302
2303         /* Ready to fill the first descriptor and set the OWN bit w/o any
2304          * problems because all the descriptors are actually ready to be
2305          * passed to the DMA engine.
2306          */
2307         if (likely(!is_jumbo)) {
2308                 bool last_segment = (nfrags == 0);
2309
2310                 des = dma_map_single(priv->device, skb->data,
2311                                      nopaged_len, DMA_TO_DEVICE);
2312                 if (dma_mapping_error(priv->device, des))
2313                         goto dma_map_err;
2314
2315                 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) {
2316                         first->des0 = des;
2317                         priv->tx_skbuff_dma[first_entry].buf = first->des0;
2318                 } else {
2319                         first->des2 = des;
2320                         priv->tx_skbuff_dma[first_entry].buf = first->des2;
2321                 }
2322
2323                 priv->tx_skbuff_dma[first_entry].len = nopaged_len;
2324                 priv->tx_skbuff_dma[first_entry].last_segment = last_segment;
2325
2326                 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2327                              priv->hwts_tx_en)) {
2328                         /* declare that device is doing timestamping */
2329                         skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2330                         priv->hw->desc->enable_tx_timestamp(first);
2331                 }
2332
2333                 /* Prepare the first descriptor setting the OWN bit too */
2334                 priv->hw->desc->prepare_tx_desc(first, 1, nopaged_len,
2335                                                 csum_insertion, priv->mode, 1,
2336                                                 last_segment);
2337
2338                 /* The own bit must be the latest setting done when prepare the
2339                  * descriptor and then barrier is needed to make sure that
2340                  * all is coherent before granting the DMA engine.
2341                  */
2342                 smp_wmb();
2343         }
2344
2345         netdev_sent_queue(dev, skb->len);
2346
2347         if (priv->synopsys_id < DWMAC_CORE_4_00)
2348                 priv->hw->dma->enable_dma_transmission(priv->ioaddr);
2349         else
2350                 priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, priv->tx_tail_addr,
2351                                                STMMAC_CHAN0);
2352
2353         spin_unlock(&priv->tx_lock);
2354         return NETDEV_TX_OK;
2355
2356 dma_map_err:
2357         spin_unlock(&priv->tx_lock);
2358         dev_err(priv->device, "Tx dma map failed\n");
2359         dev_kfree_skb(skb);
2360         priv->dev->stats.tx_dropped++;
2361         return NETDEV_TX_OK;
2362 }
2363
2364 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
2365 {
2366         struct ethhdr *ehdr;
2367         u16 vlanid;
2368
2369         if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) ==
2370             NETIF_F_HW_VLAN_CTAG_RX &&
2371             !__vlan_get_tag(skb, &vlanid)) {
2372                 /* pop the vlan tag */
2373                 ehdr = (struct ethhdr *)skb->data;
2374                 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
2375                 skb_pull(skb, VLAN_HLEN);
2376                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
2377         }
2378 }
2379
2380
2381 static inline int stmmac_rx_threshold_count(struct stmmac_priv *priv)
2382 {
2383         if (priv->rx_zeroc_thresh < STMMAC_RX_THRESH)
2384                 return 0;
2385
2386         return 1;
2387 }
2388
2389 /**
2390  * stmmac_rx_refill - refill used skb preallocated buffers
2391  * @priv: driver private structure
2392  * Description : this is to reallocate the skb for the reception process
2393  * that is based on zero-copy.
2394  */
2395 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
2396 {
2397         int bfsize = priv->dma_buf_sz;
2398         unsigned int entry = priv->dirty_rx;
2399         int dirty = stmmac_rx_dirty(priv);
2400
2401         while (dirty-- > 0) {
2402                 struct dma_desc *p;
2403
2404                 if (priv->extend_desc)
2405                         p = (struct dma_desc *)(priv->dma_erx + entry);
2406                 else
2407                         p = priv->dma_rx + entry;
2408
2409                 if (likely(priv->rx_skbuff[entry] == NULL)) {
2410                         struct sk_buff *skb;
2411
2412                         skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
2413                         if (unlikely(!skb)) {
2414                                 /* so for a while no zero-copy! */
2415                                 priv->rx_zeroc_thresh = STMMAC_RX_THRESH;
2416                                 if (unlikely(net_ratelimit()))
2417                                         dev_err(priv->device,
2418                                                 "fail to alloc skb entry %d\n",
2419                                                 entry);
2420                                 break;
2421                         }
2422
2423                         priv->rx_skbuff[entry] = skb;
2424                         priv->rx_skbuff_dma[entry] =
2425                             dma_map_single(priv->device, skb->data, bfsize,
2426                                            DMA_FROM_DEVICE);
2427                         if (dma_mapping_error(priv->device,
2428                                               priv->rx_skbuff_dma[entry])) {
2429                                 dev_err(priv->device, "Rx dma map failed\n");
2430                                 dev_kfree_skb(skb);
2431                                 break;
2432                         }
2433
2434                         if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) {
2435                                 p->des0 = priv->rx_skbuff_dma[entry];
2436                                 p->des1 = 0;
2437                         } else {
2438                                 p->des2 = priv->rx_skbuff_dma[entry];
2439                         }
2440                         if (priv->hw->mode->refill_desc3)
2441                                 priv->hw->mode->refill_desc3(priv, p);
2442
2443                         if (priv->rx_zeroc_thresh > 0)
2444                                 priv->rx_zeroc_thresh--;
2445
2446                         if (netif_msg_rx_status(priv))
2447                                 pr_debug("\trefill entry #%d\n", entry);
2448                 }
2449                 wmb();
2450
2451                 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00))
2452                         priv->hw->desc->init_rx_desc(p, priv->use_riwt, 0, 0);
2453                 else
2454                         priv->hw->desc->set_rx_owner(p);
2455
2456                 wmb();
2457
2458                 entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE);
2459         }
2460         priv->dirty_rx = entry;
2461 }
2462
2463 /**
2464  * stmmac_rx - manage the receive process
2465  * @priv: driver private structure
2466  * @limit: napi bugget.
2467  * Description :  this the function called by the napi poll method.
2468  * It gets all the frames inside the ring.
2469  */
2470 static int stmmac_rx(struct stmmac_priv *priv, int limit)
2471 {
2472         unsigned int entry = priv->cur_rx;
2473         unsigned int next_entry;
2474         unsigned int count = 0;
2475         int coe = priv->hw->rx_csum;
2476
2477         if (netif_msg_rx_status(priv)) {
2478                 void *rx_head;
2479
2480                 pr_debug("%s: descriptor ring:\n", __func__);
2481                 if (priv->extend_desc)
2482                         rx_head = (void *)priv->dma_erx;
2483                 else
2484                         rx_head = (void *)priv->dma_rx;
2485
2486                 priv->hw->desc->display_ring(rx_head, DMA_RX_SIZE, true);
2487         }
2488         while (count < limit) {
2489                 int status;
2490                 struct dma_desc *p;
2491
2492                 if (priv->extend_desc)
2493                         p = (struct dma_desc *)(priv->dma_erx + entry);
2494                 else
2495                         p = priv->dma_rx + entry;
2496
2497                 /* read the status of the incoming frame */
2498                 status = priv->hw->desc->rx_status(&priv->dev->stats,
2499                                                    &priv->xstats, p);
2500                 /* check if managed by the DMA otherwise go ahead */
2501                 if (unlikely(status & dma_own))
2502                         break;
2503
2504                 count++;
2505
2506                 priv->cur_rx = STMMAC_GET_ENTRY(priv->cur_rx, DMA_RX_SIZE);
2507                 next_entry = priv->cur_rx;
2508
2509                 if (priv->extend_desc)
2510                         prefetch(priv->dma_erx + next_entry);
2511                 else
2512                         prefetch(priv->dma_rx + next_entry);
2513
2514                 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))
2515                         priv->hw->desc->rx_extended_status(&priv->dev->stats,
2516                                                            &priv->xstats,
2517                                                            priv->dma_erx +
2518                                                            entry);
2519                 if (unlikely(status == discard_frame)) {
2520                         priv->dev->stats.rx_errors++;
2521                         if (priv->hwts_rx_en && !priv->extend_desc) {
2522                                 /* DESC2 & DESC3 will be overwitten by device
2523                                  * with timestamp value, hence reinitialize
2524                                  * them in stmmac_rx_refill() function so that
2525                                  * device can reuse it.
2526                                  */
2527                                 priv->rx_skbuff[entry] = NULL;
2528                                 dma_unmap_single(priv->device,
2529                                                  priv->rx_skbuff_dma[entry],
2530                                                  priv->dma_buf_sz,
2531                                                  DMA_FROM_DEVICE);
2532                         }
2533                 } else {
2534                         struct sk_buff *skb;
2535                         int frame_len;
2536                         unsigned int des;
2537
2538                         if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00))
2539                                 des = p->des0;
2540                         else
2541                                 des = p->des2;
2542
2543                         frame_len = priv->hw->desc->get_rx_frame_len(p, coe);
2544
2545                         /*  If frame length is greather than skb buffer size
2546                          *  (preallocated during init) then the packet is
2547                          *  ignored
2548                          */
2549                         if (frame_len > priv->dma_buf_sz) {
2550                                 pr_err("%s: len %d larger than size (%d)\n",
2551                                        priv->dev->name, frame_len,
2552                                        priv->dma_buf_sz);
2553                                 priv->dev->stats.rx_length_errors++;
2554                                 break;
2555                         }
2556
2557                         /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
2558                          * Type frames (LLC/LLC-SNAP)
2559                          */
2560                         if (unlikely(status != llc_snap))
2561                                 frame_len -= ETH_FCS_LEN;
2562
2563                         if (netif_msg_rx_status(priv)) {
2564                                 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
2565                                         p, entry, des);
2566                                 if (frame_len > ETH_FRAME_LEN)
2567                                         pr_debug("\tframe size %d, COE: %d\n",
2568                                                  frame_len, status);
2569                         }
2570
2571                         /* The zero-copy is always used for all the sizes
2572                          * in case of GMAC4 because it needs
2573                          * to refill the used descriptors, always.
2574                          */
2575                         if (unlikely(!priv->plat->has_gmac4 &&
2576                                      ((frame_len < priv->rx_copybreak) ||
2577                                      stmmac_rx_threshold_count(priv)))) {
2578                                 skb = netdev_alloc_skb_ip_align(priv->dev,
2579                                                                 frame_len);
2580                                 if (unlikely(!skb)) {
2581                                         if (net_ratelimit())
2582                                                 dev_warn(priv->device,
2583                                                          "packet dropped\n");
2584                                         priv->dev->stats.rx_dropped++;
2585                                         break;
2586                                 }
2587
2588                                 dma_sync_single_for_cpu(priv->device,
2589                                                         priv->rx_skbuff_dma
2590                                                         [entry], frame_len,
2591                                                         DMA_FROM_DEVICE);
2592                                 skb_copy_to_linear_data(skb,
2593                                                         priv->
2594                                                         rx_skbuff[entry]->data,
2595                                                         frame_len);
2596
2597                                 skb_put(skb, frame_len);
2598                                 dma_sync_single_for_device(priv->device,
2599                                                            priv->rx_skbuff_dma
2600                                                            [entry], frame_len,
2601                                                            DMA_FROM_DEVICE);
2602                         } else {
2603                                 skb = priv->rx_skbuff[entry];
2604                                 if (unlikely(!skb)) {
2605                                         pr_err("%s: Inconsistent Rx chain\n",
2606                                                priv->dev->name);
2607                                         priv->dev->stats.rx_dropped++;
2608                                         break;
2609                                 }
2610                                 prefetch(skb->data - NET_IP_ALIGN);
2611                                 priv->rx_skbuff[entry] = NULL;
2612                                 priv->rx_zeroc_thresh++;
2613
2614                                 skb_put(skb, frame_len);
2615                                 dma_unmap_single(priv->device,
2616                                                  priv->rx_skbuff_dma[entry],
2617                                                  priv->dma_buf_sz,
2618                                                  DMA_FROM_DEVICE);
2619                         }
2620
2621                         stmmac_get_rx_hwtstamp(priv, entry, skb);
2622
2623                         if (netif_msg_pktdata(priv)) {
2624                                 pr_debug("frame received (%dbytes)", frame_len);
2625                                 print_pkt(skb->data, frame_len);
2626                         }
2627
2628                         stmmac_rx_vlan(priv->dev, skb);
2629
2630                         skb->protocol = eth_type_trans(skb, priv->dev);
2631
2632                         if (unlikely(!coe))
2633                                 skb_checksum_none_assert(skb);
2634                         else
2635                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2636
2637                         napi_gro_receive(&priv->napi, skb);
2638
2639                         priv->dev->stats.rx_packets++;
2640                         priv->dev->stats.rx_bytes += frame_len;
2641                 }
2642                 entry = next_entry;
2643         }
2644
2645         stmmac_rx_refill(priv);
2646
2647         priv->xstats.rx_pkt_n += count;
2648
2649         return count;
2650 }
2651
2652 /**
2653  *  stmmac_poll - stmmac poll method (NAPI)
2654  *  @napi : pointer to the napi structure.
2655  *  @budget : maximum number of packets that the current CPU can receive from
2656  *            all interfaces.
2657  *  Description :
2658  *  To look at the incoming frames and clear the tx resources.
2659  */
2660 static int stmmac_poll(struct napi_struct *napi, int budget)
2661 {
2662         struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
2663         int work_done = 0;
2664
2665         priv->xstats.napi_poll++;
2666         stmmac_tx_clean(priv);
2667
2668         work_done = stmmac_rx(priv, budget);
2669         if (work_done < budget) {
2670                 napi_complete(napi);
2671                 stmmac_enable_dma_irq(priv);
2672         }
2673         return work_done;
2674 }
2675
2676 /**
2677  *  stmmac_tx_timeout
2678  *  @dev : Pointer to net device structure
2679  *  Description: this function is called when a packet transmission fails to
2680  *   complete within a reasonable time. The driver will mark the error in the
2681  *   netdev structure and arrange for the device to be reset to a sane state
2682  *   in order to transmit a new packet.
2683  */
2684 static void stmmac_tx_timeout(struct net_device *dev)
2685 {
2686         struct stmmac_priv *priv = netdev_priv(dev);
2687
2688         /* Clear Tx resources and restart transmitting again */
2689         stmmac_tx_err(priv);
2690 }
2691
2692 /**
2693  *  stmmac_set_rx_mode - entry point for multicast addressing
2694  *  @dev : pointer to the device structure
2695  *  Description:
2696  *  This function is a driver entry point which gets called by the kernel
2697  *  whenever multicast addresses must be enabled/disabled.
2698  *  Return value:
2699  *  void.
2700  */
2701 static void stmmac_set_rx_mode(struct net_device *dev)
2702 {
2703         struct stmmac_priv *priv = netdev_priv(dev);
2704
2705         priv->hw->mac->set_filter(priv->hw, dev);
2706 }
2707
2708 /**
2709  *  stmmac_change_mtu - entry point to change MTU size for the device.
2710  *  @dev : device pointer.
2711  *  @new_mtu : the new MTU size for the device.
2712  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
2713  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
2714  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
2715  *  Return value:
2716  *  0 on success and an appropriate (-)ve integer as defined in errno.h
2717  *  file on failure.
2718  */
2719 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
2720 {
2721         struct stmmac_priv *priv = netdev_priv(dev);
2722         int max_mtu;
2723
2724         if (netif_running(dev)) {
2725                 pr_err("%s: must be stopped to change its MTU\n", dev->name);
2726                 return -EBUSY;
2727         }
2728
2729         if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00))
2730                 max_mtu = JUMBO_LEN;
2731         else
2732                 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
2733
2734         if (priv->plat->maxmtu < max_mtu)
2735                 max_mtu = priv->plat->maxmtu;
2736
2737         if ((new_mtu < 46) || (new_mtu > max_mtu)) {
2738                 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
2739                 return -EINVAL;
2740         }
2741
2742         dev->mtu = new_mtu;
2743
2744         netdev_update_features(dev);
2745
2746         return 0;
2747 }
2748
2749 static netdev_features_t stmmac_fix_features(struct net_device *dev,
2750                                              netdev_features_t features)
2751 {
2752         struct stmmac_priv *priv = netdev_priv(dev);
2753
2754         if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
2755                 features &= ~NETIF_F_RXCSUM;
2756
2757         if (!priv->plat->tx_coe)
2758                 features &= ~NETIF_F_CSUM_MASK;
2759
2760         /* Some GMAC devices have a bugged Jumbo frame support that
2761          * needs to have the Tx COE disabled for oversized frames
2762          * (due to limited buffer sizes). In this case we disable
2763          * the TX csum insertionin the TDES and not use SF.
2764          */
2765         if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
2766                 features &= ~NETIF_F_CSUM_MASK;
2767
2768         /* Disable tso if asked by ethtool */
2769         if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
2770                 if (features & NETIF_F_TSO)
2771                         priv->tso = true;
2772                 else
2773                         priv->tso = false;
2774         }
2775
2776         return features;
2777 }
2778
2779 static int stmmac_set_features(struct net_device *netdev,
2780                                netdev_features_t features)
2781 {
2782         struct stmmac_priv *priv = netdev_priv(netdev);
2783
2784         /* Keep the COE Type in case of csum is supporting */
2785         if (features & NETIF_F_RXCSUM)
2786                 priv->hw->rx_csum = priv->plat->rx_coe;
2787         else
2788                 priv->hw->rx_csum = 0;
2789         /* No check needed because rx_coe has been set before and it will be
2790          * fixed in case of issue.
2791          */
2792         priv->hw->mac->rx_ipc(priv->hw);
2793
2794         return 0;
2795 }
2796
2797 /**
2798  *  stmmac_interrupt - main ISR
2799  *  @irq: interrupt number.
2800  *  @dev_id: to pass the net device pointer.
2801  *  Description: this is the main driver interrupt service routine.
2802  *  It can call:
2803  *  o DMA service routine (to manage incoming frame reception and transmission
2804  *    status)
2805  *  o Core interrupts to manage: remote wake-up, management counter, LPI
2806  *    interrupts.
2807  */
2808 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
2809 {
2810         struct net_device *dev = (struct net_device *)dev_id;
2811         struct stmmac_priv *priv = netdev_priv(dev);
2812
2813         if (priv->irq_wake)
2814                 pm_wakeup_event(priv->device, 0);
2815
2816         if (unlikely(!dev)) {
2817                 pr_err("%s: invalid dev pointer\n", __func__);
2818                 return IRQ_NONE;
2819         }
2820
2821         /* To handle GMAC own interrupts */
2822         if ((priv->plat->has_gmac) || (priv->plat->has_gmac4)) {
2823                 int status = priv->hw->mac->host_irq_status(priv->hw,
2824                                                             &priv->xstats);
2825                 if (unlikely(status)) {
2826                         /* For LPI we need to save the tx status */
2827                         if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
2828                                 priv->tx_path_in_lpi_mode = true;
2829                         if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
2830                                 priv->tx_path_in_lpi_mode = false;
2831                         if (status & CORE_IRQ_MTL_RX_OVERFLOW && priv->hw->dma->set_rx_tail_ptr)
2832                                 priv->hw->dma->set_rx_tail_ptr(priv->ioaddr,
2833                                                         priv->rx_tail_addr,
2834                                                         STMMAC_CHAN0);
2835                 }
2836
2837                 /* PCS link status */
2838                 if (priv->hw->pcs) {
2839                         if (priv->xstats.pcs_link)
2840                                 netif_carrier_on(dev);
2841                         else
2842                                 netif_carrier_off(dev);
2843                 }
2844         }
2845
2846         /* To handle DMA interrupts */
2847         stmmac_dma_interrupt(priv);
2848
2849         return IRQ_HANDLED;
2850 }
2851
2852 #ifdef CONFIG_NET_POLL_CONTROLLER
2853 /* Polling receive - used by NETCONSOLE and other diagnostic tools
2854  * to allow network I/O with interrupts disabled.
2855  */
2856 static void stmmac_poll_controller(struct net_device *dev)
2857 {
2858         disable_irq(dev->irq);
2859         stmmac_interrupt(dev->irq, dev);
2860         enable_irq(dev->irq);
2861 }
2862 #endif
2863
2864 /**
2865  *  stmmac_ioctl - Entry point for the Ioctl
2866  *  @dev: Device pointer.
2867  *  @rq: An IOCTL specefic structure, that can contain a pointer to
2868  *  a proprietary structure used to pass information to the driver.
2869  *  @cmd: IOCTL command
2870  *  Description:
2871  *  Currently it supports the phy_mii_ioctl(...) and HW time stamping.
2872  */
2873 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2874 {
2875         struct stmmac_priv *priv = netdev_priv(dev);
2876         int ret = -EOPNOTSUPP;
2877
2878         if (!netif_running(dev))
2879                 return -EINVAL;
2880
2881         switch (cmd) {
2882         case SIOCGMIIPHY:
2883         case SIOCGMIIREG:
2884         case SIOCSMIIREG:
2885                 if (!priv->phydev)
2886                         return -EINVAL;
2887                 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
2888                 break;
2889         case SIOCSHWTSTAMP:
2890                 ret = stmmac_hwtstamp_ioctl(dev, rq);
2891                 break;
2892         default:
2893                 break;
2894         }
2895
2896         return ret;
2897 }
2898
2899 #ifdef CONFIG_DEBUG_FS
2900 static struct dentry *stmmac_fs_dir;
2901
2902 static void sysfs_display_ring(void *head, int size, int extend_desc,
2903                                struct seq_file *seq)
2904 {
2905         int i;
2906         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
2907         struct dma_desc *p = (struct dma_desc *)head;
2908
2909         for (i = 0; i < size; i++) {
2910                 u64 x;
2911                 if (extend_desc) {
2912                         x = *(u64 *) ep;
2913                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2914                                    i, (unsigned int)virt_to_phys(ep),
2915                                    ep->basic.des0, ep->basic.des1,
2916                                    ep->basic.des2, ep->basic.des3);
2917                         ep++;
2918                 } else {
2919                         x = *(u64 *) p;
2920                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2921                                    i, (unsigned int)virt_to_phys(ep),
2922                                    p->des0, p->des1, p->des2, p->des3);
2923                         p++;
2924                 }
2925                 seq_printf(seq, "\n");
2926         }
2927 }
2928
2929 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
2930 {
2931         struct net_device *dev = seq->private;
2932         struct stmmac_priv *priv = netdev_priv(dev);
2933
2934         if (priv->extend_desc) {
2935                 seq_printf(seq, "Extended RX descriptor ring:\n");
2936                 sysfs_display_ring((void *)priv->dma_erx, DMA_RX_SIZE, 1, seq);
2937                 seq_printf(seq, "Extended TX descriptor ring:\n");
2938                 sysfs_display_ring((void *)priv->dma_etx, DMA_TX_SIZE, 1, seq);
2939         } else {
2940                 seq_printf(seq, "RX descriptor ring:\n");
2941                 sysfs_display_ring((void *)priv->dma_rx, DMA_RX_SIZE, 0, seq);
2942                 seq_printf(seq, "TX descriptor ring:\n");
2943                 sysfs_display_ring((void *)priv->dma_tx, DMA_TX_SIZE, 0, seq);
2944         }
2945
2946         return 0;
2947 }
2948
2949 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
2950 {
2951         return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
2952 }
2953
2954 static const struct file_operations stmmac_rings_status_fops = {
2955         .owner = THIS_MODULE,
2956         .open = stmmac_sysfs_ring_open,
2957         .read = seq_read,
2958         .llseek = seq_lseek,
2959         .release = single_release,
2960 };
2961
2962 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
2963 {
2964         struct net_device *dev = seq->private;
2965         struct stmmac_priv *priv = netdev_priv(dev);
2966
2967         if (!priv->hw_cap_support) {
2968                 seq_printf(seq, "DMA HW features not supported\n");
2969                 return 0;
2970         }
2971
2972         seq_printf(seq, "==============================\n");
2973         seq_printf(seq, "\tDMA HW features\n");
2974         seq_printf(seq, "==============================\n");
2975
2976         seq_printf(seq, "\t10/100 Mbps %s\n",
2977                    (priv->dma_cap.mbps_10_100) ? "Y" : "N");
2978         seq_printf(seq, "\t1000 Mbps %s\n",
2979                    (priv->dma_cap.mbps_1000) ? "Y" : "N");
2980         seq_printf(seq, "\tHalf duple %s\n",
2981                    (priv->dma_cap.half_duplex) ? "Y" : "N");
2982         seq_printf(seq, "\tHash Filter: %s\n",
2983                    (priv->dma_cap.hash_filter) ? "Y" : "N");
2984         seq_printf(seq, "\tMultiple MAC address registers: %s\n",
2985                    (priv->dma_cap.multi_addr) ? "Y" : "N");
2986         seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
2987                    (priv->dma_cap.pcs) ? "Y" : "N");
2988         seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
2989                    (priv->dma_cap.sma_mdio) ? "Y" : "N");
2990         seq_printf(seq, "\tPMT Remote wake up: %s\n",
2991                    (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
2992         seq_printf(seq, "\tPMT Magic Frame: %s\n",
2993                    (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
2994         seq_printf(seq, "\tRMON module: %s\n",
2995                    (priv->dma_cap.rmon) ? "Y" : "N");
2996         seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
2997                    (priv->dma_cap.time_stamp) ? "Y" : "N");
2998         seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
2999                    (priv->dma_cap.atime_stamp) ? "Y" : "N");
3000         seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
3001                    (priv->dma_cap.eee) ? "Y" : "N");
3002         seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
3003         seq_printf(seq, "\tChecksum Offload in TX: %s\n",
3004                    (priv->dma_cap.tx_coe) ? "Y" : "N");
3005         if (priv->synopsys_id >= DWMAC_CORE_4_00) {
3006                 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n",
3007                            (priv->dma_cap.rx_coe) ? "Y" : "N");
3008         } else {
3009                 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
3010                            (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
3011                 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
3012                            (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
3013         }
3014         seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
3015                    (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
3016         seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
3017                    priv->dma_cap.number_rx_channel);
3018         seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
3019                    priv->dma_cap.number_tx_channel);
3020         seq_printf(seq, "\tEnhanced descriptors: %s\n",
3021                    (priv->dma_cap.enh_desc) ? "Y" : "N");
3022
3023         return 0;
3024 }
3025
3026 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
3027 {
3028         return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
3029 }
3030
3031 static const struct file_operations stmmac_dma_cap_fops = {
3032         .owner = THIS_MODULE,
3033         .open = stmmac_sysfs_dma_cap_open,
3034         .read = seq_read,
3035         .llseek = seq_lseek,
3036         .release = single_release,
3037 };
3038
3039 static int stmmac_init_fs(struct net_device *dev)
3040 {
3041         struct stmmac_priv *priv = netdev_priv(dev);
3042
3043         /* Create per netdev entries */
3044         priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
3045
3046         if (!priv->dbgfs_dir || IS_ERR(priv->dbgfs_dir)) {
3047                 pr_err("ERROR %s/%s, debugfs create directory failed\n",
3048                        STMMAC_RESOURCE_NAME, dev->name);
3049
3050                 return -ENOMEM;
3051         }
3052
3053         /* Entry to report DMA RX/TX rings */
3054         priv->dbgfs_rings_status =
3055                 debugfs_create_file("descriptors_status", S_IRUGO,
3056                                     priv->dbgfs_dir, dev,
3057                                     &stmmac_rings_status_fops);
3058
3059         if (!priv->dbgfs_rings_status || IS_ERR(priv->dbgfs_rings_status)) {
3060                 pr_info("ERROR creating stmmac ring debugfs file\n");
3061                 debugfs_remove_recursive(priv->dbgfs_dir);
3062
3063                 return -ENOMEM;
3064         }
3065
3066         /* Entry to report the DMA HW features */
3067         priv->dbgfs_dma_cap = debugfs_create_file("dma_cap", S_IRUGO,
3068                                             priv->dbgfs_dir,
3069                                             dev, &stmmac_dma_cap_fops);
3070
3071         if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) {
3072                 pr_info("ERROR creating stmmac MMC debugfs file\n");
3073                 debugfs_remove_recursive(priv->dbgfs_dir);
3074
3075                 return -ENOMEM;
3076         }
3077
3078         return 0;
3079 }
3080
3081 static void stmmac_exit_fs(struct net_device *dev)
3082 {
3083         struct stmmac_priv *priv = netdev_priv(dev);
3084
3085         debugfs_remove_recursive(priv->dbgfs_dir);
3086 }
3087 #endif /* CONFIG_DEBUG_FS */
3088
3089 static const struct net_device_ops stmmac_netdev_ops = {
3090         .ndo_open = stmmac_open,
3091         .ndo_start_xmit = stmmac_xmit,
3092         .ndo_stop = stmmac_release,
3093         .ndo_change_mtu = stmmac_change_mtu,
3094         .ndo_fix_features = stmmac_fix_features,
3095         .ndo_set_features = stmmac_set_features,
3096         .ndo_set_rx_mode = stmmac_set_rx_mode,
3097         .ndo_tx_timeout = stmmac_tx_timeout,
3098         .ndo_do_ioctl = stmmac_ioctl,
3099 #ifdef CONFIG_NET_POLL_CONTROLLER
3100         .ndo_poll_controller = stmmac_poll_controller,
3101 #endif
3102         .ndo_set_mac_address = eth_mac_addr,
3103 };
3104
3105 /**
3106  *  stmmac_hw_init - Init the MAC device
3107  *  @priv: driver private structure
3108  *  Description: this function is to configure the MAC device according to
3109  *  some platform parameters or the HW capability register. It prepares the
3110  *  driver to use either ring or chain modes and to setup either enhanced or
3111  *  normal descriptors.
3112  */
3113 static int stmmac_hw_init(struct stmmac_priv *priv)
3114 {
3115         struct mac_device_info *mac;
3116
3117         /* Identify the MAC HW device */
3118         if (priv->plat->has_gmac) {
3119                 priv->dev->priv_flags |= IFF_UNICAST_FLT;
3120                 mac = dwmac1000_setup(priv->ioaddr,
3121                                       priv->plat->multicast_filter_bins,
3122                                       priv->plat->unicast_filter_entries,
3123                                       &priv->synopsys_id);
3124         } else if (priv->plat->has_gmac4) {
3125                 priv->dev->priv_flags |= IFF_UNICAST_FLT;
3126                 mac = dwmac4_setup(priv->ioaddr,
3127                                    priv->plat->multicast_filter_bins,
3128                                    priv->plat->unicast_filter_entries,
3129                                    &priv->synopsys_id);
3130         } else {
3131                 mac = dwmac100_setup(priv->ioaddr, &priv->synopsys_id);
3132         }
3133         if (!mac)
3134                 return -ENOMEM;
3135
3136         priv->hw = mac;
3137
3138         /* To use the chained or ring mode */
3139         if (priv->synopsys_id >= DWMAC_CORE_4_00) {
3140                 priv->hw->mode = &dwmac4_ring_mode_ops;
3141         } else {
3142                 if (chain_mode) {
3143                         priv->hw->mode = &chain_mode_ops;
3144                         pr_info(" Chain mode enabled\n");
3145                         priv->mode = STMMAC_CHAIN_MODE;
3146                 } else {
3147                         priv->hw->mode = &ring_mode_ops;
3148                         pr_info(" Ring mode enabled\n");
3149                         priv->mode = STMMAC_RING_MODE;
3150                 }
3151         }
3152
3153         /* Get the HW capability (new GMAC newer than 3.50a) */
3154         priv->hw_cap_support = stmmac_get_hw_features(priv);
3155         if (priv->hw_cap_support) {
3156                 pr_info(" DMA HW capability register supported");
3157
3158                 /* We can override some gmac/dma configuration fields: e.g.
3159                  * enh_desc, tx_coe (e.g. that are passed through the
3160                  * platform) with the values from the HW capability
3161                  * register (if supported).
3162                  */
3163                 priv->plat->enh_desc = priv->dma_cap.enh_desc;
3164                 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
3165                 priv->hw->pmt = priv->plat->pmt;
3166
3167                 /* TXCOE doesn't work in thresh DMA mode */
3168                 if (priv->plat->force_thresh_dma_mode)
3169                         priv->plat->tx_coe = 0;
3170                 else
3171                         priv->plat->tx_coe = priv->dma_cap.tx_coe;
3172
3173                 /* In case of GMAC4 rx_coe is from HW cap register. */
3174                 priv->plat->rx_coe = priv->dma_cap.rx_coe;
3175
3176                 if (priv->dma_cap.rx_coe_type2)
3177                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
3178                 else if (priv->dma_cap.rx_coe_type1)
3179                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
3180
3181         } else
3182                 pr_info(" No HW DMA feature register supported");
3183
3184         /* To use alternate (extended), normal or GMAC4 descriptor structures */
3185         if (priv->synopsys_id >= DWMAC_CORE_4_00)
3186                 priv->hw->desc = &dwmac4_desc_ops;
3187         else
3188                 stmmac_selec_desc_mode(priv);
3189
3190         if (priv->plat->rx_coe) {
3191                 priv->hw->rx_csum = priv->plat->rx_coe;
3192                 pr_info(" RX Checksum Offload Engine supported\n");
3193                 if (priv->synopsys_id < DWMAC_CORE_4_00)
3194                         pr_info("\tCOE Type %d\n", priv->hw->rx_csum);
3195         }
3196         if (priv->plat->tx_coe)
3197                 pr_info(" TX Checksum insertion supported\n");
3198
3199         if (priv->plat->pmt) {
3200                 pr_info(" Wake-Up On Lan supported\n");
3201                 device_set_wakeup_capable(priv->device, 1);
3202         }
3203
3204         if (priv->dma_cap.tsoen)
3205                 pr_info(" TSO supported\n");
3206
3207         return 0;
3208 }
3209
3210 /**
3211  * stmmac_dvr_probe
3212  * @device: device pointer
3213  * @plat_dat: platform data pointer
3214  * @res: stmmac resource pointer
3215  * Description: this is the main probe function used to
3216  * call the alloc_etherdev, allocate the priv structure.
3217  * Return:
3218  * returns 0 on success, otherwise errno.
3219  */
3220 int stmmac_dvr_probe(struct device *device,
3221                      struct plat_stmmacenet_data *plat_dat,
3222                      struct stmmac_resources *res)
3223 {
3224         int ret = 0;
3225         struct net_device *ndev = NULL;
3226         struct stmmac_priv *priv;
3227
3228         ndev = alloc_etherdev(sizeof(struct stmmac_priv));
3229         if (!ndev)
3230                 return -ENOMEM;
3231
3232         SET_NETDEV_DEV(ndev, device);
3233
3234         priv = netdev_priv(ndev);
3235         priv->device = device;
3236         priv->dev = ndev;
3237
3238         stmmac_set_ethtool_ops(ndev);
3239         priv->pause = pause;
3240         priv->plat = plat_dat;
3241         priv->ioaddr = res->addr;
3242         priv->dev->base_addr = (unsigned long)res->addr;
3243
3244         priv->dev->irq = res->irq;
3245         priv->wol_irq = res->wol_irq;
3246         priv->lpi_irq = res->lpi_irq;
3247
3248         if (res->mac)
3249                 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN);
3250
3251         dev_set_drvdata(device, priv->dev);
3252
3253         /* Verify driver arguments */
3254         stmmac_verify_args();
3255
3256         /* Override with kernel parameters if supplied XXX CRS XXX
3257          * this needs to have multiple instances
3258          */
3259         if ((phyaddr >= 0) && (phyaddr <= 31))
3260                 priv->plat->phy_addr = phyaddr;
3261
3262         priv->stmmac_clk = devm_clk_get(priv->device, STMMAC_RESOURCE_NAME);
3263         if (IS_ERR(priv->stmmac_clk)) {
3264                 dev_warn(priv->device, "%s: warning: cannot get CSR clock\n",
3265                          __func__);
3266                 /* If failed to obtain stmmac_clk and specific clk_csr value
3267                  * is NOT passed from the platform, probe fail.
3268                  */
3269                 if (!priv->plat->clk_csr) {
3270                         ret = PTR_ERR(priv->stmmac_clk);
3271                         goto error_clk_get;
3272                 } else {
3273                         priv->stmmac_clk = NULL;
3274                 }
3275         }
3276         clk_prepare_enable(priv->stmmac_clk);
3277
3278         priv->pclk = devm_clk_get(priv->device, "pclk");
3279         if (IS_ERR(priv->pclk)) {
3280                 if (PTR_ERR(priv->pclk) == -EPROBE_DEFER) {
3281                         ret = -EPROBE_DEFER;
3282                         goto error_pclk_get;
3283                 }
3284                 priv->pclk = NULL;
3285         }
3286         clk_prepare_enable(priv->pclk);
3287
3288         priv->stmmac_rst = devm_reset_control_get(priv->device,
3289                                                   STMMAC_RESOURCE_NAME);
3290         if (IS_ERR(priv->stmmac_rst)) {
3291                 if (PTR_ERR(priv->stmmac_rst) == -EPROBE_DEFER) {
3292                         ret = -EPROBE_DEFER;
3293                         goto error_hw_init;
3294                 }
3295                 dev_info(priv->device, "no reset control found\n");
3296                 priv->stmmac_rst = NULL;
3297         }
3298         if (priv->stmmac_rst)
3299                 reset_control_deassert(priv->stmmac_rst);
3300
3301         /* Init MAC and get the capabilities */
3302         ret = stmmac_hw_init(priv);
3303         if (ret)
3304                 goto error_hw_init;
3305
3306         ndev->netdev_ops = &stmmac_netdev_ops;
3307
3308         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
3309                             NETIF_F_RXCSUM;
3310
3311         if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
3312                 ndev->hw_features |= NETIF_F_TSO;
3313                 priv->tso = true;
3314                 pr_info(" TSO feature enabled\n");
3315         }
3316         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
3317         ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
3318 #ifdef STMMAC_VLAN_TAG_USED
3319         /* Both mac100 and gmac support receive VLAN tag detection */
3320         ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3321 #endif
3322         priv->msg_enable = netif_msg_init(debug, default_msg_level);
3323
3324         if (flow_ctrl)
3325                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
3326
3327         /* Rx Watchdog is available in the COREs newer than the 3.40.
3328          * In some case, for example on bugged HW this feature
3329          * has to be disable and this can be done by passing the
3330          * riwt_off field from the platform.
3331          */
3332         if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
3333                 priv->use_riwt = 1;
3334                 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
3335         }
3336
3337         netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
3338
3339         spin_lock_init(&priv->lock);
3340         spin_lock_init(&priv->tx_lock);
3341
3342         ret = register_netdev(ndev);
3343         if (ret) {
3344                 pr_err("%s: ERROR %i registering the device\n", __func__, ret);
3345                 goto error_netdev_register;
3346         }
3347
3348         /* If a specific clk_csr value is passed from the platform
3349          * this means that the CSR Clock Range selection cannot be
3350          * changed at run-time and it is fixed. Viceversa the driver'll try to
3351          * set the MDC clock dynamically according to the csr actual
3352          * clock input.
3353          */
3354         if (!priv->plat->clk_csr)
3355                 stmmac_clk_csr_set(priv);
3356         else
3357                 priv->clk_csr = priv->plat->clk_csr;
3358
3359         stmmac_check_pcs_mode(priv);
3360
3361         if (priv->hw->pcs != STMMAC_PCS_RGMII  &&
3362             priv->hw->pcs != STMMAC_PCS_TBI &&
3363             priv->hw->pcs != STMMAC_PCS_RTBI) {
3364                 /* MDIO bus Registration */
3365                 ret = stmmac_mdio_register(ndev);
3366                 if (ret < 0) {
3367                         pr_debug("%s: MDIO bus (id: %d) registration failed",
3368                                  __func__, priv->plat->bus_id);
3369                         goto error_mdio_register;
3370                 }
3371         }
3372
3373         return 0;
3374
3375 error_mdio_register:
3376         unregister_netdev(ndev);
3377 error_netdev_register:
3378         netif_napi_del(&priv->napi);
3379 error_hw_init:
3380         clk_disable_unprepare(priv->pclk);
3381 error_pclk_get:
3382         clk_disable_unprepare(priv->stmmac_clk);
3383 error_clk_get:
3384         free_netdev(ndev);
3385
3386         return ret;
3387 }
3388 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
3389
3390 /**
3391  * stmmac_dvr_remove
3392  * @dev: device pointer
3393  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
3394  * changes the link status, releases the DMA descriptor rings.
3395  */
3396 int stmmac_dvr_remove(struct device *dev)
3397 {
3398         struct net_device *ndev = dev_get_drvdata(dev);
3399         struct stmmac_priv *priv = netdev_priv(ndev);
3400
3401         pr_info("%s:\n\tremoving driver", __func__);
3402
3403         priv->hw->dma->stop_rx(priv->ioaddr);
3404         priv->hw->dma->stop_tx(priv->ioaddr);
3405
3406         stmmac_set_mac(priv->ioaddr, false);
3407         netif_carrier_off(ndev);
3408         unregister_netdev(ndev);
3409         of_node_put(priv->plat->phy_node);
3410         if (priv->stmmac_rst)
3411                 reset_control_assert(priv->stmmac_rst);
3412         clk_disable_unprepare(priv->pclk);
3413         clk_disable_unprepare(priv->stmmac_clk);
3414         if (priv->hw->pcs != STMMAC_PCS_RGMII &&
3415             priv->hw->pcs != STMMAC_PCS_TBI &&
3416             priv->hw->pcs != STMMAC_PCS_RTBI)
3417                 stmmac_mdio_unregister(ndev);
3418         free_netdev(ndev);
3419
3420         return 0;
3421 }
3422 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
3423
3424 /**
3425  * stmmac_suspend - suspend callback
3426  * @dev: device pointer
3427  * Description: this is the function to suspend the device and it is called
3428  * by the platform driver to stop the network queue, release the resources,
3429  * program the PMT register (for WoL), clean and release driver resources.
3430  */
3431 int stmmac_suspend(struct device *dev)
3432 {
3433         struct net_device *ndev = dev_get_drvdata(dev);
3434         struct stmmac_priv *priv = netdev_priv(ndev);
3435         unsigned long flags;
3436
3437         if (!ndev || !netif_running(ndev))
3438                 return 0;
3439
3440         if (priv->phydev)
3441                 phy_stop(priv->phydev);
3442
3443         spin_lock_irqsave(&priv->lock, flags);
3444
3445         netif_device_detach(ndev);
3446         netif_stop_queue(ndev);
3447
3448         napi_disable(&priv->napi);
3449
3450         /* Stop TX/RX DMA */
3451         priv->hw->dma->stop_tx(priv->ioaddr);
3452         priv->hw->dma->stop_rx(priv->ioaddr);
3453
3454         /* Enable Power down mode by programming the PMT regs */
3455         if (device_may_wakeup(priv->device)) {
3456                 priv->hw->mac->pmt(priv->hw, priv->wolopts);
3457                 priv->irq_wake = 1;
3458         } else {
3459                 stmmac_set_mac(priv->ioaddr, false);
3460                 pinctrl_pm_select_sleep_state(priv->device);
3461                 /* Disable clock in case of PWM is off */
3462                 clk_disable(priv->pclk);
3463                 clk_disable(priv->stmmac_clk);
3464         }
3465         spin_unlock_irqrestore(&priv->lock, flags);
3466
3467         priv->oldlink = 0;
3468         priv->speed = 0;
3469         priv->oldduplex = -1;
3470         return 0;
3471 }
3472 EXPORT_SYMBOL_GPL(stmmac_suspend);
3473
3474 /**
3475  * stmmac_resume - resume callback
3476  * @dev: device pointer
3477  * Description: when resume this function is invoked to setup the DMA and CORE
3478  * in a usable state.
3479  */
3480 int stmmac_resume(struct device *dev)
3481 {
3482         struct net_device *ndev = dev_get_drvdata(dev);
3483         struct stmmac_priv *priv = netdev_priv(ndev);
3484         unsigned long flags;
3485
3486         if (!netif_running(ndev))
3487                 return 0;
3488
3489         /* Power Down bit, into the PM register, is cleared
3490          * automatically as soon as a magic packet or a Wake-up frame
3491          * is received. Anyway, it's better to manually clear
3492          * this bit because it can generate problems while resuming
3493          * from another devices (e.g. serial console).
3494          */
3495         if (device_may_wakeup(priv->device)) {
3496                 spin_lock_irqsave(&priv->lock, flags);
3497                 priv->hw->mac->pmt(priv->hw, 0);
3498                 spin_unlock_irqrestore(&priv->lock, flags);
3499                 priv->irq_wake = 0;
3500         } else {
3501                 pinctrl_pm_select_default_state(priv->device);
3502                 /* enable the clk prevously disabled */
3503                 clk_enable(priv->stmmac_clk);
3504                 clk_enable(priv->pclk);
3505                 /* reset the phy so that it's ready */
3506                 if (priv->mii)
3507                         stmmac_mdio_reset(priv->mii);
3508         }
3509
3510         netif_device_attach(ndev);
3511
3512         spin_lock_irqsave(&priv->lock, flags);
3513
3514         priv->cur_rx = 0;
3515         priv->dirty_rx = 0;
3516         priv->dirty_tx = 0;
3517         priv->cur_tx = 0;
3518         /* reset private mss value to force mss context settings at
3519          * next tso xmit (only used for gmac4).
3520          */
3521         priv->mss = 0;
3522
3523         stmmac_clear_descriptors(priv);
3524
3525         stmmac_hw_setup(ndev, false);
3526         stmmac_init_tx_coalesce(priv);
3527         stmmac_set_rx_mode(ndev);
3528
3529         napi_enable(&priv->napi);
3530
3531         netif_start_queue(ndev);
3532
3533         spin_unlock_irqrestore(&priv->lock, flags);
3534
3535         if (priv->phydev)
3536                 phy_start(priv->phydev);
3537
3538         return 0;
3539 }
3540 EXPORT_SYMBOL_GPL(stmmac_resume);
3541
3542 #ifndef MODULE
3543 static int __init stmmac_cmdline_opt(char *str)
3544 {
3545         char *opt;
3546
3547         if (!str || !*str)
3548                 return -EINVAL;
3549         while ((opt = strsep(&str, ",")) != NULL) {
3550                 if (!strncmp(opt, "debug:", 6)) {
3551                         if (kstrtoint(opt + 6, 0, &debug))
3552                                 goto err;
3553                 } else if (!strncmp(opt, "phyaddr:", 8)) {
3554                         if (kstrtoint(opt + 8, 0, &phyaddr))
3555                                 goto err;
3556                 } else if (!strncmp(opt, "buf_sz:", 7)) {
3557                         if (kstrtoint(opt + 7, 0, &buf_sz))
3558                                 goto err;
3559                 } else if (!strncmp(opt, "tc:", 3)) {
3560                         if (kstrtoint(opt + 3, 0, &tc))
3561                                 goto err;
3562                 } else if (!strncmp(opt, "watchdog:", 9)) {
3563                         if (kstrtoint(opt + 9, 0, &watchdog))
3564                                 goto err;
3565                 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
3566                         if (kstrtoint(opt + 10, 0, &flow_ctrl))
3567                                 goto err;
3568                 } else if (!strncmp(opt, "pause:", 6)) {
3569                         if (kstrtoint(opt + 6, 0, &pause))
3570                                 goto err;
3571                 } else if (!strncmp(opt, "eee_timer:", 10)) {
3572                         if (kstrtoint(opt + 10, 0, &eee_timer))
3573                                 goto err;
3574                 } else if (!strncmp(opt, "chain_mode:", 11)) {
3575                         if (kstrtoint(opt + 11, 0, &chain_mode))
3576                                 goto err;
3577                 }
3578         }
3579         return 0;
3580
3581 err:
3582         pr_err("%s: ERROR broken module parameter conversion", __func__);
3583         return -EINVAL;
3584 }
3585
3586 __setup("stmmaceth=", stmmac_cmdline_opt);
3587 #endif /* MODULE */
3588
3589 static int __init stmmac_init(void)
3590 {
3591 #ifdef CONFIG_DEBUG_FS
3592         /* Create debugfs main directory if it doesn't exist yet */
3593         if (!stmmac_fs_dir) {
3594                 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
3595
3596                 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
3597                         pr_err("ERROR %s, debugfs create directory failed\n",
3598                                STMMAC_RESOURCE_NAME);
3599
3600                         return -ENOMEM;
3601                 }
3602         }
3603 #endif
3604
3605         return 0;
3606 }
3607
3608 static void __exit stmmac_exit(void)
3609 {
3610 #ifdef CONFIG_DEBUG_FS
3611         debugfs_remove_recursive(stmmac_fs_dir);
3612 #endif
3613 }
3614
3615 module_init(stmmac_init)
3616 module_exit(stmmac_exit)
3617
3618 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
3619 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
3620 MODULE_LICENSE("GPL");