1 /*******************************************************************************
2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3 ST Ethernet IPs are built around a Synopsys IP Core.
5 Copyright(C) 2007-2011 STMicroelectronics Ltd
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
25 Documentation available at:
26 http://www.stlinux.com
28 https://bugzilla.stlinux.com/
29 *******************************************************************************/
31 #include <linux/clk.h>
32 #include <linux/kernel.h>
33 #include <linux/interrupt.h>
35 #include <linux/tcp.h>
36 #include <linux/skbuff.h>
37 #include <linux/ethtool.h>
38 #include <linux/if_ether.h>
39 #include <linux/crc32.h>
40 #include <linux/mii.h>
42 #include <linux/if_vlan.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/slab.h>
45 #include <linux/prefetch.h>
46 #include <linux/pinctrl/consumer.h>
47 #ifdef CONFIG_DEBUG_FS
48 #include <linux/debugfs.h>
49 #include <linux/seq_file.h>
50 #endif /* CONFIG_DEBUG_FS */
51 #include <linux/net_tstamp.h>
52 #include "stmmac_ptp.h"
54 #include <linux/reset.h>
55 #include <linux/of_mdio.h>
56 #include "dwmac1000.h"
58 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
59 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1)
61 /* Module parameters */
63 static int watchdog = TX_TIMEO;
64 module_param(watchdog, int, S_IRUGO | S_IWUSR);
65 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
67 static int debug = -1;
68 module_param(debug, int, S_IRUGO | S_IWUSR);
69 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
71 static int phyaddr = -1;
72 module_param(phyaddr, int, S_IRUGO);
73 MODULE_PARM_DESC(phyaddr, "Physical device address");
75 #define STMMAC_TX_THRESH (DMA_TX_SIZE / 4)
76 #define STMMAC_RX_THRESH (DMA_RX_SIZE / 4)
78 static int flow_ctrl = FLOW_OFF;
79 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
80 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
82 static int pause = PAUSE_TIME;
83 module_param(pause, int, S_IRUGO | S_IWUSR);
84 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
87 static int tc = TC_DEFAULT;
88 module_param(tc, int, S_IRUGO | S_IWUSR);
89 MODULE_PARM_DESC(tc, "DMA threshold control value");
91 #define DEFAULT_BUFSIZE 1536
92 static int buf_sz = DEFAULT_BUFSIZE;
93 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
94 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
96 #define STMMAC_RX_COPYBREAK 256
98 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
99 NETIF_MSG_LINK | NETIF_MSG_IFUP |
100 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
102 #define STMMAC_DEFAULT_LPI_TIMER 1000
103 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
104 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
105 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
106 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
108 /* By default the driver will use the ring mode to manage tx and rx descriptors
109 * but passing this value so user can force to use the chain instead of the ring
111 static unsigned int chain_mode;
112 module_param(chain_mode, int, S_IRUGO);
113 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
115 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
117 #ifdef CONFIG_DEBUG_FS
118 static int stmmac_init_fs(struct net_device *dev);
119 static void stmmac_exit_fs(struct net_device *dev);
122 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
125 * stmmac_verify_args - verify the driver parameters.
126 * Description: it checks the driver parameters and set a default in case of
129 static void stmmac_verify_args(void)
131 if (unlikely(watchdog < 0))
133 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
134 buf_sz = DEFAULT_BUFSIZE;
135 if (unlikely(flow_ctrl > 1))
136 flow_ctrl = FLOW_AUTO;
137 else if (likely(flow_ctrl < 0))
138 flow_ctrl = FLOW_OFF;
139 if (unlikely((pause < 0) || (pause > 0xffff)))
142 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
146 * stmmac_clk_csr_set - dynamically set the MDC clock
147 * @priv: driver private structure
148 * Description: this is to dynamically set the MDC clock according to the csr
151 * If a specific clk_csr value is passed from the platform
152 * this means that the CSR Clock Range selection cannot be
153 * changed at run-time and it is fixed (as reported in the driver
154 * documentation). Viceversa the driver will try to set the MDC
155 * clock dynamically according to the actual clock input.
157 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
161 clk_rate = clk_get_rate(priv->stmmac_clk);
163 /* Platform provided default clk_csr would be assumed valid
164 * for all other cases except for the below mentioned ones.
165 * For values higher than the IEEE 802.3 specified frequency
166 * we can not estimate the proper divider as it is not known
167 * the frequency of clk_csr_i. So we do not change the default
170 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
171 if (clk_rate < CSR_F_35M)
172 priv->clk_csr = STMMAC_CSR_20_35M;
173 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
174 priv->clk_csr = STMMAC_CSR_35_60M;
175 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
176 priv->clk_csr = STMMAC_CSR_60_100M;
177 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
178 priv->clk_csr = STMMAC_CSR_100_150M;
179 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
180 priv->clk_csr = STMMAC_CSR_150_250M;
181 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
182 priv->clk_csr = STMMAC_CSR_250_300M;
186 static void print_pkt(unsigned char *buf, int len)
188 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
189 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
192 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
196 if (priv->dirty_tx > priv->cur_tx)
197 avail = priv->dirty_tx - priv->cur_tx - 1;
199 avail = DMA_TX_SIZE - priv->cur_tx + priv->dirty_tx - 1;
204 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv)
208 if (priv->dirty_rx <= priv->cur_rx)
209 dirty = priv->cur_rx - priv->dirty_rx;
211 dirty = DMA_RX_SIZE - priv->dirty_rx + priv->cur_rx;
217 * stmmac_hw_fix_mac_speed - callback for speed selection
218 * @priv: driver private structure
219 * Description: on some platforms (e.g. ST), some HW system configuraton
220 * registers have to be set according to the link speed negotiated.
222 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
224 struct phy_device *phydev = priv->phydev;
226 if (likely(priv->plat->fix_mac_speed))
227 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed);
231 * stmmac_enable_eee_mode - check and enter in LPI mode
232 * @priv: driver private structure
233 * Description: this function is to verify and enter in LPI mode in case of
236 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
238 /* Check and enter in LPI mode */
239 if ((priv->dirty_tx == priv->cur_tx) &&
240 (priv->tx_path_in_lpi_mode == false))
241 priv->hw->mac->set_eee_mode(priv->hw);
245 * stmmac_disable_eee_mode - disable and exit from LPI mode
246 * @priv: driver private structure
247 * Description: this function is to exit and disable EEE in case of
248 * LPI state is true. This is called by the xmit.
250 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
252 priv->hw->mac->reset_eee_mode(priv->hw);
253 del_timer_sync(&priv->eee_ctrl_timer);
254 priv->tx_path_in_lpi_mode = false;
258 * stmmac_eee_ctrl_timer - EEE TX SW timer.
261 * if there is no data transfer and if we are not in LPI state,
262 * then MAC Transmitter can be moved to LPI state.
264 static void stmmac_eee_ctrl_timer(unsigned long arg)
266 struct stmmac_priv *priv = (struct stmmac_priv *)arg;
268 stmmac_enable_eee_mode(priv);
269 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
273 * stmmac_eee_init - init EEE
274 * @priv: driver private structure
276 * if the GMAC supports the EEE (from the HW cap reg) and the phy device
277 * can also manage EEE, this function enable the LPI state and start related
280 bool stmmac_eee_init(struct stmmac_priv *priv)
285 /* Using PCS we cannot dial with the phy registers at this stage
286 * so we do not support extra feature like EEE.
288 if ((priv->hw->pcs == STMMAC_PCS_RGMII) ||
289 (priv->hw->pcs == STMMAC_PCS_TBI) ||
290 (priv->hw->pcs == STMMAC_PCS_RTBI))
293 /* MAC core supports the EEE feature. */
294 if (priv->dma_cap.eee) {
295 int tx_lpi_timer = priv->tx_lpi_timer;
297 /* Check if the PHY supports EEE */
298 if (phy_init_eee(priv->phydev, 1)) {
299 /* To manage at run-time if the EEE cannot be supported
300 * anymore (for example because the lp caps have been
302 * In that case the driver disable own timers.
304 spin_lock_irqsave(&priv->lock, flags);
305 if (priv->eee_active) {
306 pr_debug("stmmac: disable EEE\n");
307 del_timer_sync(&priv->eee_ctrl_timer);
308 priv->hw->mac->set_eee_timer(priv->hw, 0,
311 priv->eee_active = 0;
312 spin_unlock_irqrestore(&priv->lock, flags);
315 /* Activate the EEE and start timers */
316 spin_lock_irqsave(&priv->lock, flags);
317 if (!priv->eee_active) {
318 priv->eee_active = 1;
319 setup_timer(&priv->eee_ctrl_timer,
320 stmmac_eee_ctrl_timer,
321 (unsigned long)priv);
322 mod_timer(&priv->eee_ctrl_timer,
323 STMMAC_LPI_T(eee_timer));
325 priv->hw->mac->set_eee_timer(priv->hw,
326 STMMAC_DEFAULT_LIT_LS,
329 /* Set HW EEE according to the speed */
330 priv->hw->mac->set_eee_pls(priv->hw, priv->phydev->link);
333 spin_unlock_irqrestore(&priv->lock, flags);
335 pr_debug("stmmac: Energy-Efficient Ethernet initialized\n");
341 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
342 * @priv: driver private structure
343 * @entry : descriptor index to be used.
344 * @skb : the socket buffer
346 * This function will read timestamp from the descriptor & pass it to stack.
347 * and also perform some sanity checks.
349 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
350 unsigned int entry, struct sk_buff *skb)
352 struct skb_shared_hwtstamps shhwtstamp;
356 if (!priv->hwts_tx_en)
359 /* exit if skb doesn't support hw tstamp */
360 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
364 desc = (priv->dma_etx + entry);
366 desc = (priv->dma_tx + entry);
368 /* check tx tstamp status */
369 if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc))
372 /* get the valid tstamp */
373 ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
375 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
376 shhwtstamp.hwtstamp = ns_to_ktime(ns);
377 /* pass tstamp to stack */
378 skb_tstamp_tx(skb, &shhwtstamp);
383 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
384 * @priv: driver private structure
385 * @entry : descriptor index to be used.
386 * @skb : the socket buffer
388 * This function will read received packet's timestamp from the descriptor
389 * and pass it to stack. It also perform some sanity checks.
391 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv,
392 unsigned int entry, struct sk_buff *skb)
394 struct skb_shared_hwtstamps *shhwtstamp = NULL;
398 if (!priv->hwts_rx_en)
402 desc = (priv->dma_erx + entry);
404 desc = (priv->dma_rx + entry);
406 /* exit if rx tstamp is not valid */
407 if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts))
410 /* get valid tstamp */
411 ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
412 shhwtstamp = skb_hwtstamps(skb);
413 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
414 shhwtstamp->hwtstamp = ns_to_ktime(ns);
418 * stmmac_hwtstamp_ioctl - control hardware timestamping.
419 * @dev: device pointer.
420 * @ifr: An IOCTL specefic structure, that can contain a pointer to
421 * a proprietary structure used to pass information to the driver.
423 * This function configures the MAC to enable/disable both outgoing(TX)
424 * and incoming(RX) packets time stamping based on user input.
426 * 0 on success and an appropriate -ve integer on failure.
428 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
430 struct stmmac_priv *priv = netdev_priv(dev);
431 struct hwtstamp_config config;
432 struct timespec64 now;
436 u32 ptp_over_ipv4_udp = 0;
437 u32 ptp_over_ipv6_udp = 0;
438 u32 ptp_over_ethernet = 0;
439 u32 snap_type_sel = 0;
440 u32 ts_master_en = 0;
445 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
446 netdev_alert(priv->dev, "No support for HW time stamping\n");
447 priv->hwts_tx_en = 0;
448 priv->hwts_rx_en = 0;
453 if (copy_from_user(&config, ifr->ifr_data,
454 sizeof(struct hwtstamp_config)))
457 pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
458 __func__, config.flags, config.tx_type, config.rx_filter);
460 /* reserved for future extensions */
464 if (config.tx_type != HWTSTAMP_TX_OFF &&
465 config.tx_type != HWTSTAMP_TX_ON)
469 switch (config.rx_filter) {
470 case HWTSTAMP_FILTER_NONE:
471 /* time stamp no incoming packet at all */
472 config.rx_filter = HWTSTAMP_FILTER_NONE;
475 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
476 /* PTP v1, UDP, any kind of event packet */
477 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
478 /* take time stamp for all event messages */
479 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
481 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
482 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
485 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
486 /* PTP v1, UDP, Sync packet */
487 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
488 /* take time stamp for SYNC messages only */
489 ts_event_en = PTP_TCR_TSEVNTENA;
491 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
492 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
495 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
496 /* PTP v1, UDP, Delay_req packet */
497 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
498 /* take time stamp for Delay_Req messages only */
499 ts_master_en = PTP_TCR_TSMSTRENA;
500 ts_event_en = PTP_TCR_TSEVNTENA;
502 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
503 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
506 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
507 /* PTP v2, UDP, any kind of event packet */
508 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
509 ptp_v2 = PTP_TCR_TSVER2ENA;
510 /* take time stamp for all event messages */
511 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
513 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
514 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
517 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
518 /* PTP v2, UDP, Sync packet */
519 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
520 ptp_v2 = PTP_TCR_TSVER2ENA;
521 /* take time stamp for SYNC messages only */
522 ts_event_en = PTP_TCR_TSEVNTENA;
524 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
525 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
528 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
529 /* PTP v2, UDP, Delay_req packet */
530 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
531 ptp_v2 = PTP_TCR_TSVER2ENA;
532 /* take time stamp for Delay_Req messages only */
533 ts_master_en = PTP_TCR_TSMSTRENA;
534 ts_event_en = PTP_TCR_TSEVNTENA;
536 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
537 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
540 case HWTSTAMP_FILTER_PTP_V2_EVENT:
541 /* PTP v2/802.AS1 any layer, any kind of event packet */
542 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
543 ptp_v2 = PTP_TCR_TSVER2ENA;
544 /* take time stamp for all event messages */
545 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
547 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
548 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
549 ptp_over_ethernet = PTP_TCR_TSIPENA;
552 case HWTSTAMP_FILTER_PTP_V2_SYNC:
553 /* PTP v2/802.AS1, any layer, Sync packet */
554 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
555 ptp_v2 = PTP_TCR_TSVER2ENA;
556 /* take time stamp for SYNC messages only */
557 ts_event_en = PTP_TCR_TSEVNTENA;
559 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
560 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
561 ptp_over_ethernet = PTP_TCR_TSIPENA;
564 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
565 /* PTP v2/802.AS1, any layer, Delay_req packet */
566 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
567 ptp_v2 = PTP_TCR_TSVER2ENA;
568 /* take time stamp for Delay_Req messages only */
569 ts_master_en = PTP_TCR_TSMSTRENA;
570 ts_event_en = PTP_TCR_TSEVNTENA;
572 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
573 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
574 ptp_over_ethernet = PTP_TCR_TSIPENA;
577 case HWTSTAMP_FILTER_ALL:
578 /* time stamp any incoming packet */
579 config.rx_filter = HWTSTAMP_FILTER_ALL;
580 tstamp_all = PTP_TCR_TSENALL;
587 switch (config.rx_filter) {
588 case HWTSTAMP_FILTER_NONE:
589 config.rx_filter = HWTSTAMP_FILTER_NONE;
592 /* PTP v1, UDP, any kind of event packet */
593 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
597 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
598 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
600 if (!priv->hwts_tx_en && !priv->hwts_rx_en)
601 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0);
603 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
604 tstamp_all | ptp_v2 | ptp_over_ethernet |
605 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
606 ts_master_en | snap_type_sel);
607 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value);
609 /* program Sub Second Increment reg */
610 sec_inc = priv->hw->ptp->config_sub_second_increment(
611 priv->ioaddr, priv->clk_ptp_rate);
612 temp = div_u64(1000000000ULL, sec_inc);
614 /* calculate default added value:
616 * addend = (2^32)/freq_div_ratio;
617 * where, freq_div_ratio = 1e9ns/sec_inc
619 temp = (u64)(temp << 32);
620 priv->default_addend = div_u64(temp, priv->clk_ptp_rate);
621 priv->hw->ptp->config_addend(priv->ioaddr,
622 priv->default_addend);
624 /* initialize system time */
625 ktime_get_real_ts64(&now);
627 /* lower 32 bits of tv_sec are safe until y2106 */
628 priv->hw->ptp->init_systime(priv->ioaddr, (u32)now.tv_sec,
632 return copy_to_user(ifr->ifr_data, &config,
633 sizeof(struct hwtstamp_config)) ? -EFAULT : 0;
637 * stmmac_init_ptp - init PTP
638 * @priv: driver private structure
639 * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
640 * This is done by looking at the HW cap. register.
641 * This function also registers the ptp driver.
643 static int stmmac_init_ptp(struct stmmac_priv *priv)
645 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
648 /* Fall-back to main clock in case of no PTP ref is passed */
649 priv->clk_ptp_ref = devm_clk_get(priv->device, "clk_ptp_ref");
650 if (IS_ERR(priv->clk_ptp_ref)) {
651 priv->clk_ptp_rate = clk_get_rate(priv->stmmac_clk);
652 priv->clk_ptp_ref = NULL;
654 clk_prepare_enable(priv->clk_ptp_ref);
655 priv->clk_ptp_rate = clk_get_rate(priv->clk_ptp_ref);
659 if (priv->dma_cap.atime_stamp && priv->extend_desc)
662 if (netif_msg_hw(priv) && priv->dma_cap.time_stamp)
663 pr_debug("IEEE 1588-2002 Time Stamp supported\n");
665 if (netif_msg_hw(priv) && priv->adv_ts)
666 pr_debug("IEEE 1588-2008 Advanced Time Stamp supported\n");
668 priv->hw->ptp = &stmmac_ptp;
669 priv->hwts_tx_en = 0;
670 priv->hwts_rx_en = 0;
672 return stmmac_ptp_register(priv);
675 static void stmmac_release_ptp(struct stmmac_priv *priv)
677 if (priv->clk_ptp_ref)
678 clk_disable_unprepare(priv->clk_ptp_ref);
679 stmmac_ptp_unregister(priv);
683 * stmmac_adjust_link - adjusts the link parameters
684 * @dev: net device structure
685 * Description: this is the helper called by the physical abstraction layer
686 * drivers to communicate the phy link status. According the speed and duplex
687 * this driver can invoke registered glue-logic as well.
688 * It also invoke the eee initialization because it could happen when switch
689 * on different networks (that are eee capable).
691 static void stmmac_adjust_link(struct net_device *dev)
693 struct stmmac_priv *priv = netdev_priv(dev);
694 struct phy_device *phydev = priv->phydev;
697 unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
702 spin_lock_irqsave(&priv->lock, flags);
705 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
707 /* Now we make sure that we can be in full duplex mode.
708 * If not, we operate in half-duplex mode. */
709 if (phydev->duplex != priv->oldduplex) {
711 if (!(phydev->duplex))
712 ctrl &= ~priv->hw->link.duplex;
714 ctrl |= priv->hw->link.duplex;
715 priv->oldduplex = phydev->duplex;
717 /* Flow Control operation */
719 priv->hw->mac->flow_ctrl(priv->hw, phydev->duplex,
722 if (phydev->speed != priv->speed) {
724 switch (phydev->speed) {
726 if (likely((priv->plat->has_gmac) ||
727 (priv->plat->has_gmac4)))
728 ctrl &= ~priv->hw->link.port;
729 stmmac_hw_fix_mac_speed(priv);
733 if (likely((priv->plat->has_gmac) ||
734 (priv->plat->has_gmac4))) {
735 ctrl |= priv->hw->link.port;
736 if (phydev->speed == SPEED_100) {
737 ctrl |= priv->hw->link.speed;
739 ctrl &= ~(priv->hw->link.speed);
742 ctrl &= ~priv->hw->link.port;
744 stmmac_hw_fix_mac_speed(priv);
747 if (netif_msg_link(priv))
748 pr_warn("%s: Speed (%d) not 10/100\n",
749 dev->name, phydev->speed);
753 priv->speed = phydev->speed;
756 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
758 if (!priv->oldlink) {
762 } else if (priv->oldlink) {
766 priv->oldduplex = -1;
769 if (new_state && netif_msg_link(priv))
770 phy_print_status(phydev);
772 spin_unlock_irqrestore(&priv->lock, flags);
774 if (phydev->is_pseudo_fixed_link)
775 /* Stop PHY layer to call the hook to adjust the link in case
776 * of a switch is attached to the stmmac driver.
778 phydev->irq = PHY_IGNORE_INTERRUPT;
780 /* At this stage, init the EEE if supported.
781 * Never called in case of fixed_link.
783 priv->eee_enabled = stmmac_eee_init(priv);
787 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
788 * @priv: driver private structure
789 * Description: this is to verify if the HW supports the PCS.
790 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
791 * configured for the TBI, RTBI, or SGMII PHY interface.
793 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
795 int interface = priv->plat->interface;
797 if (priv->dma_cap.pcs) {
798 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
799 (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
800 (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
801 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
802 pr_debug("STMMAC: PCS RGMII support enable\n");
803 priv->hw->pcs = STMMAC_PCS_RGMII;
804 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
805 pr_debug("STMMAC: PCS SGMII support enable\n");
806 priv->hw->pcs = STMMAC_PCS_SGMII;
812 * stmmac_init_phy - PHY initialization
813 * @dev: net device structure
814 * Description: it initializes the driver's PHY state, and attaches the PHY
819 static int stmmac_init_phy(struct net_device *dev)
821 struct stmmac_priv *priv = netdev_priv(dev);
822 struct phy_device *phydev;
823 char phy_id_fmt[MII_BUS_ID_SIZE + 3];
824 char bus_id[MII_BUS_ID_SIZE];
825 int interface = priv->plat->interface;
826 int max_speed = priv->plat->max_speed;
829 priv->oldduplex = -1;
831 if (priv->plat->phy_node) {
832 phydev = of_phy_connect(dev, priv->plat->phy_node,
833 &stmmac_adjust_link, 0, interface);
835 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
838 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
839 priv->plat->phy_addr);
840 pr_debug("stmmac_init_phy: trying to attach to %s\n",
843 phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link,
847 if (IS_ERR_OR_NULL(phydev)) {
848 pr_err("%s: Could not attach to PHY\n", dev->name);
852 return PTR_ERR(phydev);
855 /* Stop Advertising 1000BASE Capability if interface is not GMII */
856 if ((interface == PHY_INTERFACE_MODE_MII) ||
857 (interface == PHY_INTERFACE_MODE_RMII) ||
858 (max_speed < 1000 && max_speed > 0))
859 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
860 SUPPORTED_1000baseT_Full);
863 * Broken HW is sometimes missing the pull-up resistor on the
864 * MDIO line, which results in reads to non-existent devices returning
865 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
867 * Note: phydev->phy_id is the result of reading the UID PHY registers.
869 if (!priv->plat->phy_node && phydev->phy_id == 0) {
870 phy_disconnect(phydev);
874 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)"
875 " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
877 priv->phydev = phydev;
882 static void stmmac_display_rings(struct stmmac_priv *priv)
884 void *head_rx, *head_tx;
886 if (priv->extend_desc) {
887 head_rx = (void *)priv->dma_erx;
888 head_tx = (void *)priv->dma_etx;
890 head_rx = (void *)priv->dma_rx;
891 head_tx = (void *)priv->dma_tx;
894 /* Display Rx ring */
895 priv->hw->desc->display_ring(head_rx, DMA_RX_SIZE, true);
896 /* Display Tx ring */
897 priv->hw->desc->display_ring(head_tx, DMA_TX_SIZE, false);
900 static int stmmac_set_bfsize(int mtu, int bufsize)
904 if (mtu >= BUF_SIZE_4KiB)
906 else if (mtu >= BUF_SIZE_2KiB)
908 else if (mtu > DEFAULT_BUFSIZE)
911 ret = DEFAULT_BUFSIZE;
917 * stmmac_clear_descriptors - clear descriptors
918 * @priv: driver private structure
919 * Description: this function is called to clear the tx and rx descriptors
920 * in case of both basic and extended descriptors are used.
922 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
926 /* Clear the Rx/Tx descriptors */
927 for (i = 0; i < DMA_RX_SIZE; i++)
928 if (priv->extend_desc)
929 priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic,
930 priv->use_riwt, priv->mode,
931 (i == DMA_RX_SIZE - 1));
933 priv->hw->desc->init_rx_desc(&priv->dma_rx[i],
934 priv->use_riwt, priv->mode,
935 (i == DMA_RX_SIZE - 1));
936 for (i = 0; i < DMA_TX_SIZE; i++)
937 if (priv->extend_desc)
938 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
940 (i == DMA_TX_SIZE - 1));
942 priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
944 (i == DMA_TX_SIZE - 1));
948 * stmmac_init_rx_buffers - init the RX descriptor buffer.
949 * @priv: driver private structure
950 * @p: descriptor pointer
951 * @i: descriptor index
953 * Description: this function is called to allocate a receive buffer, perform
954 * the DMA mapping and init the descriptor.
956 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
961 skb = __netdev_alloc_skb_ip_align(priv->dev, priv->dma_buf_sz, flags);
963 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
966 priv->rx_skbuff[i] = skb;
967 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
970 if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) {
971 pr_err("%s: DMA mapping error\n", __func__);
972 dev_kfree_skb_any(skb);
976 if (priv->synopsys_id >= DWMAC_CORE_4_00)
977 p->des0 = priv->rx_skbuff_dma[i];
979 p->des2 = priv->rx_skbuff_dma[i];
981 if ((priv->hw->mode->init_desc3) &&
982 (priv->dma_buf_sz == BUF_SIZE_16KiB))
983 priv->hw->mode->init_desc3(p);
988 static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i)
990 if (priv->rx_skbuff[i]) {
991 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
992 priv->dma_buf_sz, DMA_FROM_DEVICE);
993 dev_kfree_skb_any(priv->rx_skbuff[i]);
995 priv->rx_skbuff[i] = NULL;
999 * init_dma_desc_rings - init the RX/TX descriptor rings
1000 * @dev: net device structure
1002 * Description: this function initializes the DMA RX/TX descriptors
1003 * and allocates the socket buffers. It suppors the chained and ring
1006 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1009 struct stmmac_priv *priv = netdev_priv(dev);
1010 unsigned int bfsize = 0;
1013 if (priv->hw->mode->set_16kib_bfsize)
1014 bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu);
1016 if (bfsize < BUF_SIZE_16KiB)
1017 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1019 priv->dma_buf_sz = bfsize;
1021 if (netif_msg_probe(priv)) {
1022 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__,
1023 (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy);
1025 /* RX INITIALIZATION */
1026 pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n");
1028 for (i = 0; i < DMA_RX_SIZE; i++) {
1030 if (priv->extend_desc)
1031 p = &((priv->dma_erx + i)->basic);
1033 p = priv->dma_rx + i;
1035 ret = stmmac_init_rx_buffers(priv, p, i, flags);
1037 goto err_init_rx_buffers;
1039 if (netif_msg_probe(priv))
1040 pr_debug("[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
1041 priv->rx_skbuff[i]->data,
1042 (unsigned int)priv->rx_skbuff_dma[i]);
1045 priv->dirty_rx = (unsigned int)(i - DMA_RX_SIZE);
1048 /* Setup the chained descriptor addresses */
1049 if (priv->mode == STMMAC_CHAIN_MODE) {
1050 if (priv->extend_desc) {
1051 priv->hw->mode->init(priv->dma_erx, priv->dma_rx_phy,
1053 priv->hw->mode->init(priv->dma_etx, priv->dma_tx_phy,
1056 priv->hw->mode->init(priv->dma_rx, priv->dma_rx_phy,
1058 priv->hw->mode->init(priv->dma_tx, priv->dma_tx_phy,
1063 /* TX INITIALIZATION */
1064 for (i = 0; i < DMA_TX_SIZE; i++) {
1066 if (priv->extend_desc)
1067 p = &((priv->dma_etx + i)->basic);
1069 p = priv->dma_tx + i;
1071 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
1080 priv->tx_skbuff_dma[i].buf = 0;
1081 priv->tx_skbuff_dma[i].map_as_page = false;
1082 priv->tx_skbuff_dma[i].len = 0;
1083 priv->tx_skbuff_dma[i].last_segment = false;
1084 priv->tx_skbuff[i] = NULL;
1089 netdev_reset_queue(priv->dev);
1091 stmmac_clear_descriptors(priv);
1093 if (netif_msg_hw(priv))
1094 stmmac_display_rings(priv);
1097 err_init_rx_buffers:
1099 stmmac_free_rx_buffers(priv, i);
1103 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
1107 for (i = 0; i < DMA_RX_SIZE; i++)
1108 stmmac_free_rx_buffers(priv, i);
1111 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
1115 for (i = 0; i < DMA_TX_SIZE; i++) {
1118 if (priv->extend_desc)
1119 p = &((priv->dma_etx + i)->basic);
1121 p = priv->dma_tx + i;
1123 if (priv->tx_skbuff_dma[i].buf) {
1124 if (priv->tx_skbuff_dma[i].map_as_page)
1125 dma_unmap_page(priv->device,
1126 priv->tx_skbuff_dma[i].buf,
1127 priv->tx_skbuff_dma[i].len,
1130 dma_unmap_single(priv->device,
1131 priv->tx_skbuff_dma[i].buf,
1132 priv->tx_skbuff_dma[i].len,
1136 if (priv->tx_skbuff[i] != NULL) {
1137 dev_kfree_skb_any(priv->tx_skbuff[i]);
1138 priv->tx_skbuff[i] = NULL;
1139 priv->tx_skbuff_dma[i].buf = 0;
1140 priv->tx_skbuff_dma[i].map_as_page = false;
1146 * alloc_dma_desc_resources - alloc TX/RX resources.
1147 * @priv: private structure
1148 * Description: according to which descriptor can be used (extend or basic)
1149 * this function allocates the resources for TX and RX paths. In case of
1150 * reception, for example, it pre-allocated the RX socket buffer in order to
1151 * allow zero-copy mechanism.
1153 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1157 priv->rx_skbuff_dma = kmalloc_array(DMA_RX_SIZE, sizeof(dma_addr_t),
1159 if (!priv->rx_skbuff_dma)
1162 priv->rx_skbuff = kmalloc_array(DMA_RX_SIZE, sizeof(struct sk_buff *),
1164 if (!priv->rx_skbuff)
1167 priv->tx_skbuff_dma = kmalloc_array(DMA_TX_SIZE,
1168 sizeof(*priv->tx_skbuff_dma),
1170 if (!priv->tx_skbuff_dma)
1171 goto err_tx_skbuff_dma;
1173 priv->tx_skbuff = kmalloc_array(DMA_TX_SIZE, sizeof(struct sk_buff *),
1175 if (!priv->tx_skbuff)
1178 if (priv->extend_desc) {
1179 priv->dma_erx = dma_zalloc_coherent(priv->device, DMA_RX_SIZE *
1187 priv->dma_etx = dma_zalloc_coherent(priv->device, DMA_TX_SIZE *
1192 if (!priv->dma_etx) {
1193 dma_free_coherent(priv->device, DMA_RX_SIZE *
1194 sizeof(struct dma_extended_desc),
1195 priv->dma_erx, priv->dma_rx_phy);
1199 priv->dma_rx = dma_zalloc_coherent(priv->device, DMA_RX_SIZE *
1200 sizeof(struct dma_desc),
1206 priv->dma_tx = dma_zalloc_coherent(priv->device, DMA_TX_SIZE *
1207 sizeof(struct dma_desc),
1210 if (!priv->dma_tx) {
1211 dma_free_coherent(priv->device, DMA_RX_SIZE *
1212 sizeof(struct dma_desc),
1213 priv->dma_rx, priv->dma_rx_phy);
1221 kfree(priv->tx_skbuff);
1223 kfree(priv->tx_skbuff_dma);
1225 kfree(priv->rx_skbuff);
1227 kfree(priv->rx_skbuff_dma);
1231 static void free_dma_desc_resources(struct stmmac_priv *priv)
1233 /* Release the DMA TX/RX socket buffers */
1234 dma_free_rx_skbufs(priv);
1235 dma_free_tx_skbufs(priv);
1237 /* Free DMA regions of consistent memory previously allocated */
1238 if (!priv->extend_desc) {
1239 dma_free_coherent(priv->device,
1240 DMA_TX_SIZE * sizeof(struct dma_desc),
1241 priv->dma_tx, priv->dma_tx_phy);
1242 dma_free_coherent(priv->device,
1243 DMA_RX_SIZE * sizeof(struct dma_desc),
1244 priv->dma_rx, priv->dma_rx_phy);
1246 dma_free_coherent(priv->device, DMA_TX_SIZE *
1247 sizeof(struct dma_extended_desc),
1248 priv->dma_etx, priv->dma_tx_phy);
1249 dma_free_coherent(priv->device, DMA_RX_SIZE *
1250 sizeof(struct dma_extended_desc),
1251 priv->dma_erx, priv->dma_rx_phy);
1253 kfree(priv->rx_skbuff_dma);
1254 kfree(priv->rx_skbuff);
1255 kfree(priv->tx_skbuff_dma);
1256 kfree(priv->tx_skbuff);
1260 * stmmac_dma_operation_mode - HW DMA operation mode
1261 * @priv: driver private structure
1262 * Description: it is used for configuring the DMA operation mode register in
1263 * order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1265 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1267 int rxfifosz = priv->plat->rx_fifo_size;
1269 if (priv->plat->force_thresh_dma_mode)
1270 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc, rxfifosz);
1271 else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1273 * In case of GMAC, SF mode can be enabled
1274 * to perform the TX COE in HW. This depends on:
1275 * 1) TX COE if actually supported
1276 * 2) There is no bugged Jumbo frame support
1277 * that needs to not insert csum in the TDES.
1279 priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE,
1281 priv->xstats.threshold = SF_DMA_MODE;
1283 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE,
1288 * stmmac_tx_clean - to manage the transmission completion
1289 * @priv: driver private structure
1290 * Description: it reclaims the transmit resources after transmission completes.
1292 static void stmmac_tx_clean(struct stmmac_priv *priv)
1294 unsigned int bytes_compl = 0, pkts_compl = 0;
1295 unsigned int entry = priv->dirty_tx;
1297 spin_lock(&priv->tx_lock);
1299 priv->xstats.tx_clean++;
1301 while (entry != priv->cur_tx) {
1302 struct sk_buff *skb = priv->tx_skbuff[entry];
1306 if (priv->extend_desc)
1307 p = (struct dma_desc *)(priv->dma_etx + entry);
1309 p = priv->dma_tx + entry;
1311 status = priv->hw->desc->tx_status(&priv->dev->stats,
1314 /* Check if the descriptor is owned by the DMA */
1315 if (unlikely(status & tx_dma_own))
1318 /* Just consider the last segment and ...*/
1319 if (likely(!(status & tx_not_ls))) {
1320 /* ... verify the status error condition */
1321 if (unlikely(status & tx_err)) {
1322 priv->dev->stats.tx_errors++;
1324 priv->dev->stats.tx_packets++;
1325 priv->xstats.tx_pkt_n++;
1327 stmmac_get_tx_hwtstamp(priv, entry, skb);
1330 if (likely(priv->tx_skbuff_dma[entry].buf)) {
1331 if (priv->tx_skbuff_dma[entry].map_as_page)
1332 dma_unmap_page(priv->device,
1333 priv->tx_skbuff_dma[entry].buf,
1334 priv->tx_skbuff_dma[entry].len,
1337 dma_unmap_single(priv->device,
1338 priv->tx_skbuff_dma[entry].buf,
1339 priv->tx_skbuff_dma[entry].len,
1341 priv->tx_skbuff_dma[entry].buf = 0;
1342 priv->tx_skbuff_dma[entry].len = 0;
1343 priv->tx_skbuff_dma[entry].map_as_page = false;
1346 if (priv->hw->mode->clean_desc3)
1347 priv->hw->mode->clean_desc3(priv, p);
1349 priv->tx_skbuff_dma[entry].last_segment = false;
1350 priv->tx_skbuff_dma[entry].is_jumbo = false;
1352 if (likely(skb != NULL)) {
1354 bytes_compl += skb->len;
1355 dev_consume_skb_any(skb);
1356 priv->tx_skbuff[entry] = NULL;
1359 priv->hw->desc->release_tx_desc(p, priv->mode);
1361 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
1363 priv->dirty_tx = entry;
1365 netdev_completed_queue(priv->dev, pkts_compl, bytes_compl);
1367 if (unlikely(netif_queue_stopped(priv->dev) &&
1368 stmmac_tx_avail(priv) > STMMAC_TX_THRESH)) {
1369 netif_tx_lock(priv->dev);
1370 if (netif_queue_stopped(priv->dev) &&
1371 stmmac_tx_avail(priv) > STMMAC_TX_THRESH) {
1372 if (netif_msg_tx_done(priv))
1373 pr_debug("%s: restart transmit\n", __func__);
1374 netif_wake_queue(priv->dev);
1376 netif_tx_unlock(priv->dev);
1379 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1380 stmmac_enable_eee_mode(priv);
1381 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1383 spin_unlock(&priv->tx_lock);
1386 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv)
1388 priv->hw->dma->enable_dma_irq(priv->ioaddr);
1391 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv)
1393 priv->hw->dma->disable_dma_irq(priv->ioaddr);
1397 * stmmac_tx_err - to manage the tx error
1398 * @priv: driver private structure
1399 * Description: it cleans the descriptors and restarts the transmission
1400 * in case of transmission errors.
1402 static void stmmac_tx_err(struct stmmac_priv *priv)
1405 netif_stop_queue(priv->dev);
1407 priv->hw->dma->stop_tx(priv->ioaddr);
1408 dma_free_tx_skbufs(priv);
1409 for (i = 0; i < DMA_TX_SIZE; i++)
1410 if (priv->extend_desc)
1411 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
1413 (i == DMA_TX_SIZE - 1));
1415 priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
1417 (i == DMA_TX_SIZE - 1));
1420 netdev_reset_queue(priv->dev);
1421 priv->hw->dma->start_tx(priv->ioaddr);
1423 priv->dev->stats.tx_errors++;
1424 netif_wake_queue(priv->dev);
1428 * stmmac_dma_interrupt - DMA ISR
1429 * @priv: driver private structure
1430 * Description: this is the DMA ISR. It is called by the main ISR.
1431 * It calls the dwmac dma routine and schedule poll method in case of some
1434 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
1437 int rxfifosz = priv->plat->rx_fifo_size;
1439 status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
1440 if (likely((status & handle_rx)) || (status & handle_tx)) {
1441 if (likely(napi_schedule_prep(&priv->napi))) {
1442 stmmac_disable_dma_irq(priv);
1443 __napi_schedule(&priv->napi);
1446 if (unlikely(status & tx_hard_error_bump_tc)) {
1447 /* Try to bump up the dma threshold on this failure */
1448 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
1451 if (priv->plat->force_thresh_dma_mode)
1452 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc,
1455 priv->hw->dma->dma_mode(priv->ioaddr, tc,
1456 SF_DMA_MODE, rxfifosz);
1457 priv->xstats.threshold = tc;
1459 } else if (unlikely(status == tx_hard_error))
1460 stmmac_tx_err(priv);
1464 * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
1465 * @priv: driver private structure
1466 * Description: this masks the MMC irq, in fact, the counters are managed in SW.
1468 static void stmmac_mmc_setup(struct stmmac_priv *priv)
1470 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
1471 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
1473 if (priv->synopsys_id >= DWMAC_CORE_4_00)
1474 priv->mmcaddr = priv->ioaddr + MMC_GMAC4_OFFSET;
1476 priv->mmcaddr = priv->ioaddr + MMC_GMAC3_X_OFFSET;
1478 dwmac_mmc_intr_all_mask(priv->mmcaddr);
1480 if (priv->dma_cap.rmon) {
1481 dwmac_mmc_ctrl(priv->mmcaddr, mode);
1482 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
1484 pr_info(" No MAC Management Counters available\n");
1488 * stmmac_selec_desc_mode - to select among: normal/alternate/extend descriptors
1489 * @priv: driver private structure
1490 * Description: select the Enhanced/Alternate or Normal descriptors.
1491 * In case of Enhanced/Alternate, it checks if the extended descriptors are
1492 * supported by the HW capability register.
1494 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
1496 if (priv->plat->enh_desc) {
1497 pr_info(" Enhanced/Alternate descriptors\n");
1499 /* GMAC older than 3.50 has no extended descriptors */
1500 if (priv->synopsys_id >= DWMAC_CORE_3_50) {
1501 pr_info("\tEnabled extended descriptors\n");
1502 priv->extend_desc = 1;
1504 pr_warn("Extended descriptors not supported\n");
1506 priv->hw->desc = &enh_desc_ops;
1508 pr_info(" Normal descriptors\n");
1509 priv->hw->desc = &ndesc_ops;
1514 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
1515 * @priv: driver private structure
1517 * new GMAC chip generations have a new register to indicate the
1518 * presence of the optional feature/functions.
1519 * This can be also used to override the value passed through the
1520 * platform and necessary for old MAC10/100 and GMAC chips.
1522 static int stmmac_get_hw_features(struct stmmac_priv *priv)
1526 if (priv->hw->dma->get_hw_feature) {
1527 priv->hw->dma->get_hw_feature(priv->ioaddr,
1536 * stmmac_check_ether_addr - check if the MAC addr is valid
1537 * @priv: driver private structure
1539 * it is to verify if the MAC address is valid, in case of failures it
1540 * generates a random MAC address
1542 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
1544 if (!is_valid_ether_addr(priv->dev->dev_addr)) {
1545 priv->hw->mac->get_umac_addr(priv->hw,
1546 priv->dev->dev_addr, 0);
1547 if (!is_valid_ether_addr(priv->dev->dev_addr))
1548 eth_hw_addr_random(priv->dev);
1549 pr_info("%s: device MAC address %pM\n", priv->dev->name,
1550 priv->dev->dev_addr);
1555 * stmmac_init_dma_engine - DMA init.
1556 * @priv: driver private structure
1558 * It inits the DMA invoking the specific MAC/GMAC callback.
1559 * Some DMA parameters can be passed from the platform;
1560 * in case of these are not passed a default is kept for the MAC or GMAC.
1562 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
1564 int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, aal = 0;
1565 int mixed_burst = 0;
1569 if (priv->plat->dma_cfg) {
1570 pbl = priv->plat->dma_cfg->pbl;
1571 fixed_burst = priv->plat->dma_cfg->fixed_burst;
1572 mixed_burst = priv->plat->dma_cfg->mixed_burst;
1573 aal = priv->plat->dma_cfg->aal;
1576 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
1579 ret = priv->hw->dma->reset(priv->ioaddr);
1581 dev_err(priv->device, "Failed to reset the dma\n");
1585 priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst,
1586 aal, priv->dma_tx_phy, priv->dma_rx_phy, atds);
1588 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
1589 priv->rx_tail_addr = priv->dma_rx_phy +
1590 (DMA_RX_SIZE * sizeof(struct dma_desc));
1591 priv->hw->dma->set_rx_tail_ptr(priv->ioaddr, priv->rx_tail_addr,
1594 priv->tx_tail_addr = priv->dma_tx_phy +
1595 (DMA_TX_SIZE * sizeof(struct dma_desc));
1596 priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, priv->tx_tail_addr,
1600 if (priv->plat->axi && priv->hw->dma->axi)
1601 priv->hw->dma->axi(priv->ioaddr, priv->plat->axi);
1607 * stmmac_tx_timer - mitigation sw timer for tx.
1608 * @data: data pointer
1610 * This is the timer handler to directly invoke the stmmac_tx_clean.
1612 static void stmmac_tx_timer(unsigned long data)
1614 struct stmmac_priv *priv = (struct stmmac_priv *)data;
1616 stmmac_tx_clean(priv);
1620 * stmmac_init_tx_coalesce - init tx mitigation options.
1621 * @priv: driver private structure
1623 * This inits the transmit coalesce parameters: i.e. timer rate,
1624 * timer handler and default threshold used for enabling the
1625 * interrupt on completion bit.
1627 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
1629 priv->tx_coal_frames = STMMAC_TX_FRAMES;
1630 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
1631 init_timer(&priv->txtimer);
1632 priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
1633 priv->txtimer.data = (unsigned long)priv;
1634 priv->txtimer.function = stmmac_tx_timer;
1635 add_timer(&priv->txtimer);
1639 * stmmac_hw_setup - setup mac in a usable state.
1640 * @dev : pointer to the device structure.
1642 * this is the main function to setup the HW in a usable state because the
1643 * dma engine is reset, the core registers are configured (e.g. AXI,
1644 * Checksum features, timers). The DMA is ready to start receiving and
1647 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1650 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
1652 struct stmmac_priv *priv = netdev_priv(dev);
1655 /* DMA initialization and SW reset */
1656 ret = stmmac_init_dma_engine(priv);
1658 pr_err("%s: DMA engine initialization failed\n", __func__);
1662 /* Copy the MAC addr into the HW */
1663 priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0);
1665 /* If required, perform hw setup of the bus. */
1666 if (priv->plat->bus_setup)
1667 priv->plat->bus_setup(priv->ioaddr);
1669 /* PS and related bits will be programmed according to the speed */
1670 if (priv->hw->pcs) {
1671 int speed = priv->plat->mac_port_sel_speed;
1673 if ((speed == SPEED_10) || (speed == SPEED_100) ||
1674 (speed == SPEED_1000)) {
1675 priv->hw->ps = speed;
1677 dev_warn(priv->device, "invalid port speed\n");
1682 /* Initialize the MAC Core */
1683 priv->hw->mac->core_init(priv->hw, dev->mtu);
1685 ret = priv->hw->mac->rx_ipc(priv->hw);
1687 pr_warn(" RX IPC Checksum Offload disabled\n");
1688 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
1689 priv->hw->rx_csum = 0;
1692 /* Enable the MAC Rx/Tx */
1693 if (priv->synopsys_id >= DWMAC_CORE_4_00)
1694 stmmac_dwmac4_set_mac(priv->ioaddr, true);
1696 stmmac_set_mac(priv->ioaddr, true);
1698 /* Set the HW DMA mode and the COE */
1699 stmmac_dma_operation_mode(priv);
1701 stmmac_mmc_setup(priv);
1704 ret = stmmac_init_ptp(priv);
1705 if (ret && ret != -EOPNOTSUPP)
1706 pr_warn("%s: failed PTP initialisation\n", __func__);
1709 #ifdef CONFIG_DEBUG_FS
1710 ret = stmmac_init_fs(dev);
1712 pr_warn("%s: failed debugFS registration\n", __func__);
1714 /* Start the ball rolling... */
1715 pr_debug("%s: DMA RX/TX processes started...\n", dev->name);
1716 priv->hw->dma->start_tx(priv->ioaddr);
1717 priv->hw->dma->start_rx(priv->ioaddr);
1719 /* Dump DMA/MAC registers */
1720 if (netif_msg_hw(priv)) {
1721 priv->hw->mac->dump_regs(priv->hw);
1722 priv->hw->dma->dump_regs(priv->ioaddr);
1724 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
1726 if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1727 priv->rx_riwt = MAX_DMA_RIWT;
1728 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
1731 if (priv->hw->pcs && priv->hw->mac->pcs_ctrl_ane)
1732 priv->hw->mac->pcs_ctrl_ane(priv->hw, 1, priv->hw->ps, 0);
1734 /* set TX ring length */
1735 if (priv->hw->dma->set_tx_ring_len)
1736 priv->hw->dma->set_tx_ring_len(priv->ioaddr,
1738 /* set RX ring length */
1739 if (priv->hw->dma->set_rx_ring_len)
1740 priv->hw->dma->set_rx_ring_len(priv->ioaddr,
1744 priv->hw->dma->enable_tso(priv->ioaddr, 1, STMMAC_CHAN0);
1750 * stmmac_open - open entry point of the driver
1751 * @dev : pointer to the device structure.
1753 * This function is the open entry point of the driver.
1755 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1758 static int stmmac_open(struct net_device *dev)
1760 struct stmmac_priv *priv = netdev_priv(dev);
1763 stmmac_check_ether_addr(priv);
1765 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
1766 priv->hw->pcs != STMMAC_PCS_TBI &&
1767 priv->hw->pcs != STMMAC_PCS_RTBI) {
1768 ret = stmmac_init_phy(dev);
1770 pr_err("%s: Cannot attach to PHY (error: %d)\n",
1776 /* Extra statistics */
1777 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1778 priv->xstats.threshold = tc;
1780 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1781 priv->rx_copybreak = STMMAC_RX_COPYBREAK;
1783 ret = alloc_dma_desc_resources(priv);
1785 pr_err("%s: DMA descriptors allocation failed\n", __func__);
1786 goto dma_desc_error;
1789 ret = init_dma_desc_rings(dev, GFP_KERNEL);
1791 pr_err("%s: DMA descriptors initialization failed\n", __func__);
1795 ret = stmmac_hw_setup(dev, true);
1797 pr_err("%s: Hw setup failed\n", __func__);
1801 stmmac_init_tx_coalesce(priv);
1804 phy_start(priv->phydev);
1806 /* Request the IRQ lines */
1807 ret = request_irq(dev->irq, stmmac_interrupt,
1808 IRQF_SHARED, dev->name, dev);
1809 if (unlikely(ret < 0)) {
1810 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1811 __func__, dev->irq, ret);
1815 /* Request the Wake IRQ in case of another line is used for WoL */
1816 if (priv->wol_irq != dev->irq) {
1817 ret = request_irq(priv->wol_irq, stmmac_interrupt,
1818 IRQF_SHARED, dev->name, dev);
1819 if (unlikely(ret < 0)) {
1820 pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n",
1821 __func__, priv->wol_irq, ret);
1826 /* Request the IRQ lines */
1827 if (priv->lpi_irq > 0) {
1828 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
1830 if (unlikely(ret < 0)) {
1831 pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1832 __func__, priv->lpi_irq, ret);
1837 napi_enable(&priv->napi);
1838 netif_start_queue(dev);
1843 if (priv->wol_irq != dev->irq)
1844 free_irq(priv->wol_irq, dev);
1846 free_irq(dev->irq, dev);
1849 free_dma_desc_resources(priv);
1852 phy_disconnect(priv->phydev);
1858 * stmmac_release - close entry point of the driver
1859 * @dev : device pointer.
1861 * This is the stop entry point of the driver.
1863 static int stmmac_release(struct net_device *dev)
1865 struct stmmac_priv *priv = netdev_priv(dev);
1867 if (priv->eee_enabled)
1868 del_timer_sync(&priv->eee_ctrl_timer);
1870 /* Stop and disconnect the PHY */
1872 phy_stop(priv->phydev);
1873 phy_disconnect(priv->phydev);
1874 priv->phydev = NULL;
1877 netif_stop_queue(dev);
1879 napi_disable(&priv->napi);
1881 del_timer_sync(&priv->txtimer);
1883 /* Free the IRQ lines */
1884 free_irq(dev->irq, dev);
1885 if (priv->wol_irq != dev->irq)
1886 free_irq(priv->wol_irq, dev);
1887 if (priv->lpi_irq > 0)
1888 free_irq(priv->lpi_irq, dev);
1890 /* Stop TX/RX DMA and clear the descriptors */
1891 priv->hw->dma->stop_tx(priv->ioaddr);
1892 priv->hw->dma->stop_rx(priv->ioaddr);
1894 /* Release and free the Rx/Tx resources */
1895 free_dma_desc_resources(priv);
1897 /* Disable the MAC Rx/Tx */
1898 stmmac_set_mac(priv->ioaddr, false);
1900 netif_carrier_off(dev);
1902 #ifdef CONFIG_DEBUG_FS
1903 stmmac_exit_fs(dev);
1906 stmmac_release_ptp(priv);
1912 * stmmac_tso_allocator - close entry point of the driver
1913 * @priv: driver private structure
1914 * @des: buffer start address
1915 * @total_len: total length to fill in descriptors
1916 * @last_segmant: condition for the last descriptor
1918 * This function fills descriptor and request new descriptors according to
1919 * buffer length to fill
1921 static void stmmac_tso_allocator(struct stmmac_priv *priv, unsigned int des,
1922 int total_len, bool last_segment)
1924 struct dma_desc *desc;
1928 tmp_len = total_len;
1930 while (tmp_len > 0) {
1931 priv->cur_tx = STMMAC_GET_ENTRY(priv->cur_tx, DMA_TX_SIZE);
1932 desc = priv->dma_tx + priv->cur_tx;
1934 desc->des0 = des + (total_len - tmp_len);
1935 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ?
1936 TSO_MAX_BUFF_SIZE : tmp_len;
1938 priv->hw->desc->prepare_tso_tx_desc(desc, 0, buff_size,
1940 (last_segment) && (buff_size < TSO_MAX_BUFF_SIZE),
1943 tmp_len -= TSO_MAX_BUFF_SIZE;
1948 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO)
1949 * @skb : the socket buffer
1950 * @dev : device pointer
1951 * Description: this is the transmit function that is called on TSO frames
1952 * (support available on GMAC4 and newer chips).
1953 * Diagram below show the ring programming in case of TSO frames:
1957 * | DES0 |---> buffer1 = L2/L3/L4 header
1958 * | DES1 |---> TCP Payload (can continue on next descr...)
1959 * | DES2 |---> buffer 1 and 2 len
1960 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0]
1966 * | DES0 | --| Split TCP Payload on Buffers 1 and 2
1968 * | DES2 | --> buffer 1 and 2 len
1972 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field.
1974 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
1977 int tmp_pay_len = 0;
1978 struct stmmac_priv *priv = netdev_priv(dev);
1979 int nfrags = skb_shinfo(skb)->nr_frags;
1980 unsigned int first_entry, des;
1981 struct dma_desc *desc, *first, *mss_desc = NULL;
1985 spin_lock(&priv->tx_lock);
1987 /* Compute header lengths */
1988 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
1990 /* Desc availability based on threshold should be enough safe */
1991 if (unlikely(stmmac_tx_avail(priv) <
1992 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) {
1993 if (!netif_queue_stopped(dev)) {
1994 netif_stop_queue(dev);
1995 /* This is a hard error, log it. */
1996 pr_err("%s: Tx Ring full when queue awake\n", __func__);
1998 spin_unlock(&priv->tx_lock);
1999 return NETDEV_TX_BUSY;
2002 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */
2004 mss = skb_shinfo(skb)->gso_size;
2006 /* set new MSS value if needed */
2007 if (mss != priv->mss) {
2008 mss_desc = priv->dma_tx + priv->cur_tx;
2009 priv->hw->desc->set_mss(mss_desc, mss);
2011 priv->cur_tx = STMMAC_GET_ENTRY(priv->cur_tx, DMA_TX_SIZE);
2014 if (netif_msg_tx_queued(priv)) {
2015 pr_info("%s: tcphdrlen %d, hdr_len %d, pay_len %d, mss %d\n",
2016 __func__, tcp_hdrlen(skb), proto_hdr_len, pay_len, mss);
2017 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len,
2021 first_entry = priv->cur_tx;
2023 desc = priv->dma_tx + first_entry;
2026 /* first descriptor: fill Headers on Buf1 */
2027 des = dma_map_single(priv->device, skb->data, skb_headlen(skb),
2029 if (dma_mapping_error(priv->device, des))
2032 priv->tx_skbuff_dma[first_entry].buf = des;
2033 priv->tx_skbuff_dma[first_entry].len = skb_headlen(skb);
2034 priv->tx_skbuff[first_entry] = skb;
2038 /* Fill start of payload in buff2 of first descriptor */
2040 first->des1 = des + proto_hdr_len;
2042 /* If needed take extra descriptors to fill the remaining payload */
2043 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE;
2045 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0));
2047 /* Prepare fragments */
2048 for (i = 0; i < nfrags; i++) {
2049 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2051 des = skb_frag_dma_map(priv->device, frag, 0,
2052 skb_frag_size(frag),
2055 stmmac_tso_allocator(priv, des, skb_frag_size(frag),
2058 priv->tx_skbuff_dma[priv->cur_tx].buf = des;
2059 priv->tx_skbuff_dma[priv->cur_tx].len = skb_frag_size(frag);
2060 priv->tx_skbuff[priv->cur_tx] = NULL;
2061 priv->tx_skbuff_dma[priv->cur_tx].map_as_page = true;
2064 priv->tx_skbuff_dma[priv->cur_tx].last_segment = true;
2066 priv->cur_tx = STMMAC_GET_ENTRY(priv->cur_tx, DMA_TX_SIZE);
2068 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
2069 if (netif_msg_hw(priv))
2070 pr_debug("%s: stop transmitted packets\n", __func__);
2071 netif_stop_queue(dev);
2074 dev->stats.tx_bytes += skb->len;
2075 priv->xstats.tx_tso_frames++;
2076 priv->xstats.tx_tso_nfrags += nfrags;
2078 /* Manage tx mitigation */
2079 priv->tx_count_frames += nfrags + 1;
2080 if (likely(priv->tx_coal_frames > priv->tx_count_frames)) {
2081 mod_timer(&priv->txtimer,
2082 STMMAC_COAL_TIMER(priv->tx_coal_timer));
2084 priv->tx_count_frames = 0;
2085 priv->hw->desc->set_tx_ic(desc);
2086 priv->xstats.tx_set_ic_bit++;
2089 if (!priv->hwts_tx_en)
2090 skb_tx_timestamp(skb);
2092 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2093 priv->hwts_tx_en)) {
2094 /* declare that device is doing timestamping */
2095 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2096 priv->hw->desc->enable_tx_timestamp(first);
2099 /* Complete the first descriptor before granting the DMA */
2100 priv->hw->desc->prepare_tso_tx_desc(first, 1,
2103 1, priv->tx_skbuff_dma[first_entry].last_segment,
2104 tcp_hdrlen(skb) / 4, (skb->len - proto_hdr_len));
2106 /* If context desc is used to change MSS */
2108 priv->hw->desc->set_tx_owner(mss_desc);
2110 /* The own bit must be the latest setting done when prepare the
2111 * descriptor and then barrier is needed to make sure that
2112 * all is coherent before granting the DMA engine.
2116 if (netif_msg_pktdata(priv)) {
2117 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n",
2118 __func__, priv->cur_tx, priv->dirty_tx, first_entry,
2119 priv->cur_tx, first, nfrags);
2121 priv->hw->desc->display_ring((void *)priv->dma_tx, DMA_TX_SIZE,
2124 pr_info(">>> frame to be transmitted: ");
2125 print_pkt(skb->data, skb_headlen(skb));
2128 netdev_sent_queue(dev, skb->len);
2130 priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, priv->tx_tail_addr,
2133 spin_unlock(&priv->tx_lock);
2134 return NETDEV_TX_OK;
2137 spin_unlock(&priv->tx_lock);
2138 dev_err(priv->device, "Tx dma map failed\n");
2140 priv->dev->stats.tx_dropped++;
2141 return NETDEV_TX_OK;
2145 * stmmac_xmit - Tx entry point of the driver
2146 * @skb : the socket buffer
2147 * @dev : device pointer
2148 * Description : this is the tx entry point of the driver.
2149 * It programs the chain or the ring and supports oversized frames
2152 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
2154 struct stmmac_priv *priv = netdev_priv(dev);
2155 unsigned int nopaged_len = skb_headlen(skb);
2156 int i, csum_insertion = 0, is_jumbo = 0;
2157 int nfrags = skb_shinfo(skb)->nr_frags;
2158 unsigned int entry, first_entry;
2159 struct dma_desc *desc, *first;
2160 unsigned int enh_desc;
2163 /* Manage oversized TCP frames for GMAC4 device */
2164 if (skb_is_gso(skb) && priv->tso) {
2165 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2166 return stmmac_tso_xmit(skb, dev);
2169 spin_lock(&priv->tx_lock);
2171 if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
2172 spin_unlock(&priv->tx_lock);
2173 if (!netif_queue_stopped(dev)) {
2174 netif_stop_queue(dev);
2175 /* This is a hard error, log it. */
2176 pr_err("%s: Tx Ring full when queue awake\n", __func__);
2178 return NETDEV_TX_BUSY;
2181 if (priv->tx_path_in_lpi_mode)
2182 stmmac_disable_eee_mode(priv);
2184 entry = priv->cur_tx;
2185 first_entry = entry;
2187 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
2189 if (likely(priv->extend_desc))
2190 desc = (struct dma_desc *)(priv->dma_etx + entry);
2192 desc = priv->dma_tx + entry;
2196 priv->tx_skbuff[first_entry] = skb;
2198 enh_desc = priv->plat->enh_desc;
2199 /* To program the descriptors according to the size of the frame */
2201 is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc);
2203 if (unlikely(is_jumbo) && likely(priv->synopsys_id <
2205 entry = priv->hw->mode->jumbo_frm(priv, skb, csum_insertion);
2206 if (unlikely(entry < 0))
2210 for (i = 0; i < nfrags; i++) {
2211 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2212 int len = skb_frag_size(frag);
2213 bool last_segment = (i == (nfrags - 1));
2215 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
2217 if (likely(priv->extend_desc))
2218 desc = (struct dma_desc *)(priv->dma_etx + entry);
2220 desc = priv->dma_tx + entry;
2222 des = skb_frag_dma_map(priv->device, frag, 0, len,
2224 if (dma_mapping_error(priv->device, des))
2225 goto dma_map_err; /* should reuse desc w/o issues */
2227 priv->tx_skbuff[entry] = NULL;
2229 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) {
2231 priv->tx_skbuff_dma[entry].buf = desc->des0;
2234 priv->tx_skbuff_dma[entry].buf = desc->des2;
2237 priv->tx_skbuff_dma[entry].map_as_page = true;
2238 priv->tx_skbuff_dma[entry].len = len;
2239 priv->tx_skbuff_dma[entry].last_segment = last_segment;
2241 /* Prepare the descriptor and set the own bit too */
2242 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion,
2243 priv->mode, 1, last_segment);
2246 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
2248 priv->cur_tx = entry;
2250 if (netif_msg_pktdata(priv)) {
2253 pr_debug("%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d",
2254 __func__, priv->cur_tx, priv->dirty_tx, first_entry,
2255 entry, first, nfrags);
2257 if (priv->extend_desc)
2258 tx_head = (void *)priv->dma_etx;
2260 tx_head = (void *)priv->dma_tx;
2262 priv->hw->desc->display_ring(tx_head, DMA_TX_SIZE, false);
2264 pr_debug(">>> frame to be transmitted: ");
2265 print_pkt(skb->data, skb->len);
2268 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
2269 if (netif_msg_hw(priv))
2270 pr_debug("%s: stop transmitted packets\n", __func__);
2271 netif_stop_queue(dev);
2274 dev->stats.tx_bytes += skb->len;
2276 /* According to the coalesce parameter the IC bit for the latest
2277 * segment is reset and the timer re-started to clean the tx status.
2278 * This approach takes care about the fragments: desc is the first
2279 * element in case of no SG.
2281 priv->tx_count_frames += nfrags + 1;
2282 if (likely(priv->tx_coal_frames > priv->tx_count_frames)) {
2283 mod_timer(&priv->txtimer,
2284 STMMAC_COAL_TIMER(priv->tx_coal_timer));
2286 priv->tx_count_frames = 0;
2287 priv->hw->desc->set_tx_ic(desc);
2288 priv->xstats.tx_set_ic_bit++;
2291 if (!priv->hwts_tx_en)
2292 skb_tx_timestamp(skb);
2294 /* Ready to fill the first descriptor and set the OWN bit w/o any
2295 * problems because all the descriptors are actually ready to be
2296 * passed to the DMA engine.
2298 if (likely(!is_jumbo)) {
2299 bool last_segment = (nfrags == 0);
2301 des = dma_map_single(priv->device, skb->data,
2302 nopaged_len, DMA_TO_DEVICE);
2303 if (dma_mapping_error(priv->device, des))
2306 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) {
2308 priv->tx_skbuff_dma[first_entry].buf = first->des0;
2311 priv->tx_skbuff_dma[first_entry].buf = first->des2;
2314 priv->tx_skbuff_dma[first_entry].len = nopaged_len;
2315 priv->tx_skbuff_dma[first_entry].last_segment = last_segment;
2317 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2318 priv->hwts_tx_en)) {
2319 /* declare that device is doing timestamping */
2320 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2321 priv->hw->desc->enable_tx_timestamp(first);
2324 /* Prepare the first descriptor setting the OWN bit too */
2325 priv->hw->desc->prepare_tx_desc(first, 1, nopaged_len,
2326 csum_insertion, priv->mode, 1,
2329 /* The own bit must be the latest setting done when prepare the
2330 * descriptor and then barrier is needed to make sure that
2331 * all is coherent before granting the DMA engine.
2336 netdev_sent_queue(dev, skb->len);
2338 if (priv->synopsys_id < DWMAC_CORE_4_00)
2339 priv->hw->dma->enable_dma_transmission(priv->ioaddr);
2341 priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, priv->tx_tail_addr,
2344 spin_unlock(&priv->tx_lock);
2345 return NETDEV_TX_OK;
2348 spin_unlock(&priv->tx_lock);
2349 dev_err(priv->device, "Tx dma map failed\n");
2351 priv->dev->stats.tx_dropped++;
2352 return NETDEV_TX_OK;
2355 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
2357 struct ethhdr *ehdr;
2360 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) ==
2361 NETIF_F_HW_VLAN_CTAG_RX &&
2362 !__vlan_get_tag(skb, &vlanid)) {
2363 /* pop the vlan tag */
2364 ehdr = (struct ethhdr *)skb->data;
2365 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
2366 skb_pull(skb, VLAN_HLEN);
2367 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
2372 static inline int stmmac_rx_threshold_count(struct stmmac_priv *priv)
2374 if (priv->rx_zeroc_thresh < STMMAC_RX_THRESH)
2381 * stmmac_rx_refill - refill used skb preallocated buffers
2382 * @priv: driver private structure
2383 * Description : this is to reallocate the skb for the reception process
2384 * that is based on zero-copy.
2386 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
2388 int bfsize = priv->dma_buf_sz;
2389 unsigned int entry = priv->dirty_rx;
2390 int dirty = stmmac_rx_dirty(priv);
2392 while (dirty-- > 0) {
2395 if (priv->extend_desc)
2396 p = (struct dma_desc *)(priv->dma_erx + entry);
2398 p = priv->dma_rx + entry;
2400 if (likely(priv->rx_skbuff[entry] == NULL)) {
2401 struct sk_buff *skb;
2403 skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
2404 if (unlikely(!skb)) {
2405 /* so for a while no zero-copy! */
2406 priv->rx_zeroc_thresh = STMMAC_RX_THRESH;
2407 if (unlikely(net_ratelimit()))
2408 dev_err(priv->device,
2409 "fail to alloc skb entry %d\n",
2414 priv->rx_skbuff[entry] = skb;
2415 priv->rx_skbuff_dma[entry] =
2416 dma_map_single(priv->device, skb->data, bfsize,
2418 if (dma_mapping_error(priv->device,
2419 priv->rx_skbuff_dma[entry])) {
2420 dev_err(priv->device, "Rx dma map failed\n");
2425 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) {
2426 p->des0 = priv->rx_skbuff_dma[entry];
2429 p->des2 = priv->rx_skbuff_dma[entry];
2431 if (priv->hw->mode->refill_desc3)
2432 priv->hw->mode->refill_desc3(priv, p);
2434 if (priv->rx_zeroc_thresh > 0)
2435 priv->rx_zeroc_thresh--;
2437 if (netif_msg_rx_status(priv))
2438 pr_debug("\trefill entry #%d\n", entry);
2442 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00))
2443 priv->hw->desc->init_rx_desc(p, priv->use_riwt, 0, 0);
2445 priv->hw->desc->set_rx_owner(p);
2449 entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE);
2451 priv->dirty_rx = entry;
2455 * stmmac_rx - manage the receive process
2456 * @priv: driver private structure
2457 * @limit: napi bugget.
2458 * Description : this the function called by the napi poll method.
2459 * It gets all the frames inside the ring.
2461 static int stmmac_rx(struct stmmac_priv *priv, int limit)
2463 unsigned int entry = priv->cur_rx;
2464 unsigned int next_entry;
2465 unsigned int count = 0;
2466 int coe = priv->hw->rx_csum;
2468 if (netif_msg_rx_status(priv)) {
2471 pr_debug("%s: descriptor ring:\n", __func__);
2472 if (priv->extend_desc)
2473 rx_head = (void *)priv->dma_erx;
2475 rx_head = (void *)priv->dma_rx;
2477 priv->hw->desc->display_ring(rx_head, DMA_RX_SIZE, true);
2479 while (count < limit) {
2483 if (priv->extend_desc)
2484 p = (struct dma_desc *)(priv->dma_erx + entry);
2486 p = priv->dma_rx + entry;
2488 /* read the status of the incoming frame */
2489 status = priv->hw->desc->rx_status(&priv->dev->stats,
2491 /* check if managed by the DMA otherwise go ahead */
2492 if (unlikely(status & dma_own))
2497 priv->cur_rx = STMMAC_GET_ENTRY(priv->cur_rx, DMA_RX_SIZE);
2498 next_entry = priv->cur_rx;
2500 if (priv->extend_desc)
2501 prefetch(priv->dma_erx + next_entry);
2503 prefetch(priv->dma_rx + next_entry);
2505 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))
2506 priv->hw->desc->rx_extended_status(&priv->dev->stats,
2510 if (unlikely(status == discard_frame)) {
2511 priv->dev->stats.rx_errors++;
2512 if (priv->hwts_rx_en && !priv->extend_desc) {
2513 /* DESC2 & DESC3 will be overwitten by device
2514 * with timestamp value, hence reinitialize
2515 * them in stmmac_rx_refill() function so that
2516 * device can reuse it.
2518 priv->rx_skbuff[entry] = NULL;
2519 dma_unmap_single(priv->device,
2520 priv->rx_skbuff_dma[entry],
2525 struct sk_buff *skb;
2529 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00))
2534 frame_len = priv->hw->desc->get_rx_frame_len(p, coe);
2536 /* If frame length is greather than skb buffer size
2537 * (preallocated during init) then the packet is
2540 if (frame_len > priv->dma_buf_sz) {
2541 pr_err("%s: len %d larger than size (%d)\n",
2542 priv->dev->name, frame_len,
2544 priv->dev->stats.rx_length_errors++;
2548 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
2549 * Type frames (LLC/LLC-SNAP)
2551 if (unlikely(status != llc_snap))
2552 frame_len -= ETH_FCS_LEN;
2554 if (netif_msg_rx_status(priv)) {
2555 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
2557 if (frame_len > ETH_FRAME_LEN)
2558 pr_debug("\tframe size %d, COE: %d\n",
2562 /* The zero-copy is always used for all the sizes
2563 * in case of GMAC4 because it needs
2564 * to refill the used descriptors, always.
2566 if (unlikely(!priv->plat->has_gmac4 &&
2567 ((frame_len < priv->rx_copybreak) ||
2568 stmmac_rx_threshold_count(priv)))) {
2569 skb = netdev_alloc_skb_ip_align(priv->dev,
2571 if (unlikely(!skb)) {
2572 if (net_ratelimit())
2573 dev_warn(priv->device,
2574 "packet dropped\n");
2575 priv->dev->stats.rx_dropped++;
2579 dma_sync_single_for_cpu(priv->device,
2583 skb_copy_to_linear_data(skb,
2585 rx_skbuff[entry]->data,
2588 skb_put(skb, frame_len);
2589 dma_sync_single_for_device(priv->device,
2594 skb = priv->rx_skbuff[entry];
2595 if (unlikely(!skb)) {
2596 pr_err("%s: Inconsistent Rx chain\n",
2598 priv->dev->stats.rx_dropped++;
2601 prefetch(skb->data - NET_IP_ALIGN);
2602 priv->rx_skbuff[entry] = NULL;
2603 priv->rx_zeroc_thresh++;
2605 skb_put(skb, frame_len);
2606 dma_unmap_single(priv->device,
2607 priv->rx_skbuff_dma[entry],
2612 stmmac_get_rx_hwtstamp(priv, entry, skb);
2614 if (netif_msg_pktdata(priv)) {
2615 pr_debug("frame received (%dbytes)", frame_len);
2616 print_pkt(skb->data, frame_len);
2619 stmmac_rx_vlan(priv->dev, skb);
2621 skb->protocol = eth_type_trans(skb, priv->dev);
2624 skb_checksum_none_assert(skb);
2626 skb->ip_summed = CHECKSUM_UNNECESSARY;
2628 napi_gro_receive(&priv->napi, skb);
2630 priv->dev->stats.rx_packets++;
2631 priv->dev->stats.rx_bytes += frame_len;
2636 stmmac_rx_refill(priv);
2638 priv->xstats.rx_pkt_n += count;
2644 * stmmac_poll - stmmac poll method (NAPI)
2645 * @napi : pointer to the napi structure.
2646 * @budget : maximum number of packets that the current CPU can receive from
2649 * To look at the incoming frames and clear the tx resources.
2651 static int stmmac_poll(struct napi_struct *napi, int budget)
2653 struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
2656 priv->xstats.napi_poll++;
2657 stmmac_tx_clean(priv);
2659 work_done = stmmac_rx(priv, budget);
2660 if (work_done < budget) {
2661 napi_complete(napi);
2662 stmmac_enable_dma_irq(priv);
2669 * @dev : Pointer to net device structure
2670 * Description: this function is called when a packet transmission fails to
2671 * complete within a reasonable time. The driver will mark the error in the
2672 * netdev structure and arrange for the device to be reset to a sane state
2673 * in order to transmit a new packet.
2675 static void stmmac_tx_timeout(struct net_device *dev)
2677 struct stmmac_priv *priv = netdev_priv(dev);
2679 /* Clear Tx resources and restart transmitting again */
2680 stmmac_tx_err(priv);
2684 * stmmac_set_rx_mode - entry point for multicast addressing
2685 * @dev : pointer to the device structure
2687 * This function is a driver entry point which gets called by the kernel
2688 * whenever multicast addresses must be enabled/disabled.
2692 static void stmmac_set_rx_mode(struct net_device *dev)
2694 struct stmmac_priv *priv = netdev_priv(dev);
2696 priv->hw->mac->set_filter(priv->hw, dev);
2700 * stmmac_change_mtu - entry point to change MTU size for the device.
2701 * @dev : device pointer.
2702 * @new_mtu : the new MTU size for the device.
2703 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
2704 * to drive packet transmission. Ethernet has an MTU of 1500 octets
2705 * (ETH_DATA_LEN). This value can be changed with ifconfig.
2707 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2710 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
2712 struct stmmac_priv *priv = netdev_priv(dev);
2715 if (netif_running(dev)) {
2716 pr_err("%s: must be stopped to change its MTU\n", dev->name);
2720 if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00))
2721 max_mtu = JUMBO_LEN;
2723 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
2725 if (priv->plat->maxmtu < max_mtu)
2726 max_mtu = priv->plat->maxmtu;
2728 if ((new_mtu < 46) || (new_mtu > max_mtu)) {
2729 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
2735 netdev_update_features(dev);
2740 static netdev_features_t stmmac_fix_features(struct net_device *dev,
2741 netdev_features_t features)
2743 struct stmmac_priv *priv = netdev_priv(dev);
2745 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
2746 features &= ~NETIF_F_RXCSUM;
2748 if (!priv->plat->tx_coe)
2749 features &= ~NETIF_F_CSUM_MASK;
2751 /* Some GMAC devices have a bugged Jumbo frame support that
2752 * needs to have the Tx COE disabled for oversized frames
2753 * (due to limited buffer sizes). In this case we disable
2754 * the TX csum insertionin the TDES and not use SF.
2756 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
2757 features &= ~NETIF_F_CSUM_MASK;
2759 /* Disable tso if asked by ethtool */
2760 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
2761 if (features & NETIF_F_TSO)
2770 static int stmmac_set_features(struct net_device *netdev,
2771 netdev_features_t features)
2773 struct stmmac_priv *priv = netdev_priv(netdev);
2775 /* Keep the COE Type in case of csum is supporting */
2776 if (features & NETIF_F_RXCSUM)
2777 priv->hw->rx_csum = priv->plat->rx_coe;
2779 priv->hw->rx_csum = 0;
2780 /* No check needed because rx_coe has been set before and it will be
2781 * fixed in case of issue.
2783 priv->hw->mac->rx_ipc(priv->hw);
2789 * stmmac_interrupt - main ISR
2790 * @irq: interrupt number.
2791 * @dev_id: to pass the net device pointer.
2792 * Description: this is the main driver interrupt service routine.
2794 * o DMA service routine (to manage incoming frame reception and transmission
2796 * o Core interrupts to manage: remote wake-up, management counter, LPI
2799 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
2801 struct net_device *dev = (struct net_device *)dev_id;
2802 struct stmmac_priv *priv = netdev_priv(dev);
2805 pm_wakeup_event(priv->device, 0);
2807 if (unlikely(!dev)) {
2808 pr_err("%s: invalid dev pointer\n", __func__);
2812 /* To handle GMAC own interrupts */
2813 if ((priv->plat->has_gmac) || (priv->plat->has_gmac4)) {
2814 int status = priv->hw->mac->host_irq_status(priv->hw,
2816 if (unlikely(status)) {
2817 /* For LPI we need to save the tx status */
2818 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
2819 priv->tx_path_in_lpi_mode = true;
2820 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
2821 priv->tx_path_in_lpi_mode = false;
2822 if (status & CORE_IRQ_MTL_RX_OVERFLOW && priv->hw->dma->set_rx_tail_ptr)
2823 priv->hw->dma->set_rx_tail_ptr(priv->ioaddr,
2828 /* PCS link status */
2829 if (priv->hw->pcs) {
2830 if (priv->xstats.pcs_link)
2831 netif_carrier_on(dev);
2833 netif_carrier_off(dev);
2837 /* To handle DMA interrupts */
2838 stmmac_dma_interrupt(priv);
2843 #ifdef CONFIG_NET_POLL_CONTROLLER
2844 /* Polling receive - used by NETCONSOLE and other diagnostic tools
2845 * to allow network I/O with interrupts disabled.
2847 static void stmmac_poll_controller(struct net_device *dev)
2849 disable_irq(dev->irq);
2850 stmmac_interrupt(dev->irq, dev);
2851 enable_irq(dev->irq);
2856 * stmmac_ioctl - Entry point for the Ioctl
2857 * @dev: Device pointer.
2858 * @rq: An IOCTL specefic structure, that can contain a pointer to
2859 * a proprietary structure used to pass information to the driver.
2860 * @cmd: IOCTL command
2862 * Currently it supports the phy_mii_ioctl(...) and HW time stamping.
2864 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2866 struct stmmac_priv *priv = netdev_priv(dev);
2867 int ret = -EOPNOTSUPP;
2869 if (!netif_running(dev))
2878 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
2881 ret = stmmac_hwtstamp_ioctl(dev, rq);
2890 #ifdef CONFIG_DEBUG_FS
2891 static struct dentry *stmmac_fs_dir;
2893 static void sysfs_display_ring(void *head, int size, int extend_desc,
2894 struct seq_file *seq)
2897 struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
2898 struct dma_desc *p = (struct dma_desc *)head;
2900 for (i = 0; i < size; i++) {
2904 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2905 i, (unsigned int)virt_to_phys(ep),
2906 ep->basic.des0, ep->basic.des1,
2907 ep->basic.des2, ep->basic.des3);
2911 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2912 i, (unsigned int)virt_to_phys(ep),
2913 p->des0, p->des1, p->des2, p->des3);
2916 seq_printf(seq, "\n");
2920 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
2922 struct net_device *dev = seq->private;
2923 struct stmmac_priv *priv = netdev_priv(dev);
2925 if (priv->extend_desc) {
2926 seq_printf(seq, "Extended RX descriptor ring:\n");
2927 sysfs_display_ring((void *)priv->dma_erx, DMA_RX_SIZE, 1, seq);
2928 seq_printf(seq, "Extended TX descriptor ring:\n");
2929 sysfs_display_ring((void *)priv->dma_etx, DMA_TX_SIZE, 1, seq);
2931 seq_printf(seq, "RX descriptor ring:\n");
2932 sysfs_display_ring((void *)priv->dma_rx, DMA_RX_SIZE, 0, seq);
2933 seq_printf(seq, "TX descriptor ring:\n");
2934 sysfs_display_ring((void *)priv->dma_tx, DMA_TX_SIZE, 0, seq);
2940 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
2942 return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
2945 static const struct file_operations stmmac_rings_status_fops = {
2946 .owner = THIS_MODULE,
2947 .open = stmmac_sysfs_ring_open,
2949 .llseek = seq_lseek,
2950 .release = single_release,
2953 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
2955 struct net_device *dev = seq->private;
2956 struct stmmac_priv *priv = netdev_priv(dev);
2958 if (!priv->hw_cap_support) {
2959 seq_printf(seq, "DMA HW features not supported\n");
2963 seq_printf(seq, "==============================\n");
2964 seq_printf(seq, "\tDMA HW features\n");
2965 seq_printf(seq, "==============================\n");
2967 seq_printf(seq, "\t10/100 Mbps %s\n",
2968 (priv->dma_cap.mbps_10_100) ? "Y" : "N");
2969 seq_printf(seq, "\t1000 Mbps %s\n",
2970 (priv->dma_cap.mbps_1000) ? "Y" : "N");
2971 seq_printf(seq, "\tHalf duple %s\n",
2972 (priv->dma_cap.half_duplex) ? "Y" : "N");
2973 seq_printf(seq, "\tHash Filter: %s\n",
2974 (priv->dma_cap.hash_filter) ? "Y" : "N");
2975 seq_printf(seq, "\tMultiple MAC address registers: %s\n",
2976 (priv->dma_cap.multi_addr) ? "Y" : "N");
2977 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
2978 (priv->dma_cap.pcs) ? "Y" : "N");
2979 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
2980 (priv->dma_cap.sma_mdio) ? "Y" : "N");
2981 seq_printf(seq, "\tPMT Remote wake up: %s\n",
2982 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
2983 seq_printf(seq, "\tPMT Magic Frame: %s\n",
2984 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
2985 seq_printf(seq, "\tRMON module: %s\n",
2986 (priv->dma_cap.rmon) ? "Y" : "N");
2987 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
2988 (priv->dma_cap.time_stamp) ? "Y" : "N");
2989 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
2990 (priv->dma_cap.atime_stamp) ? "Y" : "N");
2991 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
2992 (priv->dma_cap.eee) ? "Y" : "N");
2993 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
2994 seq_printf(seq, "\tChecksum Offload in TX: %s\n",
2995 (priv->dma_cap.tx_coe) ? "Y" : "N");
2996 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
2997 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n",
2998 (priv->dma_cap.rx_coe) ? "Y" : "N");
3000 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
3001 (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
3002 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
3003 (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
3005 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
3006 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
3007 seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
3008 priv->dma_cap.number_rx_channel);
3009 seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
3010 priv->dma_cap.number_tx_channel);
3011 seq_printf(seq, "\tEnhanced descriptors: %s\n",
3012 (priv->dma_cap.enh_desc) ? "Y" : "N");
3017 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
3019 return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
3022 static const struct file_operations stmmac_dma_cap_fops = {
3023 .owner = THIS_MODULE,
3024 .open = stmmac_sysfs_dma_cap_open,
3026 .llseek = seq_lseek,
3027 .release = single_release,
3030 static int stmmac_init_fs(struct net_device *dev)
3032 struct stmmac_priv *priv = netdev_priv(dev);
3034 /* Create per netdev entries */
3035 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
3037 if (!priv->dbgfs_dir || IS_ERR(priv->dbgfs_dir)) {
3038 pr_err("ERROR %s/%s, debugfs create directory failed\n",
3039 STMMAC_RESOURCE_NAME, dev->name);
3044 /* Entry to report DMA RX/TX rings */
3045 priv->dbgfs_rings_status =
3046 debugfs_create_file("descriptors_status", S_IRUGO,
3047 priv->dbgfs_dir, dev,
3048 &stmmac_rings_status_fops);
3050 if (!priv->dbgfs_rings_status || IS_ERR(priv->dbgfs_rings_status)) {
3051 pr_info("ERROR creating stmmac ring debugfs file\n");
3052 debugfs_remove_recursive(priv->dbgfs_dir);
3057 /* Entry to report the DMA HW features */
3058 priv->dbgfs_dma_cap = debugfs_create_file("dma_cap", S_IRUGO,
3060 dev, &stmmac_dma_cap_fops);
3062 if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) {
3063 pr_info("ERROR creating stmmac MMC debugfs file\n");
3064 debugfs_remove_recursive(priv->dbgfs_dir);
3072 static void stmmac_exit_fs(struct net_device *dev)
3074 struct stmmac_priv *priv = netdev_priv(dev);
3076 debugfs_remove_recursive(priv->dbgfs_dir);
3078 #endif /* CONFIG_DEBUG_FS */
3080 static const struct net_device_ops stmmac_netdev_ops = {
3081 .ndo_open = stmmac_open,
3082 .ndo_start_xmit = stmmac_xmit,
3083 .ndo_stop = stmmac_release,
3084 .ndo_change_mtu = stmmac_change_mtu,
3085 .ndo_fix_features = stmmac_fix_features,
3086 .ndo_set_features = stmmac_set_features,
3087 .ndo_set_rx_mode = stmmac_set_rx_mode,
3088 .ndo_tx_timeout = stmmac_tx_timeout,
3089 .ndo_do_ioctl = stmmac_ioctl,
3090 #ifdef CONFIG_NET_POLL_CONTROLLER
3091 .ndo_poll_controller = stmmac_poll_controller,
3093 .ndo_set_mac_address = eth_mac_addr,
3097 * stmmac_hw_init - Init the MAC device
3098 * @priv: driver private structure
3099 * Description: this function is to configure the MAC device according to
3100 * some platform parameters or the HW capability register. It prepares the
3101 * driver to use either ring or chain modes and to setup either enhanced or
3102 * normal descriptors.
3104 static int stmmac_hw_init(struct stmmac_priv *priv)
3106 struct mac_device_info *mac;
3108 /* Identify the MAC HW device */
3109 if (priv->plat->has_gmac) {
3110 priv->dev->priv_flags |= IFF_UNICAST_FLT;
3111 mac = dwmac1000_setup(priv->ioaddr,
3112 priv->plat->multicast_filter_bins,
3113 priv->plat->unicast_filter_entries,
3114 &priv->synopsys_id);
3115 } else if (priv->plat->has_gmac4) {
3116 priv->dev->priv_flags |= IFF_UNICAST_FLT;
3117 mac = dwmac4_setup(priv->ioaddr,
3118 priv->plat->multicast_filter_bins,
3119 priv->plat->unicast_filter_entries,
3120 &priv->synopsys_id);
3122 mac = dwmac100_setup(priv->ioaddr, &priv->synopsys_id);
3129 /* To use the chained or ring mode */
3130 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
3131 priv->hw->mode = &dwmac4_ring_mode_ops;
3134 priv->hw->mode = &chain_mode_ops;
3135 pr_info(" Chain mode enabled\n");
3136 priv->mode = STMMAC_CHAIN_MODE;
3138 priv->hw->mode = &ring_mode_ops;
3139 pr_info(" Ring mode enabled\n");
3140 priv->mode = STMMAC_RING_MODE;
3144 /* Get the HW capability (new GMAC newer than 3.50a) */
3145 priv->hw_cap_support = stmmac_get_hw_features(priv);
3146 if (priv->hw_cap_support) {
3147 pr_info(" DMA HW capability register supported");
3149 /* We can override some gmac/dma configuration fields: e.g.
3150 * enh_desc, tx_coe (e.g. that are passed through the
3151 * platform) with the values from the HW capability
3152 * register (if supported).
3154 priv->plat->enh_desc = priv->dma_cap.enh_desc;
3155 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
3156 priv->hw->pmt = priv->plat->pmt;
3158 /* TXCOE doesn't work in thresh DMA mode */
3159 if (priv->plat->force_thresh_dma_mode)
3160 priv->plat->tx_coe = 0;
3162 priv->plat->tx_coe = priv->dma_cap.tx_coe;
3164 /* In case of GMAC4 rx_coe is from HW cap register. */
3165 priv->plat->rx_coe = priv->dma_cap.rx_coe;
3167 if (priv->dma_cap.rx_coe_type2)
3168 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
3169 else if (priv->dma_cap.rx_coe_type1)
3170 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
3173 pr_info(" No HW DMA feature register supported");
3175 /* To use alternate (extended), normal or GMAC4 descriptor structures */
3176 if (priv->synopsys_id >= DWMAC_CORE_4_00)
3177 priv->hw->desc = &dwmac4_desc_ops;
3179 stmmac_selec_desc_mode(priv);
3181 if (priv->plat->rx_coe) {
3182 priv->hw->rx_csum = priv->plat->rx_coe;
3183 pr_info(" RX Checksum Offload Engine supported\n");
3184 if (priv->synopsys_id < DWMAC_CORE_4_00)
3185 pr_info("\tCOE Type %d\n", priv->hw->rx_csum);
3187 if (priv->plat->tx_coe)
3188 pr_info(" TX Checksum insertion supported\n");
3190 if (priv->plat->pmt) {
3191 pr_info(" Wake-Up On Lan supported\n");
3192 device_set_wakeup_capable(priv->device, 1);
3195 if (priv->dma_cap.tsoen)
3196 pr_info(" TSO supported\n");
3203 * @device: device pointer
3204 * @plat_dat: platform data pointer
3205 * @res: stmmac resource pointer
3206 * Description: this is the main probe function used to
3207 * call the alloc_etherdev, allocate the priv structure.
3209 * returns 0 on success, otherwise errno.
3211 int stmmac_dvr_probe(struct device *device,
3212 struct plat_stmmacenet_data *plat_dat,
3213 struct stmmac_resources *res)
3216 struct net_device *ndev = NULL;
3217 struct stmmac_priv *priv;
3219 ndev = alloc_etherdev(sizeof(struct stmmac_priv));
3223 SET_NETDEV_DEV(ndev, device);
3225 priv = netdev_priv(ndev);
3226 priv->device = device;
3229 stmmac_set_ethtool_ops(ndev);
3230 priv->pause = pause;
3231 priv->plat = plat_dat;
3232 priv->ioaddr = res->addr;
3233 priv->dev->base_addr = (unsigned long)res->addr;
3235 priv->dev->irq = res->irq;
3236 priv->wol_irq = res->wol_irq;
3237 priv->lpi_irq = res->lpi_irq;
3240 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN);
3242 dev_set_drvdata(device, priv->dev);
3244 /* Verify driver arguments */
3245 stmmac_verify_args();
3247 /* Override with kernel parameters if supplied XXX CRS XXX
3248 * this needs to have multiple instances
3250 if ((phyaddr >= 0) && (phyaddr <= 31))
3251 priv->plat->phy_addr = phyaddr;
3253 priv->stmmac_clk = devm_clk_get(priv->device, STMMAC_RESOURCE_NAME);
3254 if (IS_ERR(priv->stmmac_clk)) {
3255 dev_warn(priv->device, "%s: warning: cannot get CSR clock\n",
3257 /* If failed to obtain stmmac_clk and specific clk_csr value
3258 * is NOT passed from the platform, probe fail.
3260 if (!priv->plat->clk_csr) {
3261 ret = PTR_ERR(priv->stmmac_clk);
3264 priv->stmmac_clk = NULL;
3267 clk_prepare_enable(priv->stmmac_clk);
3269 priv->pclk = devm_clk_get(priv->device, "pclk");
3270 if (IS_ERR(priv->pclk)) {
3271 if (PTR_ERR(priv->pclk) == -EPROBE_DEFER) {
3272 ret = -EPROBE_DEFER;
3273 goto error_pclk_get;
3277 clk_prepare_enable(priv->pclk);
3279 priv->stmmac_rst = devm_reset_control_get(priv->device,
3280 STMMAC_RESOURCE_NAME);
3281 if (IS_ERR(priv->stmmac_rst)) {
3282 if (PTR_ERR(priv->stmmac_rst) == -EPROBE_DEFER) {
3283 ret = -EPROBE_DEFER;
3286 dev_info(priv->device, "no reset control found\n");
3287 priv->stmmac_rst = NULL;
3289 if (priv->stmmac_rst)
3290 reset_control_deassert(priv->stmmac_rst);
3292 /* Init MAC and get the capabilities */
3293 ret = stmmac_hw_init(priv);
3297 ndev->netdev_ops = &stmmac_netdev_ops;
3299 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
3302 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
3303 ndev->hw_features |= NETIF_F_TSO;
3305 pr_info(" TSO feature enabled\n");
3307 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
3308 ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
3309 #ifdef STMMAC_VLAN_TAG_USED
3310 /* Both mac100 and gmac support receive VLAN tag detection */
3311 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3313 priv->msg_enable = netif_msg_init(debug, default_msg_level);
3316 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
3318 /* Rx Watchdog is available in the COREs newer than the 3.40.
3319 * In some case, for example on bugged HW this feature
3320 * has to be disable and this can be done by passing the
3321 * riwt_off field from the platform.
3323 if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
3325 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
3328 netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
3330 spin_lock_init(&priv->lock);
3331 spin_lock_init(&priv->tx_lock);
3333 ret = register_netdev(ndev);
3335 pr_err("%s: ERROR %i registering the device\n", __func__, ret);
3336 goto error_netdev_register;
3339 /* If a specific clk_csr value is passed from the platform
3340 * this means that the CSR Clock Range selection cannot be
3341 * changed at run-time and it is fixed. Viceversa the driver'll try to
3342 * set the MDC clock dynamically according to the csr actual
3345 if (!priv->plat->clk_csr)
3346 stmmac_clk_csr_set(priv);
3348 priv->clk_csr = priv->plat->clk_csr;
3350 stmmac_check_pcs_mode(priv);
3352 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
3353 priv->hw->pcs != STMMAC_PCS_TBI &&
3354 priv->hw->pcs != STMMAC_PCS_RTBI) {
3355 /* MDIO bus Registration */
3356 ret = stmmac_mdio_register(ndev);
3358 pr_debug("%s: MDIO bus (id: %d) registration failed",
3359 __func__, priv->plat->bus_id);
3360 goto error_mdio_register;
3366 error_mdio_register:
3367 unregister_netdev(ndev);
3368 error_netdev_register:
3369 netif_napi_del(&priv->napi);
3371 clk_disable_unprepare(priv->pclk);
3373 clk_disable_unprepare(priv->stmmac_clk);
3379 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
3383 * @dev: device pointer
3384 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
3385 * changes the link status, releases the DMA descriptor rings.
3387 int stmmac_dvr_remove(struct device *dev)
3389 struct net_device *ndev = dev_get_drvdata(dev);
3390 struct stmmac_priv *priv = netdev_priv(ndev);
3392 pr_info("%s:\n\tremoving driver", __func__);
3394 priv->hw->dma->stop_rx(priv->ioaddr);
3395 priv->hw->dma->stop_tx(priv->ioaddr);
3397 stmmac_set_mac(priv->ioaddr, false);
3398 netif_carrier_off(ndev);
3399 unregister_netdev(ndev);
3400 of_node_put(priv->plat->phy_node);
3401 if (priv->stmmac_rst)
3402 reset_control_assert(priv->stmmac_rst);
3403 clk_disable_unprepare(priv->pclk);
3404 clk_disable_unprepare(priv->stmmac_clk);
3405 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
3406 priv->hw->pcs != STMMAC_PCS_TBI &&
3407 priv->hw->pcs != STMMAC_PCS_RTBI)
3408 stmmac_mdio_unregister(ndev);
3413 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
3416 * stmmac_suspend - suspend callback
3417 * @dev: device pointer
3418 * Description: this is the function to suspend the device and it is called
3419 * by the platform driver to stop the network queue, release the resources,
3420 * program the PMT register (for WoL), clean and release driver resources.
3422 int stmmac_suspend(struct device *dev)
3424 struct net_device *ndev = dev_get_drvdata(dev);
3425 struct stmmac_priv *priv = netdev_priv(ndev);
3426 unsigned long flags;
3428 if (!ndev || !netif_running(ndev))
3432 phy_stop(priv->phydev);
3434 spin_lock_irqsave(&priv->lock, flags);
3436 netif_device_detach(ndev);
3437 netif_stop_queue(ndev);
3439 napi_disable(&priv->napi);
3441 /* Stop TX/RX DMA */
3442 priv->hw->dma->stop_tx(priv->ioaddr);
3443 priv->hw->dma->stop_rx(priv->ioaddr);
3445 /* Enable Power down mode by programming the PMT regs */
3446 if (device_may_wakeup(priv->device)) {
3447 priv->hw->mac->pmt(priv->hw, priv->wolopts);
3450 stmmac_set_mac(priv->ioaddr, false);
3451 pinctrl_pm_select_sleep_state(priv->device);
3452 /* Disable clock in case of PWM is off */
3453 clk_disable(priv->pclk);
3454 clk_disable(priv->stmmac_clk);
3456 spin_unlock_irqrestore(&priv->lock, flags);
3460 priv->oldduplex = -1;
3463 EXPORT_SYMBOL_GPL(stmmac_suspend);
3466 * stmmac_resume - resume callback
3467 * @dev: device pointer
3468 * Description: when resume this function is invoked to setup the DMA and CORE
3469 * in a usable state.
3471 int stmmac_resume(struct device *dev)
3473 struct net_device *ndev = dev_get_drvdata(dev);
3474 struct stmmac_priv *priv = netdev_priv(ndev);
3475 unsigned long flags;
3477 if (!netif_running(ndev))
3480 /* Power Down bit, into the PM register, is cleared
3481 * automatically as soon as a magic packet or a Wake-up frame
3482 * is received. Anyway, it's better to manually clear
3483 * this bit because it can generate problems while resuming
3484 * from another devices (e.g. serial console).
3486 if (device_may_wakeup(priv->device)) {
3487 spin_lock_irqsave(&priv->lock, flags);
3488 priv->hw->mac->pmt(priv->hw, 0);
3489 spin_unlock_irqrestore(&priv->lock, flags);
3492 pinctrl_pm_select_default_state(priv->device);
3493 /* enable the clk prevously disabled */
3494 clk_enable(priv->stmmac_clk);
3495 clk_enable(priv->pclk);
3496 /* reset the phy so that it's ready */
3498 stmmac_mdio_reset(priv->mii);
3501 netif_device_attach(ndev);
3503 spin_lock_irqsave(&priv->lock, flags);
3509 /* reset private mss value to force mss context settings at
3510 * next tso xmit (only used for gmac4).
3514 stmmac_clear_descriptors(priv);
3516 stmmac_hw_setup(ndev, false);
3517 stmmac_init_tx_coalesce(priv);
3518 stmmac_set_rx_mode(ndev);
3520 napi_enable(&priv->napi);
3522 netif_start_queue(ndev);
3524 spin_unlock_irqrestore(&priv->lock, flags);
3527 phy_start(priv->phydev);
3531 EXPORT_SYMBOL_GPL(stmmac_resume);
3534 static int __init stmmac_cmdline_opt(char *str)
3540 while ((opt = strsep(&str, ",")) != NULL) {
3541 if (!strncmp(opt, "debug:", 6)) {
3542 if (kstrtoint(opt + 6, 0, &debug))
3544 } else if (!strncmp(opt, "phyaddr:", 8)) {
3545 if (kstrtoint(opt + 8, 0, &phyaddr))
3547 } else if (!strncmp(opt, "buf_sz:", 7)) {
3548 if (kstrtoint(opt + 7, 0, &buf_sz))
3550 } else if (!strncmp(opt, "tc:", 3)) {
3551 if (kstrtoint(opt + 3, 0, &tc))
3553 } else if (!strncmp(opt, "watchdog:", 9)) {
3554 if (kstrtoint(opt + 9, 0, &watchdog))
3556 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
3557 if (kstrtoint(opt + 10, 0, &flow_ctrl))
3559 } else if (!strncmp(opt, "pause:", 6)) {
3560 if (kstrtoint(opt + 6, 0, &pause))
3562 } else if (!strncmp(opt, "eee_timer:", 10)) {
3563 if (kstrtoint(opt + 10, 0, &eee_timer))
3565 } else if (!strncmp(opt, "chain_mode:", 11)) {
3566 if (kstrtoint(opt + 11, 0, &chain_mode))
3573 pr_err("%s: ERROR broken module parameter conversion", __func__);
3577 __setup("stmmaceth=", stmmac_cmdline_opt);
3580 static int __init stmmac_init(void)
3582 #ifdef CONFIG_DEBUG_FS
3583 /* Create debugfs main directory if it doesn't exist yet */
3584 if (!stmmac_fs_dir) {
3585 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
3587 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
3588 pr_err("ERROR %s, debugfs create directory failed\n",
3589 STMMAC_RESOURCE_NAME);
3599 static void __exit stmmac_exit(void)
3601 #ifdef CONFIG_DEBUG_FS
3602 debugfs_remove_recursive(stmmac_fs_dir);
3606 module_init(stmmac_init)
3607 module_exit(stmmac_exit)
3609 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
3610 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
3611 MODULE_LICENSE("GPL");