drivers/net/ethernet/ti/cpsw.c

   1 /*
   2  * Texas Instruments Ethernet Switch Driver
   3  *
   4  * Copyright (C) 2012 Texas Instruments
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/io.h>
  18 #include <linux/clk.h>
  19 #include <linux/timer.h>
  20 #include <linux/module.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/irqreturn.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/if_ether.h>
  25 #include <linux/etherdevice.h>
  26 #include <linux/netdevice.h>
  27 #include <linux/net_tstamp.h>
  28 #include <linux/phy.h>
  29 #include <linux/workqueue.h>
  30 #include <linux/delay.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/of.h>
  33 #include <linux/of_net.h>
  34 #include <linux/of_device.h>
  35 #include <linux/if_vlan.h>
  36
  37 #include <linux/pinctrl/consumer.h>
  38
  39 #include "cpsw.h"
  40 #include "cpsw_ale.h"
  41 #include "cpts.h"
  42 #include "davinci_cpdma.h"
  43
  44 #define CPSW_DEBUG      (NETIF_MSG_HW           | NETIF_MSG_WOL         | \
  45                          NETIF_MSG_DRV          | NETIF_MSG_LINK        | \
  46                          NETIF_MSG_IFUP         | NETIF_MSG_INTR        | \
  47                          NETIF_MSG_PROBE        | NETIF_MSG_TIMER       | \
  48                          NETIF_MSG_IFDOWN       | NETIF_MSG_RX_ERR      | \
  49                          NETIF_MSG_TX_ERR       | NETIF_MSG_TX_DONE     | \
  50                          NETIF_MSG_PKTDATA      | NETIF_MSG_TX_QUEUED   | \
  51                          NETIF_MSG_RX_STATUS)
  52
  53 #define cpsw_info(priv, type, format, ...)              \
  54 do {                                                            \
  55         if (netif_msg_##type(priv) && net_ratelimit())          \
  56                 dev_info(priv->dev, format, ## __VA_ARGS__);    \
  57 } while (0)
  58
  59 #define cpsw_err(priv, type, format, ...)               \
  60 do {                                                            \
  61         if (netif_msg_##type(priv) && net_ratelimit())          \
  62                 dev_err(priv->dev, format, ## __VA_ARGS__);     \
  63 } while (0)
  64
  65 #define cpsw_dbg(priv, type, format, ...)               \
  66 do {                                                            \
  67         if (netif_msg_##type(priv) && net_ratelimit())          \
  68                 dev_dbg(priv->dev, format, ## __VA_ARGS__);     \
  69 } while (0)
  70
  71 #define cpsw_notice(priv, type, format, ...)            \
  72 do {                                                            \
  73         if (netif_msg_##type(priv) && net_ratelimit())          \
  74                 dev_notice(priv->dev, format, ## __VA_ARGS__);  \
  75 } while (0)
  76
  77 #define ALE_ALL_PORTS           0x7
  78
  79 #define CPSW_MAJOR_VERSION(reg)         (reg >> 8 & 0x7)
  80 #define CPSW_MINOR_VERSION(reg)         (reg & 0xff)
  81 #define CPSW_RTL_VERSION(reg)           ((reg >> 11) & 0x1f)
  82
  83 #define CPSW_VERSION_1          0x19010a
  84 #define CPSW_VERSION_2          0x19010c
  85 #define CPSW_VERSION_3          0x19010f
  86 #define CPSW_VERSION_4          0x190112
  87
  88 #define HOST_PORT_NUM           0
  89 #define SLIVER_SIZE             0x40
  90
  91 #define CPSW1_HOST_PORT_OFFSET  0x028
  92 #define CPSW1_SLAVE_OFFSET      0x050
  93 #define CPSW1_SLAVE_SIZE        0x040
  94 #define CPSW1_CPDMA_OFFSET      0x100
  95 #define CPSW1_STATERAM_OFFSET   0x200
  96 #define CPSW1_HW_STATS          0x400
  97 #define CPSW1_CPTS_OFFSET       0x500
  98 #define CPSW1_ALE_OFFSET        0x600
  99 #define CPSW1_SLIVER_OFFSET     0x700
 100
 101 #define CPSW2_HOST_PORT_OFFSET  0x108
 102 #define CPSW2_SLAVE_OFFSET      0x200
 103 #define CPSW2_SLAVE_SIZE        0x100
 104 #define CPSW2_CPDMA_OFFSET      0x800
 105 #define CPSW2_HW_STATS          0x900
 106 #define CPSW2_STATERAM_OFFSET   0xa00
 107 #define CPSW2_CPTS_OFFSET       0xc00
 108 #define CPSW2_ALE_OFFSET        0xd00
 109 #define CPSW2_SLIVER_OFFSET     0xd80
 110 #define CPSW2_BD_OFFSET         0x2000
 111
 112 #define CPDMA_RXTHRESH          0x0c0
 113 #define CPDMA_RXFREE            0x0e0
 114 #define CPDMA_TXHDP             0x00
 115 #define CPDMA_RXHDP             0x20
 116 #define CPDMA_TXCP              0x40
 117 #define CPDMA_RXCP              0x60
 118
 119 #define CPSW_POLL_WEIGHT        64
 120 #define CPSW_MIN_PACKET_SIZE    60
 121 #define CPSW_MAX_PACKET_SIZE    (1500 + 14 + 4 + 4)
 122
 123 #define RX_PRIORITY_MAPPING     0x76543210
 124 #define TX_PRIORITY_MAPPING     0x33221100
 125 #define CPDMA_TX_PRIORITY_MAP   0x76543210
 126
 127 #define CPSW_VLAN_AWARE         BIT(1)
 128 #define CPSW_ALE_VLAN_AWARE     1
 129
 130 #define CPSW_FIFO_NORMAL_MODE           (0 << 15)
 131 #define CPSW_FIFO_DUAL_MAC_MODE         (1 << 15)
 132 #define CPSW_FIFO_RATE_LIMIT_MODE       (2 << 15)
 133
 134 #define CPSW_INTPACEEN          (0x3f << 16)
 135 #define CPSW_INTPRESCALE_MASK   (0x7FF << 0)
 136 #define CPSW_CMINTMAX_CNT       63
 137 #define CPSW_CMINTMIN_CNT       2
 138 #define CPSW_CMINTMAX_INTVL     (1000 / CPSW_CMINTMIN_CNT)
 139 #define CPSW_CMINTMIN_INTVL     ((1000 / CPSW_CMINTMAX_CNT) + 1)
 140
 141 #define cpsw_enable_irq(priv)   \
 142         do {                    \
 143                 u32 i;          \
 144                 for (i = 0; i < priv->num_irqs; i++) \
 145                         enable_irq(priv->irqs_table[i]); \
 146         } while (0);
 147 #define cpsw_disable_irq(priv)  \
 148         do {                    \
 149                 u32 i;          \
 150                 for (i = 0; i < priv->num_irqs; i++) \
 151                         disable_irq_nosync(priv->irqs_table[i]); \
 152         } while (0);
 153
 154 #define cpsw_slave_index(priv)                          \
 155                 ((priv->data.dual_emac) ? priv->emac_port :     \
 156                 priv->data.active_slave)
 157
 158 static int debug_level;
 159 module_param(debug_level, int, 0);
 160 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
 161
 162 static int ale_ageout = 10;
 163 module_param(ale_ageout, int, 0);
 164 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
 165
 166 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
 167 module_param(rx_packet_max, int, 0);
 168 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
 169
 170 struct cpsw_wr_regs {
 171         u32     id_ver;
 172         u32     soft_reset;
 173         u32     control;
 174         u32     int_control;
 175         u32     rx_thresh_en;
 176         u32     rx_en;
 177         u32     tx_en;
 178         u32     misc_en;
 179         u32     mem_allign1[8];
 180         u32     rx_thresh_stat;
 181         u32     rx_stat;
 182         u32     tx_stat;
 183         u32     misc_stat;
 184         u32     mem_allign2[8];
 185         u32     rx_imax;
 186         u32     tx_imax;
 187
 188 };
 189
 190 struct cpsw_ss_regs {
 191         u32     id_ver;
 192         u32     control;
 193         u32     soft_reset;
 194         u32     stat_port_en;
 195         u32     ptype;
 196         u32     soft_idle;
 197         u32     thru_rate;
 198         u32     gap_thresh;
 199         u32     tx_start_wds;
 200         u32     flow_control;
 201         u32     vlan_ltype;
 202         u32     ts_ltype;
 203         u32     dlr_ltype;
 204 };
 205
 206 /* CPSW_PORT_V1 */
 207 #define CPSW1_MAX_BLKS      0x00 /* Maximum FIFO Blocks */
 208 #define CPSW1_BLK_CNT       0x04 /* FIFO Block Usage Count (Read Only) */
 209 #define CPSW1_TX_IN_CTL     0x08 /* Transmit FIFO Control */
 210 #define CPSW1_PORT_VLAN     0x0c /* VLAN Register */
 211 #define CPSW1_TX_PRI_MAP    0x10 /* Tx Header Priority to Switch Pri Mapping */
 212 #define CPSW1_TS_CTL        0x14 /* Time Sync Control */
 213 #define CPSW1_TS_SEQ_LTYPE  0x18 /* Time Sync Sequence ID Offset and Msg Type */
 214 #define CPSW1_TS_VLAN       0x1c /* Time Sync VLAN1 and VLAN2 */
 215
 216 /* CPSW_PORT_V2 */
 217 #define CPSW2_CONTROL       0x00 /* Control Register */
 218 #define CPSW2_MAX_BLKS      0x08 /* Maximum FIFO Blocks */
 219 #define CPSW2_BLK_CNT       0x0c /* FIFO Block Usage Count (Read Only) */
 220 #define CPSW2_TX_IN_CTL     0x10 /* Transmit FIFO Control */
 221 #define CPSW2_PORT_VLAN     0x14 /* VLAN Register */
 222 #define CPSW2_TX_PRI_MAP    0x18 /* Tx Header Priority to Switch Pri Mapping */
 223 #define CPSW2_TS_SEQ_MTYPE  0x1c /* Time Sync Sequence ID Offset and Msg Type */
 224
 225 /* CPSW_PORT_V1 and V2 */
 226 #define SA_LO               0x20 /* CPGMAC_SL Source Address Low */
 227 #define SA_HI               0x24 /* CPGMAC_SL Source Address High */
 228 #define SEND_PERCENT        0x28 /* Transmit Queue Send Percentages */
 229
 230 /* CPSW_PORT_V2 only */
 231 #define RX_DSCP_PRI_MAP0    0x30 /* Rx DSCP Priority to Rx Packet Mapping */
 232 #define RX_DSCP_PRI_MAP1    0x34 /* Rx DSCP Priority to Rx Packet Mapping */
 233 #define RX_DSCP_PRI_MAP2    0x38 /* Rx DSCP Priority to Rx Packet Mapping */
 234 #define RX_DSCP_PRI_MAP3    0x3c /* Rx DSCP Priority to Rx Packet Mapping */
 235 #define RX_DSCP_PRI_MAP4    0x40 /* Rx DSCP Priority to Rx Packet Mapping */
 236 #define RX_DSCP_PRI_MAP5    0x44 /* Rx DSCP Priority to Rx Packet Mapping */
 237 #define RX_DSCP_PRI_MAP6    0x48 /* Rx DSCP Priority to Rx Packet Mapping */
 238 #define RX_DSCP_PRI_MAP7    0x4c /* Rx DSCP Priority to Rx Packet Mapping */
 239
 240 /* Bit definitions for the CPSW2_CONTROL register */
 241 #define PASS_PRI_TAGGED     (1<<24) /* Pass Priority Tagged */
 242 #define VLAN_LTYPE2_EN      (1<<21) /* VLAN LTYPE 2 enable */
 243 #define VLAN_LTYPE1_EN      (1<<20) /* VLAN LTYPE 1 enable */
 244 #define DSCP_PRI_EN         (1<<16) /* DSCP Priority Enable */
 245 #define TS_320              (1<<14) /* Time Sync Dest Port 320 enable */
 246 #define TS_319              (1<<13) /* Time Sync Dest Port 319 enable */
 247 #define TS_132              (1<<12) /* Time Sync Dest IP Addr 132 enable */
 248 #define TS_131              (1<<11) /* Time Sync Dest IP Addr 131 enable */
 249 #define TS_130              (1<<10) /* Time Sync Dest IP Addr 130 enable */
 250 #define TS_129              (1<<9)  /* Time Sync Dest IP Addr 129 enable */
 251 #define TS_BIT8             (1<<8)  /* ts_ttl_nonzero? */
 252 #define TS_ANNEX_D_EN       (1<<4)  /* Time Sync Annex D enable */
 253 #define TS_LTYPE2_EN        (1<<3)  /* Time Sync LTYPE 2 enable */
 254 #define TS_LTYPE1_EN        (1<<2)  /* Time Sync LTYPE 1 enable */
 255 #define TS_TX_EN            (1<<1)  /* Time Sync Transmit Enable */
 256 #define TS_RX_EN            (1<<0)  /* Time Sync Receive Enable */
 257
 258 #define CTRL_TS_BITS \
 259         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 | TS_BIT8 | \
 260          TS_ANNEX_D_EN | TS_LTYPE1_EN)
 261
 262 #define CTRL_ALL_TS_MASK (CTRL_TS_BITS | TS_TX_EN | TS_RX_EN)
 263 #define CTRL_TX_TS_BITS  (CTRL_TS_BITS | TS_TX_EN)
 264 #define CTRL_RX_TS_BITS  (CTRL_TS_BITS | TS_RX_EN)
 265
 266 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
 267 #define TS_SEQ_ID_OFFSET_SHIFT   (16)    /* Time Sync Sequence ID Offset */
 268 #define TS_SEQ_ID_OFFSET_MASK    (0x3f)
 269 #define TS_MSG_TYPE_EN_SHIFT     (0)     /* Time Sync Message Type Enable */
 270 #define TS_MSG_TYPE_EN_MASK      (0xffff)
 271
 272 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
 273 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
 274
 275 /* Bit definitions for the CPSW1_TS_CTL register */
 276 #define CPSW_V1_TS_RX_EN                BIT(0)
 277 #define CPSW_V1_TS_TX_EN                BIT(4)
 278 #define CPSW_V1_MSG_TYPE_OFS            16
 279
 280 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
 281 #define CPSW_V1_SEQ_ID_OFS_SHIFT        16
 282
 283 struct cpsw_host_regs {
 284         u32     max_blks;
 285         u32     blk_cnt;
 286         u32     tx_in_ctl;
 287         u32     port_vlan;
 288         u32     tx_pri_map;
 289         u32     cpdma_tx_pri_map;
 290         u32     cpdma_rx_chan_map;
 291 };
 292
 293 struct cpsw_sliver_regs {
 294         u32     id_ver;
 295         u32     mac_control;
 296         u32     mac_status;
 297         u32     soft_reset;
 298         u32     rx_maxlen;
 299         u32     __reserved_0;
 300         u32     rx_pause;
 301         u32     tx_pause;
 302         u32     __reserved_1;
 303         u32     rx_pri_map;
 304 };
 305
 306 struct cpsw_hw_stats {
 307         u32     rxgoodframes;
 308         u32     rxbroadcastframes;
 309         u32     rxmulticastframes;
 310         u32     rxpauseframes;
 311         u32     rxcrcerrors;
 312         u32     rxaligncodeerrors;
 313         u32     rxoversizedframes;
 314         u32     rxjabberframes;
 315         u32     rxundersizedframes;
 316         u32     rxfragments;
 317         u32     __pad_0[2];
 318         u32     rxoctets;
 319         u32     txgoodframes;
 320         u32     txbroadcastframes;
 321         u32     txmulticastframes;
 322         u32     txpauseframes;
 323         u32     txdeferredframes;
 324         u32     txcollisionframes;
 325         u32     txsinglecollframes;
 326         u32     txmultcollframes;
 327         u32     txexcessivecollisions;
 328         u32     txlatecollisions;
 329         u32     txunderrun;
 330         u32     txcarriersenseerrors;
 331         u32     txoctets;
 332         u32     octetframes64;
 333         u32     octetframes65t127;
 334         u32     octetframes128t255;
 335         u32     octetframes256t511;
 336         u32     octetframes512t1023;
 337         u32     octetframes1024tup;
 338         u32     netoctets;
 339         u32     rxsofoverruns;
 340         u32     rxmofoverruns;
 341         u32     rxdmaoverruns;
 342 };
 343
 344 struct cpsw_slave {
 345         void __iomem                    *regs;
 346         struct cpsw_sliver_regs __iomem *sliver;
 347         int                             slave_num;
 348         u32                             mac_control;
 349         struct cpsw_slave_data          *data;
 350         struct phy_device               *phy;
 351         struct net_device               *ndev;
 352         u32                             port_vlan;
 353         u32                             open_stat;
 354 };
 355
 356 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
 357 {
 358         return __raw_readl(slave->regs + offset);
 359 }
 360
 361 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
 362 {
 363         __raw_writel(val, slave->regs + offset);
 364 }
 365
 366 struct cpsw_priv {
 367         spinlock_t                      lock;
 368         struct platform_device          *pdev;
 369         struct net_device               *ndev;
 370         struct napi_struct              napi;
 371         struct device                   *dev;
 372         struct cpsw_platform_data       data;
 373         struct cpsw_ss_regs __iomem     *regs;
 374         struct cpsw_wr_regs __iomem     *wr_regs;
 375         u8 __iomem                      *hw_stats;
 376         struct cpsw_host_regs __iomem   *host_port_regs;
 377         u32                             msg_enable;
 378         u32                             version;
 379         u32                             coal_intvl;
 380         u32                             bus_freq_mhz;
 381         struct net_device_stats         stats;
 382         int                             rx_packet_max;
 383         int                             host_port;
 384         struct clk                      *clk;
 385         u8                              mac_addr[ETH_ALEN];
 386         struct cpsw_slave               *slaves;
 387         struct cpdma_ctlr               *dma;
 388         struct cpdma_chan               *txch, *rxch;
 389         struct cpsw_ale                 *ale;
 390         /* snapshot of IRQ numbers */
 391         u32 irqs_table[4];
 392         u32 num_irqs;
 393         bool irq_enabled;
 394         struct cpts *cpts;
 395         u32 emac_port;
 396 };
 397
 398 struct cpsw_stats {
 399         char stat_string[ETH_GSTRING_LEN];
 400         int type;
 401         int sizeof_stat;
 402         int stat_offset;
 403 };
 404
 405 enum {
 406         CPSW_STATS,
 407         CPDMA_RX_STATS,
 408         CPDMA_TX_STATS,
 409 };
 410
 411 #define CPSW_STAT(m)            CPSW_STATS,                             \
 412                                 sizeof(((struct cpsw_hw_stats *)0)->m), \
 413                                 offsetof(struct cpsw_hw_stats, m)
 414 #define CPDMA_RX_STAT(m)        CPDMA_RX_STATS,                            \
 415                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 416                                 offsetof(struct cpdma_chan_stats, m)
 417 #define CPDMA_TX_STAT(m)        CPDMA_TX_STATS,                            \
 418                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 419                                 offsetof(struct cpdma_chan_stats, m)
 420
 421 static const struct cpsw_stats cpsw_gstrings_stats[] = {
 422         { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
 423         { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
 424         { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
 425         { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
 426         { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
 427         { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
 428         { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
 429         { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
 430         { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
 431         { "Rx Fragments", CPSW_STAT(rxfragments) },
 432         { "Rx Octets", CPSW_STAT(rxoctets) },
 433         { "Good Tx Frames", CPSW_STAT(txgoodframes) },
 434         { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
 435         { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
 436         { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
 437         { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
 438         { "Collisions", CPSW_STAT(txcollisionframes) },
 439         { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
 440         { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
 441         { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
 442         { "Late Collisions", CPSW_STAT(txlatecollisions) },
 443         { "Tx Underrun", CPSW_STAT(txunderrun) },
 444         { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
 445         { "Tx Octets", CPSW_STAT(txoctets) },
 446         { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
 447         { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
 448         { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
 449         { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
 450         { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
 451         { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
 452         { "Net Octets", CPSW_STAT(netoctets) },
 453         { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
 454         { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
 455         { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
 456         { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) },
 457         { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
 458         { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
 459         { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) },
 460         { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
 461         { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
 462         { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
 463         { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
 464         { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
 465         { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
 466         { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) },
 467         { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) },
 468         { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
 469         { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) },
 470         { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) },
 471         { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) },
 472         { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) },
 473         { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) },
 474         { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) },
 475         { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) },
 476         { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) },
 477         { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) },
 478         { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) },
 479         { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) },
 480         { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) },
 481         { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) },
 482 };
 483
 484 #define CPSW_STATS_LEN  ARRAY_SIZE(cpsw_gstrings_stats)
 485
 486 #define napi_to_priv(napi)      container_of(napi, struct cpsw_priv, napi)
 487 #define for_each_slave(priv, func, arg...)                              \
 488         do {                                                            \
 489                 struct cpsw_slave *slave;                               \
 490                 int n;                                                  \
 491                 if (priv->data.dual_emac)                               \
 492                         (func)((priv)->slaves + priv->emac_port, ##arg);\
 493                 else                                                    \
 494                         for (n = (priv)->data.slaves,                   \
 495                                         slave = (priv)->slaves;         \
 496                                         n; n--)                         \
 497                                 (func)(slave++, ##arg);                 \
 498         } while (0)
 499 #define cpsw_get_slave_ndev(priv, __slave_no__)                         \
 500         (priv->slaves[__slave_no__].ndev)
 501 #define cpsw_get_slave_priv(priv, __slave_no__)                         \
 502         ((priv->slaves[__slave_no__].ndev) ?                            \
 503                 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL)    \
 504
 505 #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb)         \
 506         do {                                                            \
 507                 if (!priv->data.dual_emac)                              \
 508                         break;                                          \
 509                 if (CPDMA_RX_SOURCE_PORT(status) == 1) {                \
 510                         ndev = cpsw_get_slave_ndev(priv, 0);            \
 511                         priv = netdev_priv(ndev);                       \
 512                         skb->dev = ndev;                                \
 513                 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) {         \
 514                         ndev = cpsw_get_slave_ndev(priv, 1);            \
 515                         priv = netdev_priv(ndev);                       \
 516                         skb->dev = ndev;                                \
 517                 }                                                       \
 518         } while (0)
 519 #define cpsw_add_mcast(priv, addr)                                      \
 520         do {                                                            \
 521                 if (priv->data.dual_emac) {                             \
 522                         struct cpsw_slave *slave = priv->slaves +       \
 523                                                 priv->emac_port;        \
 524                         int slave_port = cpsw_get_slave_port(priv,      \
 525                                                 slave->slave_num);      \
 526                         cpsw_ale_add_mcast(priv->ale, addr,             \
 527                                 1 << slave_port | 1 << priv->host_port, \
 528                                 ALE_VLAN, slave->port_vlan, 0);         \
 529                 } else {                                                \
 530                         cpsw_ale_add_mcast(priv->ale, addr,             \
 531                                 ALE_ALL_PORTS << priv->host_port,       \
 532                                 0, 0, 0);                               \
 533                 }                                                       \
 534         } while (0)
 535
 536 static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
 537 {
 538         if (priv->host_port == 0)
 539                 return slave_num + 1;
 540         else
 541                 return slave_num;
 542 }
 543
 544 static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
 545 {
 546         struct cpsw_priv *priv = netdev_priv(ndev);
 547         struct cpsw_ale *ale = priv->ale;
 548         int i;
 549
 550         if (priv->data.dual_emac) {
 551                 bool flag = false;
 552
 553                 /* Enabling promiscuous mode for one interface will be
 554                  * common for both the interface as the interface shares
 555                  * the same hardware resource.
 556                  */
 557                 for (i = 0; i <= priv->data.slaves; i++)
 558                         if (priv->slaves[i].ndev->flags & IFF_PROMISC)
 559                                 flag = true;
 560
 561                 if (!enable && flag) {
 562                         enable = true;
 563                         dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
 564                 }
 565
 566                 if (enable) {
 567                         /* Enable Bypass */
 568                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
 569
 570                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 571                 } else {
 572                         /* Disable Bypass */
 573                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
 574                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 575                 }
 576         } else {
 577                 if (enable) {
 578                         unsigned long timeout = jiffies + HZ;
 579
 580                         /* Disable Learn for all ports */
 581                         for (i = 0; i <= priv->data.slaves; i++) {
 582                                 cpsw_ale_control_set(ale, i,
 583                                                      ALE_PORT_NOLEARN, 1);
 584                                 cpsw_ale_control_set(ale, i,
 585                                                      ALE_PORT_NO_SA_UPDATE, 1);
 586                         }
 587
 588                         /* Clear All Untouched entries */
 589                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 590                         do {
 591                                 cpu_relax();
 592                                 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
 593                                         break;
 594                         } while (time_after(timeout, jiffies));
 595                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 596
 597                         /* Clear all mcast from ALE */
 598                         cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS <<
 599                                                  priv->host_port);
 600
 601                         /* Flood All Unicast Packets to Host port */
 602                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
 603                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 604                 } else {
 605                         /* Flood All Unicast Packets to Host port */
 606                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
 607
 608                         /* Enable Learn for all ports */
 609                         for (i = 0; i <= priv->data.slaves; i++) {
 610                                 cpsw_ale_control_set(ale, i,
 611                                                      ALE_PORT_NOLEARN, 0);
 612                                 cpsw_ale_control_set(ale, i,
 613                                                      ALE_PORT_NO_SA_UPDATE, 0);
 614                         }
 615                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 616                 }
 617         }
 618 }
 619
 620 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
 621 {
 622         struct cpsw_priv *priv = netdev_priv(ndev);
 623
 624         if (ndev->flags & IFF_PROMISC) {
 625                 /* Enable promiscuous mode */
 626                 cpsw_set_promiscious(ndev, true);
 627                 return;
 628         } else {
 629                 /* Disable promiscuous mode */
 630                 cpsw_set_promiscious(ndev, false);
 631         }
 632
 633         /* Clear all mcast from ALE */
 634         cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port);
 635
 636         if (!netdev_mc_empty(ndev)) {
 637                 struct netdev_hw_addr *ha;
 638
 639                 /* program multicast address list into ALE register */
 640                 netdev_for_each_mc_addr(ha, ndev) {
 641                         cpsw_add_mcast(priv, (u8 *)ha->addr);
 642                 }
 643         }
 644 }
 645
 646 static void cpsw_intr_enable(struct cpsw_priv *priv)
 647 {
 648         __raw_writel(0xFF, &priv->wr_regs->tx_en);
 649         __raw_writel(0xFF, &priv->wr_regs->rx_en);
 650
 651         cpdma_ctlr_int_ctrl(priv->dma, true);
 652         return;
 653 }
 654
 655 static void cpsw_intr_disable(struct cpsw_priv *priv)
 656 {
 657         __raw_writel(0, &priv->wr_regs->tx_en);
 658         __raw_writel(0, &priv->wr_regs->rx_en);
 659
 660         cpdma_ctlr_int_ctrl(priv->dma, false);
 661         return;
 662 }
 663
 664 static void cpsw_tx_handler(void *token, int len, int status)
 665 {
 666         struct sk_buff          *skb = token;
 667         struct net_device       *ndev = skb->dev;
 668         struct cpsw_priv        *priv = netdev_priv(ndev);
 669
 670         /* Check whether the queue is stopped due to stalled tx dma, if the
 671          * queue is stopped then start the queue as we have free desc for tx
 672          */
 673         if (unlikely(netif_queue_stopped(ndev)))
 674                 netif_wake_queue(ndev);
 675         cpts_tx_timestamp(priv->cpts, skb);
 676         priv->stats.tx_packets++;
 677         priv->stats.tx_bytes += len;
 678         dev_kfree_skb_any(skb);
 679 }
 680
 681 static void cpsw_rx_handler(void *token, int len, int status)
 682 {
 683         struct sk_buff          *skb = token;
 684         struct sk_buff          *new_skb;
 685         struct net_device       *ndev = skb->dev;
 686         struct cpsw_priv        *priv = netdev_priv(ndev);
 687         int                     ret = 0;
 688
 689         cpsw_dual_emac_src_port_detect(status, priv, ndev, skb);
 690
 691         if (unlikely(status < 0)) {
 692                 /* the interface is going down, skbs are purged */
 693                 dev_kfree_skb_any(skb);
 694                 return;
 695         }
 696
 697         new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
 698         if (new_skb) {
 699                 skb_put(skb, len);
 700                 cpts_rx_timestamp(priv->cpts, skb);
 701                 skb->protocol = eth_type_trans(skb, ndev);
 702                 netif_receive_skb(skb);
 703                 priv->stats.rx_bytes += len;
 704                 priv->stats.rx_packets++;
 705         } else {
 706                 priv->stats.rx_dropped++;
 707                 new_skb = skb;
 708         }
 709
 710         ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data,
 711                         skb_tailroom(new_skb), 0);
 712         if (WARN_ON(ret < 0))
 713                 dev_kfree_skb_any(new_skb);
 714 }
 715
 716 static irqreturn_t cpsw_interrupt(int irq, void *dev_id)
 717 {
 718         struct cpsw_priv *priv = dev_id;
 719
 720         cpsw_intr_disable(priv);
 721         if (priv->irq_enabled == true) {
 722                 cpsw_disable_irq(priv);
 723                 priv->irq_enabled = false;
 724         }
 725
 726         if (netif_running(priv->ndev)) {
 727                 napi_schedule(&priv->napi);
 728                 return IRQ_HANDLED;
 729         }
 730
 731         priv = cpsw_get_slave_priv(priv, 1);
 732         if (!priv)
 733                 return IRQ_NONE;
 734
 735         if (netif_running(priv->ndev)) {
 736                 napi_schedule(&priv->napi);
 737                 return IRQ_HANDLED;
 738         }
 739         return IRQ_NONE;
 740 }
 741
 742 static int cpsw_poll(struct napi_struct *napi, int budget)
 743 {
 744         struct cpsw_priv        *priv = napi_to_priv(napi);
 745         int                     num_tx, num_rx;
 746
 747         num_tx = cpdma_chan_process(priv->txch, 128);
 748         if (num_tx)
 749                 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
 750
 751         num_rx = cpdma_chan_process(priv->rxch, budget);
 752         if (num_rx < budget) {
 753                 struct cpsw_priv *prim_cpsw;
 754
 755                 napi_complete(napi);
 756                 cpsw_intr_enable(priv);
 757                 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
 758                 prim_cpsw = cpsw_get_slave_priv(priv, 0);
 759                 if (prim_cpsw->irq_enabled == false) {
 760                         prim_cpsw->irq_enabled = true;
 761                         cpsw_enable_irq(priv);
 762                 }
 763         }
 764
 765         if (num_rx || num_tx)
 766                 cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n",
 767                          num_rx, num_tx);
 768
 769         return num_rx;
 770 }
 771
 772 static inline void soft_reset(const char *module, void __iomem *reg)
 773 {
 774         unsigned long timeout = jiffies + HZ;
 775
 776         __raw_writel(1, reg);
 777         do {
 778                 cpu_relax();
 779         } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
 780
 781         WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
 782 }
 783
 784 #define mac_hi(mac)     (((mac)[0] << 0) | ((mac)[1] << 8) |    \
 785                          ((mac)[2] << 16) | ((mac)[3] << 24))
 786 #define mac_lo(mac)     (((mac)[4] << 0) | ((mac)[5] << 8))
 787
 788 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
 789                                struct cpsw_priv *priv)
 790 {
 791         slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
 792         slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
 793 }
 794
 795 static void _cpsw_adjust_link(struct cpsw_slave *slave,
 796                               struct cpsw_priv *priv, bool *link)
 797 {
 798         struct phy_device       *phy = slave->phy;
 799         u32                     mac_control = 0;
 800         u32                     slave_port;
 801
 802         if (!phy)
 803                 return;
 804
 805         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
 806
 807         if (phy->link) {
 808                 mac_control = priv->data.mac_control;
 809
 810                 /* enable forwarding */
 811                 cpsw_ale_control_set(priv->ale, slave_port,
 812                                      ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
 813
 814                 if (phy->speed == 1000)
 815                         mac_control |= BIT(7);  /* GIGABITEN    */
 816                 if (phy->duplex)
 817                         mac_control |= BIT(0);  /* FULLDUPLEXEN */
 818
 819                 /* set speed_in input in case RMII mode is used in 100Mbps */
 820                 if (phy->speed == 100)
 821                         mac_control |= BIT(15);
 822                 else if (phy->speed == 10)
 823                         mac_control |= BIT(18); /* In Band mode */
 824
 825                 *link = true;
 826         } else {
 827                 mac_control = 0;
 828                 /* disable forwarding */
 829                 cpsw_ale_control_set(priv->ale, slave_port,
 830                                      ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
 831         }
 832
 833         if (mac_control != slave->mac_control) {
 834                 phy_print_status(phy);
 835                 __raw_writel(mac_control, &slave->sliver->mac_control);
 836         }
 837
 838         slave->mac_control = mac_control;
 839 }
 840
 841 static void cpsw_adjust_link(struct net_device *ndev)
 842 {
 843         struct cpsw_priv        *priv = netdev_priv(ndev);
 844         bool                    link = false;
 845
 846         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
 847
 848         if (link) {
 849                 netif_carrier_on(ndev);
 850                 if (netif_running(ndev))
 851                         netif_wake_queue(ndev);
 852         } else {
 853                 netif_carrier_off(ndev);
 854                 netif_stop_queue(ndev);
 855         }
 856 }
 857
 858 static int cpsw_get_coalesce(struct net_device *ndev,
 859                                 struct ethtool_coalesce *coal)
 860 {
 861         struct cpsw_priv *priv = netdev_priv(ndev);
 862
 863         coal->rx_coalesce_usecs = priv->coal_intvl;
 864         return 0;
 865 }
 866
 867 static int cpsw_set_coalesce(struct net_device *ndev,
 868                                 struct ethtool_coalesce *coal)
 869 {
 870         struct cpsw_priv *priv = netdev_priv(ndev);
 871         u32 int_ctrl;
 872         u32 num_interrupts = 0;
 873         u32 prescale = 0;
 874         u32 addnl_dvdr = 1;
 875         u32 coal_intvl = 0;
 876
 877         if (!coal->rx_coalesce_usecs)
 878                 return -EINVAL;
 879
 880         coal_intvl = coal->rx_coalesce_usecs;
 881
 882         int_ctrl =  readl(&priv->wr_regs->int_control);
 883         prescale = priv->bus_freq_mhz * 4;
 884
 885         if (coal_intvl < CPSW_CMINTMIN_INTVL)
 886                 coal_intvl = CPSW_CMINTMIN_INTVL;
 887
 888         if (coal_intvl > CPSW_CMINTMAX_INTVL) {
 889                 /* Interrupt pacer works with 4us Pulse, we can
 890                  * throttle further by dilating the 4us pulse.
 891                  */
 892                 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
 893
 894                 if (addnl_dvdr > 1) {
 895                         prescale *= addnl_dvdr;
 896                         if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
 897                                 coal_intvl = (CPSW_CMINTMAX_INTVL
 898                                                 * addnl_dvdr);
 899                 } else {
 900                         addnl_dvdr = 1;
 901                         coal_intvl = CPSW_CMINTMAX_INTVL;
 902                 }
 903         }
 904
 905         num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
 906         writel(num_interrupts, &priv->wr_regs->rx_imax);
 907         writel(num_interrupts, &priv->wr_regs->tx_imax);
 908
 909         int_ctrl |= CPSW_INTPACEEN;
 910         int_ctrl &= (~CPSW_INTPRESCALE_MASK);
 911         int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
 912         writel(int_ctrl, &priv->wr_regs->int_control);
 913
 914         cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
 915         if (priv->data.dual_emac) {
 916                 int i;
 917
 918                 for (i = 0; i < priv->data.slaves; i++) {
 919                         priv = netdev_priv(priv->slaves[i].ndev);
 920                         priv->coal_intvl = coal_intvl;
 921                 }
 922         } else {
 923                 priv->coal_intvl = coal_intvl;
 924         }
 925
 926         return 0;
 927 }
 928
 929 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
 930 {
 931         switch (sset) {
 932         case ETH_SS_STATS:
 933                 return CPSW_STATS_LEN;
 934         default:
 935                 return -EOPNOTSUPP;
 936         }
 937 }
 938
 939 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
 940 {
 941         u8 *p = data;
 942         int i;
 943
 944         switch (stringset) {
 945         case ETH_SS_STATS:
 946                 for (i = 0; i < CPSW_STATS_LEN; i++) {
 947                         memcpy(p, cpsw_gstrings_stats[i].stat_string,
 948                                ETH_GSTRING_LEN);
 949                         p += ETH_GSTRING_LEN;
 950                 }
 951                 break;
 952         }
 953 }
 954
 955 static void cpsw_get_ethtool_stats(struct net_device *ndev,
 956                                     struct ethtool_stats *stats, u64 *data)
 957 {
 958         struct cpsw_priv *priv = netdev_priv(ndev);
 959         struct cpdma_chan_stats rx_stats;
 960         struct cpdma_chan_stats tx_stats;
 961         u32 val;
 962         u8 *p;
 963         int i;
 964
 965         /* Collect Davinci CPDMA stats for Rx and Tx Channel */
 966         cpdma_chan_get_stats(priv->rxch, &rx_stats);
 967         cpdma_chan_get_stats(priv->txch, &tx_stats);
 968
 969         for (i = 0; i < CPSW_STATS_LEN; i++) {
 970                 switch (cpsw_gstrings_stats[i].type) {
 971                 case CPSW_STATS:
 972                         val = readl(priv->hw_stats +
 973                                     cpsw_gstrings_stats[i].stat_offset);
 974                         data[i] = val;
 975                         break;
 976
 977                 case CPDMA_RX_STATS:
 978                         p = (u8 *)&rx_stats +
 979                                 cpsw_gstrings_stats[i].stat_offset;
 980                         data[i] = *(u32 *)p;
 981                         break;
 982
 983                 case CPDMA_TX_STATS:
 984                         p = (u8 *)&tx_stats +
 985                                 cpsw_gstrings_stats[i].stat_offset;
 986                         data[i] = *(u32 *)p;
 987                         break;
 988                 }
 989         }
 990 }
 991
 992 static inline int __show_stat(char *buf, int maxlen, const char *name, u32 val)
 993 {
 994         static char *leader = "........................................";
 995
 996         if (!val)
 997                 return 0;
 998         else
 999                 return snprintf(buf, maxlen, "%s %s %10d\n", name,
1000                                 leader + strlen(name), val);
1001 }
1002
1003 static int cpsw_common_res_usage_state(struct cpsw_priv *priv)
1004 {
1005         u32 i;
1006         u32 usage_count = 0;
1007
1008         if (!priv->data.dual_emac)
1009                 return 0;
1010
1011         for (i = 0; i < priv->data.slaves; i++)
1012                 if (priv->slaves[i].open_stat)
1013                         usage_count++;
1014
1015         return usage_count;
1016 }
1017
1018 static inline int cpsw_tx_packet_submit(struct net_device *ndev,
1019                         struct cpsw_priv *priv, struct sk_buff *skb)
1020 {
1021         if (!priv->data.dual_emac)
1022                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1023                                   skb->len, 0);
1024
1025         if (ndev == cpsw_get_slave_ndev(priv, 0))
1026                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1027                                   skb->len, 1);
1028         else
1029                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1030                                   skb->len, 2);
1031 }
1032
1033 static inline void cpsw_add_dual_emac_def_ale_entries(
1034                 struct cpsw_priv *priv, struct cpsw_slave *slave,
1035                 u32 slave_port)
1036 {
1037         u32 port_mask = 1 << slave_port | 1 << priv->host_port;
1038
1039         if (priv->version == CPSW_VERSION_1)
1040                 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1041         else
1042                 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1043         cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask,
1044                           port_mask, port_mask, 0);
1045         cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1046                            port_mask, ALE_VLAN, slave->port_vlan, 0);
1047         cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1048                 priv->host_port, ALE_VLAN, slave->port_vlan);
1049 }
1050
1051 static void soft_reset_slave(struct cpsw_slave *slave)
1052 {
1053         char name[32];
1054
1055         snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1056         soft_reset(name, &slave->sliver->soft_reset);
1057 }
1058
1059 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1060 {
1061         u32 slave_port;
1062
1063         soft_reset_slave(slave);
1064
1065         /* setup priority mapping */
1066         __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
1067
1068         switch (priv->version) {
1069         case CPSW_VERSION_1:
1070                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1071                 break;
1072         case CPSW_VERSION_2:
1073         case CPSW_VERSION_3:
1074         case CPSW_VERSION_4:
1075                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1076                 break;
1077         }
1078
1079         /* setup max packet size, and mac address */
1080         __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
1081         cpsw_set_slave_mac(slave, priv);
1082
1083         slave->mac_control = 0; /* no link yet */
1084
1085         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1086
1087         if (priv->data.dual_emac)
1088                 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1089         else
1090                 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1091                                    1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1092
1093         slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
1094                                  &cpsw_adjust_link, slave->data->phy_if);
1095         if (IS_ERR(slave->phy)) {
1096                 dev_err(priv->dev, "phy %s not found on slave %d\n",
1097                         slave->data->phy_id, slave->slave_num);
1098                 slave->phy = NULL;
1099         } else {
1100                 dev_info(priv->dev, "phy found : id is : 0x%x\n",
1101                          slave->phy->phy_id);
1102                 phy_start(slave->phy);
1103
1104                 /* Configure GMII_SEL register */
1105                 cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface,
1106                              slave->slave_num);
1107         }
1108 }
1109
1110 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1111 {
1112         const int vlan = priv->data.default_vlan;
1113         const int port = priv->host_port;
1114         u32 reg;
1115         int i;
1116
1117         reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1118                CPSW2_PORT_VLAN;
1119
1120         writel(vlan, &priv->host_port_regs->port_vlan);
1121
1122         for (i = 0; i < priv->data.slaves; i++)
1123                 slave_write(priv->slaves + i, vlan, reg);
1124
1125         cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port,
1126                           ALE_ALL_PORTS << port, ALE_ALL_PORTS << port,
1127                           (ALE_PORT_1 | ALE_PORT_2) << port);
1128 }
1129
1130 static void cpsw_init_host_port(struct cpsw_priv *priv)
1131 {
1132         u32 control_reg;
1133         u32 fifo_mode;
1134
1135         /* soft reset the controller and initialize ale */
1136         soft_reset("cpsw", &priv->regs->soft_reset);
1137         cpsw_ale_start(priv->ale);
1138
1139         /* switch to vlan unaware mode */
1140         cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE,
1141                              CPSW_ALE_VLAN_AWARE);
1142         control_reg = readl(&priv->regs->control);
1143         control_reg |= CPSW_VLAN_AWARE;
1144         writel(control_reg, &priv->regs->control);
1145         fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1146                      CPSW_FIFO_NORMAL_MODE;
1147         writel(fifo_mode, &priv->host_port_regs->tx_in_ctl);
1148
1149         /* setup host port priority mapping */
1150         __raw_writel(CPDMA_TX_PRIORITY_MAP,
1151                      &priv->host_port_regs->cpdma_tx_pri_map);
1152         __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
1153
1154         cpsw_ale_control_set(priv->ale, priv->host_port,
1155                              ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1156
1157         if (!priv->data.dual_emac) {
1158                 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port,
1159                                    0, 0);
1160                 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1161                                    1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2);
1162         }
1163 }
1164
1165 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
1166 {
1167         if (!slave->phy)
1168                 return;
1169         phy_stop(slave->phy);
1170         phy_disconnect(slave->phy);
1171         slave->phy = NULL;
1172 }
1173
1174 static int cpsw_ndo_open(struct net_device *ndev)
1175 {
1176         struct cpsw_priv *priv = netdev_priv(ndev);
1177         struct cpsw_priv *prim_cpsw;
1178         int i, ret;
1179         u32 reg;
1180
1181         if (!cpsw_common_res_usage_state(priv))
1182                 cpsw_intr_disable(priv);
1183         netif_carrier_off(ndev);
1184
1185         pm_runtime_get_sync(&priv->pdev->dev);
1186
1187         reg = priv->version;
1188
1189         dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1190                  CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1191                  CPSW_RTL_VERSION(reg));
1192
1193         /* initialize host and slave ports */
1194         if (!cpsw_common_res_usage_state(priv))
1195                 cpsw_init_host_port(priv);
1196         for_each_slave(priv, cpsw_slave_open, priv);
1197
1198         /* Add default VLAN */
1199         if (!priv->data.dual_emac)
1200                 cpsw_add_default_vlan(priv);
1201
1202         if (!cpsw_common_res_usage_state(priv)) {
1203                 /* setup tx dma to fixed prio and zero offset */
1204                 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
1205                 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
1206
1207                 /* disable priority elevation */
1208                 __raw_writel(0, &priv->regs->ptype);
1209
1210                 /* enable statistics collection only on all ports */
1211                 __raw_writel(0x7, &priv->regs->stat_port_en);
1212
1213                 if (WARN_ON(!priv->data.rx_descs))
1214                         priv->data.rx_descs = 128;
1215
1216                 for (i = 0; i < priv->data.rx_descs; i++) {
1217                         struct sk_buff *skb;
1218
1219                         ret = -ENOMEM;
1220                         skb = __netdev_alloc_skb_ip_align(priv->ndev,
1221                                         priv->rx_packet_max, GFP_KERNEL);
1222                         if (!skb)
1223                                 goto err_cleanup;
1224                         ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
1225                                         skb_tailroom(skb), 0);
1226                         if (ret < 0) {
1227                                 kfree_skb(skb);
1228                                 goto err_cleanup;
1229                         }
1230                 }
1231                 /* continue even if we didn't manage to submit all
1232                  * receive descs
1233                  */
1234                 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
1235
1236                 if (cpts_register(&priv->pdev->dev, priv->cpts,
1237                                   priv->data.cpts_clock_mult,
1238                                   priv->data.cpts_clock_shift))
1239                         dev_err(priv->dev, "error registering cpts device\n");
1240
1241         }
1242
1243         /* Enable Interrupt pacing if configured */
1244         if (priv->coal_intvl != 0) {
1245                 struct ethtool_coalesce coal;
1246
1247                 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1248                 cpsw_set_coalesce(ndev, &coal);
1249         }
1250
1251         prim_cpsw = cpsw_get_slave_priv(priv, 0);
1252         if (prim_cpsw->irq_enabled == false) {
1253                 if ((priv == prim_cpsw) || !netif_running(prim_cpsw->ndev)) {
1254                         prim_cpsw->irq_enabled = true;
1255                         cpsw_enable_irq(prim_cpsw);
1256                 }
1257         }
1258
1259         napi_enable(&priv->napi);
1260         cpdma_ctlr_start(priv->dma);
1261         cpsw_intr_enable(priv);
1262         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
1263         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
1264
1265         if (priv->data.dual_emac)
1266                 priv->slaves[priv->emac_port].open_stat = true;
1267         return 0;
1268
1269 err_cleanup:
1270         cpdma_ctlr_stop(priv->dma);
1271         for_each_slave(priv, cpsw_slave_stop, priv);
1272         pm_runtime_put_sync(&priv->pdev->dev);
1273         netif_carrier_off(priv->ndev);
1274         return ret;
1275 }
1276
1277 static int cpsw_ndo_stop(struct net_device *ndev)
1278 {
1279         struct cpsw_priv *priv = netdev_priv(ndev);
1280
1281         cpsw_info(priv, ifdown, "shutting down cpsw device\n");
1282         netif_stop_queue(priv->ndev);
1283         napi_disable(&priv->napi);
1284         netif_carrier_off(priv->ndev);
1285
1286         if (cpsw_common_res_usage_state(priv) <= 1) {
1287                 cpts_unregister(priv->cpts);
1288                 cpsw_intr_disable(priv);
1289                 cpdma_ctlr_int_ctrl(priv->dma, false);
1290                 cpdma_ctlr_stop(priv->dma);
1291                 cpsw_ale_stop(priv->ale);
1292         }
1293         for_each_slave(priv, cpsw_slave_stop, priv);
1294         pm_runtime_put_sync(&priv->pdev->dev);
1295         if (priv->data.dual_emac)
1296                 priv->slaves[priv->emac_port].open_stat = false;
1297         return 0;
1298 }
1299
1300 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1301                                        struct net_device *ndev)
1302 {
1303         struct cpsw_priv *priv = netdev_priv(ndev);
1304         int ret;
1305
1306         ndev->trans_start = jiffies;
1307
1308         if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1309                 cpsw_err(priv, tx_err, "packet pad failed\n");
1310                 priv->stats.tx_dropped++;
1311                 return NETDEV_TX_OK;
1312         }
1313
1314         if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1315                                 priv->cpts->tx_enable)
1316                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1317
1318         skb_tx_timestamp(skb);
1319
1320         ret = cpsw_tx_packet_submit(ndev, priv, skb);
1321         if (unlikely(ret != 0)) {
1322                 cpsw_err(priv, tx_err, "desc submit failed\n");
1323                 goto fail;
1324         }
1325
1326         /* If there is no more tx desc left free then we need to
1327          * tell the kernel to stop sending us tx frames.
1328          */
1329         if (unlikely(!cpdma_check_free_tx_desc(priv->txch)))
1330                 netif_stop_queue(ndev);
1331
1332         return NETDEV_TX_OK;
1333 fail:
1334         priv->stats.tx_dropped++;
1335         netif_stop_queue(ndev);
1336         return NETDEV_TX_BUSY;
1337 }
1338
1339 #ifdef CONFIG_TI_CPTS
1340
1341 static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
1342 {
1343         struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];
1344         u32 ts_en, seq_id;
1345
1346         if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
1347                 slave_write(slave, 0, CPSW1_TS_CTL);
1348                 return;
1349         }
1350
1351         seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1352         ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1353
1354         if (priv->cpts->tx_enable)
1355                 ts_en |= CPSW_V1_TS_TX_EN;
1356
1357         if (priv->cpts->rx_enable)
1358                 ts_en |= CPSW_V1_TS_RX_EN;
1359
1360         slave_write(slave, ts_en, CPSW1_TS_CTL);
1361         slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1362 }
1363
1364 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1365 {
1366         struct cpsw_slave *slave;
1367         u32 ctrl, mtype;
1368
1369         if (priv->data.dual_emac)
1370                 slave = &priv->slaves[priv->emac_port];
1371         else
1372                 slave = &priv->slaves[priv->data.active_slave];
1373
1374         ctrl = slave_read(slave, CPSW2_CONTROL);
1375         ctrl &= ~CTRL_ALL_TS_MASK;
1376
1377         if (priv->cpts->tx_enable)
1378                 ctrl |= CTRL_TX_TS_BITS;
1379
1380         if (priv->cpts->rx_enable)
1381                 ctrl |= CTRL_RX_TS_BITS;
1382
1383         mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1384
1385         slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1386         slave_write(slave, ctrl, CPSW2_CONTROL);
1387         __raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
1388 }
1389
1390 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1391 {
1392         struct cpsw_priv *priv = netdev_priv(dev);
1393         struct cpts *cpts = priv->cpts;
1394         struct hwtstamp_config cfg;
1395
1396         if (priv->version != CPSW_VERSION_1 &&
1397             priv->version != CPSW_VERSION_2)
1398                 return -EOPNOTSUPP;
1399
1400         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1401                 return -EFAULT;
1402
1403         /* reserved for future extensions */
1404         if (cfg.flags)
1405                 return -EINVAL;
1406
1407         if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
1408                 return -ERANGE;
1409
1410         switch (cfg.rx_filter) {
1411         case HWTSTAMP_FILTER_NONE:
1412                 cpts->rx_enable = 0;
1413                 break;
1414         case HWTSTAMP_FILTER_ALL:
1415         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1416         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1417         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1418                 return -ERANGE;
1419         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1420         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1421         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1422         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1423         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1424         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1425         case HWTSTAMP_FILTER_PTP_V2_EVENT:
1426         case HWTSTAMP_FILTER_PTP_V2_SYNC:
1427         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1428                 cpts->rx_enable = 1;
1429                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1430                 break;
1431         default:
1432                 return -ERANGE;
1433         }
1434
1435         cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON;
1436
1437         switch (priv->version) {
1438         case CPSW_VERSION_1:
1439                 cpsw_hwtstamp_v1(priv);
1440                 break;
1441         case CPSW_VERSION_2:
1442                 cpsw_hwtstamp_v2(priv);
1443                 break;
1444         default:
1445                 WARN_ON(1);
1446         }
1447
1448         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1449 }
1450
1451 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1452 {
1453         struct cpsw_priv *priv = netdev_priv(dev);
1454         struct cpts *cpts = priv->cpts;
1455         struct hwtstamp_config cfg;
1456
1457         if (priv->version != CPSW_VERSION_1 &&
1458             priv->version != CPSW_VERSION_2)
1459                 return -EOPNOTSUPP;
1460
1461         cfg.flags = 0;
1462         cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1463         cfg.rx_filter = (cpts->rx_enable ?
1464                          HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE);
1465
1466         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1467 }
1468
1469 #endif /*CONFIG_TI_CPTS*/
1470
1471 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1472 {
1473         struct cpsw_priv *priv = netdev_priv(dev);
1474         struct mii_ioctl_data *data = if_mii(req);
1475         int slave_no = cpsw_slave_index(priv);
1476
1477         if (!netif_running(dev))
1478                 return -EINVAL;
1479
1480         switch (cmd) {
1481 #ifdef CONFIG_TI_CPTS
1482         case SIOCSHWTSTAMP:
1483                 return cpsw_hwtstamp_set(dev, req);
1484         case SIOCGHWTSTAMP:
1485                 return cpsw_hwtstamp_get(dev, req);
1486 #endif
1487         case SIOCGMIIPHY:
1488                 data->phy_id = priv->slaves[slave_no].phy->addr;
1489                 break;
1490         default:
1491                 return -ENOTSUPP;
1492         }
1493
1494         return 0;
1495 }
1496
1497 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1498 {
1499         struct cpsw_priv *priv = netdev_priv(ndev);
1500
1501         cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1502         priv->stats.tx_errors++;
1503         cpsw_intr_disable(priv);
1504         cpdma_ctlr_int_ctrl(priv->dma, false);
1505         cpdma_chan_stop(priv->txch);
1506         cpdma_chan_start(priv->txch);
1507         cpdma_ctlr_int_ctrl(priv->dma, true);
1508         cpsw_intr_enable(priv);
1509         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
1510         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
1511
1512 }
1513
1514 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1515 {
1516         struct cpsw_priv *priv = netdev_priv(ndev);
1517         struct sockaddr *addr = (struct sockaddr *)p;
1518         int flags = 0;
1519         u16 vid = 0;
1520
1521         if (!is_valid_ether_addr(addr->sa_data))
1522                 return -EADDRNOTAVAIL;
1523
1524         if (priv->data.dual_emac) {
1525                 vid = priv->slaves[priv->emac_port].port_vlan;
1526                 flags = ALE_VLAN;
1527         }
1528
1529         cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port,
1530                            flags, vid);
1531         cpsw_ale_add_ucast(priv->ale, addr->sa_data, priv->host_port,
1532                            flags, vid);
1533
1534         memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1535         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1536         for_each_slave(priv, cpsw_set_slave_mac, priv);
1537
1538         return 0;
1539 }
1540
1541 static struct net_device_stats *cpsw_ndo_get_stats(struct net_device *ndev)
1542 {
1543         struct cpsw_priv *priv = netdev_priv(ndev);
1544         return &priv->stats;
1545 }
1546
1547 #ifdef CONFIG_NET_POLL_CONTROLLER
1548 static void cpsw_ndo_poll_controller(struct net_device *ndev)
1549 {
1550         struct cpsw_priv *priv = netdev_priv(ndev);
1551
1552         cpsw_intr_disable(priv);
1553         cpdma_ctlr_int_ctrl(priv->dma, false);
1554         cpsw_interrupt(ndev->irq, priv);
1555         cpdma_ctlr_int_ctrl(priv->dma, true);
1556         cpsw_intr_enable(priv);
1557         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
1558         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
1559
1560 }
1561 #endif
1562
1563 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1564                                 unsigned short vid)
1565 {
1566         int ret;
1567
1568         ret = cpsw_ale_add_vlan(priv->ale, vid,
1569                                 ALE_ALL_PORTS << priv->host_port,
1570                                 0, ALE_ALL_PORTS << priv->host_port,
1571                                 (ALE_PORT_1 | ALE_PORT_2) << priv->host_port);
1572         if (ret != 0)
1573                 return ret;
1574
1575         ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1576                                  priv->host_port, ALE_VLAN, vid);
1577         if (ret != 0)
1578                 goto clean_vid;
1579
1580         ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1581                                  ALE_ALL_PORTS << priv->host_port,
1582                                  ALE_VLAN, vid, 0);
1583         if (ret != 0)
1584                 goto clean_vlan_ucast;
1585         return 0;
1586
1587 clean_vlan_ucast:
1588         cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1589                             priv->host_port, ALE_VLAN, vid);
1590 clean_vid:
1591         cpsw_ale_del_vlan(priv->ale, vid, 0);
1592         return ret;
1593 }
1594
1595 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
1596                                     __be16 proto, u16 vid)
1597 {
1598         struct cpsw_priv *priv = netdev_priv(ndev);
1599
1600         if (vid == priv->data.default_vlan)
1601                 return 0;
1602
1603         dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1604         return cpsw_add_vlan_ale_entry(priv, vid);
1605 }
1606
1607 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
1608                                      __be16 proto, u16 vid)
1609 {
1610         struct cpsw_priv *priv = netdev_priv(ndev);
1611         int ret;
1612
1613         if (vid == priv->data.default_vlan)
1614                 return 0;
1615
1616         dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1617         ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
1618         if (ret != 0)
1619                 return ret;
1620
1621         ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1622                                  priv->host_port, ALE_VLAN, vid);
1623         if (ret != 0)
1624                 return ret;
1625
1626         return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,
1627                                   0, ALE_VLAN, vid);
1628 }
1629
1630 static const struct net_device_ops cpsw_netdev_ops = {
1631         .ndo_open               = cpsw_ndo_open,
1632         .ndo_stop               = cpsw_ndo_stop,
1633         .ndo_start_xmit         = cpsw_ndo_start_xmit,
1634         .ndo_set_mac_address    = cpsw_ndo_set_mac_address,
1635         .ndo_do_ioctl           = cpsw_ndo_ioctl,
1636         .ndo_validate_addr      = eth_validate_addr,
1637         .ndo_change_mtu         = eth_change_mtu,
1638         .ndo_tx_timeout         = cpsw_ndo_tx_timeout,
1639         .ndo_get_stats          = cpsw_ndo_get_stats,
1640         .ndo_set_rx_mode        = cpsw_ndo_set_rx_mode,
1641 #ifdef CONFIG_NET_POLL_CONTROLLER
1642         .ndo_poll_controller    = cpsw_ndo_poll_controller,
1643 #endif
1644         .ndo_vlan_rx_add_vid    = cpsw_ndo_vlan_rx_add_vid,
1645         .ndo_vlan_rx_kill_vid   = cpsw_ndo_vlan_rx_kill_vid,
1646 };
1647
1648 static void cpsw_get_drvinfo(struct net_device *ndev,
1649                              struct ethtool_drvinfo *info)
1650 {
1651         struct cpsw_priv *priv = netdev_priv(ndev);
1652
1653         strlcpy(info->driver, "TI CPSW Driver v1.0", sizeof(info->driver));
1654         strlcpy(info->version, "1.0", sizeof(info->version));
1655         strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info));
1656 }
1657
1658 static u32 cpsw_get_msglevel(struct net_device *ndev)
1659 {
1660         struct cpsw_priv *priv = netdev_priv(ndev);
1661         return priv->msg_enable;
1662 }
1663
1664 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1665 {
1666         struct cpsw_priv *priv = netdev_priv(ndev);
1667         priv->msg_enable = value;
1668 }
1669
1670 static int cpsw_get_ts_info(struct net_device *ndev,
1671                             struct ethtool_ts_info *info)
1672 {
1673 #ifdef CONFIG_TI_CPTS
1674         struct cpsw_priv *priv = netdev_priv(ndev);
1675
1676         info->so_timestamping =
1677                 SOF_TIMESTAMPING_TX_HARDWARE |
1678                 SOF_TIMESTAMPING_TX_SOFTWARE |
1679                 SOF_TIMESTAMPING_RX_HARDWARE |
1680                 SOF_TIMESTAMPING_RX_SOFTWARE |
1681                 SOF_TIMESTAMPING_SOFTWARE |
1682                 SOF_TIMESTAMPING_RAW_HARDWARE;
1683         info->phc_index = priv->cpts->phc_index;
1684         info->tx_types =
1685                 (1 << HWTSTAMP_TX_OFF) |
1686                 (1 << HWTSTAMP_TX_ON);
1687         info->rx_filters =
1688                 (1 << HWTSTAMP_FILTER_NONE) |
1689                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1690 #else
1691         info->so_timestamping =
1692                 SOF_TIMESTAMPING_TX_SOFTWARE |
1693                 SOF_TIMESTAMPING_RX_SOFTWARE |
1694                 SOF_TIMESTAMPING_SOFTWARE;
1695         info->phc_index = -1;
1696         info->tx_types = 0;
1697         info->rx_filters = 0;
1698 #endif
1699         return 0;
1700 }
1701
1702 static int cpsw_get_settings(struct net_device *ndev,
1703                              struct ethtool_cmd *ecmd)
1704 {
1705         struct cpsw_priv *priv = netdev_priv(ndev);
1706         int slave_no = cpsw_slave_index(priv);
1707
1708         if (priv->slaves[slave_no].phy)
1709                 return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
1710         else
1711                 return -EOPNOTSUPP;
1712 }
1713
1714 static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1715 {
1716         struct cpsw_priv *priv = netdev_priv(ndev);
1717         int slave_no = cpsw_slave_index(priv);
1718
1719         if (priv->slaves[slave_no].phy)
1720                 return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
1721         else
1722                 return -EOPNOTSUPP;
1723 }
1724
1725 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1726 {
1727         struct cpsw_priv *priv = netdev_priv(ndev);
1728         int slave_no = cpsw_slave_index(priv);
1729
1730         wol->supported = 0;
1731         wol->wolopts = 0;
1732
1733         if (priv->slaves[slave_no].phy)
1734                 phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol);
1735 }
1736
1737 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1738 {
1739         struct cpsw_priv *priv = netdev_priv(ndev);
1740         int slave_no = cpsw_slave_index(priv);
1741
1742         if (priv->slaves[slave_no].phy)
1743                 return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol);
1744         else
1745                 return -EOPNOTSUPP;
1746 }
1747
1748 static const struct ethtool_ops cpsw_ethtool_ops = {
1749         .get_drvinfo    = cpsw_get_drvinfo,
1750         .get_msglevel   = cpsw_get_msglevel,
1751         .set_msglevel   = cpsw_set_msglevel,
1752         .get_link       = ethtool_op_get_link,
1753         .get_ts_info    = cpsw_get_ts_info,
1754         .get_settings   = cpsw_get_settings,
1755         .set_settings   = cpsw_set_settings,
1756         .get_coalesce   = cpsw_get_coalesce,
1757         .set_coalesce   = cpsw_set_coalesce,
1758         .get_sset_count         = cpsw_get_sset_count,
1759         .get_strings            = cpsw_get_strings,
1760         .get_ethtool_stats      = cpsw_get_ethtool_stats,
1761         .get_wol        = cpsw_get_wol,
1762         .set_wol        = cpsw_set_wol,
1763 };
1764
1765 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
1766                             u32 slave_reg_ofs, u32 sliver_reg_ofs)
1767 {
1768         void __iomem            *regs = priv->regs;
1769         int                     slave_num = slave->slave_num;
1770         struct cpsw_slave_data  *data = priv->data.slave_data + slave_num;
1771
1772         slave->data     = data;
1773         slave->regs     = regs + slave_reg_ofs;
1774         slave->sliver   = regs + sliver_reg_ofs;
1775         slave->port_vlan = data->dual_emac_res_vlan;
1776 }
1777
1778 static int cpsw_probe_dt(struct cpsw_platform_data *data,
1779                          struct platform_device *pdev)
1780 {
1781         struct device_node *node = pdev->dev.of_node;
1782         struct device_node *slave_node;
1783         int i = 0, ret;
1784         u32 prop;
1785
1786         if (!node)
1787                 return -EINVAL;
1788
1789         if (of_property_read_u32(node, "slaves", &prop)) {
1790                 pr_err("Missing slaves property in the DT.\n");
1791                 return -EINVAL;
1792         }
1793         data->slaves = prop;
1794
1795         if (of_property_read_u32(node, "active_slave", &prop)) {
1796                 pr_err("Missing active_slave property in the DT.\n");
1797                 return -EINVAL;
1798         }
1799         data->active_slave = prop;
1800
1801         if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
1802                 pr_err("Missing cpts_clock_mult property in the DT.\n");
1803                 return -EINVAL;
1804         }
1805         data->cpts_clock_mult = prop;
1806
1807         if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
1808                 pr_err("Missing cpts_clock_shift property in the DT.\n");
1809                 return -EINVAL;
1810         }
1811         data->cpts_clock_shift = prop;
1812
1813         data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
1814                                         * sizeof(struct cpsw_slave_data),
1815                                         GFP_KERNEL);
1816         if (!data->slave_data)
1817                 return -ENOMEM;
1818
1819         if (of_property_read_u32(node, "cpdma_channels", &prop)) {
1820                 pr_err("Missing cpdma_channels property in the DT.\n");
1821                 return -EINVAL;
1822         }
1823         data->channels = prop;
1824
1825         if (of_property_read_u32(node, "ale_entries", &prop)) {
1826                 pr_err("Missing ale_entries property in the DT.\n");
1827                 return -EINVAL;
1828         }
1829         data->ale_entries = prop;
1830
1831         if (of_property_read_u32(node, "bd_ram_size", &prop)) {
1832                 pr_err("Missing bd_ram_size property in the DT.\n");
1833                 return -EINVAL;
1834         }
1835         data->bd_ram_size = prop;
1836
1837         if (of_property_read_u32(node, "rx_descs", &prop)) {
1838                 pr_err("Missing rx_descs property in the DT.\n");
1839                 return -EINVAL;
1840         }
1841         data->rx_descs = prop;
1842
1843         if (of_property_read_u32(node, "mac_control", &prop)) {
1844                 pr_err("Missing mac_control property in the DT.\n");
1845                 return -EINVAL;
1846         }
1847         data->mac_control = prop;
1848
1849         if (of_property_read_bool(node, "dual_emac"))
1850                 data->dual_emac = 1;
1851
1852         /*
1853          * Populate all the child nodes here...
1854          */
1855         ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
1856         /* We do not want to force this, as in some cases may not have child */
1857         if (ret)
1858                 pr_warn("Doesn't have any child node\n");
1859
1860         for_each_child_of_node(node, slave_node) {
1861                 struct cpsw_slave_data *slave_data = data->slave_data + i;
1862                 const void *mac_addr = NULL;
1863                 u32 phyid;
1864                 int lenp;
1865                 const __be32 *parp;
1866                 struct device_node *mdio_node;
1867                 struct platform_device *mdio;
1868
1869                 /* This is no slave child node, continue */
1870                 if (strcmp(slave_node->name, "slave"))
1871                         continue;
1872
1873                 parp = of_get_property(slave_node, "phy_id", &lenp);
1874                 if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) {
1875                         pr_err("Missing slave[%d] phy_id property\n", i);
1876                         return -EINVAL;
1877                 }
1878                 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
1879                 phyid = be32_to_cpup(parp+1);
1880                 mdio = of_find_device_by_node(mdio_node);
1881                 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
1882                          PHY_ID_FMT, mdio->name, phyid);
1883
1884                 mac_addr = of_get_mac_address(slave_node);
1885                 if (mac_addr)
1886                         memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
1887
1888                 slave_data->phy_if = of_get_phy_mode(slave_node);
1889
1890                 if (data->dual_emac) {
1891                         if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
1892                                                  &prop)) {
1893                                 pr_err("Missing dual_emac_res_vlan in DT.\n");
1894                                 slave_data->dual_emac_res_vlan = i+1;
1895                                 pr_err("Using %d as Reserved VLAN for %d slave\n",
1896                                        slave_data->dual_emac_res_vlan, i);
1897                         } else {
1898                                 slave_data->dual_emac_res_vlan = prop;
1899                         }
1900                 }
1901
1902                 i++;
1903                 if (i == data->slaves)
1904                         break;
1905         }
1906
1907         return 0;
1908 }
1909
1910 static int cpsw_probe_dual_emac(struct platform_device *pdev,
1911                                 struct cpsw_priv *priv)
1912 {
1913         struct cpsw_platform_data       *data = &priv->data;
1914         struct net_device               *ndev;
1915         struct cpsw_priv                *priv_sl2;
1916         int ret = 0, i;
1917
1918         ndev = alloc_etherdev(sizeof(struct cpsw_priv));
1919         if (!ndev) {
1920                 pr_err("cpsw: error allocating net_device\n");
1921                 return -ENOMEM;
1922         }
1923
1924         priv_sl2 = netdev_priv(ndev);
1925         spin_lock_init(&priv_sl2->lock);
1926         priv_sl2->data = *data;
1927         priv_sl2->pdev = pdev;
1928         priv_sl2->ndev = ndev;
1929         priv_sl2->dev  = &ndev->dev;
1930         priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
1931         priv_sl2->rx_packet_max = max(rx_packet_max, 128);
1932
1933         if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
1934                 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
1935                         ETH_ALEN);
1936                 pr_info("cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);
1937         } else {
1938                 random_ether_addr(priv_sl2->mac_addr);
1939                 pr_info("cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);
1940         }
1941         memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
1942
1943         priv_sl2->slaves = priv->slaves;
1944         priv_sl2->clk = priv->clk;
1945
1946         priv_sl2->coal_intvl = 0;
1947         priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;
1948
1949         priv_sl2->regs = priv->regs;
1950         priv_sl2->host_port = priv->host_port;
1951         priv_sl2->host_port_regs = priv->host_port_regs;
1952         priv_sl2->wr_regs = priv->wr_regs;
1953         priv_sl2->hw_stats = priv->hw_stats;
1954         priv_sl2->dma = priv->dma;
1955         priv_sl2->txch = priv->txch;
1956         priv_sl2->rxch = priv->rxch;
1957         priv_sl2->ale = priv->ale;
1958         priv_sl2->emac_port = 1;
1959         priv->slaves[1].ndev = ndev;
1960         priv_sl2->cpts = priv->cpts;
1961         priv_sl2->version = priv->version;
1962
1963         for (i = 0; i < priv->num_irqs; i++) {
1964                 priv_sl2->irqs_table[i] = priv->irqs_table[i];
1965                 priv_sl2->num_irqs = priv->num_irqs;
1966         }
1967         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1968
1969         ndev->netdev_ops = &cpsw_netdev_ops;
1970         SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops);
1971         netif_napi_add(ndev, &priv_sl2->napi, cpsw_poll, CPSW_POLL_WEIGHT);
1972
1973         /* register the network device */
1974         SET_NETDEV_DEV(ndev, &pdev->dev);
1975         ret = register_netdev(ndev);
1976         if (ret) {
1977                 pr_err("cpsw: error registering net device\n");
1978                 free_netdev(ndev);
1979                 ret = -ENODEV;
1980         }
1981
1982         return ret;
1983 }
1984
1985 static int cpsw_probe(struct platform_device *pdev)
1986 {
1987         struct cpsw_platform_data       *data;
1988         struct net_device               *ndev;
1989         struct cpsw_priv                *priv;
1990         struct cpdma_params             dma_params;
1991         struct cpsw_ale_params          ale_params;
1992         void __iomem                    *ss_regs;
1993         struct resource                 *res, *ss_res;
1994         u32 slave_offset, sliver_offset, slave_size;
1995         int ret = 0, i, k = 0;
1996
1997         ndev = alloc_etherdev(sizeof(struct cpsw_priv));
1998         if (!ndev) {
1999                 pr_err("error allocating net_device\n");
2000                 return -ENOMEM;
2001         }
2002
2003         platform_set_drvdata(pdev, ndev);
2004         priv = netdev_priv(ndev);
2005         spin_lock_init(&priv->lock);
2006         priv->pdev = pdev;
2007         priv->ndev = ndev;
2008         priv->dev  = &ndev->dev;
2009         priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2010         priv->rx_packet_max = max(rx_packet_max, 128);
2011         priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
2012         priv->irq_enabled = true;
2013         if (!priv->cpts) {
2014                 pr_err("error allocating cpts\n");
2015                 goto clean_ndev_ret;
2016         }
2017
2018         /*
2019          * This may be required here for child devices.
2020          */
2021         pm_runtime_enable(&pdev->dev);
2022
2023         /* Select default pin state */
2024         pinctrl_pm_select_default_state(&pdev->dev);
2025
2026         if (cpsw_probe_dt(&priv->data, pdev)) {
2027                 pr_err("cpsw: platform data missing\n");
2028                 ret = -ENODEV;
2029                 goto clean_runtime_disable_ret;
2030         }
2031         data = &priv->data;
2032
2033         if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2034                 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
2035                 pr_info("Detected MACID = %pM\n", priv->mac_addr);
2036         } else {
2037                 eth_random_addr(priv->mac_addr);
2038                 pr_info("Random MACID = %pM\n", priv->mac_addr);
2039         }
2040
2041         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2042
2043         priv->slaves = devm_kzalloc(&pdev->dev,
2044                                     sizeof(struct cpsw_slave) * data->slaves,
2045                                     GFP_KERNEL);
2046         if (!priv->slaves) {
2047                 ret = -ENOMEM;
2048                 goto clean_runtime_disable_ret;
2049         }
2050         for (i = 0; i < data->slaves; i++)
2051                 priv->slaves[i].slave_num = i;
2052
2053         priv->slaves[0].ndev = ndev;
2054         priv->emac_port = 0;
2055
2056         priv->clk = devm_clk_get(&pdev->dev, "fck");
2057         if (IS_ERR(priv->clk)) {
2058                 dev_err(priv->dev, "fck is not found\n");
2059                 ret = -ENODEV;
2060                 goto clean_runtime_disable_ret;
2061         }
2062         priv->coal_intvl = 0;
2063         priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;
2064
2065         ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2066         ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2067         if (IS_ERR(ss_regs)) {
2068                 ret = PTR_ERR(ss_regs);
2069                 goto clean_runtime_disable_ret;
2070         }
2071         priv->regs = ss_regs;
2072         priv->host_port = HOST_PORT_NUM;
2073
2074         /* Need to enable clocks with runtime PM api to access module
2075          * registers
2076          */
2077         pm_runtime_get_sync(&pdev->dev);
2078         priv->version = readl(&priv->regs->id_ver);
2079         pm_runtime_put_sync(&pdev->dev);
2080
2081         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2082         priv->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2083         if (IS_ERR(priv->wr_regs)) {
2084                 ret = PTR_ERR(priv->wr_regs);
2085                 goto clean_runtime_disable_ret;
2086         }
2087
2088         memset(&dma_params, 0, sizeof(dma_params));
2089         memset(&ale_params, 0, sizeof(ale_params));
2090
2091         switch (priv->version) {
2092         case CPSW_VERSION_1:
2093                 priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
2094                 priv->cpts->reg      = ss_regs + CPSW1_CPTS_OFFSET;
2095                 priv->hw_stats       = ss_regs + CPSW1_HW_STATS;
2096                 dma_params.dmaregs   = ss_regs + CPSW1_CPDMA_OFFSET;
2097                 dma_params.txhdp     = ss_regs + CPSW1_STATERAM_OFFSET;
2098                 ale_params.ale_regs  = ss_regs + CPSW1_ALE_OFFSET;
2099                 slave_offset         = CPSW1_SLAVE_OFFSET;
2100                 slave_size           = CPSW1_SLAVE_SIZE;
2101                 sliver_offset        = CPSW1_SLIVER_OFFSET;
2102                 dma_params.desc_mem_phys = 0;
2103                 break;
2104         case CPSW_VERSION_2:
2105         case CPSW_VERSION_3:
2106         case CPSW_VERSION_4:
2107                 priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
2108                 priv->cpts->reg      = ss_regs + CPSW2_CPTS_OFFSET;
2109                 priv->hw_stats       = ss_regs + CPSW2_HW_STATS;
2110                 dma_params.dmaregs   = ss_regs + CPSW2_CPDMA_OFFSET;
2111                 dma_params.txhdp     = ss_regs + CPSW2_STATERAM_OFFSET;
2112                 ale_params.ale_regs  = ss_regs + CPSW2_ALE_OFFSET;
2113                 slave_offset         = CPSW2_SLAVE_OFFSET;
2114                 slave_size           = CPSW2_SLAVE_SIZE;
2115                 sliver_offset        = CPSW2_SLIVER_OFFSET;
2116                 dma_params.desc_mem_phys =
2117                         (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
2118                 break;
2119         default:
2120                 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
2121                 ret = -ENODEV;
2122                 goto clean_runtime_disable_ret;
2123         }
2124         for (i = 0; i < priv->data.slaves; i++) {
2125                 struct cpsw_slave *slave = &priv->slaves[i];
2126                 cpsw_slave_init(slave, priv, slave_offset, sliver_offset);
2127                 slave_offset  += slave_size;
2128                 sliver_offset += SLIVER_SIZE;
2129         }
2130
2131         dma_params.dev          = &pdev->dev;
2132         dma_params.rxthresh     = dma_params.dmaregs + CPDMA_RXTHRESH;
2133         dma_params.rxfree       = dma_params.dmaregs + CPDMA_RXFREE;
2134         dma_params.rxhdp        = dma_params.txhdp + CPDMA_RXHDP;
2135         dma_params.txcp         = dma_params.txhdp + CPDMA_TXCP;
2136         dma_params.rxcp         = dma_params.txhdp + CPDMA_RXCP;
2137
2138         dma_params.num_chan             = data->channels;
2139         dma_params.has_soft_reset       = true;
2140         dma_params.min_packet_size      = CPSW_MIN_PACKET_SIZE;
2141         dma_params.desc_mem_size        = data->bd_ram_size;
2142         dma_params.desc_align           = 16;
2143         dma_params.has_ext_regs         = true;
2144         dma_params.desc_hw_addr         = dma_params.desc_mem_phys;
2145
2146         priv->dma = cpdma_ctlr_create(&dma_params);
2147         if (!priv->dma) {
2148                 dev_err(priv->dev, "error initializing dma\n");
2149                 ret = -ENOMEM;
2150                 goto clean_runtime_disable_ret;
2151         }
2152
2153         priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
2154                                        cpsw_tx_handler);
2155         priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
2156                                        cpsw_rx_handler);
2157
2158         if (WARN_ON(!priv->txch || !priv->rxch)) {
2159                 dev_err(priv->dev, "error initializing dma channels\n");
2160                 ret = -ENOMEM;
2161                 goto clean_dma_ret;
2162         }
2163
2164         ale_params.dev                  = &ndev->dev;
2165         ale_params.ale_ageout           = ale_ageout;
2166         ale_params.ale_entries          = data->ale_entries;
2167         ale_params.ale_ports            = data->slaves;
2168
2169         priv->ale = cpsw_ale_create(&ale_params);
2170         if (!priv->ale) {
2171                 dev_err(priv->dev, "error initializing ale engine\n");
2172                 ret = -ENODEV;
2173                 goto clean_dma_ret;
2174         }
2175
2176         ndev->irq = platform_get_irq(pdev, 0);
2177         if (ndev->irq < 0) {
2178                 dev_err(priv->dev, "error getting irq resource\n");
2179                 ret = -ENOENT;
2180                 goto clean_ale_ret;
2181         }
2182
2183         while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {
2184                 for (i = res->start; i <= res->end; i++) {
2185                         if (devm_request_irq(&pdev->dev, i, cpsw_interrupt, 0,
2186                                              dev_name(&pdev->dev), priv)) {
2187                                 dev_err(priv->dev, "error attaching irq\n");
2188                                 goto clean_ale_ret;
2189                         }
2190                         priv->irqs_table[k] = i;
2191                         priv->num_irqs = k + 1;
2192                 }
2193                 k++;
2194         }
2195
2196         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2197
2198         ndev->netdev_ops = &cpsw_netdev_ops;
2199         SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops);
2200         netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT);
2201
2202         /* register the network device */
2203         SET_NETDEV_DEV(ndev, &pdev->dev);
2204         ret = register_netdev(ndev);
2205         if (ret) {
2206                 dev_err(priv->dev, "error registering net device\n");
2207                 ret = -ENODEV;
2208                 goto clean_ale_ret;
2209         }
2210
2211         if (cpts_register(&pdev->dev, priv->cpts,
2212                           data->cpts_clock_mult, data->cpts_clock_shift))
2213                 dev_err(priv->dev, "error registering cpts device\n");
2214
2215         cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n",
2216                     &ss_res->start, ndev->irq);
2217
2218         if (priv->data.dual_emac) {
2219                 ret = cpsw_probe_dual_emac(pdev, priv);
2220                 if (ret) {
2221                         cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
2222                         goto clean_ale_ret;
2223                 }
2224         }
2225
2226         return 0;
2227
2228 clean_ale_ret:
2229         cpsw_ale_destroy(priv->ale);
2230 clean_dma_ret:
2231         cpdma_chan_destroy(priv->txch);
2232         cpdma_chan_destroy(priv->rxch);
2233         cpdma_ctlr_destroy(priv->dma);
2234 clean_runtime_disable_ret:
2235         pm_runtime_disable(&pdev->dev);
2236 clean_ndev_ret:
2237         free_netdev(priv->ndev);
2238         return ret;
2239 }
2240
2241 static int cpsw_remove(struct platform_device *pdev)
2242 {
2243         struct net_device *ndev = platform_get_drvdata(pdev);
2244         struct cpsw_priv *priv = netdev_priv(ndev);
2245
2246         if (priv->data.dual_emac)
2247                 unregister_netdev(cpsw_get_slave_ndev(priv, 1));
2248         unregister_netdev(ndev);
2249
2250         cpsw_ale_destroy(priv->ale);
2251         cpdma_chan_destroy(priv->txch);
2252         cpdma_chan_destroy(priv->rxch);
2253         cpdma_ctlr_destroy(priv->dma);
2254         pm_runtime_disable(&pdev->dev);
2255         if (priv->data.dual_emac)
2256                 free_netdev(cpsw_get_slave_ndev(priv, 1));
2257         free_netdev(ndev);
2258         return 0;
2259 }
2260
2261 static int cpsw_suspend(struct device *dev)
2262 {
2263         struct platform_device  *pdev = to_platform_device(dev);
2264         struct net_device       *ndev = platform_get_drvdata(pdev);
2265         struct cpsw_priv        *priv = netdev_priv(ndev);
2266
2267         if (netif_running(ndev))
2268                 cpsw_ndo_stop(ndev);
2269
2270         for_each_slave(priv, soft_reset_slave);
2271
2272         pm_runtime_put_sync(&pdev->dev);
2273
2274         /* Select sleep pin state */
2275         pinctrl_pm_select_sleep_state(&pdev->dev);
2276
2277         return 0;
2278 }
2279
2280 static int cpsw_resume(struct device *dev)
2281 {
2282         struct platform_device  *pdev = to_platform_device(dev);
2283         struct net_device       *ndev = platform_get_drvdata(pdev);
2284
2285         pm_runtime_get_sync(&pdev->dev);
2286
2287         /* Select default pin state */
2288         pinctrl_pm_select_default_state(&pdev->dev);
2289
2290         if (netif_running(ndev))
2291                 cpsw_ndo_open(ndev);
2292         return 0;
2293 }
2294
2295 static const struct dev_pm_ops cpsw_pm_ops = {
2296         .suspend        = cpsw_suspend,
2297         .resume         = cpsw_resume,
2298 };
2299
2300 static const struct of_device_id cpsw_of_mtable[] = {
2301         { .compatible = "ti,cpsw", },
2302         { /* sentinel */ },
2303 };
2304 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2305
2306 static struct platform_driver cpsw_driver = {
2307         .driver = {
2308                 .name    = "cpsw",
2309                 .owner   = THIS_MODULE,
2310                 .pm      = &cpsw_pm_ops,
2311                 .of_match_table = cpsw_of_mtable,
2312         },
2313         .probe = cpsw_probe,
2314         .remove = cpsw_remove,
2315 };
2316
2317 static int __init cpsw_init(void)
2318 {
2319         return platform_driver_register(&cpsw_driver);
2320 }
2321 late_initcall(cpsw_init);
2322
2323 static void __exit cpsw_exit(void)
2324 {
2325         platform_driver_unregister(&cpsw_driver);
2326 }
2327 module_exit(cpsw_exit);
2328
2329 MODULE_LICENSE("GPL");
2330 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2331 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2332 MODULE_DESCRIPTION("TI CPSW Ethernet driver");