drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/pkt_sched.h>
  38 #include <linux/ipv6.h>
  39 #include <net/checksum.h>
  40 #include <net/ip6_checksum.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/if_vlan.h>
  43 #include <scsi/fc/fc_fcoe.h>
  44
  45 #include "ixgbe.h"
  46 #include "ixgbe_common.h"
  47
  48 char ixgbe_driver_name[] = "ixgbe";
  49 static const char ixgbe_driver_string[] =
  50                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  51
  52 #define DRV_VERSION "2.0.44-k2"
  53 const char ixgbe_driver_version[] = DRV_VERSION;
  54 static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
  55
  56 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  57         [board_82598] = &ixgbe_82598_info,
  58         [board_82599] = &ixgbe_82599_info,
  59 };
  60
  61 /* ixgbe_pci_tbl - PCI Device ID Table
  62  *
  63  * Wildcard entries (PCI_ANY_ID) should come last
  64  * Last entry must be all 0s
  65  *
  66  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  67  *   Class, Class Mask, private data (not used) }
  68  */
  69 static struct pci_device_id ixgbe_pci_tbl[] = {
  70         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  71          board_82598 },
  72         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  73          board_82598 },
  74         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  75          board_82598 },
  76         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  77          board_82598 },
  78         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  79          board_82598 },
  80         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  81          board_82598 },
  82         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  83          board_82598 },
  84         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  85          board_82598 },
  86         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  87          board_82598 },
  88         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  89          board_82598 },
  90         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  91          board_82598 },
  92         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  93          board_82598 },
  94         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  95          board_82599 },
  96         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
  97          board_82599 },
  98         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
  99          board_82599 },
 100         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
 101          board_82599 },
 102         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 103          board_82599 },
 104         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
 105          board_82599 },
 106
 107         /* required last entry */
 108         {0, }
 109 };
 110 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 111
 112 #ifdef CONFIG_IXGBE_DCA
 113 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 114                             void *p);
 115 static struct notifier_block dca_notifier = {
 116         .notifier_call = ixgbe_notify_dca,
 117         .next          = NULL,
 118         .priority      = 0
 119 };
 120 #endif
 121
 122 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 123 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 124 MODULE_LICENSE("GPL");
 125 MODULE_VERSION(DRV_VERSION);
 126
 127 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 128
 129 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 130 {
 131         u32 ctrl_ext;
 132
 133         /* Let firmware take over control of h/w */
 134         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 135         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 136                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 137 }
 138
 139 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 140 {
 141         u32 ctrl_ext;
 142
 143         /* Let firmware know the driver has taken over */
 144         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 145         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 146                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 147 }
 148
 149 /*
 150  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 151  * @adapter: pointer to adapter struct
 152  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 153  * @queue: queue to map the corresponding interrupt to
 154  * @msix_vector: the vector to map to the corresponding queue
 155  *
 156  */
 157 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 158                            u8 queue, u8 msix_vector)
 159 {
 160         u32 ivar, index;
 161         struct ixgbe_hw *hw = &adapter->hw;
 162         switch (hw->mac.type) {
 163         case ixgbe_mac_82598EB:
 164                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 165                 if (direction == -1)
 166                         direction = 0;
 167                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 168                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 169                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 170                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 171                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 172                 break;
 173         case ixgbe_mac_82599EB:
 174                 if (direction == -1) {
 175                         /* other causes */
 176                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 177                         index = ((queue & 1) * 8);
 178                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 179                         ivar &= ~(0xFF << index);
 180                         ivar |= (msix_vector << index);
 181                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 182                         break;
 183                 } else {
 184                         /* tx or rx causes */
 185                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 186                         index = ((16 * (queue & 1)) + (8 * direction));
 187                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 188                         ivar &= ~(0xFF << index);
 189                         ivar |= (msix_vector << index);
 190                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 191                         break;
 192                 }
 193         default:
 194                 break;
 195         }
 196 }
 197
 198 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 199                                           u64 qmask)
 200 {
 201         u32 mask;
 202
 203         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 204                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 205                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 206         } else {
 207                 mask = (qmask & 0xFFFFFFFF);
 208                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 209                 mask = (qmask >> 32);
 210                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 211         }
 212 }
 213
 214 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
 215                                              struct ixgbe_tx_buffer
 216                                              *tx_buffer_info)
 217 {
 218         tx_buffer_info->dma = 0;
 219         if (tx_buffer_info->skb) {
 220                 skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb,
 221                               DMA_TO_DEVICE);
 222                 dev_kfree_skb_any(tx_buffer_info->skb);
 223                 tx_buffer_info->skb = NULL;
 224         }
 225         tx_buffer_info->time_stamp = 0;
 226         /* tx_buffer_info must be completely set up in the transmit path */
 227 }
 228
 229 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 230                                        struct ixgbe_ring *tx_ring,
 231                                        unsigned int eop)
 232 {
 233         struct ixgbe_hw *hw = &adapter->hw;
 234
 235         /* Detect a transmit hang in hardware, this serializes the
 236          * check with the clearing of time_stamp and movement of eop */
 237         adapter->detect_tx_hung = false;
 238         if (tx_ring->tx_buffer_info[eop].time_stamp &&
 239             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 240             !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
 241                 /* detected Tx unit hang */
 242                 union ixgbe_adv_tx_desc *tx_desc;
 243                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 244                 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
 245                         "  Tx Queue             <%d>\n"
 246                         "  TDH, TDT             <%x>, <%x>\n"
 247                         "  next_to_use          <%x>\n"
 248                         "  next_to_clean        <%x>\n"
 249                         "tx_buffer_info[next_to_clean]\n"
 250                         "  time_stamp           <%lx>\n"
 251                         "  jiffies              <%lx>\n",
 252                         tx_ring->queue_index,
 253                         IXGBE_READ_REG(hw, tx_ring->head),
 254                         IXGBE_READ_REG(hw, tx_ring->tail),
 255                         tx_ring->next_to_use, eop,
 256                         tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 257                 return true;
 258         }
 259
 260         return false;
 261 }
 262
 263 #define IXGBE_MAX_TXD_PWR       14
 264 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 265
 266 /* Tx Descriptors needed, worst case */
 267 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 268                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 269 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 270         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 271
 272 static void ixgbe_tx_timeout(struct net_device *netdev);
 273
 274 /**
 275  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 276  * @q_vector: structure containing interrupt and ring information
 277  * @tx_ring: tx ring to clean
 278  **/
 279 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 280                                struct ixgbe_ring *tx_ring)
 281 {
 282         struct ixgbe_adapter *adapter = q_vector->adapter;
 283         struct net_device *netdev = adapter->netdev;
 284         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 285         struct ixgbe_tx_buffer *tx_buffer_info;
 286         unsigned int i, eop, count = 0;
 287         unsigned int total_bytes = 0, total_packets = 0;
 288
 289         i = tx_ring->next_to_clean;
 290         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 291         eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 292
 293         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 294                (count < tx_ring->work_limit)) {
 295                 bool cleaned = false;
 296                 for ( ; !cleaned; count++) {
 297                         struct sk_buff *skb;
 298                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
 299                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 300                         cleaned = (i == eop);
 301                         skb = tx_buffer_info->skb;
 302
 303                         if (cleaned && skb) {
 304                                 unsigned int segs, bytecount;
 305                                 unsigned int hlen = skb_headlen(skb);
 306
 307                                 /* gso_segs is currently only valid for tcp */
 308                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
 309 #ifdef IXGBE_FCOE
 310                                 /* adjust for FCoE Sequence Offload */
 311                                 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
 312                                     && (skb->protocol == htons(ETH_P_FCOE)) &&
 313                                     skb_is_gso(skb)) {
 314                                         hlen = skb_transport_offset(skb) +
 315                                                 sizeof(struct fc_frame_header) +
 316                                                 sizeof(struct fcoe_crc_eof);
 317                                         segs = DIV_ROUND_UP(skb->len - hlen,
 318                                                 skb_shinfo(skb)->gso_size);
 319                                 }
 320 #endif /* IXGBE_FCOE */
 321                                 /* multiply data chunks by size of headers */
 322                                 bytecount = ((segs - 1) * hlen) + skb->len;
 323                                 total_packets += segs;
 324                                 total_bytes += bytecount;
 325                         }
 326
 327                         ixgbe_unmap_and_free_tx_resource(adapter,
 328                                                          tx_buffer_info);
 329
 330                         tx_desc->wb.status = 0;
 331
 332                         i++;
 333                         if (i == tx_ring->count)
 334                                 i = 0;
 335                 }
 336
 337                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 338                 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 339         }
 340
 341         tx_ring->next_to_clean = i;
 342
 343 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 344         if (unlikely(count && netif_carrier_ok(netdev) &&
 345                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 346                 /* Make sure that anybody stopping the queue after this
 347                  * sees the new next_to_clean.
 348                  */
 349                 smp_mb();
 350                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
 351                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 352                         netif_wake_subqueue(netdev, tx_ring->queue_index);
 353                         ++adapter->restart_queue;
 354                 }
 355         }
 356
 357         if (adapter->detect_tx_hung) {
 358                 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 359                         /* schedule immediate reset if we believe we hung */
 360                         DPRINTK(PROBE, INFO,
 361                                 "tx hang %d detected, resetting adapter\n",
 362                                 adapter->tx_timeout_count + 1);
 363                         ixgbe_tx_timeout(adapter->netdev);
 364                 }
 365         }
 366
 367         /* re-arm the interrupt */
 368         if (count >= tx_ring->work_limit)
 369                 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
 370
 371         tx_ring->total_bytes += total_bytes;
 372         tx_ring->total_packets += total_packets;
 373         tx_ring->stats.packets += total_packets;
 374         tx_ring->stats.bytes += total_bytes;
 375         adapter->net_stats.tx_bytes += total_bytes;
 376         adapter->net_stats.tx_packets += total_packets;
 377         return (count < tx_ring->work_limit);
 378 }
 379
 380 #ifdef CONFIG_IXGBE_DCA
 381 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 382                                 struct ixgbe_ring *rx_ring)
 383 {
 384         u32 rxctrl;
 385         int cpu = get_cpu();
 386         int q = rx_ring - adapter->rx_ring;
 387
 388         if (rx_ring->cpu != cpu) {
 389                 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
 390                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 391                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 392                         rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 393                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 394                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 395                         rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 396                                    IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 397                 }
 398                 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 399                 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 400                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 401                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 402                             IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 403                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
 404                 rx_ring->cpu = cpu;
 405         }
 406         put_cpu();
 407 }
 408
 409 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 410                                 struct ixgbe_ring *tx_ring)
 411 {
 412         u32 txctrl;
 413         int cpu = get_cpu();
 414         int q = tx_ring - adapter->tx_ring;
 415
 416         if (tx_ring->cpu != cpu) {
 417                 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
 418                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 419                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 420                         txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 421                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 422                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 423                         txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 424                                    IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 425                 }
 426                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 427                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
 428                 tx_ring->cpu = cpu;
 429         }
 430         put_cpu();
 431 }
 432
 433 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 434 {
 435         int i;
 436
 437         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 438                 return;
 439
 440         /* always use CB2 mode, difference is masked in the CB driver */
 441         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 442
 443         for (i = 0; i < adapter->num_tx_queues; i++) {
 444                 adapter->tx_ring[i].cpu = -1;
 445                 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
 446         }
 447         for (i = 0; i < adapter->num_rx_queues; i++) {
 448                 adapter->rx_ring[i].cpu = -1;
 449                 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
 450         }
 451 }
 452
 453 static int __ixgbe_notify_dca(struct device *dev, void *data)
 454 {
 455         struct net_device *netdev = dev_get_drvdata(dev);
 456         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 457         unsigned long event = *(unsigned long *)data;
 458
 459         switch (event) {
 460         case DCA_PROVIDER_ADD:
 461                 /* if we're already enabled, don't do it again */
 462                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 463                         break;
 464                 if (dca_add_requester(dev) == 0) {
 465                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 466                         ixgbe_setup_dca(adapter);
 467                         break;
 468                 }
 469                 /* Fall Through since DCA is disabled. */
 470         case DCA_PROVIDER_REMOVE:
 471                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 472                         dca_remove_requester(dev);
 473                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 474                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 475                 }
 476                 break;
 477         }
 478
 479         return 0;
 480 }
 481
 482 #endif /* CONFIG_IXGBE_DCA */
 483 /**
 484  * ixgbe_receive_skb - Send a completed packet up the stack
 485  * @adapter: board private structure
 486  * @skb: packet to send up
 487  * @status: hardware indication of status of receive
 488  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 489  * @rx_desc: rx descriptor
 490  **/
 491 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 492                               struct sk_buff *skb, u8 status,
 493                               struct ixgbe_ring *ring,
 494                               union ixgbe_adv_rx_desc *rx_desc)
 495 {
 496         struct ixgbe_adapter *adapter = q_vector->adapter;
 497         struct napi_struct *napi = &q_vector->napi;
 498         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 499         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 500
 501         skb_record_rx_queue(skb, ring->queue_index);
 502         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
 503                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 504                         vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
 505                 else
 506                         napi_gro_receive(napi, skb);
 507         } else {
 508                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 509                         vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
 510                 else
 511                         netif_rx(skb);
 512         }
 513 }
 514
 515 /**
 516  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 517  * @adapter: address of board private structure
 518  * @status_err: hardware indication of status of receive
 519  * @skb: skb currently being received and modified
 520  **/
 521 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 522                                      union ixgbe_adv_rx_desc *rx_desc,
 523                                      struct sk_buff *skb)
 524 {
 525         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
 526
 527         skb->ip_summed = CHECKSUM_NONE;
 528
 529         /* Rx csum disabled */
 530         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
 531                 return;
 532
 533         /* if IP and error */
 534         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
 535             (status_err & IXGBE_RXDADV_ERR_IPE)) {
 536                 adapter->hw_csum_rx_error++;
 537                 return;
 538         }
 539
 540         if (!(status_err & IXGBE_RXD_STAT_L4CS))
 541                 return;
 542
 543         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
 544                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 545
 546                 /*
 547                  * 82599 errata, UDP frames with a 0 checksum can be marked as
 548                  * checksum errors.
 549                  */
 550                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
 551                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
 552                         return;
 553
 554                 adapter->hw_csum_rx_error++;
 555                 return;
 556         }
 557
 558         /* It must be a TCP or UDP packet with a valid checksum */
 559         skb->ip_summed = CHECKSUM_UNNECESSARY;
 560         adapter->hw_csum_rx_good++;
 561 }
 562
 563 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
 564                                          struct ixgbe_ring *rx_ring, u32 val)
 565 {
 566         /*
 567          * Force memory writes to complete before letting h/w
 568          * know there are new descriptors to fetch.  (Only
 569          * applicable for weak-ordered memory model archs,
 570          * such as IA-64).
 571          */
 572         wmb();
 573         IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
 574 }
 575
 576 /**
 577  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
 578  * @adapter: address of board private structure
 579  **/
 580 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
 581                                    struct ixgbe_ring *rx_ring,
 582                                    int cleaned_count)
 583 {
 584         struct pci_dev *pdev = adapter->pdev;
 585         union ixgbe_adv_rx_desc *rx_desc;
 586         struct ixgbe_rx_buffer *bi;
 587         unsigned int i;
 588
 589         i = rx_ring->next_to_use;
 590         bi = &rx_ring->rx_buffer_info[i];
 591
 592         while (cleaned_count--) {
 593                 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 594
 595                 if (!bi->page_dma &&
 596                     (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
 597                         if (!bi->page) {
 598                                 bi->page = alloc_page(GFP_ATOMIC);
 599                                 if (!bi->page) {
 600                                         adapter->alloc_rx_page_failed++;
 601                                         goto no_buffers;
 602                                 }
 603                                 bi->page_offset = 0;
 604                         } else {
 605                                 /* use a half page if we're re-using */
 606                                 bi->page_offset ^= (PAGE_SIZE / 2);
 607                         }
 608
 609                         bi->page_dma = pci_map_page(pdev, bi->page,
 610                                                     bi->page_offset,
 611                                                     (PAGE_SIZE / 2),
 612                                                     PCI_DMA_FROMDEVICE);
 613                 }
 614
 615                 if (!bi->skb) {
 616                         struct sk_buff *skb;
 617                         skb = netdev_alloc_skb(adapter->netdev,
 618                                                (rx_ring->rx_buf_len +
 619                                                 NET_IP_ALIGN));
 620
 621                         if (!skb) {
 622                                 adapter->alloc_rx_buff_failed++;
 623                                 goto no_buffers;
 624                         }
 625
 626                         /*
 627                          * Make buffer alignment 2 beyond a 16 byte boundary
 628                          * this will result in a 16 byte aligned IP header after
 629                          * the 14 byte MAC header is removed
 630                          */
 631                         skb_reserve(skb, NET_IP_ALIGN);
 632
 633                         bi->skb = skb;
 634                         bi->dma = pci_map_single(pdev, skb->data,
 635                                                  rx_ring->rx_buf_len,
 636                                                  PCI_DMA_FROMDEVICE);
 637                 }
 638                 /* Refresh the desc even if buffer_addrs didn't change because
 639                  * each write-back erases this info. */
 640                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
 641                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
 642                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
 643                 } else {
 644                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
 645                 }
 646
 647                 i++;
 648                 if (i == rx_ring->count)
 649                         i = 0;
 650                 bi = &rx_ring->rx_buffer_info[i];
 651         }
 652
 653 no_buffers:
 654         if (rx_ring->next_to_use != i) {
 655                 rx_ring->next_to_use = i;
 656                 if (i-- == 0)
 657                         i = (rx_ring->count - 1);
 658
 659                 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
 660         }
 661 }
 662
 663 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
 664 {
 665         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
 666 }
 667
 668 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
 669 {
 670         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 671 }
 672
 673 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
 674 {
 675         return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
 676                 IXGBE_RXDADV_RSCCNT_MASK) >>
 677                 IXGBE_RXDADV_RSCCNT_SHIFT;
 678 }
 679
 680 /**
 681  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
 682  * @skb: pointer to the last skb in the rsc queue
 683  *
 684  * This function changes a queue full of hw rsc buffers into a completed
 685  * packet.  It uses the ->prev pointers to find the first packet and then
 686  * turns it into the frag list owner.
 687  **/
 688 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
 689 {
 690         unsigned int frag_list_size = 0;
 691
 692         while (skb->prev) {
 693                 struct sk_buff *prev = skb->prev;
 694                 frag_list_size += skb->len;
 695                 skb->prev = NULL;
 696                 skb = prev;
 697         }
 698
 699         skb_shinfo(skb)->frag_list = skb->next;
 700         skb->next = NULL;
 701         skb->len += frag_list_size;
 702         skb->data_len += frag_list_size;
 703         skb->truesize += frag_list_size;
 704         return skb;
 705 }
 706
 707 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
 708                                struct ixgbe_ring *rx_ring,
 709                                int *work_done, int work_to_do)
 710 {
 711         struct ixgbe_adapter *adapter = q_vector->adapter;
 712         struct pci_dev *pdev = adapter->pdev;
 713         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
 714         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
 715         struct sk_buff *skb;
 716         unsigned int i, rsc_count = 0;
 717         u32 len, staterr;
 718         u16 hdr_info;
 719         bool cleaned = false;
 720         int cleaned_count = 0;
 721         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
 722 #ifdef IXGBE_FCOE
 723         int ddp_bytes = 0;
 724 #endif /* IXGBE_FCOE */
 725
 726         i = rx_ring->next_to_clean;
 727         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 728         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 729         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 730
 731         while (staterr & IXGBE_RXD_STAT_DD) {
 732                 u32 upper_len = 0;
 733                 if (*work_done >= work_to_do)
 734                         break;
 735                 (*work_done)++;
 736
 737                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
 738                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
 739                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
 740                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
 741                         if (hdr_info & IXGBE_RXDADV_SPH)
 742                                 adapter->rx_hdr_split++;
 743                         if (len > IXGBE_RX_HDR_SIZE)
 744                                 len = IXGBE_RX_HDR_SIZE;
 745                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
 746                 } else {
 747                         len = le16_to_cpu(rx_desc->wb.upper.length);
 748                 }
 749
 750                 cleaned = true;
 751                 skb = rx_buffer_info->skb;
 752                 prefetch(skb->data - NET_IP_ALIGN);
 753                 rx_buffer_info->skb = NULL;
 754
 755                 if (rx_buffer_info->dma) {
 756                         pci_unmap_single(pdev, rx_buffer_info->dma,
 757                                          rx_ring->rx_buf_len,
 758                                          PCI_DMA_FROMDEVICE);
 759                         rx_buffer_info->dma = 0;
 760                         skb_put(skb, len);
 761                 }
 762
 763                 if (upper_len) {
 764                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
 765                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
 766                         rx_buffer_info->page_dma = 0;
 767                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
 768                                            rx_buffer_info->page,
 769                                            rx_buffer_info->page_offset,
 770                                            upper_len);
 771
 772                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
 773                             (page_count(rx_buffer_info->page) != 1))
 774                                 rx_buffer_info->page = NULL;
 775                         else
 776                                 get_page(rx_buffer_info->page);
 777
 778                         skb->len += upper_len;
 779                         skb->data_len += upper_len;
 780                         skb->truesize += upper_len;
 781                 }
 782
 783                 i++;
 784                 if (i == rx_ring->count)
 785                         i = 0;
 786
 787                 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
 788                 prefetch(next_rxd);
 789                 cleaned_count++;
 790
 791                 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
 792                         rsc_count = ixgbe_get_rsc_count(rx_desc);
 793
 794                 if (rsc_count) {
 795                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
 796                                      IXGBE_RXDADV_NEXTP_SHIFT;
 797                         next_buffer = &rx_ring->rx_buffer_info[nextp];
 798                         rx_ring->rsc_count += (rsc_count - 1);
 799                 } else {
 800                         next_buffer = &rx_ring->rx_buffer_info[i];
 801                 }
 802
 803                 if (staterr & IXGBE_RXD_STAT_EOP) {
 804                         if (skb->prev)
 805                                 skb = ixgbe_transform_rsc_queue(skb);
 806                         rx_ring->stats.packets++;
 807                         rx_ring->stats.bytes += skb->len;
 808                 } else {
 809                         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
 810                                 rx_buffer_info->skb = next_buffer->skb;
 811                                 rx_buffer_info->dma = next_buffer->dma;
 812                                 next_buffer->skb = skb;
 813                                 next_buffer->dma = 0;
 814                         } else {
 815                                 skb->next = next_buffer->skb;
 816                                 skb->next->prev = skb;
 817                         }
 818                         adapter->non_eop_descs++;
 819                         goto next_desc;
 820                 }
 821
 822                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
 823                         dev_kfree_skb_irq(skb);
 824                         goto next_desc;
 825                 }
 826
 827                 ixgbe_rx_checksum(adapter, rx_desc, skb);
 828
 829                 /* probably a little skewed due to removing CRC */
 830                 total_rx_bytes += skb->len;
 831                 total_rx_packets++;
 832
 833                 skb->protocol = eth_type_trans(skb, adapter->netdev);
 834 #ifdef IXGBE_FCOE
 835                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
 836                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
 837                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
 838                         if (!ddp_bytes)
 839                                 goto next_desc;
 840                 }
 841 #endif /* IXGBE_FCOE */
 842                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
 843
 844 next_desc:
 845                 rx_desc->wb.upper.status_error = 0;
 846
 847                 /* return some buffers to hardware, one at a time is too slow */
 848                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
 849                         ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 850                         cleaned_count = 0;
 851                 }
 852
 853                 /* use prefetched values */
 854                 rx_desc = next_rxd;
 855                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
 856
 857                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 858         }
 859
 860         rx_ring->next_to_clean = i;
 861         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
 862
 863         if (cleaned_count)
 864                 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 865
 866 #ifdef IXGBE_FCOE
 867         /* include DDPed FCoE data */
 868         if (ddp_bytes > 0) {
 869                 unsigned int mss;
 870
 871                 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
 872                         sizeof(struct fc_frame_header) -
 873                         sizeof(struct fcoe_crc_eof);
 874                 if (mss > 512)
 875                         mss &= ~511;
 876                 total_rx_bytes += ddp_bytes;
 877                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
 878         }
 879 #endif /* IXGBE_FCOE */
 880
 881         rx_ring->total_packets += total_rx_packets;
 882         rx_ring->total_bytes += total_rx_bytes;
 883         adapter->net_stats.rx_bytes += total_rx_bytes;
 884         adapter->net_stats.rx_packets += total_rx_packets;
 885
 886         return cleaned;
 887 }
 888
 889 static int ixgbe_clean_rxonly(struct napi_struct *, int);
 890 /**
 891  * ixgbe_configure_msix - Configure MSI-X hardware
 892  * @adapter: board private structure
 893  *
 894  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
 895  * interrupts.
 896  **/
 897 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
 898 {
 899         struct ixgbe_q_vector *q_vector;
 900         int i, j, q_vectors, v_idx, r_idx;
 901         u32 mask;
 902
 903         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
 904
 905         /*
 906          * Populate the IVAR table and set the ITR values to the
 907          * corresponding register.
 908          */
 909         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
 910                 q_vector = adapter->q_vector[v_idx];
 911                 /* XXX for_each_bit(...) */
 912                 r_idx = find_first_bit(q_vector->rxr_idx,
 913                                        adapter->num_rx_queues);
 914
 915                 for (i = 0; i < q_vector->rxr_count; i++) {
 916                         j = adapter->rx_ring[r_idx].reg_idx;
 917                         ixgbe_set_ivar(adapter, 0, j, v_idx);
 918                         r_idx = find_next_bit(q_vector->rxr_idx,
 919                                               adapter->num_rx_queues,
 920                                               r_idx + 1);
 921                 }
 922                 r_idx = find_first_bit(q_vector->txr_idx,
 923                                        adapter->num_tx_queues);
 924
 925                 for (i = 0; i < q_vector->txr_count; i++) {
 926                         j = adapter->tx_ring[r_idx].reg_idx;
 927                         ixgbe_set_ivar(adapter, 1, j, v_idx);
 928                         r_idx = find_next_bit(q_vector->txr_idx,
 929                                               adapter->num_tx_queues,
 930                                               r_idx + 1);
 931                 }
 932
 933                 if (q_vector->txr_count && !q_vector->rxr_count)
 934                         /* tx only */
 935                         q_vector->eitr = adapter->tx_eitr_param;
 936                 else if (q_vector->rxr_count)
 937                         /* rx or mixed */
 938                         q_vector->eitr = adapter->rx_eitr_param;
 939
 940                 ixgbe_write_eitr(q_vector);
 941         }
 942
 943         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
 944                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
 945                                v_idx);
 946         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
 947                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
 948         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
 949
 950         /* set up to autoclear timer, and the vectors */
 951         mask = IXGBE_EIMS_ENABLE_MASK;
 952         mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
 953         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
 954 }
 955
 956 enum latency_range {
 957         lowest_latency = 0,
 958         low_latency = 1,
 959         bulk_latency = 2,
 960         latency_invalid = 255
 961 };
 962
 963 /**
 964  * ixgbe_update_itr - update the dynamic ITR value based on statistics
 965  * @adapter: pointer to adapter
 966  * @eitr: eitr setting (ints per sec) to give last timeslice
 967  * @itr_setting: current throttle rate in ints/second
 968  * @packets: the number of packets during this measurement interval
 969  * @bytes: the number of bytes during this measurement interval
 970  *
 971  *      Stores a new ITR value based on packets and byte
 972  *      counts during the last interrupt.  The advantage of per interrupt
 973  *      computation is faster updates and more accurate ITR for the current
 974  *      traffic pattern.  Constants in this function were computed
 975  *      based on theoretical maximum wire speed and thresholds were set based
 976  *      on testing data as well as attempting to minimize response time
 977  *      while increasing bulk throughput.
 978  *      this functionality is controlled by the InterruptThrottleRate module
 979  *      parameter (see ixgbe_param.c)
 980  **/
 981 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
 982                            u32 eitr, u8 itr_setting,
 983                            int packets, int bytes)
 984 {
 985         unsigned int retval = itr_setting;
 986         u32 timepassed_us;
 987         u64 bytes_perint;
 988
 989         if (packets == 0)
 990                 goto update_itr_done;
 991
 992
 993         /* simple throttlerate management
 994          *    0-20MB/s lowest (100000 ints/s)
 995          *   20-100MB/s low   (20000 ints/s)
 996          *  100-1249MB/s bulk (8000 ints/s)
 997          */
 998         /* what was last interrupt timeslice? */
 999         timepassed_us = 1000000/eitr;
1000         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1001
1002         switch (itr_setting) {
1003         case lowest_latency:
1004                 if (bytes_perint > adapter->eitr_low)
1005                         retval = low_latency;
1006                 break;
1007         case low_latency:
1008                 if (bytes_perint > adapter->eitr_high)
1009                         retval = bulk_latency;
1010                 else if (bytes_perint <= adapter->eitr_low)
1011                         retval = lowest_latency;
1012                 break;
1013         case bulk_latency:
1014                 if (bytes_perint <= adapter->eitr_high)
1015                         retval = low_latency;
1016                 break;
1017         }
1018
1019 update_itr_done:
1020         return retval;
1021 }
1022
1023 /**
1024  * ixgbe_write_eitr - write EITR register in hardware specific way
1025  * @q_vector: structure containing interrupt and ring information
1026  *
1027  * This function is made to be called by ethtool and by the driver
1028  * when it needs to update EITR registers at runtime.  Hardware
1029  * specific quirks/differences are taken care of here.
1030  */
1031 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1032 {
1033         struct ixgbe_adapter *adapter = q_vector->adapter;
1034         struct ixgbe_hw *hw = &adapter->hw;
1035         int v_idx = q_vector->v_idx;
1036         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1037
1038         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1039                 /* must write high and low 16 bits to reset counter */
1040                 itr_reg |= (itr_reg << 16);
1041         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1042                 /*
1043                  * set the WDIS bit to not clear the timer bits and cause an
1044                  * immediate assertion of the interrupt
1045                  */
1046                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1047         }
1048         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1049 }
1050
1051 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1052 {
1053         struct ixgbe_adapter *adapter = q_vector->adapter;
1054         u32 new_itr;
1055         u8 current_itr, ret_itr;
1056         int i, r_idx;
1057         struct ixgbe_ring *rx_ring, *tx_ring;
1058
1059         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1060         for (i = 0; i < q_vector->txr_count; i++) {
1061                 tx_ring = &(adapter->tx_ring[r_idx]);
1062                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1063                                            q_vector->tx_itr,
1064                                            tx_ring->total_packets,
1065                                            tx_ring->total_bytes);
1066                 /* if the result for this queue would decrease interrupt
1067                  * rate for this vector then use that result */
1068                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1069                                     q_vector->tx_itr - 1 : ret_itr);
1070                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1071                                       r_idx + 1);
1072         }
1073
1074         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1075         for (i = 0; i < q_vector->rxr_count; i++) {
1076                 rx_ring = &(adapter->rx_ring[r_idx]);
1077                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1078                                            q_vector->rx_itr,
1079                                            rx_ring->total_packets,
1080                                            rx_ring->total_bytes);
1081                 /* if the result for this queue would decrease interrupt
1082                  * rate for this vector then use that result */
1083                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1084                                     q_vector->rx_itr - 1 : ret_itr);
1085                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1086                                       r_idx + 1);
1087         }
1088
1089         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1090
1091         switch (current_itr) {
1092         /* counts and packets in update_itr are dependent on these numbers */
1093         case lowest_latency:
1094                 new_itr = 100000;
1095                 break;
1096         case low_latency:
1097                 new_itr = 20000; /* aka hwitr = ~200 */
1098                 break;
1099         case bulk_latency:
1100         default:
1101                 new_itr = 8000;
1102                 break;
1103         }
1104
1105         if (new_itr != q_vector->eitr) {
1106                 /* do an exponential smoothing */
1107                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1108
1109                 /* save the algorithm value here, not the smoothed one */
1110                 q_vector->eitr = new_itr;
1111
1112                 ixgbe_write_eitr(q_vector);
1113         }
1114
1115         return;
1116 }
1117
1118 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1119 {
1120         struct ixgbe_hw *hw = &adapter->hw;
1121
1122         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1123             (eicr & IXGBE_EICR_GPI_SDP1)) {
1124                 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1125                 /* write to clear the interrupt */
1126                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1127         }
1128 }
1129
1130 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1131 {
1132         struct ixgbe_hw *hw = &adapter->hw;
1133
1134         if (eicr & IXGBE_EICR_GPI_SDP1) {
1135                 /* Clear the interrupt */
1136                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1137                 schedule_work(&adapter->multispeed_fiber_task);
1138         } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1139                 /* Clear the interrupt */
1140                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1141                 schedule_work(&adapter->sfp_config_module_task);
1142         } else {
1143                 /* Interrupt isn't for us... */
1144                 return;
1145         }
1146 }
1147
1148 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1149 {
1150         struct ixgbe_hw *hw = &adapter->hw;
1151
1152         adapter->lsc_int++;
1153         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1154         adapter->link_check_timeout = jiffies;
1155         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1156                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1157                 schedule_work(&adapter->watchdog_task);
1158         }
1159 }
1160
1161 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1162 {
1163         struct net_device *netdev = data;
1164         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1165         struct ixgbe_hw *hw = &adapter->hw;
1166         u32 eicr;
1167
1168         /*
1169          * Workaround for Silicon errata.  Use clear-by-write instead
1170          * of clear-by-read.  Reading with EICS will return the
1171          * interrupt causes without clearing, which later be done
1172          * with the write to EICR.
1173          */
1174         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1175         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1176
1177         if (eicr & IXGBE_EICR_LSC)
1178                 ixgbe_check_lsc(adapter);
1179
1180         if (hw->mac.type == ixgbe_mac_82598EB)
1181                 ixgbe_check_fan_failure(adapter, eicr);
1182
1183         if (hw->mac.type == ixgbe_mac_82599EB) {
1184                 ixgbe_check_sfp_event(adapter, eicr);
1185
1186                 /* Handle Flow Director Full threshold interrupt */
1187                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1188                         int i;
1189                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1190                         /* Disable transmits before FDIR Re-initialization */
1191                         netif_tx_stop_all_queues(netdev);
1192                         for (i = 0; i < adapter->num_tx_queues; i++) {
1193                                 struct ixgbe_ring *tx_ring =
1194                                                            &adapter->tx_ring[i];
1195                                 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1196                                                        &tx_ring->reinit_state))
1197                                         schedule_work(&adapter->fdir_reinit_task);
1198                         }
1199                 }
1200         }
1201         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1202                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1203
1204         return IRQ_HANDLED;
1205 }
1206
1207 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1208                                            u64 qmask)
1209 {
1210         u32 mask;
1211
1212         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1213                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1214                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1215         } else {
1216                 mask = (qmask & 0xFFFFFFFF);
1217                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1218                 mask = (qmask >> 32);
1219                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1220         }
1221         /* skip the flush */
1222 }
1223
1224 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1225                                             u64 qmask)
1226 {
1227         u32 mask;
1228
1229         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1230                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1231                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1232         } else {
1233                 mask = (qmask & 0xFFFFFFFF);
1234                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1235                 mask = (qmask >> 32);
1236                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1237         }
1238         /* skip the flush */
1239 }
1240
1241 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1242 {
1243         struct ixgbe_q_vector *q_vector = data;
1244         struct ixgbe_adapter  *adapter = q_vector->adapter;
1245         struct ixgbe_ring     *tx_ring;
1246         int i, r_idx;
1247
1248         if (!q_vector->txr_count)
1249                 return IRQ_HANDLED;
1250
1251         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1252         for (i = 0; i < q_vector->txr_count; i++) {
1253                 tx_ring = &(adapter->tx_ring[r_idx]);
1254                 tx_ring->total_bytes = 0;
1255                 tx_ring->total_packets = 0;
1256                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1257                                       r_idx + 1);
1258         }
1259
1260         /* disable interrupts on this vector only */
1261         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1262         napi_schedule(&q_vector->napi);
1263
1264         return IRQ_HANDLED;
1265 }
1266
1267 /**
1268  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1269  * @irq: unused
1270  * @data: pointer to our q_vector struct for this interrupt vector
1271  **/
1272 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1273 {
1274         struct ixgbe_q_vector *q_vector = data;
1275         struct ixgbe_adapter  *adapter = q_vector->adapter;
1276         struct ixgbe_ring  *rx_ring;
1277         int r_idx;
1278         int i;
1279
1280         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1281         for (i = 0;  i < q_vector->rxr_count; i++) {
1282                 rx_ring = &(adapter->rx_ring[r_idx]);
1283                 rx_ring->total_bytes = 0;
1284                 rx_ring->total_packets = 0;
1285                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1286                                       r_idx + 1);
1287         }
1288
1289         if (!q_vector->rxr_count)
1290                 return IRQ_HANDLED;
1291
1292         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1293         rx_ring = &(adapter->rx_ring[r_idx]);
1294         /* disable interrupts on this vector only */
1295         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1296         napi_schedule(&q_vector->napi);
1297
1298         return IRQ_HANDLED;
1299 }
1300
1301 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1302 {
1303         struct ixgbe_q_vector *q_vector = data;
1304         struct ixgbe_adapter  *adapter = q_vector->adapter;
1305         struct ixgbe_ring  *ring;
1306         int r_idx;
1307         int i;
1308
1309         if (!q_vector->txr_count && !q_vector->rxr_count)
1310                 return IRQ_HANDLED;
1311
1312         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1313         for (i = 0; i < q_vector->txr_count; i++) {
1314                 ring = &(adapter->tx_ring[r_idx]);
1315                 ring->total_bytes = 0;
1316                 ring->total_packets = 0;
1317                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1318                                       r_idx + 1);
1319         }
1320
1321         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1322         for (i = 0; i < q_vector->rxr_count; i++) {
1323                 ring = &(adapter->rx_ring[r_idx]);
1324                 ring->total_bytes = 0;
1325                 ring->total_packets = 0;
1326                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1327                                       r_idx + 1);
1328         }
1329
1330         /* disable interrupts on this vector only */
1331         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1332         napi_schedule(&q_vector->napi);
1333
1334         return IRQ_HANDLED;
1335 }
1336
1337 /**
1338  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1339  * @napi: napi struct with our devices info in it
1340  * @budget: amount of work driver is allowed to do this pass, in packets
1341  *
1342  * This function is optimized for cleaning one queue only on a single
1343  * q_vector!!!
1344  **/
1345 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1346 {
1347         struct ixgbe_q_vector *q_vector =
1348                                container_of(napi, struct ixgbe_q_vector, napi);
1349         struct ixgbe_adapter *adapter = q_vector->adapter;
1350         struct ixgbe_ring *rx_ring = NULL;
1351         int work_done = 0;
1352         long r_idx;
1353
1354         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1355         rx_ring = &(adapter->rx_ring[r_idx]);
1356 #ifdef CONFIG_IXGBE_DCA
1357         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1358                 ixgbe_update_rx_dca(adapter, rx_ring);
1359 #endif
1360
1361         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1362
1363         /* If all Rx work done, exit the polling mode */
1364         if (work_done < budget) {
1365                 napi_complete(napi);
1366                 if (adapter->rx_itr_setting & 1)
1367                         ixgbe_set_itr_msix(q_vector);
1368                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1369                         ixgbe_irq_enable_queues(adapter,
1370                                                 ((u64)1 << q_vector->v_idx));
1371         }
1372
1373         return work_done;
1374 }
1375
1376 /**
1377  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1378  * @napi: napi struct with our devices info in it
1379  * @budget: amount of work driver is allowed to do this pass, in packets
1380  *
1381  * This function will clean more than one rx queue associated with a
1382  * q_vector.
1383  **/
1384 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1385 {
1386         struct ixgbe_q_vector *q_vector =
1387                                container_of(napi, struct ixgbe_q_vector, napi);
1388         struct ixgbe_adapter *adapter = q_vector->adapter;
1389         struct ixgbe_ring *ring = NULL;
1390         int work_done = 0, i;
1391         long r_idx;
1392         bool tx_clean_complete = true;
1393
1394         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1395         for (i = 0; i < q_vector->txr_count; i++) {
1396                 ring = &(adapter->tx_ring[r_idx]);
1397 #ifdef CONFIG_IXGBE_DCA
1398                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1399                         ixgbe_update_tx_dca(adapter, ring);
1400 #endif
1401                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1402                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1403                                       r_idx + 1);
1404         }
1405
1406         /* attempt to distribute budget to each queue fairly, but don't allow
1407          * the budget to go below 1 because we'll exit polling */
1408         budget /= (q_vector->rxr_count ?: 1);
1409         budget = max(budget, 1);
1410         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1411         for (i = 0; i < q_vector->rxr_count; i++) {
1412                 ring = &(adapter->rx_ring[r_idx]);
1413 #ifdef CONFIG_IXGBE_DCA
1414                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1415                         ixgbe_update_rx_dca(adapter, ring);
1416 #endif
1417                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1418                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1419                                       r_idx + 1);
1420         }
1421
1422         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1423         ring = &(adapter->rx_ring[r_idx]);
1424         /* If all Rx work done, exit the polling mode */
1425         if (work_done < budget) {
1426                 napi_complete(napi);
1427                 if (adapter->rx_itr_setting & 1)
1428                         ixgbe_set_itr_msix(q_vector);
1429                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1430                         ixgbe_irq_enable_queues(adapter,
1431                                                 ((u64)1 << q_vector->v_idx));
1432                 return 0;
1433         }
1434
1435         return work_done;
1436 }
1437
1438 /**
1439  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1440  * @napi: napi struct with our devices info in it
1441  * @budget: amount of work driver is allowed to do this pass, in packets
1442  *
1443  * This function is optimized for cleaning one queue only on a single
1444  * q_vector!!!
1445  **/
1446 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1447 {
1448         struct ixgbe_q_vector *q_vector =
1449                                container_of(napi, struct ixgbe_q_vector, napi);
1450         struct ixgbe_adapter *adapter = q_vector->adapter;
1451         struct ixgbe_ring *tx_ring = NULL;
1452         int work_done = 0;
1453         long r_idx;
1454
1455         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1456         tx_ring = &(adapter->tx_ring[r_idx]);
1457 #ifdef CONFIG_IXGBE_DCA
1458         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1459                 ixgbe_update_tx_dca(adapter, tx_ring);
1460 #endif
1461
1462         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1463                 work_done = budget;
1464
1465         /* If all Tx work done, exit the polling mode */
1466         if (work_done < budget) {
1467                 napi_complete(napi);
1468                 if (adapter->tx_itr_setting & 1)
1469                         ixgbe_set_itr_msix(q_vector);
1470                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1471                         ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1472         }
1473
1474         return work_done;
1475 }
1476
1477 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1478                                      int r_idx)
1479 {
1480         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1481
1482         set_bit(r_idx, q_vector->rxr_idx);
1483         q_vector->rxr_count++;
1484 }
1485
1486 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1487                                      int t_idx)
1488 {
1489         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1490
1491         set_bit(t_idx, q_vector->txr_idx);
1492         q_vector->txr_count++;
1493 }
1494
1495 /**
1496  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1497  * @adapter: board private structure to initialize
1498  * @vectors: allotted vector count for descriptor rings
1499  *
1500  * This function maps descriptor rings to the queue-specific vectors
1501  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
1502  * one vector per ring/queue, but on a constrained vector budget, we
1503  * group the rings as "efficiently" as possible.  You would add new
1504  * mapping configurations in here.
1505  **/
1506 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1507                                       int vectors)
1508 {
1509         int v_start = 0;
1510         int rxr_idx = 0, txr_idx = 0;
1511         int rxr_remaining = adapter->num_rx_queues;
1512         int txr_remaining = adapter->num_tx_queues;
1513         int i, j;
1514         int rqpv, tqpv;
1515         int err = 0;
1516
1517         /* No mapping required if MSI-X is disabled. */
1518         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1519                 goto out;
1520
1521         /*
1522          * The ideal configuration...
1523          * We have enough vectors to map one per queue.
1524          */
1525         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1526                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1527                         map_vector_to_rxq(adapter, v_start, rxr_idx);
1528
1529                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1530                         map_vector_to_txq(adapter, v_start, txr_idx);
1531
1532                 goto out;
1533         }
1534
1535         /*
1536          * If we don't have enough vectors for a 1-to-1
1537          * mapping, we'll have to group them so there are
1538          * multiple queues per vector.
1539          */
1540         /* Re-adjusting *qpv takes care of the remainder. */
1541         for (i = v_start; i < vectors; i++) {
1542                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1543                 for (j = 0; j < rqpv; j++) {
1544                         map_vector_to_rxq(adapter, i, rxr_idx);
1545                         rxr_idx++;
1546                         rxr_remaining--;
1547                 }
1548         }
1549         for (i = v_start; i < vectors; i++) {
1550                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1551                 for (j = 0; j < tqpv; j++) {
1552                         map_vector_to_txq(adapter, i, txr_idx);
1553                         txr_idx++;
1554                         txr_remaining--;
1555                 }
1556         }
1557
1558 out:
1559         return err;
1560 }
1561
1562 /**
1563  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1564  * @adapter: board private structure
1565  *
1566  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1567  * interrupts from the kernel.
1568  **/
1569 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1570 {
1571         struct net_device *netdev = adapter->netdev;
1572         irqreturn_t (*handler)(int, void *);
1573         int i, vector, q_vectors, err;
1574         int ri=0, ti=0;
1575
1576         /* Decrement for Other and TCP Timer vectors */
1577         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1578
1579         /* Map the Tx/Rx rings to the vectors we were allotted. */
1580         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1581         if (err)
1582                 goto out;
1583
1584 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1585                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1586                          &ixgbe_msix_clean_many)
1587         for (vector = 0; vector < q_vectors; vector++) {
1588                 handler = SET_HANDLER(adapter->q_vector[vector]);
1589
1590                 if(handler == &ixgbe_msix_clean_rx) {
1591                         sprintf(adapter->name[vector], "%s-%s-%d",
1592                                 netdev->name, "rx", ri++);
1593                 }
1594                 else if(handler == &ixgbe_msix_clean_tx) {
1595                         sprintf(adapter->name[vector], "%s-%s-%d",
1596                                 netdev->name, "tx", ti++);
1597                 }
1598                 else
1599                         sprintf(adapter->name[vector], "%s-%s-%d",
1600                                 netdev->name, "TxRx", vector);
1601
1602                 err = request_irq(adapter->msix_entries[vector].vector,
1603                                   handler, 0, adapter->name[vector],
1604                                   adapter->q_vector[vector]);
1605                 if (err) {
1606                         DPRINTK(PROBE, ERR,
1607                                 "request_irq failed for MSIX interrupt "
1608                                 "Error: %d\n", err);
1609                         goto free_queue_irqs;
1610                 }
1611         }
1612
1613         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1614         err = request_irq(adapter->msix_entries[vector].vector,
1615                           &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
1616         if (err) {
1617                 DPRINTK(PROBE, ERR,
1618                         "request_irq for msix_lsc failed: %d\n", err);
1619                 goto free_queue_irqs;
1620         }
1621
1622         return 0;
1623
1624 free_queue_irqs:
1625         for (i = vector - 1; i >= 0; i--)
1626                 free_irq(adapter->msix_entries[--vector].vector,
1627                          adapter->q_vector[i]);
1628         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1629         pci_disable_msix(adapter->pdev);
1630         kfree(adapter->msix_entries);
1631         adapter->msix_entries = NULL;
1632 out:
1633         return err;
1634 }
1635
1636 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1637 {
1638         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1639         u8 current_itr;
1640         u32 new_itr = q_vector->eitr;
1641         struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1642         struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1643
1644         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
1645                                             q_vector->tx_itr,
1646                                             tx_ring->total_packets,
1647                                             tx_ring->total_bytes);
1648         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
1649                                             q_vector->rx_itr,
1650                                             rx_ring->total_packets,
1651                                             rx_ring->total_bytes);
1652
1653         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1654
1655         switch (current_itr) {
1656         /* counts and packets in update_itr are dependent on these numbers */
1657         case lowest_latency:
1658                 new_itr = 100000;
1659                 break;
1660         case low_latency:
1661                 new_itr = 20000; /* aka hwitr = ~200 */
1662                 break;
1663         case bulk_latency:
1664                 new_itr = 8000;
1665                 break;
1666         default:
1667                 break;
1668         }
1669
1670         if (new_itr != q_vector->eitr) {
1671                 /* do an exponential smoothing */
1672                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1673
1674                 /* save the algorithm value here, not the smoothed one */
1675                 q_vector->eitr = new_itr;
1676
1677                 ixgbe_write_eitr(q_vector);
1678         }
1679
1680         return;
1681 }
1682
1683 /**
1684  * ixgbe_irq_enable - Enable default interrupt generation settings
1685  * @adapter: board private structure
1686  **/
1687 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1688 {
1689         u32 mask;
1690
1691         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1692         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1693                 mask |= IXGBE_EIMS_GPI_SDP1;
1694         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1695                 mask |= IXGBE_EIMS_ECC;
1696                 mask |= IXGBE_EIMS_GPI_SDP1;
1697                 mask |= IXGBE_EIMS_GPI_SDP2;
1698         }
1699         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1700             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1701                 mask |= IXGBE_EIMS_FLOW_DIR;
1702
1703         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1704         ixgbe_irq_enable_queues(adapter, ~0);
1705         IXGBE_WRITE_FLUSH(&adapter->hw);
1706 }
1707
1708 /**
1709  * ixgbe_intr - legacy mode Interrupt Handler
1710  * @irq: interrupt number
1711  * @data: pointer to a network interface device structure
1712  **/
1713 static irqreturn_t ixgbe_intr(int irq, void *data)
1714 {
1715         struct net_device *netdev = data;
1716         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1717         struct ixgbe_hw *hw = &adapter->hw;
1718         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1719         u32 eicr;
1720
1721         /*
1722          * Workaround for silicon errata.  Mask the interrupts
1723          * before the read of EICR.
1724          */
1725         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1726
1727         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1728          * therefore no explict interrupt disable is necessary */
1729         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1730         if (!eicr) {
1731                 /* shared interrupt alert!
1732                  * make sure interrupts are enabled because the read will
1733                  * have disabled interrupts due to EIAM */
1734                 ixgbe_irq_enable(adapter);
1735                 return IRQ_NONE;        /* Not our interrupt */
1736         }
1737
1738         if (eicr & IXGBE_EICR_LSC)
1739                 ixgbe_check_lsc(adapter);
1740
1741         if (hw->mac.type == ixgbe_mac_82599EB)
1742                 ixgbe_check_sfp_event(adapter, eicr);
1743
1744         ixgbe_check_fan_failure(adapter, eicr);
1745
1746         if (napi_schedule_prep(&(q_vector->napi))) {
1747                 adapter->tx_ring[0].total_packets = 0;
1748                 adapter->tx_ring[0].total_bytes = 0;
1749                 adapter->rx_ring[0].total_packets = 0;
1750                 adapter->rx_ring[0].total_bytes = 0;
1751                 /* would disable interrupts here but EIAM disabled it */
1752                 __napi_schedule(&(q_vector->napi));
1753         }
1754
1755         return IRQ_HANDLED;
1756 }
1757
1758 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1759 {
1760         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1761
1762         for (i = 0; i < q_vectors; i++) {
1763                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
1764                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1765                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1766                 q_vector->rxr_count = 0;
1767                 q_vector->txr_count = 0;
1768         }
1769 }
1770
1771 /**
1772  * ixgbe_request_irq - initialize interrupts
1773  * @adapter: board private structure
1774  *
1775  * Attempts to configure interrupts using the best available
1776  * capabilities of the hardware and kernel.
1777  **/
1778 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
1779 {
1780         struct net_device *netdev = adapter->netdev;
1781         int err;
1782
1783         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1784                 err = ixgbe_request_msix_irqs(adapter);
1785         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1786                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
1787                                   netdev->name, netdev);
1788         } else {
1789                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
1790                                   netdev->name, netdev);
1791         }
1792
1793         if (err)
1794                 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1795
1796         return err;
1797 }
1798
1799 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1800 {
1801         struct net_device *netdev = adapter->netdev;
1802
1803         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1804                 int i, q_vectors;
1805
1806                 q_vectors = adapter->num_msix_vectors;
1807
1808                 i = q_vectors - 1;
1809                 free_irq(adapter->msix_entries[i].vector, netdev);
1810
1811                 i--;
1812                 for (; i >= 0; i--) {
1813                         free_irq(adapter->msix_entries[i].vector,
1814                                  adapter->q_vector[i]);
1815                 }
1816
1817                 ixgbe_reset_q_vectors(adapter);
1818         } else {
1819                 free_irq(adapter->pdev->irq, netdev);
1820         }
1821 }
1822
1823 /**
1824  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1825  * @adapter: board private structure
1826  **/
1827 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1828 {
1829         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1830                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1831         } else {
1832                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1833                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
1834                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1835         }
1836         IXGBE_WRITE_FLUSH(&adapter->hw);
1837         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1838                 int i;
1839                 for (i = 0; i < adapter->num_msix_vectors; i++)
1840                         synchronize_irq(adapter->msix_entries[i].vector);
1841         } else {
1842                 synchronize_irq(adapter->pdev->irq);
1843         }
1844 }
1845
1846 /**
1847  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1848  *
1849  **/
1850 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1851 {
1852         struct ixgbe_hw *hw = &adapter->hw;
1853
1854         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1855                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
1856
1857         ixgbe_set_ivar(adapter, 0, 0, 0);
1858         ixgbe_set_ivar(adapter, 1, 0, 0);
1859
1860         map_vector_to_rxq(adapter, 0, 0);
1861         map_vector_to_txq(adapter, 0, 0);
1862
1863         DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
1864 }
1865
1866 /**
1867  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
1868  * @adapter: board private structure
1869  *
1870  * Configure the Tx unit of the MAC after a reset.
1871  **/
1872 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1873 {
1874         u64 tdba;
1875         struct ixgbe_hw *hw = &adapter->hw;
1876         u32 i, j, tdlen, txctrl;
1877
1878         /* Setup the HW Tx Head and Tail descriptor pointers */
1879         for (i = 0; i < adapter->num_tx_queues; i++) {
1880                 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1881                 j = ring->reg_idx;
1882                 tdba = ring->dma;
1883                 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
1884                 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
1885                                 (tdba & DMA_BIT_MASK(32)));
1886                 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1887                 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1888                 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1889                 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1890                 adapter->tx_ring[i].head = IXGBE_TDH(j);
1891                 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1892                 /*
1893                  * Disable Tx Head Writeback RO bit, since this hoses
1894                  * bookkeeping if things aren't delivered in order.
1895                  */
1896                 switch (hw->mac.type) {
1897                 case ixgbe_mac_82598EB:
1898                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
1899                         break;
1900                 case ixgbe_mac_82599EB:
1901                 default:
1902                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
1903                         break;
1904                 }
1905                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1906                 switch (hw->mac.type) {
1907                 case ixgbe_mac_82598EB:
1908                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
1909                         break;
1910                 case ixgbe_mac_82599EB:
1911                 default:
1912                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl);
1913                         break;
1914                 }
1915         }
1916         if (hw->mac.type == ixgbe_mac_82599EB) {
1917                 /* We enable 8 traffic classes, DCB only */
1918                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1919                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1920                                         IXGBE_MTQC_8TC_8TQ));
1921         }
1922 }
1923
1924 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1925
1926 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
1927                                    struct ixgbe_ring *rx_ring)
1928 {
1929         u32 srrctl;
1930         int index;
1931         struct ixgbe_ring_feature *feature = adapter->ring_feature;
1932
1933         index = rx_ring->reg_idx;
1934         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1935                 unsigned long mask;
1936                 mask = (unsigned long) feature[RING_F_RSS].mask;
1937                 index = index & mask;
1938         }
1939         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1940
1941         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1942         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1943
1944         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1945                   IXGBE_SRRCTL_BSIZEHDR_MASK;
1946
1947         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1948 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
1949                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1950 #else
1951                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1952 #endif
1953                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1954         } else {
1955                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
1956                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1957                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1958         }
1959
1960         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1961 }
1962
1963 static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
1964 {
1965         u32 mrqc = 0;
1966         int mask;
1967
1968         if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
1969                 return mrqc;
1970
1971         mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
1972 #ifdef CONFIG_IXGBE_DCB
1973                                  | IXGBE_FLAG_DCB_ENABLED
1974 #endif
1975                                 );
1976
1977         switch (mask) {
1978         case (IXGBE_FLAG_RSS_ENABLED):
1979                 mrqc = IXGBE_MRQC_RSSEN;
1980                 break;
1981 #ifdef CONFIG_IXGBE_DCB
1982         case (IXGBE_FLAG_DCB_ENABLED):
1983                 mrqc = IXGBE_MRQC_RT8TCEN;
1984                 break;
1985 #endif /* CONFIG_IXGBE_DCB */
1986         default:
1987                 break;
1988         }
1989
1990         return mrqc;
1991 }
1992
1993 /**
1994  * ixgbe_configure_rscctl - enable RSC for the indicated ring
1995  * @adapter:    address of board private structure
1996  * @index:      index of ring to set
1997  * @rx_buf_len: rx buffer length
1998  **/
1999 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index,
2000                                    int rx_buf_len)
2001 {
2002         struct ixgbe_ring *rx_ring;
2003         struct ixgbe_hw *hw = &adapter->hw;
2004         int j;
2005         u32 rscctrl;
2006
2007         rx_ring = &adapter->rx_ring[index];
2008         j = rx_ring->reg_idx;
2009         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2010         rscctrl |= IXGBE_RSCCTL_RSCEN;
2011         /*
2012          * we must limit the number of descriptors so that the
2013          * total size of max desc * buf_len is not greater
2014          * than 65535
2015          */
2016         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2017 #if (MAX_SKB_FRAGS > 16)
2018                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2019 #elif (MAX_SKB_FRAGS > 8)
2020                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2021 #elif (MAX_SKB_FRAGS > 4)
2022                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2023 #else
2024                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2025 #endif
2026         } else {
2027                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2028                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2029                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2030                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2031                 else
2032                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2033         }
2034         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2035 }
2036
2037 /**
2038  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2039  * @adapter: board private structure
2040  *
2041  * Configure the Rx unit of the MAC after a reset.
2042  **/
2043 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2044 {
2045         u64 rdba;
2046         struct ixgbe_hw *hw = &adapter->hw;
2047         struct ixgbe_ring *rx_ring;
2048         struct net_device *netdev = adapter->netdev;
2049         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2050         int i, j;
2051         u32 rdlen, rxctrl, rxcsum;
2052         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2053                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2054                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2055         u32 fctrl, hlreg0;
2056         u32 reta = 0, mrqc = 0;
2057         u32 rdrxctl;
2058         int rx_buf_len;
2059
2060         /* Decide whether to use packet split mode or not */
2061         adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2062
2063         /* Set the RX buffer length according to the mode */
2064         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2065                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2066                 if (hw->mac.type == ixgbe_mac_82599EB) {
2067                         /* PSRTYPE must be initialized in 82599 */
2068                         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2069                                       IXGBE_PSRTYPE_UDPHDR |
2070                                       IXGBE_PSRTYPE_IPV4HDR |
2071                                       IXGBE_PSRTYPE_IPV6HDR |
2072                                       IXGBE_PSRTYPE_L2HDR;
2073                         IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
2074                 }
2075         } else {
2076                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2077                     (netdev->mtu <= ETH_DATA_LEN))
2078                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2079                 else
2080                         rx_buf_len = ALIGN(max_frame, 1024);
2081         }
2082
2083         fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2084         fctrl |= IXGBE_FCTRL_BAM;
2085         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
2086         fctrl |= IXGBE_FCTRL_PMCF;
2087         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2088
2089         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2090         if (adapter->netdev->mtu <= ETH_DATA_LEN)
2091                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2092         else
2093                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2094 #ifdef IXGBE_FCOE
2095         if (netdev->features & NETIF_F_FCOE_MTU)
2096                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2097 #endif
2098         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2099
2100         rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
2101         /* disable receives while setting up the descriptors */
2102         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2103         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2104
2105         /*
2106          * Setup the HW Rx Head and Tail Descriptor Pointers and
2107          * the Base and Length of the Rx Descriptor Ring
2108          */
2109         for (i = 0; i < adapter->num_rx_queues; i++) {
2110                 rx_ring = &adapter->rx_ring[i];
2111                 rdba = rx_ring->dma;
2112                 j = rx_ring->reg_idx;
2113                 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
2114                 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2115                 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2116                 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2117                 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
2118                 rx_ring->head = IXGBE_RDH(j);
2119                 rx_ring->tail = IXGBE_RDT(j);
2120                 rx_ring->rx_buf_len = rx_buf_len;
2121
2122                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2123                         rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
2124                 else
2125                         rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2126
2127 #ifdef IXGBE_FCOE
2128                 if (netdev->features & NETIF_F_FCOE_MTU) {
2129                         struct ixgbe_ring_feature *f;
2130                         f = &adapter->ring_feature[RING_F_FCOE];
2131                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
2132                                 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2133                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2134                                         rx_ring->rx_buf_len =
2135                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2136                         }
2137                 }
2138
2139 #endif /* IXGBE_FCOE */
2140                 ixgbe_configure_srrctl(adapter, rx_ring);
2141         }
2142
2143         if (hw->mac.type == ixgbe_mac_82598EB) {
2144                 /*
2145                  * For VMDq support of different descriptor types or
2146                  * buffer sizes through the use of multiple SRRCTL
2147                  * registers, RDRXCTL.MVMEN must be set to 1
2148                  *
2149                  * also, the manual doesn't mention it clearly but DCA hints
2150                  * will only use queue 0's tags unless this bit is set.  Side
2151                  * effects of setting this bit are only that SRRCTL must be
2152                  * fully programmed [0..15]
2153                  */
2154                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2155                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2156                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2157         }
2158
2159         /* Program MRQC for the distribution of queues */
2160         mrqc = ixgbe_setup_mrqc(adapter);
2161
2162         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2163                 /* Fill out redirection table */
2164                 for (i = 0, j = 0; i < 128; i++, j++) {
2165                         if (j == adapter->ring_feature[RING_F_RSS].indices)
2166                                 j = 0;
2167                         /* reta = 4-byte sliding window of
2168                          * 0x00..(indices-1)(indices-1)00..etc. */
2169                         reta = (reta << 8) | (j * 0x11);
2170                         if ((i & 3) == 3)
2171                                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2172                 }
2173
2174                 /* Fill out hash function seeds */
2175                 for (i = 0; i < 10; i++)
2176                         IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2177
2178                 if (hw->mac.type == ixgbe_mac_82598EB)
2179                         mrqc |= IXGBE_MRQC_RSSEN;
2180                     /* Perform hash on these packet types */
2181                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2182                       | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2183                       | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2184                       | IXGBE_MRQC_RSS_FIELD_IPV6
2185                       | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2186                       | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2187         }
2188         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2189
2190         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2191
2192         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2193             adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2194                 /* Disable indicating checksum in descriptor, enables
2195                  * RSS hash */
2196                 rxcsum |= IXGBE_RXCSUM_PCSD;
2197         }
2198         if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2199                 /* Enable IPv4 payload checksum for UDP fragments
2200                  * if PCSD is not set */
2201                 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2202         }
2203
2204         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2205
2206         if (hw->mac.type == ixgbe_mac_82599EB) {
2207                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2208                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2209                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2210                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2211         }
2212
2213         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2214                 /* Enable 82599 HW-RSC */
2215                 for (i = 0; i < adapter->num_rx_queues; i++)
2216                         ixgbe_configure_rscctl(adapter, i, rx_buf_len);
2217
2218                 /* Disable RSC for ACK packets */
2219                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2220                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2221         }
2222 }
2223
2224 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2225 {
2226         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2227         struct ixgbe_hw *hw = &adapter->hw;
2228
2229         /* add VID to filter table */
2230         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
2231 }
2232
2233 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2234 {
2235         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2236         struct ixgbe_hw *hw = &adapter->hw;
2237
2238         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2239                 ixgbe_irq_disable(adapter);
2240
2241         vlan_group_set_device(adapter->vlgrp, vid, NULL);
2242
2243         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2244                 ixgbe_irq_enable(adapter);
2245
2246         /* remove VID from filter table */
2247         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
2248 }
2249
2250 static void ixgbe_vlan_rx_register(struct net_device *netdev,
2251                                    struct vlan_group *grp)
2252 {
2253         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2254         u32 ctrl;
2255         int i, j;
2256
2257         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2258                 ixgbe_irq_disable(adapter);
2259         adapter->vlgrp = grp;
2260
2261         /*
2262          * For a DCB driver, always enable VLAN tag stripping so we can
2263          * still receive traffic from a DCB-enabled host even if we're
2264          * not in DCB mode.
2265          */
2266         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2267         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2268                 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2269                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2270                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2271         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2272                 ctrl |= IXGBE_VLNCTRL_VFE;
2273                 /* enable VLAN tag insert/strip */
2274                 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2275                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2276                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2277                 for (i = 0; i < adapter->num_rx_queues; i++) {
2278                         j = adapter->rx_ring[i].reg_idx;
2279                         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2280                         ctrl |= IXGBE_RXDCTL_VME;
2281                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2282                 }
2283         }
2284         ixgbe_vlan_rx_add_vid(netdev, 0);
2285
2286         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2287                 ixgbe_irq_enable(adapter);
2288 }
2289
2290 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2291 {
2292         ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2293
2294         if (adapter->vlgrp) {
2295                 u16 vid;
2296                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2297                         if (!vlan_group_get_device(adapter->vlgrp, vid))
2298                                 continue;
2299                         ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2300                 }
2301         }
2302 }
2303
2304 static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2305 {
2306         struct dev_mc_list *mc_ptr;
2307         u8 *addr = *mc_addr_ptr;
2308         *vmdq = 0;
2309
2310         mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2311         if (mc_ptr->next)
2312                 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2313         else
2314                 *mc_addr_ptr = NULL;
2315
2316         return addr;
2317 }
2318
2319 /**
2320  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2321  * @netdev: network interface device structure
2322  *
2323  * The set_rx_method entry point is called whenever the unicast/multicast
2324  * address list or the network interface flags are updated.  This routine is
2325  * responsible for configuring the hardware for proper unicast, multicast and
2326  * promiscuous mode.
2327  **/
2328 static void ixgbe_set_rx_mode(struct net_device *netdev)
2329 {
2330         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2331         struct ixgbe_hw *hw = &adapter->hw;
2332         u32 fctrl, vlnctrl;
2333         u8 *addr_list = NULL;
2334         int addr_count = 0;
2335
2336         /* Check for Promiscuous and All Multicast modes */
2337
2338         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2339         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2340
2341         if (netdev->flags & IFF_PROMISC) {
2342                 hw->addr_ctrl.user_set_promisc = 1;
2343                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2344                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2345         } else {
2346                 if (netdev->flags & IFF_ALLMULTI) {
2347                         fctrl |= IXGBE_FCTRL_MPE;
2348                         fctrl &= ~IXGBE_FCTRL_UPE;
2349                 } else {
2350                         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2351                 }
2352                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2353                 hw->addr_ctrl.user_set_promisc = 0;
2354         }
2355
2356         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2357         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2358
2359         /* reprogram secondary unicast list */
2360         hw->mac.ops.update_uc_addr_list(hw, &netdev->uc.list);
2361
2362         /* reprogram multicast list */
2363         addr_count = netdev->mc_count;
2364         if (addr_count)
2365                 addr_list = netdev->mc_list->dmi_addr;
2366         hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2367                                         ixgbe_addr_list_itr);
2368 }
2369
2370 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2371 {
2372         int q_idx;
2373         struct ixgbe_q_vector *q_vector;
2374         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2375
2376         /* legacy and MSI only use one vector */
2377         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2378                 q_vectors = 1;
2379
2380         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2381                 struct napi_struct *napi;
2382                 q_vector = adapter->q_vector[q_idx];
2383                 napi = &q_vector->napi;
2384                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2385                         if (!q_vector->rxr_count || !q_vector->txr_count) {
2386                                 if (q_vector->txr_count == 1)
2387                                         napi->poll = &ixgbe_clean_txonly;
2388                                 else if (q_vector->rxr_count == 1)
2389                                         napi->poll = &ixgbe_clean_rxonly;
2390                         }
2391                 }
2392
2393                 napi_enable(napi);
2394         }
2395 }
2396
2397 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2398 {
2399         int q_idx;
2400         struct ixgbe_q_vector *q_vector;
2401         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2402
2403         /* legacy and MSI only use one vector */
2404         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2405                 q_vectors = 1;
2406
2407         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2408                 q_vector = adapter->q_vector[q_idx];
2409                 napi_disable(&q_vector->napi);
2410         }
2411 }
2412
2413 #ifdef CONFIG_IXGBE_DCB
2414 /*
2415  * ixgbe_configure_dcb - Configure DCB hardware
2416  * @adapter: ixgbe adapter struct
2417  *
2418  * This is called by the driver on open to configure the DCB hardware.
2419  * This is also called by the gennetlink interface when reconfiguring
2420  * the DCB state.
2421  */
2422 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2423 {
2424         struct ixgbe_hw *hw = &adapter->hw;
2425         u32 txdctl, vlnctrl;
2426         int i, j;
2427
2428         ixgbe_dcb_check_config(&adapter->dcb_cfg);
2429         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2430         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2431
2432         /* reconfigure the hardware */
2433         ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2434
2435         for (i = 0; i < adapter->num_tx_queues; i++) {
2436                 j = adapter->tx_ring[i].reg_idx;
2437                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2438                 /* PThresh workaround for Tx hang with DFP enabled. */
2439                 txdctl |= 32;
2440                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2441         }
2442         /* Enable VLAN tag insert/strip */
2443         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2444         if (hw->mac.type == ixgbe_mac_82598EB) {
2445                 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2446                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2447                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2448         } else if (hw->mac.type == ixgbe_mac_82599EB) {
2449                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2450                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2451                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2452                 for (i = 0; i < adapter->num_rx_queues; i++) {
2453                         j = adapter->rx_ring[i].reg_idx;
2454                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2455                         vlnctrl |= IXGBE_RXDCTL_VME;
2456                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2457                 }
2458         }
2459         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2460 }
2461
2462 #endif
2463 static void ixgbe_configure(struct ixgbe_adapter *adapter)
2464 {
2465         struct net_device *netdev = adapter->netdev;
2466         struct ixgbe_hw *hw = &adapter->hw;
2467         int i;
2468
2469         ixgbe_set_rx_mode(netdev);
2470
2471         ixgbe_restore_vlan(adapter);
2472 #ifdef CONFIG_IXGBE_DCB
2473         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2474                 netif_set_gso_max_size(netdev, 32768);
2475                 ixgbe_configure_dcb(adapter);
2476         } else {
2477                 netif_set_gso_max_size(netdev, 65536);
2478         }
2479 #else
2480         netif_set_gso_max_size(netdev, 65536);
2481 #endif
2482
2483 #ifdef IXGBE_FCOE
2484         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2485                 ixgbe_configure_fcoe(adapter);
2486
2487 #endif /* IXGBE_FCOE */
2488         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2489                 for (i = 0; i < adapter->num_tx_queues; i++)
2490                         adapter->tx_ring[i].atr_sample_rate =
2491                                                        adapter->atr_sample_rate;
2492                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2493         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2494                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2495         }
2496
2497         ixgbe_configure_tx(adapter);
2498         ixgbe_configure_rx(adapter);
2499         for (i = 0; i < adapter->num_rx_queues; i++)
2500                 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
2501                                        (adapter->rx_ring[i].count - 1));
2502 }
2503
2504 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2505 {
2506         switch (hw->phy.type) {
2507         case ixgbe_phy_sfp_avago:
2508         case ixgbe_phy_sfp_ftl:
2509         case ixgbe_phy_sfp_intel:
2510         case ixgbe_phy_sfp_unknown:
2511         case ixgbe_phy_tw_tyco:
2512         case ixgbe_phy_tw_unknown:
2513                 return true;
2514         default:
2515                 return false;
2516         }
2517 }
2518
2519 /**
2520  * ixgbe_sfp_link_config - set up SFP+ link
2521  * @adapter: pointer to private adapter struct
2522  **/
2523 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2524 {
2525         struct ixgbe_hw *hw = &adapter->hw;
2526
2527                 if (hw->phy.multispeed_fiber) {
2528                         /*
2529                          * In multispeed fiber setups, the device may not have
2530                          * had a physical connection when the driver loaded.
2531                          * If that's the case, the initial link configuration
2532                          * couldn't get the MAC into 10G or 1G mode, so we'll
2533                          * never have a link status change interrupt fire.
2534                          * We need to try and force an autonegotiation
2535                          * session, then bring up link.
2536                          */
2537                         hw->mac.ops.setup_sfp(hw);
2538                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2539                                 schedule_work(&adapter->multispeed_fiber_task);
2540                 } else {
2541                         /*
2542                          * Direct Attach Cu and non-multispeed fiber modules
2543                          * still need to be configured properly prior to
2544                          * attempting link.
2545                          */
2546                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2547                                 schedule_work(&adapter->sfp_config_module_task);
2548                 }
2549 }
2550
2551 /**
2552  * ixgbe_non_sfp_link_config - set up non-SFP+ link
2553  * @hw: pointer to private hardware struct
2554  *
2555  * Returns 0 on success, negative on failure
2556  **/
2557 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
2558 {
2559         u32 autoneg;
2560         bool negotiation, link_up = false;
2561         u32 ret = IXGBE_ERR_LINK_SETUP;
2562
2563         if (hw->mac.ops.check_link)
2564                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2565
2566         if (ret)
2567                 goto link_cfg_out;
2568
2569         if (hw->mac.ops.get_link_capabilities)
2570                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
2571         if (ret)
2572                 goto link_cfg_out;
2573
2574         if (hw->mac.ops.setup_link)
2575                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
2576 link_cfg_out:
2577         return ret;
2578 }
2579
2580 #define IXGBE_MAX_RX_DESC_POLL 10
2581 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2582                                               int rxr)
2583 {
2584         int j = adapter->rx_ring[rxr].reg_idx;
2585         int k;
2586
2587         for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2588                 if (IXGBE_READ_REG(&adapter->hw,
2589                                    IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2590                         break;
2591                 else
2592                         msleep(1);
2593         }
2594         if (k >= IXGBE_MAX_RX_DESC_POLL) {
2595                 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2596                         "not set within the polling period\n", rxr);
2597         }
2598         ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2599                               (adapter->rx_ring[rxr].count - 1));
2600 }
2601
2602 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2603 {
2604         struct net_device *netdev = adapter->netdev;
2605         struct ixgbe_hw *hw = &adapter->hw;
2606         int i, j = 0;
2607         int num_rx_rings = adapter->num_rx_queues;
2608         int err;
2609         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2610         u32 txdctl, rxdctl, mhadd;
2611         u32 dmatxctl;
2612         u32 gpie;
2613
2614         ixgbe_get_hw_control(adapter);
2615
2616         if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2617             (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
2618                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2619                         gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
2620                                 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
2621                 } else {
2622                         /* MSI only */
2623                         gpie = 0;
2624                 }
2625                 /* XXX: to interrupt immediately for EICS writes, enable this */
2626                 /* gpie |= IXGBE_GPIE_EIMEN; */
2627                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2628         }
2629
2630         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2631                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2632                  * specifically only auto mask tx and rx interrupts */
2633                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2634         }
2635
2636         /* Enable fan failure interrupt if media type is copper */
2637         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2638                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2639                 gpie |= IXGBE_SDP1_GPIEN;
2640                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2641         }
2642
2643         if (hw->mac.type == ixgbe_mac_82599EB) {
2644                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2645                 gpie |= IXGBE_SDP1_GPIEN;
2646                 gpie |= IXGBE_SDP2_GPIEN;
2647                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2648         }
2649
2650 #ifdef IXGBE_FCOE
2651         /* adjust max frame to be able to do baby jumbo for FCoE */
2652         if ((netdev->features & NETIF_F_FCOE_MTU) &&
2653             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2654                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2655
2656 #endif /* IXGBE_FCOE */
2657         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2658         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2659                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2660                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2661
2662                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2663         }
2664
2665         for (i = 0; i < adapter->num_tx_queues; i++) {
2666                 j = adapter->tx_ring[i].reg_idx;
2667                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2668                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2669                 txdctl |= (8 << 16);
2670                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2671         }
2672
2673         if (hw->mac.type == ixgbe_mac_82599EB) {
2674                 /* DMATXCTL.EN must be set after all Tx queue config is done */
2675                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2676                 dmatxctl |= IXGBE_DMATXCTL_TE;
2677                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2678         }
2679         for (i = 0; i < adapter->num_tx_queues; i++) {
2680                 j = adapter->tx_ring[i].reg_idx;
2681                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2682                 txdctl |= IXGBE_TXDCTL_ENABLE;
2683                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2684         }
2685
2686         for (i = 0; i < num_rx_rings; i++) {
2687                 j = adapter->rx_ring[i].reg_idx;
2688                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2689                 /* enable PTHRESH=32 descriptors (half the internal cache)
2690                  * and HTHRESH=0 descriptors (to minimize latency on fetch),
2691                  * this also removes a pesky rx_no_buffer_count increment */
2692                 rxdctl |= 0x0020;
2693                 rxdctl |= IXGBE_RXDCTL_ENABLE;
2694                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
2695                 if (hw->mac.type == ixgbe_mac_82599EB)
2696                         ixgbe_rx_desc_queue_enable(adapter, i);
2697         }
2698         /* enable all receives */
2699         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2700         if (hw->mac.type == ixgbe_mac_82598EB)
2701                 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2702         else
2703                 rxdctl |= IXGBE_RXCTRL_RXEN;
2704         hw->mac.ops.enable_rx_dma(hw, rxdctl);
2705
2706         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2707                 ixgbe_configure_msix(adapter);
2708         else
2709                 ixgbe_configure_msi_and_legacy(adapter);
2710
2711         clear_bit(__IXGBE_DOWN, &adapter->state);
2712         ixgbe_napi_enable_all(adapter);
2713
2714         /* clear any pending interrupts, may auto mask */
2715         IXGBE_READ_REG(hw, IXGBE_EICR);
2716
2717         ixgbe_irq_enable(adapter);
2718
2719         /*
2720          * If this adapter has a fan, check to see if we had a failure
2721          * before we enabled the interrupt.
2722          */
2723         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2724                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2725                 if (esdp & IXGBE_ESDP_SDP1)
2726                         DPRINTK(DRV, CRIT,
2727                                 "Fan has stopped, replace the adapter\n");
2728         }
2729
2730         /*
2731          * For hot-pluggable SFP+ devices, a new SFP+ module may have
2732          * arrived before interrupts were enabled but after probe.  Such
2733          * devices wouldn't have their type identified yet. We need to
2734          * kick off the SFP+ module setup first, then try to bring up link.
2735          * If we're not hot-pluggable SFP+, we just need to configure link
2736          * and bring it up.
2737          */
2738         if (hw->phy.type == ixgbe_phy_unknown) {
2739                 err = hw->phy.ops.identify(hw);
2740                 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2741                         /*
2742                          * Take the device down and schedule the sfp tasklet
2743                          * which will unregister_netdev and log it.
2744                          */
2745                         ixgbe_down(adapter);
2746                         schedule_work(&adapter->sfp_config_module_task);
2747                         return err;
2748                 }
2749         }
2750
2751         if (ixgbe_is_sfp(hw)) {
2752                 ixgbe_sfp_link_config(adapter);
2753         } else {
2754                 err = ixgbe_non_sfp_link_config(hw);
2755                 if (err)
2756                         DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2757         }
2758
2759         for (i = 0; i < adapter->num_tx_queues; i++)
2760                 set_bit(__IXGBE_FDIR_INIT_DONE,
2761                         &(adapter->tx_ring[i].reinit_state));
2762
2763         /* enable transmits */
2764         netif_tx_start_all_queues(netdev);
2765
2766         /* bring the link up in the watchdog, this could race with our first
2767          * link up interrupt but shouldn't be a problem */
2768         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2769         adapter->link_check_timeout = jiffies;
2770         mod_timer(&adapter->watchdog_timer, jiffies);
2771         return 0;
2772 }
2773
2774 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2775 {
2776         WARN_ON(in_interrupt());
2777         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2778                 msleep(1);
2779         ixgbe_down(adapter);
2780         ixgbe_up(adapter);
2781         clear_bit(__IXGBE_RESETTING, &adapter->state);
2782 }
2783
2784 int ixgbe_up(struct ixgbe_adapter *adapter)
2785 {
2786         /* hardware has been reset, we need to reload some things */
2787         ixgbe_configure(adapter);
2788
2789         return ixgbe_up_complete(adapter);
2790 }
2791
2792 void ixgbe_reset(struct ixgbe_adapter *adapter)
2793 {
2794         struct ixgbe_hw *hw = &adapter->hw;
2795         int err;
2796
2797         err = hw->mac.ops.init_hw(hw);
2798         switch (err) {
2799         case 0:
2800         case IXGBE_ERR_SFP_NOT_PRESENT:
2801                 break;
2802         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
2803                 dev_err(&adapter->pdev->dev, "master disable timed out\n");
2804                 break;
2805         case IXGBE_ERR_EEPROM_VERSION:
2806                 /* We are running on a pre-production device, log a warning */
2807                 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
2808                          "adapter/LOM.  Please be aware there may be issues "
2809                          "associated with your hardware.  If you are "
2810                          "experiencing problems please contact your Intel or "
2811                          "hardware representative who provided you with this "
2812                          "hardware.\n");
2813                 break;
2814         default:
2815                 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
2816         }
2817
2818         /* reprogram the RAR[0] in case user changed it. */
2819         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2820 }
2821
2822 /**
2823  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2824  * @adapter: board private structure
2825  * @rx_ring: ring to free buffers from
2826  **/
2827 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
2828                                 struct ixgbe_ring *rx_ring)
2829 {
2830         struct pci_dev *pdev = adapter->pdev;
2831         unsigned long size;
2832         unsigned int i;
2833
2834         /* Free all the Rx ring sk_buffs */
2835
2836         for (i = 0; i < rx_ring->count; i++) {
2837                 struct ixgbe_rx_buffer *rx_buffer_info;
2838
2839                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2840                 if (rx_buffer_info->dma) {
2841                         pci_unmap_single(pdev, rx_buffer_info->dma,
2842                                          rx_ring->rx_buf_len,
2843                                          PCI_DMA_FROMDEVICE);
2844                         rx_buffer_info->dma = 0;
2845                 }
2846                 if (rx_buffer_info->skb) {
2847                         struct sk_buff *skb = rx_buffer_info->skb;
2848                         rx_buffer_info->skb = NULL;
2849                         do {
2850                                 struct sk_buff *this = skb;
2851                                 skb = skb->prev;
2852                                 dev_kfree_skb(this);
2853                         } while (skb);
2854                 }
2855                 if (!rx_buffer_info->page)
2856                         continue;
2857                 if (rx_buffer_info->page_dma) {
2858                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
2859                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
2860                         rx_buffer_info->page_dma = 0;
2861                 }
2862                 put_page(rx_buffer_info->page);
2863                 rx_buffer_info->page = NULL;
2864                 rx_buffer_info->page_offset = 0;
2865         }
2866
2867         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2868         memset(rx_ring->rx_buffer_info, 0, size);
2869
2870         /* Zero out the descriptor ring */
2871         memset(rx_ring->desc, 0, rx_ring->size);
2872
2873         rx_ring->next_to_clean = 0;
2874         rx_ring->next_to_use = 0;
2875
2876         if (rx_ring->head)
2877                 writel(0, adapter->hw.hw_addr + rx_ring->head);
2878         if (rx_ring->tail)
2879                 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2880 }
2881
2882 /**
2883  * ixgbe_clean_tx_ring - Free Tx Buffers
2884  * @adapter: board private structure
2885  * @tx_ring: ring to be cleaned
2886  **/
2887 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
2888                                 struct ixgbe_ring *tx_ring)
2889 {
2890         struct ixgbe_tx_buffer *tx_buffer_info;
2891         unsigned long size;
2892         unsigned int i;
2893
2894         /* Free all the Tx ring sk_buffs */
2895
2896         for (i = 0; i < tx_ring->count; i++) {
2897                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2898                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2899         }
2900
2901         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2902         memset(tx_ring->tx_buffer_info, 0, size);
2903
2904         /* Zero out the descriptor ring */
2905         memset(tx_ring->desc, 0, tx_ring->size);
2906
2907         tx_ring->next_to_use = 0;
2908         tx_ring->next_to_clean = 0;
2909
2910         if (tx_ring->head)
2911                 writel(0, adapter->hw.hw_addr + tx_ring->head);
2912         if (tx_ring->tail)
2913                 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2914 }
2915
2916 /**
2917  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
2918  * @adapter: board private structure
2919  **/
2920 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
2921 {
2922         int i;
2923
2924         for (i = 0; i < adapter->num_rx_queues; i++)
2925                 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
2926 }
2927
2928 /**
2929  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
2930  * @adapter: board private structure
2931  **/
2932 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
2933 {
2934         int i;
2935
2936         for (i = 0; i < adapter->num_tx_queues; i++)
2937                 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
2938 }
2939
2940 void ixgbe_down(struct ixgbe_adapter *adapter)
2941 {
2942         struct net_device *netdev = adapter->netdev;
2943         struct ixgbe_hw *hw = &adapter->hw;
2944         u32 rxctrl;
2945         u32 txdctl;
2946         int i, j;
2947
2948         /* signal that we are down to the interrupt handler */
2949         set_bit(__IXGBE_DOWN, &adapter->state);
2950
2951         /* disable receives */
2952         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2953         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2954
2955         netif_tx_disable(netdev);
2956
2957         IXGBE_WRITE_FLUSH(hw);
2958         msleep(10);
2959
2960         netif_tx_stop_all_queues(netdev);
2961
2962         ixgbe_irq_disable(adapter);
2963
2964         ixgbe_napi_disable_all(adapter);
2965
2966         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
2967         del_timer_sync(&adapter->sfp_timer);
2968         del_timer_sync(&adapter->watchdog_timer);
2969         cancel_work_sync(&adapter->watchdog_task);
2970
2971         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2972             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2973                 cancel_work_sync(&adapter->fdir_reinit_task);
2974
2975         /* disable transmits in the hardware now that interrupts are off */
2976         for (i = 0; i < adapter->num_tx_queues; i++) {
2977                 j = adapter->tx_ring[i].reg_idx;
2978                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2979                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2980                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2981         }
2982         /* Disable the Tx DMA engine on 82599 */
2983         if (hw->mac.type == ixgbe_mac_82599EB)
2984                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
2985                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
2986                                  ~IXGBE_DMATXCTL_TE));
2987
2988         netif_carrier_off(netdev);
2989
2990         if (!pci_channel_offline(adapter->pdev))
2991                 ixgbe_reset(adapter);
2992         ixgbe_clean_all_tx_rings(adapter);
2993         ixgbe_clean_all_rx_rings(adapter);
2994
2995 #ifdef CONFIG_IXGBE_DCA
2996         /* since we reset the hardware DCA settings were cleared */
2997         ixgbe_setup_dca(adapter);
2998 #endif
2999 }
3000
3001 /**
3002  * ixgbe_poll - NAPI Rx polling callback
3003  * @napi: structure for representing this polling device
3004  * @budget: how many packets driver is allowed to clean
3005  *
3006  * This function is used for legacy and MSI, NAPI mode
3007  **/
3008 static int ixgbe_poll(struct napi_struct *napi, int budget)
3009 {
3010         struct ixgbe_q_vector *q_vector =
3011                                 container_of(napi, struct ixgbe_q_vector, napi);
3012         struct ixgbe_adapter *adapter = q_vector->adapter;
3013         int tx_clean_complete, work_done = 0;
3014
3015 #ifdef CONFIG_IXGBE_DCA
3016         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3017                 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
3018                 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
3019         }
3020 #endif
3021
3022         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring);
3023         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
3024
3025         if (!tx_clean_complete)
3026                 work_done = budget;
3027
3028         /* If budget not fully consumed, exit the polling mode */
3029         if (work_done < budget) {
3030                 napi_complete(napi);
3031                 if (adapter->rx_itr_setting & 1)
3032                         ixgbe_set_itr(adapter);
3033                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3034                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3035         }
3036         return work_done;
3037 }
3038
3039 /**
3040  * ixgbe_tx_timeout - Respond to a Tx Hang
3041  * @netdev: network interface device structure
3042  **/
3043 static void ixgbe_tx_timeout(struct net_device *netdev)
3044 {
3045         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3046
3047         /* Do the reset outside of interrupt context */
3048         schedule_work(&adapter->reset_task);
3049 }
3050
3051 static void ixgbe_reset_task(struct work_struct *work)
3052 {
3053         struct ixgbe_adapter *adapter;
3054         adapter = container_of(work, struct ixgbe_adapter, reset_task);
3055
3056         /* If we're already down or resetting, just bail */
3057         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3058             test_bit(__IXGBE_RESETTING, &adapter->state))
3059                 return;
3060
3061         adapter->tx_timeout_count++;
3062
3063         ixgbe_reinit_locked(adapter);
3064 }
3065
3066 #ifdef CONFIG_IXGBE_DCB
3067 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3068 {
3069         bool ret = false;
3070         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3071
3072         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3073                 return ret;
3074
3075         f->mask = 0x7 << 3;
3076         adapter->num_rx_queues = f->indices;
3077         adapter->num_tx_queues = f->indices;
3078         ret = true;
3079
3080         return ret;
3081 }
3082 #endif
3083
3084 /**
3085  * ixgbe_set_rss_queues: Allocate queues for RSS
3086  * @adapter: board private structure to initialize
3087  *
3088  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
3089  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3090  *
3091  **/
3092 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3093 {
3094         bool ret = false;
3095         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3096
3097         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3098                 f->mask = 0xF;
3099                 adapter->num_rx_queues = f->indices;
3100                 adapter->num_tx_queues = f->indices;
3101                 ret = true;
3102         } else {
3103                 ret = false;
3104         }
3105
3106         return ret;
3107 }
3108
3109 /**
3110  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3111  * @adapter: board private structure to initialize
3112  *
3113  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3114  * to the original CPU that initiated the Tx session.  This runs in addition
3115  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3116  * Rx load across CPUs using RSS.
3117  *
3118  **/
3119 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3120 {
3121         bool ret = false;
3122         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3123
3124         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3125         f_fdir->mask = 0;
3126
3127         /* Flow Director must have RSS enabled */
3128         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3129             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3130              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3131                 adapter->num_tx_queues = f_fdir->indices;
3132                 adapter->num_rx_queues = f_fdir->indices;
3133                 ret = true;
3134         } else {
3135                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3136                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3137         }
3138         return ret;
3139 }
3140
3141 #ifdef IXGBE_FCOE
3142 /**
3143  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3144  * @adapter: board private structure to initialize
3145  *
3146  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3147  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3148  * rx queues out of the max number of rx queues, instead, it is used as the
3149  * index of the first rx queue used by FCoE.
3150  *
3151  **/
3152 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3153 {
3154         bool ret = false;
3155         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3156
3157         f->indices = min((int)num_online_cpus(), f->indices);
3158         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3159                 adapter->num_rx_queues = 1;
3160                 adapter->num_tx_queues = 1;
3161 #ifdef CONFIG_IXGBE_DCB
3162                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3163                         DPRINTK(PROBE, INFO, "FCoE enabled with DCB \n");
3164                         ixgbe_set_dcb_queues(adapter);
3165                 }
3166 #endif
3167                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3168                         DPRINTK(PROBE, INFO, "FCoE enabled with RSS \n");
3169                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3170                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3171                                 ixgbe_set_fdir_queues(adapter);
3172                         else
3173                                 ixgbe_set_rss_queues(adapter);
3174                 }
3175                 /* adding FCoE rx rings to the end */
3176                 f->mask = adapter->num_rx_queues;
3177                 adapter->num_rx_queues += f->indices;
3178                 adapter->num_tx_queues += f->indices;
3179
3180                 ret = true;
3181         }
3182
3183         return ret;
3184 }
3185
3186 #endif /* IXGBE_FCOE */
3187 /*
3188  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3189  * @adapter: board private structure to initialize
3190  *
3191  * This is the top level queue allocation routine.  The order here is very
3192  * important, starting with the "most" number of features turned on at once,
3193  * and ending with the smallest set of features.  This way large combinations
3194  * can be allocated if they're turned on, and smaller combinations are the
3195  * fallthrough conditions.
3196  *
3197  **/
3198 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3199 {
3200 #ifdef IXGBE_FCOE
3201         if (ixgbe_set_fcoe_queues(adapter))
3202                 goto done;
3203
3204 #endif /* IXGBE_FCOE */
3205 #ifdef CONFIG_IXGBE_DCB
3206         if (ixgbe_set_dcb_queues(adapter))
3207                 goto done;
3208
3209 #endif
3210         if (ixgbe_set_fdir_queues(adapter))
3211                 goto done;
3212
3213         if (ixgbe_set_rss_queues(adapter))
3214                 goto done;
3215
3216         /* fallback to base case */
3217         adapter->num_rx_queues = 1;
3218         adapter->num_tx_queues = 1;
3219
3220 done:
3221         /* Notify the stack of the (possibly) reduced Tx Queue count. */
3222         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
3223 }
3224
3225 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
3226                                        int vectors)
3227 {
3228         int err, vector_threshold;
3229
3230         /* We'll want at least 3 (vector_threshold):
3231          * 1) TxQ[0] Cleanup
3232          * 2) RxQ[0] Cleanup
3233          * 3) Other (Link Status Change, etc.)
3234          * 4) TCP Timer (optional)
3235          */
3236         vector_threshold = MIN_MSIX_COUNT;
3237
3238         /* The more we get, the more we will assign to Tx/Rx Cleanup
3239          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3240          * Right now, we simply care about how many we'll get; we'll
3241          * set them up later while requesting irq's.
3242          */
3243         while (vectors >= vector_threshold) {
3244                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
3245                                       vectors);
3246                 if (!err) /* Success in acquiring all requested vectors. */
3247                         break;
3248                 else if (err < 0)
3249                         vectors = 0; /* Nasty failure, quit now */
3250                 else /* err == number of vectors we should try again with */
3251                         vectors = err;
3252         }
3253
3254         if (vectors < vector_threshold) {
3255                 /* Can't allocate enough MSI-X interrupts?  Oh well.
3256                  * This just means we'll go with either a single MSI
3257                  * vector or fall back to legacy interrupts.
3258                  */
3259                 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3260                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3261                 kfree(adapter->msix_entries);
3262                 adapter->msix_entries = NULL;
3263         } else {
3264                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
3265                 /*
3266                  * Adjust for only the vectors we'll use, which is minimum
3267                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3268                  * vectors we were allocated.
3269                  */
3270                 adapter->num_msix_vectors = min(vectors,
3271                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
3272         }
3273 }
3274
3275 /**
3276  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
3277  * @adapter: board private structure to initialize
3278  *
3279  * Cache the descriptor ring offsets for RSS to the assigned rings.
3280  *
3281  **/
3282 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
3283 {
3284         int i;
3285         bool ret = false;
3286
3287         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3288                 for (i = 0; i < adapter->num_rx_queues; i++)
3289                         adapter->rx_ring[i].reg_idx = i;
3290                 for (i = 0; i < adapter->num_tx_queues; i++)
3291                         adapter->tx_ring[i].reg_idx = i;
3292                 ret = true;
3293         } else {
3294                 ret = false;
3295         }
3296
3297         return ret;
3298 }
3299
3300 #ifdef CONFIG_IXGBE_DCB
3301 /**
3302  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3303  * @adapter: board private structure to initialize
3304  *
3305  * Cache the descriptor ring offsets for DCB to the assigned rings.
3306  *
3307  **/
3308 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3309 {
3310         int i;
3311         bool ret = false;
3312         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3313
3314         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3315                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3316                         /* the number of queues is assumed to be symmetric */
3317                         for (i = 0; i < dcb_i; i++) {
3318                                 adapter->rx_ring[i].reg_idx = i << 3;
3319                                 adapter->tx_ring[i].reg_idx = i << 2;
3320                         }
3321                         ret = true;
3322                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
3323                         if (dcb_i == 8) {
3324                                 /*
3325                                  * Tx TC0 starts at: descriptor queue 0
3326                                  * Tx TC1 starts at: descriptor queue 32
3327                                  * Tx TC2 starts at: descriptor queue 64
3328                                  * Tx TC3 starts at: descriptor queue 80
3329                                  * Tx TC4 starts at: descriptor queue 96
3330                                  * Tx TC5 starts at: descriptor queue 104
3331                                  * Tx TC6 starts at: descriptor queue 112
3332                                  * Tx TC7 starts at: descriptor queue 120
3333                                  *
3334                                  * Rx TC0-TC7 are offset by 16 queues each
3335                                  */
3336                                 for (i = 0; i < 3; i++) {
3337                                         adapter->tx_ring[i].reg_idx = i << 5;
3338                                         adapter->rx_ring[i].reg_idx = i << 4;
3339                                 }
3340                                 for ( ; i < 5; i++) {
3341                                         adapter->tx_ring[i].reg_idx =
3342                                                                  ((i + 2) << 4);
3343                                         adapter->rx_ring[i].reg_idx = i << 4;
3344                                 }
3345                                 for ( ; i < dcb_i; i++) {
3346                                         adapter->tx_ring[i].reg_idx =
3347                                                                  ((i + 8) << 3);
3348                                         adapter->rx_ring[i].reg_idx = i << 4;
3349                                 }
3350
3351                                 ret = true;
3352                         } else if (dcb_i == 4) {
3353                                 /*
3354                                  * Tx TC0 starts at: descriptor queue 0
3355                                  * Tx TC1 starts at: descriptor queue 64
3356                                  * Tx TC2 starts at: descriptor queue 96
3357                                  * Tx TC3 starts at: descriptor queue 112
3358                                  *
3359                                  * Rx TC0-TC3 are offset by 32 queues each
3360                                  */
3361                                 adapter->tx_ring[0].reg_idx = 0;
3362                                 adapter->tx_ring[1].reg_idx = 64;
3363                                 adapter->tx_ring[2].reg_idx = 96;
3364                                 adapter->tx_ring[3].reg_idx = 112;
3365                                 for (i = 0 ; i < dcb_i; i++)
3366                                         adapter->rx_ring[i].reg_idx = i << 5;
3367
3368                                 ret = true;
3369                         } else {
3370                                 ret = false;
3371                         }
3372                 } else {
3373                         ret = false;
3374                 }
3375         } else {
3376                 ret = false;
3377         }
3378
3379         return ret;
3380 }
3381 #endif
3382
3383 /**
3384  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3385  * @adapter: board private structure to initialize
3386  *
3387  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3388  *
3389  **/
3390 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
3391 {
3392         int i;
3393         bool ret = false;
3394
3395         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3396             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3397              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
3398                 for (i = 0; i < adapter->num_rx_queues; i++)
3399                         adapter->rx_ring[i].reg_idx = i;
3400                 for (i = 0; i < adapter->num_tx_queues; i++)
3401                         adapter->tx_ring[i].reg_idx = i;
3402                 ret = true;
3403         }
3404
3405         return ret;
3406 }
3407
3408 #ifdef IXGBE_FCOE
3409 /**
3410  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3411  * @adapter: board private structure to initialize
3412  *
3413  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3414  *
3415  */
3416 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3417 {
3418         int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
3419         bool ret = false;
3420         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3421
3422         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3423 #ifdef CONFIG_IXGBE_DCB
3424                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3425                         struct ixgbe_fcoe *fcoe = &adapter->fcoe;
3426
3427                         ixgbe_cache_ring_dcb(adapter);
3428                         /* find out queues in TC for FCoE */
3429                         fcoe_rx_i = adapter->rx_ring[fcoe->tc].reg_idx + 1;
3430                         fcoe_tx_i = adapter->tx_ring[fcoe->tc].reg_idx + 1;
3431                         /*
3432                          * In 82599, the number of Tx queues for each traffic
3433                          * class for both 8-TC and 4-TC modes are:
3434                          * TCs  : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
3435                          * 8 TCs:  32  32  16  16   8   8   8   8
3436                          * 4 TCs:  64  64  32  32
3437                          * We have max 8 queues for FCoE, where 8 the is
3438                          * FCoE redirection table size. If TC for FCoE is
3439                          * less than or equal to TC3, we have enough queues
3440                          * to add max of 8 queues for FCoE, so we start FCoE
3441                          * tx descriptor from the next one, i.e., reg_idx + 1.
3442                          * If TC for FCoE is above TC3, implying 8 TC mode,
3443                          * and we need 8 for FCoE, we have to take all queues
3444                          * in that traffic class for FCoE.
3445                          */
3446                         if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
3447                                 fcoe_tx_i--;
3448                 }
3449 #endif /* CONFIG_IXGBE_DCB */
3450                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3451                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3452                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3453                                 ixgbe_cache_ring_fdir(adapter);
3454                         else
3455                                 ixgbe_cache_ring_rss(adapter);
3456
3457                         fcoe_rx_i = f->mask;
3458                         fcoe_tx_i = f->mask;
3459                 }
3460                 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
3461                         adapter->rx_ring[f->mask + i].reg_idx = fcoe_rx_i;
3462                         adapter->tx_ring[f->mask + i].reg_idx = fcoe_tx_i;
3463                 }
3464                 ret = true;
3465         }
3466         return ret;
3467 }
3468
3469 #endif /* IXGBE_FCOE */
3470 /**
3471  * ixgbe_cache_ring_register - Descriptor ring to register mapping
3472  * @adapter: board private structure to initialize
3473  *
3474  * Once we know the feature-set enabled for the device, we'll cache
3475  * the register offset the descriptor ring is assigned to.
3476  *
3477  * Note, the order the various feature calls is important.  It must start with
3478  * the "most" features enabled at the same time, then trickle down to the
3479  * least amount of features turned on at once.
3480  **/
3481 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3482 {
3483         /* start with default case */
3484         adapter->rx_ring[0].reg_idx = 0;
3485         adapter->tx_ring[0].reg_idx = 0;
3486
3487 #ifdef IXGBE_FCOE
3488         if (ixgbe_cache_ring_fcoe(adapter))
3489                 return;
3490
3491 #endif /* IXGBE_FCOE */
3492 #ifdef CONFIG_IXGBE_DCB
3493         if (ixgbe_cache_ring_dcb(adapter))
3494                 return;
3495
3496 #endif
3497         if (ixgbe_cache_ring_fdir(adapter))
3498                 return;
3499
3500         if (ixgbe_cache_ring_rss(adapter))
3501                 return;
3502 }
3503
3504 /**
3505  * ixgbe_alloc_queues - Allocate memory for all rings
3506  * @adapter: board private structure to initialize
3507  *
3508  * We allocate one ring per queue at run-time since we don't know the
3509  * number of queues at compile-time.  The polling_netdev array is
3510  * intended for Multiqueue, but should work fine with a single queue.
3511  **/
3512 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
3513 {
3514         int i;
3515
3516         adapter->tx_ring = kcalloc(adapter->num_tx_queues,
3517                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
3518         if (!adapter->tx_ring)
3519                 goto err_tx_ring_allocation;
3520
3521         adapter->rx_ring = kcalloc(adapter->num_rx_queues,
3522                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
3523         if (!adapter->rx_ring)
3524                 goto err_rx_ring_allocation;
3525
3526         for (i = 0; i < adapter->num_tx_queues; i++) {
3527                 adapter->tx_ring[i].count = adapter->tx_ring_count;
3528                 adapter->tx_ring[i].queue_index = i;
3529         }
3530
3531         for (i = 0; i < adapter->num_rx_queues; i++) {
3532                 adapter->rx_ring[i].count = adapter->rx_ring_count;
3533                 adapter->rx_ring[i].queue_index = i;
3534         }
3535
3536         ixgbe_cache_ring_register(adapter);
3537
3538         return 0;
3539
3540 err_rx_ring_allocation:
3541         kfree(adapter->tx_ring);
3542 err_tx_ring_allocation:
3543         return -ENOMEM;
3544 }
3545
3546 /**
3547  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3548  * @adapter: board private structure to initialize
3549  *
3550  * Attempt to configure the interrupts using the best available
3551  * capabilities of the hardware and the kernel.
3552  **/
3553 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
3554 {
3555         struct ixgbe_hw *hw = &adapter->hw;
3556         int err = 0;
3557         int vector, v_budget;
3558
3559         /*
3560          * It's easy to be greedy for MSI-X vectors, but it really
3561          * doesn't do us much good if we have a lot more vectors
3562          * than CPU's.  So let's be conservative and only ask for
3563          * (roughly) twice the number of vectors as there are CPU's.
3564          */
3565         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
3566                        (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
3567
3568         /*
3569          * At the same time, hardware can only support a maximum of
3570          * hw.mac->max_msix_vectors vectors.  With features
3571          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3572          * descriptor queues supported by our device.  Thus, we cap it off in
3573          * those rare cases where the cpu count also exceeds our vector limit.
3574          */
3575         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
3576
3577         /* A failure in MSI-X entry allocation isn't fatal, but it does
3578          * mean we disable MSI-X capabilities of the adapter. */
3579         adapter->msix_entries = kcalloc(v_budget,
3580                                         sizeof(struct msix_entry), GFP_KERNEL);
3581         if (adapter->msix_entries) {
3582                 for (vector = 0; vector < v_budget; vector++)
3583                         adapter->msix_entries[vector].entry = vector;
3584
3585                 ixgbe_acquire_msix_vectors(adapter, v_budget);
3586
3587                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3588                         goto out;
3589         }
3590
3591         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3592         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
3593         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3594         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3595         adapter->atr_sample_rate = 0;
3596         ixgbe_set_num_queues(adapter);
3597
3598         err = pci_enable_msi(adapter->pdev);
3599         if (!err) {
3600                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3601         } else {
3602                 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
3603                         "falling back to legacy.  Error: %d\n", err);
3604                 /* reset err */
3605                 err = 0;
3606         }
3607
3608 out:
3609         return err;
3610 }
3611
3612 /**
3613  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3614  * @adapter: board private structure to initialize
3615  *
3616  * We allocate one q_vector per queue interrupt.  If allocation fails we
3617  * return -ENOMEM.
3618  **/
3619 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3620 {
3621         int q_idx, num_q_vectors;
3622         struct ixgbe_q_vector *q_vector;
3623         int napi_vectors;
3624         int (*poll)(struct napi_struct *, int);
3625
3626         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3627                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3628                 napi_vectors = adapter->num_rx_queues;
3629                 poll = &ixgbe_clean_rxtx_many;
3630         } else {
3631                 num_q_vectors = 1;
3632                 napi_vectors = 1;
3633                 poll = &ixgbe_poll;
3634         }
3635
3636         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3637                 q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL);
3638                 if (!q_vector)
3639                         goto err_out;
3640                 q_vector->adapter = adapter;
3641                 if (q_vector->txr_count && !q_vector->rxr_count)
3642                         q_vector->eitr = adapter->tx_eitr_param;
3643                 else
3644                         q_vector->eitr = adapter->rx_eitr_param;
3645                 q_vector->v_idx = q_idx;
3646                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
3647                 adapter->q_vector[q_idx] = q_vector;
3648         }
3649
3650         return 0;
3651
3652 err_out:
3653         while (q_idx) {
3654                 q_idx--;
3655                 q_vector = adapter->q_vector[q_idx];
3656                 netif_napi_del(&q_vector->napi);
3657                 kfree(q_vector);
3658                 adapter->q_vector[q_idx] = NULL;
3659         }
3660         return -ENOMEM;
3661 }
3662
3663 /**
3664  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3665  * @adapter: board private structure to initialize
3666  *
3667  * This function frees the memory allocated to the q_vectors.  In addition if
3668  * NAPI is enabled it will delete any references to the NAPI struct prior
3669  * to freeing the q_vector.
3670  **/
3671 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
3672 {
3673         int q_idx, num_q_vectors;
3674
3675         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3676                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3677         else
3678                 num_q_vectors = 1;
3679
3680         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3681                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
3682                 adapter->q_vector[q_idx] = NULL;
3683                 netif_napi_del(&q_vector->napi);
3684                 kfree(q_vector);
3685         }
3686 }
3687
3688 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
3689 {
3690         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3691                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3692                 pci_disable_msix(adapter->pdev);
3693                 kfree(adapter->msix_entries);
3694                 adapter->msix_entries = NULL;
3695         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3696                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3697                 pci_disable_msi(adapter->pdev);
3698         }
3699         return;
3700 }
3701
3702 /**
3703  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3704  * @adapter: board private structure to initialize
3705  *
3706  * We determine which interrupt scheme to use based on...
3707  * - Kernel support (MSI, MSI-X)
3708  *   - which can be user-defined (via MODULE_PARAM)
3709  * - Hardware queue count (num_*_queues)
3710  *   - defined by miscellaneous hardware support/features (RSS, etc.)
3711  **/
3712 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
3713 {
3714         int err;
3715
3716         /* Number of supported queues */
3717         ixgbe_set_num_queues(adapter);
3718
3719         err = ixgbe_set_interrupt_capability(adapter);
3720         if (err) {
3721                 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3722                 goto err_set_interrupt;
3723         }
3724
3725         err = ixgbe_alloc_q_vectors(adapter);
3726         if (err) {
3727                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
3728                         "vectors\n");
3729                 goto err_alloc_q_vectors;
3730         }
3731
3732         err = ixgbe_alloc_queues(adapter);
3733         if (err) {
3734                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3735                 goto err_alloc_queues;
3736         }
3737
3738         DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
3739                 "Tx Queue count = %u\n",
3740                 (adapter->num_rx_queues > 1) ? "Enabled" :
3741                 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
3742
3743         set_bit(__IXGBE_DOWN, &adapter->state);
3744
3745         return 0;
3746
3747 err_alloc_queues:
3748         ixgbe_free_q_vectors(adapter);
3749 err_alloc_q_vectors:
3750         ixgbe_reset_interrupt_capability(adapter);
3751 err_set_interrupt:
3752         return err;
3753 }
3754
3755 /**
3756  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
3757  * @adapter: board private structure to clear interrupt scheme on
3758  *
3759  * We go through and clear interrupt specific resources and reset the structure
3760  * to pre-load conditions
3761  **/
3762 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
3763 {
3764         kfree(adapter->tx_ring);
3765         kfree(adapter->rx_ring);
3766         adapter->tx_ring = NULL;
3767         adapter->rx_ring = NULL;
3768
3769         ixgbe_free_q_vectors(adapter);
3770         ixgbe_reset_interrupt_capability(adapter);
3771 }
3772
3773 /**
3774  * ixgbe_sfp_timer - worker thread to find a missing module
3775  * @data: pointer to our adapter struct
3776  **/
3777 static void ixgbe_sfp_timer(unsigned long data)
3778 {
3779         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3780
3781         /*
3782          * Do the sfp_timer outside of interrupt context due to the
3783          * delays that sfp+ detection requires
3784          */
3785         schedule_work(&adapter->sfp_task);
3786 }
3787
3788 /**
3789  * ixgbe_sfp_task - worker thread to find a missing module
3790  * @work: pointer to work_struct containing our data
3791  **/
3792 static void ixgbe_sfp_task(struct work_struct *work)
3793 {
3794         struct ixgbe_adapter *adapter = container_of(work,
3795                                                      struct ixgbe_adapter,
3796                                                      sfp_task);
3797         struct ixgbe_hw *hw = &adapter->hw;
3798
3799         if ((hw->phy.type == ixgbe_phy_nl) &&
3800             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3801                 s32 ret = hw->phy.ops.identify_sfp(hw);
3802                 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
3803                         goto reschedule;
3804                 ret = hw->phy.ops.reset(hw);
3805                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3806                         dev_err(&adapter->pdev->dev, "failed to initialize "
3807                                 "because an unsupported SFP+ module type "
3808                                 "was detected.\n"
3809                                 "Reload the driver after installing a "
3810                                 "supported module.\n");
3811                         unregister_netdev(adapter->netdev);
3812                 } else {
3813                         DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3814                                 hw->phy.sfp_type);
3815                 }
3816                 /* don't need this routine any more */
3817                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3818         }
3819         return;
3820 reschedule:
3821         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3822                 mod_timer(&adapter->sfp_timer,
3823                           round_jiffies(jiffies + (2 * HZ)));
3824 }
3825
3826 /**
3827  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3828  * @adapter: board private structure to initialize
3829  *
3830  * ixgbe_sw_init initializes the Adapter private data structure.
3831  * Fields are initialized based on PCI device information and
3832  * OS network device settings (MTU size).
3833  **/
3834 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3835 {
3836         struct ixgbe_hw *hw = &adapter->hw;
3837         struct pci_dev *pdev = adapter->pdev;
3838         unsigned int rss;
3839 #ifdef CONFIG_IXGBE_DCB
3840         int j;
3841         struct tc_configuration *tc;
3842 #endif
3843
3844         /* PCI config space info */
3845
3846         hw->vendor_id = pdev->vendor;
3847         hw->device_id = pdev->device;
3848         hw->revision_id = pdev->revision;
3849         hw->subsystem_vendor_id = pdev->subsystem_vendor;
3850         hw->subsystem_device_id = pdev->subsystem_device;
3851
3852         /* Set capability flags */
3853         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3854         adapter->ring_feature[RING_F_RSS].indices = rss;
3855         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
3856         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
3857         if (hw->mac.type == ixgbe_mac_82598EB) {
3858                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
3859                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
3860                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
3861         } else if (hw->mac.type == ixgbe_mac_82599EB) {
3862                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
3863                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
3864                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
3865                 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
3866                 adapter->ring_feature[RING_F_FDIR].indices =
3867                                                          IXGBE_MAX_FDIR_INDICES;
3868                 adapter->atr_sample_rate = 20;
3869                 adapter->fdir_pballoc = 0;
3870 #ifdef IXGBE_FCOE
3871                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
3872                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
3873                 adapter->ring_feature[RING_F_FCOE].indices = 0;
3874                 /* Default traffic class to use for FCoE */
3875                 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
3876 #endif /* IXGBE_FCOE */
3877         }
3878
3879 #ifdef CONFIG_IXGBE_DCB
3880         /* Configure DCB traffic classes */
3881         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3882                 tc = &adapter->dcb_cfg.tc_config[j];
3883                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3884                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3885                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3886                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3887                 tc->dcb_pfc = pfc_disabled;
3888         }
3889         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3890         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3891         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
3892         adapter->dcb_cfg.pfc_mode_enable = false;
3893         adapter->dcb_cfg.round_robin_enable = false;
3894         adapter->dcb_set_bitmap = 0x00;
3895         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3896                            adapter->ring_feature[RING_F_DCB].indices);
3897
3898 #endif
3899
3900         /* default flow control settings */
3901         hw->fc.requested_mode = ixgbe_fc_full;
3902         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
3903 #ifdef CONFIG_DCB
3904         adapter->last_lfc_mode = hw->fc.current_mode;
3905 #endif
3906         hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3907         hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3908         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3909         hw->fc.send_xon = true;
3910         hw->fc.disable_fc_autoneg = false;
3911
3912         /* enable itr by default in dynamic mode */
3913         adapter->rx_itr_setting = 1;
3914         adapter->rx_eitr_param = 20000;
3915         adapter->tx_itr_setting = 1;
3916         adapter->tx_eitr_param = 10000;
3917
3918         /* set defaults for eitr in MegaBytes */
3919         adapter->eitr_low = 10;
3920         adapter->eitr_high = 20;
3921
3922         /* set default ring sizes */
3923         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3924         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
3925
3926         /* initialize eeprom parameters */
3927         if (ixgbe_init_eeprom_params_generic(hw)) {
3928                 dev_err(&pdev->dev, "EEPROM initialization failed\n");
3929                 return -EIO;
3930         }
3931
3932         /* enable rx csum by default */
3933         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
3934
3935         set_bit(__IXGBE_DOWN, &adapter->state);
3936
3937         return 0;
3938 }
3939
3940 /**
3941  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3942  * @adapter: board private structure
3943  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
3944  *
3945  * Return 0 on success, negative on failure
3946  **/
3947 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
3948                              struct ixgbe_ring *tx_ring)
3949 {
3950         struct pci_dev *pdev = adapter->pdev;
3951         int size;
3952
3953         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3954         tx_ring->tx_buffer_info = vmalloc(size);
3955         if (!tx_ring->tx_buffer_info)
3956                 goto err;
3957         memset(tx_ring->tx_buffer_info, 0, size);
3958
3959         /* round up to nearest 4K */
3960         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3961         tx_ring->size = ALIGN(tx_ring->size, 4096);
3962
3963         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
3964                                              &tx_ring->dma);
3965         if (!tx_ring->desc)
3966                 goto err;
3967
3968         tx_ring->next_to_use = 0;
3969         tx_ring->next_to_clean = 0;
3970         tx_ring->work_limit = tx_ring->count;
3971         return 0;
3972
3973 err:
3974         vfree(tx_ring->tx_buffer_info);
3975         tx_ring->tx_buffer_info = NULL;
3976         DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
3977                             "descriptor ring\n");
3978         return -ENOMEM;
3979 }
3980
3981 /**
3982  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
3983  * @adapter: board private structure
3984  *
3985  * If this function returns with an error, then it's possible one or
3986  * more of the rings is populated (while the rest are not).  It is the
3987  * callers duty to clean those orphaned rings.
3988  *
3989  * Return 0 on success, negative on failure
3990  **/
3991 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
3992 {
3993         int i, err = 0;
3994
3995         for (i = 0; i < adapter->num_tx_queues; i++) {
3996                 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
3997                 if (!err)
3998                         continue;
3999                 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
4000                 break;
4001         }
4002
4003         return err;
4004 }
4005
4006 /**
4007  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4008  * @adapter: board private structure
4009  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
4010  *
4011  * Returns 0 on success, negative on failure
4012  **/
4013 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
4014                              struct ixgbe_ring *rx_ring)
4015 {
4016         struct pci_dev *pdev = adapter->pdev;
4017         int size;
4018
4019         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4020         rx_ring->rx_buffer_info = vmalloc(size);
4021         if (!rx_ring->rx_buffer_info) {
4022                 DPRINTK(PROBE, ERR,
4023                         "vmalloc allocation failed for the rx desc ring\n");
4024                 goto alloc_failed;
4025         }
4026         memset(rx_ring->rx_buffer_info, 0, size);
4027
4028         /* Round up to nearest 4K */
4029         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4030         rx_ring->size = ALIGN(rx_ring->size, 4096);
4031
4032         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
4033
4034         if (!rx_ring->desc) {
4035                 DPRINTK(PROBE, ERR,
4036                         "Memory allocation failed for the rx desc ring\n");
4037                 vfree(rx_ring->rx_buffer_info);
4038                 goto alloc_failed;
4039         }
4040
4041         rx_ring->next_to_clean = 0;
4042         rx_ring->next_to_use = 0;
4043
4044         return 0;
4045
4046 alloc_failed:
4047         return -ENOMEM;
4048 }
4049
4050 /**
4051  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4052  * @adapter: board private structure
4053  *
4054  * If this function returns with an error, then it's possible one or
4055  * more of the rings is populated (while the rest are not).  It is the
4056  * callers duty to clean those orphaned rings.
4057  *
4058  * Return 0 on success, negative on failure
4059  **/
4060
4061 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4062 {
4063         int i, err = 0;
4064
4065         for (i = 0; i < adapter->num_rx_queues; i++) {
4066                 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
4067                 if (!err)
4068                         continue;
4069                 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
4070                 break;
4071         }
4072
4073         return err;
4074 }
4075
4076 /**
4077  * ixgbe_free_tx_resources - Free Tx Resources per Queue
4078  * @adapter: board private structure
4079  * @tx_ring: Tx descriptor ring for a specific queue
4080  *
4081  * Free all transmit software resources
4082  **/
4083 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4084                              struct ixgbe_ring *tx_ring)
4085 {
4086         struct pci_dev *pdev = adapter->pdev;
4087
4088         ixgbe_clean_tx_ring(adapter, tx_ring);
4089
4090         vfree(tx_ring->tx_buffer_info);
4091         tx_ring->tx_buffer_info = NULL;
4092
4093         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
4094
4095         tx_ring->desc = NULL;
4096 }
4097
4098 /**
4099  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4100  * @adapter: board private structure
4101  *
4102  * Free all transmit software resources
4103  **/
4104 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4105 {
4106         int i;
4107
4108         for (i = 0; i < adapter->num_tx_queues; i++)
4109                 if (adapter->tx_ring[i].desc)
4110                         ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
4111 }
4112
4113 /**
4114  * ixgbe_free_rx_resources - Free Rx Resources
4115  * @adapter: board private structure
4116  * @rx_ring: ring to clean the resources from
4117  *
4118  * Free all receive software resources
4119  **/
4120 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4121                              struct ixgbe_ring *rx_ring)
4122 {
4123         struct pci_dev *pdev = adapter->pdev;
4124
4125         ixgbe_clean_rx_ring(adapter, rx_ring);
4126
4127         vfree(rx_ring->rx_buffer_info);
4128         rx_ring->rx_buffer_info = NULL;
4129
4130         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
4131
4132         rx_ring->desc = NULL;
4133 }
4134
4135 /**
4136  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4137  * @adapter: board private structure
4138  *
4139  * Free all receive software resources
4140  **/
4141 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4142 {
4143         int i;
4144
4145         for (i = 0; i < adapter->num_rx_queues; i++)
4146                 if (adapter->rx_ring[i].desc)
4147                         ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
4148 }
4149
4150 /**
4151  * ixgbe_change_mtu - Change the Maximum Transfer Unit
4152  * @netdev: network interface device structure
4153  * @new_mtu: new value for maximum frame size
4154  *
4155  * Returns 0 on success, negative on failure
4156  **/
4157 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4158 {
4159         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4160         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4161
4162         /* MTU < 68 is an error and causes problems on some kernels */
4163         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4164                 return -EINVAL;
4165
4166         DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
4167                 netdev->mtu, new_mtu);
4168         /* must set new MTU before calling down or up */
4169         netdev->mtu = new_mtu;
4170
4171         if (netif_running(netdev))
4172                 ixgbe_reinit_locked(adapter);
4173
4174         return 0;
4175 }
4176
4177 /**
4178  * ixgbe_open - Called when a network interface is made active
4179  * @netdev: network interface device structure
4180  *
4181  * Returns 0 on success, negative value on failure
4182  *
4183  * The open entry point is called when a network interface is made
4184  * active by the system (IFF_UP).  At this point all resources needed
4185  * for transmit and receive operations are allocated, the interrupt
4186  * handler is registered with the OS, the watchdog timer is started,
4187  * and the stack is notified that the interface is ready.
4188  **/
4189 static int ixgbe_open(struct net_device *netdev)
4190 {
4191         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4192         int err;
4193
4194         /* disallow open during test */
4195         if (test_bit(__IXGBE_TESTING, &adapter->state))
4196                 return -EBUSY;
4197
4198         netif_carrier_off(netdev);
4199
4200         /* allocate transmit descriptors */
4201         err = ixgbe_setup_all_tx_resources(adapter);
4202         if (err)
4203                 goto err_setup_tx;
4204
4205         /* allocate receive descriptors */
4206         err = ixgbe_setup_all_rx_resources(adapter);
4207         if (err)
4208                 goto err_setup_rx;
4209
4210         ixgbe_configure(adapter);
4211
4212         err = ixgbe_request_irq(adapter);
4213         if (err)
4214                 goto err_req_irq;
4215
4216         err = ixgbe_up_complete(adapter);
4217         if (err)
4218                 goto err_up;
4219
4220         netif_tx_start_all_queues(netdev);
4221
4222         return 0;
4223
4224 err_up:
4225         ixgbe_release_hw_control(adapter);
4226         ixgbe_free_irq(adapter);
4227 err_req_irq:
4228 err_setup_rx:
4229         ixgbe_free_all_rx_resources(adapter);
4230 err_setup_tx:
4231         ixgbe_free_all_tx_resources(adapter);
4232         ixgbe_reset(adapter);
4233
4234         return err;
4235 }
4236
4237 /**
4238  * ixgbe_close - Disables a network interface
4239  * @netdev: network interface device structure
4240  *
4241  * Returns 0, this is not allowed to fail
4242  *
4243  * The close entry point is called when an interface is de-activated
4244  * by the OS.  The hardware is still under the drivers control, but
4245  * needs to be disabled.  A global MAC reset is issued to stop the
4246  * hardware, and all transmit and receive resources are freed.
4247  **/
4248 static int ixgbe_close(struct net_device *netdev)
4249 {
4250         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4251
4252         ixgbe_down(adapter);
4253         ixgbe_free_irq(adapter);
4254
4255         ixgbe_free_all_tx_resources(adapter);
4256         ixgbe_free_all_rx_resources(adapter);
4257
4258         ixgbe_release_hw_control(adapter);
4259
4260         return 0;
4261 }
4262
4263 #ifdef CONFIG_PM
4264 static int ixgbe_resume(struct pci_dev *pdev)
4265 {
4266         struct net_device *netdev = pci_get_drvdata(pdev);
4267         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4268         u32 err;
4269
4270         pci_set_power_state(pdev, PCI_D0);
4271         pci_restore_state(pdev);
4272
4273         err = pci_enable_device_mem(pdev);
4274         if (err) {
4275                 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
4276                                 "suspend\n");
4277                 return err;
4278         }
4279         pci_set_master(pdev);
4280
4281         pci_wake_from_d3(pdev, false);
4282
4283         err = ixgbe_init_interrupt_scheme(adapter);
4284         if (err) {
4285                 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
4286                                 "device\n");
4287                 return err;
4288         }
4289
4290         ixgbe_reset(adapter);
4291
4292         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4293
4294         if (netif_running(netdev)) {
4295                 err = ixgbe_open(adapter->netdev);
4296                 if (err)
4297                         return err;
4298         }
4299
4300         netif_device_attach(netdev);
4301
4302         return 0;
4303 }
4304 #endif /* CONFIG_PM */
4305
4306 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
4307 {
4308         struct net_device *netdev = pci_get_drvdata(pdev);
4309         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4310         struct ixgbe_hw *hw = &adapter->hw;
4311         u32 ctrl, fctrl;
4312         u32 wufc = adapter->wol;
4313 #ifdef CONFIG_PM
4314         int retval = 0;
4315 #endif
4316
4317         netif_device_detach(netdev);
4318
4319         if (netif_running(netdev)) {
4320                 ixgbe_down(adapter);
4321                 ixgbe_free_irq(adapter);
4322                 ixgbe_free_all_tx_resources(adapter);
4323                 ixgbe_free_all_rx_resources(adapter);
4324         }
4325         ixgbe_clear_interrupt_scheme(adapter);
4326
4327 #ifdef CONFIG_PM
4328         retval = pci_save_state(pdev);
4329         if (retval)
4330                 return retval;
4331
4332 #endif
4333         if (wufc) {
4334                 ixgbe_set_rx_mode(netdev);
4335
4336                 /* turn on all-multi mode if wake on multicast is enabled */
4337                 if (wufc & IXGBE_WUFC_MC) {
4338                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4339                         fctrl |= IXGBE_FCTRL_MPE;
4340                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4341                 }
4342
4343                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4344                 ctrl |= IXGBE_CTRL_GIO_DIS;
4345                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4346
4347                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4348         } else {
4349                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4350                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4351         }
4352
4353         if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4354                 pci_wake_from_d3(pdev, true);
4355         else
4356                 pci_wake_from_d3(pdev, false);
4357
4358         *enable_wake = !!wufc;
4359
4360         ixgbe_release_hw_control(adapter);
4361
4362         pci_disable_device(pdev);
4363
4364         return 0;
4365 }
4366
4367 #ifdef CONFIG_PM
4368 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4369 {
4370         int retval;
4371         bool wake;
4372
4373         retval = __ixgbe_shutdown(pdev, &wake);
4374         if (retval)
4375                 return retval;
4376
4377         if (wake) {
4378                 pci_prepare_to_sleep(pdev);
4379         } else {
4380                 pci_wake_from_d3(pdev, false);
4381                 pci_set_power_state(pdev, PCI_D3hot);
4382         }
4383
4384         return 0;
4385 }
4386 #endif /* CONFIG_PM */
4387
4388 static void ixgbe_shutdown(struct pci_dev *pdev)
4389 {
4390         bool wake;
4391
4392         __ixgbe_shutdown(pdev, &wake);
4393
4394         if (system_state == SYSTEM_POWER_OFF) {
4395                 pci_wake_from_d3(pdev, wake);
4396                 pci_set_power_state(pdev, PCI_D3hot);
4397         }
4398 }
4399
4400 /**
4401  * ixgbe_update_stats - Update the board statistics counters.
4402  * @adapter: board private structure
4403  **/
4404 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4405 {
4406         struct ixgbe_hw *hw = &adapter->hw;
4407         u64 total_mpc = 0;
4408         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
4409
4410         if (hw->mac.type == ixgbe_mac_82599EB) {
4411                 u64 rsc_count = 0;
4412                 for (i = 0; i < 16; i++)
4413                         adapter->hw_rx_no_dma_resources +=
4414                                              IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4415                 for (i = 0; i < adapter->num_rx_queues; i++)
4416                         rsc_count += adapter->rx_ring[i].rsc_count;
4417                 adapter->rsc_count = rsc_count;
4418         }
4419
4420         adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
4421         for (i = 0; i < 8; i++) {
4422                 /* for packet buffers not used, the register should read 0 */
4423                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4424                 missed_rx += mpc;
4425                 adapter->stats.mpc[i] += mpc;
4426                 total_mpc += adapter->stats.mpc[i];
4427                 if (hw->mac.type == ixgbe_mac_82598EB)
4428                         adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
4429                 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4430                 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4431                 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4432                 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
4433                 if (hw->mac.type == ixgbe_mac_82599EB) {
4434                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4435                                                             IXGBE_PXONRXCNT(i));
4436                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4437                                                            IXGBE_PXOFFRXCNT(i));
4438                         adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4439                 } else {
4440                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4441                                                               IXGBE_PXONRXC(i));
4442                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4443                                                              IXGBE_PXOFFRXC(i));
4444                 }
4445                 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4446                                                             IXGBE_PXONTXC(i));
4447                 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
4448                                                              IXGBE_PXOFFTXC(i));
4449         }
4450         adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4451         /* work around hardware counting issue */
4452         adapter->stats.gprc -= missed_rx;
4453
4454         /* 82598 hardware only has a 32 bit counter in the high register */
4455         if (hw->mac.type == ixgbe_mac_82599EB) {
4456                 u64 tmp;
4457                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
4458                 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
4459                 adapter->stats.gorc += (tmp << 32);
4460                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
4461                 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
4462                 adapter->stats.gotc += (tmp << 32);
4463                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4464                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4465                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4466                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
4467                 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
4468                 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
4469 #ifdef IXGBE_FCOE
4470                 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4471                 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4472                 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4473                 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4474                 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4475                 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4476 #endif /* IXGBE_FCOE */
4477         } else {
4478                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4479                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4480                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4481                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4482                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4483         }
4484         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4485         adapter->stats.bprc += bprc;
4486         adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
4487         if (hw->mac.type == ixgbe_mac_82598EB)
4488                 adapter->stats.mprc -= bprc;
4489         adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4490         adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4491         adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4492         adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4493         adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4494         adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4495         adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
4496         adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
4497         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4498         adapter->stats.lxontxc += lxon;
4499         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4500         adapter->stats.lxofftxc += lxoff;
4501         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4502         adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
4503         adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4504         /*
4505          * 82598 errata - tx of flow control packets is included in tx counters
4506          */
4507         xon_off_tot = lxon + lxoff;
4508         adapter->stats.gptc -= xon_off_tot;
4509         adapter->stats.mptc -= xon_off_tot;
4510         adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
4511         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4512         adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4513         adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
4514         adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4515         adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
4516         adapter->stats.ptc64 -= xon_off_tot;
4517         adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4518         adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4519         adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4520         adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4521         adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
4522         adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4523
4524         /* Fill out the OS statistics structure */
4525         adapter->net_stats.multicast = adapter->stats.mprc;
4526
4527         /* Rx Errors */
4528         adapter->net_stats.rx_errors = adapter->stats.crcerrs +
4529                                        adapter->stats.rlec;
4530         adapter->net_stats.rx_dropped = 0;
4531         adapter->net_stats.rx_length_errors = adapter->stats.rlec;
4532         adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
4533         adapter->net_stats.rx_missed_errors = total_mpc;
4534 }
4535
4536 /**
4537  * ixgbe_watchdog - Timer Call-back
4538  * @data: pointer to adapter cast into an unsigned long
4539  **/
4540 static void ixgbe_watchdog(unsigned long data)
4541 {
4542         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4543         struct ixgbe_hw *hw = &adapter->hw;
4544         u64 eics = 0;
4545         int i;
4546
4547         /*
4548          *  Do the watchdog outside of interrupt context due to the lovely
4549          * delays that some of the newer hardware requires
4550          */
4551
4552         if (test_bit(__IXGBE_DOWN, &adapter->state))
4553                 goto watchdog_short_circuit;
4554
4555         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
4556                 /*
4557                  * for legacy and MSI interrupts don't set any bits
4558                  * that are enabled for EIAM, because this operation
4559                  * would set *both* EIMS and EICS for any bit in EIAM
4560                  */
4561                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4562                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4563                 goto watchdog_reschedule;
4564         }
4565
4566         /* get one bit for every active tx/rx interrupt vector */
4567         for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
4568                 struct ixgbe_q_vector *qv = adapter->q_vector[i];
4569                 if (qv->rxr_count || qv->txr_count)
4570                         eics |= ((u64)1 << i);
4571         }
4572
4573         /* Cause software interrupt to ensure rx rings are cleaned */
4574         ixgbe_irq_rearm_queues(adapter, eics);
4575
4576 watchdog_reschedule:
4577         /* Reset the timer */
4578         mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
4579
4580 watchdog_short_circuit:
4581         schedule_work(&adapter->watchdog_task);
4582 }
4583
4584 /**
4585  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4586  * @work: pointer to work_struct containing our data
4587  **/
4588 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4589 {
4590         struct ixgbe_adapter *adapter = container_of(work,
4591                                                      struct ixgbe_adapter,
4592                                                      multispeed_fiber_task);
4593         struct ixgbe_hw *hw = &adapter->hw;
4594         u32 autoneg;
4595         bool negotiation;
4596
4597         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
4598         autoneg = hw->phy.autoneg_advertised;
4599         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
4600                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
4601         if (hw->mac.ops.setup_link)
4602                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
4603         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4604         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4605 }
4606
4607 /**
4608  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4609  * @work: pointer to work_struct containing our data
4610  **/
4611 static void ixgbe_sfp_config_module_task(struct work_struct *work)
4612 {
4613         struct ixgbe_adapter *adapter = container_of(work,
4614                                                      struct ixgbe_adapter,
4615                                                      sfp_config_module_task);
4616         struct ixgbe_hw *hw = &adapter->hw;
4617         u32 err;
4618
4619         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
4620
4621         /* Time for electrical oscillations to settle down */
4622         msleep(100);
4623         err = hw->phy.ops.identify_sfp(hw);
4624
4625         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4626                 dev_err(&adapter->pdev->dev, "failed to initialize because "
4627                         "an unsupported SFP+ module type was detected.\n"
4628                         "Reload the driver after installing a supported "
4629                         "module.\n");
4630                 unregister_netdev(adapter->netdev);
4631                 return;
4632         }
4633         hw->mac.ops.setup_sfp(hw);
4634
4635         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
4636                 /* This will also work for DA Twinax connections */
4637                 schedule_work(&adapter->multispeed_fiber_task);
4638         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4639 }
4640
4641 /**
4642  * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
4643  * @work: pointer to work_struct containing our data
4644  **/
4645 static void ixgbe_fdir_reinit_task(struct work_struct *work)
4646 {
4647         struct ixgbe_adapter *adapter = container_of(work,
4648                                                      struct ixgbe_adapter,
4649                                                      fdir_reinit_task);
4650         struct ixgbe_hw *hw = &adapter->hw;
4651         int i;
4652
4653         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
4654                 for (i = 0; i < adapter->num_tx_queues; i++)
4655                         set_bit(__IXGBE_FDIR_INIT_DONE,
4656                                 &(adapter->tx_ring[i].reinit_state));
4657         } else {
4658                 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
4659                         "ignored adding FDIR ATR filters \n");
4660         }
4661         /* Done FDIR Re-initialization, enable transmits */
4662         netif_tx_start_all_queues(adapter->netdev);
4663 }
4664
4665 /**
4666  * ixgbe_watchdog_task - worker thread to bring link up
4667  * @work: pointer to work_struct containing our data
4668  **/
4669 static void ixgbe_watchdog_task(struct work_struct *work)
4670 {
4671         struct ixgbe_adapter *adapter = container_of(work,
4672                                                      struct ixgbe_adapter,
4673                                                      watchdog_task);
4674         struct net_device *netdev = adapter->netdev;
4675         struct ixgbe_hw *hw = &adapter->hw;
4676         u32 link_speed = adapter->link_speed;
4677         bool link_up = adapter->link_up;
4678         int i;
4679         struct ixgbe_ring *tx_ring;
4680         int some_tx_pending = 0;
4681
4682         adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4683
4684         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4685                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
4686                 if (link_up) {
4687 #ifdef CONFIG_DCB
4688                         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4689                                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
4690                                         hw->mac.ops.fc_enable(hw, i);
4691                         } else {
4692                                 hw->mac.ops.fc_enable(hw, 0);
4693                         }
4694 #else
4695                         hw->mac.ops.fc_enable(hw, 0);
4696 #endif
4697                 }
4698
4699                 if (link_up ||
4700                     time_after(jiffies, (adapter->link_check_timeout +
4701                                          IXGBE_TRY_LINK_TIMEOUT))) {
4702                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4703                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
4704                 }
4705                 adapter->link_up = link_up;
4706                 adapter->link_speed = link_speed;
4707         }
4708
4709         if (link_up) {
4710                 if (!netif_carrier_ok(netdev)) {
4711                         bool flow_rx, flow_tx;
4712
4713                         if (hw->mac.type == ixgbe_mac_82599EB) {
4714                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4715                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4716                                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
4717                                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
4718                         } else {
4719                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4720                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
4721                                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
4722                                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
4723                         }
4724
4725                         printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4726                                "Flow Control: %s\n",
4727                                netdev->name,
4728                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4729                                 "10 Gbps" :
4730                                 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4731                                  "1 Gbps" : "unknown speed")),
4732                                ((flow_rx && flow_tx) ? "RX/TX" :
4733                                 (flow_rx ? "RX" :
4734                                 (flow_tx ? "TX" : "None"))));
4735
4736                         netif_carrier_on(netdev);
4737                 } else {
4738                         /* Force detection of hung controller */
4739                         adapter->detect_tx_hung = true;
4740                 }
4741         } else {
4742                 adapter->link_up = false;
4743                 adapter->link_speed = 0;
4744                 if (netif_carrier_ok(netdev)) {
4745                         printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4746                                netdev->name);
4747                         netif_carrier_off(netdev);
4748                 }
4749         }
4750
4751         if (!netif_carrier_ok(netdev)) {
4752                 for (i = 0; i < adapter->num_tx_queues; i++) {
4753                         tx_ring = &adapter->tx_ring[i];
4754                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
4755                                 some_tx_pending = 1;
4756                                 break;
4757                         }
4758                 }
4759
4760                 if (some_tx_pending) {
4761                         /* We've lost link, so the controller stops DMA,
4762                          * but we've got queued Tx work that's never going
4763                          * to get done, so reset controller to flush Tx.
4764                          * (Do the reset outside of interrupt context).
4765                          */
4766                          schedule_work(&adapter->reset_task);
4767                 }
4768         }
4769
4770         ixgbe_update_stats(adapter);
4771         adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
4772 }
4773
4774 static int ixgbe_tso(struct ixgbe_adapter *adapter,
4775                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4776                      u32 tx_flags, u8 *hdr_len)
4777 {
4778         struct ixgbe_adv_tx_context_desc *context_desc;
4779         unsigned int i;
4780         int err;
4781         struct ixgbe_tx_buffer *tx_buffer_info;
4782         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4783         u32 mss_l4len_idx, l4len;
4784
4785         if (skb_is_gso(skb)) {
4786                 if (skb_header_cloned(skb)) {
4787                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4788                         if (err)
4789                                 return err;
4790                 }
4791                 l4len = tcp_hdrlen(skb);
4792                 *hdr_len += l4len;
4793
4794                 if (skb->protocol == htons(ETH_P_IP)) {
4795                         struct iphdr *iph = ip_hdr(skb);
4796                         iph->tot_len = 0;
4797                         iph->check = 0;
4798                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4799                                                                  iph->daddr, 0,
4800                                                                  IPPROTO_TCP,
4801                                                                  0);
4802                         adapter->hw_tso_ctxt++;
4803                 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4804                         ipv6_hdr(skb)->payload_len = 0;
4805                         tcp_hdr(skb)->check =
4806                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4807                                              &ipv6_hdr(skb)->daddr,
4808                                              0, IPPROTO_TCP, 0);
4809                         adapter->hw_tso6_ctxt++;
4810                 }
4811
4812                 i = tx_ring->next_to_use;
4813
4814                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4815                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4816
4817                 /* VLAN MACLEN IPLEN */
4818                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4819                         vlan_macip_lens |=
4820                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4821                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
4822                                     IXGBE_ADVTXD_MACLEN_SHIFT);
4823                 *hdr_len += skb_network_offset(skb);
4824                 vlan_macip_lens |=
4825                     (skb_transport_header(skb) - skb_network_header(skb));
4826                 *hdr_len +=
4827                     (skb_transport_header(skb) - skb_network_header(skb));
4828                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4829                 context_desc->seqnum_seed = 0;
4830
4831                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4832                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
4833                                    IXGBE_ADVTXD_DTYP_CTXT);
4834
4835                 if (skb->protocol == htons(ETH_P_IP))
4836                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4837                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4838                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4839
4840                 /* MSS L4LEN IDX */
4841                 mss_l4len_idx =
4842                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4843                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4844                 /* use index 1 for TSO */
4845                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4846                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4847
4848                 tx_buffer_info->time_stamp = jiffies;
4849                 tx_buffer_info->next_to_watch = i;
4850
4851                 i++;
4852                 if (i == tx_ring->count)
4853                         i = 0;
4854                 tx_ring->next_to_use = i;
4855
4856                 return true;
4857         }
4858         return false;
4859 }
4860
4861 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
4862                           struct ixgbe_ring *tx_ring,
4863                           struct sk_buff *skb, u32 tx_flags)
4864 {
4865         struct ixgbe_adv_tx_context_desc *context_desc;
4866         unsigned int i;
4867         struct ixgbe_tx_buffer *tx_buffer_info;
4868         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4869
4870         if (skb->ip_summed == CHECKSUM_PARTIAL ||
4871             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4872                 i = tx_ring->next_to_use;
4873                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4874                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4875
4876                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4877                         vlan_macip_lens |=
4878                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4879                 vlan_macip_lens |= (skb_network_offset(skb) <<
4880                                     IXGBE_ADVTXD_MACLEN_SHIFT);
4881                 if (skb->ip_summed == CHECKSUM_PARTIAL)
4882                         vlan_macip_lens |= (skb_transport_header(skb) -
4883                                             skb_network_header(skb));
4884
4885                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4886                 context_desc->seqnum_seed = 0;
4887
4888                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
4889                                     IXGBE_ADVTXD_DTYP_CTXT);
4890
4891                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4892                         switch (skb->protocol) {
4893                         case cpu_to_be16(ETH_P_IP):
4894                                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4895                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4896                                         type_tucmd_mlhl |=
4897                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4898                                 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
4899                                         type_tucmd_mlhl |=
4900                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4901                                 break;
4902                         case cpu_to_be16(ETH_P_IPV6):
4903                                 /* XXX what about other V6 headers?? */
4904                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4905                                         type_tucmd_mlhl |=
4906                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4907                                 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
4908                                         type_tucmd_mlhl |=
4909                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4910                                 break;
4911                         default:
4912                                 if (unlikely(net_ratelimit())) {
4913                                         DPRINTK(PROBE, WARNING,
4914                                          "partial checksum but proto=%x!\n",
4915                                          skb->protocol);
4916                                 }
4917                                 break;
4918                         }
4919                 }
4920
4921                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4922                 /* use index zero for tx checksum offload */
4923                 context_desc->mss_l4len_idx = 0;
4924
4925                 tx_buffer_info->time_stamp = jiffies;
4926                 tx_buffer_info->next_to_watch = i;
4927
4928                 adapter->hw_csum_tx_good++;
4929                 i++;
4930                 if (i == tx_ring->count)
4931                         i = 0;
4932                 tx_ring->next_to_use = i;
4933
4934                 return true;
4935         }
4936
4937         return false;
4938 }
4939
4940 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
4941                         struct ixgbe_ring *tx_ring,
4942                         struct sk_buff *skb, u32 tx_flags,
4943                         unsigned int first)
4944 {
4945         struct ixgbe_tx_buffer *tx_buffer_info;
4946         unsigned int len;
4947         unsigned int total = skb->len;
4948         unsigned int offset = 0, size, count = 0, i;
4949         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
4950         unsigned int f;
4951         dma_addr_t *map;
4952
4953         i = tx_ring->next_to_use;
4954
4955         if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
4956                 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
4957                 return 0;
4958         }
4959
4960         map = skb_shinfo(skb)->dma_maps;
4961
4962         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
4963                 /* excluding fcoe_crc_eof for FCoE */
4964                 total -= sizeof(struct fcoe_crc_eof);
4965
4966         len = min(skb_headlen(skb), total);
4967         while (len) {
4968                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4969                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4970
4971                 tx_buffer_info->length = size;
4972                 tx_buffer_info->dma = skb_shinfo(skb)->dma_head + offset;
4973                 tx_buffer_info->time_stamp = jiffies;
4974                 tx_buffer_info->next_to_watch = i;
4975
4976                 len -= size;
4977                 total -= size;
4978                 offset += size;
4979                 count++;
4980
4981                 if (len) {
4982                         i++;
4983                         if (i == tx_ring->count)
4984                                 i = 0;
4985                 }
4986         }
4987
4988         for (f = 0; f < nr_frags; f++) {
4989                 struct skb_frag_struct *frag;
4990
4991                 frag = &skb_shinfo(skb)->frags[f];
4992                 len = min((unsigned int)frag->size, total);
4993                 offset = 0;
4994
4995                 while (len) {
4996                         i++;
4997                         if (i == tx_ring->count)
4998                                 i = 0;
4999
5000                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
5001                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5002
5003                         tx_buffer_info->length = size;
5004                         tx_buffer_info->dma = map[f] + offset;
5005                         tx_buffer_info->time_stamp = jiffies;
5006                         tx_buffer_info->next_to_watch = i;
5007
5008                         len -= size;
5009                         total -= size;
5010                         offset += size;
5011                         count++;
5012                 }
5013                 if (total == 0)
5014                         break;
5015         }
5016
5017         tx_ring->tx_buffer_info[i].skb = skb;
5018         tx_ring->tx_buffer_info[first].next_to_watch = i;
5019
5020         return count;
5021 }
5022
5023 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
5024                            struct ixgbe_ring *tx_ring,
5025                            int tx_flags, int count, u32 paylen, u8 hdr_len)
5026 {
5027         union ixgbe_adv_tx_desc *tx_desc = NULL;
5028         struct ixgbe_tx_buffer *tx_buffer_info;
5029         u32 olinfo_status = 0, cmd_type_len = 0;
5030         unsigned int i;
5031         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
5032
5033         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
5034
5035         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
5036
5037         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5038                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
5039
5040         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
5041                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5042
5043                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5044                                  IXGBE_ADVTXD_POPTS_SHIFT;
5045
5046                 /* use index 1 context for tso */
5047                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5048                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5049                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
5050                                          IXGBE_ADVTXD_POPTS_SHIFT;
5051
5052         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5053                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5054                                  IXGBE_ADVTXD_POPTS_SHIFT;
5055
5056         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5057                 olinfo_status |= IXGBE_ADVTXD_CC;
5058                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5059                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
5060                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5061         }
5062
5063         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
5064
5065         i = tx_ring->next_to_use;
5066         while (count--) {
5067                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5068                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
5069                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
5070                 tx_desc->read.cmd_type_len =
5071                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
5072                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
5073                 i++;
5074                 if (i == tx_ring->count)
5075                         i = 0;
5076         }
5077
5078         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5079
5080         /*
5081          * Force memory writes to complete before letting h/w
5082          * know there are new descriptors to fetch.  (Only
5083          * applicable for weak-ordered memory model archs,
5084          * such as IA-64).
5085          */
5086         wmb();
5087
5088         tx_ring->next_to_use = i;
5089         writel(i, adapter->hw.hw_addr + tx_ring->tail);
5090 }
5091
5092 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5093                       int queue, u32 tx_flags)
5094 {
5095         /* Right now, we support IPv4 only */
5096         struct ixgbe_atr_input atr_input;
5097         struct tcphdr *th;
5098         struct iphdr *iph = ip_hdr(skb);
5099         struct ethhdr *eth = (struct ethhdr *)skb->data;
5100         u16 vlan_id, src_port, dst_port, flex_bytes;
5101         u32 src_ipv4_addr, dst_ipv4_addr;
5102         u8 l4type = 0;
5103
5104         /* check if we're UDP or TCP */
5105         if (iph->protocol == IPPROTO_TCP) {
5106                 th = tcp_hdr(skb);
5107                 src_port = th->source;
5108                 dst_port = th->dest;
5109                 l4type |= IXGBE_ATR_L4TYPE_TCP;
5110                 /* l4type IPv4 type is 0, no need to assign */
5111         } else {
5112                 /* Unsupported L4 header, just bail here */
5113                 return;
5114         }
5115
5116         memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5117
5118         vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5119                    IXGBE_TX_FLAGS_VLAN_SHIFT;
5120         src_ipv4_addr = iph->saddr;
5121         dst_ipv4_addr = iph->daddr;
5122         flex_bytes = eth->h_proto;
5123
5124         ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5125         ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5126         ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5127         ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5128         ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5129         /* src and dst are inverted, think how the receiver sees them */
5130         ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5131         ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5132
5133         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5134         ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5135 }
5136
5137 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
5138                                  struct ixgbe_ring *tx_ring, int size)
5139 {
5140         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5141
5142         netif_stop_subqueue(netdev, tx_ring->queue_index);
5143         /* Herbert's original patch had:
5144          *  smp_mb__after_netif_stop_queue();
5145          * but since that doesn't exist yet, just open code it. */
5146         smp_mb();
5147
5148         /* We need to check again in a case another CPU has just
5149          * made room available. */
5150         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
5151                 return -EBUSY;
5152
5153         /* A reprieve! - use start_queue because it doesn't call schedule */
5154         netif_start_subqueue(netdev, tx_ring->queue_index);
5155         ++adapter->restart_queue;
5156         return 0;
5157 }
5158
5159 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
5160                               struct ixgbe_ring *tx_ring, int size)
5161 {
5162         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
5163                 return 0;
5164         return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
5165 }
5166
5167 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
5168 {
5169         struct ixgbe_adapter *adapter = netdev_priv(dev);
5170
5171         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
5172                 return smp_processor_id();
5173
5174         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5175                 return (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK) >> 13;
5176
5177         return skb_tx_hash(dev, skb);
5178 }
5179
5180 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
5181                                     struct net_device *netdev)
5182 {
5183         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5184         struct ixgbe_ring *tx_ring;
5185         unsigned int first;
5186         unsigned int tx_flags = 0;
5187         u8 hdr_len = 0;
5188         int r_idx = 0, tso;
5189         int count = 0;
5190         unsigned int f;
5191
5192         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
5193                 tx_flags |= vlan_tx_tag_get(skb);
5194                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5195                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5196                         tx_flags |= (skb->queue_mapping << 13);
5197                 }
5198                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5199                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5200         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5201                 if (skb->priority != TC_PRIO_CONTROL) {
5202                         tx_flags |= (skb->queue_mapping << 13);
5203                         tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5204                         tx_flags |= IXGBE_TX_FLAGS_VLAN;
5205                 } else {
5206                         skb->queue_mapping =
5207                                 adapter->ring_feature[RING_F_DCB].indices-1;
5208                 }
5209         }
5210
5211         r_idx = skb->queue_mapping;
5212         tx_ring = &adapter->tx_ring[r_idx];
5213
5214         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
5215             (skb->protocol == htons(ETH_P_FCOE))) {
5216                 tx_flags |= IXGBE_TX_FLAGS_FCOE;
5217 #ifdef IXGBE_FCOE
5218                 r_idx = smp_processor_id();
5219                 r_idx &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
5220                 r_idx += adapter->ring_feature[RING_F_FCOE].mask;
5221                 tx_ring = &adapter->tx_ring[r_idx];
5222 #endif
5223         }
5224         /* four things can cause us to need a context descriptor */
5225         if (skb_is_gso(skb) ||
5226             (skb->ip_summed == CHECKSUM_PARTIAL) ||
5227             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
5228             (tx_flags & IXGBE_TX_FLAGS_FCOE))
5229                 count++;
5230
5231         count += TXD_USE_COUNT(skb_headlen(skb));
5232         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5233                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5234
5235         if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
5236                 adapter->tx_busy++;
5237                 return NETDEV_TX_BUSY;
5238         }
5239
5240         first = tx_ring->next_to_use;
5241         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5242 #ifdef IXGBE_FCOE
5243                 /* setup tx offload for FCoE */
5244                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5245                 if (tso < 0) {
5246                         dev_kfree_skb_any(skb);
5247                         return NETDEV_TX_OK;
5248                 }
5249                 if (tso)
5250                         tx_flags |= IXGBE_TX_FLAGS_FSO;
5251 #endif /* IXGBE_FCOE */
5252         } else {
5253                 if (skb->protocol == htons(ETH_P_IP))
5254                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
5255                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5256                 if (tso < 0) {
5257                         dev_kfree_skb_any(skb);
5258                         return NETDEV_TX_OK;
5259                 }
5260
5261                 if (tso)
5262                         tx_flags |= IXGBE_TX_FLAGS_TSO;
5263                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
5264                          (skb->ip_summed == CHECKSUM_PARTIAL))
5265                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
5266         }
5267
5268         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
5269         if (count) {
5270                 /* add the ATR filter if ATR is on */
5271                 if (tx_ring->atr_sample_rate) {
5272                         ++tx_ring->atr_count;
5273                         if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
5274                              test_bit(__IXGBE_FDIR_INIT_DONE,
5275                                       &tx_ring->reinit_state)) {
5276                                 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5277                                           tx_flags);
5278                                 tx_ring->atr_count = 0;
5279                         }
5280                 }
5281                 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
5282                                hdr_len);
5283                 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
5284
5285         } else {
5286                 dev_kfree_skb_any(skb);
5287                 tx_ring->tx_buffer_info[first].time_stamp = 0;
5288                 tx_ring->next_to_use = first;
5289         }
5290
5291         return NETDEV_TX_OK;
5292 }
5293
5294 /**
5295  * ixgbe_get_stats - Get System Network Statistics
5296  * @netdev: network interface device structure
5297  *
5298  * Returns the address of the device statistics structure.
5299  * The statistics are actually updated from the timer callback.
5300  **/
5301 static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
5302 {
5303         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5304
5305         /* only return the current stats */
5306         return &adapter->net_stats;
5307 }
5308
5309 /**
5310  * ixgbe_set_mac - Change the Ethernet Address of the NIC
5311  * @netdev: network interface device structure
5312  * @p: pointer to an address structure
5313  *
5314  * Returns 0 on success, negative on failure
5315  **/
5316 static int ixgbe_set_mac(struct net_device *netdev, void *p)
5317 {
5318         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5319         struct ixgbe_hw *hw = &adapter->hw;
5320         struct sockaddr *addr = p;
5321
5322         if (!is_valid_ether_addr(addr->sa_data))
5323                 return -EADDRNOTAVAIL;
5324
5325         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
5326         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
5327
5328         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
5329
5330         return 0;
5331 }
5332
5333 static int
5334 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
5335 {
5336         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5337         struct ixgbe_hw *hw = &adapter->hw;
5338         u16 value;
5339         int rc;
5340
5341         if (prtad != hw->phy.mdio.prtad)
5342                 return -EINVAL;
5343         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
5344         if (!rc)
5345                 rc = value;
5346         return rc;
5347 }
5348
5349 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
5350                             u16 addr, u16 value)
5351 {
5352         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5353         struct ixgbe_hw *hw = &adapter->hw;
5354
5355         if (prtad != hw->phy.mdio.prtad)
5356                 return -EINVAL;
5357         return hw->phy.ops.write_reg(hw, addr, devad, value);
5358 }
5359
5360 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
5361 {
5362         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5363
5364         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
5365 }
5366
5367 /**
5368  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
5369  * netdev->dev_addrs
5370  * @netdev: network interface device structure
5371  *
5372  * Returns non-zero on failure
5373  **/
5374 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
5375 {
5376         int err = 0;
5377         struct ixgbe_adapter *adapter = netdev_priv(dev);
5378         struct ixgbe_mac_info *mac = &adapter->hw.mac;
5379
5380         if (is_valid_ether_addr(mac->san_addr)) {
5381                 rtnl_lock();
5382                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5383                 rtnl_unlock();
5384         }
5385         return err;
5386 }
5387
5388 /**
5389  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
5390  * netdev->dev_addrs
5391  * @netdev: network interface device structure
5392  *
5393  * Returns non-zero on failure
5394  **/
5395 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
5396 {
5397         int err = 0;
5398         struct ixgbe_adapter *adapter = netdev_priv(dev);
5399         struct ixgbe_mac_info *mac = &adapter->hw.mac;
5400
5401         if (is_valid_ether_addr(mac->san_addr)) {
5402                 rtnl_lock();
5403                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5404                 rtnl_unlock();
5405         }
5406         return err;
5407 }
5408
5409 #ifdef CONFIG_NET_POLL_CONTROLLER
5410 /*
5411  * Polling 'interrupt' - used by things like netconsole to send skbs
5412  * without having to re-enable interrupts. It's not called while
5413  * the interrupt routine is executing.
5414  */
5415 static void ixgbe_netpoll(struct net_device *netdev)
5416 {
5417         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5418         int i;
5419
5420         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
5421         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5422                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5423                 for (i = 0; i < num_q_vectors; i++) {
5424                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
5425                         ixgbe_msix_clean_many(0, q_vector);
5426                 }
5427         } else {
5428                 ixgbe_intr(adapter->pdev->irq, netdev);
5429         }
5430         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
5431 }
5432 #endif
5433
5434 static const struct net_device_ops ixgbe_netdev_ops = {
5435         .ndo_open               = ixgbe_open,
5436         .ndo_stop               = ixgbe_close,
5437         .ndo_start_xmit         = ixgbe_xmit_frame,
5438         .ndo_select_queue       = ixgbe_select_queue,
5439         .ndo_get_stats          = ixgbe_get_stats,
5440         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
5441         .ndo_set_multicast_list = ixgbe_set_rx_mode,
5442         .ndo_validate_addr      = eth_validate_addr,
5443         .ndo_set_mac_address    = ixgbe_set_mac,
5444         .ndo_change_mtu         = ixgbe_change_mtu,
5445         .ndo_tx_timeout         = ixgbe_tx_timeout,
5446         .ndo_vlan_rx_register   = ixgbe_vlan_rx_register,
5447         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
5448         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
5449         .ndo_do_ioctl           = ixgbe_ioctl,
5450 #ifdef CONFIG_NET_POLL_CONTROLLER
5451         .ndo_poll_controller    = ixgbe_netpoll,
5452 #endif
5453 #ifdef IXGBE_FCOE
5454         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5455         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
5456         .ndo_fcoe_enable = ixgbe_fcoe_enable,
5457         .ndo_fcoe_disable = ixgbe_fcoe_disable,
5458 #endif /* IXGBE_FCOE */
5459 };
5460
5461 /**
5462  * ixgbe_probe - Device Initialization Routine
5463  * @pdev: PCI device information struct
5464  * @ent: entry in ixgbe_pci_tbl
5465  *
5466  * Returns 0 on success, negative on failure
5467  *
5468  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5469  * The OS initialization, configuring of the adapter private structure,
5470  * and a hardware reset occur.
5471  **/
5472 static int __devinit ixgbe_probe(struct pci_dev *pdev,
5473                                  const struct pci_device_id *ent)
5474 {
5475         struct net_device *netdev;
5476         struct ixgbe_adapter *adapter = NULL;
5477         struct ixgbe_hw *hw;
5478         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
5479         static int cards_found;
5480         int i, err, pci_using_dac;
5481 #ifdef IXGBE_FCOE
5482         u16 device_caps;
5483 #endif
5484         u32 part_num, eec;
5485
5486         err = pci_enable_device_mem(pdev);
5487         if (err)
5488                 return err;
5489
5490         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
5491             !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
5492                 pci_using_dac = 1;
5493         } else {
5494                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
5495                 if (err) {
5496                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5497                         if (err) {
5498                                 dev_err(&pdev->dev, "No usable DMA "
5499                                         "configuration, aborting\n");
5500                                 goto err_dma;
5501                         }
5502                 }
5503                 pci_using_dac = 0;
5504         }
5505
5506         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
5507                                            IORESOURCE_MEM), ixgbe_driver_name);
5508         if (err) {
5509                 dev_err(&pdev->dev,
5510                         "pci_request_selected_regions failed 0x%x\n", err);
5511                 goto err_pci_reg;
5512         }
5513
5514         pci_enable_pcie_error_reporting(pdev);
5515
5516         pci_set_master(pdev);
5517         pci_save_state(pdev);
5518
5519         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
5520         if (!netdev) {
5521                 err = -ENOMEM;
5522                 goto err_alloc_etherdev;
5523         }
5524
5525         SET_NETDEV_DEV(netdev, &pdev->dev);
5526
5527         pci_set_drvdata(pdev, netdev);
5528         adapter = netdev_priv(netdev);
5529
5530         adapter->netdev = netdev;
5531         adapter->pdev = pdev;
5532         hw = &adapter->hw;
5533         hw->back = adapter;
5534         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
5535
5536         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
5537                               pci_resource_len(pdev, 0));
5538         if (!hw->hw_addr) {
5539                 err = -EIO;
5540                 goto err_ioremap;
5541         }
5542
5543         for (i = 1; i <= 5; i++) {
5544                 if (pci_resource_len(pdev, i) == 0)
5545                         continue;
5546         }
5547
5548         netdev->netdev_ops = &ixgbe_netdev_ops;
5549         ixgbe_set_ethtool_ops(netdev);
5550         netdev->watchdog_timeo = 5 * HZ;
5551         strcpy(netdev->name, pci_name(pdev));
5552
5553         adapter->bd_number = cards_found;
5554
5555         /* Setup hw api */
5556         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
5557         hw->mac.type  = ii->mac;
5558
5559         /* EEPROM */
5560         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
5561         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
5562         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
5563         if (!(eec & (1 << 8)))
5564                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
5565
5566         /* PHY */
5567         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
5568         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
5569         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
5570         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
5571         hw->phy.mdio.mmds = 0;
5572         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
5573         hw->phy.mdio.dev = netdev;
5574         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
5575         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
5576
5577         /* set up this timer and work struct before calling get_invariants
5578          * which might start the timer
5579          */
5580         init_timer(&adapter->sfp_timer);
5581         adapter->sfp_timer.function = &ixgbe_sfp_timer;
5582         adapter->sfp_timer.data = (unsigned long) adapter;
5583
5584         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
5585
5586         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
5587         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
5588
5589         /* a new SFP+ module arrival, called from GPI SDP2 context */
5590         INIT_WORK(&adapter->sfp_config_module_task,
5591                   ixgbe_sfp_config_module_task);
5592
5593         ii->get_invariants(hw);
5594
5595         /* setup the private structure */
5596         err = ixgbe_sw_init(adapter);
5597         if (err)
5598                 goto err_sw_init;
5599
5600         /*
5601          * If there is a fan on this device and it has failed log the
5602          * failure.
5603          */
5604         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5605                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5606                 if (esdp & IXGBE_ESDP_SDP1)
5607                         DPRINTK(PROBE, CRIT,
5608                                 "Fan has stopped, replace the adapter\n");
5609         }
5610
5611         /* reset_hw fills in the perm_addr as well */
5612         err = hw->mac.ops.reset_hw(hw);
5613         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
5614             hw->mac.type == ixgbe_mac_82598EB) {
5615                 /*
5616                  * Start a kernel thread to watch for a module to arrive.
5617                  * Only do this for 82598, since 82599 will generate
5618                  * interrupts on module arrival.
5619                  */
5620                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5621                 mod_timer(&adapter->sfp_timer,
5622                           round_jiffies(jiffies + (2 * HZ)));
5623                 err = 0;
5624         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5625                 dev_err(&adapter->pdev->dev, "failed to initialize because "
5626                         "an unsupported SFP+ module type was detected.\n"
5627                         "Reload the driver after installing a supported "
5628                         "module.\n");
5629                 goto err_sw_init;
5630         } else if (err) {
5631                 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
5632                 goto err_sw_init;
5633         }
5634
5635         netdev->features = NETIF_F_SG |
5636                            NETIF_F_IP_CSUM |
5637                            NETIF_F_HW_VLAN_TX |
5638                            NETIF_F_HW_VLAN_RX |
5639                            NETIF_F_HW_VLAN_FILTER;
5640
5641         netdev->features |= NETIF_F_IPV6_CSUM;
5642         netdev->features |= NETIF_F_TSO;
5643         netdev->features |= NETIF_F_TSO6;
5644         netdev->features |= NETIF_F_GRO;
5645
5646         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
5647                 netdev->features |= NETIF_F_SCTP_CSUM;
5648
5649         netdev->vlan_features |= NETIF_F_TSO;
5650         netdev->vlan_features |= NETIF_F_TSO6;
5651         netdev->vlan_features |= NETIF_F_IP_CSUM;
5652         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
5653         netdev->vlan_features |= NETIF_F_SG;
5654
5655         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5656                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
5657
5658 #ifdef CONFIG_IXGBE_DCB
5659         netdev->dcbnl_ops = &dcbnl_ops;
5660 #endif
5661
5662 #ifdef IXGBE_FCOE
5663         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
5664                 if (hw->mac.ops.get_device_caps) {
5665                         hw->mac.ops.get_device_caps(hw, &device_caps);
5666                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
5667                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5668                 }
5669         }
5670 #endif /* IXGBE_FCOE */
5671         if (pci_using_dac)
5672                 netdev->features |= NETIF_F_HIGHDMA;
5673
5674         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
5675                 netdev->features |= NETIF_F_LRO;
5676
5677         /* make sure the EEPROM is good */
5678         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
5679                 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
5680                 err = -EIO;
5681                 goto err_eeprom;
5682         }
5683
5684         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
5685         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
5686
5687         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
5688                 dev_err(&pdev->dev, "invalid MAC address\n");
5689                 err = -EIO;
5690                 goto err_eeprom;
5691         }
5692
5693         init_timer(&adapter->watchdog_timer);
5694         adapter->watchdog_timer.function = &ixgbe_watchdog;
5695         adapter->watchdog_timer.data = (unsigned long)adapter;
5696
5697         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
5698         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
5699
5700         err = ixgbe_init_interrupt_scheme(adapter);
5701         if (err)
5702                 goto err_sw_init;
5703
5704         switch (pdev->device) {
5705         case IXGBE_DEV_ID_82599_KX4:
5706                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
5707                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
5708                 /* Enable ACPI wakeup in GRC */
5709                 IXGBE_WRITE_REG(hw, IXGBE_GRC,
5710                              (IXGBE_READ_REG(hw, IXGBE_GRC) & ~IXGBE_GRC_APME));
5711                 break;
5712         default:
5713                 adapter->wol = 0;
5714                 break;
5715         }
5716         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
5717
5718         /* pick up the PCI bus settings for reporting later */
5719         hw->mac.ops.get_bus_info(hw);
5720
5721         /* print bus type/speed/width info */
5722         dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
5723                 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
5724                  (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
5725                 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
5726                  (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
5727                  (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
5728                  "Unknown"),
5729                 netdev->dev_addr);
5730         ixgbe_read_pba_num_generic(hw, &part_num);
5731         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
5732                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
5733                          hw->mac.type, hw->phy.type, hw->phy.sfp_type,
5734                          (part_num >> 8), (part_num & 0xff));
5735         else
5736                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
5737                          hw->mac.type, hw->phy.type,
5738                          (part_num >> 8), (part_num & 0xff));
5739
5740         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
5741                 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
5742                          "this card is not sufficient for optimal "
5743                          "performance.\n");
5744                 dev_warn(&pdev->dev, "For optimal performance a x8 "
5745                          "PCI-Express slot is required.\n");
5746         }
5747
5748         /* save off EEPROM version number */
5749         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
5750
5751         /* reset the hardware with the new settings */
5752         err = hw->mac.ops.start_hw(hw);
5753
5754         if (err == IXGBE_ERR_EEPROM_VERSION) {
5755                 /* We are running on a pre-production device, log a warning */
5756                 dev_warn(&pdev->dev, "This device is a pre-production "
5757                          "adapter/LOM.  Please be aware there may be issues "
5758                          "associated with your hardware.  If you are "
5759                          "experiencing problems please contact your Intel or "
5760                          "hardware representative who provided you with this "
5761                          "hardware.\n");
5762         }
5763         strcpy(netdev->name, "eth%d");
5764         err = register_netdev(netdev);
5765         if (err)
5766                 goto err_register;
5767
5768         /* carrier off reporting is important to ethtool even BEFORE open */
5769         netif_carrier_off(netdev);
5770
5771         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5772             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5773                 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
5774
5775 #ifdef CONFIG_IXGBE_DCA
5776         if (dca_add_requester(&pdev->dev) == 0) {
5777                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
5778                 ixgbe_setup_dca(adapter);
5779         }
5780 #endif
5781         /* add san mac addr to netdev */
5782         ixgbe_add_sanmac_netdev(netdev);
5783
5784         dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
5785         cards_found++;
5786         return 0;
5787
5788 err_register:
5789         ixgbe_release_hw_control(adapter);
5790         ixgbe_clear_interrupt_scheme(adapter);
5791 err_sw_init:
5792 err_eeprom:
5793         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5794         del_timer_sync(&adapter->sfp_timer);
5795         cancel_work_sync(&adapter->sfp_task);
5796         cancel_work_sync(&adapter->multispeed_fiber_task);
5797         cancel_work_sync(&adapter->sfp_config_module_task);
5798         iounmap(hw->hw_addr);
5799 err_ioremap:
5800         free_netdev(netdev);
5801 err_alloc_etherdev:
5802         pci_release_selected_regions(pdev, pci_select_bars(pdev,
5803                                      IORESOURCE_MEM));
5804 err_pci_reg:
5805 err_dma:
5806         pci_disable_device(pdev);
5807         return err;
5808 }
5809
5810 /**
5811  * ixgbe_remove - Device Removal Routine
5812  * @pdev: PCI device information struct
5813  *
5814  * ixgbe_remove is called by the PCI subsystem to alert the driver
5815  * that it should release a PCI device.  The could be caused by a
5816  * Hot-Plug event, or because the driver is going to be removed from
5817  * memory.
5818  **/
5819 static void __devexit ixgbe_remove(struct pci_dev *pdev)
5820 {
5821         struct net_device *netdev = pci_get_drvdata(pdev);
5822         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5823
5824         set_bit(__IXGBE_DOWN, &adapter->state);
5825         /* clear the module not found bit to make sure the worker won't
5826          * reschedule
5827          */
5828         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5829         del_timer_sync(&adapter->watchdog_timer);
5830
5831         del_timer_sync(&adapter->sfp_timer);
5832         cancel_work_sync(&adapter->watchdog_task);
5833         cancel_work_sync(&adapter->sfp_task);
5834         cancel_work_sync(&adapter->multispeed_fiber_task);
5835         cancel_work_sync(&adapter->sfp_config_module_task);
5836         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5837             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5838                 cancel_work_sync(&adapter->fdir_reinit_task);
5839         flush_scheduled_work();
5840
5841 #ifdef CONFIG_IXGBE_DCA
5842         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
5843                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
5844                 dca_remove_requester(&pdev->dev);
5845                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
5846         }
5847
5848 #endif
5849 #ifdef IXGBE_FCOE
5850         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
5851                 ixgbe_cleanup_fcoe(adapter);
5852
5853 #endif /* IXGBE_FCOE */
5854
5855         /* remove the added san mac */
5856         ixgbe_del_sanmac_netdev(netdev);
5857
5858         if (netdev->reg_state == NETREG_REGISTERED)
5859                 unregister_netdev(netdev);
5860
5861         ixgbe_clear_interrupt_scheme(adapter);
5862
5863         ixgbe_release_hw_control(adapter);
5864
5865         iounmap(adapter->hw.hw_addr);
5866         pci_release_selected_regions(pdev, pci_select_bars(pdev,
5867                                      IORESOURCE_MEM));
5868
5869         DPRINTK(PROBE, INFO, "complete\n");
5870
5871         free_netdev(netdev);
5872
5873         pci_disable_pcie_error_reporting(pdev);
5874
5875         pci_disable_device(pdev);
5876 }
5877
5878 /**
5879  * ixgbe_io_error_detected - called when PCI error is detected
5880  * @pdev: Pointer to PCI device
5881  * @state: The current pci connection state
5882  *
5883  * This function is called after a PCI bus error affecting
5884  * this device has been detected.
5885  */
5886 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
5887                                                 pci_channel_state_t state)
5888 {
5889         struct net_device *netdev = pci_get_drvdata(pdev);
5890         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5891
5892         netif_device_detach(netdev);
5893
5894         if (state == pci_channel_io_perm_failure)
5895                 return PCI_ERS_RESULT_DISCONNECT;
5896
5897         if (netif_running(netdev))
5898                 ixgbe_down(adapter);
5899         pci_disable_device(pdev);
5900
5901         /* Request a slot reset. */
5902         return PCI_ERS_RESULT_NEED_RESET;
5903 }
5904
5905 /**
5906  * ixgbe_io_slot_reset - called after the pci bus has been reset.
5907  * @pdev: Pointer to PCI device
5908  *
5909  * Restart the card from scratch, as if from a cold-boot.
5910  */
5911 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
5912 {
5913         struct net_device *netdev = pci_get_drvdata(pdev);
5914         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5915         pci_ers_result_t result;
5916         int err;
5917
5918         if (pci_enable_device_mem(pdev)) {
5919                 DPRINTK(PROBE, ERR,
5920                         "Cannot re-enable PCI device after reset.\n");
5921                 result = PCI_ERS_RESULT_DISCONNECT;
5922         } else {
5923                 pci_set_master(pdev);
5924                 pci_restore_state(pdev);
5925
5926                 pci_wake_from_d3(pdev, false);
5927
5928                 ixgbe_reset(adapter);
5929                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5930                 result = PCI_ERS_RESULT_RECOVERED;
5931         }
5932
5933         err = pci_cleanup_aer_uncorrect_error_status(pdev);
5934         if (err) {
5935                 dev_err(&pdev->dev,
5936                   "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
5937                 /* non-fatal, continue */
5938         }
5939
5940         return result;
5941 }
5942
5943 /**
5944  * ixgbe_io_resume - called when traffic can start flowing again.
5945  * @pdev: Pointer to PCI device
5946  *
5947  * This callback is called when the error recovery driver tells us that
5948  * its OK to resume normal operation.
5949  */
5950 static void ixgbe_io_resume(struct pci_dev *pdev)
5951 {
5952         struct net_device *netdev = pci_get_drvdata(pdev);
5953         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5954
5955         if (netif_running(netdev)) {
5956                 if (ixgbe_up(adapter)) {
5957                         DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
5958                         return;
5959                 }
5960         }
5961
5962         netif_device_attach(netdev);
5963 }
5964
5965 static struct pci_error_handlers ixgbe_err_handler = {
5966         .error_detected = ixgbe_io_error_detected,
5967         .slot_reset = ixgbe_io_slot_reset,
5968         .resume = ixgbe_io_resume,
5969 };
5970
5971 static struct pci_driver ixgbe_driver = {
5972         .name     = ixgbe_driver_name,
5973         .id_table = ixgbe_pci_tbl,
5974         .probe    = ixgbe_probe,
5975         .remove   = __devexit_p(ixgbe_remove),
5976 #ifdef CONFIG_PM
5977         .suspend  = ixgbe_suspend,
5978         .resume   = ixgbe_resume,
5979 #endif
5980         .shutdown = ixgbe_shutdown,
5981         .err_handler = &ixgbe_err_handler
5982 };
5983
5984 /**
5985  * ixgbe_init_module - Driver Registration Routine
5986  *
5987  * ixgbe_init_module is the first routine called when the driver is
5988  * loaded. All it does is register with the PCI subsystem.
5989  **/
5990 static int __init ixgbe_init_module(void)
5991 {
5992         int ret;
5993         printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
5994                ixgbe_driver_string, ixgbe_driver_version);
5995
5996         printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
5997
5998 #ifdef CONFIG_IXGBE_DCA
5999         dca_register_notify(&dca_notifier);
6000 #endif
6001
6002         ret = pci_register_driver(&ixgbe_driver);
6003         return ret;
6004 }
6005
6006 module_init(ixgbe_init_module);
6007
6008 /**
6009  * ixgbe_exit_module - Driver Exit Cleanup Routine
6010  *
6011  * ixgbe_exit_module is called just before the driver is removed
6012  * from memory.
6013  **/
6014 static void __exit ixgbe_exit_module(void)
6015 {
6016 #ifdef CONFIG_IXGBE_DCA
6017         dca_unregister_notify(&dca_notifier);
6018 #endif
6019         pci_unregister_driver(&ixgbe_driver);
6020 }
6021
6022 #ifdef CONFIG_IXGBE_DCA
6023 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
6024                             void *p)
6025 {
6026         int ret_val;
6027
6028         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
6029                                          __ixgbe_notify_dca);
6030
6031         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
6032 }
6033
6034 #endif /* CONFIG_IXGBE_DCA */
6035 #ifdef DEBUG
6036 /**
6037  * ixgbe_get_hw_dev_name - return device name string
6038  * used by hardware layer to print debugging information
6039  **/
6040 char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
6041 {
6042         struct ixgbe_adapter *adapter = hw->back;
6043         return adapter->netdev->name;
6044 }
6045
6046 #endif
6047 module_exit(ixgbe_exit_module);
6048
6049 /* ixgbe_main.c */