2 * drivers/net/phy/at803x.c
4 * Driver for Atheros 803x PHY
6 * Author: Matus Ujhelyi <ujhelyi.m@gmail.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
14 #include <linux/phy.h>
15 #include <linux/module.h>
16 #include <linux/string.h>
17 #include <linux/netdevice.h>
18 #include <linux/etherdevice.h>
19 #include <linux/of_gpio.h>
20 #include <linux/gpio/consumer.h>
22 #define AT803X_INTR_ENABLE 0x12
23 #define AT803X_INTR_ENABLE_AUTONEG_ERR BIT(15)
24 #define AT803X_INTR_ENABLE_SPEED_CHANGED BIT(14)
25 #define AT803X_INTR_ENABLE_DUPLEX_CHANGED BIT(13)
26 #define AT803X_INTR_ENABLE_PAGE_RECEIVED BIT(12)
27 #define AT803X_INTR_ENABLE_LINK_FAIL BIT(11)
28 #define AT803X_INTR_ENABLE_LINK_SUCCESS BIT(10)
29 #define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE BIT(5)
30 #define AT803X_INTR_ENABLE_POLARITY_CHANGED BIT(1)
31 #define AT803X_INTR_ENABLE_WOL BIT(0)
33 #define AT803X_INTR_STATUS 0x13
35 #define AT803X_SMART_SPEED 0x14
36 #define AT803X_LED_CONTROL 0x18
38 #define AT803X_DEVICE_ADDR 0x03
39 #define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C
40 #define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B
41 #define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A
42 #define AT803X_MMD_ACCESS_CONTROL 0x0D
43 #define AT803X_MMD_ACCESS_CONTROL_DATA 0x0E
44 #define AT803X_FUNC_DATA 0x4003
45 #define AT803X_REG_CHIP_CONFIG 0x1f
46 #define AT803X_BT_BX_REG_SEL 0x8000
48 #define AT803X_DEBUG_ADDR 0x1D
49 #define AT803X_DEBUG_DATA 0x1E
51 #define AT803X_MODE_CFG_MASK 0x0F
52 #define AT803X_MODE_CFG_SGMII 0x01
54 #define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/
55 #define AT803X_PSSR_MR_AN_COMPLETE 0x0200
57 #define AT803X_DEBUG_REG_0 0x00
58 #define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15)
60 #define AT803X_DEBUG_REG_5 0x05
61 #define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8)
63 #define ATH8030_PHY_ID 0x004dd076
64 #define ATH8031_PHY_ID 0x004dd074
65 #define ATH8035_PHY_ID 0x004dd072
67 MODULE_DESCRIPTION("Atheros 803x PHY driver");
68 MODULE_AUTHOR("Matus Ujhelyi");
69 MODULE_LICENSE("GPL");
73 struct gpio_desc *gpiod_reset;
76 struct at803x_context {
85 static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg)
89 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
93 return phy_read(phydev, AT803X_DEBUG_DATA);
96 static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
102 ret = at803x_debug_reg_read(phydev, reg);
110 return phy_write(phydev, AT803X_DEBUG_DATA, val);
113 static inline int at803x_enable_rx_delay(struct phy_device *phydev)
115 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 0,
116 AT803X_DEBUG_RX_CLK_DLY_EN);
119 static inline int at803x_enable_tx_delay(struct phy_device *phydev)
121 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 0,
122 AT803X_DEBUG_TX_CLK_DLY_EN);
125 /* save relevant PHY registers to private copy */
126 static void at803x_context_save(struct phy_device *phydev,
127 struct at803x_context *context)
129 context->bmcr = phy_read(phydev, MII_BMCR);
130 context->advertise = phy_read(phydev, MII_ADVERTISE);
131 context->control1000 = phy_read(phydev, MII_CTRL1000);
132 context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE);
133 context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED);
134 context->led_control = phy_read(phydev, AT803X_LED_CONTROL);
137 /* restore relevant PHY registers from private copy */
138 static void at803x_context_restore(struct phy_device *phydev,
139 const struct at803x_context *context)
141 phy_write(phydev, MII_BMCR, context->bmcr);
142 phy_write(phydev, MII_ADVERTISE, context->advertise);
143 phy_write(phydev, MII_CTRL1000, context->control1000);
144 phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable);
145 phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed);
146 phy_write(phydev, AT803X_LED_CONTROL, context->led_control);
149 static int at803x_set_wol(struct phy_device *phydev,
150 struct ethtool_wolinfo *wol)
152 struct net_device *ndev = phydev->attached_dev;
156 unsigned int i, offsets[] = {
157 AT803X_LOC_MAC_ADDR_32_47_OFFSET,
158 AT803X_LOC_MAC_ADDR_16_31_OFFSET,
159 AT803X_LOC_MAC_ADDR_0_15_OFFSET,
165 if (wol->wolopts & WAKE_MAGIC) {
166 mac = (const u8 *) ndev->dev_addr;
168 if (!is_valid_ether_addr(mac))
171 for (i = 0; i < 3; i++) {
172 phy_write(phydev, AT803X_MMD_ACCESS_CONTROL,
174 phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA,
176 phy_write(phydev, AT803X_MMD_ACCESS_CONTROL,
178 phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA,
179 mac[(i * 2) + 1] | (mac[(i * 2)] << 8));
182 value = phy_read(phydev, AT803X_INTR_ENABLE);
183 value |= AT803X_INTR_ENABLE_WOL;
184 ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
187 value = phy_read(phydev, AT803X_INTR_STATUS);
189 value = phy_read(phydev, AT803X_INTR_ENABLE);
190 value &= (~AT803X_INTR_ENABLE_WOL);
191 ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
194 value = phy_read(phydev, AT803X_INTR_STATUS);
200 static void at803x_get_wol(struct phy_device *phydev,
201 struct ethtool_wolinfo *wol)
205 wol->supported = WAKE_MAGIC;
208 value = phy_read(phydev, AT803X_INTR_ENABLE);
209 if (value & AT803X_INTR_ENABLE_WOL)
210 wol->wolopts |= WAKE_MAGIC;
213 static int at803x_suspend(struct phy_device *phydev)
218 mutex_lock(&phydev->lock);
220 value = phy_read(phydev, AT803X_INTR_ENABLE);
221 wol_enabled = value & AT803X_INTR_ENABLE_WOL;
223 value = phy_read(phydev, MII_BMCR);
226 value |= BMCR_ISOLATE;
230 phy_write(phydev, MII_BMCR, value);
232 mutex_unlock(&phydev->lock);
237 static int at803x_resume(struct phy_device *phydev)
241 mutex_lock(&phydev->lock);
243 value = phy_read(phydev, MII_BMCR);
244 value &= ~(BMCR_PDOWN | BMCR_ISOLATE);
245 phy_write(phydev, MII_BMCR, value);
247 mutex_unlock(&phydev->lock);
252 static int at803x_probe(struct phy_device *phydev)
254 struct device *dev = &phydev->mdio.dev;
255 struct at803x_priv *priv;
256 struct gpio_desc *gpiod_reset;
258 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
262 if (phydev->drv->phy_id != ATH8030_PHY_ID)
263 goto does_not_require_reset_workaround;
265 gpiod_reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
266 if (IS_ERR(gpiod_reset))
267 return PTR_ERR(gpiod_reset);
269 priv->gpiod_reset = gpiod_reset;
271 does_not_require_reset_workaround:
277 static int at803x_config_init(struct phy_device *phydev)
281 ret = genphy_config_init(phydev);
285 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
286 phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
287 ret = at803x_enable_rx_delay(phydev);
292 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
293 phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
294 ret = at803x_enable_tx_delay(phydev);
302 static int at803x_ack_interrupt(struct phy_device *phydev)
306 err = phy_read(phydev, AT803X_INTR_STATUS);
308 return (err < 0) ? err : 0;
311 static int at803x_config_intr(struct phy_device *phydev)
316 value = phy_read(phydev, AT803X_INTR_ENABLE);
318 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
319 value |= AT803X_INTR_ENABLE_AUTONEG_ERR;
320 value |= AT803X_INTR_ENABLE_SPEED_CHANGED;
321 value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED;
322 value |= AT803X_INTR_ENABLE_LINK_FAIL;
323 value |= AT803X_INTR_ENABLE_LINK_SUCCESS;
325 err = phy_write(phydev, AT803X_INTR_ENABLE, value);
328 err = phy_write(phydev, AT803X_INTR_ENABLE, 0);
333 static void at803x_link_change_notify(struct phy_device *phydev)
335 struct at803x_priv *priv = phydev->priv;
338 * Conduct a hardware reset for AT8030 every time a link loss is
339 * signalled. This is necessary to circumvent a hardware bug that
340 * occurs when the cable is unplugged while TX packets are pending
341 * in the FIFO. In such cases, the FIFO enters an error mode it
342 * cannot recover from by software.
344 if (phydev->state == PHY_NOLINK) {
345 if (priv->gpiod_reset && !priv->phy_reset) {
346 struct at803x_context context;
348 at803x_context_save(phydev, &context);
350 gpiod_set_value(priv->gpiod_reset, 1);
352 gpiod_set_value(priv->gpiod_reset, 0);
355 at803x_context_restore(phydev, &context);
357 phydev_dbg(phydev, "%s(): phy was reset\n",
359 priv->phy_reset = true;
362 priv->phy_reset = false;
366 static int at803x_aneg_done(struct phy_device *phydev)
370 int aneg_done = genphy_aneg_done(phydev);
371 if (aneg_done != BMSR_ANEGCOMPLETE)
375 * in SGMII mode, if copper side autoneg is successful,
376 * also check SGMII side autoneg result
378 ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG);
379 if ((ccr & AT803X_MODE_CFG_MASK) != AT803X_MODE_CFG_SGMII)
382 /* switch to SGMII/fiber page */
383 phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr & ~AT803X_BT_BX_REG_SEL);
385 /* check if the SGMII link is OK. */
386 if (!(phy_read(phydev, AT803X_PSSR) & AT803X_PSSR_MR_AN_COMPLETE)) {
387 pr_warn("803x_aneg_done: SGMII link is not ok\n");
390 /* switch back to copper page */
391 phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr | AT803X_BT_BX_REG_SEL);
396 static struct phy_driver at803x_driver[] = {
399 .phy_id = ATH8035_PHY_ID,
400 .name = "Atheros 8035 ethernet",
401 .phy_id_mask = 0xffffffef,
402 .probe = at803x_probe,
403 .config_init = at803x_config_init,
404 .set_wol = at803x_set_wol,
405 .get_wol = at803x_get_wol,
406 .suspend = at803x_suspend,
407 .resume = at803x_resume,
408 .features = PHY_GBIT_FEATURES,
409 .flags = PHY_HAS_INTERRUPT,
410 .config_aneg = genphy_config_aneg,
411 .read_status = genphy_read_status,
412 .ack_interrupt = at803x_ack_interrupt,
413 .config_intr = at803x_config_intr,
416 .phy_id = ATH8030_PHY_ID,
417 .name = "Atheros 8030 ethernet",
418 .phy_id_mask = 0xffffffef,
419 .probe = at803x_probe,
420 .config_init = at803x_config_init,
421 .link_change_notify = at803x_link_change_notify,
422 .set_wol = at803x_set_wol,
423 .get_wol = at803x_get_wol,
424 .suspend = at803x_suspend,
425 .resume = at803x_resume,
426 .features = PHY_BASIC_FEATURES,
427 .flags = PHY_HAS_INTERRUPT,
428 .config_aneg = genphy_config_aneg,
429 .read_status = genphy_read_status,
430 .ack_interrupt = at803x_ack_interrupt,
431 .config_intr = at803x_config_intr,
434 .phy_id = ATH8031_PHY_ID,
435 .name = "Atheros 8031 ethernet",
436 .phy_id_mask = 0xffffffef,
437 .probe = at803x_probe,
438 .config_init = at803x_config_init,
439 .set_wol = at803x_set_wol,
440 .get_wol = at803x_get_wol,
441 .suspend = at803x_suspend,
442 .resume = at803x_resume,
443 .features = PHY_GBIT_FEATURES,
444 .flags = PHY_HAS_INTERRUPT,
445 .config_aneg = genphy_config_aneg,
446 .read_status = genphy_read_status,
447 .aneg_done = at803x_aneg_done,
448 .ack_interrupt = &at803x_ack_interrupt,
449 .config_intr = &at803x_config_intr,
452 module_phy_driver(at803x_driver);
454 static struct mdio_device_id __maybe_unused atheros_tbl[] = {
455 { ATH8030_PHY_ID, 0xffffffef },
456 { ATH8031_PHY_ID, 0xffffffef },
457 { ATH8035_PHY_ID, 0xffffffef },
461 MODULE_DEVICE_TABLE(mdio, atheros_tbl);