drivers/net/phy/micrel.c

   1 /*
   2  * drivers/net/phy/micrel.c
   3  *
   4  * Driver for Micrel PHYs
   5  *
   6  * Author: David J. Choi
   7  *
   8  * Copyright (c) 2010-2013 Micrel, Inc.
   9  * Copyright (c) 2014 Johan Hovold <johan@kernel.org>
  10  *
  11  * This program is free software; you can redistribute  it and/or modify it
  12  * under  the terms of  the GNU General  Public License as published by the
  13  * Free Software Foundation;  either version 2 of the  License, or (at your
  14  * option) any later version.
  15  *
  16  * Support : Micrel Phys:
  17  *              Giga phys: ksz9021, ksz9031
  18  *              100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
  19  *                         ksz8021, ksz8031, ksz8051,
  20  *                         ksz8081, ksz8091,
  21  *                         ksz8061,
  22  *              Switch : ksz8873, ksz886x
  23  */
  24
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/phy.h>
  28 #include <linux/micrel_phy.h>
  29 #include <linux/of.h>
  30 #include <linux/clk.h>
  31
  32 /* Operation Mode Strap Override */
  33 #define MII_KSZPHY_OMSO                         0x16
  34 #define KSZPHY_OMSO_B_CAST_OFF                  BIT(9)
  35 #define KSZPHY_OMSO_NAND_TREE_ON                BIT(5)
  36 #define KSZPHY_OMSO_RMII_OVERRIDE               BIT(1)
  37 #define KSZPHY_OMSO_MII_OVERRIDE                BIT(0)
  38
  39 /* general Interrupt control/status reg in vendor specific block. */
  40 #define MII_KSZPHY_INTCS                        0x1B
  41 #define KSZPHY_INTCS_JABBER                     BIT(15)
  42 #define KSZPHY_INTCS_RECEIVE_ERR                BIT(14)
  43 #define KSZPHY_INTCS_PAGE_RECEIVE               BIT(13)
  44 #define KSZPHY_INTCS_PARELLEL                   BIT(12)
  45 #define KSZPHY_INTCS_LINK_PARTNER_ACK           BIT(11)
  46 #define KSZPHY_INTCS_LINK_DOWN                  BIT(10)
  47 #define KSZPHY_INTCS_REMOTE_FAULT               BIT(9)
  48 #define KSZPHY_INTCS_LINK_UP                    BIT(8)
  49 #define KSZPHY_INTCS_ALL                        (KSZPHY_INTCS_LINK_UP |\
  50                                                 KSZPHY_INTCS_LINK_DOWN)
  51
  52 /* PHY Control 1 */
  53 #define MII_KSZPHY_CTRL_1                       0x1e
  54
  55 /* PHY Control 2 / PHY Control (if no PHY Control 1) */
  56 #define MII_KSZPHY_CTRL_2                       0x1f
  57 #define MII_KSZPHY_CTRL                         MII_KSZPHY_CTRL_2
  58 /* bitmap of PHY register to set interrupt mode */
  59 #define KSZPHY_CTRL_INT_ACTIVE_HIGH             BIT(9)
  60 #define KSZPHY_RMII_REF_CLK_SEL                 BIT(7)
  61
  62 /* Write/read to/from extended registers */
  63 #define MII_KSZPHY_EXTREG                       0x0b
  64 #define KSZPHY_EXTREG_WRITE                     0x8000
  65
  66 #define MII_KSZPHY_EXTREG_WRITE                 0x0c
  67 #define MII_KSZPHY_EXTREG_READ                  0x0d
  68
  69 /* Extended registers */
  70 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW         0x104
  71 #define MII_KSZPHY_RX_DATA_PAD_SKEW             0x105
  72 #define MII_KSZPHY_TX_DATA_PAD_SKEW             0x106
  73
  74 #define PS_TO_REG                               200
  75
  76 struct kszphy_hw_stat {
  77         const char *string;
  78         u8 reg;
  79         u8 bits;
  80 };
  81
  82 static struct kszphy_hw_stat kszphy_hw_stats[] = {
  83         { "phy_receive_errors", 21, 16},
  84         { "phy_idle_errors", 10, 8 },
  85 };
  86
  87 struct kszphy_type {
  88         u32 led_mode_reg;
  89         u16 interrupt_level_mask;
  90         bool has_broadcast_disable;
  91         bool has_nand_tree_disable;
  92         bool has_rmii_ref_clk_sel;
  93 };
  94
  95 struct kszphy_priv {
  96         const struct kszphy_type *type;
  97         int led_mode;
  98         bool rmii_ref_clk_sel;
  99         bool rmii_ref_clk_sel_val;
 100         u64 stats[ARRAY_SIZE(kszphy_hw_stats)];
 101 };
 102
 103 static const struct kszphy_type ksz8021_type = {
 104         .led_mode_reg           = MII_KSZPHY_CTRL_2,
 105         .has_broadcast_disable  = true,
 106         .has_nand_tree_disable  = true,
 107         .has_rmii_ref_clk_sel   = true,
 108 };
 109
 110 static const struct kszphy_type ksz8041_type = {
 111         .led_mode_reg           = MII_KSZPHY_CTRL_1,
 112 };
 113
 114 static const struct kszphy_type ksz8051_type = {
 115         .led_mode_reg           = MII_KSZPHY_CTRL_2,
 116         .has_nand_tree_disable  = true,
 117 };
 118
 119 static const struct kszphy_type ksz8081_type = {
 120         .led_mode_reg           = MII_KSZPHY_CTRL_2,
 121         .has_broadcast_disable  = true,
 122         .has_nand_tree_disable  = true,
 123         .has_rmii_ref_clk_sel   = true,
 124 };
 125
 126 static const struct kszphy_type ks8737_type = {
 127         .interrupt_level_mask   = BIT(14),
 128 };
 129
 130 static const struct kszphy_type ksz9021_type = {
 131         .interrupt_level_mask   = BIT(14),
 132 };
 133
 134 static int kszphy_extended_write(struct phy_device *phydev,
 135                                 u32 regnum, u16 val)
 136 {
 137         phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
 138         return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
 139 }
 140
 141 static int kszphy_extended_read(struct phy_device *phydev,
 142                                 u32 regnum)
 143 {
 144         phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
 145         return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
 146 }
 147
 148 static int kszphy_ack_interrupt(struct phy_device *phydev)
 149 {
 150         /* bit[7..0] int status, which is a read and clear register. */
 151         int rc;
 152
 153         rc = phy_read(phydev, MII_KSZPHY_INTCS);
 154
 155         return (rc < 0) ? rc : 0;
 156 }
 157
 158 static int kszphy_config_intr(struct phy_device *phydev)
 159 {
 160         const struct kszphy_type *type = phydev->drv->driver_data;
 161         int temp;
 162         u16 mask;
 163
 164         if (type && type->interrupt_level_mask)
 165                 mask = type->interrupt_level_mask;
 166         else
 167                 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
 168
 169         /* set the interrupt pin active low */
 170         temp = phy_read(phydev, MII_KSZPHY_CTRL);
 171         if (temp < 0)
 172                 return temp;
 173         temp &= ~mask;
 174         phy_write(phydev, MII_KSZPHY_CTRL, temp);
 175
 176         /* enable / disable interrupts */
 177         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 178                 temp = KSZPHY_INTCS_ALL;
 179         else
 180                 temp = 0;
 181
 182         return phy_write(phydev, MII_KSZPHY_INTCS, temp);
 183 }
 184
 185 static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
 186 {
 187         int ctrl;
 188
 189         ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
 190         if (ctrl < 0)
 191                 return ctrl;
 192
 193         if (val)
 194                 ctrl |= KSZPHY_RMII_REF_CLK_SEL;
 195         else
 196                 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
 197
 198         return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
 199 }
 200
 201 static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
 202 {
 203         int rc, temp, shift;
 204
 205         switch (reg) {
 206         case MII_KSZPHY_CTRL_1:
 207                 shift = 14;
 208                 break;
 209         case MII_KSZPHY_CTRL_2:
 210                 shift = 4;
 211                 break;
 212         default:
 213                 return -EINVAL;
 214         }
 215
 216         temp = phy_read(phydev, reg);
 217         if (temp < 0) {
 218                 rc = temp;
 219                 goto out;
 220         }
 221
 222         temp &= ~(3 << shift);
 223         temp |= val << shift;
 224         rc = phy_write(phydev, reg, temp);
 225 out:
 226         if (rc < 0)
 227                 phydev_err(phydev, "failed to set led mode\n");
 228
 229         return rc;
 230 }
 231
 232 /* Disable PHY address 0 as the broadcast address, so that it can be used as a
 233  * unique (non-broadcast) address on a shared bus.
 234  */
 235 static int kszphy_broadcast_disable(struct phy_device *phydev)
 236 {
 237         int ret;
 238
 239         ret = phy_read(phydev, MII_KSZPHY_OMSO);
 240         if (ret < 0)
 241                 goto out;
 242
 243         ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
 244 out:
 245         if (ret)
 246                 phydev_err(phydev, "failed to disable broadcast address\n");
 247
 248         return ret;
 249 }
 250
 251 static int kszphy_nand_tree_disable(struct phy_device *phydev)
 252 {
 253         int ret;
 254
 255         ret = phy_read(phydev, MII_KSZPHY_OMSO);
 256         if (ret < 0)
 257                 goto out;
 258
 259         if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
 260                 return 0;
 261
 262         ret = phy_write(phydev, MII_KSZPHY_OMSO,
 263                         ret & ~KSZPHY_OMSO_NAND_TREE_ON);
 264 out:
 265         if (ret)
 266                 phydev_err(phydev, "failed to disable NAND tree mode\n");
 267
 268         return ret;
 269 }
 270
 271 static int kszphy_config_init(struct phy_device *phydev)
 272 {
 273         struct kszphy_priv *priv = phydev->priv;
 274         const struct kszphy_type *type;
 275         int ret;
 276
 277         if (!priv)
 278                 return 0;
 279
 280         type = priv->type;
 281
 282         if (type->has_broadcast_disable)
 283                 kszphy_broadcast_disable(phydev);
 284
 285         if (type->has_nand_tree_disable)
 286                 kszphy_nand_tree_disable(phydev);
 287
 288         if (priv->rmii_ref_clk_sel) {
 289                 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
 290                 if (ret) {
 291                         phydev_err(phydev,
 292                                    "failed to set rmii reference clock\n");
 293                         return ret;
 294                 }
 295         }
 296
 297         if (priv->led_mode >= 0)
 298                 kszphy_setup_led(phydev, type->led_mode_reg, priv->led_mode);
 299
 300         if (phy_interrupt_is_valid(phydev)) {
 301                 int ctl = phy_read(phydev, MII_BMCR);
 302
 303                 if (ctl < 0)
 304                         return ctl;
 305
 306                 ret = phy_write(phydev, MII_BMCR, ctl & ~BMCR_ANENABLE);
 307                 if (ret < 0)
 308                         return ret;
 309         }
 310
 311         return 0;
 312 }
 313
 314 static int ksz8041_config_init(struct phy_device *phydev)
 315 {
 316         struct device_node *of_node = phydev->mdio.dev.of_node;
 317
 318         /* Limit supported and advertised modes in fiber mode */
 319         if (of_property_read_bool(of_node, "micrel,fiber-mode")) {
 320                 phydev->dev_flags |= MICREL_PHY_FXEN;
 321                 phydev->supported &= SUPPORTED_FIBRE |
 322                                      SUPPORTED_100baseT_Full |
 323                                      SUPPORTED_100baseT_Half;
 324                 phydev->advertising &= ADVERTISED_FIBRE |
 325                                        ADVERTISED_100baseT_Full |
 326                                        ADVERTISED_100baseT_Half;
 327                 phydev->autoneg = AUTONEG_DISABLE;
 328         }
 329
 330         return kszphy_config_init(phydev);
 331 }
 332
 333 static int ksz8041_config_aneg(struct phy_device *phydev)
 334 {
 335         /* Skip auto-negotiation in fiber mode */
 336         if (phydev->dev_flags & MICREL_PHY_FXEN) {
 337                 phydev->speed = SPEED_100;
 338                 return 0;
 339         }
 340
 341         return genphy_config_aneg(phydev);
 342 }
 343
 344 static int ksz9021_load_values_from_of(struct phy_device *phydev,
 345                                        const struct device_node *of_node,
 346                                        u16 reg,
 347                                        const char *field1, const char *field2,
 348                                        const char *field3, const char *field4)
 349 {
 350         int val1 = -1;
 351         int val2 = -2;
 352         int val3 = -3;
 353         int val4 = -4;
 354         int newval;
 355         int matches = 0;
 356
 357         if (!of_property_read_u32(of_node, field1, &val1))
 358                 matches++;
 359
 360         if (!of_property_read_u32(of_node, field2, &val2))
 361                 matches++;
 362
 363         if (!of_property_read_u32(of_node, field3, &val3))
 364                 matches++;
 365
 366         if (!of_property_read_u32(of_node, field4, &val4))
 367                 matches++;
 368
 369         if (!matches)
 370                 return 0;
 371
 372         if (matches < 4)
 373                 newval = kszphy_extended_read(phydev, reg);
 374         else
 375                 newval = 0;
 376
 377         if (val1 != -1)
 378                 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
 379
 380         if (val2 != -2)
 381                 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
 382
 383         if (val3 != -3)
 384                 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
 385
 386         if (val4 != -4)
 387                 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
 388
 389         return kszphy_extended_write(phydev, reg, newval);
 390 }
 391
 392 static int ksz9021_config_init(struct phy_device *phydev)
 393 {
 394         const struct device *dev = &phydev->mdio.dev;
 395         const struct device_node *of_node = dev->of_node;
 396         const struct device *dev_walker;
 397
 398         /* The Micrel driver has a deprecated option to place phy OF
 399          * properties in the MAC node. Walk up the tree of devices to
 400          * find a device with an OF node.
 401          */
 402         dev_walker = &phydev->mdio.dev;
 403         do {
 404                 of_node = dev_walker->of_node;
 405                 dev_walker = dev_walker->parent;
 406
 407         } while (!of_node && dev_walker);
 408
 409         if (of_node) {
 410                 ksz9021_load_values_from_of(phydev, of_node,
 411                                     MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
 412                                     "txen-skew-ps", "txc-skew-ps",
 413                                     "rxdv-skew-ps", "rxc-skew-ps");
 414                 ksz9021_load_values_from_of(phydev, of_node,
 415                                     MII_KSZPHY_RX_DATA_PAD_SKEW,
 416                                     "rxd0-skew-ps", "rxd1-skew-ps",
 417                                     "rxd2-skew-ps", "rxd3-skew-ps");
 418                 ksz9021_load_values_from_of(phydev, of_node,
 419                                     MII_KSZPHY_TX_DATA_PAD_SKEW,
 420                                     "txd0-skew-ps", "txd1-skew-ps",
 421                                     "txd2-skew-ps", "txd3-skew-ps");
 422         }
 423         return 0;
 424 }
 425
 426 #define MII_KSZ9031RN_MMD_CTRL_REG      0x0d
 427 #define MII_KSZ9031RN_MMD_REGDATA_REG   0x0e
 428 #define OP_DATA                         1
 429 #define KSZ9031_PS_TO_REG               60
 430
 431 /* Extended registers */
 432 /* MMD Address 0x0 */
 433 #define MII_KSZ9031RN_FLP_BURST_TX_LO   3
 434 #define MII_KSZ9031RN_FLP_BURST_TX_HI   4
 435
 436 /* MMD Address 0x2 */
 437 #define MII_KSZ9031RN_CONTROL_PAD_SKEW  4
 438 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW  5
 439 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW  6
 440 #define MII_KSZ9031RN_CLK_PAD_SKEW      8
 441
 442 /* MMD Address 0x1C */
 443 #define MII_KSZ9031RN_EDPD              0x23
 444 #define MII_KSZ9031RN_EDPD_ENABLE       BIT(0)
 445
 446 static int ksz9031_extended_write(struct phy_device *phydev,
 447                                   u8 mode, u32 dev_addr, u32 regnum, u16 val)
 448 {
 449         phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
 450         phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
 451         phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
 452         return phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, val);
 453 }
 454
 455 static int ksz9031_extended_read(struct phy_device *phydev,
 456                                  u8 mode, u32 dev_addr, u32 regnum)
 457 {
 458         phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
 459         phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
 460         phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
 461         return phy_read(phydev, MII_KSZ9031RN_MMD_REGDATA_REG);
 462 }
 463
 464 static int ksz9031_of_load_skew_values(struct phy_device *phydev,
 465                                        const struct device_node *of_node,
 466                                        u16 reg, size_t field_sz,
 467                                        const char *field[], u8 numfields)
 468 {
 469         int val[4] = {-1, -2, -3, -4};
 470         int matches = 0;
 471         u16 mask;
 472         u16 maxval;
 473         u16 newval;
 474         int i;
 475
 476         for (i = 0; i < numfields; i++)
 477                 if (!of_property_read_u32(of_node, field[i], val + i))
 478                         matches++;
 479
 480         if (!matches)
 481                 return 0;
 482
 483         if (matches < numfields)
 484                 newval = ksz9031_extended_read(phydev, OP_DATA, 2, reg);
 485         else
 486                 newval = 0;
 487
 488         maxval = (field_sz == 4) ? 0xf : 0x1f;
 489         for (i = 0; i < numfields; i++)
 490                 if (val[i] != -(i + 1)) {
 491                         mask = 0xffff;
 492                         mask ^= maxval << (field_sz * i);
 493                         newval = (newval & mask) |
 494                                 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
 495                                         << (field_sz * i));
 496                 }
 497
 498         return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval);
 499 }
 500
 501 static int ksz9031_center_flp_timing(struct phy_device *phydev)
 502 {
 503         int result;
 504
 505         /* Center KSZ9031RNX FLP timing at 16ms. */
 506         result = ksz9031_extended_write(phydev, OP_DATA, 0,
 507                                         MII_KSZ9031RN_FLP_BURST_TX_HI, 0x0006);
 508         result = ksz9031_extended_write(phydev, OP_DATA, 0,
 509                                         MII_KSZ9031RN_FLP_BURST_TX_LO, 0x1A80);
 510
 511         if (result)
 512                 return result;
 513
 514         return genphy_restart_aneg(phydev);
 515 }
 516
 517 /* Enable energy-detect power-down mode */
 518 static int ksz9031_enable_edpd(struct phy_device *phydev)
 519 {
 520         int reg;
 521
 522         reg = ksz9031_extended_read(phydev, OP_DATA, 0x1C, MII_KSZ9031RN_EDPD);
 523         if (reg < 0)
 524                 return reg;
 525         return ksz9031_extended_write(phydev, OP_DATA, 0x1C, MII_KSZ9031RN_EDPD,
 526                                       reg | MII_KSZ9031RN_EDPD_ENABLE);
 527 }
 528
 529 static int ksz9031_config_init(struct phy_device *phydev)
 530 {
 531         const struct device *dev = &phydev->mdio.dev;
 532         const struct device_node *of_node = dev->of_node;
 533         static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
 534         static const char *rx_data_skews[4] = {
 535                 "rxd0-skew-ps", "rxd1-skew-ps",
 536                 "rxd2-skew-ps", "rxd3-skew-ps"
 537         };
 538         static const char *tx_data_skews[4] = {
 539                 "txd0-skew-ps", "txd1-skew-ps",
 540                 "txd2-skew-ps", "txd3-skew-ps"
 541         };
 542         static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
 543         const struct device *dev_walker;
 544         int result;
 545
 546         result = ksz9031_enable_edpd(phydev);
 547         if (result < 0)
 548                 return result;
 549
 550         /* The Micrel driver has a deprecated option to place phy OF
 551          * properties in the MAC node. Walk up the tree of devices to
 552          * find a device with an OF node.
 553          */
 554         dev_walker = &phydev->mdio.dev;
 555         do {
 556                 of_node = dev_walker->of_node;
 557                 dev_walker = dev_walker->parent;
 558         } while (!of_node && dev_walker);
 559
 560         if (of_node) {
 561                 ksz9031_of_load_skew_values(phydev, of_node,
 562                                 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
 563                                 clk_skews, 2);
 564
 565                 ksz9031_of_load_skew_values(phydev, of_node,
 566                                 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
 567                                 control_skews, 2);
 568
 569                 ksz9031_of_load_skew_values(phydev, of_node,
 570                                 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
 571                                 rx_data_skews, 4);
 572
 573                 ksz9031_of_load_skew_values(phydev, of_node,
 574                                 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
 575                                 tx_data_skews, 4);
 576         }
 577
 578         return ksz9031_center_flp_timing(phydev);
 579 }
 580
 581 #define KSZ8873MLL_GLOBAL_CONTROL_4     0x06
 582 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX      BIT(6)
 583 #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED       BIT(4)
 584 static int ksz8873mll_read_status(struct phy_device *phydev)
 585 {
 586         int regval;
 587
 588         /* dummy read */
 589         regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
 590
 591         regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
 592
 593         if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
 594                 phydev->duplex = DUPLEX_HALF;
 595         else
 596                 phydev->duplex = DUPLEX_FULL;
 597
 598         if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
 599                 phydev->speed = SPEED_10;
 600         else
 601                 phydev->speed = SPEED_100;
 602
 603         phydev->link = 1;
 604         phydev->pause = phydev->asym_pause = 0;
 605
 606         return 0;
 607 }
 608
 609 static int ksz9031_read_status(struct phy_device *phydev)
 610 {
 611         int err;
 612         int regval;
 613
 614         err = genphy_read_status(phydev);
 615         if (err)
 616                 return err;
 617
 618         /* Make sure the PHY is not broken. Read idle error count,
 619          * and reset the PHY if it is maxed out.
 620          */
 621         regval = phy_read(phydev, MII_STAT1000);
 622         if ((regval & 0xFF) == 0xFF) {
 623                 phy_init_hw(phydev);
 624                 phydev->link = 0;
 625         }
 626
 627         return 0;
 628 }
 629
 630 static int ksz8873mll_config_aneg(struct phy_device *phydev)
 631 {
 632         return 0;
 633 }
 634
 635 /* This routine returns -1 as an indication to the caller that the
 636  * Micrel ksz9021 10/100/1000 PHY does not support standard IEEE
 637  * MMD extended PHY registers.
 638  */
 639 static int
 640 ksz9021_rd_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum,
 641                       int regnum)
 642 {
 643         return -1;
 644 }
 645
 646 /* This routine does nothing since the Micrel ksz9021 does not support
 647  * standard IEEE MMD extended PHY registers.
 648  */
 649 static void
 650 ksz9021_wr_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum,
 651                       int regnum, u32 val)
 652 {
 653 }
 654
 655 static int kszphy_get_sset_count(struct phy_device *phydev)
 656 {
 657         return ARRAY_SIZE(kszphy_hw_stats);
 658 }
 659
 660 static void kszphy_get_strings(struct phy_device *phydev, u8 *data)
 661 {
 662         int i;
 663
 664         for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) {
 665                 memcpy(data + i * ETH_GSTRING_LEN,
 666                        kszphy_hw_stats[i].string, ETH_GSTRING_LEN);
 667         }
 668 }
 669
 670 #ifndef UINT64_MAX
 671 #define UINT64_MAX              (u64)(~((u64)0))
 672 #endif
 673 static u64 kszphy_get_stat(struct phy_device *phydev, int i)
 674 {
 675         struct kszphy_hw_stat stat = kszphy_hw_stats[i];
 676         struct kszphy_priv *priv = phydev->priv;
 677         int val;
 678         u64 ret;
 679
 680         val = phy_read(phydev, stat.reg);
 681         if (val < 0) {
 682                 ret = UINT64_MAX;
 683         } else {
 684                 val = val & ((1 << stat.bits) - 1);
 685                 priv->stats[i] += val;
 686                 ret = priv->stats[i];
 687         }
 688
 689         return ret;
 690 }
 691
 692 static void kszphy_get_stats(struct phy_device *phydev,
 693                              struct ethtool_stats *stats, u64 *data)
 694 {
 695         int i;
 696
 697         for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
 698                 data[i] = kszphy_get_stat(phydev, i);
 699 }
 700
 701 static int kszphy_suspend(struct phy_device *phydev)
 702 {
 703         /* Disable PHY Interrupts */
 704         if (phy_interrupt_is_valid(phydev)) {
 705                 phydev->interrupts = PHY_INTERRUPT_DISABLED;
 706                 if (phydev->drv->config_intr)
 707                         phydev->drv->config_intr(phydev);
 708         }
 709
 710         return genphy_suspend(phydev);
 711 }
 712
 713 static int kszphy_resume(struct phy_device *phydev)
 714 {
 715         genphy_resume(phydev);
 716
 717         /* Enable PHY Interrupts */
 718         if (phy_interrupt_is_valid(phydev)) {
 719                 phydev->interrupts = PHY_INTERRUPT_ENABLED;
 720                 if (phydev->drv->config_intr)
 721                         phydev->drv->config_intr(phydev);
 722         }
 723
 724         return 0;
 725 }
 726
 727 static int kszphy_probe(struct phy_device *phydev)
 728 {
 729         const struct kszphy_type *type = phydev->drv->driver_data;
 730         const struct device_node *np = phydev->mdio.dev.of_node;
 731         struct kszphy_priv *priv;
 732         struct clk *clk;
 733         int ret;
 734
 735         priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
 736         if (!priv)
 737                 return -ENOMEM;
 738
 739         phydev->priv = priv;
 740
 741         priv->type = type;
 742
 743         if (type->led_mode_reg) {
 744                 ret = of_property_read_u32(np, "micrel,led-mode",
 745                                 &priv->led_mode);
 746                 if (ret)
 747                         priv->led_mode = -1;
 748
 749                 if (priv->led_mode > 3) {
 750                         phydev_err(phydev, "invalid led mode: 0x%02x\n",
 751                                    priv->led_mode);
 752                         priv->led_mode = -1;
 753                 }
 754         } else {
 755                 priv->led_mode = -1;
 756         }
 757
 758         clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref");
 759         /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
 760         if (!IS_ERR_OR_NULL(clk)) {
 761                 unsigned long rate = clk_get_rate(clk);
 762                 bool rmii_ref_clk_sel_25_mhz;
 763
 764                 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
 765                 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
 766                                 "micrel,rmii-reference-clock-select-25-mhz");
 767
 768                 if (rate > 24500000 && rate < 25500000) {
 769                         priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
 770                 } else if (rate > 49500000 && rate < 50500000) {
 771                         priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
 772                 } else {
 773                         phydev_err(phydev, "Clock rate out of range: %ld\n",
 774                                    rate);
 775                         return -EINVAL;
 776                 }
 777         }
 778
 779         /* Support legacy board-file configuration */
 780         if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
 781                 priv->rmii_ref_clk_sel = true;
 782                 priv->rmii_ref_clk_sel_val = true;
 783         }
 784
 785         return 0;
 786 }
 787
 788 static struct phy_driver ksphy_driver[] = {
 789 {
 790         .phy_id         = PHY_ID_KS8737,
 791         .phy_id_mask    = MICREL_PHY_ID_MASK,
 792         .name           = "Micrel KS8737",
 793         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
 794         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 795         .driver_data    = &ks8737_type,
 796         .config_init    = kszphy_config_init,
 797         .config_aneg    = genphy_config_aneg,
 798         .read_status    = genphy_read_status,
 799         .ack_interrupt  = kszphy_ack_interrupt,
 800         .config_intr    = kszphy_config_intr,
 801         .get_sset_count = kszphy_get_sset_count,
 802         .get_strings    = kszphy_get_strings,
 803         .get_stats      = kszphy_get_stats,
 804         .suspend        = genphy_suspend,
 805         .resume         = genphy_resume,
 806 }, {
 807         .phy_id         = PHY_ID_KSZ8021,
 808         .phy_id_mask    = 0x00ffffff,
 809         .name           = "Micrel KSZ8021 or KSZ8031",
 810         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
 811                            SUPPORTED_Asym_Pause),
 812         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 813         .driver_data    = &ksz8021_type,
 814         .probe          = kszphy_probe,
 815         .config_init    = kszphy_config_init,
 816         .config_aneg    = genphy_config_aneg,
 817         .read_status    = genphy_read_status,
 818         .ack_interrupt  = kszphy_ack_interrupt,
 819         .config_intr    = kszphy_config_intr,
 820         .get_sset_count = kszphy_get_sset_count,
 821         .get_strings    = kszphy_get_strings,
 822         .get_stats      = kszphy_get_stats,
 823         .suspend        = genphy_suspend,
 824         .resume         = genphy_resume,
 825 }, {
 826         .phy_id         = PHY_ID_KSZ8031,
 827         .phy_id_mask    = 0x00ffffff,
 828         .name           = "Micrel KSZ8031",
 829         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
 830                            SUPPORTED_Asym_Pause),
 831         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 832         .driver_data    = &ksz8021_type,
 833         .probe          = kszphy_probe,
 834         .config_init    = kszphy_config_init,
 835         .config_aneg    = genphy_config_aneg,
 836         .read_status    = genphy_read_status,
 837         .ack_interrupt  = kszphy_ack_interrupt,
 838         .config_intr    = kszphy_config_intr,
 839         .get_sset_count = kszphy_get_sset_count,
 840         .get_strings    = kszphy_get_strings,
 841         .get_stats      = kszphy_get_stats,
 842         .suspend        = genphy_suspend,
 843         .resume         = genphy_resume,
 844 }, {
 845         .phy_id         = PHY_ID_KSZ8041,
 846         .phy_id_mask    = MICREL_PHY_ID_MASK,
 847         .name           = "Micrel KSZ8041",
 848         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause
 849                                 | SUPPORTED_Asym_Pause),
 850         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 851         .driver_data    = &ksz8041_type,
 852         .probe          = kszphy_probe,
 853         .config_init    = ksz8041_config_init,
 854         .config_aneg    = ksz8041_config_aneg,
 855         .read_status    = genphy_read_status,
 856         .ack_interrupt  = kszphy_ack_interrupt,
 857         .config_intr    = kszphy_config_intr,
 858         .get_sset_count = kszphy_get_sset_count,
 859         .get_strings    = kszphy_get_strings,
 860         .get_stats      = kszphy_get_stats,
 861         .suspend        = genphy_suspend,
 862         .resume         = genphy_resume,
 863 }, {
 864         .phy_id         = PHY_ID_KSZ8041RNLI,
 865         .phy_id_mask    = MICREL_PHY_ID_MASK,
 866         .name           = "Micrel KSZ8041RNLI",
 867         .features       = PHY_BASIC_FEATURES |
 868                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 869         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 870         .driver_data    = &ksz8041_type,
 871         .probe          = kszphy_probe,
 872         .config_init    = kszphy_config_init,
 873         .config_aneg    = genphy_config_aneg,
 874         .read_status    = genphy_read_status,
 875         .ack_interrupt  = kszphy_ack_interrupt,
 876         .config_intr    = kszphy_config_intr,
 877         .get_sset_count = kszphy_get_sset_count,
 878         .get_strings    = kszphy_get_strings,
 879         .get_stats      = kszphy_get_stats,
 880         .suspend        = genphy_suspend,
 881         .resume         = genphy_resume,
 882 }, {
 883         .phy_id         = PHY_ID_KSZ8051,
 884         .phy_id_mask    = MICREL_PHY_ID_MASK,
 885         .name           = "Micrel KSZ8051",
 886         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause
 887                                 | SUPPORTED_Asym_Pause),
 888         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 889         .driver_data    = &ksz8051_type,
 890         .probe          = kszphy_probe,
 891         .config_init    = kszphy_config_init,
 892         .config_aneg    = genphy_config_aneg,
 893         .read_status    = genphy_read_status,
 894         .ack_interrupt  = kszphy_ack_interrupt,
 895         .config_intr    = kszphy_config_intr,
 896         .get_sset_count = kszphy_get_sset_count,
 897         .get_strings    = kszphy_get_strings,
 898         .get_stats      = kszphy_get_stats,
 899         .suspend        = genphy_suspend,
 900         .resume         = genphy_resume,
 901 }, {
 902         .phy_id         = PHY_ID_KSZ8001,
 903         .name           = "Micrel KSZ8001 or KS8721",
 904         .phy_id_mask    = 0x00fffffc,
 905         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
 906         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 907         .driver_data    = &ksz8041_type,
 908         .probe          = kszphy_probe,
 909         .config_init    = kszphy_config_init,
 910         .config_aneg    = genphy_config_aneg,
 911         .read_status    = genphy_read_status,
 912         .ack_interrupt  = kszphy_ack_interrupt,
 913         .config_intr    = kszphy_config_intr,
 914         .get_sset_count = kszphy_get_sset_count,
 915         .get_strings    = kszphy_get_strings,
 916         .get_stats      = kszphy_get_stats,
 917         .suspend        = genphy_suspend,
 918         .resume         = genphy_resume,
 919 }, {
 920         .phy_id         = PHY_ID_KSZ8081,
 921         .name           = "Micrel KSZ8081 or KSZ8091",
 922         .phy_id_mask    = MICREL_PHY_ID_MASK,
 923         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
 924         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 925         .driver_data    = &ksz8081_type,
 926         .probe          = kszphy_probe,
 927         .config_init    = kszphy_config_init,
 928         .config_aneg    = genphy_config_aneg,
 929         .read_status    = genphy_read_status,
 930         .ack_interrupt  = kszphy_ack_interrupt,
 931         .config_intr    = kszphy_config_intr,
 932         .get_sset_count = kszphy_get_sset_count,
 933         .get_strings    = kszphy_get_strings,
 934         .get_stats      = kszphy_get_stats,
 935         .suspend        = kszphy_suspend,
 936         .resume         = kszphy_resume,
 937 }, {
 938         .phy_id         = PHY_ID_KSZ8061,
 939         .name           = "Micrel KSZ8061",
 940         .phy_id_mask    = MICREL_PHY_ID_MASK,
 941         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
 942         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 943         .config_init    = kszphy_config_init,
 944         .config_aneg    = genphy_config_aneg,
 945         .read_status    = genphy_read_status,
 946         .ack_interrupt  = kszphy_ack_interrupt,
 947         .config_intr    = kszphy_config_intr,
 948         .get_sset_count = kszphy_get_sset_count,
 949         .get_strings    = kszphy_get_strings,
 950         .get_stats      = kszphy_get_stats,
 951         .suspend        = genphy_suspend,
 952         .resume         = genphy_resume,
 953 }, {
 954         .phy_id         = PHY_ID_KSZ9021,
 955         .phy_id_mask    = 0x000ffffe,
 956         .name           = "Micrel KSZ9021 Gigabit PHY",
 957         .features       = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
 958         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 959         .driver_data    = &ksz9021_type,
 960         .config_init    = ksz9021_config_init,
 961         .config_aneg    = genphy_config_aneg,
 962         .read_status    = genphy_read_status,
 963         .ack_interrupt  = kszphy_ack_interrupt,
 964         .config_intr    = kszphy_config_intr,
 965         .get_sset_count = kszphy_get_sset_count,
 966         .get_strings    = kszphy_get_strings,
 967         .get_stats      = kszphy_get_stats,
 968         .suspend        = genphy_suspend,
 969         .resume         = genphy_resume,
 970         .read_mmd_indirect = ksz9021_rd_mmd_phyreg,
 971         .write_mmd_indirect = ksz9021_wr_mmd_phyreg,
 972 }, {
 973         .phy_id         = PHY_ID_KSZ9031,
 974         .phy_id_mask    = MICREL_PHY_ID_MASK,
 975         .name           = "Micrel KSZ9031 Gigabit PHY",
 976         .features       = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
 977         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 978         .driver_data    = &ksz9021_type,
 979         .config_init    = ksz9031_config_init,
 980         .config_aneg    = genphy_config_aneg,
 981         .read_status    = ksz9031_read_status,
 982         .ack_interrupt  = kszphy_ack_interrupt,
 983         .config_intr    = kszphy_config_intr,
 984         .get_sset_count = kszphy_get_sset_count,
 985         .get_strings    = kszphy_get_strings,
 986         .get_stats      = kszphy_get_stats,
 987         .suspend        = genphy_suspend,
 988         .resume         = kszphy_resume,
 989 }, {
 990         .phy_id         = PHY_ID_KSZ8873MLL,
 991         .phy_id_mask    = MICREL_PHY_ID_MASK,
 992         .name           = "Micrel KSZ8873MLL Switch",
 993         .features       = (SUPPORTED_Pause | SUPPORTED_Asym_Pause),
 994         .flags          = PHY_HAS_MAGICANEG,
 995         .config_init    = kszphy_config_init,
 996         .config_aneg    = ksz8873mll_config_aneg,
 997         .read_status    = ksz8873mll_read_status,
 998         .get_sset_count = kszphy_get_sset_count,
 999         .get_strings    = kszphy_get_strings,
1000         .get_stats      = kszphy_get_stats,
1001         .suspend        = genphy_suspend,
1002         .resume         = genphy_resume,
1003 }, {
1004         .phy_id         = PHY_ID_KSZ886X,
1005         .phy_id_mask    = MICREL_PHY_ID_MASK,
1006         .name           = "Micrel KSZ886X Switch",
1007         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
1008         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
1009         .config_init    = kszphy_config_init,
1010         .config_aneg    = genphy_config_aneg,
1011         .read_status    = genphy_read_status,
1012         .get_sset_count = kszphy_get_sset_count,
1013         .get_strings    = kszphy_get_strings,
1014         .get_stats      = kszphy_get_stats,
1015         .suspend        = genphy_suspend,
1016         .resume         = genphy_resume,
1017 } };
1018
1019 module_phy_driver(ksphy_driver);
1020
1021 MODULE_DESCRIPTION("Micrel PHY driver");
1022 MODULE_AUTHOR("David J. Choi");
1023 MODULE_LICENSE("GPL");
1024
1025 static struct mdio_device_id __maybe_unused micrel_tbl[] = {
1026         { PHY_ID_KSZ9021, 0x000ffffe },
1027         { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK },
1028         { PHY_ID_KSZ8001, 0x00fffffc },
1029         { PHY_ID_KS8737, MICREL_PHY_ID_MASK },
1030         { PHY_ID_KSZ8021, 0x00ffffff },
1031         { PHY_ID_KSZ8031, 0x00ffffff },
1032         { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK },
1033         { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK },
1034         { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK },
1035         { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK },
1036         { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK },
1037         { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK },
1038         { }
1039 };
1040
1041 MODULE_DEVICE_TABLE(mdio, micrel_tbl);