2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
24 /* Maximum number of Copy Engine's supported */
25 #define CE_COUNT_MAX 8
26 #define CE_HTT_H2T_MSG_SRC_NENTRIES 2048
28 /* Descriptor rings must be aligned to this boundary */
29 #define CE_DESC_RING_ALIGN 8
30 #define CE_SENDLIST_ITEMS_MAX 12
31 #define CE_SEND_FLAG_GATHER 0x00010000
34 * Copy Engine support: low-level Target-side Copy Engine API.
35 * This is a hardware access layer used by code that understands
36 * how to use copy engines.
39 struct ath10k_ce_pipe;
42 #define CE_DESC_FLAGS_GATHER (1 << 0)
43 #define CE_DESC_FLAGS_BYTE_SWAP (1 << 1)
44 #define CE_DESC_FLAGS_META_DATA_MASK 0xFFFC
45 #define CE_DESC_FLAGS_META_DATA_LSB 3
50 __le16 flags; /* %CE_DESC_FLAGS_ */
53 struct ath10k_ce_ring {
54 /* Number of entries in this ring; must be power of 2 */
55 unsigned int nentries;
56 unsigned int nentries_mask;
59 * For dest ring, this is the next index to be processed
60 * by software after it was/is received into.
62 * For src ring, this is the last descriptor that was sent
63 * and completion processed by software.
65 * Regardless of src or dest ring, this is an invariant
67 * write index >= read index >= sw_index
69 unsigned int sw_index;
71 unsigned int write_index;
73 * For src ring, this is the next index not yet processed by HW.
74 * This is a cached copy of the real HW index (read index), used
75 * for avoiding reading the HW index register more often than
77 * This extends the invariant:
78 * write index >= read index >= hw_index >= sw_index
80 * For dest ring, this is currently unused.
83 unsigned int hw_index;
85 /* Start of DMA-coherent area reserved for descriptors */
86 /* Host address space */
87 void *base_addr_owner_space_unaligned;
88 /* CE address space */
89 u32 base_addr_ce_space_unaligned;
92 * Actual start of descriptors.
93 * Aligned to descriptor-size boundary.
94 * Points into reserved DMA-coherent area, above.
96 /* Host address space */
97 void *base_addr_owner_space;
99 /* CE address space */
100 u32 base_addr_ce_space;
102 * Start of shadow copy of descriptors, within regular memory.
103 * Aligned to descriptor-size boundary.
105 void *shadow_base_unaligned;
106 struct ce_desc *shadow_base;
108 void **per_transfer_context;
111 struct ath10k_ce_pipe {
115 unsigned int attr_flags;
119 void (*send_cb) (struct ath10k_ce_pipe *ce_state,
120 void *per_transfer_send_context,
123 unsigned int transfer_id);
124 void (*recv_cb) (struct ath10k_ce_pipe *ce_state,
125 void *per_transfer_recv_context,
128 unsigned int transfer_id,
131 unsigned int src_sz_max;
132 struct ath10k_ce_ring *src_ring;
133 struct ath10k_ce_ring *dest_ring;
136 struct ce_sendlist_item {
137 /* e.g. buffer or desc list */
142 /* Rx descriptor list */
145 /* externally-specified flags; OR-ed with internal flags */
150 unsigned int num_items;
151 struct ce_sendlist_item item[CE_SENDLIST_ITEMS_MAX];
154 /* Copy Engine settable attributes */
157 /*==================Send====================*/
159 /* ath10k_ce_send flags */
160 #define CE_SEND_FLAG_BYTE_SWAP 1
163 * Queue a source buffer to be sent to an anonymous destination buffer.
164 * ce - which copy engine to use
165 * buffer - address of buffer
166 * nbytes - number of bytes to send
167 * transfer_id - arbitrary ID; reflected to destination
168 * flags - CE_SEND_FLAG_* values
169 * Returns 0 on success; otherwise an error status.
171 * Note: If no flags are specified, use CE's default data swap mode.
173 * Implementation note: pushes 1 buffer to Source ring
175 int ath10k_ce_send(struct ath10k_ce_pipe *ce_state,
176 void *per_transfer_send_context,
180 unsigned int transfer_id,
183 void ath10k_ce_send_cb_register(struct ath10k_ce_pipe *ce_state,
184 void (*send_cb)(struct ath10k_ce_pipe *ce_state,
185 void *transfer_context,
188 unsigned int transfer_id),
189 int disable_interrupts);
191 /* Append a simple buffer (address/length) to a sendlist. */
192 void ath10k_ce_sendlist_buf_add(struct ce_sendlist *sendlist,
195 /* OR-ed with internal flags */
199 * Queue a "sendlist" of buffers to be sent using gather to a single
200 * anonymous destination buffer
201 * ce - which copy engine to use
202 * sendlist - list of simple buffers to send using gather
203 * transfer_id - arbitrary ID; reflected to destination
204 * Returns 0 on success; otherwise an error status.
206 * Implemenation note: Pushes multiple buffers with Gather to Source ring.
208 int ath10k_ce_sendlist_send(struct ath10k_ce_pipe *ce_state,
209 void *per_transfer_send_context,
210 struct ce_sendlist *sendlist,
212 unsigned int transfer_id);
214 /*==================Recv=======================*/
217 * Make a buffer available to receive. The buffer must be at least of a
218 * minimal size appropriate for this copy engine (src_sz_max attribute).
219 * ce - which copy engine to use
220 * per_transfer_recv_context - context passed back to caller's recv_cb
221 * buffer - address of buffer in CE space
222 * Returns 0 on success; otherwise an error status.
224 * Implemenation note: Pushes a buffer to Dest ring.
226 int ath10k_ce_recv_buf_enqueue(struct ath10k_ce_pipe *ce_state,
227 void *per_transfer_recv_context,
230 void ath10k_ce_recv_cb_register(struct ath10k_ce_pipe *ce_state,
231 void (*recv_cb)(struct ath10k_ce_pipe *ce_state,
232 void *transfer_context,
235 unsigned int transfer_id,
236 unsigned int flags));
239 /* Data is byte-swapped */
240 #define CE_RECV_FLAG_SWAPPED 1
243 * Supply data for the next completed unprocessed receive descriptor.
244 * Pops buffer from Dest ring.
246 int ath10k_ce_completed_recv_next(struct ath10k_ce_pipe *ce_state,
247 void **per_transfer_contextp,
249 unsigned int *nbytesp,
250 unsigned int *transfer_idp,
251 unsigned int *flagsp);
253 * Supply data for the next completed unprocessed send descriptor.
254 * Pops 1 completed send buffer from Source ring.
256 int ath10k_ce_completed_send_next(struct ath10k_ce_pipe *ce_state,
257 void **per_transfer_contextp,
259 unsigned int *nbytesp,
260 unsigned int *transfer_idp);
262 /*==================CE Engine Initialization=======================*/
264 /* Initialize an instance of a CE */
265 struct ath10k_ce_pipe *ath10k_ce_init(struct ath10k *ar,
267 const struct ce_attr *attr);
269 /*==================CE Engine Shutdown=======================*/
271 * Support clean shutdown by allowing the caller to revoke
272 * receive buffers. Target DMA must be stopped before using
275 int ath10k_ce_revoke_recv_next(struct ath10k_ce_pipe *ce_state,
276 void **per_transfer_contextp,
280 * Support clean shutdown by allowing the caller to cancel
281 * pending sends. Target DMA must be stopped before using
284 int ath10k_ce_cancel_send_next(struct ath10k_ce_pipe *ce_state,
285 void **per_transfer_contextp,
287 unsigned int *nbytesp,
288 unsigned int *transfer_idp);
290 void ath10k_ce_deinit(struct ath10k_ce_pipe *ce_state);
292 /*==================CE Interrupt Handlers====================*/
293 void ath10k_ce_per_engine_service_any(struct ath10k *ar);
294 void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id);
295 void ath10k_ce_disable_interrupts(struct ath10k *ar);
297 /* ce_attr.flags values */
298 /* Use NonSnooping PCIe accesses? */
299 #define CE_ATTR_NO_SNOOP 1
301 /* Byte swap data words */
302 #define CE_ATTR_BYTE_SWAP_DATA 2
304 /* Swizzle descriptors? */
305 #define CE_ATTR_SWIZZLE_DESCRIPTORS 4
307 /* no interrupt on copy completion */
308 #define CE_ATTR_DIS_INTR 8
310 /* Attributes of an instance of a Copy Engine */
312 /* CE_ATTR_* values */
315 /* #entries in source ring - Must be a power of 2 */
316 unsigned int src_nentries;
319 * Max source send size for this CE.
320 * This is also the minimum size of a destination buffer.
322 unsigned int src_sz_max;
324 /* #entries in destination ring - Must be a power of 2 */
325 unsigned int dest_nentries;
329 * When using sendlist_send to transfer multiple buffer fragments, the
330 * transfer context of each fragment, except last one, will be filled
331 * with CE_SENDLIST_ITEM_CTXT. ce_completed_send will return success for
332 * each fragment done with send and the transfer context would be
333 * CE_SENDLIST_ITEM_CTXT. Upper layer could use this to identify the
334 * status of a send completion.
336 #define CE_SENDLIST_ITEM_CTXT ((void *)0xcecebeef)
338 #define SR_BA_ADDRESS 0x0000
339 #define SR_SIZE_ADDRESS 0x0004
340 #define DR_BA_ADDRESS 0x0008
341 #define DR_SIZE_ADDRESS 0x000c
342 #define CE_CMD_ADDRESS 0x0018
344 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MSB 17
345 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB 17
346 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK 0x00020000
347 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(x) \
348 (((0 | (x)) << CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB) & \
349 CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK)
351 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MSB 16
352 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB 16
353 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK 0x00010000
354 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_GET(x) \
355 (((x) & CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) >> \
356 CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB)
357 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(x) \
358 (((0 | (x)) << CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB) & \
359 CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK)
361 #define CE_CTRL1_DMAX_LENGTH_MSB 15
362 #define CE_CTRL1_DMAX_LENGTH_LSB 0
363 #define CE_CTRL1_DMAX_LENGTH_MASK 0x0000ffff
364 #define CE_CTRL1_DMAX_LENGTH_GET(x) \
365 (((x) & CE_CTRL1_DMAX_LENGTH_MASK) >> CE_CTRL1_DMAX_LENGTH_LSB)
366 #define CE_CTRL1_DMAX_LENGTH_SET(x) \
367 (((0 | (x)) << CE_CTRL1_DMAX_LENGTH_LSB) & CE_CTRL1_DMAX_LENGTH_MASK)
369 #define CE_CTRL1_ADDRESS 0x0010
370 #define CE_CTRL1_HW_MASK 0x0007ffff
371 #define CE_CTRL1_SW_MASK 0x0007ffff
372 #define CE_CTRL1_HW_WRITE_MASK 0x00000000
373 #define CE_CTRL1_SW_WRITE_MASK 0x0007ffff
374 #define CE_CTRL1_RSTMASK 0xffffffff
375 #define CE_CTRL1_RESET 0x00000080
377 #define CE_CMD_HALT_STATUS_MSB 3
378 #define CE_CMD_HALT_STATUS_LSB 3
379 #define CE_CMD_HALT_STATUS_MASK 0x00000008
380 #define CE_CMD_HALT_STATUS_GET(x) \
381 (((x) & CE_CMD_HALT_STATUS_MASK) >> CE_CMD_HALT_STATUS_LSB)
382 #define CE_CMD_HALT_STATUS_SET(x) \
383 (((0 | (x)) << CE_CMD_HALT_STATUS_LSB) & CE_CMD_HALT_STATUS_MASK)
384 #define CE_CMD_HALT_STATUS_RESET 0
385 #define CE_CMD_HALT_MSB 0
386 #define CE_CMD_HALT_MASK 0x00000001
388 #define HOST_IE_COPY_COMPLETE_MSB 0
389 #define HOST_IE_COPY_COMPLETE_LSB 0
390 #define HOST_IE_COPY_COMPLETE_MASK 0x00000001
391 #define HOST_IE_COPY_COMPLETE_GET(x) \
392 (((x) & HOST_IE_COPY_COMPLETE_MASK) >> HOST_IE_COPY_COMPLETE_LSB)
393 #define HOST_IE_COPY_COMPLETE_SET(x) \
394 (((0 | (x)) << HOST_IE_COPY_COMPLETE_LSB) & HOST_IE_COPY_COMPLETE_MASK)
395 #define HOST_IE_COPY_COMPLETE_RESET 0
396 #define HOST_IE_ADDRESS 0x002c
398 #define HOST_IS_DST_RING_LOW_WATERMARK_MASK 0x00000010
399 #define HOST_IS_DST_RING_HIGH_WATERMARK_MASK 0x00000008
400 #define HOST_IS_SRC_RING_LOW_WATERMARK_MASK 0x00000004
401 #define HOST_IS_SRC_RING_HIGH_WATERMARK_MASK 0x00000002
402 #define HOST_IS_COPY_COMPLETE_MASK 0x00000001
403 #define HOST_IS_ADDRESS 0x0030
405 #define MISC_IE_ADDRESS 0x0034
407 #define MISC_IS_AXI_ERR_MASK 0x00000400
409 #define MISC_IS_DST_ADDR_ERR_MASK 0x00000200
410 #define MISC_IS_SRC_LEN_ERR_MASK 0x00000100
411 #define MISC_IS_DST_MAX_LEN_VIO_MASK 0x00000080
412 #define MISC_IS_DST_RING_OVERFLOW_MASK 0x00000040
413 #define MISC_IS_SRC_RING_OVERFLOW_MASK 0x00000020
415 #define MISC_IS_ADDRESS 0x0038
417 #define SR_WR_INDEX_ADDRESS 0x003c
419 #define DST_WR_INDEX_ADDRESS 0x0040
421 #define CURRENT_SRRI_ADDRESS 0x0044
423 #define CURRENT_DRRI_ADDRESS 0x0048
425 #define SRC_WATERMARK_LOW_MSB 31
426 #define SRC_WATERMARK_LOW_LSB 16
427 #define SRC_WATERMARK_LOW_MASK 0xffff0000
428 #define SRC_WATERMARK_LOW_GET(x) \
429 (((x) & SRC_WATERMARK_LOW_MASK) >> SRC_WATERMARK_LOW_LSB)
430 #define SRC_WATERMARK_LOW_SET(x) \
431 (((0 | (x)) << SRC_WATERMARK_LOW_LSB) & SRC_WATERMARK_LOW_MASK)
432 #define SRC_WATERMARK_LOW_RESET 0
433 #define SRC_WATERMARK_HIGH_MSB 15
434 #define SRC_WATERMARK_HIGH_LSB 0
435 #define SRC_WATERMARK_HIGH_MASK 0x0000ffff
436 #define SRC_WATERMARK_HIGH_GET(x) \
437 (((x) & SRC_WATERMARK_HIGH_MASK) >> SRC_WATERMARK_HIGH_LSB)
438 #define SRC_WATERMARK_HIGH_SET(x) \
439 (((0 | (x)) << SRC_WATERMARK_HIGH_LSB) & SRC_WATERMARK_HIGH_MASK)
440 #define SRC_WATERMARK_HIGH_RESET 0
441 #define SRC_WATERMARK_ADDRESS 0x004c
443 #define DST_WATERMARK_LOW_LSB 16
444 #define DST_WATERMARK_LOW_MASK 0xffff0000
445 #define DST_WATERMARK_LOW_SET(x) \
446 (((0 | (x)) << DST_WATERMARK_LOW_LSB) & DST_WATERMARK_LOW_MASK)
447 #define DST_WATERMARK_LOW_RESET 0
448 #define DST_WATERMARK_HIGH_MSB 15
449 #define DST_WATERMARK_HIGH_LSB 0
450 #define DST_WATERMARK_HIGH_MASK 0x0000ffff
451 #define DST_WATERMARK_HIGH_GET(x) \
452 (((x) & DST_WATERMARK_HIGH_MASK) >> DST_WATERMARK_HIGH_LSB)
453 #define DST_WATERMARK_HIGH_SET(x) \
454 (((0 | (x)) << DST_WATERMARK_HIGH_LSB) & DST_WATERMARK_HIGH_MASK)
455 #define DST_WATERMARK_HIGH_RESET 0
456 #define DST_WATERMARK_ADDRESS 0x0050
459 static inline u32 ath10k_ce_base_address(unsigned int ce_id)
461 return CE0_BASE_ADDRESS + (CE1_BASE_ADDRESS - CE0_BASE_ADDRESS) * ce_id;
464 #define CE_WATERMARK_MASK (HOST_IS_SRC_RING_LOW_WATERMARK_MASK | \
465 HOST_IS_SRC_RING_HIGH_WATERMARK_MASK | \
466 HOST_IS_DST_RING_LOW_WATERMARK_MASK | \
467 HOST_IS_DST_RING_HIGH_WATERMARK_MASK)
469 #define CE_ERROR_MASK (MISC_IS_AXI_ERR_MASK | \
470 MISC_IS_DST_ADDR_ERR_MASK | \
471 MISC_IS_SRC_LEN_ERR_MASK | \
472 MISC_IS_DST_MAX_LEN_VIO_MASK | \
473 MISC_IS_DST_RING_OVERFLOW_MASK | \
474 MISC_IS_SRC_RING_OVERFLOW_MASK)
476 #define CE_SRC_RING_TO_DESC(baddr, idx) \
477 (&(((struct ce_desc *)baddr)[idx]))
479 #define CE_DEST_RING_TO_DESC(baddr, idx) \
480 (&(((struct ce_desc *)baddr)[idx]))
482 /* Ring arithmetic (modulus number of entries in ring, which is a pwr of 2). */
483 #define CE_RING_DELTA(nentries_mask, fromidx, toidx) \
484 (((int)(toidx)-(int)(fromidx)) & (nentries_mask))
486 #define CE_RING_IDX_INCR(nentries_mask, idx) (((idx) + 1) & (nentries_mask))
488 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB 8
489 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK 0x0000ff00
490 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET(x) \
491 (((x) & CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK) >> \
492 CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB)
493 #define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS 0x0000
495 #define CE_INTERRUPT_SUMMARY(ar) \
496 CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET( \
497 ath10k_pci_read32((ar), CE_WRAPPER_BASE_ADDRESS + \
498 CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS))