2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
24 /* Maximum number of Copy Engine's supported */
25 #define CE_COUNT_MAX 8
26 #define CE_HTT_H2T_MSG_SRC_NENTRIES 2048
28 /* Descriptor rings must be aligned to this boundary */
29 #define CE_DESC_RING_ALIGN 8
30 #define CE_SENDLIST_ITEMS_MAX 12
31 #define CE_SEND_FLAG_GATHER 0x00010000
34 * Copy Engine support: low-level Target-side Copy Engine API.
35 * This is a hardware access layer used by code that understands
36 * how to use copy engines.
39 struct ath10k_ce_pipe;
42 #define CE_DESC_FLAGS_GATHER (1 << 0)
43 #define CE_DESC_FLAGS_BYTE_SWAP (1 << 1)
44 #define CE_DESC_FLAGS_META_DATA_MASK 0xFFFC
45 #define CE_DESC_FLAGS_META_DATA_LSB 3
50 __le16 flags; /* %CE_DESC_FLAGS_ */
53 struct ath10k_ce_ring {
54 /* Number of entries in this ring; must be power of 2 */
55 unsigned int nentries;
56 unsigned int nentries_mask;
59 * For dest ring, this is the next index to be processed
60 * by software after it was/is received into.
62 * For src ring, this is the last descriptor that was sent
63 * and completion processed by software.
65 * Regardless of src or dest ring, this is an invariant
67 * write index >= read index >= sw_index
69 unsigned int sw_index;
71 unsigned int write_index;
73 * For src ring, this is the next index not yet processed by HW.
74 * This is a cached copy of the real HW index (read index), used
75 * for avoiding reading the HW index register more often than
77 * This extends the invariant:
78 * write index >= read index >= hw_index >= sw_index
80 * For dest ring, this is currently unused.
83 unsigned int hw_index;
85 /* Start of DMA-coherent area reserved for descriptors */
86 /* Host address space */
87 void *base_addr_owner_space_unaligned;
88 /* CE address space */
89 u32 base_addr_ce_space_unaligned;
92 * Actual start of descriptors.
93 * Aligned to descriptor-size boundary.
94 * Points into reserved DMA-coherent area, above.
96 /* Host address space */
97 void *base_addr_owner_space;
99 /* CE address space */
100 u32 base_addr_ce_space;
102 * Start of shadow copy of descriptors, within regular memory.
103 * Aligned to descriptor-size boundary.
105 void *shadow_base_unaligned;
106 struct ce_desc *shadow_base;
108 void **per_transfer_context;
111 struct ath10k_ce_pipe {
115 unsigned int attr_flags;
119 void (*send_cb)(struct ath10k_ce_pipe *);
120 void (*recv_cb)(struct ath10k_ce_pipe *);
122 unsigned int src_sz_max;
123 struct ath10k_ce_ring *src_ring;
124 struct ath10k_ce_ring *dest_ring;
127 struct ce_sendlist_item {
128 /* e.g. buffer or desc list */
133 /* Rx descriptor list */
136 /* externally-specified flags; OR-ed with internal flags */
141 unsigned int num_items;
142 struct ce_sendlist_item item[CE_SENDLIST_ITEMS_MAX];
145 /* Copy Engine settable attributes */
148 /*==================Send====================*/
150 /* ath10k_ce_send flags */
151 #define CE_SEND_FLAG_BYTE_SWAP 1
154 * Queue a source buffer to be sent to an anonymous destination buffer.
155 * ce - which copy engine to use
156 * buffer - address of buffer
157 * nbytes - number of bytes to send
158 * transfer_id - arbitrary ID; reflected to destination
159 * flags - CE_SEND_FLAG_* values
160 * Returns 0 on success; otherwise an error status.
162 * Note: If no flags are specified, use CE's default data swap mode.
164 * Implementation note: pushes 1 buffer to Source ring
166 int ath10k_ce_send(struct ath10k_ce_pipe *ce_state,
167 void *per_transfer_send_context,
171 unsigned int transfer_id,
174 void ath10k_ce_send_cb_register(struct ath10k_ce_pipe *ce_state,
175 void (*send_cb)(struct ath10k_ce_pipe *),
176 int disable_interrupts);
178 /* Append a simple buffer (address/length) to a sendlist. */
179 void ath10k_ce_sendlist_buf_add(struct ce_sendlist *sendlist,
182 /* OR-ed with internal flags */
186 * Queue a "sendlist" of buffers to be sent using gather to a single
187 * anonymous destination buffer
188 * ce - which copy engine to use
189 * sendlist - list of simple buffers to send using gather
190 * transfer_id - arbitrary ID; reflected to destination
191 * Returns 0 on success; otherwise an error status.
193 * Implemenation note: Pushes multiple buffers with Gather to Source ring.
195 int ath10k_ce_sendlist_send(struct ath10k_ce_pipe *ce_state,
196 void *per_transfer_send_context,
197 struct ce_sendlist *sendlist,
199 unsigned int transfer_id);
201 /*==================Recv=======================*/
204 * Make a buffer available to receive. The buffer must be at least of a
205 * minimal size appropriate for this copy engine (src_sz_max attribute).
206 * ce - which copy engine to use
207 * per_transfer_recv_context - context passed back to caller's recv_cb
208 * buffer - address of buffer in CE space
209 * Returns 0 on success; otherwise an error status.
211 * Implemenation note: Pushes a buffer to Dest ring.
213 int ath10k_ce_recv_buf_enqueue(struct ath10k_ce_pipe *ce_state,
214 void *per_transfer_recv_context,
217 void ath10k_ce_recv_cb_register(struct ath10k_ce_pipe *ce_state,
218 void (*recv_cb)(struct ath10k_ce_pipe *));
221 /* Data is byte-swapped */
222 #define CE_RECV_FLAG_SWAPPED 1
225 * Supply data for the next completed unprocessed receive descriptor.
226 * Pops buffer from Dest ring.
228 int ath10k_ce_completed_recv_next(struct ath10k_ce_pipe *ce_state,
229 void **per_transfer_contextp,
231 unsigned int *nbytesp,
232 unsigned int *transfer_idp,
233 unsigned int *flagsp);
235 * Supply data for the next completed unprocessed send descriptor.
236 * Pops 1 completed send buffer from Source ring.
238 int ath10k_ce_completed_send_next(struct ath10k_ce_pipe *ce_state,
239 void **per_transfer_contextp,
241 unsigned int *nbytesp,
242 unsigned int *transfer_idp);
244 /*==================CE Engine Initialization=======================*/
246 /* Initialize an instance of a CE */
247 struct ath10k_ce_pipe *ath10k_ce_init(struct ath10k *ar,
249 const struct ce_attr *attr);
251 /*==================CE Engine Shutdown=======================*/
253 * Support clean shutdown by allowing the caller to revoke
254 * receive buffers. Target DMA must be stopped before using
257 int ath10k_ce_revoke_recv_next(struct ath10k_ce_pipe *ce_state,
258 void **per_transfer_contextp,
262 * Support clean shutdown by allowing the caller to cancel
263 * pending sends. Target DMA must be stopped before using
266 int ath10k_ce_cancel_send_next(struct ath10k_ce_pipe *ce_state,
267 void **per_transfer_contextp,
269 unsigned int *nbytesp,
270 unsigned int *transfer_idp);
272 void ath10k_ce_deinit(struct ath10k_ce_pipe *ce_state);
274 /*==================CE Interrupt Handlers====================*/
275 void ath10k_ce_per_engine_service_any(struct ath10k *ar);
276 void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id);
277 void ath10k_ce_disable_interrupts(struct ath10k *ar);
279 /* ce_attr.flags values */
280 /* Use NonSnooping PCIe accesses? */
281 #define CE_ATTR_NO_SNOOP 1
283 /* Byte swap data words */
284 #define CE_ATTR_BYTE_SWAP_DATA 2
286 /* Swizzle descriptors? */
287 #define CE_ATTR_SWIZZLE_DESCRIPTORS 4
289 /* no interrupt on copy completion */
290 #define CE_ATTR_DIS_INTR 8
292 /* Attributes of an instance of a Copy Engine */
294 /* CE_ATTR_* values */
297 /* #entries in source ring - Must be a power of 2 */
298 unsigned int src_nentries;
301 * Max source send size for this CE.
302 * This is also the minimum size of a destination buffer.
304 unsigned int src_sz_max;
306 /* #entries in destination ring - Must be a power of 2 */
307 unsigned int dest_nentries;
311 * When using sendlist_send to transfer multiple buffer fragments, the
312 * transfer context of each fragment, except last one, will be filled
313 * with CE_SENDLIST_ITEM_CTXT. ce_completed_send will return success for
314 * each fragment done with send and the transfer context would be
315 * CE_SENDLIST_ITEM_CTXT. Upper layer could use this to identify the
316 * status of a send completion.
318 #define CE_SENDLIST_ITEM_CTXT ((void *)0xcecebeef)
320 #define SR_BA_ADDRESS 0x0000
321 #define SR_SIZE_ADDRESS 0x0004
322 #define DR_BA_ADDRESS 0x0008
323 #define DR_SIZE_ADDRESS 0x000c
324 #define CE_CMD_ADDRESS 0x0018
326 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MSB 17
327 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB 17
328 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK 0x00020000
329 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(x) \
330 (((0 | (x)) << CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB) & \
331 CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK)
333 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MSB 16
334 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB 16
335 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK 0x00010000
336 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_GET(x) \
337 (((x) & CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) >> \
338 CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB)
339 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(x) \
340 (((0 | (x)) << CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB) & \
341 CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK)
343 #define CE_CTRL1_DMAX_LENGTH_MSB 15
344 #define CE_CTRL1_DMAX_LENGTH_LSB 0
345 #define CE_CTRL1_DMAX_LENGTH_MASK 0x0000ffff
346 #define CE_CTRL1_DMAX_LENGTH_GET(x) \
347 (((x) & CE_CTRL1_DMAX_LENGTH_MASK) >> CE_CTRL1_DMAX_LENGTH_LSB)
348 #define CE_CTRL1_DMAX_LENGTH_SET(x) \
349 (((0 | (x)) << CE_CTRL1_DMAX_LENGTH_LSB) & CE_CTRL1_DMAX_LENGTH_MASK)
351 #define CE_CTRL1_ADDRESS 0x0010
352 #define CE_CTRL1_HW_MASK 0x0007ffff
353 #define CE_CTRL1_SW_MASK 0x0007ffff
354 #define CE_CTRL1_HW_WRITE_MASK 0x00000000
355 #define CE_CTRL1_SW_WRITE_MASK 0x0007ffff
356 #define CE_CTRL1_RSTMASK 0xffffffff
357 #define CE_CTRL1_RESET 0x00000080
359 #define CE_CMD_HALT_STATUS_MSB 3
360 #define CE_CMD_HALT_STATUS_LSB 3
361 #define CE_CMD_HALT_STATUS_MASK 0x00000008
362 #define CE_CMD_HALT_STATUS_GET(x) \
363 (((x) & CE_CMD_HALT_STATUS_MASK) >> CE_CMD_HALT_STATUS_LSB)
364 #define CE_CMD_HALT_STATUS_SET(x) \
365 (((0 | (x)) << CE_CMD_HALT_STATUS_LSB) & CE_CMD_HALT_STATUS_MASK)
366 #define CE_CMD_HALT_STATUS_RESET 0
367 #define CE_CMD_HALT_MSB 0
368 #define CE_CMD_HALT_MASK 0x00000001
370 #define HOST_IE_COPY_COMPLETE_MSB 0
371 #define HOST_IE_COPY_COMPLETE_LSB 0
372 #define HOST_IE_COPY_COMPLETE_MASK 0x00000001
373 #define HOST_IE_COPY_COMPLETE_GET(x) \
374 (((x) & HOST_IE_COPY_COMPLETE_MASK) >> HOST_IE_COPY_COMPLETE_LSB)
375 #define HOST_IE_COPY_COMPLETE_SET(x) \
376 (((0 | (x)) << HOST_IE_COPY_COMPLETE_LSB) & HOST_IE_COPY_COMPLETE_MASK)
377 #define HOST_IE_COPY_COMPLETE_RESET 0
378 #define HOST_IE_ADDRESS 0x002c
380 #define HOST_IS_DST_RING_LOW_WATERMARK_MASK 0x00000010
381 #define HOST_IS_DST_RING_HIGH_WATERMARK_MASK 0x00000008
382 #define HOST_IS_SRC_RING_LOW_WATERMARK_MASK 0x00000004
383 #define HOST_IS_SRC_RING_HIGH_WATERMARK_MASK 0x00000002
384 #define HOST_IS_COPY_COMPLETE_MASK 0x00000001
385 #define HOST_IS_ADDRESS 0x0030
387 #define MISC_IE_ADDRESS 0x0034
389 #define MISC_IS_AXI_ERR_MASK 0x00000400
391 #define MISC_IS_DST_ADDR_ERR_MASK 0x00000200
392 #define MISC_IS_SRC_LEN_ERR_MASK 0x00000100
393 #define MISC_IS_DST_MAX_LEN_VIO_MASK 0x00000080
394 #define MISC_IS_DST_RING_OVERFLOW_MASK 0x00000040
395 #define MISC_IS_SRC_RING_OVERFLOW_MASK 0x00000020
397 #define MISC_IS_ADDRESS 0x0038
399 #define SR_WR_INDEX_ADDRESS 0x003c
401 #define DST_WR_INDEX_ADDRESS 0x0040
403 #define CURRENT_SRRI_ADDRESS 0x0044
405 #define CURRENT_DRRI_ADDRESS 0x0048
407 #define SRC_WATERMARK_LOW_MSB 31
408 #define SRC_WATERMARK_LOW_LSB 16
409 #define SRC_WATERMARK_LOW_MASK 0xffff0000
410 #define SRC_WATERMARK_LOW_GET(x) \
411 (((x) & SRC_WATERMARK_LOW_MASK) >> SRC_WATERMARK_LOW_LSB)
412 #define SRC_WATERMARK_LOW_SET(x) \
413 (((0 | (x)) << SRC_WATERMARK_LOW_LSB) & SRC_WATERMARK_LOW_MASK)
414 #define SRC_WATERMARK_LOW_RESET 0
415 #define SRC_WATERMARK_HIGH_MSB 15
416 #define SRC_WATERMARK_HIGH_LSB 0
417 #define SRC_WATERMARK_HIGH_MASK 0x0000ffff
418 #define SRC_WATERMARK_HIGH_GET(x) \
419 (((x) & SRC_WATERMARK_HIGH_MASK) >> SRC_WATERMARK_HIGH_LSB)
420 #define SRC_WATERMARK_HIGH_SET(x) \
421 (((0 | (x)) << SRC_WATERMARK_HIGH_LSB) & SRC_WATERMARK_HIGH_MASK)
422 #define SRC_WATERMARK_HIGH_RESET 0
423 #define SRC_WATERMARK_ADDRESS 0x004c
425 #define DST_WATERMARK_LOW_LSB 16
426 #define DST_WATERMARK_LOW_MASK 0xffff0000
427 #define DST_WATERMARK_LOW_SET(x) \
428 (((0 | (x)) << DST_WATERMARK_LOW_LSB) & DST_WATERMARK_LOW_MASK)
429 #define DST_WATERMARK_LOW_RESET 0
430 #define DST_WATERMARK_HIGH_MSB 15
431 #define DST_WATERMARK_HIGH_LSB 0
432 #define DST_WATERMARK_HIGH_MASK 0x0000ffff
433 #define DST_WATERMARK_HIGH_GET(x) \
434 (((x) & DST_WATERMARK_HIGH_MASK) >> DST_WATERMARK_HIGH_LSB)
435 #define DST_WATERMARK_HIGH_SET(x) \
436 (((0 | (x)) << DST_WATERMARK_HIGH_LSB) & DST_WATERMARK_HIGH_MASK)
437 #define DST_WATERMARK_HIGH_RESET 0
438 #define DST_WATERMARK_ADDRESS 0x0050
441 static inline u32 ath10k_ce_base_address(unsigned int ce_id)
443 return CE0_BASE_ADDRESS + (CE1_BASE_ADDRESS - CE0_BASE_ADDRESS) * ce_id;
446 #define CE_WATERMARK_MASK (HOST_IS_SRC_RING_LOW_WATERMARK_MASK | \
447 HOST_IS_SRC_RING_HIGH_WATERMARK_MASK | \
448 HOST_IS_DST_RING_LOW_WATERMARK_MASK | \
449 HOST_IS_DST_RING_HIGH_WATERMARK_MASK)
451 #define CE_ERROR_MASK (MISC_IS_AXI_ERR_MASK | \
452 MISC_IS_DST_ADDR_ERR_MASK | \
453 MISC_IS_SRC_LEN_ERR_MASK | \
454 MISC_IS_DST_MAX_LEN_VIO_MASK | \
455 MISC_IS_DST_RING_OVERFLOW_MASK | \
456 MISC_IS_SRC_RING_OVERFLOW_MASK)
458 #define CE_SRC_RING_TO_DESC(baddr, idx) \
459 (&(((struct ce_desc *)baddr)[idx]))
461 #define CE_DEST_RING_TO_DESC(baddr, idx) \
462 (&(((struct ce_desc *)baddr)[idx]))
464 /* Ring arithmetic (modulus number of entries in ring, which is a pwr of 2). */
465 #define CE_RING_DELTA(nentries_mask, fromidx, toidx) \
466 (((int)(toidx)-(int)(fromidx)) & (nentries_mask))
468 #define CE_RING_IDX_INCR(nentries_mask, idx) (((idx) + 1) & (nentries_mask))
470 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB 8
471 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK 0x0000ff00
472 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET(x) \
473 (((x) & CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK) >> \
474 CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB)
475 #define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS 0x0000
477 #define CE_INTERRUPT_SUMMARY(ar) \
478 CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET( \
479 ath10k_pci_read32((ar), CE_WRAPPER_BASE_ADDRESS + \
480 CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS))