2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
24 /* Maximum number of Copy Engine's supported */
25 #define CE_COUNT_MAX 8
26 #define CE_HTT_H2T_MSG_SRC_NENTRIES 4096
28 /* Descriptor rings must be aligned to this boundary */
29 #define CE_DESC_RING_ALIGN 8
30 #define CE_SEND_FLAG_GATHER 0x00010000
33 * Copy Engine support: low-level Target-side Copy Engine API.
34 * This is a hardware access layer used by code that understands
35 * how to use copy engines.
38 struct ath10k_ce_pipe;
41 #define CE_DESC_FLAGS_GATHER (1 << 0)
42 #define CE_DESC_FLAGS_BYTE_SWAP (1 << 1)
43 #define CE_DESC_FLAGS_META_DATA_MASK 0xFFFC
44 #define CE_DESC_FLAGS_META_DATA_LSB 3
49 __le16 flags; /* %CE_DESC_FLAGS_ */
52 struct ath10k_ce_ring {
53 /* Number of entries in this ring; must be power of 2 */
54 unsigned int nentries;
55 unsigned int nentries_mask;
58 * For dest ring, this is the next index to be processed
59 * by software after it was/is received into.
61 * For src ring, this is the last descriptor that was sent
62 * and completion processed by software.
64 * Regardless of src or dest ring, this is an invariant
66 * write index >= read index >= sw_index
68 unsigned int sw_index;
70 unsigned int write_index;
72 * For src ring, this is the next index not yet processed by HW.
73 * This is a cached copy of the real HW index (read index), used
74 * for avoiding reading the HW index register more often than
76 * This extends the invariant:
77 * write index >= read index >= hw_index >= sw_index
79 * For dest ring, this is currently unused.
82 unsigned int hw_index;
84 /* Start of DMA-coherent area reserved for descriptors */
85 /* Host address space */
86 void *base_addr_owner_space_unaligned;
87 /* CE address space */
88 u32 base_addr_ce_space_unaligned;
91 * Actual start of descriptors.
92 * Aligned to descriptor-size boundary.
93 * Points into reserved DMA-coherent area, above.
95 /* Host address space */
96 void *base_addr_owner_space;
98 /* CE address space */
99 u32 base_addr_ce_space;
101 * Start of shadow copy of descriptors, within regular memory.
102 * Aligned to descriptor-size boundary.
104 void *shadow_base_unaligned;
105 struct ce_desc *shadow_base;
108 void *per_transfer_context[0];
111 struct ath10k_ce_pipe {
115 unsigned int attr_flags;
119 void (*send_cb)(struct ath10k_ce_pipe *);
120 void (*recv_cb)(struct ath10k_ce_pipe *);
122 unsigned int src_sz_max;
123 struct ath10k_ce_ring *src_ring;
124 struct ath10k_ce_ring *dest_ring;
127 /* Copy Engine settable attributes */
130 /*==================Send====================*/
132 /* ath10k_ce_send flags */
133 #define CE_SEND_FLAG_BYTE_SWAP 1
136 * Queue a source buffer to be sent to an anonymous destination buffer.
137 * ce - which copy engine to use
138 * buffer - address of buffer
139 * nbytes - number of bytes to send
140 * transfer_id - arbitrary ID; reflected to destination
141 * flags - CE_SEND_FLAG_* values
142 * Returns 0 on success; otherwise an error status.
144 * Note: If no flags are specified, use CE's default data swap mode.
146 * Implementation note: pushes 1 buffer to Source ring
148 int ath10k_ce_send(struct ath10k_ce_pipe *ce_state,
149 void *per_transfer_send_context,
153 unsigned int transfer_id,
156 int ath10k_ce_send_nolock(struct ath10k_ce_pipe *ce_state,
157 void *per_transfer_context,
160 unsigned int transfer_id,
163 void __ath10k_ce_send_revert(struct ath10k_ce_pipe *pipe);
165 void ath10k_ce_send_cb_register(struct ath10k_ce_pipe *ce_state,
166 void (*send_cb)(struct ath10k_ce_pipe *),
167 int disable_interrupts);
169 int ath10k_ce_num_free_src_entries(struct ath10k_ce_pipe *pipe);
171 /*==================Recv=======================*/
174 * Make a buffer available to receive. The buffer must be at least of a
175 * minimal size appropriate for this copy engine (src_sz_max attribute).
176 * ce - which copy engine to use
177 * per_transfer_recv_context - context passed back to caller's recv_cb
178 * buffer - address of buffer in CE space
179 * Returns 0 on success; otherwise an error status.
181 * Implemenation note: Pushes a buffer to Dest ring.
183 int ath10k_ce_recv_buf_enqueue(struct ath10k_ce_pipe *ce_state,
184 void *per_transfer_recv_context,
187 void ath10k_ce_recv_cb_register(struct ath10k_ce_pipe *ce_state,
188 void (*recv_cb)(struct ath10k_ce_pipe *));
191 /* Data is byte-swapped */
192 #define CE_RECV_FLAG_SWAPPED 1
195 * Supply data for the next completed unprocessed receive descriptor.
196 * Pops buffer from Dest ring.
198 int ath10k_ce_completed_recv_next(struct ath10k_ce_pipe *ce_state,
199 void **per_transfer_contextp,
201 unsigned int *nbytesp,
202 unsigned int *transfer_idp,
203 unsigned int *flagsp);
205 * Supply data for the next completed unprocessed send descriptor.
206 * Pops 1 completed send buffer from Source ring.
208 int ath10k_ce_completed_send_next(struct ath10k_ce_pipe *ce_state,
209 void **per_transfer_contextp,
211 unsigned int *nbytesp,
212 unsigned int *transfer_idp);
214 /*==================CE Engine Initialization=======================*/
216 int ath10k_ce_init_pipe(struct ath10k *ar, unsigned int ce_id,
217 const struct ce_attr *attr);
218 void ath10k_ce_deinit_pipe(struct ath10k *ar, unsigned int ce_id);
219 int ath10k_ce_alloc_pipe(struct ath10k *ar, int ce_id,
220 const struct ce_attr *attr);
221 void ath10k_ce_free_pipe(struct ath10k *ar, int ce_id);
223 /*==================CE Engine Shutdown=======================*/
225 * Support clean shutdown by allowing the caller to revoke
226 * receive buffers. Target DMA must be stopped before using
229 int ath10k_ce_revoke_recv_next(struct ath10k_ce_pipe *ce_state,
230 void **per_transfer_contextp,
234 * Support clean shutdown by allowing the caller to cancel
235 * pending sends. Target DMA must be stopped before using
238 int ath10k_ce_cancel_send_next(struct ath10k_ce_pipe *ce_state,
239 void **per_transfer_contextp,
241 unsigned int *nbytesp,
242 unsigned int *transfer_idp);
244 /*==================CE Interrupt Handlers====================*/
245 void ath10k_ce_per_engine_service_any(struct ath10k *ar);
246 void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id);
247 int ath10k_ce_disable_interrupts(struct ath10k *ar);
249 /* ce_attr.flags values */
250 /* Use NonSnooping PCIe accesses? */
251 #define CE_ATTR_NO_SNOOP 1
253 /* Byte swap data words */
254 #define CE_ATTR_BYTE_SWAP_DATA 2
256 /* Swizzle descriptors? */
257 #define CE_ATTR_SWIZZLE_DESCRIPTORS 4
259 /* no interrupt on copy completion */
260 #define CE_ATTR_DIS_INTR 8
262 /* Attributes of an instance of a Copy Engine */
264 /* CE_ATTR_* values */
267 /* #entries in source ring - Must be a power of 2 */
268 unsigned int src_nentries;
271 * Max source send size for this CE.
272 * This is also the minimum size of a destination buffer.
274 unsigned int src_sz_max;
276 /* #entries in destination ring - Must be a power of 2 */
277 unsigned int dest_nentries;
280 #define SR_BA_ADDRESS 0x0000
281 #define SR_SIZE_ADDRESS 0x0004
282 #define DR_BA_ADDRESS 0x0008
283 #define DR_SIZE_ADDRESS 0x000c
284 #define CE_CMD_ADDRESS 0x0018
286 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MSB 17
287 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB 17
288 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK 0x00020000
289 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(x) \
290 (((0 | (x)) << CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB) & \
291 CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK)
293 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MSB 16
294 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB 16
295 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK 0x00010000
296 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_GET(x) \
297 (((x) & CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) >> \
298 CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB)
299 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(x) \
300 (((0 | (x)) << CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB) & \
301 CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK)
303 #define CE_CTRL1_DMAX_LENGTH_MSB 15
304 #define CE_CTRL1_DMAX_LENGTH_LSB 0
305 #define CE_CTRL1_DMAX_LENGTH_MASK 0x0000ffff
306 #define CE_CTRL1_DMAX_LENGTH_GET(x) \
307 (((x) & CE_CTRL1_DMAX_LENGTH_MASK) >> CE_CTRL1_DMAX_LENGTH_LSB)
308 #define CE_CTRL1_DMAX_LENGTH_SET(x) \
309 (((0 | (x)) << CE_CTRL1_DMAX_LENGTH_LSB) & CE_CTRL1_DMAX_LENGTH_MASK)
311 #define CE_CTRL1_ADDRESS 0x0010
312 #define CE_CTRL1_HW_MASK 0x0007ffff
313 #define CE_CTRL1_SW_MASK 0x0007ffff
314 #define CE_CTRL1_HW_WRITE_MASK 0x00000000
315 #define CE_CTRL1_SW_WRITE_MASK 0x0007ffff
316 #define CE_CTRL1_RSTMASK 0xffffffff
317 #define CE_CTRL1_RESET 0x00000080
319 #define CE_CMD_HALT_STATUS_MSB 3
320 #define CE_CMD_HALT_STATUS_LSB 3
321 #define CE_CMD_HALT_STATUS_MASK 0x00000008
322 #define CE_CMD_HALT_STATUS_GET(x) \
323 (((x) & CE_CMD_HALT_STATUS_MASK) >> CE_CMD_HALT_STATUS_LSB)
324 #define CE_CMD_HALT_STATUS_SET(x) \
325 (((0 | (x)) << CE_CMD_HALT_STATUS_LSB) & CE_CMD_HALT_STATUS_MASK)
326 #define CE_CMD_HALT_STATUS_RESET 0
327 #define CE_CMD_HALT_MSB 0
328 #define CE_CMD_HALT_MASK 0x00000001
330 #define HOST_IE_COPY_COMPLETE_MSB 0
331 #define HOST_IE_COPY_COMPLETE_LSB 0
332 #define HOST_IE_COPY_COMPLETE_MASK 0x00000001
333 #define HOST_IE_COPY_COMPLETE_GET(x) \
334 (((x) & HOST_IE_COPY_COMPLETE_MASK) >> HOST_IE_COPY_COMPLETE_LSB)
335 #define HOST_IE_COPY_COMPLETE_SET(x) \
336 (((0 | (x)) << HOST_IE_COPY_COMPLETE_LSB) & HOST_IE_COPY_COMPLETE_MASK)
337 #define HOST_IE_COPY_COMPLETE_RESET 0
338 #define HOST_IE_ADDRESS 0x002c
340 #define HOST_IS_DST_RING_LOW_WATERMARK_MASK 0x00000010
341 #define HOST_IS_DST_RING_HIGH_WATERMARK_MASK 0x00000008
342 #define HOST_IS_SRC_RING_LOW_WATERMARK_MASK 0x00000004
343 #define HOST_IS_SRC_RING_HIGH_WATERMARK_MASK 0x00000002
344 #define HOST_IS_COPY_COMPLETE_MASK 0x00000001
345 #define HOST_IS_ADDRESS 0x0030
347 #define MISC_IE_ADDRESS 0x0034
349 #define MISC_IS_AXI_ERR_MASK 0x00000400
351 #define MISC_IS_DST_ADDR_ERR_MASK 0x00000200
352 #define MISC_IS_SRC_LEN_ERR_MASK 0x00000100
353 #define MISC_IS_DST_MAX_LEN_VIO_MASK 0x00000080
354 #define MISC_IS_DST_RING_OVERFLOW_MASK 0x00000040
355 #define MISC_IS_SRC_RING_OVERFLOW_MASK 0x00000020
357 #define MISC_IS_ADDRESS 0x0038
359 #define SR_WR_INDEX_ADDRESS 0x003c
361 #define DST_WR_INDEX_ADDRESS 0x0040
363 #define CURRENT_SRRI_ADDRESS 0x0044
365 #define CURRENT_DRRI_ADDRESS 0x0048
367 #define SRC_WATERMARK_LOW_MSB 31
368 #define SRC_WATERMARK_LOW_LSB 16
369 #define SRC_WATERMARK_LOW_MASK 0xffff0000
370 #define SRC_WATERMARK_LOW_GET(x) \
371 (((x) & SRC_WATERMARK_LOW_MASK) >> SRC_WATERMARK_LOW_LSB)
372 #define SRC_WATERMARK_LOW_SET(x) \
373 (((0 | (x)) << SRC_WATERMARK_LOW_LSB) & SRC_WATERMARK_LOW_MASK)
374 #define SRC_WATERMARK_LOW_RESET 0
375 #define SRC_WATERMARK_HIGH_MSB 15
376 #define SRC_WATERMARK_HIGH_LSB 0
377 #define SRC_WATERMARK_HIGH_MASK 0x0000ffff
378 #define SRC_WATERMARK_HIGH_GET(x) \
379 (((x) & SRC_WATERMARK_HIGH_MASK) >> SRC_WATERMARK_HIGH_LSB)
380 #define SRC_WATERMARK_HIGH_SET(x) \
381 (((0 | (x)) << SRC_WATERMARK_HIGH_LSB) & SRC_WATERMARK_HIGH_MASK)
382 #define SRC_WATERMARK_HIGH_RESET 0
383 #define SRC_WATERMARK_ADDRESS 0x004c
385 #define DST_WATERMARK_LOW_LSB 16
386 #define DST_WATERMARK_LOW_MASK 0xffff0000
387 #define DST_WATERMARK_LOW_SET(x) \
388 (((0 | (x)) << DST_WATERMARK_LOW_LSB) & DST_WATERMARK_LOW_MASK)
389 #define DST_WATERMARK_LOW_RESET 0
390 #define DST_WATERMARK_HIGH_MSB 15
391 #define DST_WATERMARK_HIGH_LSB 0
392 #define DST_WATERMARK_HIGH_MASK 0x0000ffff
393 #define DST_WATERMARK_HIGH_GET(x) \
394 (((x) & DST_WATERMARK_HIGH_MASK) >> DST_WATERMARK_HIGH_LSB)
395 #define DST_WATERMARK_HIGH_SET(x) \
396 (((0 | (x)) << DST_WATERMARK_HIGH_LSB) & DST_WATERMARK_HIGH_MASK)
397 #define DST_WATERMARK_HIGH_RESET 0
398 #define DST_WATERMARK_ADDRESS 0x0050
401 static inline u32 ath10k_ce_base_address(unsigned int ce_id)
403 return CE0_BASE_ADDRESS + (CE1_BASE_ADDRESS - CE0_BASE_ADDRESS) * ce_id;
406 #define CE_WATERMARK_MASK (HOST_IS_SRC_RING_LOW_WATERMARK_MASK | \
407 HOST_IS_SRC_RING_HIGH_WATERMARK_MASK | \
408 HOST_IS_DST_RING_LOW_WATERMARK_MASK | \
409 HOST_IS_DST_RING_HIGH_WATERMARK_MASK)
411 #define CE_ERROR_MASK (MISC_IS_AXI_ERR_MASK | \
412 MISC_IS_DST_ADDR_ERR_MASK | \
413 MISC_IS_SRC_LEN_ERR_MASK | \
414 MISC_IS_DST_MAX_LEN_VIO_MASK | \
415 MISC_IS_DST_RING_OVERFLOW_MASK | \
416 MISC_IS_SRC_RING_OVERFLOW_MASK)
418 #define CE_SRC_RING_TO_DESC(baddr, idx) \
419 (&(((struct ce_desc *)baddr)[idx]))
421 #define CE_DEST_RING_TO_DESC(baddr, idx) \
422 (&(((struct ce_desc *)baddr)[idx]))
424 /* Ring arithmetic (modulus number of entries in ring, which is a pwr of 2). */
425 #define CE_RING_DELTA(nentries_mask, fromidx, toidx) \
426 (((int)(toidx)-(int)(fromidx)) & (nentries_mask))
428 #define CE_RING_IDX_INCR(nentries_mask, idx) (((idx) + 1) & (nentries_mask))
430 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB 8
431 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK 0x0000ff00
432 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET(x) \
433 (((x) & CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK) >> \
434 CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB)
435 #define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS 0x0000
437 #define CE_INTERRUPT_SUMMARY(ar) \
438 CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET( \
439 ath10k_pci_read32((ar), CE_WRAPPER_BASE_ADDRESS + \
440 CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS))